Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T540 /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2786352355 Jun 26 06:22:09 PM PDT 24 Jun 26 06:22:17 PM PDT 24 1226699581 ps
T541 /workspace/coverage/default/37.rstmgr_por_stretcher.3363353975 Jun 26 06:22:23 PM PDT 24 Jun 26 06:22:26 PM PDT 24 144648680 ps
T542 /workspace/coverage/default/24.rstmgr_stress_all.276431361 Jun 26 06:22:05 PM PDT 24 Jun 26 06:22:28 PM PDT 24 5704904865 ps
T543 /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.4145154418 Jun 26 06:21:52 PM PDT 24 Jun 26 06:21:53 PM PDT 24 243898431 ps
T544 /workspace/coverage/default/31.rstmgr_sw_rst.1176215927 Jun 26 06:22:15 PM PDT 24 Jun 26 06:22:18 PM PDT 24 155320957 ps
T67 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2441047405 Jun 26 06:21:04 PM PDT 24 Jun 26 06:21:06 PM PDT 24 73698362 ps
T68 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.679669701 Jun 26 06:20:52 PM PDT 24 Jun 26 06:20:55 PM PDT 24 155579069 ps
T71 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1249487448 Jun 26 06:20:38 PM PDT 24 Jun 26 06:20:41 PM PDT 24 228700351 ps
T69 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1644766762 Jun 26 06:20:45 PM PDT 24 Jun 26 06:20:48 PM PDT 24 139356710 ps
T70 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3947913018 Jun 26 06:21:00 PM PDT 24 Jun 26 06:21:03 PM PDT 24 491901648 ps
T128 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3709114379 Jun 26 06:20:40 PM PDT 24 Jun 26 06:20:42 PM PDT 24 72191858 ps
T72 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2110482592 Jun 26 06:20:51 PM PDT 24 Jun 26 06:20:55 PM PDT 24 505201380 ps
T73 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.497838489 Jun 26 06:20:44 PM PDT 24 Jun 26 06:20:50 PM PDT 24 509485847 ps
T79 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1333129494 Jun 26 06:21:00 PM PDT 24 Jun 26 06:21:03 PM PDT 24 465738934 ps
T127 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2088006566 Jun 26 06:20:42 PM PDT 24 Jun 26 06:20:46 PM PDT 24 463239394 ps
T95 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.13825531 Jun 26 06:21:14 PM PDT 24 Jun 26 06:21:18 PM PDT 24 768704011 ps
T88 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1225499657 Jun 26 06:20:49 PM PDT 24 Jun 26 06:20:53 PM PDT 24 825711798 ps
T108 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2835033918 Jun 26 06:20:50 PM PDT 24 Jun 26 06:20:53 PM PDT 24 220119262 ps
T109 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4110034716 Jun 26 06:20:50 PM PDT 24 Jun 26 06:20:53 PM PDT 24 132539145 ps
T89 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2240283980 Jun 26 06:20:36 PM PDT 24 Jun 26 06:20:38 PM PDT 24 490367606 ps
T74 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4056866482 Jun 26 06:20:50 PM PDT 24 Jun 26 06:20:55 PM PDT 24 610119732 ps
T90 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1021473682 Jun 26 06:20:58 PM PDT 24 Jun 26 06:21:01 PM PDT 24 311447351 ps
T91 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3408728188 Jun 26 06:21:04 PM PDT 24 Jun 26 06:21:06 PM PDT 24 197862968 ps
T545 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2288351868 Jun 26 06:20:56 PM PDT 24 Jun 26 06:20:58 PM PDT 24 67662346 ps
T92 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3002214157 Jun 26 06:20:55 PM PDT 24 Jun 26 06:21:00 PM PDT 24 968743243 ps
T110 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.968616862 Jun 26 06:20:43 PM PDT 24 Jun 26 06:20:46 PM PDT 24 153323518 ps
T111 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4079084702 Jun 26 06:20:56 PM PDT 24 Jun 26 06:20:59 PM PDT 24 98072237 ps
T93 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1001067972 Jun 26 06:20:55 PM PDT 24 Jun 26 06:20:59 PM PDT 24 460112773 ps
T546 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1259740103 Jun 26 06:21:05 PM PDT 24 Jun 26 06:21:07 PM PDT 24 67981041 ps
T94 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1758422068 Jun 26 06:20:47 PM PDT 24 Jun 26 06:20:49 PM PDT 24 98986319 ps
T547 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1785493799 Jun 26 06:20:56 PM PDT 24 Jun 26 06:20:58 PM PDT 24 88940654 ps
T112 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2081138428 Jun 26 06:21:15 PM PDT 24 Jun 26 06:21:16 PM PDT 24 66573686 ps
T113 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2138849623 Jun 26 06:20:50 PM PDT 24 Jun 26 06:20:53 PM PDT 24 82369352 ps
T96 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3092192613 Jun 26 06:20:36 PM PDT 24 Jun 26 06:20:41 PM PDT 24 594122588 ps
T97 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.871537616 Jun 26 06:20:39 PM PDT 24 Jun 26 06:20:42 PM PDT 24 155279490 ps
T548 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4063030224 Jun 26 06:20:50 PM PDT 24 Jun 26 06:20:54 PM PDT 24 786328700 ps
T119 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2722750736 Jun 26 06:20:46 PM PDT 24 Jun 26 06:20:50 PM PDT 24 422829673 ps
T114 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1221907239 Jun 26 06:20:37 PM PDT 24 Jun 26 06:20:40 PM PDT 24 212327009 ps
T115 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.509076337 Jun 26 06:20:47 PM PDT 24 Jun 26 06:20:49 PM PDT 24 63777902 ps
T123 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.849964276 Jun 26 06:20:45 PM PDT 24 Jun 26 06:20:48 PM PDT 24 430944399 ps
T549 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.22538367 Jun 26 06:20:44 PM PDT 24 Jun 26 06:20:47 PM PDT 24 141902443 ps
T550 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1359273654 Jun 26 06:20:43 PM PDT 24 Jun 26 06:20:46 PM PDT 24 506530916 ps
T551 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2457018826 Jun 26 06:20:38 PM PDT 24 Jun 26 06:20:40 PM PDT 24 75537535 ps
T120 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.967661146 Jun 26 06:21:02 PM PDT 24 Jun 26 06:21:06 PM PDT 24 935573984 ps
T552 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1053357187 Jun 26 06:21:03 PM PDT 24 Jun 26 06:21:05 PM PDT 24 65445362 ps
T553 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1286423436 Jun 26 06:20:55 PM PDT 24 Jun 26 06:20:58 PM PDT 24 178244556 ps
T554 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.381718395 Jun 26 06:20:40 PM PDT 24 Jun 26 06:20:41 PM PDT 24 91943364 ps
T555 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.362976910 Jun 26 06:20:56 PM PDT 24 Jun 26 06:20:58 PM PDT 24 85833011 ps
T556 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1490042785 Jun 26 06:21:02 PM PDT 24 Jun 26 06:21:06 PM PDT 24 192492789 ps
T557 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3154070072 Jun 26 06:20:51 PM PDT 24 Jun 26 06:20:54 PM PDT 24 206817359 ps
T558 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1159680521 Jun 26 06:20:43 PM PDT 24 Jun 26 06:20:45 PM PDT 24 59157120 ps
T559 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.154942192 Jun 26 06:21:04 PM PDT 24 Jun 26 06:21:07 PM PDT 24 312956552 ps
T560 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.66526972 Jun 26 06:20:38 PM PDT 24 Jun 26 06:20:41 PM PDT 24 203708599 ps
T561 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3661205916 Jun 26 06:20:43 PM PDT 24 Jun 26 06:20:46 PM PDT 24 113981715 ps
T562 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.153960298 Jun 26 06:20:58 PM PDT 24 Jun 26 06:21:00 PM PDT 24 90788723 ps
T563 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3379061934 Jun 26 06:21:06 PM PDT 24 Jun 26 06:21:08 PM PDT 24 124491733 ps
T564 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2623753935 Jun 26 06:20:42 PM PDT 24 Jun 26 06:20:48 PM PDT 24 480336257 ps
T565 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2916740121 Jun 26 06:20:52 PM PDT 24 Jun 26 06:20:55 PM PDT 24 191079123 ps
T116 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3679930892 Jun 26 06:20:53 PM PDT 24 Jun 26 06:20:57 PM PDT 24 545233948 ps
T566 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2907854966 Jun 26 06:20:48 PM PDT 24 Jun 26 06:20:50 PM PDT 24 189981180 ps
T567 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.755822629 Jun 26 06:20:57 PM PDT 24 Jun 26 06:21:00 PM PDT 24 130988569 ps
T568 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.621048974 Jun 26 06:20:43 PM PDT 24 Jun 26 06:20:45 PM PDT 24 74150805 ps
T569 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3293329749 Jun 26 06:20:39 PM PDT 24 Jun 26 06:20:42 PM PDT 24 250026957 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3692622547 Jun 26 06:20:45 PM PDT 24 Jun 26 06:20:47 PM PDT 24 70316649 ps
T571 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2832442041 Jun 26 06:20:52 PM PDT 24 Jun 26 06:20:55 PM PDT 24 156280147 ps
T572 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1511069663 Jun 26 06:20:44 PM PDT 24 Jun 26 06:20:47 PM PDT 24 128566435 ps
T573 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3263931875 Jun 26 06:20:51 PM PDT 24 Jun 26 06:20:54 PM PDT 24 81914405 ps
T574 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3101860246 Jun 26 06:21:11 PM PDT 24 Jun 26 06:21:14 PM PDT 24 110401919 ps
T118 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.678267458 Jun 26 06:20:37 PM PDT 24 Jun 26 06:20:42 PM PDT 24 1032250998 ps
T575 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.669358451 Jun 26 06:20:55 PM PDT 24 Jun 26 06:21:00 PM PDT 24 951213299 ps
T576 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.48559327 Jun 26 06:20:50 PM PDT 24 Jun 26 06:20:53 PM PDT 24 72705135 ps
T577 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3166424513 Jun 26 06:21:10 PM PDT 24 Jun 26 06:21:16 PM PDT 24 803780198 ps
T121 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1520249922 Jun 26 06:20:44 PM PDT 24 Jun 26 06:20:48 PM PDT 24 778036993 ps
T578 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.226214320 Jun 26 06:20:38 PM PDT 24 Jun 26 06:20:40 PM PDT 24 150456435 ps
T579 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1844267697 Jun 26 06:20:54 PM PDT 24 Jun 26 06:20:58 PM PDT 24 446403250 ps
T126 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1778759470 Jun 26 06:21:04 PM PDT 24 Jun 26 06:21:08 PM PDT 24 950954393 ps
T580 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1931680840 Jun 26 06:20:46 PM PDT 24 Jun 26 06:20:49 PM PDT 24 244318371 ps
T581 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1591585402 Jun 26 06:21:05 PM PDT 24 Jun 26 06:21:07 PM PDT 24 133748217 ps
T582 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1938631425 Jun 26 06:20:44 PM PDT 24 Jun 26 06:20:47 PM PDT 24 184363538 ps
T117 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.242632915 Jun 26 06:20:49 PM PDT 24 Jun 26 06:20:54 PM PDT 24 1026494336 ps
T583 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1512809610 Jun 26 06:21:03 PM PDT 24 Jun 26 06:21:06 PM PDT 24 488858968 ps
T584 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3835825015 Jun 26 06:20:44 PM PDT 24 Jun 26 06:20:47 PM PDT 24 150491986 ps
T585 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2979586500 Jun 26 06:20:53 PM PDT 24 Jun 26 06:20:56 PM PDT 24 213523827 ps
T586 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3202448598 Jun 26 06:20:39 PM PDT 24 Jun 26 06:20:43 PM PDT 24 436166165 ps
T587 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1398816971 Jun 26 06:20:49 PM PDT 24 Jun 26 06:20:52 PM PDT 24 189826817 ps
T588 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4202190229 Jun 26 06:20:44 PM PDT 24 Jun 26 06:20:47 PM PDT 24 140994883 ps
T100 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.989616491 Jun 26 06:20:50 PM PDT 24 Jun 26 06:20:52 PM PDT 24 58577245 ps
T589 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2701084442 Jun 26 06:20:56 PM PDT 24 Jun 26 06:20:59 PM PDT 24 94439059 ps
T590 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2679220449 Jun 26 06:20:57 PM PDT 24 Jun 26 06:21:00 PM PDT 24 202291896 ps
T591 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3301128999 Jun 26 06:21:03 PM PDT 24 Jun 26 06:21:06 PM PDT 24 136498558 ps
T592 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1382754412 Jun 26 06:21:02 PM PDT 24 Jun 26 06:21:04 PM PDT 24 179244808 ps
T593 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1374622664 Jun 26 06:20:37 PM PDT 24 Jun 26 06:20:39 PM PDT 24 73540150 ps
T594 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1191187424 Jun 26 06:21:00 PM PDT 24 Jun 26 06:21:02 PM PDT 24 199082668 ps
T595 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1565576998 Jun 26 06:20:51 PM PDT 24 Jun 26 06:20:55 PM PDT 24 167571814 ps
T596 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3021237438 Jun 26 06:20:37 PM PDT 24 Jun 26 06:20:40 PM PDT 24 483917226 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4209906835 Jun 26 06:20:44 PM PDT 24 Jun 26 06:20:56 PM PDT 24 2313882602 ps
T598 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2440334049 Jun 26 06:21:04 PM PDT 24 Jun 26 06:21:07 PM PDT 24 79788751 ps
T599 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2277201851 Jun 26 06:20:54 PM PDT 24 Jun 26 06:20:56 PM PDT 24 121689576 ps
T122 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3753108806 Jun 26 06:20:55 PM PDT 24 Jun 26 06:20:59 PM PDT 24 778577144 ps
T600 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3347845384 Jun 26 06:20:44 PM PDT 24 Jun 26 06:20:46 PM PDT 24 204077759 ps
T601 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.220103878 Jun 26 06:20:40 PM PDT 24 Jun 26 06:20:49 PM PDT 24 1534536966 ps
T602 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2415020464 Jun 26 06:20:50 PM PDT 24 Jun 26 06:20:53 PM PDT 24 187158123 ps
T603 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2601013857 Jun 26 06:21:01 PM PDT 24 Jun 26 06:21:03 PM PDT 24 83521958 ps
T604 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.853627698 Jun 26 06:20:59 PM PDT 24 Jun 26 06:21:02 PM PDT 24 247536637 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3746005071 Jun 26 06:20:40 PM PDT 24 Jun 26 06:20:43 PM PDT 24 194370713 ps
T606 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2411524040 Jun 26 06:20:50 PM PDT 24 Jun 26 06:20:53 PM PDT 24 289651627 ps
T607 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4002224620 Jun 26 06:21:00 PM PDT 24 Jun 26 06:21:05 PM PDT 24 451618582 ps
T608 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2334114050 Jun 26 06:20:57 PM PDT 24 Jun 26 06:20:59 PM PDT 24 69532038 ps
T609 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3039765435 Jun 26 06:20:55 PM PDT 24 Jun 26 06:20:57 PM PDT 24 100943591 ps
T610 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.955809965 Jun 26 06:21:03 PM PDT 24 Jun 26 06:21:06 PM PDT 24 168068188 ps
T611 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2100367356 Jun 26 06:21:03 PM PDT 24 Jun 26 06:21:05 PM PDT 24 68240014 ps
T612 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.221334642 Jun 26 06:21:01 PM PDT 24 Jun 26 06:21:03 PM PDT 24 75497443 ps
T613 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.520248283 Jun 26 06:21:12 PM PDT 24 Jun 26 06:21:15 PM PDT 24 287659550 ps
T614 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2275303790 Jun 26 06:21:04 PM PDT 24 Jun 26 06:21:06 PM PDT 24 72324931 ps
T615 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3345011738 Jun 26 06:20:44 PM PDT 24 Jun 26 06:20:47 PM PDT 24 83999098 ps
T616 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3988686666 Jun 26 06:20:56 PM PDT 24 Jun 26 06:21:00 PM PDT 24 234613286 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4225768647 Jun 26 06:20:43 PM PDT 24 Jun 26 06:20:45 PM PDT 24 198283926 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3227534892 Jun 26 06:20:39 PM PDT 24 Jun 26 06:20:46 PM PDT 24 484167740 ps
T619 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3553998810 Jun 26 06:21:01 PM PDT 24 Jun 26 06:21:05 PM PDT 24 496149925 ps
T620 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.791636227 Jun 26 06:21:04 PM PDT 24 Jun 26 06:21:07 PM PDT 24 169207805 ps

Test location /workspace/coverage/default/25.rstmgr_stress_all.3552665915
Short name T7
Test name
Test status
Simulation time 3226007873 ps
CPU time 14.37 seconds
Started Jun 26 06:22:07 PM PDT 24
Finished Jun 26 06:22:24 PM PDT 24
Peak memory 208604 kb
Host smart-9ab268c6-cf63-42e1-b2f4-87c4e5efc0a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552665915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3552665915
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1162744457
Short name T23
Test name
Test status
Simulation time 224904541 ps
CPU time 1.52 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:09 PM PDT 24
Peak memory 200272 kb
Host smart-df30e765-a460-47d0-9c92-14de6a6ceb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162744457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1162744457
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1225499657
Short name T88
Test name
Test status
Simulation time 825711798 ps
CPU time 2.87 seconds
Started Jun 26 06:20:49 PM PDT 24
Finished Jun 26 06:20:53 PM PDT 24
Peak memory 200496 kb
Host smart-6a832ed6-9750-4bb2-9508-d269da9d678a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225499657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1225499657
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3684222332
Short name T76
Test name
Test status
Simulation time 8287713704 ps
CPU time 15.06 seconds
Started Jun 26 06:21:19 PM PDT 24
Finished Jun 26 06:21:36 PM PDT 24
Peak memory 217092 kb
Host smart-67e795bc-d394-4935-95e1-4c4860eec4b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684222332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3684222332
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3001873263
Short name T24
Test name
Test status
Simulation time 1223745869 ps
CPU time 5.68 seconds
Started Jun 26 06:22:28 PM PDT 24
Finished Jun 26 06:22:35 PM PDT 24
Peak memory 217252 kb
Host smart-9913328b-989a-4609-94a5-20f0755b40f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001873263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3001873263
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3382003203
Short name T37
Test name
Test status
Simulation time 381621055 ps
CPU time 2.15 seconds
Started Jun 26 06:22:12 PM PDT 24
Finished Jun 26 06:22:15 PM PDT 24
Peak memory 200012 kb
Host smart-bd42be65-7a79-4154-9fe1-a0d988a58aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382003203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3382003203
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.497838489
Short name T73
Test name
Test status
Simulation time 509485847 ps
CPU time 4.19 seconds
Started Jun 26 06:20:44 PM PDT 24
Finished Jun 26 06:20:50 PM PDT 24
Peak memory 200356 kb
Host smart-52ae07cc-7dc8-4442-9955-8e79fd21f603
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497838489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.497838489
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2718038331
Short name T35
Test name
Test status
Simulation time 5464912582 ps
CPU time 23.92 seconds
Started Jun 26 06:21:33 PM PDT 24
Finished Jun 26 06:21:59 PM PDT 24
Peak memory 200424 kb
Host smart-154b73a4-8cdc-4760-b08d-43fa814a04aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718038331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2718038331
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3710308507
Short name T156
Test name
Test status
Simulation time 61661473 ps
CPU time 0.74 seconds
Started Jun 26 06:21:40 PM PDT 24
Finished Jun 26 06:21:42 PM PDT 24
Peak memory 199904 kb
Host smart-6f4c91e5-6827-4a7f-9733-22401e9a1ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710308507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3710308507
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3349971573
Short name T33
Test name
Test status
Simulation time 7987434963 ps
CPU time 28.92 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:22:23 PM PDT 24
Peak memory 208596 kb
Host smart-47ac02ce-290e-4989-bb41-575e99ed845c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349971573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3349971573
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2595068676
Short name T39
Test name
Test status
Simulation time 2365847063 ps
CPU time 8.47 seconds
Started Jun 26 06:22:25 PM PDT 24
Finished Jun 26 06:22:36 PM PDT 24
Peak memory 217840 kb
Host smart-d4298553-c48b-46f3-8847-6ee457ec63c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595068676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2595068676
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3389416129
Short name T151
Test name
Test status
Simulation time 94327613 ps
CPU time 1.01 seconds
Started Jun 26 06:21:30 PM PDT 24
Finished Jun 26 06:21:32 PM PDT 24
Peak memory 200088 kb
Host smart-e29e5bdc-3f5e-4fd7-8885-dcdc02f801fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389416129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3389416129
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2895679028
Short name T131
Test name
Test status
Simulation time 251986800 ps
CPU time 1.47 seconds
Started Jun 26 06:21:57 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 200116 kb
Host smart-c58ce8cc-89ab-4ff5-ad29-691da5c7a428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895679028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2895679028
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1778759470
Short name T126
Test name
Test status
Simulation time 950954393 ps
CPU time 3.27 seconds
Started Jun 26 06:21:04 PM PDT 24
Finished Jun 26 06:21:08 PM PDT 24
Peak memory 200476 kb
Host smart-339b2d61-dfbc-4d4e-ba74-64478359a578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778759470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1778759470
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1490042785
Short name T556
Test name
Test status
Simulation time 192492789 ps
CPU time 3 seconds
Started Jun 26 06:21:02 PM PDT 24
Finished Jun 26 06:21:06 PM PDT 24
Peak memory 208552 kb
Host smart-cb0ce61c-d9b9-4491-8dac-4e97814e5250
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490042785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1490042785
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1221907239
Short name T114
Test name
Test status
Simulation time 212327009 ps
CPU time 1.48 seconds
Started Jun 26 06:20:37 PM PDT 24
Finished Jun 26 06:20:40 PM PDT 24
Peak memory 200424 kb
Host smart-578ca03b-9f11-481e-ab71-55a736ac27f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221907239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1221907239
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2371534896
Short name T19
Test name
Test status
Simulation time 80163955 ps
CPU time 0.74 seconds
Started Jun 26 06:21:32 PM PDT 24
Finished Jun 26 06:21:34 PM PDT 24
Peak memory 199900 kb
Host smart-4bae2e39-bad8-426f-933b-2c5a9b967a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371534896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2371534896
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3679930892
Short name T116
Test name
Test status
Simulation time 545233948 ps
CPU time 2.11 seconds
Started Jun 26 06:20:53 PM PDT 24
Finished Jun 26 06:20:57 PM PDT 24
Peak memory 200424 kb
Host smart-c09f0cc0-d6ce-4b14-a66c-9cff38d4a9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679930892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3679930892
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3753108806
Short name T122
Test name
Test status
Simulation time 778577144 ps
CPU time 3.33 seconds
Started Jun 26 06:20:55 PM PDT 24
Finished Jun 26 06:20:59 PM PDT 24
Peak memory 200324 kb
Host smart-2e72393c-84bd-43bd-aba9-afe341ebed0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753108806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3753108806
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.678267458
Short name T118
Test name
Test status
Simulation time 1032250998 ps
CPU time 3.59 seconds
Started Jun 26 06:20:37 PM PDT 24
Finished Jun 26 06:20:42 PM PDT 24
Peak memory 200460 kb
Host smart-f3440e8e-eef4-4fbc-9aee-5f3f1878295f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678267458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
678267458
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.849964276
Short name T123
Test name
Test status
Simulation time 430944399 ps
CPU time 1.8 seconds
Started Jun 26 06:20:45 PM PDT 24
Finished Jun 26 06:20:48 PM PDT 24
Peak memory 200468 kb
Host smart-bf7cd605-9884-49e0-9692-d0b2733e5f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849964276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
849964276
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3202448598
Short name T586
Test name
Test status
Simulation time 436166165 ps
CPU time 2.37 seconds
Started Jun 26 06:20:39 PM PDT 24
Finished Jun 26 06:20:43 PM PDT 24
Peak memory 200280 kb
Host smart-043eb3dc-312d-4938-9bdf-94e8e36bba63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202448598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
202448598
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.220103878
Short name T601
Test name
Test status
Simulation time 1534536966 ps
CPU time 8.69 seconds
Started Jun 26 06:20:40 PM PDT 24
Finished Jun 26 06:20:49 PM PDT 24
Peak memory 200372 kb
Host smart-13361aa4-eadb-4787-a53e-f9c1756c8449
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220103878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.220103878
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.381718395
Short name T554
Test name
Test status
Simulation time 91943364 ps
CPU time 0.82 seconds
Started Jun 26 06:20:40 PM PDT 24
Finished Jun 26 06:20:41 PM PDT 24
Peak memory 200372 kb
Host smart-07001733-4e10-45ee-9264-0f28ac2d9884
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381718395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.381718395
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.66526972
Short name T560
Test name
Test status
Simulation time 203708599 ps
CPU time 1.44 seconds
Started Jun 26 06:20:38 PM PDT 24
Finished Jun 26 06:20:41 PM PDT 24
Peak memory 211216 kb
Host smart-ac35d5a9-aac3-4067-ac7d-1e30da7554b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66526972 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.66526972
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3709114379
Short name T128
Test name
Test status
Simulation time 72191858 ps
CPU time 0.86 seconds
Started Jun 26 06:20:40 PM PDT 24
Finished Jun 26 06:20:42 PM PDT 24
Peak memory 200120 kb
Host smart-de0aff27-fc9d-4a43-abac-3fed7c27914a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709114379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3709114379
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.871537616
Short name T97
Test name
Test status
Simulation time 155279490 ps
CPU time 2.24 seconds
Started Jun 26 06:20:39 PM PDT 24
Finished Jun 26 06:20:42 PM PDT 24
Peak memory 208496 kb
Host smart-e3365887-4798-4c19-8466-74011aac0b94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871537616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.871537616
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3021237438
Short name T596
Test name
Test status
Simulation time 483917226 ps
CPU time 1.92 seconds
Started Jun 26 06:20:37 PM PDT 24
Finished Jun 26 06:20:40 PM PDT 24
Peak memory 200428 kb
Host smart-d35831f2-21f4-4109-89ee-348094c8bacb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021237438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3021237438
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3293329749
Short name T569
Test name
Test status
Simulation time 250026957 ps
CPU time 1.8 seconds
Started Jun 26 06:20:39 PM PDT 24
Finished Jun 26 06:20:42 PM PDT 24
Peak memory 200380 kb
Host smart-d201fbdf-6c2b-4e13-aedd-f008375943ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293329749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
293329749
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3227534892
Short name T618
Test name
Test status
Simulation time 484167740 ps
CPU time 5.94 seconds
Started Jun 26 06:20:39 PM PDT 24
Finished Jun 26 06:20:46 PM PDT 24
Peak memory 200360 kb
Host smart-2bae8fea-f60a-487a-977e-0a4d5ccd1b59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227534892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
227534892
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.226214320
Short name T578
Test name
Test status
Simulation time 150456435 ps
CPU time 0.97 seconds
Started Jun 26 06:20:38 PM PDT 24
Finished Jun 26 06:20:40 PM PDT 24
Peak memory 200184 kb
Host smart-3c4d41e5-2c45-475c-8d9f-23a5d713d77b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226214320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.226214320
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3746005071
Short name T605
Test name
Test status
Simulation time 194370713 ps
CPU time 1.27 seconds
Started Jun 26 06:20:40 PM PDT 24
Finished Jun 26 06:20:43 PM PDT 24
Peak memory 208992 kb
Host smart-66d6ff14-34a0-449d-938a-41fd2cf17902
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746005071 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3746005071
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2457018826
Short name T551
Test name
Test status
Simulation time 75537535 ps
CPU time 0.85 seconds
Started Jun 26 06:20:38 PM PDT 24
Finished Jun 26 06:20:40 PM PDT 24
Peak memory 200224 kb
Host smart-b4f25e1c-92d5-404a-974f-98ac1ca9e9f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457018826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2457018826
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1374622664
Short name T593
Test name
Test status
Simulation time 73540150 ps
CPU time 0.94 seconds
Started Jun 26 06:20:37 PM PDT 24
Finished Jun 26 06:20:39 PM PDT 24
Peak memory 200280 kb
Host smart-7b187158-e3f3-48e6-aa95-71a58bb4e002
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374622664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1374622664
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1249487448
Short name T71
Test name
Test status
Simulation time 228700351 ps
CPU time 1.91 seconds
Started Jun 26 06:20:38 PM PDT 24
Finished Jun 26 06:20:41 PM PDT 24
Peak memory 208512 kb
Host smart-b4a29716-09c3-410f-b741-ba756e7c5891
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249487448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1249487448
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2240283980
Short name T89
Test name
Test status
Simulation time 490367606 ps
CPU time 1.87 seconds
Started Jun 26 06:20:36 PM PDT 24
Finished Jun 26 06:20:38 PM PDT 24
Peak memory 200420 kb
Host smart-f9f10b9d-8802-4392-a162-23f06f33506a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240283980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2240283980
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2679220449
Short name T590
Test name
Test status
Simulation time 202291896 ps
CPU time 1.4 seconds
Started Jun 26 06:20:57 PM PDT 24
Finished Jun 26 06:21:00 PM PDT 24
Peak memory 208540 kb
Host smart-6a78d9b0-3f68-4e1d-bcc8-45773413e596
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679220449 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2679220449
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2288351868
Short name T545
Test name
Test status
Simulation time 67662346 ps
CPU time 0.75 seconds
Started Jun 26 06:20:56 PM PDT 24
Finished Jun 26 06:20:58 PM PDT 24
Peak memory 200128 kb
Host smart-5362ef45-b4ad-4a8e-85e3-165d0800900e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288351868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2288351868
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2701084442
Short name T589
Test name
Test status
Simulation time 94439059 ps
CPU time 1.26 seconds
Started Jun 26 06:20:56 PM PDT 24
Finished Jun 26 06:20:59 PM PDT 24
Peak memory 200348 kb
Host smart-0e99b737-5aee-4b24-9099-e2da9ff7abcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701084442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2701084442
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1021473682
Short name T90
Test name
Test status
Simulation time 311447351 ps
CPU time 2.33 seconds
Started Jun 26 06:20:58 PM PDT 24
Finished Jun 26 06:21:01 PM PDT 24
Peak memory 208436 kb
Host smart-b09f9b0b-88bf-4e3e-a1de-d6f3b331697c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021473682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1021473682
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3002214157
Short name T92
Test name
Test status
Simulation time 968743243 ps
CPU time 3.28 seconds
Started Jun 26 06:20:55 PM PDT 24
Finished Jun 26 06:21:00 PM PDT 24
Peak memory 200320 kb
Host smart-50cad080-6dce-4e30-80fa-b31ac4e80654
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002214157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3002214157
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1191187424
Short name T594
Test name
Test status
Simulation time 199082668 ps
CPU time 1.41 seconds
Started Jun 26 06:21:00 PM PDT 24
Finished Jun 26 06:21:02 PM PDT 24
Peak memory 208564 kb
Host smart-f7717270-1665-463e-a55e-13f2d97f3ce8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191187424 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1191187424
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4079084702
Short name T111
Test name
Test status
Simulation time 98072237 ps
CPU time 0.87 seconds
Started Jun 26 06:20:56 PM PDT 24
Finished Jun 26 06:20:59 PM PDT 24
Peak memory 200228 kb
Host smart-70765481-a155-4773-bba1-2b3c011409d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079084702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4079084702
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.153960298
Short name T562
Test name
Test status
Simulation time 90788723 ps
CPU time 1.09 seconds
Started Jun 26 06:20:58 PM PDT 24
Finished Jun 26 06:21:00 PM PDT 24
Peak memory 200508 kb
Host smart-0e78a502-e03e-4973-b2fe-e51908ad88a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153960298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.153960298
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3988686666
Short name T616
Test name
Test status
Simulation time 234613286 ps
CPU time 2.01 seconds
Started Jun 26 06:20:56 PM PDT 24
Finished Jun 26 06:21:00 PM PDT 24
Peak memory 216660 kb
Host smart-cffba2c7-6eda-44c3-8203-a21f1dbd1cd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988686666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3988686666
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.669358451
Short name T575
Test name
Test status
Simulation time 951213299 ps
CPU time 3.29 seconds
Started Jun 26 06:20:55 PM PDT 24
Finished Jun 26 06:21:00 PM PDT 24
Peak memory 200508 kb
Host smart-296bdf6c-a47e-4645-aea2-326263abd7d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669358451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.669358451
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2277201851
Short name T599
Test name
Test status
Simulation time 121689576 ps
CPU time 1.04 seconds
Started Jun 26 06:20:54 PM PDT 24
Finished Jun 26 06:20:56 PM PDT 24
Peak memory 200368 kb
Host smart-2327bf27-c942-403e-8263-edecb8e9a9c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277201851 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2277201851
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2334114050
Short name T608
Test name
Test status
Simulation time 69532038 ps
CPU time 0.82 seconds
Started Jun 26 06:20:57 PM PDT 24
Finished Jun 26 06:20:59 PM PDT 24
Peak memory 200220 kb
Host smart-5de5efbd-9c68-404d-9cbe-128ec5f43969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334114050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2334114050
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.362976910
Short name T555
Test name
Test status
Simulation time 85833011 ps
CPU time 1.08 seconds
Started Jun 26 06:20:56 PM PDT 24
Finished Jun 26 06:20:58 PM PDT 24
Peak memory 200192 kb
Host smart-a5b58f82-f84e-4cf0-b6ad-52539d7d020e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362976910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.362976910
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1001067972
Short name T93
Test name
Test status
Simulation time 460112773 ps
CPU time 3.04 seconds
Started Jun 26 06:20:55 PM PDT 24
Finished Jun 26 06:20:59 PM PDT 24
Peak memory 216708 kb
Host smart-0721bf3a-050f-466a-8e64-33468c06fc47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001067972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1001067972
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1286423436
Short name T553
Test name
Test status
Simulation time 178244556 ps
CPU time 1.25 seconds
Started Jun 26 06:20:55 PM PDT 24
Finished Jun 26 06:20:58 PM PDT 24
Peak memory 208540 kb
Host smart-6fe96c87-f5ef-4477-9ffb-b36ba09302d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286423436 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1286423436
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1785493799
Short name T547
Test name
Test status
Simulation time 88940654 ps
CPU time 0.91 seconds
Started Jun 26 06:20:56 PM PDT 24
Finished Jun 26 06:20:58 PM PDT 24
Peak memory 200200 kb
Host smart-e1f36dc1-a0a7-4349-b270-af1709f7e4c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785493799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1785493799
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.755822629
Short name T567
Test name
Test status
Simulation time 130988569 ps
CPU time 1.33 seconds
Started Jun 26 06:20:57 PM PDT 24
Finished Jun 26 06:21:00 PM PDT 24
Peak memory 200316 kb
Host smart-853a8fce-5ee9-43e4-a541-8141f6c55d35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755822629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.755822629
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.853627698
Short name T604
Test name
Test status
Simulation time 247536637 ps
CPU time 1.87 seconds
Started Jun 26 06:20:59 PM PDT 24
Finished Jun 26 06:21:02 PM PDT 24
Peak memory 208500 kb
Host smart-14f85527-91c8-46d5-bb4d-619e2b0273f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853627698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.853627698
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1333129494
Short name T79
Test name
Test status
Simulation time 465738934 ps
CPU time 1.99 seconds
Started Jun 26 06:21:00 PM PDT 24
Finished Jun 26 06:21:03 PM PDT 24
Peak memory 200484 kb
Host smart-d882e157-006c-407f-9baf-88c0774e5837
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333129494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1333129494
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.955809965
Short name T610
Test name
Test status
Simulation time 168068188 ps
CPU time 1.19 seconds
Started Jun 26 06:21:03 PM PDT 24
Finished Jun 26 06:21:06 PM PDT 24
Peak memory 200356 kb
Host smart-985a0a37-15ec-4bfe-804b-19e4c9c89d90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955809965 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.955809965
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.221334642
Short name T612
Test name
Test status
Simulation time 75497443 ps
CPU time 0.83 seconds
Started Jun 26 06:21:01 PM PDT 24
Finished Jun 26 06:21:03 PM PDT 24
Peak memory 200224 kb
Host smart-ad8feb3f-ad78-4438-9608-6405d8edd8b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221334642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.221334642
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3039765435
Short name T609
Test name
Test status
Simulation time 100943591 ps
CPU time 1.31 seconds
Started Jun 26 06:20:55 PM PDT 24
Finished Jun 26 06:20:57 PM PDT 24
Peak memory 200408 kb
Host smart-9f88a137-1a0b-42b2-9358-37e376490543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039765435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3039765435
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2979586500
Short name T585
Test name
Test status
Simulation time 213523827 ps
CPU time 1.92 seconds
Started Jun 26 06:20:53 PM PDT 24
Finished Jun 26 06:20:56 PM PDT 24
Peak memory 208528 kb
Host smart-5455f856-48c0-48bb-a13a-c6e721af58cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979586500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2979586500
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1382754412
Short name T592
Test name
Test status
Simulation time 179244808 ps
CPU time 1.21 seconds
Started Jun 26 06:21:02 PM PDT 24
Finished Jun 26 06:21:04 PM PDT 24
Peak memory 200328 kb
Host smart-e22c3574-0147-4597-8d2a-649b008a58b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382754412 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1382754412
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2275303790
Short name T614
Test name
Test status
Simulation time 72324931 ps
CPU time 0.83 seconds
Started Jun 26 06:21:04 PM PDT 24
Finished Jun 26 06:21:06 PM PDT 24
Peak memory 200228 kb
Host smart-e128f1fc-138a-4268-a6ae-fd57723c13b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275303790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2275303790
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.791636227
Short name T620
Test name
Test status
Simulation time 169207805 ps
CPU time 1.37 seconds
Started Jun 26 06:21:04 PM PDT 24
Finished Jun 26 06:21:07 PM PDT 24
Peak memory 200268 kb
Host smart-50514a6d-2749-42fa-b003-87cb8da14666
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791636227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.791636227
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.967661146
Short name T120
Test name
Test status
Simulation time 935573984 ps
CPU time 3.29 seconds
Started Jun 26 06:21:02 PM PDT 24
Finished Jun 26 06:21:06 PM PDT 24
Peak memory 200444 kb
Host smart-40481efb-6081-410c-b7cc-52c8be4052c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967661146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.967661146
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1591585402
Short name T581
Test name
Test status
Simulation time 133748217 ps
CPU time 1.57 seconds
Started Jun 26 06:21:05 PM PDT 24
Finished Jun 26 06:21:07 PM PDT 24
Peak memory 208784 kb
Host smart-c371a6cb-bf4e-4ceb-a034-2bbf2a58c61e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591585402 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1591585402
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1259740103
Short name T546
Test name
Test status
Simulation time 67981041 ps
CPU time 0.85 seconds
Started Jun 26 06:21:05 PM PDT 24
Finished Jun 26 06:21:07 PM PDT 24
Peak memory 200216 kb
Host smart-690ffbf5-963b-45eb-af27-e629d6a9edac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259740103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1259740103
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2601013857
Short name T603
Test name
Test status
Simulation time 83521958 ps
CPU time 1.07 seconds
Started Jun 26 06:21:01 PM PDT 24
Finished Jun 26 06:21:03 PM PDT 24
Peak memory 200256 kb
Host smart-41a0fbb7-34de-4cbd-ac7d-33249a44937a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601013857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2601013857
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3553998810
Short name T619
Test name
Test status
Simulation time 496149925 ps
CPU time 3.95 seconds
Started Jun 26 06:21:01 PM PDT 24
Finished Jun 26 06:21:05 PM PDT 24
Peak memory 208556 kb
Host smart-7297985d-0801-40c4-b371-1abd2c4f9ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553998810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3553998810
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3947913018
Short name T70
Test name
Test status
Simulation time 491901648 ps
CPU time 2.26 seconds
Started Jun 26 06:21:00 PM PDT 24
Finished Jun 26 06:21:03 PM PDT 24
Peak memory 200320 kb
Host smart-1e191f94-c443-47db-9afd-f1931d1caf94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947913018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3947913018
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3301128999
Short name T591
Test name
Test status
Simulation time 136498558 ps
CPU time 1.21 seconds
Started Jun 26 06:21:03 PM PDT 24
Finished Jun 26 06:21:06 PM PDT 24
Peak memory 200256 kb
Host smart-d8759c16-ce2d-4794-b07f-f4d036e668d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301128999 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3301128999
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2100367356
Short name T611
Test name
Test status
Simulation time 68240014 ps
CPU time 0.89 seconds
Started Jun 26 06:21:03 PM PDT 24
Finished Jun 26 06:21:05 PM PDT 24
Peak memory 200408 kb
Host smart-31ecf727-5e78-4ce2-b6e7-3f947935384e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100367356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2100367356
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2440334049
Short name T598
Test name
Test status
Simulation time 79788751 ps
CPU time 1.06 seconds
Started Jun 26 06:21:04 PM PDT 24
Finished Jun 26 06:21:07 PM PDT 24
Peak memory 200248 kb
Host smart-665d4646-e17d-4f4b-8412-0d588404ab28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440334049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2440334049
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3379061934
Short name T563
Test name
Test status
Simulation time 124491733 ps
CPU time 1.65 seconds
Started Jun 26 06:21:06 PM PDT 24
Finished Jun 26 06:21:08 PM PDT 24
Peak memory 208584 kb
Host smart-8e0f37bd-f619-4951-9ece-1dc916ddf1fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379061934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3379061934
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3408728188
Short name T91
Test name
Test status
Simulation time 197862968 ps
CPU time 1.26 seconds
Started Jun 26 06:21:04 PM PDT 24
Finished Jun 26 06:21:06 PM PDT 24
Peak memory 208560 kb
Host smart-9f68224a-e835-459e-97aa-5e629905eed9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408728188 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3408728188
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1053357187
Short name T552
Test name
Test status
Simulation time 65445362 ps
CPU time 0.87 seconds
Started Jun 26 06:21:03 PM PDT 24
Finished Jun 26 06:21:05 PM PDT 24
Peak memory 200192 kb
Host smart-6380b89c-6e42-4452-ae25-270e4dd671d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053357187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1053357187
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2441047405
Short name T67
Test name
Test status
Simulation time 73698362 ps
CPU time 0.92 seconds
Started Jun 26 06:21:04 PM PDT 24
Finished Jun 26 06:21:06 PM PDT 24
Peak memory 200224 kb
Host smart-b2b50946-d76b-4112-b388-c60f19ce90fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441047405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2441047405
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4002224620
Short name T607
Test name
Test status
Simulation time 451618582 ps
CPU time 3.69 seconds
Started Jun 26 06:21:00 PM PDT 24
Finished Jun 26 06:21:05 PM PDT 24
Peak memory 216720 kb
Host smart-46b22480-a988-4d02-9fa2-74c862dca89d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002224620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.4002224620
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1512809610
Short name T583
Test name
Test status
Simulation time 488858968 ps
CPU time 2.05 seconds
Started Jun 26 06:21:03 PM PDT 24
Finished Jun 26 06:21:06 PM PDT 24
Peak memory 200416 kb
Host smart-88f24139-942f-4a11-9d72-a69266cc3132
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512809610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1512809610
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3101860246
Short name T574
Test name
Test status
Simulation time 110401919 ps
CPU time 1 seconds
Started Jun 26 06:21:11 PM PDT 24
Finished Jun 26 06:21:14 PM PDT 24
Peak memory 200256 kb
Host smart-a69fc653-c8af-4fae-8dd0-902b470609a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101860246 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3101860246
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2081138428
Short name T112
Test name
Test status
Simulation time 66573686 ps
CPU time 0.78 seconds
Started Jun 26 06:21:15 PM PDT 24
Finished Jun 26 06:21:16 PM PDT 24
Peak memory 200136 kb
Host smart-e6fbdfdc-8ef9-4e11-836e-1c9e3e6247db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081138428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2081138428
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.520248283
Short name T613
Test name
Test status
Simulation time 287659550 ps
CPU time 1.72 seconds
Started Jun 26 06:21:12 PM PDT 24
Finished Jun 26 06:21:15 PM PDT 24
Peak memory 200412 kb
Host smart-4496b299-7e19-4d1a-9abb-5109aa7ef8f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520248283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.520248283
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.154942192
Short name T559
Test name
Test status
Simulation time 312956552 ps
CPU time 2.18 seconds
Started Jun 26 06:21:04 PM PDT 24
Finished Jun 26 06:21:07 PM PDT 24
Peak memory 208504 kb
Host smart-09a6b45b-91df-40a5-8f5c-632abb5a900b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154942192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.154942192
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.13825531
Short name T95
Test name
Test status
Simulation time 768704011 ps
CPU time 2.98 seconds
Started Jun 26 06:21:14 PM PDT 24
Finished Jun 26 06:21:18 PM PDT 24
Peak memory 200400 kb
Host smart-caa687f6-7e8c-4b76-9f0c-66273b227bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13825531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.13825531
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2088006566
Short name T127
Test name
Test status
Simulation time 463239394 ps
CPU time 2.74 seconds
Started Jun 26 06:20:42 PM PDT 24
Finished Jun 26 06:20:46 PM PDT 24
Peak memory 200380 kb
Host smart-2d4062c0-f7f7-4746-9e83-921ca2c9ce30
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088006566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
088006566
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2623753935
Short name T564
Test name
Test status
Simulation time 480336257 ps
CPU time 5.52 seconds
Started Jun 26 06:20:42 PM PDT 24
Finished Jun 26 06:20:48 PM PDT 24
Peak memory 200384 kb
Host smart-c229aa00-1f2e-4bd7-bc70-a7ee94eb35d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623753935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
623753935
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.22538367
Short name T549
Test name
Test status
Simulation time 141902443 ps
CPU time 1.02 seconds
Started Jun 26 06:20:44 PM PDT 24
Finished Jun 26 06:20:47 PM PDT 24
Peak memory 200124 kb
Host smart-494a890a-bc3f-4614-9df4-5eeb270a7a59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22538367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.22538367
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3347845384
Short name T600
Test name
Test status
Simulation time 204077759 ps
CPU time 1.37 seconds
Started Jun 26 06:20:44 PM PDT 24
Finished Jun 26 06:20:46 PM PDT 24
Peak memory 208628 kb
Host smart-24bd7177-3ce0-47a4-934a-7dd811a5854c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347845384 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3347845384
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3345011738
Short name T615
Test name
Test status
Simulation time 83999098 ps
CPU time 0.88 seconds
Started Jun 26 06:20:44 PM PDT 24
Finished Jun 26 06:20:47 PM PDT 24
Peak memory 200408 kb
Host smart-90f85981-e3b8-4526-b69a-7e4713cd9f4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345011738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3345011738
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1511069663
Short name T572
Test name
Test status
Simulation time 128566435 ps
CPU time 1.14 seconds
Started Jun 26 06:20:44 PM PDT 24
Finished Jun 26 06:20:47 PM PDT 24
Peak memory 200292 kb
Host smart-ee83e146-3ebb-4836-84ae-5c4ee72c00e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511069663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1511069663
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3092192613
Short name T96
Test name
Test status
Simulation time 594122588 ps
CPU time 4.46 seconds
Started Jun 26 06:20:36 PM PDT 24
Finished Jun 26 06:20:41 PM PDT 24
Peak memory 208388 kb
Host smart-66b40e41-b268-4ac1-89b7-fbdede0dfb8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092192613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3092192613
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1931680840
Short name T580
Test name
Test status
Simulation time 244318371 ps
CPU time 1.78 seconds
Started Jun 26 06:20:46 PM PDT 24
Finished Jun 26 06:20:49 PM PDT 24
Peak memory 200388 kb
Host smart-4c93d8a1-b203-47fe-8f55-edca468d1b1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931680840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
931680840
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3166424513
Short name T577
Test name
Test status
Simulation time 803780198 ps
CPU time 4.52 seconds
Started Jun 26 06:21:10 PM PDT 24
Finished Jun 26 06:21:16 PM PDT 24
Peak memory 200276 kb
Host smart-ec6fb409-1307-4620-844a-60efc2de7419
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166424513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
166424513
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4202190229
Short name T588
Test name
Test status
Simulation time 140994883 ps
CPU time 0.94 seconds
Started Jun 26 06:20:44 PM PDT 24
Finished Jun 26 06:20:47 PM PDT 24
Peak memory 200244 kb
Host smart-2876b90d-5e4a-4be6-a684-1d687aa5ffe9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202190229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4
202190229
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3835825015
Short name T584
Test name
Test status
Simulation time 150491986 ps
CPU time 1.36 seconds
Started Jun 26 06:20:44 PM PDT 24
Finished Jun 26 06:20:47 PM PDT 24
Peak memory 208552 kb
Host smart-e0b5086d-ba7b-4c23-8445-53b225ea309c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835825015 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3835825015
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3692622547
Short name T570
Test name
Test status
Simulation time 70316649 ps
CPU time 0.77 seconds
Started Jun 26 06:20:45 PM PDT 24
Finished Jun 26 06:20:47 PM PDT 24
Peak memory 200200 kb
Host smart-037b576d-9b0f-4bdb-8a77-cf201ca59420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692622547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3692622547
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4225768647
Short name T617
Test name
Test status
Simulation time 198283926 ps
CPU time 1.56 seconds
Started Jun 26 06:20:43 PM PDT 24
Finished Jun 26 06:20:45 PM PDT 24
Peak memory 200392 kb
Host smart-10e94f49-c206-4f8d-a1d8-a949c113cb2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225768647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4225768647
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1758422068
Short name T94
Test name
Test status
Simulation time 98986319 ps
CPU time 1.38 seconds
Started Jun 26 06:20:47 PM PDT 24
Finished Jun 26 06:20:49 PM PDT 24
Peak memory 208556 kb
Host smart-6c668e21-0729-4e5b-b003-3e4323e078c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758422068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1758422068
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3661205916
Short name T561
Test name
Test status
Simulation time 113981715 ps
CPU time 1.38 seconds
Started Jun 26 06:20:43 PM PDT 24
Finished Jun 26 06:20:46 PM PDT 24
Peak memory 200280 kb
Host smart-3b7ffc45-f047-4d0a-8cd1-8d4e6105024a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661205916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
661205916
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4209906835
Short name T597
Test name
Test status
Simulation time 2313882602 ps
CPU time 10.5 seconds
Started Jun 26 06:20:44 PM PDT 24
Finished Jun 26 06:20:56 PM PDT 24
Peak memory 200448 kb
Host smart-a405ce6f-1a59-4583-bd9f-8bc1e9c99dff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209906835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4
209906835
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1644766762
Short name T69
Test name
Test status
Simulation time 139356710 ps
CPU time 1 seconds
Started Jun 26 06:20:45 PM PDT 24
Finished Jun 26 06:20:48 PM PDT 24
Peak memory 200244 kb
Host smart-1ea8e416-e67e-41c2-9025-66fae7a59b2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644766762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
644766762
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1938631425
Short name T582
Test name
Test status
Simulation time 184363538 ps
CPU time 1.37 seconds
Started Jun 26 06:20:44 PM PDT 24
Finished Jun 26 06:20:47 PM PDT 24
Peak memory 208508 kb
Host smart-325af83f-5008-40a8-a8aa-9eff9827737d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938631425 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1938631425
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1159680521
Short name T558
Test name
Test status
Simulation time 59157120 ps
CPU time 0.73 seconds
Started Jun 26 06:20:43 PM PDT 24
Finished Jun 26 06:20:45 PM PDT 24
Peak memory 200216 kb
Host smart-d2cd65ab-8bf3-4583-82d8-43d31d524b33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159680521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1159680521
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.968616862
Short name T110
Test name
Test status
Simulation time 153323518 ps
CPU time 1.2 seconds
Started Jun 26 06:20:43 PM PDT 24
Finished Jun 26 06:20:46 PM PDT 24
Peak memory 200248 kb
Host smart-698a4822-b7d9-4cc9-8819-b9d9b999c580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968616862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.968616862
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2722750736
Short name T119
Test name
Test status
Simulation time 422829673 ps
CPU time 2.66 seconds
Started Jun 26 06:20:46 PM PDT 24
Finished Jun 26 06:20:50 PM PDT 24
Peak memory 208624 kb
Host smart-7fb957ab-2821-4d5d-b7be-825642599cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722750736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2722750736
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1359273654
Short name T550
Test name
Test status
Simulation time 506530916 ps
CPU time 2.1 seconds
Started Jun 26 06:20:43 PM PDT 24
Finished Jun 26 06:20:46 PM PDT 24
Peak memory 200444 kb
Host smart-6e219bbf-f0d9-4083-8d32-7a2a4d89b185
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359273654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1359273654
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2916740121
Short name T565
Test name
Test status
Simulation time 191079123 ps
CPU time 1.27 seconds
Started Jun 26 06:20:52 PM PDT 24
Finished Jun 26 06:20:55 PM PDT 24
Peak memory 208560 kb
Host smart-700fd8b3-0f1d-46f1-a82c-05ef96400fa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916740121 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2916740121
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.621048974
Short name T568
Test name
Test status
Simulation time 74150805 ps
CPU time 0.81 seconds
Started Jun 26 06:20:43 PM PDT 24
Finished Jun 26 06:20:45 PM PDT 24
Peak memory 200060 kb
Host smart-91c6cc0a-c5e1-44ca-8e8c-a25860d9dfe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621048974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.621048974
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2415020464
Short name T602
Test name
Test status
Simulation time 187158123 ps
CPU time 1.44 seconds
Started Jun 26 06:20:50 PM PDT 24
Finished Jun 26 06:20:53 PM PDT 24
Peak memory 200412 kb
Host smart-60d5b6a1-3324-48dd-bb6b-d1717d6ed26f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415020464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2415020464
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1520249922
Short name T121
Test name
Test status
Simulation time 778036993 ps
CPU time 2.69 seconds
Started Jun 26 06:20:44 PM PDT 24
Finished Jun 26 06:20:48 PM PDT 24
Peak memory 200504 kb
Host smart-9e7982c7-bd7c-495d-b332-46b96fa86208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520249922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1520249922
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1398816971
Short name T587
Test name
Test status
Simulation time 189826817 ps
CPU time 1.35 seconds
Started Jun 26 06:20:49 PM PDT 24
Finished Jun 26 06:20:52 PM PDT 24
Peak memory 208552 kb
Host smart-957ebc3b-5d11-4be6-91ca-6672509349a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398816971 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1398816971
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3263931875
Short name T573
Test name
Test status
Simulation time 81914405 ps
CPU time 0.87 seconds
Started Jun 26 06:20:51 PM PDT 24
Finished Jun 26 06:20:54 PM PDT 24
Peak memory 200192 kb
Host smart-04664c88-efff-4618-a5bd-c866abf8e9b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263931875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3263931875
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4110034716
Short name T109
Test name
Test status
Simulation time 132539145 ps
CPU time 1.35 seconds
Started Jun 26 06:20:50 PM PDT 24
Finished Jun 26 06:20:53 PM PDT 24
Peak memory 200444 kb
Host smart-0d6036ea-46f2-4704-9d60-feba52fe414c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110034716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.4110034716
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2411524040
Short name T606
Test name
Test status
Simulation time 289651627 ps
CPU time 2.15 seconds
Started Jun 26 06:20:50 PM PDT 24
Finished Jun 26 06:20:53 PM PDT 24
Peak memory 216672 kb
Host smart-2a1296ab-4daf-48a4-9bd2-0ca7d4d2c37b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411524040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2411524040
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4063030224
Short name T548
Test name
Test status
Simulation time 786328700 ps
CPU time 2.97 seconds
Started Jun 26 06:20:50 PM PDT 24
Finished Jun 26 06:20:54 PM PDT 24
Peak memory 208664 kb
Host smart-711603b2-8e13-48ee-b7e0-cd33858ab969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063030224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.4063030224
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3154070072
Short name T557
Test name
Test status
Simulation time 206817359 ps
CPU time 1.26 seconds
Started Jun 26 06:20:51 PM PDT 24
Finished Jun 26 06:20:54 PM PDT 24
Peak memory 208532 kb
Host smart-474d3aac-007e-4406-8132-92d71a4675d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154070072 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3154070072
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.989616491
Short name T100
Test name
Test status
Simulation time 58577245 ps
CPU time 0.76 seconds
Started Jun 26 06:20:50 PM PDT 24
Finished Jun 26 06:20:52 PM PDT 24
Peak memory 200188 kb
Host smart-355407d9-aae0-41e1-8a9f-cee3b61258ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989616491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.989616491
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.679669701
Short name T68
Test name
Test status
Simulation time 155579069 ps
CPU time 1.17 seconds
Started Jun 26 06:20:52 PM PDT 24
Finished Jun 26 06:20:55 PM PDT 24
Peak memory 200300 kb
Host smart-07d0a9ca-4343-4ed0-a6c6-4ef691971d70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679669701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.679669701
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4056866482
Short name T74
Test name
Test status
Simulation time 610119732 ps
CPU time 3.58 seconds
Started Jun 26 06:20:50 PM PDT 24
Finished Jun 26 06:20:55 PM PDT 24
Peak memory 208568 kb
Host smart-05926e97-048c-46ac-9d0b-6c30a8d9d9cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056866482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.4056866482
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.242632915
Short name T117
Test name
Test status
Simulation time 1026494336 ps
CPU time 3.41 seconds
Started Jun 26 06:20:49 PM PDT 24
Finished Jun 26 06:20:54 PM PDT 24
Peak memory 200444 kb
Host smart-44c2ed36-5a6f-4743-9034-c277d0272752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242632915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
242632915
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2832442041
Short name T571
Test name
Test status
Simulation time 156280147 ps
CPU time 1.31 seconds
Started Jun 26 06:20:52 PM PDT 24
Finished Jun 26 06:20:55 PM PDT 24
Peak memory 208508 kb
Host smart-491d823b-b2ee-4b87-a865-49c27266f261
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832442041 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2832442041
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.509076337
Short name T115
Test name
Test status
Simulation time 63777902 ps
CPU time 0.76 seconds
Started Jun 26 06:20:47 PM PDT 24
Finished Jun 26 06:20:49 PM PDT 24
Peak memory 200116 kb
Host smart-a77d036a-4f2a-416e-90b4-8065fb9c804a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509076337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.509076337
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2835033918
Short name T108
Test name
Test status
Simulation time 220119262 ps
CPU time 1.52 seconds
Started Jun 26 06:20:50 PM PDT 24
Finished Jun 26 06:20:53 PM PDT 24
Peak memory 200308 kb
Host smart-5743ddad-5e14-46cc-a6ed-c4caf48abb0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835033918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2835033918
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1565576998
Short name T595
Test name
Test status
Simulation time 167571814 ps
CPU time 2.4 seconds
Started Jun 26 06:20:51 PM PDT 24
Finished Jun 26 06:20:55 PM PDT 24
Peak memory 212008 kb
Host smart-c154fb96-71de-47ef-ae5f-50f52305a4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565576998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1565576998
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2907854966
Short name T566
Test name
Test status
Simulation time 189981180 ps
CPU time 1.21 seconds
Started Jun 26 06:20:48 PM PDT 24
Finished Jun 26 06:20:50 PM PDT 24
Peak memory 208596 kb
Host smart-897e76e1-ccf2-412b-8334-754420570fdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907854966 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2907854966
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.48559327
Short name T576
Test name
Test status
Simulation time 72705135 ps
CPU time 0.8 seconds
Started Jun 26 06:20:50 PM PDT 24
Finished Jun 26 06:20:53 PM PDT 24
Peak memory 200204 kb
Host smart-31e286a1-05ec-4795-98c5-7042e11e87e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48559327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.48559327
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2138849623
Short name T113
Test name
Test status
Simulation time 82369352 ps
CPU time 1.02 seconds
Started Jun 26 06:20:50 PM PDT 24
Finished Jun 26 06:20:53 PM PDT 24
Peak memory 200264 kb
Host smart-5b4ea2a8-fdcd-449e-9f3f-1aad538faa65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138849623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2138849623
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1844267697
Short name T579
Test name
Test status
Simulation time 446403250 ps
CPU time 3.35 seconds
Started Jun 26 06:20:54 PM PDT 24
Finished Jun 26 06:20:58 PM PDT 24
Peak memory 208572 kb
Host smart-daf1c613-f6a8-402f-b659-a9087ca5ad74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844267697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1844267697
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2110482592
Short name T72
Test name
Test status
Simulation time 505201380 ps
CPU time 1.92 seconds
Started Jun 26 06:20:51 PM PDT 24
Finished Jun 26 06:20:55 PM PDT 24
Peak memory 200468 kb
Host smart-09be57cd-4886-4124-b9c6-d311a73deccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110482592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2110482592
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1448011437
Short name T313
Test name
Test status
Simulation time 63118305 ps
CPU time 0.75 seconds
Started Jun 26 06:21:11 PM PDT 24
Finished Jun 26 06:21:13 PM PDT 24
Peak memory 199888 kb
Host smart-901704e5-24a0-4194-bf7c-f57d44e9d540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448011437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1448011437
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2062338562
Short name T64
Test name
Test status
Simulation time 1887875625 ps
CPU time 7.24 seconds
Started Jun 26 06:21:10 PM PDT 24
Finished Jun 26 06:21:18 PM PDT 24
Peak memory 217460 kb
Host smart-2f02d4a5-ee33-431b-8823-59eb40600883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062338562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2062338562
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2750967972
Short name T142
Test name
Test status
Simulation time 244568724 ps
CPU time 1.08 seconds
Started Jun 26 06:21:14 PM PDT 24
Finished Jun 26 06:21:16 PM PDT 24
Peak memory 217356 kb
Host smart-3bf032aa-a318-49eb-94b9-f20f793d0358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750967972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2750967972
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.40362127
Short name T447
Test name
Test status
Simulation time 105245221 ps
CPU time 0.81 seconds
Started Jun 26 06:21:14 PM PDT 24
Finished Jun 26 06:21:16 PM PDT 24
Peak memory 199800 kb
Host smart-b54e143c-e438-433c-bf4f-7f8d95d44aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40362127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.40362127
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3908986685
Short name T11
Test name
Test status
Simulation time 1260709599 ps
CPU time 4.93 seconds
Started Jun 26 06:21:12 PM PDT 24
Finished Jun 26 06:21:18 PM PDT 24
Peak memory 200352 kb
Host smart-e43e7f28-8c67-459c-81e2-9e9e3bc08fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908986685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3908986685
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1687943021
Short name T78
Test name
Test status
Simulation time 16706295275 ps
CPU time 24.28 seconds
Started Jun 26 06:21:09 PM PDT 24
Finished Jun 26 06:21:34 PM PDT 24
Peak memory 217216 kb
Host smart-774cb9b0-14da-47b6-b6ab-0db65518e0b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687943021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1687943021
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1519288367
Short name T189
Test name
Test status
Simulation time 159075007 ps
CPU time 1.11 seconds
Started Jun 26 06:21:12 PM PDT 24
Finished Jun 26 06:21:14 PM PDT 24
Peak memory 200088 kb
Host smart-ab3f2cdd-d823-4301-bb5e-7ab7f2d59516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519288367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1519288367
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.588839045
Short name T222
Test name
Test status
Simulation time 109373989 ps
CPU time 1.16 seconds
Started Jun 26 06:21:11 PM PDT 24
Finished Jun 26 06:21:14 PM PDT 24
Peak memory 200296 kb
Host smart-7252231a-018f-4acb-be56-06b3b4844903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588839045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.588839045
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.4096420844
Short name T293
Test name
Test status
Simulation time 6597667673 ps
CPU time 21.96 seconds
Started Jun 26 06:21:10 PM PDT 24
Finished Jun 26 06:21:33 PM PDT 24
Peak memory 208608 kb
Host smart-9bbb9d78-6f0d-49a0-998c-381e68f086c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096420844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.4096420844
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.489817599
Short name T205
Test name
Test status
Simulation time 125194708 ps
CPU time 1.54 seconds
Started Jun 26 06:21:13 PM PDT 24
Finished Jun 26 06:21:15 PM PDT 24
Peak memory 200136 kb
Host smart-d6d7d0ea-f42d-48c9-ba2b-1597c260de56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489817599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.489817599
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1399880402
Short name T451
Test name
Test status
Simulation time 117327507 ps
CPU time 1.07 seconds
Started Jun 26 06:21:12 PM PDT 24
Finished Jun 26 06:21:14 PM PDT 24
Peak memory 200096 kb
Host smart-cbe79dcc-b6a2-4cb5-991c-db282a392e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399880402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1399880402
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1562013643
Short name T203
Test name
Test status
Simulation time 71989908 ps
CPU time 0.83 seconds
Started Jun 26 06:21:14 PM PDT 24
Finished Jun 26 06:21:16 PM PDT 24
Peak memory 199836 kb
Host smart-08a17a9c-9ff4-4635-babf-771ab3e57b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562013643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1562013643
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3746127268
Short name T265
Test name
Test status
Simulation time 1215825832 ps
CPU time 5.9 seconds
Started Jun 26 06:21:13 PM PDT 24
Finished Jun 26 06:21:20 PM PDT 24
Peak memory 217400 kb
Host smart-739cea29-b176-4be7-9d19-760a87af0e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746127268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3746127268
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2707421458
Short name T538
Test name
Test status
Simulation time 244825056 ps
CPU time 1.15 seconds
Started Jun 26 06:21:12 PM PDT 24
Finished Jun 26 06:21:15 PM PDT 24
Peak memory 217348 kb
Host smart-290bfa0c-3f67-4bd8-85ac-67935ee1543a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707421458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2707421458
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.990503377
Short name T364
Test name
Test status
Simulation time 194832970 ps
CPU time 0.92 seconds
Started Jun 26 06:21:11 PM PDT 24
Finished Jun 26 06:21:13 PM PDT 24
Peak memory 199876 kb
Host smart-201103ef-1fee-4a0b-b597-3c109a833aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990503377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.990503377
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1446119178
Short name T535
Test name
Test status
Simulation time 801211126 ps
CPU time 4.47 seconds
Started Jun 26 06:21:09 PM PDT 24
Finished Jun 26 06:21:15 PM PDT 24
Peak memory 200348 kb
Host smart-a07713ca-46da-4857-a8d3-d27b64c60191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446119178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1446119178
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.4129192189
Short name T81
Test name
Test status
Simulation time 8298882229 ps
CPU time 15.77 seconds
Started Jun 26 06:21:10 PM PDT 24
Finished Jun 26 06:21:27 PM PDT 24
Peak memory 217024 kb
Host smart-fe072512-e5a3-47d1-860b-f33ade3b1418
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129192189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4129192189
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1209117019
Short name T434
Test name
Test status
Simulation time 102286388 ps
CPU time 0.99 seconds
Started Jun 26 06:21:11 PM PDT 24
Finished Jun 26 06:21:13 PM PDT 24
Peak memory 199956 kb
Host smart-06bf83d6-ce0f-43ff-9be7-533a132e6899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209117019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1209117019
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3618380402
Short name T141
Test name
Test status
Simulation time 198910036 ps
CPU time 1.4 seconds
Started Jun 26 06:21:11 PM PDT 24
Finished Jun 26 06:21:14 PM PDT 24
Peak memory 200284 kb
Host smart-ebc75018-ca64-46f0-9595-3fa374d2a2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618380402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3618380402
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2316233911
Short name T509
Test name
Test status
Simulation time 2477392677 ps
CPU time 10.17 seconds
Started Jun 26 06:21:10 PM PDT 24
Finished Jun 26 06:21:22 PM PDT 24
Peak memory 200364 kb
Host smart-9d49dede-d583-479a-bc83-4e817f7b48c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316233911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2316233911
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.248999143
Short name T388
Test name
Test status
Simulation time 287159070 ps
CPU time 2.12 seconds
Started Jun 26 06:21:13 PM PDT 24
Finished Jun 26 06:21:16 PM PDT 24
Peak memory 200092 kb
Host smart-95dcf8c0-7b2b-4eb7-b8d2-a5a1b5a7e300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248999143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.248999143
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2640241029
Short name T468
Test name
Test status
Simulation time 178206434 ps
CPU time 1.24 seconds
Started Jun 26 06:21:09 PM PDT 24
Finished Jun 26 06:21:11 PM PDT 24
Peak memory 200092 kb
Host smart-4b9d1245-78e0-4663-a764-84351e54f52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640241029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2640241029
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.948907756
Short name T377
Test name
Test status
Simulation time 66195122 ps
CPU time 0.74 seconds
Started Jun 26 06:21:31 PM PDT 24
Finished Jun 26 06:21:32 PM PDT 24
Peak memory 199864 kb
Host smart-719116f7-5342-4088-8788-a8b7656f8698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948907756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.948907756
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1627581163
Short name T40
Test name
Test status
Simulation time 2360091718 ps
CPU time 8.14 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:21:44 PM PDT 24
Peak memory 221772 kb
Host smart-c234a635-9c85-49c1-aea3-990b2c1ec019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627581163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1627581163
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1922018260
Short name T320
Test name
Test status
Simulation time 253648826 ps
CPU time 1.1 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:21:37 PM PDT 24
Peak memory 217384 kb
Host smart-7746eb06-bdb8-4a49-9be4-cfe9074a4745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922018260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1922018260
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3690895852
Short name T232
Test name
Test status
Simulation time 106488202 ps
CPU time 0.77 seconds
Started Jun 26 06:21:33 PM PDT 24
Finished Jun 26 06:21:35 PM PDT 24
Peak memory 199924 kb
Host smart-3cc92a86-b435-4e82-803c-c62f9d74dc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690895852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3690895852
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3706773715
Short name T482
Test name
Test status
Simulation time 1371296218 ps
CPU time 5.49 seconds
Started Jun 26 06:21:31 PM PDT 24
Finished Jun 26 06:21:38 PM PDT 24
Peak memory 200348 kb
Host smart-89fee742-1322-4158-b9a6-cc04680035ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706773715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3706773715
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.853692182
Short name T342
Test name
Test status
Simulation time 116442095 ps
CPU time 1 seconds
Started Jun 26 06:21:33 PM PDT 24
Finished Jun 26 06:21:36 PM PDT 24
Peak memory 200104 kb
Host smart-9cad0fbf-edae-43b8-bd51-0d174e565cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853692182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.853692182
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.4185146234
Short name T517
Test name
Test status
Simulation time 234150103 ps
CPU time 1.48 seconds
Started Jun 26 06:21:31 PM PDT 24
Finished Jun 26 06:21:34 PM PDT 24
Peak memory 200272 kb
Host smart-d4bf80c2-a8fa-44d3-aa59-43adbd15fc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185146234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.4185146234
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3010508062
Short name T184
Test name
Test status
Simulation time 7605591867 ps
CPU time 36.43 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:22:12 PM PDT 24
Peak memory 208416 kb
Host smart-6d2bf9ef-608a-4899-9ce1-d74afb37ed80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010508062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3010508062
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3481569259
Short name T58
Test name
Test status
Simulation time 320530006 ps
CPU time 2.18 seconds
Started Jun 26 06:21:32 PM PDT 24
Finished Jun 26 06:21:36 PM PDT 24
Peak memory 200292 kb
Host smart-ce782d1a-714b-4dff-98aa-64495ab208df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481569259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3481569259
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3586333797
Short name T378
Test name
Test status
Simulation time 160442101 ps
CPU time 1.11 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:21:37 PM PDT 24
Peak memory 200096 kb
Host smart-95232b6d-5b40-4544-9293-6ed5f3dba27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586333797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3586333797
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2695301194
Short name T215
Test name
Test status
Simulation time 64029193 ps
CPU time 0.75 seconds
Started Jun 26 06:21:36 PM PDT 24
Finished Jun 26 06:21:38 PM PDT 24
Peak memory 199788 kb
Host smart-d557ed16-4af1-4f65-bf57-7d801d60b3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695301194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2695301194
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.4265919591
Short name T382
Test name
Test status
Simulation time 1219497164 ps
CPU time 5.61 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:21:41 PM PDT 24
Peak memory 217516 kb
Host smart-7b171948-42bf-4afd-b0d0-b04a6c5185af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265919591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.4265919591
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.293879544
Short name T282
Test name
Test status
Simulation time 244742223 ps
CPU time 1.15 seconds
Started Jun 26 06:21:36 PM PDT 24
Finished Jun 26 06:21:39 PM PDT 24
Peak memory 217480 kb
Host smart-db23522b-aa3a-4b54-a478-1e409bd6b34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293879544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.293879544
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4081556048
Short name T297
Test name
Test status
Simulation time 1054125061 ps
CPU time 4.86 seconds
Started Jun 26 06:21:38 PM PDT 24
Finished Jun 26 06:21:44 PM PDT 24
Peak memory 199744 kb
Host smart-d394c375-2e14-4156-be2a-7dc66551096e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081556048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4081556048
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.62939451
Short name T494
Test name
Test status
Simulation time 128116994 ps
CPU time 1.24 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:21:37 PM PDT 24
Peak memory 200316 kb
Host smart-63b22f9c-846c-44fa-bc99-2a04a0c1084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62939451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.62939451
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1301663034
Short name T208
Test name
Test status
Simulation time 5390865255 ps
CPU time 27.53 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:22:03 PM PDT 24
Peak memory 200456 kb
Host smart-403fd98d-664c-4128-bfa9-0c0228def360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301663034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1301663034
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2808655377
Short name T438
Test name
Test status
Simulation time 152416005 ps
CPU time 1.88 seconds
Started Jun 26 06:21:33 PM PDT 24
Finished Jun 26 06:21:36 PM PDT 24
Peak memory 200068 kb
Host smart-c1b5fbb5-671d-41fa-9b26-736301a90e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808655377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2808655377
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2182530489
Short name T426
Test name
Test status
Simulation time 199830899 ps
CPU time 1.2 seconds
Started Jun 26 06:21:37 PM PDT 24
Finished Jun 26 06:21:39 PM PDT 24
Peak memory 200076 kb
Host smart-74572642-9b1b-472f-94dc-0b0f030b364d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182530489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2182530489
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.590962908
Short name T273
Test name
Test status
Simulation time 70288491 ps
CPU time 0.76 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:21:37 PM PDT 24
Peak memory 199876 kb
Host smart-6dbaf47c-6003-4bfd-a3bb-dd9ba4fe2dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590962908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.590962908
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2666167556
Short name T65
Test name
Test status
Simulation time 1220216520 ps
CPU time 5.59 seconds
Started Jun 26 06:21:36 PM PDT 24
Finished Jun 26 06:21:43 PM PDT 24
Peak memory 217756 kb
Host smart-e7d416fe-1d34-4ff5-9e4e-6f192126c364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666167556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2666167556
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2012393028
Short name T267
Test name
Test status
Simulation time 244076337 ps
CPU time 1.16 seconds
Started Jun 26 06:21:37 PM PDT 24
Finished Jun 26 06:21:39 PM PDT 24
Peak memory 217368 kb
Host smart-7cd24531-300b-4878-9d6f-0c804ce1d15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012393028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2012393028
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1873293468
Short name T6
Test name
Test status
Simulation time 78114009 ps
CPU time 0.75 seconds
Started Jun 26 06:21:33 PM PDT 24
Finished Jun 26 06:21:35 PM PDT 24
Peak memory 199912 kb
Host smart-f8e4e479-f941-48c3-9570-5b3b0c6947e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873293468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1873293468
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2700087278
Short name T345
Test name
Test status
Simulation time 1665799629 ps
CPU time 7.63 seconds
Started Jun 26 06:21:33 PM PDT 24
Finished Jun 26 06:21:43 PM PDT 24
Peak memory 200364 kb
Host smart-f4956428-4f21-4227-94e3-30038c63151f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700087278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2700087278
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.817459524
Short name T391
Test name
Test status
Simulation time 153398981 ps
CPU time 1.11 seconds
Started Jun 26 06:21:32 PM PDT 24
Finished Jun 26 06:21:35 PM PDT 24
Peak memory 200048 kb
Host smart-4cd4bc71-e9e9-48b8-b79e-dc060f94def5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817459524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.817459524
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3980329746
Short name T292
Test name
Test status
Simulation time 256280763 ps
CPU time 1.59 seconds
Started Jun 26 06:21:30 PM PDT 24
Finished Jun 26 06:21:33 PM PDT 24
Peak memory 200300 kb
Host smart-ef16f36a-499a-4fed-b724-28ee2a411394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980329746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3980329746
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3218670881
Short name T366
Test name
Test status
Simulation time 294068229 ps
CPU time 2.1 seconds
Started Jun 26 06:21:35 PM PDT 24
Finished Jun 26 06:21:39 PM PDT 24
Peak memory 200276 kb
Host smart-e76207bb-0d6b-4eec-9549-f3109bc55ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218670881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3218670881
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.118062369
Short name T523
Test name
Test status
Simulation time 144319177 ps
CPU time 1.81 seconds
Started Jun 26 06:21:30 PM PDT 24
Finished Jun 26 06:21:33 PM PDT 24
Peak memory 200040 kb
Host smart-24cf97ab-f61a-42ee-8aff-76c58e3b4cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118062369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.118062369
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3147375209
Short name T272
Test name
Test status
Simulation time 233625561 ps
CPU time 1.35 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:21:37 PM PDT 24
Peak memory 200104 kb
Host smart-cff8091c-bafb-4cf0-83be-b224bc1d9db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147375209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3147375209
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.4244794000
Short name T387
Test name
Test status
Simulation time 67035766 ps
CPU time 0.79 seconds
Started Jun 26 06:21:41 PM PDT 24
Finished Jun 26 06:21:43 PM PDT 24
Peak memory 199888 kb
Host smart-46020c3a-6121-4719-b7a9-9208c9621bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244794000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.4244794000
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2681677215
Short name T409
Test name
Test status
Simulation time 1214632029 ps
CPU time 5.95 seconds
Started Jun 26 06:21:56 PM PDT 24
Finished Jun 26 06:22:05 PM PDT 24
Peak memory 221648 kb
Host smart-78d48b3c-7530-4faf-8fc9-53af7514fcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681677215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2681677215
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3014285021
Short name T532
Test name
Test status
Simulation time 244665243 ps
CPU time 1.15 seconds
Started Jun 26 06:21:43 PM PDT 24
Finished Jun 26 06:21:45 PM PDT 24
Peak memory 217412 kb
Host smart-d145717c-f9df-4fed-9ae0-e17443658916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014285021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3014285021
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2788198991
Short name T446
Test name
Test status
Simulation time 109247383 ps
CPU time 0.79 seconds
Started Jun 26 06:21:32 PM PDT 24
Finished Jun 26 06:21:35 PM PDT 24
Peak memory 199856 kb
Host smart-73fa6c64-33d0-49d9-82c7-fd9ec2c69c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788198991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2788198991
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.4037405483
Short name T353
Test name
Test status
Simulation time 1952170122 ps
CPU time 7 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:21:43 PM PDT 24
Peak memory 200340 kb
Host smart-6299446b-a0ec-4ee2-b939-6d2ebca79fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037405483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.4037405483
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2045695078
Short name T528
Test name
Test status
Simulation time 101772732 ps
CPU time 1.01 seconds
Started Jun 26 06:21:42 PM PDT 24
Finished Jun 26 06:21:45 PM PDT 24
Peak memory 200044 kb
Host smart-bb922ce3-fba2-426d-a37f-9b43337eb66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045695078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2045695078
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3714034869
Short name T513
Test name
Test status
Simulation time 128855855 ps
CPU time 1.2 seconds
Started Jun 26 06:21:32 PM PDT 24
Finished Jun 26 06:21:35 PM PDT 24
Peak memory 200244 kb
Host smart-9ea465a5-eaf6-4efa-ae3f-8a3f6f4e5823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714034869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3714034869
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.765190523
Short name T476
Test name
Test status
Simulation time 8785648091 ps
CPU time 34.24 seconds
Started Jun 26 06:21:42 PM PDT 24
Finished Jun 26 06:22:18 PM PDT 24
Peak memory 208668 kb
Host smart-6a15e426-5a94-4bd8-8b12-6f2825f7818c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765190523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.765190523
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3625304211
Short name T137
Test name
Test status
Simulation time 363115286 ps
CPU time 2.21 seconds
Started Jun 26 06:21:52 PM PDT 24
Finished Jun 26 06:21:55 PM PDT 24
Peak memory 208216 kb
Host smart-3c0d77c7-51f0-480d-8cc2-787a2140935d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625304211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3625304211
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.335628575
Short name T276
Test name
Test status
Simulation time 116701635 ps
CPU time 0.94 seconds
Started Jun 26 06:21:38 PM PDT 24
Finished Jun 26 06:21:40 PM PDT 24
Peak memory 199532 kb
Host smart-87ab0f46-3e8d-4c57-80da-83aa31d9fca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335628575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.335628575
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2750728998
Short name T213
Test name
Test status
Simulation time 88873047 ps
CPU time 0.86 seconds
Started Jun 26 06:21:40 PM PDT 24
Finished Jun 26 06:21:42 PM PDT 24
Peak memory 199888 kb
Host smart-08bf13e7-99c1-461c-bd99-1b57ed32af95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750728998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2750728998
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2667722030
Short name T27
Test name
Test status
Simulation time 1223752183 ps
CPU time 6.12 seconds
Started Jun 26 06:21:43 PM PDT 24
Finished Jun 26 06:21:50 PM PDT 24
Peak memory 217724 kb
Host smart-6f9513cb-8e05-43b5-a281-98619a2cd5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667722030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2667722030
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2388067242
Short name T179
Test name
Test status
Simulation time 244699957 ps
CPU time 1.09 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:21:56 PM PDT 24
Peak memory 217484 kb
Host smart-ef2e5819-2ccf-444d-9783-f22f157777da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388067242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2388067242
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.265765923
Short name T258
Test name
Test status
Simulation time 168452730 ps
CPU time 0.93 seconds
Started Jun 26 06:21:52 PM PDT 24
Finished Jun 26 06:21:53 PM PDT 24
Peak memory 199888 kb
Host smart-f7fff31a-f744-4bb4-b0e0-b7ba759ed9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265765923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.265765923
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1872950665
Short name T367
Test name
Test status
Simulation time 1182046458 ps
CPU time 5.77 seconds
Started Jun 26 06:21:56 PM PDT 24
Finished Jun 26 06:22:05 PM PDT 24
Peak memory 200348 kb
Host smart-f353ee69-fe33-432b-aed8-95dfbed3881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872950665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1872950665
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.211391165
Short name T243
Test name
Test status
Simulation time 154110602 ps
CPU time 1.11 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:00 PM PDT 24
Peak memory 200080 kb
Host smart-3cc57419-353c-437b-a723-0a35a6830806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211391165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.211391165
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3137865749
Short name T221
Test name
Test status
Simulation time 193823558 ps
CPU time 1.41 seconds
Started Jun 26 06:21:42 PM PDT 24
Finished Jun 26 06:21:45 PM PDT 24
Peak memory 200284 kb
Host smart-dd5d508d-0a50-475c-a807-c9ca6fa421f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137865749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3137865749
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3543101177
Short name T284
Test name
Test status
Simulation time 1837830002 ps
CPU time 7.69 seconds
Started Jun 26 06:21:51 PM PDT 24
Finished Jun 26 06:21:59 PM PDT 24
Peak memory 200204 kb
Host smart-bf04d8b3-8c55-418a-a799-720bec647a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543101177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3543101177
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1691474843
Short name T256
Test name
Test status
Simulation time 338276488 ps
CPU time 2.21 seconds
Started Jun 26 06:21:42 PM PDT 24
Finished Jun 26 06:21:45 PM PDT 24
Peak memory 200060 kb
Host smart-ad32c291-49ac-4797-b6c2-02ac5e34783e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691474843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1691474843
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3350935833
Short name T531
Test name
Test status
Simulation time 120072225 ps
CPU time 1.1 seconds
Started Jun 26 06:21:41 PM PDT 24
Finished Jun 26 06:21:43 PM PDT 24
Peak memory 200092 kb
Host smart-3e7debe1-a0b1-444b-a3b4-ce354df85cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350935833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3350935833
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2774214707
Short name T31
Test name
Test status
Simulation time 1225951603 ps
CPU time 5.89 seconds
Started Jun 26 06:21:43 PM PDT 24
Finished Jun 26 06:21:51 PM PDT 24
Peak memory 217392 kb
Host smart-906acf0b-00b7-4992-9764-ab69180a7f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774214707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2774214707
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.4145154418
Short name T543
Test name
Test status
Simulation time 243898431 ps
CPU time 1.22 seconds
Started Jun 26 06:21:52 PM PDT 24
Finished Jun 26 06:21:53 PM PDT 24
Peak memory 217476 kb
Host smart-5197d47c-0901-41c9-85a7-2ad1c504b1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145154418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.4145154418
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.252903749
Short name T465
Test name
Test status
Simulation time 154366950 ps
CPU time 0.89 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:21:58 PM PDT 24
Peak memory 199908 kb
Host smart-2936ff45-3bdf-455a-9db1-3f36d7f06162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252903749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.252903749
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3726847246
Short name T287
Test name
Test status
Simulation time 1553037592 ps
CPU time 5.96 seconds
Started Jun 26 06:21:52 PM PDT 24
Finished Jun 26 06:21:59 PM PDT 24
Peak memory 200308 kb
Host smart-7a3cccd6-60d3-4231-b5e9-323fa2e253fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726847246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3726847246
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2871812012
Short name T408
Test name
Test status
Simulation time 156734296 ps
CPU time 1.21 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:21:57 PM PDT 24
Peak memory 200312 kb
Host smart-f19526cb-19da-4b80-b915-4547c175d87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871812012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2871812012
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3720823890
Short name T153
Test name
Test status
Simulation time 120407255 ps
CPU time 1.19 seconds
Started Jun 26 06:21:40 PM PDT 24
Finished Jun 26 06:21:42 PM PDT 24
Peak memory 200280 kb
Host smart-0014d0aa-99cd-46eb-8fbe-33915bf3c138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720823890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3720823890
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.124616480
Short name T336
Test name
Test status
Simulation time 311247863 ps
CPU time 2.41 seconds
Started Jun 26 06:21:45 PM PDT 24
Finished Jun 26 06:21:48 PM PDT 24
Peak memory 200500 kb
Host smart-4c40316f-123c-427f-bbdc-970e78b4e168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124616480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.124616480
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1210805208
Short name T87
Test name
Test status
Simulation time 139236656 ps
CPU time 2.07 seconds
Started Jun 26 06:21:43 PM PDT 24
Finished Jun 26 06:21:46 PM PDT 24
Peak memory 200104 kb
Host smart-0efd0d69-c729-4a92-89e3-febc63396210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210805208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1210805208
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.183668975
Short name T202
Test name
Test status
Simulation time 140406489 ps
CPU time 1.08 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:21:59 PM PDT 24
Peak memory 200100 kb
Host smart-3f6cd008-7fc9-428c-868a-91705a32d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183668975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.183668975
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2761070290
Short name T298
Test name
Test status
Simulation time 71153646 ps
CPU time 0.81 seconds
Started Jun 26 06:21:51 PM PDT 24
Finished Jun 26 06:21:53 PM PDT 24
Peak memory 199872 kb
Host smart-95970c0d-7f57-4452-9253-9880a5ec69e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761070290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2761070290
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.505979860
Short name T54
Test name
Test status
Simulation time 1895549157 ps
CPU time 7.73 seconds
Started Jun 26 06:21:41 PM PDT 24
Finished Jun 26 06:21:50 PM PDT 24
Peak memory 221628 kb
Host smart-45a318d7-b299-49c6-8694-b28b5b36d271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505979860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.505979860
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.346156831
Short name T242
Test name
Test status
Simulation time 244625152 ps
CPU time 1.08 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:21:59 PM PDT 24
Peak memory 217432 kb
Host smart-999b631c-288d-4088-b40e-9adaa4b360aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346156831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.346156831
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2434350335
Short name T233
Test name
Test status
Simulation time 139691532 ps
CPU time 0.85 seconds
Started Jun 26 06:21:41 PM PDT 24
Finished Jun 26 06:21:43 PM PDT 24
Peak memory 199900 kb
Host smart-254f662a-4dba-4fe0-a464-b0b647b7c693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434350335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2434350335
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.826915237
Short name T199
Test name
Test status
Simulation time 868655705 ps
CPU time 4.6 seconds
Started Jun 26 06:21:41 PM PDT 24
Finished Jun 26 06:21:47 PM PDT 24
Peak memory 200368 kb
Host smart-0c9ca210-95ad-4bee-b4e9-c4df97be4271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826915237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.826915237
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.815536157
Short name T422
Test name
Test status
Simulation time 147828378 ps
CPU time 1.1 seconds
Started Jun 26 06:21:43 PM PDT 24
Finished Jun 26 06:21:46 PM PDT 24
Peak memory 200092 kb
Host smart-3fdc2ed9-64c6-4660-8bf0-01a65b5c0bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815536157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.815536157
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.693646497
Short name T220
Test name
Test status
Simulation time 116039705 ps
CPU time 1.18 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:21:56 PM PDT 24
Peak memory 200284 kb
Host smart-38af4fe7-fc53-4102-877b-b231fa8cae69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693646497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.693646497
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.824812278
Short name T194
Test name
Test status
Simulation time 8921724129 ps
CPU time 37.09 seconds
Started Jun 26 06:21:40 PM PDT 24
Finished Jun 26 06:22:18 PM PDT 24
Peak memory 208608 kb
Host smart-29d5ccc5-6113-4f07-9131-242d5be9e722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824812278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.824812278
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3217719784
Short name T415
Test name
Test status
Simulation time 391623032 ps
CPU time 2.58 seconds
Started Jun 26 06:21:51 PM PDT 24
Finished Jun 26 06:21:54 PM PDT 24
Peak memory 199988 kb
Host smart-f482d2e3-dc05-490a-a6de-e82d812f5892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217719784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3217719784
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3989751225
Short name T398
Test name
Test status
Simulation time 290493961 ps
CPU time 1.6 seconds
Started Jun 26 06:21:40 PM PDT 24
Finished Jun 26 06:21:42 PM PDT 24
Peak memory 200252 kb
Host smart-73a97a66-04ef-4e40-8d68-5a2eb144d947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989751225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3989751225
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2543332085
Short name T4
Test name
Test status
Simulation time 71071200 ps
CPU time 0.83 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:21:58 PM PDT 24
Peak memory 199888 kb
Host smart-c1499c27-1bec-4ba5-8438-bbdbb2e06f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543332085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2543332085
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1257479984
Short name T32
Test name
Test status
Simulation time 2366013131 ps
CPU time 8.12 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 217160 kb
Host smart-8f11be78-5462-4656-9216-a33cf2241df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257479984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1257479984
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2452763857
Short name T154
Test name
Test status
Simulation time 244366686 ps
CPU time 1.24 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:00 PM PDT 24
Peak memory 217372 kb
Host smart-8e6bc525-888c-4ee3-9b4f-1fd18a042c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452763857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2452763857
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2248665435
Short name T368
Test name
Test status
Simulation time 190664922 ps
CPU time 0.87 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:21:57 PM PDT 24
Peak memory 199924 kb
Host smart-886ed598-e8bd-4bef-8d30-d02bf3bef284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248665435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2248665435
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.4123244897
Short name T442
Test name
Test status
Simulation time 759879568 ps
CPU time 4.34 seconds
Started Jun 26 06:21:43 PM PDT 24
Finished Jun 26 06:21:49 PM PDT 24
Peak memory 200364 kb
Host smart-ddcdfc7f-778a-4fcd-a902-4ca12603ebd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123244897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.4123244897
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2279146640
Short name T441
Test name
Test status
Simulation time 100901736 ps
CPU time 1.08 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:21:56 PM PDT 24
Peak memory 200096 kb
Host smart-a7898db0-71da-420a-b675-eb35e47a78c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279146640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2279146640
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.297427837
Short name T420
Test name
Test status
Simulation time 127910576 ps
CPU time 1.23 seconds
Started Jun 26 06:21:45 PM PDT 24
Finished Jun 26 06:21:47 PM PDT 24
Peak memory 200276 kb
Host smart-f622ff4b-77b9-45d8-b8ea-35104ff25145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297427837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.297427837
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3721758765
Short name T244
Test name
Test status
Simulation time 3947313993 ps
CPU time 19.6 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:17 PM PDT 24
Peak memory 208604 kb
Host smart-cd6731ac-f002-48a5-b9df-67bedd9a19f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721758765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3721758765
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4271957677
Short name T289
Test name
Test status
Simulation time 435906062 ps
CPU time 2.41 seconds
Started Jun 26 06:21:51 PM PDT 24
Finished Jun 26 06:21:54 PM PDT 24
Peak memory 200092 kb
Host smart-1473a9f0-64dd-42e0-a3a5-c7b9a93e1960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271957677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4271957677
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2559501730
Short name T262
Test name
Test status
Simulation time 84360523 ps
CPU time 0.83 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:21:56 PM PDT 24
Peak memory 200100 kb
Host smart-bc65ea8f-d9ca-4469-82f9-f86de7be5c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559501730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2559501730
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3240209948
Short name T351
Test name
Test status
Simulation time 73486732 ps
CPU time 0.79 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:21:56 PM PDT 24
Peak memory 199856 kb
Host smart-9b44b872-4246-432b-94b7-e4656b75e0ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240209948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3240209948
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.4258677239
Short name T452
Test name
Test status
Simulation time 1230209805 ps
CPU time 5.81 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:04 PM PDT 24
Peak memory 217680 kb
Host smart-580444d1-0ab8-48a7-ad4c-7a545cd897da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258677239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.4258677239
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2935369586
Short name T271
Test name
Test status
Simulation time 244483363 ps
CPU time 1.05 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:21:59 PM PDT 24
Peak memory 217400 kb
Host smart-fdf4f592-af12-4b20-92aa-6938da348035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935369586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2935369586
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3788250437
Short name T397
Test name
Test status
Simulation time 146856728 ps
CPU time 0.84 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:21:58 PM PDT 24
Peak memory 199888 kb
Host smart-626ebab7-9de6-4281-b0d2-7cba9b92992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788250437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3788250437
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3174600278
Short name T301
Test name
Test status
Simulation time 1234370702 ps
CPU time 5.74 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 200384 kb
Host smart-90ceebb1-8f51-4655-818d-c999cac3ec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174600278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3174600278
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1004047991
Short name T217
Test name
Test status
Simulation time 177028385 ps
CPU time 1.25 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:21:55 PM PDT 24
Peak memory 200096 kb
Host smart-58a1edaf-93ca-46c1-b8cc-e86292636d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004047991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1004047991
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1862514979
Short name T503
Test name
Test status
Simulation time 229439936 ps
CPU time 1.71 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:21:59 PM PDT 24
Peak memory 200272 kb
Host smart-42869574-f100-4df3-b4e3-f206db725346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862514979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1862514979
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2039678907
Short name T102
Test name
Test status
Simulation time 1976181439 ps
CPU time 8.84 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:22:06 PM PDT 24
Peak memory 200356 kb
Host smart-524166c7-cdf5-4b54-ba93-b054dad5079a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039678907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2039678907
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.465866529
Short name T60
Test name
Test status
Simulation time 260828864 ps
CPU time 1.78 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:00 PM PDT 24
Peak memory 200072 kb
Host smart-3454b6aa-11bc-417f-91ff-b91fda3a6017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465866529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.465866529
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1393777908
Short name T231
Test name
Test status
Simulation time 155868234 ps
CPU time 1.28 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:21:56 PM PDT 24
Peak memory 200032 kb
Host smart-23587184-6bac-4131-9f2d-347cdaba95a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393777908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1393777908
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.339028955
Short name T433
Test name
Test status
Simulation time 59278451 ps
CPU time 0.73 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:21:58 PM PDT 24
Peak memory 199804 kb
Host smart-01424d05-a417-473e-a411-07eb11340455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339028955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.339028955
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3165527435
Short name T423
Test name
Test status
Simulation time 1219037346 ps
CPU time 5.93 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:05 PM PDT 24
Peak memory 217740 kb
Host smart-b8355b6e-bc3e-46aa-a0b8-ccae66286704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165527435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3165527435
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.72890046
Short name T240
Test name
Test status
Simulation time 243986359 ps
CPU time 1.15 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:21:56 PM PDT 24
Peak memory 217484 kb
Host smart-4f5585a4-79e3-4ed2-b9ab-7b03900a6073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72890046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.72890046
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2577573277
Short name T537
Test name
Test status
Simulation time 104819853 ps
CPU time 0.76 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:21:57 PM PDT 24
Peak memory 199924 kb
Host smart-96cc4fb6-bf82-4eb1-98af-b2758ecd0016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577573277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2577573277
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3267845227
Short name T467
Test name
Test status
Simulation time 962711757 ps
CPU time 4.55 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:21:59 PM PDT 24
Peak memory 200340 kb
Host smart-637795c5-78fb-4d8b-9aa3-64d549fefe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267845227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3267845227
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3834348811
Short name T322
Test name
Test status
Simulation time 141989592 ps
CPU time 1.17 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:21:58 PM PDT 24
Peak memory 200056 kb
Host smart-9d8a50c7-e4f3-438e-b310-d9a39bfc0b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834348811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3834348811
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2559969749
Short name T241
Test name
Test status
Simulation time 120775296 ps
CPU time 1.23 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:00 PM PDT 24
Peak memory 200280 kb
Host smart-414e9f43-6b7d-42a3-aa7c-deeb97657601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559969749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2559969749
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1407666367
Short name T472
Test name
Test status
Simulation time 129483566 ps
CPU time 1.72 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:00 PM PDT 24
Peak memory 200092 kb
Host smart-96f514e1-4ddd-4ae7-b1f0-9591b8c888bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407666367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1407666367
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3956385878
Short name T236
Test name
Test status
Simulation time 68666046 ps
CPU time 0.75 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:21:58 PM PDT 24
Peak memory 200088 kb
Host smart-bf6c0d98-db1d-4b17-b3ba-b115fa0f93ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956385878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3956385878
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2303389127
Short name T365
Test name
Test status
Simulation time 69030687 ps
CPU time 0.84 seconds
Started Jun 26 06:21:21 PM PDT 24
Finished Jun 26 06:21:23 PM PDT 24
Peak memory 199888 kb
Host smart-524db5bc-c123-4f40-bc2b-b4c8255ac807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303389127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2303389127
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1803651452
Short name T413
Test name
Test status
Simulation time 2376503919 ps
CPU time 8.29 seconds
Started Jun 26 06:21:18 PM PDT 24
Finished Jun 26 06:21:27 PM PDT 24
Peak memory 217852 kb
Host smart-d632fca5-8029-4b57-bdcb-1414794d1e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803651452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1803651452
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.765067922
Short name T406
Test name
Test status
Simulation time 244248135 ps
CPU time 1.08 seconds
Started Jun 26 06:21:21 PM PDT 24
Finished Jun 26 06:21:24 PM PDT 24
Peak memory 217312 kb
Host smart-22aa8d0a-8f9b-4985-be90-797dd4c10cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765067922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.765067922
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2904006495
Short name T470
Test name
Test status
Simulation time 132771949 ps
CPU time 0.86 seconds
Started Jun 26 06:21:18 PM PDT 24
Finished Jun 26 06:21:20 PM PDT 24
Peak memory 199908 kb
Host smart-b158e61f-5297-45e3-a234-58810fe90a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904006495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2904006495
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2850693075
Short name T402
Test name
Test status
Simulation time 1693504968 ps
CPU time 5.61 seconds
Started Jun 26 06:21:19 PM PDT 24
Finished Jun 26 06:21:27 PM PDT 24
Peak memory 200288 kb
Host smart-70502ac4-4c43-4b54-bbd9-80e1314dd814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850693075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2850693075
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.4203466063
Short name T77
Test name
Test status
Simulation time 16515876951 ps
CPU time 34.13 seconds
Started Jun 26 06:21:18 PM PDT 24
Finished Jun 26 06:21:53 PM PDT 24
Peak memory 217180 kb
Host smart-4df9ab9a-9ed2-4c2a-ace4-017fb01c1160
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203466063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.4203466063
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2197755681
Short name T264
Test name
Test status
Simulation time 102534575 ps
CPU time 1.02 seconds
Started Jun 26 06:21:21 PM PDT 24
Finished Jun 26 06:21:23 PM PDT 24
Peak memory 200096 kb
Host smart-21282b78-cf24-4e7f-b6e0-0c6f560069ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197755681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2197755681
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3142309322
Short name T411
Test name
Test status
Simulation time 208166065 ps
CPU time 1.49 seconds
Started Jun 26 06:21:18 PM PDT 24
Finished Jun 26 06:21:20 PM PDT 24
Peak memory 200284 kb
Host smart-10b2505f-5132-4c13-9f31-acbad9fe70fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142309322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3142309322
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1535846713
Short name T375
Test name
Test status
Simulation time 2758255569 ps
CPU time 11.26 seconds
Started Jun 26 06:21:22 PM PDT 24
Finished Jun 26 06:21:34 PM PDT 24
Peak memory 208532 kb
Host smart-d78be980-199d-4d31-b578-be11a3f2091c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535846713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1535846713
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3969094696
Short name T150
Test name
Test status
Simulation time 371614390 ps
CPU time 2.42 seconds
Started Jun 26 06:21:19 PM PDT 24
Finished Jun 26 06:21:23 PM PDT 24
Peak memory 200036 kb
Host smart-d3b78dbe-3dfa-4b82-9dac-0d9eaacaddb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969094696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3969094696
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.4211405082
Short name T384
Test name
Test status
Simulation time 104284953 ps
CPU time 0.9 seconds
Started Jun 26 06:21:19 PM PDT 24
Finished Jun 26 06:21:21 PM PDT 24
Peak memory 200084 kb
Host smart-c98fffdb-7a53-484a-9396-475f7fccfa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211405082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.4211405082
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.131038969
Short name T164
Test name
Test status
Simulation time 56416129 ps
CPU time 0.73 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:21:59 PM PDT 24
Peak memory 199824 kb
Host smart-30c5be62-1c42-4e8f-b78f-8dce5d52a8db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131038969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.131038969
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1070141575
Short name T453
Test name
Test status
Simulation time 2349390034 ps
CPU time 8.44 seconds
Started Jun 26 06:21:58 PM PDT 24
Finished Jun 26 06:22:09 PM PDT 24
Peak memory 217840 kb
Host smart-8c4d9be2-70d8-465d-bc94-ced8404120a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070141575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1070141575
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2900083951
Short name T175
Test name
Test status
Simulation time 243862871 ps
CPU time 1.09 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:00 PM PDT 24
Peak memory 217460 kb
Host smart-2137d139-76ff-457a-88d8-2281e03a3240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900083951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2900083951
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.518895396
Short name T459
Test name
Test status
Simulation time 223318295 ps
CPU time 0.95 seconds
Started Jun 26 06:21:52 PM PDT 24
Finished Jun 26 06:21:54 PM PDT 24
Peak memory 199896 kb
Host smart-fd36ea2b-ac4b-48e1-be89-41792aec7ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518895396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.518895396
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1056705100
Short name T280
Test name
Test status
Simulation time 1370073917 ps
CPU time 5.71 seconds
Started Jun 26 06:21:53 PM PDT 24
Finished Jun 26 06:22:01 PM PDT 24
Peak memory 200352 kb
Host smart-bc44bac3-8551-4dbd-9288-6efbc3613f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056705100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1056705100
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.789043308
Short name T145
Test name
Test status
Simulation time 148612449 ps
CPU time 1.18 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:21:58 PM PDT 24
Peak memory 200064 kb
Host smart-3155433f-4cd1-454b-a47f-e95e4d34cbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789043308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.789043308
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2138589287
Short name T166
Test name
Test status
Simulation time 217202015 ps
CPU time 1.45 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:00 PM PDT 24
Peak memory 200284 kb
Host smart-b8eb652a-48c3-4f30-98dd-4bced27fee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138589287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2138589287
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.723917397
Short name T105
Test name
Test status
Simulation time 4576524557 ps
CPU time 16.79 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:22:14 PM PDT 24
Peak memory 208600 kb
Host smart-f58e98ca-4aac-458b-aada-7e06593ad606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723917397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.723917397
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.302221188
Short name T445
Test name
Test status
Simulation time 507405807 ps
CPU time 2.67 seconds
Started Jun 26 06:21:54 PM PDT 24
Finished Jun 26 06:21:59 PM PDT 24
Peak memory 200072 kb
Host smart-ff2e154d-9400-42d1-b5ff-abed81bdb714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302221188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.302221188
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3722016176
Short name T497
Test name
Test status
Simulation time 238080196 ps
CPU time 1.3 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:00 PM PDT 24
Peak memory 200064 kb
Host smart-75105419-1ac5-4c2c-9322-2bbbfeb26344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722016176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3722016176
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.873515089
Short name T178
Test name
Test status
Simulation time 78193239 ps
CPU time 0.85 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:07 PM PDT 24
Peak memory 199892 kb
Host smart-11c7325f-595c-485b-aa3d-f04e746ea762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873515089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.873515089
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1365530069
Short name T125
Test name
Test status
Simulation time 2180675463 ps
CPU time 7.72 seconds
Started Jun 26 06:21:59 PM PDT 24
Finished Jun 26 06:22:09 PM PDT 24
Peak memory 221668 kb
Host smart-a0fe27a3-4274-4dcc-b8e6-f11ccea1480c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365530069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1365530069
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.935556919
Short name T162
Test name
Test status
Simulation time 244196170 ps
CPU time 1.13 seconds
Started Jun 26 06:21:59 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 217456 kb
Host smart-6dbbbbd2-8818-463b-87b9-dbceb00184a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935556919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.935556919
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2163545389
Short name T172
Test name
Test status
Simulation time 190456484 ps
CPU time 0.97 seconds
Started Jun 26 06:21:56 PM PDT 24
Finished Jun 26 06:22:01 PM PDT 24
Peak memory 199884 kb
Host smart-5758eb31-2c23-4f88-82d3-6689e4d8a12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163545389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2163545389
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2790885989
Short name T432
Test name
Test status
Simulation time 1587540489 ps
CPU time 6.61 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:14 PM PDT 24
Peak memory 200356 kb
Host smart-d5c64213-9c94-4674-ac60-3b1f6e34578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790885989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2790885989
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3304621444
Short name T146
Test name
Test status
Simulation time 150570890 ps
CPU time 1.1 seconds
Started Jun 26 06:21:59 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 200064 kb
Host smart-3c0f9ba7-49b5-455d-b07e-ef594b4d08b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304621444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3304621444
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1843417341
Short name T160
Test name
Test status
Simulation time 117323553 ps
CPU time 1.26 seconds
Started Jun 26 06:21:57 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 200340 kb
Host smart-a590a1d0-193f-4ddb-84d2-99b878513634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843417341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1843417341
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2048098939
Short name T225
Test name
Test status
Simulation time 1968507335 ps
CPU time 9.84 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:16 PM PDT 24
Peak memory 208556 kb
Host smart-6c090144-135b-491e-b9b1-fe6583f1b55e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048098939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2048098939
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3369561590
Short name T86
Test name
Test status
Simulation time 128273932 ps
CPU time 1.71 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:10 PM PDT 24
Peak memory 200068 kb
Host smart-f237af12-c405-4f32-9a1a-e15effea5015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369561590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3369561590
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2154521667
Short name T43
Test name
Test status
Simulation time 123248082 ps
CPU time 1.11 seconds
Started Jun 26 06:21:58 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 200116 kb
Host smart-d5fef378-b53b-41bc-a0ed-157cac6fd2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154521667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2154521667
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.356046973
Short name T229
Test name
Test status
Simulation time 71153328 ps
CPU time 0.81 seconds
Started Jun 26 06:21:58 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 199876 kb
Host smart-c76a27e7-4e49-4d64-8cdd-4e4444dd507d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356046973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.356046973
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3219187038
Short name T437
Test name
Test status
Simulation time 1899718581 ps
CPU time 7.5 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:14 PM PDT 24
Peak memory 217372 kb
Host smart-a4a20065-f37b-4e37-af1c-7e20a0f4d7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219187038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3219187038
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1345224261
Short name T539
Test name
Test status
Simulation time 244614764 ps
CPU time 1.07 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:08 PM PDT 24
Peak memory 217460 kb
Host smart-2cd21df5-de04-4c5e-a8e8-988cba726870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345224261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1345224261
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2976245538
Short name T310
Test name
Test status
Simulation time 82447656 ps
CPU time 0.72 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:07 PM PDT 24
Peak memory 199896 kb
Host smart-9254d494-5595-4f2a-ba68-01ff9d60798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976245538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2976245538
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1361469210
Short name T327
Test name
Test status
Simulation time 973947331 ps
CPU time 5.09 seconds
Started Jun 26 06:21:57 PM PDT 24
Finished Jun 26 06:22:05 PM PDT 24
Peak memory 200348 kb
Host smart-a6c485b6-8a21-4ca9-9e7c-b715baf263d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361469210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1361469210
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1453903843
Short name T308
Test name
Test status
Simulation time 108618042 ps
CPU time 1.06 seconds
Started Jun 26 06:21:57 PM PDT 24
Finished Jun 26 06:22:01 PM PDT 24
Peak memory 200088 kb
Host smart-6d147f53-5acd-4aaf-a10c-c29b1f24f8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453903843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1453903843
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2416726492
Short name T418
Test name
Test status
Simulation time 225116379 ps
CPU time 1.54 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:09 PM PDT 24
Peak memory 200264 kb
Host smart-dc43d997-e996-4a11-8459-f66b0780a8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416726492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2416726492
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.49888055
Short name T458
Test name
Test status
Simulation time 185568718 ps
CPU time 1.76 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:09 PM PDT 24
Peak memory 200140 kb
Host smart-61840b81-4db3-4e3b-9ac6-85c1048e8b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49888055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.49888055
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2872893116
Short name T332
Test name
Test status
Simulation time 141738499 ps
CPU time 1.87 seconds
Started Jun 26 06:21:57 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 200076 kb
Host smart-34683a10-dd68-40c1-89bc-bafcd4dfd929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872893116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2872893116
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.305919854
Short name T419
Test name
Test status
Simulation time 170826266 ps
CPU time 1.19 seconds
Started Jun 26 06:21:57 PM PDT 24
Finished Jun 26 06:22:01 PM PDT 24
Peak memory 200024 kb
Host smart-d0ed1a9b-2b48-46d8-9f33-7f212e6a66ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305919854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.305919854
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3305023894
Short name T481
Test name
Test status
Simulation time 63487753 ps
CPU time 0.74 seconds
Started Jun 26 06:21:58 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 199860 kb
Host smart-ce624fec-48b7-4908-b7ae-2f0860e962e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305023894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3305023894
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1640965283
Short name T475
Test name
Test status
Simulation time 1214825897 ps
CPU time 5.56 seconds
Started Jun 26 06:21:59 PM PDT 24
Finished Jun 26 06:22:07 PM PDT 24
Peak memory 217460 kb
Host smart-90c3c912-2721-46ca-bb61-b6a9936c4c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640965283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1640965283
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.524808685
Short name T290
Test name
Test status
Simulation time 243784153 ps
CPU time 1.11 seconds
Started Jun 26 06:22:04 PM PDT 24
Finished Jun 26 06:22:06 PM PDT 24
Peak memory 217436 kb
Host smart-7888616d-b2c1-4601-94b6-a686b0946095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524808685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.524808685
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1768059276
Short name T372
Test name
Test status
Simulation time 168613269 ps
CPU time 0.86 seconds
Started Jun 26 06:22:03 PM PDT 24
Finished Jun 26 06:22:04 PM PDT 24
Peak memory 199888 kb
Host smart-f93ec59b-4ee0-413f-95e0-521cb85a9518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768059276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1768059276
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3216146308
Short name T98
Test name
Test status
Simulation time 1310449263 ps
CPU time 5.35 seconds
Started Jun 26 06:21:55 PM PDT 24
Finished Jun 26 06:22:04 PM PDT 24
Peak memory 200320 kb
Host smart-534c52e6-6bf3-46c9-8d19-70edf2fbff77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216146308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3216146308
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3817026230
Short name T501
Test name
Test status
Simulation time 99988179 ps
CPU time 0.98 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:10 PM PDT 24
Peak memory 200072 kb
Host smart-ad323ebc-343e-4f01-be87-7e28bcf2cbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817026230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3817026230
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3308779920
Short name T239
Test name
Test status
Simulation time 180064194 ps
CPU time 1.41 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:09 PM PDT 24
Peak memory 200268 kb
Host smart-bae4b50d-94b4-4c8f-951f-bc5c327731fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308779920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3308779920
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.532490819
Short name T534
Test name
Test status
Simulation time 8407386380 ps
CPU time 29.36 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:35 PM PDT 24
Peak memory 216748 kb
Host smart-ec169a36-4d39-490d-ab89-c5cafd29e80c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532490819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.532490819
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3171785372
Short name T168
Test name
Test status
Simulation time 534077258 ps
CPU time 2.7 seconds
Started Jun 26 06:21:58 PM PDT 24
Finished Jun 26 06:22:04 PM PDT 24
Peak memory 200060 kb
Host smart-49921fa8-b611-4c71-a284-b8a12ab0b2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171785372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3171785372
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2866015941
Short name T295
Test name
Test status
Simulation time 65787538 ps
CPU time 0.81 seconds
Started Jun 26 06:22:03 PM PDT 24
Finished Jun 26 06:22:05 PM PDT 24
Peak memory 199836 kb
Host smart-61cfc004-1403-4114-9cf0-052630d97cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866015941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2866015941
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2352584415
Short name T29
Test name
Test status
Simulation time 1907172989 ps
CPU time 7.16 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:14 PM PDT 24
Peak memory 217528 kb
Host smart-d810470a-351b-4ed9-9cd4-9a5412b4d5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352584415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2352584415
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2556595059
Short name T201
Test name
Test status
Simulation time 243329300 ps
CPU time 1.08 seconds
Started Jun 26 06:22:12 PM PDT 24
Finished Jun 26 06:22:14 PM PDT 24
Peak memory 217420 kb
Host smart-64ec7836-cf9d-4dca-9cef-3c055c0d1a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556595059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2556595059
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.72727548
Short name T329
Test name
Test status
Simulation time 175249703 ps
CPU time 0.89 seconds
Started Jun 26 06:22:02 PM PDT 24
Finished Jun 26 06:22:04 PM PDT 24
Peak memory 199900 kb
Host smart-553af0ee-50f1-4a2a-b0c2-3d4cb96a3131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72727548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.72727548
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3635164338
Short name T82
Test name
Test status
Simulation time 2029753272 ps
CPU time 6.94 seconds
Started Jun 26 06:21:58 PM PDT 24
Finished Jun 26 06:22:07 PM PDT 24
Peak memory 200336 kb
Host smart-b600692f-9e8c-461d-a405-fd345ba5d2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635164338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3635164338
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1559521374
Short name T10
Test name
Test status
Simulation time 171611420 ps
CPU time 1.19 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:09 PM PDT 24
Peak memory 200080 kb
Host smart-6a5ce857-adfb-4e90-aa08-e2e9ad442b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559521374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1559521374
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.276431361
Short name T542
Test name
Test status
Simulation time 5704904865 ps
CPU time 21.34 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:28 PM PDT 24
Peak memory 208612 kb
Host smart-1d4ad0e9-9c40-44a5-a2e6-6edcaaab081b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276431361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.276431361
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2108574370
Short name T460
Test name
Test status
Simulation time 147108655 ps
CPU time 1.89 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:11 PM PDT 24
Peak memory 200084 kb
Host smart-d2419db0-33c8-4d1b-8e6e-2d75a6feef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108574370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2108574370
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1862476714
Short name T522
Test name
Test status
Simulation time 112244834 ps
CPU time 1.02 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:09 PM PDT 24
Peak memory 200096 kb
Host smart-0cb69d44-0e09-40e4-846e-bb7cea967635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862476714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1862476714
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.4168289224
Short name T51
Test name
Test status
Simulation time 52331055 ps
CPU time 0.73 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:09 PM PDT 24
Peak memory 199816 kb
Host smart-eb106fc6-2d6f-479d-b0e9-73ef217a4d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168289224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.4168289224
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2786352355
Short name T540
Test name
Test status
Simulation time 1226699581 ps
CPU time 5.88 seconds
Started Jun 26 06:22:09 PM PDT 24
Finished Jun 26 06:22:17 PM PDT 24
Peak memory 217656 kb
Host smart-9f939f05-fd09-475e-bd2f-2f7ab9327487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786352355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2786352355
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1741353884
Short name T510
Test name
Test status
Simulation time 244076344 ps
CPU time 1.09 seconds
Started Jun 26 06:22:08 PM PDT 24
Finished Jun 26 06:22:11 PM PDT 24
Peak memory 217456 kb
Host smart-3245a5aa-6da5-4f0c-a13c-6cad28c7a40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741353884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1741353884
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3475807489
Short name T17
Test name
Test status
Simulation time 127028389 ps
CPU time 0.84 seconds
Started Jun 26 06:22:08 PM PDT 24
Finished Jun 26 06:22:11 PM PDT 24
Peak memory 199912 kb
Host smart-9db764b1-5403-4280-8b43-2ee4974ea763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475807489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3475807489
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3228406361
Short name T371
Test name
Test status
Simulation time 1911745796 ps
CPU time 7.17 seconds
Started Jun 26 06:22:07 PM PDT 24
Finished Jun 26 06:22:17 PM PDT 24
Peak memory 200312 kb
Host smart-9a83f5f5-6b36-4bd6-b817-9be3d3c747a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228406361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3228406361
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3637350101
Short name T196
Test name
Test status
Simulation time 105999173 ps
CPU time 1.09 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:10 PM PDT 24
Peak memory 200112 kb
Host smart-6044fb29-7fa0-43c8-a1b8-38d59a663892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637350101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3637350101
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3131181539
Short name T444
Test name
Test status
Simulation time 111531001 ps
CPU time 1.2 seconds
Started Jun 26 06:22:12 PM PDT 24
Finished Jun 26 06:22:14 PM PDT 24
Peak memory 200232 kb
Host smart-463b25aa-8d0e-4788-8977-81cc1c63a81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131181539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3131181539
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3174795091
Short name T259
Test name
Test status
Simulation time 526947256 ps
CPU time 3.05 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:10 PM PDT 24
Peak memory 200068 kb
Host smart-97ce9376-6aef-4a00-b480-2e33e4d38613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174795091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3174795091
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.4237503086
Short name T346
Test name
Test status
Simulation time 191648073 ps
CPU time 1.27 seconds
Started Jun 26 06:22:03 PM PDT 24
Finished Jun 26 06:22:06 PM PDT 24
Peak memory 199956 kb
Host smart-62e24456-bdda-4f69-9f0f-b1c732952a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237503086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.4237503086
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.524723178
Short name T9
Test name
Test status
Simulation time 65397298 ps
CPU time 0.77 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:08 PM PDT 24
Peak memory 199864 kb
Host smart-07a329bc-ec3a-4de4-a50c-2312a8f8cede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524723178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.524723178
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2118694823
Short name T25
Test name
Test status
Simulation time 1898176264 ps
CPU time 6.87 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:13 PM PDT 24
Peak memory 217644 kb
Host smart-316947c3-7669-4ec8-9300-722ab96219d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118694823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2118694823
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3328983729
Short name T348
Test name
Test status
Simulation time 244283780 ps
CPU time 1.15 seconds
Started Jun 26 06:22:04 PM PDT 24
Finished Jun 26 06:22:06 PM PDT 24
Peak memory 217412 kb
Host smart-14f7bf8a-8eff-4ada-ae26-b653652ea5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328983729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3328983729
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3440539008
Short name T428
Test name
Test status
Simulation time 82066823 ps
CPU time 0.75 seconds
Started Jun 26 06:22:08 PM PDT 24
Finished Jun 26 06:22:11 PM PDT 24
Peak memory 199900 kb
Host smart-ad897df4-62c3-41ad-aafa-a8c4f33baed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440539008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3440539008
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3546745064
Short name T383
Test name
Test status
Simulation time 1715303898 ps
CPU time 6.32 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:13 PM PDT 24
Peak memory 200276 kb
Host smart-e55deb78-cf05-4f69-837c-50fee90197e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546745064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3546745064
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1702725932
Short name T516
Test name
Test status
Simulation time 174325517 ps
CPU time 1.15 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:07 PM PDT 24
Peak memory 199992 kb
Host smart-e8cab927-d798-4711-a660-2f5c7ea0b366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702725932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1702725932
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3702284301
Short name T134
Test name
Test status
Simulation time 113369637 ps
CPU time 1.15 seconds
Started Jun 26 06:22:07 PM PDT 24
Finished Jun 26 06:22:10 PM PDT 24
Peak memory 200288 kb
Host smart-e5ce6f87-c857-4160-91dc-7a5683c62a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702284301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3702284301
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.76224789
Short name T34
Test name
Test status
Simulation time 4279889792 ps
CPU time 18.25 seconds
Started Jun 26 06:22:08 PM PDT 24
Finished Jun 26 06:22:28 PM PDT 24
Peak memory 208576 kb
Host smart-2f4c228f-d7b4-45da-ac3c-565ea1f10e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76224789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.76224789
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1874355834
Short name T429
Test name
Test status
Simulation time 306574009 ps
CPU time 2.03 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:10 PM PDT 24
Peak memory 208288 kb
Host smart-16150113-99d1-4296-b0b0-d9dc5aa22547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874355834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1874355834
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1178081837
Short name T521
Test name
Test status
Simulation time 122523840 ps
CPU time 1.07 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:08 PM PDT 24
Peak memory 200104 kb
Host smart-d71b88d4-f709-4e17-a752-12839536a2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178081837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1178081837
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3187127867
Short name T414
Test name
Test status
Simulation time 77358025 ps
CPU time 0.79 seconds
Started Jun 26 06:22:07 PM PDT 24
Finished Jun 26 06:22:10 PM PDT 24
Peak memory 199888 kb
Host smart-7e0d816d-ca0e-4e00-8212-ba35dcfe8a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187127867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3187127867
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3573110877
Short name T350
Test name
Test status
Simulation time 1225833065 ps
CPU time 6.01 seconds
Started Jun 26 06:22:08 PM PDT 24
Finished Jun 26 06:22:16 PM PDT 24
Peak memory 217716 kb
Host smart-6b913a66-ea27-4941-b48d-133bddd1b7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573110877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3573110877
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.4081451319
Short name T57
Test name
Test status
Simulation time 244457719 ps
CPU time 1.04 seconds
Started Jun 26 06:22:09 PM PDT 24
Finished Jun 26 06:22:12 PM PDT 24
Peak memory 217440 kb
Host smart-0588b93f-9980-4bab-b366-37af9fff636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081451319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.4081451319
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1594568575
Short name T18
Test name
Test status
Simulation time 176665839 ps
CPU time 0.95 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:09 PM PDT 24
Peak memory 199912 kb
Host smart-5ea1855a-eb77-4548-a525-c9e8d4c50ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594568575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1594568575
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2337978898
Short name T466
Test name
Test status
Simulation time 1075839188 ps
CPU time 5.02 seconds
Started Jun 26 06:22:06 PM PDT 24
Finished Jun 26 06:22:14 PM PDT 24
Peak memory 200308 kb
Host smart-6638c2bb-be33-4173-8718-451e0f74e8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337978898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2337978898
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3127002422
Short name T62
Test name
Test status
Simulation time 143737403 ps
CPU time 1.06 seconds
Started Jun 26 06:22:08 PM PDT 24
Finished Jun 26 06:22:11 PM PDT 24
Peak memory 200008 kb
Host smart-f8a2642e-dcd1-4764-9e9c-2e401ea64c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127002422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3127002422
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3884910289
Short name T376
Test name
Test status
Simulation time 260451409 ps
CPU time 1.58 seconds
Started Jun 26 06:22:08 PM PDT 24
Finished Jun 26 06:22:12 PM PDT 24
Peak memory 200276 kb
Host smart-9c9431f1-30ed-4a23-8d81-d14e5690f640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884910289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3884910289
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2965385906
Short name T12
Test name
Test status
Simulation time 2184876092 ps
CPU time 8.33 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:16 PM PDT 24
Peak memory 200472 kb
Host smart-e0aa5a14-17f0-4350-843b-fbf268b8e046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965385906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2965385906
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.81936828
Short name T439
Test name
Test status
Simulation time 146528671 ps
CPU time 1.96 seconds
Started Jun 26 06:22:07 PM PDT 24
Finished Jun 26 06:22:11 PM PDT 24
Peak memory 200092 kb
Host smart-b6d34cfe-2461-4a41-9e37-a5581b71a610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81936828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.81936828
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2770297238
Short name T311
Test name
Test status
Simulation time 193118770 ps
CPU time 1.14 seconds
Started Jun 26 06:22:09 PM PDT 24
Finished Jun 26 06:22:12 PM PDT 24
Peak memory 200088 kb
Host smart-6362fed2-6d02-4431-b7e4-37a8cef92437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770297238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2770297238
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3471624185
Short name T269
Test name
Test status
Simulation time 66830518 ps
CPU time 0.89 seconds
Started Jun 26 06:22:14 PM PDT 24
Finished Jun 26 06:22:17 PM PDT 24
Peak memory 199880 kb
Host smart-5ba875db-6fba-41b4-973a-5c220f75db4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471624185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3471624185
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3956856047
Short name T485
Test name
Test status
Simulation time 1881510399 ps
CPU time 7.12 seconds
Started Jun 26 06:22:05 PM PDT 24
Finished Jun 26 06:22:15 PM PDT 24
Peak memory 221648 kb
Host smart-410c0342-076b-4926-b423-08bf02010dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956856047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3956856047
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3612464780
Short name T226
Test name
Test status
Simulation time 243789116 ps
CPU time 1.15 seconds
Started Jun 26 06:22:08 PM PDT 24
Finished Jun 26 06:22:11 PM PDT 24
Peak memory 217460 kb
Host smart-d8239870-1148-4bb1-b070-4352ec45b32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612464780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3612464780
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2365169348
Short name T403
Test name
Test status
Simulation time 99870671 ps
CPU time 0.79 seconds
Started Jun 26 06:22:07 PM PDT 24
Finished Jun 26 06:22:10 PM PDT 24
Peak memory 199900 kb
Host smart-f8df7c8f-5628-4fbe-ba0a-3d99f78c304e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365169348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2365169348
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.168997389
Short name T349
Test name
Test status
Simulation time 1523170889 ps
CPU time 6.86 seconds
Started Jun 26 06:22:08 PM PDT 24
Finished Jun 26 06:22:17 PM PDT 24
Peak memory 200296 kb
Host smart-fa32735d-1c11-48c7-b25c-8aca9676fa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168997389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.168997389
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2230398318
Short name T140
Test name
Test status
Simulation time 97410649 ps
CPU time 1 seconds
Started Jun 26 06:22:07 PM PDT 24
Finished Jun 26 06:22:10 PM PDT 24
Peak memory 200108 kb
Host smart-5d1cd9f7-7f24-43d9-9a82-6417edc988a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230398318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2230398318
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.66079365
Short name T174
Test name
Test status
Simulation time 122690131 ps
CPU time 1.26 seconds
Started Jun 26 06:22:08 PM PDT 24
Finished Jun 26 06:22:12 PM PDT 24
Peak memory 200360 kb
Host smart-c54d2885-d0c4-440f-b4f7-c76890cd2b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66079365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.66079365
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3674533068
Short name T193
Test name
Test status
Simulation time 5569572903 ps
CPU time 20.28 seconds
Started Jun 26 06:22:13 PM PDT 24
Finished Jun 26 06:22:34 PM PDT 24
Peak memory 208628 kb
Host smart-5834c943-8103-40c4-9ad0-7f8a61e7f54d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674533068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3674533068
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.248028129
Short name T463
Test name
Test status
Simulation time 105200894 ps
CPU time 1.44 seconds
Started Jun 26 06:22:12 PM PDT 24
Finished Jun 26 06:22:15 PM PDT 24
Peak memory 200040 kb
Host smart-1e18089f-a3ae-4740-9a6d-f2ddd48b1623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248028129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.248028129
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2098820565
Short name T84
Test name
Test status
Simulation time 88455219 ps
CPU time 0.93 seconds
Started Jun 26 06:22:08 PM PDT 24
Finished Jun 26 06:22:11 PM PDT 24
Peak memory 200080 kb
Host smart-88b2c8e8-bbdd-4ddc-b7fc-647228d9e7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098820565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2098820565
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1085285854
Short name T469
Test name
Test status
Simulation time 63328508 ps
CPU time 0.78 seconds
Started Jun 26 06:22:14 PM PDT 24
Finished Jun 26 06:22:16 PM PDT 24
Peak memory 199884 kb
Host smart-26788b7d-0cce-49be-8eb9-921227bafef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085285854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1085285854
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2439323360
Short name T491
Test name
Test status
Simulation time 2368374588 ps
CPU time 8.74 seconds
Started Jun 26 06:22:11 PM PDT 24
Finished Jun 26 06:22:21 PM PDT 24
Peak memory 217136 kb
Host smart-2b82e397-c430-4429-96b2-2bf6b87f3782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439323360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2439323360
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1608329597
Short name T504
Test name
Test status
Simulation time 248990002 ps
CPU time 1.15 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:16 PM PDT 24
Peak memory 217436 kb
Host smart-d41391b1-c64c-489b-a816-d66bdb4aa873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608329597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1608329597
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3961725560
Short name T457
Test name
Test status
Simulation time 222232671 ps
CPU time 0.96 seconds
Started Jun 26 06:22:13 PM PDT 24
Finished Jun 26 06:22:16 PM PDT 24
Peak memory 199856 kb
Host smart-adc020f0-1df4-4083-840d-626f6fac7a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961725560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3961725560
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.4114715419
Short name T486
Test name
Test status
Simulation time 1927889520 ps
CPU time 6.84 seconds
Started Jun 26 06:22:17 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 200296 kb
Host smart-b132d075-3d48-4448-a32c-9f2b86100baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114715419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.4114715419
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2256882112
Short name T312
Test name
Test status
Simulation time 149525358 ps
CPU time 1.19 seconds
Started Jun 26 06:22:13 PM PDT 24
Finished Jun 26 06:22:15 PM PDT 24
Peak memory 200040 kb
Host smart-deee6cc0-bec7-458c-83b2-a7c8f02e6eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256882112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2256882112
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1503669102
Short name T492
Test name
Test status
Simulation time 201488864 ps
CPU time 1.38 seconds
Started Jun 26 06:22:15 PM PDT 24
Finished Jun 26 06:22:18 PM PDT 24
Peak memory 200260 kb
Host smart-8849d237-54fe-4924-bdc9-6775e6d6c951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503669102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1503669102
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1295270381
Short name T405
Test name
Test status
Simulation time 3397650443 ps
CPU time 13.83 seconds
Started Jun 26 06:22:11 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 200428 kb
Host smart-1eba19ce-6723-4177-9c91-fa2f40a2c9e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295270381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1295270381
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.886823142
Short name T261
Test name
Test status
Simulation time 270994678 ps
CPU time 1.57 seconds
Started Jun 26 06:22:15 PM PDT 24
Finished Jun 26 06:22:19 PM PDT 24
Peak memory 200116 kb
Host smart-e0b27e94-e175-437f-be15-1507db538dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886823142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.886823142
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2078237523
Short name T394
Test name
Test status
Simulation time 74454858 ps
CPU time 0.77 seconds
Started Jun 26 06:21:18 PM PDT 24
Finished Jun 26 06:21:20 PM PDT 24
Peak memory 199876 kb
Host smart-18dee542-0a34-45a6-bcf6-17202ad6f6d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078237523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2078237523
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2421886025
Short name T309
Test name
Test status
Simulation time 1885970599 ps
CPU time 6.97 seconds
Started Jun 26 06:21:20 PM PDT 24
Finished Jun 26 06:21:29 PM PDT 24
Peak memory 217716 kb
Host smart-541b6a94-265e-4585-bd4a-6be708f17c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421886025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2421886025
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2485971208
Short name T75
Test name
Test status
Simulation time 244232429 ps
CPU time 1.06 seconds
Started Jun 26 06:21:20 PM PDT 24
Finished Jun 26 06:21:23 PM PDT 24
Peak memory 217432 kb
Host smart-1823d1f4-780d-46d4-80fb-405f0ef117cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485971208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2485971208
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1594763651
Short name T363
Test name
Test status
Simulation time 204189470 ps
CPU time 0.97 seconds
Started Jun 26 06:21:20 PM PDT 24
Finished Jun 26 06:21:23 PM PDT 24
Peak memory 199872 kb
Host smart-ecddafbb-de0c-4972-a46a-99cdfd01158d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594763651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1594763651
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2438639507
Short name T321
Test name
Test status
Simulation time 976082437 ps
CPU time 4.35 seconds
Started Jun 26 06:21:20 PM PDT 24
Finished Jun 26 06:21:26 PM PDT 24
Peak memory 200372 kb
Host smart-2309e1fd-3693-4f6e-aef1-521b939034ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438639507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2438639507
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4218295396
Short name T518
Test name
Test status
Simulation time 180482730 ps
CPU time 1.27 seconds
Started Jun 26 06:21:22 PM PDT 24
Finished Jun 26 06:21:24 PM PDT 24
Peak memory 200024 kb
Host smart-6f8469ce-5e67-4b3b-b074-128b81c81eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218295396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.4218295396
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2442652309
Short name T484
Test name
Test status
Simulation time 118188581 ps
CPU time 1.18 seconds
Started Jun 26 06:21:19 PM PDT 24
Finished Jun 26 06:21:21 PM PDT 24
Peak memory 200244 kb
Host smart-f020fe7d-ad54-44f6-928d-372002b6c6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442652309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2442652309
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3104024235
Short name T132
Test name
Test status
Simulation time 8303633091 ps
CPU time 38.1 seconds
Started Jun 26 06:21:22 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 210380 kb
Host smart-3c0e1b72-6660-432c-8809-377e9edccd48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104024235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3104024235
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3912343157
Short name T191
Test name
Test status
Simulation time 339361739 ps
CPU time 1.97 seconds
Started Jun 26 06:21:22 PM PDT 24
Finished Jun 26 06:21:26 PM PDT 24
Peak memory 200076 kb
Host smart-db6d7890-6807-4ac3-8106-17a13bae0cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912343157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3912343157
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3778700441
Short name T325
Test name
Test status
Simulation time 101658119 ps
CPU time 0.9 seconds
Started Jun 26 06:21:20 PM PDT 24
Finished Jun 26 06:21:23 PM PDT 24
Peak memory 200108 kb
Host smart-7aa645e0-ced8-4732-8eb3-8c9cd8d97051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778700441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3778700441
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.108881280
Short name T133
Test name
Test status
Simulation time 72898998 ps
CPU time 0.83 seconds
Started Jun 26 06:22:15 PM PDT 24
Finished Jun 26 06:22:17 PM PDT 24
Peak memory 199896 kb
Host smart-df3bc2ff-0cef-4b9e-8b31-6039d77bd590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108881280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.108881280
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.265729349
Short name T30
Test name
Test status
Simulation time 1233206488 ps
CPU time 5.48 seconds
Started Jun 26 06:22:19 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 221644 kb
Host smart-1fd06356-c9ed-4764-8dba-45440bc7c7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265729349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.265729349
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1031382121
Short name T430
Test name
Test status
Simulation time 244831545 ps
CPU time 1.22 seconds
Started Jun 26 06:22:12 PM PDT 24
Finished Jun 26 06:22:14 PM PDT 24
Peak memory 217464 kb
Host smart-65813260-8efb-4013-b7e1-face71d1b6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031382121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1031382121
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2728440843
Short name T3
Test name
Test status
Simulation time 226364521 ps
CPU time 0.97 seconds
Started Jun 26 06:22:12 PM PDT 24
Finished Jun 26 06:22:14 PM PDT 24
Peak memory 199808 kb
Host smart-82e312fb-fc16-49e9-8658-f1ce75e6086a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728440843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2728440843
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3741417527
Short name T200
Test name
Test status
Simulation time 931039622 ps
CPU time 5.17 seconds
Started Jun 26 06:22:11 PM PDT 24
Finished Jun 26 06:22:17 PM PDT 24
Peak memory 200364 kb
Host smart-a3e490d8-2c40-4010-818d-a88f6f93be62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741417527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3741417527
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.4037171666
Short name T198
Test name
Test status
Simulation time 175954020 ps
CPU time 1.26 seconds
Started Jun 26 06:22:15 PM PDT 24
Finished Jun 26 06:22:19 PM PDT 24
Peak memory 200108 kb
Host smart-b86c2dbb-c240-469c-8e2e-c44ac1a9dda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037171666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.4037171666
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3081329065
Short name T360
Test name
Test status
Simulation time 121819207 ps
CPU time 1.26 seconds
Started Jun 26 06:22:14 PM PDT 24
Finished Jun 26 06:22:17 PM PDT 24
Peak memory 200272 kb
Host smart-2597ea05-eb81-4a72-be2f-8d9e98090264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081329065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3081329065
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.505727394
Short name T448
Test name
Test status
Simulation time 6706207998 ps
CPU time 23.07 seconds
Started Jun 26 06:22:18 PM PDT 24
Finished Jun 26 06:22:43 PM PDT 24
Peak memory 200360 kb
Host smart-da374fa8-63cf-4eef-80e6-c782275dde30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505727394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.505727394
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2139768444
Short name T85
Test name
Test status
Simulation time 286824113 ps
CPU time 2.02 seconds
Started Jun 26 06:22:17 PM PDT 24
Finished Jun 26 06:22:21 PM PDT 24
Peak memory 208272 kb
Host smart-308fb284-69fc-4149-826b-8a95e07dcdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139768444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2139768444
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3932944872
Short name T407
Test name
Test status
Simulation time 133373688 ps
CPU time 1.17 seconds
Started Jun 26 06:22:17 PM PDT 24
Finished Jun 26 06:22:20 PM PDT 24
Peak memory 200296 kb
Host smart-d68fffae-fd52-4920-8439-0c0001fa65c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932944872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3932944872
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.4130980234
Short name T480
Test name
Test status
Simulation time 69118348 ps
CPU time 0.82 seconds
Started Jun 26 06:22:18 PM PDT 24
Finished Jun 26 06:22:20 PM PDT 24
Peak memory 200088 kb
Host smart-9abf3040-7df5-4c19-821c-ecfbec242f63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130980234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.4130980234
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2052914059
Short name T519
Test name
Test status
Simulation time 1217576736 ps
CPU time 5.56 seconds
Started Jun 26 06:22:16 PM PDT 24
Finished Jun 26 06:22:23 PM PDT 24
Peak memory 217684 kb
Host smart-0db4a937-f5b0-48c5-939d-4f46565d8010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052914059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2052914059
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1445264466
Short name T315
Test name
Test status
Simulation time 244030625 ps
CPU time 1.13 seconds
Started Jun 26 06:22:12 PM PDT 24
Finished Jun 26 06:22:14 PM PDT 24
Peak memory 217436 kb
Host smart-934a2207-e9cc-49ca-adf5-51916443eefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445264466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1445264466
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1128755575
Short name T478
Test name
Test status
Simulation time 124491444 ps
CPU time 0.88 seconds
Started Jun 26 06:22:15 PM PDT 24
Finished Jun 26 06:22:18 PM PDT 24
Peak memory 199912 kb
Host smart-fa1551a5-1fb2-45bf-b236-9aa062698927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128755575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1128755575
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1247304432
Short name T435
Test name
Test status
Simulation time 1449796736 ps
CPU time 5.75 seconds
Started Jun 26 06:22:17 PM PDT 24
Finished Jun 26 06:22:25 PM PDT 24
Peak memory 200552 kb
Host smart-b914bb91-95fb-435d-80fc-222c1a7aeb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247304432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1247304432
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3571850133
Short name T274
Test name
Test status
Simulation time 171906939 ps
CPU time 1.24 seconds
Started Jun 26 06:22:16 PM PDT 24
Finished Jun 26 06:22:19 PM PDT 24
Peak memory 200088 kb
Host smart-7999a35c-9964-46d8-891a-a06aaf256e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571850133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3571850133
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.4108670137
Short name T1
Test name
Test status
Simulation time 119290463 ps
CPU time 1.16 seconds
Started Jun 26 06:22:15 PM PDT 24
Finished Jun 26 06:22:18 PM PDT 24
Peak memory 200288 kb
Host smart-304a04a5-00c6-4bf9-9cdf-4e0770d0f7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108670137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.4108670137
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.689312740
Short name T107
Test name
Test status
Simulation time 11304945553 ps
CPU time 42.3 seconds
Started Jun 26 06:22:14 PM PDT 24
Finished Jun 26 06:22:58 PM PDT 24
Peak memory 208616 kb
Host smart-d1916ee4-681b-456b-a572-0ff73b777747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689312740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.689312740
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1176215927
Short name T544
Test name
Test status
Simulation time 155320957 ps
CPU time 1.85 seconds
Started Jun 26 06:22:15 PM PDT 24
Finished Jun 26 06:22:18 PM PDT 24
Peak memory 200076 kb
Host smart-9ee8c0bd-0f42-4f5d-a5be-8db413b0780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176215927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1176215927
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1261788486
Short name T339
Test name
Test status
Simulation time 237655316 ps
CPU time 1.48 seconds
Started Jun 26 06:22:15 PM PDT 24
Finished Jun 26 06:22:18 PM PDT 24
Peak memory 200076 kb
Host smart-8c9a16f4-d298-4779-a45c-299af1b0b88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261788486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1261788486
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2475449458
Short name T283
Test name
Test status
Simulation time 137285712 ps
CPU time 0.9 seconds
Started Jun 26 06:22:14 PM PDT 24
Finished Jun 26 06:22:16 PM PDT 24
Peak memory 199900 kb
Host smart-b2d20054-86e5-405e-a985-6a68e124d2fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475449458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2475449458
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3325252173
Short name T53
Test name
Test status
Simulation time 2366545912 ps
CPU time 8.97 seconds
Started Jun 26 06:22:16 PM PDT 24
Finished Jun 26 06:22:27 PM PDT 24
Peak memory 221500 kb
Host smart-bf105330-3516-4405-a95d-6016a0626704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325252173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3325252173
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4082039021
Short name T278
Test name
Test status
Simulation time 243833950 ps
CPU time 1.18 seconds
Started Jun 26 06:22:16 PM PDT 24
Finished Jun 26 06:22:19 PM PDT 24
Peak memory 217460 kb
Host smart-e544bd5e-b7e5-433c-9c1c-35850671b5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082039021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4082039021
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.554346961
Short name T277
Test name
Test status
Simulation time 186526337 ps
CPU time 0.94 seconds
Started Jun 26 06:22:17 PM PDT 24
Finished Jun 26 06:22:20 PM PDT 24
Peak memory 199900 kb
Host smart-534bcdb9-0081-4f01-819c-82dffa67fbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554346961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.554346961
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2802191564
Short name T399
Test name
Test status
Simulation time 942337070 ps
CPU time 4.78 seconds
Started Jun 26 06:22:14 PM PDT 24
Finished Jun 26 06:22:21 PM PDT 24
Peak memory 200348 kb
Host smart-0e40bb0e-e25d-4849-ac3a-dab84df1bd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802191564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2802191564
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3582215674
Short name T300
Test name
Test status
Simulation time 106985631 ps
CPU time 1.09 seconds
Started Jun 26 06:22:16 PM PDT 24
Finished Jun 26 06:22:19 PM PDT 24
Peak memory 200080 kb
Host smart-d93c754a-64ca-4154-b93a-e213a5e76ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582215674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3582215674
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2910750667
Short name T56
Test name
Test status
Simulation time 126488719 ps
CPU time 1.21 seconds
Started Jun 26 06:22:17 PM PDT 24
Finished Jun 26 06:22:20 PM PDT 24
Peak memory 200288 kb
Host smart-be486b7e-f478-49c0-8daa-f50047e0e346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910750667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2910750667
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3384142522
Short name T260
Test name
Test status
Simulation time 1659832400 ps
CPU time 7.59 seconds
Started Jun 26 06:22:16 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 200280 kb
Host smart-5a9c637d-fe04-4c95-90be-e1290864e053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384142522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3384142522
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3679981454
Short name T192
Test name
Test status
Simulation time 150238252 ps
CPU time 1.97 seconds
Started Jun 26 06:22:14 PM PDT 24
Finished Jun 26 06:22:18 PM PDT 24
Peak memory 200100 kb
Host smart-e3b91566-5312-4f47-b6f5-f55333d90c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679981454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3679981454
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3409536768
Short name T163
Test name
Test status
Simulation time 230691779 ps
CPU time 1.4 seconds
Started Jun 26 06:22:14 PM PDT 24
Finished Jun 26 06:22:17 PM PDT 24
Peak memory 200080 kb
Host smart-69235f25-5567-4d46-bcca-89e4dfd980f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409536768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3409536768
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2380111265
Short name T357
Test name
Test status
Simulation time 89694355 ps
CPU time 0.87 seconds
Started Jun 26 06:22:14 PM PDT 24
Finished Jun 26 06:22:16 PM PDT 24
Peak memory 199900 kb
Host smart-abdad693-8a85-4ea1-860e-787ed528b0c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380111265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2380111265
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1419208410
Short name T369
Test name
Test status
Simulation time 1894801001 ps
CPU time 7.17 seconds
Started Jun 26 06:22:14 PM PDT 24
Finished Jun 26 06:22:23 PM PDT 24
Peak memory 217896 kb
Host smart-862e2839-981b-4436-b2d8-7f33b2456fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419208410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1419208410
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3995019217
Short name T400
Test name
Test status
Simulation time 244109288 ps
CPU time 1.24 seconds
Started Jun 26 06:22:15 PM PDT 24
Finished Jun 26 06:22:18 PM PDT 24
Peak memory 217476 kb
Host smart-adcc90ac-f705-4e02-b3ce-a39fbbaebc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995019217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3995019217
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2533173927
Short name T450
Test name
Test status
Simulation time 226234669 ps
CPU time 0.99 seconds
Started Jun 26 06:22:15 PM PDT 24
Finished Jun 26 06:22:17 PM PDT 24
Peak memory 199920 kb
Host smart-0c3e2e46-03dd-4444-8838-f791a386b9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533173927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2533173927
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1776165796
Short name T230
Test name
Test status
Simulation time 1376132176 ps
CPU time 5.23 seconds
Started Jun 26 06:22:14 PM PDT 24
Finished Jun 26 06:22:21 PM PDT 24
Peak memory 200344 kb
Host smart-f61ca8b4-60f2-41d9-94ee-ced677c68c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776165796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1776165796
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2474812550
Short name T129
Test name
Test status
Simulation time 180737460 ps
CPU time 1.28 seconds
Started Jun 26 06:22:16 PM PDT 24
Finished Jun 26 06:22:20 PM PDT 24
Peak memory 200052 kb
Host smart-c1d9bad6-2f11-4319-b00d-cb01ed88475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474812550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2474812550
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.658959420
Short name T512
Test name
Test status
Simulation time 191333122 ps
CPU time 1.49 seconds
Started Jun 26 06:22:11 PM PDT 24
Finished Jun 26 06:22:13 PM PDT 24
Peak memory 200288 kb
Host smart-2f5d6688-0daf-45f9-9247-7a4f6cffcb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658959420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.658959420
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3501974107
Short name T288
Test name
Test status
Simulation time 2482791453 ps
CPU time 11.47 seconds
Started Jun 26 06:22:16 PM PDT 24
Finished Jun 26 06:22:29 PM PDT 24
Peak memory 208600 kb
Host smart-2e83ac68-4aea-4c58-b16f-97c8f3d4417c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501974107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3501974107
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3557514652
Short name T169
Test name
Test status
Simulation time 127701337 ps
CPU time 1.46 seconds
Started Jun 26 06:22:18 PM PDT 24
Finished Jun 26 06:22:21 PM PDT 24
Peak memory 200120 kb
Host smart-5e5d3fe8-02e0-4bca-bab2-0cd9f8c35dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557514652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3557514652
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3771114688
Short name T330
Test name
Test status
Simulation time 77034469 ps
CPU time 0.83 seconds
Started Jun 26 06:22:16 PM PDT 24
Finished Jun 26 06:22:19 PM PDT 24
Peak memory 200096 kb
Host smart-219db4fb-0c70-4c4e-b115-701f2e8d3d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771114688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3771114688
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3787042939
Short name T59
Test name
Test status
Simulation time 61855434 ps
CPU time 0.78 seconds
Started Jun 26 06:22:19 PM PDT 24
Finished Jun 26 06:22:21 PM PDT 24
Peak memory 199836 kb
Host smart-3ab3d431-b8dc-46e0-bac9-391f347b1d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787042939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3787042939
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2681200549
Short name T337
Test name
Test status
Simulation time 1236541223 ps
CPU time 5.72 seconds
Started Jun 26 06:22:25 PM PDT 24
Finished Jun 26 06:22:32 PM PDT 24
Peak memory 221648 kb
Host smart-55c4761f-27e4-4a9e-8f5f-99d8264d8a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681200549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2681200549
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2542949915
Short name T454
Test name
Test status
Simulation time 245000037 ps
CPU time 1.03 seconds
Started Jun 26 06:22:18 PM PDT 24
Finished Jun 26 06:22:21 PM PDT 24
Peak memory 217452 kb
Host smart-a12d072c-8d43-4004-8360-186dab6851aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542949915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2542949915
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.74453062
Short name T246
Test name
Test status
Simulation time 73198525 ps
CPU time 0.76 seconds
Started Jun 26 06:22:23 PM PDT 24
Finished Jun 26 06:22:25 PM PDT 24
Peak memory 199924 kb
Host smart-26e7b188-ed58-4cf0-9fb8-450c8dff574d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74453062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.74453062
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3086490900
Short name T252
Test name
Test status
Simulation time 931997404 ps
CPU time 4.89 seconds
Started Jun 26 06:22:22 PM PDT 24
Finished Jun 26 06:22:29 PM PDT 24
Peak memory 200344 kb
Host smart-26a41a60-99d8-411c-9db2-b49d5dc0c967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086490900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3086490900
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.685672246
Short name T358
Test name
Test status
Simulation time 102982089 ps
CPU time 1.01 seconds
Started Jun 26 06:22:21 PM PDT 24
Finished Jun 26 06:22:23 PM PDT 24
Peak memory 200104 kb
Host smart-bf577390-16eb-4b0e-ba4d-f319026f7839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685672246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.685672246
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2081920358
Short name T471
Test name
Test status
Simulation time 253411581 ps
CPU time 1.45 seconds
Started Jun 26 06:22:23 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 200260 kb
Host smart-5d68e688-1fe8-4d02-bd84-1a228cb61d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081920358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2081920358
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.4092155748
Short name T424
Test name
Test status
Simulation time 1640581715 ps
CPU time 5.86 seconds
Started Jun 26 06:22:21 PM PDT 24
Finished Jun 26 06:22:29 PM PDT 24
Peak memory 200408 kb
Host smart-cba6603e-99d4-4a15-9707-48fc0cff92d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092155748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.4092155748
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.678064687
Short name T393
Test name
Test status
Simulation time 277780791 ps
CPU time 1.89 seconds
Started Jun 26 06:22:27 PM PDT 24
Finished Jun 26 06:22:30 PM PDT 24
Peak memory 200068 kb
Host smart-5139b8ca-502b-4a05-9b03-37693f8b46a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678064687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.678064687
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3807228411
Short name T479
Test name
Test status
Simulation time 117613478 ps
CPU time 0.93 seconds
Started Jun 26 06:22:23 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 200080 kb
Host smart-64fadde4-6cda-4db7-89ad-7db77c5d0803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807228411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3807228411
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.110133051
Short name T152
Test name
Test status
Simulation time 75611212 ps
CPU time 0.8 seconds
Started Jun 26 06:22:22 PM PDT 24
Finished Jun 26 06:22:24 PM PDT 24
Peak memory 199852 kb
Host smart-27f34da5-24b5-4631-b181-6df69a46558d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110133051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.110133051
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.983650597
Short name T412
Test name
Test status
Simulation time 1223698970 ps
CPU time 6.15 seconds
Started Jun 26 06:22:23 PM PDT 24
Finished Jun 26 06:22:30 PM PDT 24
Peak memory 221616 kb
Host smart-422b2b2b-cf7e-44cc-acc1-d09cc0a79f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983650597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.983650597
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3565462495
Short name T224
Test name
Test status
Simulation time 244872750 ps
CPU time 1.05 seconds
Started Jun 26 06:22:21 PM PDT 24
Finished Jun 26 06:22:23 PM PDT 24
Peak memory 217464 kb
Host smart-da19297a-8aab-4f49-ab66-94ffdddeb977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565462495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3565462495
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3847618063
Short name T347
Test name
Test status
Simulation time 82333119 ps
CPU time 0.78 seconds
Started Jun 26 06:22:22 PM PDT 24
Finished Jun 26 06:22:24 PM PDT 24
Peak memory 199764 kb
Host smart-85d9f99d-522c-4803-bf8d-e951af16860d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847618063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3847618063
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3407936014
Short name T299
Test name
Test status
Simulation time 957571804 ps
CPU time 5.26 seconds
Started Jun 26 06:22:21 PM PDT 24
Finished Jun 26 06:22:27 PM PDT 24
Peak memory 200356 kb
Host smart-6bc60fb1-ca30-4a7a-a8d4-21cfb790fded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407936014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3407936014
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3950245831
Short name T183
Test name
Test status
Simulation time 92698226 ps
CPU time 1.02 seconds
Started Jun 26 06:22:21 PM PDT 24
Finished Jun 26 06:22:24 PM PDT 24
Peak memory 200084 kb
Host smart-2b2c32a6-8724-4ad9-bb4a-b6af7471dab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950245831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3950245831
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1085916817
Short name T170
Test name
Test status
Simulation time 241612651 ps
CPU time 1.52 seconds
Started Jun 26 06:22:22 PM PDT 24
Finished Jun 26 06:22:25 PM PDT 24
Peak memory 200272 kb
Host smart-e1593b84-17d3-4330-b5a7-fc7c29c18f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085916817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1085916817
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3165323139
Short name T324
Test name
Test status
Simulation time 1643959004 ps
CPU time 8.96 seconds
Started Jun 26 06:22:23 PM PDT 24
Finished Jun 26 06:22:34 PM PDT 24
Peak memory 208824 kb
Host smart-d6558862-a5da-4c7e-92ca-601ab86b9eb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165323139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3165323139
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1019924478
Short name T5
Test name
Test status
Simulation time 431613658 ps
CPU time 2.38 seconds
Started Jun 26 06:22:23 PM PDT 24
Finished Jun 26 06:22:27 PM PDT 24
Peak memory 208184 kb
Host smart-b57de2ef-799b-4519-a984-f2172325e117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019924478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1019924478
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3098089839
Short name T124
Test name
Test status
Simulation time 175064403 ps
CPU time 1.19 seconds
Started Jun 26 06:22:25 PM PDT 24
Finished Jun 26 06:22:28 PM PDT 24
Peak memory 200000 kb
Host smart-d934779c-66b7-4b2c-ac78-03bbb61e1261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098089839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3098089839
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3732576857
Short name T462
Test name
Test status
Simulation time 166482362 ps
CPU time 0.98 seconds
Started Jun 26 06:22:24 PM PDT 24
Finished Jun 26 06:22:27 PM PDT 24
Peak memory 199900 kb
Host smart-2fb4c491-d4fd-4576-82f8-ba4e1592f5d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732576857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3732576857
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1299406236
Short name T204
Test name
Test status
Simulation time 244206822 ps
CPU time 1.28 seconds
Started Jun 26 06:22:25 PM PDT 24
Finished Jun 26 06:22:29 PM PDT 24
Peak memory 217328 kb
Host smart-c1f09c74-7c73-43c2-942f-ce5e415b2dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299406236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1299406236
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2754708616
Short name T461
Test name
Test status
Simulation time 153481432 ps
CPU time 0.91 seconds
Started Jun 26 06:22:20 PM PDT 24
Finished Jun 26 06:22:22 PM PDT 24
Peak memory 199924 kb
Host smart-69bed551-6cfb-4ae4-9220-dc5c5adf1166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754708616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2754708616
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1229093795
Short name T234
Test name
Test status
Simulation time 859502067 ps
CPU time 4.32 seconds
Started Jun 26 06:22:21 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 200348 kb
Host smart-eb748fe2-1bc1-4af8-acc1-2a4bef1fc9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229093795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1229093795
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3862166777
Short name T362
Test name
Test status
Simulation time 109576546 ps
CPU time 1.03 seconds
Started Jun 26 06:22:24 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 200108 kb
Host smart-86532e02-82c2-405d-bb1f-56c436d6315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862166777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3862166777
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.4940886
Short name T304
Test name
Test status
Simulation time 110485576 ps
CPU time 1.27 seconds
Started Jun 26 06:22:24 PM PDT 24
Finished Jun 26 06:22:27 PM PDT 24
Peak memory 200308 kb
Host smart-b6ef3d36-7fe8-4e31-b080-8db33b0e9a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4940886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.4940886
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1725147510
Short name T506
Test name
Test status
Simulation time 5087484686 ps
CPU time 18.44 seconds
Started Jun 26 06:22:21 PM PDT 24
Finished Jun 26 06:22:40 PM PDT 24
Peak memory 200412 kb
Host smart-fca9516d-9a6e-48cb-ab0c-c21f4351e08a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725147510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1725147510
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1144317863
Short name T343
Test name
Test status
Simulation time 564122940 ps
CPU time 2.91 seconds
Started Jun 26 06:22:26 PM PDT 24
Finished Jun 26 06:22:31 PM PDT 24
Peak memory 200036 kb
Host smart-22bf9d31-5f04-4382-84b7-5c2090110518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144317863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1144317863
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1361036545
Short name T186
Test name
Test status
Simulation time 171493467 ps
CPU time 1.32 seconds
Started Jun 26 06:22:23 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 200340 kb
Host smart-5cecfc01-d9df-443f-8aed-676ef0b082c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361036545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1361036545
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1947865693
Short name T341
Test name
Test status
Simulation time 63490923 ps
CPU time 0.77 seconds
Started Jun 26 06:22:23 PM PDT 24
Finished Jun 26 06:22:25 PM PDT 24
Peak memory 199884 kb
Host smart-9f9b1785-2fdf-4ed5-bf8a-f1d24f883b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947865693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1947865693
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2203910075
Short name T455
Test name
Test status
Simulation time 1225841428 ps
CPU time 5.67 seconds
Started Jun 26 06:22:21 PM PDT 24
Finished Jun 26 06:22:28 PM PDT 24
Peak memory 221632 kb
Host smart-8d6a89f2-2156-4a72-ab2a-69f0c54f2aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203910075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2203910075
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.123995317
Short name T255
Test name
Test status
Simulation time 245409953 ps
CPU time 1.02 seconds
Started Jun 26 06:22:25 PM PDT 24
Finished Jun 26 06:22:28 PM PDT 24
Peak memory 217476 kb
Host smart-2823d130-5e8e-4346-9d8e-561d9e59ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123995317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.123995317
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3363353975
Short name T541
Test name
Test status
Simulation time 144648680 ps
CPU time 0.87 seconds
Started Jun 26 06:22:23 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 199900 kb
Host smart-daf1aeb4-fa00-47f3-a69d-e730bd4ca682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363353975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3363353975
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.219958713
Short name T328
Test name
Test status
Simulation time 1502659494 ps
CPU time 6.54 seconds
Started Jun 26 06:22:23 PM PDT 24
Finished Jun 26 06:22:31 PM PDT 24
Peak memory 200240 kb
Host smart-c922da8d-cff5-4925-a3b4-3245bed9620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219958713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.219958713
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.448197556
Short name T161
Test name
Test status
Simulation time 174565773 ps
CPU time 1.34 seconds
Started Jun 26 06:22:23 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 200116 kb
Host smart-19b804e1-3ac8-44eb-ac6a-4703cc8aeee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448197556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.448197556
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.939317638
Short name T185
Test name
Test status
Simulation time 257484240 ps
CPU time 1.53 seconds
Started Jun 26 06:22:22 PM PDT 24
Finished Jun 26 06:22:25 PM PDT 24
Peak memory 200276 kb
Host smart-9822aa14-03e8-4e8b-907b-a41bf5f32c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939317638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.939317638
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1934018352
Short name T270
Test name
Test status
Simulation time 1922498889 ps
CPU time 9.06 seconds
Started Jun 26 06:22:22 PM PDT 24
Finished Jun 26 06:22:32 PM PDT 24
Peak memory 208564 kb
Host smart-26544a31-db1e-457b-8393-0af32faf899b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934018352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1934018352
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3753148092
Short name T66
Test name
Test status
Simulation time 342861401 ps
CPU time 2.2 seconds
Started Jun 26 06:22:22 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 200080 kb
Host smart-74240034-fd39-40fb-be8b-851170b347f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753148092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3753148092
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.761258251
Short name T209
Test name
Test status
Simulation time 69743982 ps
CPU time 0.77 seconds
Started Jun 26 06:22:25 PM PDT 24
Finished Jun 26 06:22:28 PM PDT 24
Peak memory 200072 kb
Host smart-e52a5724-be75-467f-acd2-ddf8c94e9417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761258251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.761258251
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3194224876
Short name T237
Test name
Test status
Simulation time 81444426 ps
CPU time 0.83 seconds
Started Jun 26 06:22:34 PM PDT 24
Finished Jun 26 06:22:36 PM PDT 24
Peak memory 199868 kb
Host smart-d79320d1-2fca-434d-98ae-8c17d8348b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194224876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3194224876
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.571071293
Short name T26
Test name
Test status
Simulation time 1220780989 ps
CPU time 5.72 seconds
Started Jun 26 06:22:32 PM PDT 24
Finished Jun 26 06:22:39 PM PDT 24
Peak memory 217488 kb
Host smart-619c10da-4fcd-4ba3-b518-4f90209cb558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571071293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.571071293
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.811561520
Short name T212
Test name
Test status
Simulation time 244990189 ps
CPU time 1.09 seconds
Started Jun 26 06:22:34 PM PDT 24
Finished Jun 26 06:22:36 PM PDT 24
Peak memory 217468 kb
Host smart-b3f9033b-2151-4e97-af40-ed4ff1f729d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811561520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.811561520
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1849045768
Short name T338
Test name
Test status
Simulation time 188033067 ps
CPU time 1.06 seconds
Started Jun 26 06:22:25 PM PDT 24
Finished Jun 26 06:22:29 PM PDT 24
Peak memory 199840 kb
Host smart-9f3c50d6-cbc3-4cd7-a363-17b1a63bae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849045768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1849045768
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.111515391
Short name T104
Test name
Test status
Simulation time 1386040252 ps
CPU time 5.41 seconds
Started Jun 26 06:22:24 PM PDT 24
Finished Jun 26 06:22:31 PM PDT 24
Peak memory 200352 kb
Host smart-d9cd32a8-555b-441c-a50b-1734f5ba2031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111515391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.111515391
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3867919488
Short name T431
Test name
Test status
Simulation time 148403115 ps
CPU time 1.21 seconds
Started Jun 26 06:22:30 PM PDT 24
Finished Jun 26 06:22:32 PM PDT 24
Peak memory 200040 kb
Host smart-ca245b25-128a-40f2-9ef0-21e74f029319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867919488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3867919488
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3625373166
Short name T130
Test name
Test status
Simulation time 120327832 ps
CPU time 1.31 seconds
Started Jun 26 06:22:21 PM PDT 24
Finished Jun 26 06:22:23 PM PDT 24
Peak memory 200344 kb
Host smart-15994f53-4b66-4ecf-98f9-aaa6e5259dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625373166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3625373166
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1851809064
Short name T385
Test name
Test status
Simulation time 1219749043 ps
CPU time 5.7 seconds
Started Jun 26 06:22:31 PM PDT 24
Finished Jun 26 06:22:38 PM PDT 24
Peak memory 200392 kb
Host smart-70075443-d44b-4ff4-ab17-ab37d849c230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851809064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1851809064
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3078213931
Short name T219
Test name
Test status
Simulation time 368109586 ps
CPU time 2 seconds
Started Jun 26 06:22:31 PM PDT 24
Finished Jun 26 06:22:34 PM PDT 24
Peak memory 200080 kb
Host smart-a153e1b0-4f06-4102-ae94-943895abb7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078213931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3078213931
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1424874317
Short name T425
Test name
Test status
Simulation time 110958318 ps
CPU time 1.04 seconds
Started Jun 26 06:22:22 PM PDT 24
Finished Jun 26 06:22:25 PM PDT 24
Peak memory 200116 kb
Host smart-410e0ca4-17cd-4ea8-b470-c8e6028ee058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424874317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1424874317
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1032645404
Short name T147
Test name
Test status
Simulation time 80827578 ps
CPU time 0.86 seconds
Started Jun 26 06:22:30 PM PDT 24
Finished Jun 26 06:22:32 PM PDT 24
Peak memory 199840 kb
Host smart-db542205-072a-41e6-b94f-cf2fa39e8578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032645404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1032645404
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3945969134
Short name T487
Test name
Test status
Simulation time 244109248 ps
CPU time 1.08 seconds
Started Jun 26 06:22:33 PM PDT 24
Finished Jun 26 06:22:35 PM PDT 24
Peak memory 217492 kb
Host smart-0b3e5233-c832-42ce-958a-6dd18211abfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945969134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3945969134
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2495093317
Short name T354
Test name
Test status
Simulation time 205449356 ps
CPU time 0.96 seconds
Started Jun 26 06:22:30 PM PDT 24
Finished Jun 26 06:22:32 PM PDT 24
Peak memory 199892 kb
Host smart-662c5f72-8233-4b1b-9cee-796b43a7dfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495093317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2495093317
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2771475986
Short name T211
Test name
Test status
Simulation time 1286031513 ps
CPU time 5.2 seconds
Started Jun 26 06:22:30 PM PDT 24
Finished Jun 26 06:22:36 PM PDT 24
Peak memory 200324 kb
Host smart-f0909990-5f49-4aae-954f-484b19e4ef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771475986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2771475986
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.247076365
Short name T302
Test name
Test status
Simulation time 152528527 ps
CPU time 1.12 seconds
Started Jun 26 06:22:30 PM PDT 24
Finished Jun 26 06:22:32 PM PDT 24
Peak memory 200104 kb
Host smart-11063440-9f81-4517-9a20-69db5fbc58db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247076365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.247076365
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1463933327
Short name T296
Test name
Test status
Simulation time 199124644 ps
CPU time 1.55 seconds
Started Jun 26 06:22:29 PM PDT 24
Finished Jun 26 06:22:32 PM PDT 24
Peak memory 200276 kb
Host smart-190da352-616c-497e-a651-4a2be21f37f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463933327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1463933327
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2374493661
Short name T48
Test name
Test status
Simulation time 4506233817 ps
CPU time 16.79 seconds
Started Jun 26 06:22:33 PM PDT 24
Finished Jun 26 06:22:50 PM PDT 24
Peak memory 200408 kb
Host smart-360dee8e-ca04-4058-9ea6-725121acd351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374493661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2374493661
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3374676158
Short name T306
Test name
Test status
Simulation time 367440814 ps
CPU time 2.41 seconds
Started Jun 26 06:22:31 PM PDT 24
Finished Jun 26 06:22:34 PM PDT 24
Peak memory 200036 kb
Host smart-213a6ff4-6266-40a8-8ee3-c35e112bf683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374676158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3374676158
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1299069150
Short name T144
Test name
Test status
Simulation time 114998377 ps
CPU time 0.99 seconds
Started Jun 26 06:22:33 PM PDT 24
Finished Jun 26 06:22:36 PM PDT 24
Peak memory 200032 kb
Host smart-45819250-8add-4b28-939d-5c6097c31cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299069150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1299069150
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3158137155
Short name T136
Test name
Test status
Simulation time 83163281 ps
CPU time 0.84 seconds
Started Jun 26 06:21:19 PM PDT 24
Finished Jun 26 06:21:21 PM PDT 24
Peak memory 199880 kb
Host smart-7420bb50-24b3-411e-83e6-7be28c0ceee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158137155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3158137155
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2946895511
Short name T379
Test name
Test status
Simulation time 2340219012 ps
CPU time 7.89 seconds
Started Jun 26 06:21:19 PM PDT 24
Finished Jun 26 06:21:28 PM PDT 24
Peak memory 217884 kb
Host smart-2b1a30f8-4204-46a9-b294-1a9046295df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946895511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2946895511
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3559222102
Short name T218
Test name
Test status
Simulation time 244864565 ps
CPU time 1.06 seconds
Started Jun 26 06:21:22 PM PDT 24
Finished Jun 26 06:21:24 PM PDT 24
Peak memory 217400 kb
Host smart-ad0adfcb-1c01-4b87-8cbf-b162fc871ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559222102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3559222102
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2411507477
Short name T286
Test name
Test status
Simulation time 114916235 ps
CPU time 0.8 seconds
Started Jun 26 06:21:20 PM PDT 24
Finished Jun 26 06:21:23 PM PDT 24
Peak memory 199900 kb
Host smart-b86f34b5-c52f-4464-910b-08919092c1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411507477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2411507477
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1050444803
Short name T101
Test name
Test status
Simulation time 771777598 ps
CPU time 4.28 seconds
Started Jun 26 06:21:17 PM PDT 24
Finished Jun 26 06:21:22 PM PDT 24
Peak memory 200352 kb
Host smart-8a92d4e2-1e68-4da9-a324-9ec00e55cac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050444803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1050444803
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.359433024
Short name T80
Test name
Test status
Simulation time 19308473330 ps
CPU time 29.6 seconds
Started Jun 26 06:21:17 PM PDT 24
Finished Jun 26 06:21:47 PM PDT 24
Peak memory 217060 kb
Host smart-23456ee3-c207-4357-8c47-2fd767ad67e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359433024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.359433024
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2568991046
Short name T316
Test name
Test status
Simulation time 155075664 ps
CPU time 1.32 seconds
Started Jun 26 06:21:22 PM PDT 24
Finished Jun 26 06:21:25 PM PDT 24
Peak memory 200024 kb
Host smart-59d5df63-95ea-4e47-a536-678b8a68f22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568991046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2568991046
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.4188741548
Short name T533
Test name
Test status
Simulation time 126438798 ps
CPU time 1.23 seconds
Started Jun 26 06:21:16 PM PDT 24
Finished Jun 26 06:21:18 PM PDT 24
Peak memory 200340 kb
Host smart-7a25dbc9-4053-4066-9bee-3c58de037f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188741548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.4188741548
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.302678085
Short name T490
Test name
Test status
Simulation time 1930749223 ps
CPU time 8.81 seconds
Started Jun 26 06:21:19 PM PDT 24
Finished Jun 26 06:21:30 PM PDT 24
Peak memory 216392 kb
Host smart-6fffad0a-d3ac-400a-8249-41a8c8c6d045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302678085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.302678085
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3335734056
Short name T473
Test name
Test status
Simulation time 481127712 ps
CPU time 2.77 seconds
Started Jun 26 06:21:18 PM PDT 24
Finished Jun 26 06:21:21 PM PDT 24
Peak memory 208284 kb
Host smart-c450f64c-cf85-41c2-8541-7c2d334e5678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335734056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3335734056
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.836058150
Short name T499
Test name
Test status
Simulation time 135732031 ps
CPU time 1.17 seconds
Started Jun 26 06:21:19 PM PDT 24
Finished Jun 26 06:21:22 PM PDT 24
Peak memory 200100 kb
Host smart-5e617867-35c1-49e2-aba6-0218e9839f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836058150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.836058150
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.76953653
Short name T36
Test name
Test status
Simulation time 65775158 ps
CPU time 0.78 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:45 PM PDT 24
Peak memory 199864 kb
Host smart-787dbc1d-99f7-4fa6-9f4a-50562bc144c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76953653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.76953653
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.502273822
Short name T28
Test name
Test status
Simulation time 2173040404 ps
CPU time 8.42 seconds
Started Jun 26 06:22:37 PM PDT 24
Finished Jun 26 06:22:47 PM PDT 24
Peak memory 217772 kb
Host smart-3b2a7a83-372e-48ca-a023-4d3065f66ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502273822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.502273822
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2093038005
Short name T525
Test name
Test status
Simulation time 244032450 ps
CPU time 1.12 seconds
Started Jun 26 06:22:40 PM PDT 24
Finished Jun 26 06:22:43 PM PDT 24
Peak memory 217504 kb
Host smart-6ae43d68-407c-4a55-8e77-cf8d59607558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093038005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2093038005
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1348543221
Short name T331
Test name
Test status
Simulation time 123535318 ps
CPU time 0.79 seconds
Started Jun 26 06:22:29 PM PDT 24
Finished Jun 26 06:22:31 PM PDT 24
Peak memory 199892 kb
Host smart-437c8f44-6a57-45cd-8f42-8f4fac97cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348543221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1348543221
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1082946059
Short name T436
Test name
Test status
Simulation time 2177421990 ps
CPU time 7.3 seconds
Started Jun 26 06:22:33 PM PDT 24
Finished Jun 26 06:22:41 PM PDT 24
Peak memory 200416 kb
Host smart-74be7f84-e81d-4aed-aaa4-2b78695d9637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082946059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1082946059
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.96306948
Short name T245
Test name
Test status
Simulation time 182247602 ps
CPU time 1.31 seconds
Started Jun 26 06:22:33 PM PDT 24
Finished Jun 26 06:22:35 PM PDT 24
Peak memory 200080 kb
Host smart-65f4d7a2-61d1-4778-89fb-950d4f034345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96306948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.96306948
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3909180901
Short name T177
Test name
Test status
Simulation time 124374839 ps
CPU time 1.24 seconds
Started Jun 26 06:22:31 PM PDT 24
Finished Jun 26 06:22:33 PM PDT 24
Peak memory 200284 kb
Host smart-89c15539-4a51-4fdf-9753-15e6b57f768f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909180901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3909180901
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.4115043144
Short name T449
Test name
Test status
Simulation time 3696274375 ps
CPU time 15.54 seconds
Started Jun 26 06:22:38 PM PDT 24
Finished Jun 26 06:22:54 PM PDT 24
Peak memory 200420 kb
Host smart-de199f8d-e86b-4046-8913-65d8e1cfe6ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115043144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.4115043144
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1142189589
Short name T188
Test name
Test status
Simulation time 118832305 ps
CPU time 1.5 seconds
Started Jun 26 06:22:32 PM PDT 24
Finished Jun 26 06:22:34 PM PDT 24
Peak memory 200092 kb
Host smart-ce4ddef0-df95-4bfe-9b5e-fe62dbf8e273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142189589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1142189589
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2248628723
Short name T155
Test name
Test status
Simulation time 79573315 ps
CPU time 0.84 seconds
Started Jun 26 06:22:32 PM PDT 24
Finished Jun 26 06:22:34 PM PDT 24
Peak memory 200296 kb
Host smart-ef720d65-0403-47fe-b2d4-14c5a423724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248628723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2248628723
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.622379714
Short name T55
Test name
Test status
Simulation time 65358922 ps
CPU time 0.82 seconds
Started Jun 26 06:22:40 PM PDT 24
Finished Jun 26 06:22:43 PM PDT 24
Peak memory 199900 kb
Host smart-1c0b2e2b-55cc-4ee5-b9e6-e80cfa0b72a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622379714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.622379714
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.86818339
Short name T495
Test name
Test status
Simulation time 1223126604 ps
CPU time 6.01 seconds
Started Jun 26 06:22:37 PM PDT 24
Finished Jun 26 06:22:44 PM PDT 24
Peak memory 217760 kb
Host smart-37178679-7025-4e28-a019-2992df737d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86818339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.86818339
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2819974474
Short name T483
Test name
Test status
Simulation time 244120683 ps
CPU time 1.22 seconds
Started Jun 26 06:22:40 PM PDT 24
Finished Jun 26 06:22:43 PM PDT 24
Peak memory 217468 kb
Host smart-7c48b03a-88db-4d10-84c7-7b049cd6bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819974474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2819974474
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1861445769
Short name T511
Test name
Test status
Simulation time 150739179 ps
CPU time 0.84 seconds
Started Jun 26 06:22:42 PM PDT 24
Finished Jun 26 06:22:46 PM PDT 24
Peak memory 199888 kb
Host smart-8f500625-e0c6-4775-b6c2-97625440895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861445769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1861445769
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3695926935
Short name T294
Test name
Test status
Simulation time 901322869 ps
CPU time 4.66 seconds
Started Jun 26 06:22:40 PM PDT 24
Finished Jun 26 06:22:47 PM PDT 24
Peak memory 200360 kb
Host smart-602bb7c0-d16e-4cf5-8de9-5f8bf14ae106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695926935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3695926935
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2557866862
Short name T374
Test name
Test status
Simulation time 183458897 ps
CPU time 1.21 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:44 PM PDT 24
Peak memory 200080 kb
Host smart-90a1602c-55a1-4edd-9550-474e66a621fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557866862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2557866862
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3721279258
Short name T228
Test name
Test status
Simulation time 121446605 ps
CPU time 1.2 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:46 PM PDT 24
Peak memory 200288 kb
Host smart-7b377624-6c38-4d3e-8d7e-8ea83cefe7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721279258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3721279258
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2392919448
Short name T210
Test name
Test status
Simulation time 6625587579 ps
CPU time 27.36 seconds
Started Jun 26 06:22:40 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 208644 kb
Host smart-b9998e43-7897-411f-8223-a13243219022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392919448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2392919448
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1176770667
Short name T410
Test name
Test status
Simulation time 118323130 ps
CPU time 1.66 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:45 PM PDT 24
Peak memory 208216 kb
Host smart-5ed92084-4c25-4fb5-b5e2-f2c373bf0dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176770667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1176770667
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.979530391
Short name T333
Test name
Test status
Simulation time 114148735 ps
CPU time 0.97 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:45 PM PDT 24
Peak memory 200316 kb
Host smart-3e4d5916-5cd3-46ba-b01e-33fdf3be4cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979530391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.979530391
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2660244690
Short name T223
Test name
Test status
Simulation time 77064654 ps
CPU time 0.79 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:43 PM PDT 24
Peak memory 199876 kb
Host smart-58c3a7a6-3425-4757-870e-cff4c24d6723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660244690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2660244690
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.766180108
Short name T45
Test name
Test status
Simulation time 2385174792 ps
CPU time 8.09 seconds
Started Jun 26 06:22:38 PM PDT 24
Finished Jun 26 06:22:48 PM PDT 24
Peak memory 217872 kb
Host smart-131ff99d-88d2-4542-8696-fac9874891c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766180108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.766180108
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.761245262
Short name T197
Test name
Test status
Simulation time 244693318 ps
CPU time 1.25 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:44 PM PDT 24
Peak memory 217384 kb
Host smart-9fadd169-a2aa-43b1-9ab2-1dcf518bf461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761245262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.761245262
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.639727413
Short name T317
Test name
Test status
Simulation time 210067735 ps
CPU time 0.94 seconds
Started Jun 26 06:22:40 PM PDT 24
Finished Jun 26 06:22:42 PM PDT 24
Peak memory 199880 kb
Host smart-b3718fd4-46c7-4790-b9cc-66212ed6f3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639727413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.639727413
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3392245108
Short name T49
Test name
Test status
Simulation time 1882546149 ps
CPU time 7.83 seconds
Started Jun 26 06:22:43 PM PDT 24
Finished Jun 26 06:22:54 PM PDT 24
Peak memory 200244 kb
Host smart-6a97b3ca-a554-498f-a1db-0614d35d9618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392245108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3392245108
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.4182076026
Short name T381
Test name
Test status
Simulation time 109249605 ps
CPU time 1.05 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:45 PM PDT 24
Peak memory 200060 kb
Host smart-528991b6-83d1-4bf8-90eb-17a1bf99fcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182076026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.4182076026
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3695140182
Short name T314
Test name
Test status
Simulation time 113458015 ps
CPU time 1.25 seconds
Started Jun 26 06:22:39 PM PDT 24
Finished Jun 26 06:22:42 PM PDT 24
Peak memory 200272 kb
Host smart-463e1cfd-25ed-48d2-a203-62f88ccc9517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695140182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3695140182
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.4160962874
Short name T502
Test name
Test status
Simulation time 334123544 ps
CPU time 2.53 seconds
Started Jun 26 06:22:39 PM PDT 24
Finished Jun 26 06:22:43 PM PDT 24
Peak memory 200344 kb
Host smart-7e64c75b-264c-45a2-bd09-a65462169148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160962874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4160962874
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2377926181
Short name T401
Test name
Test status
Simulation time 119859167 ps
CPU time 1.52 seconds
Started Jun 26 06:22:42 PM PDT 24
Finished Jun 26 06:22:47 PM PDT 24
Peak memory 200020 kb
Host smart-1e02fac4-bb5c-472e-bf0b-5cec01172c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377926181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2377926181
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.142328934
Short name T279
Test name
Test status
Simulation time 69355790 ps
CPU time 0.76 seconds
Started Jun 26 06:22:44 PM PDT 24
Finished Jun 26 06:22:47 PM PDT 24
Peak memory 200112 kb
Host smart-9d9ea7c0-bb56-430f-b9fb-98920d009454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142328934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.142328934
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3119357233
Short name T195
Test name
Test status
Simulation time 69786645 ps
CPU time 0.82 seconds
Started Jun 26 06:22:39 PM PDT 24
Finished Jun 26 06:22:41 PM PDT 24
Peak memory 199864 kb
Host smart-27ed5730-f846-4175-8bb0-ddf302b6944e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119357233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3119357233
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3636944657
Short name T63
Test name
Test status
Simulation time 1223322993 ps
CPU time 5.63 seconds
Started Jun 26 06:22:39 PM PDT 24
Finished Jun 26 06:22:46 PM PDT 24
Peak memory 217696 kb
Host smart-7cf0cd93-b4bc-479b-87f7-f1e3f30c59f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636944657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3636944657
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1412906572
Short name T507
Test name
Test status
Simulation time 243567965 ps
CPU time 1.12 seconds
Started Jun 26 06:22:43 PM PDT 24
Finished Jun 26 06:22:47 PM PDT 24
Peak memory 217460 kb
Host smart-d22ecfca-82d6-4c77-a7b9-cc8e4f246005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412906572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1412906572
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2828119828
Short name T15
Test name
Test status
Simulation time 127495642 ps
CPU time 0.85 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:45 PM PDT 24
Peak memory 199908 kb
Host smart-29369036-bea0-47a0-a0b2-d338d0201682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828119828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2828119828
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.760755274
Short name T13
Test name
Test status
Simulation time 1461533095 ps
CPU time 5.58 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:49 PM PDT 24
Peak memory 200588 kb
Host smart-c983c0df-297b-43e4-86bb-85137f2ff788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760755274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.760755274
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.306208595
Short name T248
Test name
Test status
Simulation time 151776894 ps
CPU time 1.16 seconds
Started Jun 26 06:22:38 PM PDT 24
Finished Jun 26 06:22:40 PM PDT 24
Peak memory 200100 kb
Host smart-439f1d36-e8ce-4409-92a7-ba3087cd3c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306208595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.306208595
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3612440764
Short name T138
Test name
Test status
Simulation time 120283141 ps
CPU time 1.28 seconds
Started Jun 26 06:22:40 PM PDT 24
Finished Jun 26 06:22:43 PM PDT 24
Peak memory 200344 kb
Host smart-bfd2fcf0-cc51-448c-a430-7860f570af78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612440764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3612440764
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2830753104
Short name T334
Test name
Test status
Simulation time 204784471 ps
CPU time 1.41 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:44 PM PDT 24
Peak memory 199848 kb
Host smart-6dfcf24e-0691-4d3c-b7d0-17fa5392d2e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830753104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2830753104
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3102661071
Short name T250
Test name
Test status
Simulation time 367537080 ps
CPU time 2.44 seconds
Started Jun 26 06:22:38 PM PDT 24
Finished Jun 26 06:22:41 PM PDT 24
Peak memory 200080 kb
Host smart-adeaec72-affa-4635-907d-0758a023562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102661071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3102661071
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2147224303
Short name T257
Test name
Test status
Simulation time 177792036 ps
CPU time 1.21 seconds
Started Jun 26 06:22:42 PM PDT 24
Finished Jun 26 06:22:47 PM PDT 24
Peak memory 200116 kb
Host smart-efbeb42c-e15e-4bd6-9899-683cd19d4145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147224303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2147224303
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2256687328
Short name T46
Test name
Test status
Simulation time 68781754 ps
CPU time 0.81 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:43 PM PDT 24
Peak memory 199880 kb
Host smart-e50ea0ca-8156-40fc-a70e-3f0740c3aa84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256687328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2256687328
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1475610669
Short name T396
Test name
Test status
Simulation time 1886703858 ps
CPU time 7.06 seconds
Started Jun 26 06:22:43 PM PDT 24
Finished Jun 26 06:22:53 PM PDT 24
Peak memory 221580 kb
Host smart-490ee3cb-1951-4e3e-b0e9-684f90659893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475610669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1475610669
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1785388871
Short name T285
Test name
Test status
Simulation time 245697727 ps
CPU time 1.03 seconds
Started Jun 26 06:22:40 PM PDT 24
Finished Jun 26 06:22:42 PM PDT 24
Peak memory 217432 kb
Host smart-65d46f97-c681-40f8-a9f1-d019a4ecde9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785388871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1785388871
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.243622957
Short name T16
Test name
Test status
Simulation time 223414816 ps
CPU time 0.9 seconds
Started Jun 26 06:22:42 PM PDT 24
Finished Jun 26 06:22:46 PM PDT 24
Peak memory 199912 kb
Host smart-59834ed7-eb7d-455f-b464-28598c2340fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243622957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.243622957
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1216773917
Short name T158
Test name
Test status
Simulation time 1115000016 ps
CPU time 5.25 seconds
Started Jun 26 06:22:38 PM PDT 24
Finished Jun 26 06:22:44 PM PDT 24
Peak memory 200328 kb
Host smart-fa0bb4ae-1b27-4098-b4b1-27133097e697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216773917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1216773917
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1596555804
Short name T50
Test name
Test status
Simulation time 171620085 ps
CPU time 1.19 seconds
Started Jun 26 06:22:40 PM PDT 24
Finished Jun 26 06:22:43 PM PDT 24
Peak memory 200108 kb
Host smart-93f775b9-0f1b-4aac-8897-6edbfbff1a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596555804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1596555804
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2702326979
Short name T373
Test name
Test status
Simulation time 254535361 ps
CPU time 1.5 seconds
Started Jun 26 06:22:42 PM PDT 24
Finished Jun 26 06:22:47 PM PDT 24
Peak memory 200264 kb
Host smart-8d1c99df-d9fd-4f12-8ff3-52eb4ee00c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702326979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2702326979
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.271392022
Short name T404
Test name
Test status
Simulation time 3285173544 ps
CPU time 11.12 seconds
Started Jun 26 06:22:42 PM PDT 24
Finished Jun 26 06:22:56 PM PDT 24
Peak memory 200416 kb
Host smart-b43d79bb-a218-400f-96f1-f04f8725e75f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271392022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.271392022
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3217088459
Short name T489
Test name
Test status
Simulation time 387073772 ps
CPU time 2.39 seconds
Started Jun 26 06:22:39 PM PDT 24
Finished Jun 26 06:22:43 PM PDT 24
Peak memory 200076 kb
Host smart-41e185ae-56c7-4bc2-99c3-074a3eed0f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217088459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3217088459
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.424438790
Short name T227
Test name
Test status
Simulation time 101612634 ps
CPU time 0.95 seconds
Started Jun 26 06:22:40 PM PDT 24
Finished Jun 26 06:22:43 PM PDT 24
Peak memory 200024 kb
Host smart-4215c85f-aa1b-4693-bea0-90700c8c2a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424438790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.424438790
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2119244197
Short name T323
Test name
Test status
Simulation time 63328180 ps
CPU time 0.77 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:51 PM PDT 24
Peak memory 199900 kb
Host smart-bdaa9a50-9526-4a15-a5c5-910bde3e708e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119244197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2119244197
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2180110614
Short name T493
Test name
Test status
Simulation time 2358256040 ps
CPU time 7.75 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:51 PM PDT 24
Peak memory 217828 kb
Host smart-c5fbebbd-5002-473d-a256-5ce13d4e0e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180110614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2180110614
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1473372422
Short name T83
Test name
Test status
Simulation time 243958728 ps
CPU time 1.21 seconds
Started Jun 26 06:22:42 PM PDT 24
Finished Jun 26 06:22:47 PM PDT 24
Peak memory 217468 kb
Host smart-fc2e4184-94ab-474d-ac20-75aa409bd1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473372422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1473372422
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1069101615
Short name T20
Test name
Test status
Simulation time 130945429 ps
CPU time 0.79 seconds
Started Jun 26 06:22:38 PM PDT 24
Finished Jun 26 06:22:40 PM PDT 24
Peak memory 199900 kb
Host smart-884e9b6a-7cc0-46b8-bbd0-8c1fa4fbe13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069101615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1069101615
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3701167209
Short name T214
Test name
Test status
Simulation time 1588750981 ps
CPU time 6.17 seconds
Started Jun 26 06:22:42 PM PDT 24
Finished Jun 26 06:22:51 PM PDT 24
Peak memory 200356 kb
Host smart-aec6e325-40a3-4151-a95d-8a51e9b66a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701167209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3701167209
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3891486948
Short name T143
Test name
Test status
Simulation time 97160246 ps
CPU time 1 seconds
Started Jun 26 06:22:40 PM PDT 24
Finished Jun 26 06:22:42 PM PDT 24
Peak memory 200088 kb
Host smart-b449b10d-b3ca-4f78-be26-d6169f125689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891486948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3891486948
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4068906817
Short name T135
Test name
Test status
Simulation time 244693149 ps
CPU time 1.55 seconds
Started Jun 26 06:22:43 PM PDT 24
Finished Jun 26 06:22:48 PM PDT 24
Peak memory 200300 kb
Host smart-bd7d2490-729d-4ce1-945e-0df9dbb831eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068906817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4068906817
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2378015328
Short name T249
Test name
Test status
Simulation time 3246382555 ps
CPU time 14.91 seconds
Started Jun 26 06:22:42 PM PDT 24
Finished Jun 26 06:23:00 PM PDT 24
Peak memory 210396 kb
Host smart-3a7fe19f-08df-4484-9f2e-ca050ba7c919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378015328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2378015328
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3328870231
Short name T335
Test name
Test status
Simulation time 370667626 ps
CPU time 2.55 seconds
Started Jun 26 06:22:43 PM PDT 24
Finished Jun 26 06:22:48 PM PDT 24
Peak memory 200068 kb
Host smart-3bf25973-3f11-4415-956e-73bad2816c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328870231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3328870231
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2073141453
Short name T515
Test name
Test status
Simulation time 205945387 ps
CPU time 1.37 seconds
Started Jun 26 06:22:41 PM PDT 24
Finished Jun 26 06:22:45 PM PDT 24
Peak memory 200100 kb
Host smart-5eb016a2-961e-4884-86bd-00acece0b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073141453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2073141453
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2566288048
Short name T167
Test name
Test status
Simulation time 66819941 ps
CPU time 0.77 seconds
Started Jun 26 06:22:50 PM PDT 24
Finished Jun 26 06:22:53 PM PDT 24
Peak memory 199764 kb
Host smart-9f7e39bc-72d0-4128-87e4-ab2911bf82c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566288048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2566288048
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3367754198
Short name T464
Test name
Test status
Simulation time 2163123875 ps
CPU time 8.3 seconds
Started Jun 26 06:22:46 PM PDT 24
Finished Jun 26 06:22:56 PM PDT 24
Peak memory 217484 kb
Host smart-41d73030-fbcb-4eaf-ab16-6dce285a4f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367754198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3367754198
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2659090205
Short name T139
Test name
Test status
Simulation time 243246209 ps
CPU time 1.08 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:55 PM PDT 24
Peak memory 217452 kb
Host smart-ccfdcc7c-7c46-4cd3-bb15-2de839ae92e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659090205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2659090205
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2335391183
Short name T216
Test name
Test status
Simulation time 133867569 ps
CPU time 0.91 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:55 PM PDT 24
Peak memory 199924 kb
Host smart-c41a7a0d-cfb2-4067-8b88-cf15e5c3b795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335391183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2335391183
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1833415790
Short name T235
Test name
Test status
Simulation time 1152336124 ps
CPU time 5.36 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:56 PM PDT 24
Peak memory 200272 kb
Host smart-cfeb81ff-b771-40d1-a3a8-f73cb3d9e077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833415790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1833415790
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2969889171
Short name T263
Test name
Test status
Simulation time 150480680 ps
CPU time 1.16 seconds
Started Jun 26 06:22:50 PM PDT 24
Finished Jun 26 06:22:54 PM PDT 24
Peak memory 199992 kb
Host smart-fb0d3156-8379-4654-a67d-361d7a85723d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969889171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2969889171
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1077086670
Short name T2
Test name
Test status
Simulation time 202999765 ps
CPU time 1.61 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:56 PM PDT 24
Peak memory 200288 kb
Host smart-dbcf85c9-8d55-4a42-8f7e-abbde29765db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077086670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1077086670
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1758396383
Short name T99
Test name
Test status
Simulation time 6577753861 ps
CPU time 23.8 seconds
Started Jun 26 06:22:47 PM PDT 24
Finished Jun 26 06:23:12 PM PDT 24
Peak memory 200408 kb
Host smart-af6b9a23-aef4-4988-bad6-575ac04fe052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758396383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1758396383
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3588228842
Short name T291
Test name
Test status
Simulation time 141447121 ps
CPU time 1.84 seconds
Started Jun 26 06:22:48 PM PDT 24
Finished Jun 26 06:22:51 PM PDT 24
Peak memory 200068 kb
Host smart-6757f67d-9f55-4b6b-944b-dd7f6492b6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588228842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3588228842
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.4051560417
Short name T148
Test name
Test status
Simulation time 120650416 ps
CPU time 1.07 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:52 PM PDT 24
Peak memory 200088 kb
Host smart-8a658bf3-1f3f-42b1-bd0a-9979281c8b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051560417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4051560417
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.386780147
Short name T474
Test name
Test status
Simulation time 74703708 ps
CPU time 0.87 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:55 PM PDT 24
Peak memory 199880 kb
Host smart-e145ede1-872e-496d-8388-5ec89cb9cdf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386780147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.386780147
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.439019647
Short name T41
Test name
Test status
Simulation time 1907550073 ps
CPU time 7.73 seconds
Started Jun 26 06:22:47 PM PDT 24
Finished Jun 26 06:22:56 PM PDT 24
Peak memory 217756 kb
Host smart-b49441ca-a062-4a96-a5e7-65a700f42821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439019647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.439019647
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.29402836
Short name T356
Test name
Test status
Simulation time 244122610 ps
CPU time 1.05 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:53 PM PDT 24
Peak memory 217460 kb
Host smart-70fbe103-4de5-4e4f-888a-040b39a2906a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29402836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.29402836
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3548259207
Short name T266
Test name
Test status
Simulation time 232356528 ps
CPU time 0.93 seconds
Started Jun 26 06:22:48 PM PDT 24
Finished Jun 26 06:22:50 PM PDT 24
Peak memory 199840 kb
Host smart-869115fd-ac17-4a2f-9ec0-c85bcbe28e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548259207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3548259207
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3810848469
Short name T386
Test name
Test status
Simulation time 1003869709 ps
CPU time 4.76 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:56 PM PDT 24
Peak memory 200288 kb
Host smart-0218f6ff-549f-4374-8eb2-0f3169a7193c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810848469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3810848469
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2178622574
Short name T477
Test name
Test status
Simulation time 178442526 ps
CPU time 1.18 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:53 PM PDT 24
Peak memory 200080 kb
Host smart-7c9e6559-0d32-4705-a2b4-7dc84d98ce8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178622574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2178622574
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3746005462
Short name T536
Test name
Test status
Simulation time 203166616 ps
CPU time 1.51 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:55 PM PDT 24
Peak memory 200276 kb
Host smart-31908b1f-0926-4c90-8c68-83643b841714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746005462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3746005462
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.985847673
Short name T103
Test name
Test status
Simulation time 5707951335 ps
CPU time 19.13 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:23:10 PM PDT 24
Peak memory 208640 kb
Host smart-108daae2-87bd-4d7e-9860-9619eca483a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985847673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.985847673
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2703798548
Short name T416
Test name
Test status
Simulation time 373709096 ps
CPU time 2.18 seconds
Started Jun 26 06:22:48 PM PDT 24
Finished Jun 26 06:22:52 PM PDT 24
Peak memory 208288 kb
Host smart-ccc4c829-7d9a-464d-a2ea-3e1b5ba71277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703798548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2703798548
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1337727446
Short name T165
Test name
Test status
Simulation time 159272770 ps
CPU time 1.26 seconds
Started Jun 26 06:22:50 PM PDT 24
Finished Jun 26 06:22:54 PM PDT 24
Peak memory 200172 kb
Host smart-ffc66b68-ff65-4cef-994e-8c5dec570d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337727446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1337727446
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.224678614
Short name T326
Test name
Test status
Simulation time 94566043 ps
CPU time 0.86 seconds
Started Jun 26 06:22:50 PM PDT 24
Finished Jun 26 06:22:54 PM PDT 24
Peak memory 199864 kb
Host smart-f544408b-2313-42e5-b09b-0d19503783cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224678614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.224678614
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1604987980
Short name T251
Test name
Test status
Simulation time 1222575840 ps
CPU time 5.69 seconds
Started Jun 26 06:22:47 PM PDT 24
Finished Jun 26 06:22:54 PM PDT 24
Peak memory 217664 kb
Host smart-fe211877-3e22-44e6-8701-256a26313e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604987980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1604987980
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2251375621
Short name T268
Test name
Test status
Simulation time 243540642 ps
CPU time 1.07 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:55 PM PDT 24
Peak memory 217460 kb
Host smart-add0b965-9f3b-4e00-883a-793443fb717e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251375621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2251375621
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2357966236
Short name T14
Test name
Test status
Simulation time 114498116 ps
CPU time 0.82 seconds
Started Jun 26 06:22:47 PM PDT 24
Finished Jun 26 06:22:49 PM PDT 24
Peak memory 199868 kb
Host smart-6a574f9f-a239-4e87-b8f8-2a704f4ee894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357966236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2357966236
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1465015835
Short name T456
Test name
Test status
Simulation time 1431255046 ps
CPU time 6.41 seconds
Started Jun 26 06:22:48 PM PDT 24
Finished Jun 26 06:22:55 PM PDT 24
Peak memory 200352 kb
Host smart-25b994f0-ea9c-4f80-8cd4-e79608d079fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465015835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1465015835
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3549774108
Short name T520
Test name
Test status
Simulation time 103989693 ps
CPU time 1.01 seconds
Started Jun 26 06:22:50 PM PDT 24
Finished Jun 26 06:22:54 PM PDT 24
Peak memory 200084 kb
Host smart-c70326c7-7115-48ba-8572-f8f0967bd63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549774108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3549774108
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1680362659
Short name T180
Test name
Test status
Simulation time 118329020 ps
CPU time 1.26 seconds
Started Jun 26 06:22:46 PM PDT 24
Finished Jun 26 06:22:49 PM PDT 24
Peak memory 200284 kb
Host smart-fec2507b-a410-40f7-b9c1-7f109daf030f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680362659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1680362659
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.813819831
Short name T305
Test name
Test status
Simulation time 234734436 ps
CPU time 1.64 seconds
Started Jun 26 06:22:48 PM PDT 24
Finished Jun 26 06:22:52 PM PDT 24
Peak memory 200068 kb
Host smart-0e88b476-8a4e-44e3-8a4e-788c33724dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813819831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.813819831
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1833953818
Short name T380
Test name
Test status
Simulation time 350193623 ps
CPU time 2.24 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:53 PM PDT 24
Peak memory 200028 kb
Host smart-1bce5777-132b-445e-8fa6-e31e761cd0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833953818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1833953818
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3608606272
Short name T389
Test name
Test status
Simulation time 200484446 ps
CPU time 1.21 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:56 PM PDT 24
Peak memory 200108 kb
Host smart-aaf4f950-be98-4753-a264-b315cb500c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608606272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3608606272
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2793795793
Short name T488
Test name
Test status
Simulation time 78655456 ps
CPU time 0.86 seconds
Started Jun 26 06:22:48 PM PDT 24
Finished Jun 26 06:22:50 PM PDT 24
Peak memory 199844 kb
Host smart-aaf74cb7-6c6f-43dc-9706-e70a0d8437d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793795793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2793795793
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2525312596
Short name T42
Test name
Test status
Simulation time 1223409700 ps
CPU time 6.38 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:23:01 PM PDT 24
Peak memory 221688 kb
Host smart-59a49c0d-fb3d-451a-ae41-1ff0405394a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525312596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2525312596
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3377439188
Short name T254
Test name
Test status
Simulation time 244401828 ps
CPU time 1.12 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:52 PM PDT 24
Peak memory 217436 kb
Host smart-0b7934c9-55b1-427e-ab22-a5e33d460317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377439188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3377439188
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2109199208
Short name T171
Test name
Test status
Simulation time 188986137 ps
CPU time 0.88 seconds
Started Jun 26 06:22:46 PM PDT 24
Finished Jun 26 06:22:49 PM PDT 24
Peak memory 199908 kb
Host smart-3ca1a67b-4230-48ae-86ed-4eb50523fefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109199208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2109199208
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3895845958
Short name T47
Test name
Test status
Simulation time 1914462573 ps
CPU time 7.52 seconds
Started Jun 26 06:22:48 PM PDT 24
Finished Jun 26 06:22:57 PM PDT 24
Peak memory 200364 kb
Host smart-3ee57860-86f9-4e71-a403-c883c4c001e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895845958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3895845958
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1464677701
Short name T395
Test name
Test status
Simulation time 135399679 ps
CPU time 1.15 seconds
Started Jun 26 06:22:48 PM PDT 24
Finished Jun 26 06:22:51 PM PDT 24
Peak memory 200064 kb
Host smart-03d37370-530d-4915-a83e-9e9ea85569c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464677701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1464677701
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.192305583
Short name T149
Test name
Test status
Simulation time 233373468 ps
CPU time 1.48 seconds
Started Jun 26 06:22:47 PM PDT 24
Finished Jun 26 06:22:50 PM PDT 24
Peak memory 200276 kb
Host smart-6aa9ffcd-a702-4248-969b-db3685b8f29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192305583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.192305583
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2899986884
Short name T106
Test name
Test status
Simulation time 1920428748 ps
CPU time 7.61 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:23:02 PM PDT 24
Peak memory 200352 kb
Host smart-f1789d4e-b6ab-4696-91b7-977c38d8b999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899986884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2899986884
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3190140284
Short name T182
Test name
Test status
Simulation time 152539679 ps
CPU time 1.83 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:53 PM PDT 24
Peak memory 200084 kb
Host smart-08bc3fc5-c9c8-492f-be8e-5ddd8ebcc59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190140284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3190140284
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1985575287
Short name T157
Test name
Test status
Simulation time 114203761 ps
CPU time 0.99 seconds
Started Jun 26 06:22:47 PM PDT 24
Finished Jun 26 06:22:50 PM PDT 24
Peak memory 200104 kb
Host smart-e5b23ab7-75a3-46c5-b65c-3ded981fb4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985575287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1985575287
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3049949512
Short name T390
Test name
Test status
Simulation time 83315495 ps
CPU time 0.82 seconds
Started Jun 26 06:21:33 PM PDT 24
Finished Jun 26 06:21:36 PM PDT 24
Peak memory 200088 kb
Host smart-6b8938d8-adba-438e-8baf-c9722fe6d375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049949512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3049949512
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3732895033
Short name T21
Test name
Test status
Simulation time 2343929797 ps
CPU time 8.36 seconds
Started Jun 26 06:21:22 PM PDT 24
Finished Jun 26 06:21:32 PM PDT 24
Peak memory 217600 kb
Host smart-1eadcd00-193c-430a-9a2f-d772f8503dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732895033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3732895033
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2426085492
Short name T340
Test name
Test status
Simulation time 246709249 ps
CPU time 1.09 seconds
Started Jun 26 06:21:25 PM PDT 24
Finished Jun 26 06:21:27 PM PDT 24
Peak memory 217396 kb
Host smart-06d6049e-37cb-44b0-8e6e-edd2963e5bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426085492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2426085492
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1353658305
Short name T527
Test name
Test status
Simulation time 199662586 ps
CPU time 0.92 seconds
Started Jun 26 06:21:20 PM PDT 24
Finished Jun 26 06:21:23 PM PDT 24
Peak memory 199868 kb
Host smart-8eca44c8-8301-4ac9-8851-4edbb285257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353658305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1353658305
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.306313698
Short name T352
Test name
Test status
Simulation time 1821619216 ps
CPU time 6.43 seconds
Started Jun 26 06:21:23 PM PDT 24
Finished Jun 26 06:21:31 PM PDT 24
Peak memory 200360 kb
Host smart-70826b17-6406-4ad7-93f1-7f65fda2fe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306313698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.306313698
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3810838630
Short name T181
Test name
Test status
Simulation time 177234172 ps
CPU time 1.22 seconds
Started Jun 26 06:21:35 PM PDT 24
Finished Jun 26 06:21:38 PM PDT 24
Peak memory 200312 kb
Host smart-e7a2ae57-1242-4274-8763-58534c1a8593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810838630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3810838630
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2334989763
Short name T529
Test name
Test status
Simulation time 115909125 ps
CPU time 1.2 seconds
Started Jun 26 06:21:20 PM PDT 24
Finished Jun 26 06:21:23 PM PDT 24
Peak memory 200288 kb
Host smart-8770c00d-f52c-4dde-a093-4e93c0cd7669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334989763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2334989763
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1122455093
Short name T61
Test name
Test status
Simulation time 2138256925 ps
CPU time 7.58 seconds
Started Jun 26 06:21:25 PM PDT 24
Finished Jun 26 06:21:35 PM PDT 24
Peak memory 200384 kb
Host smart-ed2837f8-ac1d-4174-acd6-77faf6411ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122455093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1122455093
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3091687785
Short name T303
Test name
Test status
Simulation time 368817728 ps
CPU time 2.22 seconds
Started Jun 26 06:21:24 PM PDT 24
Finished Jun 26 06:21:27 PM PDT 24
Peak memory 200092 kb
Host smart-4827e375-57a9-4a43-b09f-4bfa11808554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091687785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3091687785
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2853338666
Short name T496
Test name
Test status
Simulation time 111985852 ps
CPU time 1.03 seconds
Started Jun 26 06:21:26 PM PDT 24
Finished Jun 26 06:21:29 PM PDT 24
Peak memory 200056 kb
Host smart-d9cab6ff-25e0-43b9-8ab1-5eee562949d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853338666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2853338666
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.886703406
Short name T173
Test name
Test status
Simulation time 76906554 ps
CPU time 0.81 seconds
Started Jun 26 06:21:24 PM PDT 24
Finished Jun 26 06:21:26 PM PDT 24
Peak memory 199740 kb
Host smart-bf3feca6-b5fb-498a-8311-e92da4a7eb79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886703406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.886703406
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2636466741
Short name T52
Test name
Test status
Simulation time 1216502959 ps
CPU time 6 seconds
Started Jun 26 06:21:26 PM PDT 24
Finished Jun 26 06:21:34 PM PDT 24
Peak memory 217756 kb
Host smart-89b8ee42-7f4f-4149-8f66-8adb91cdb323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636466741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2636466741
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.4185515534
Short name T253
Test name
Test status
Simulation time 245290651 ps
CPU time 1.08 seconds
Started Jun 26 06:21:25 PM PDT 24
Finished Jun 26 06:21:28 PM PDT 24
Peak memory 217460 kb
Host smart-4be80076-9178-42ea-89a0-32213ca98a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185515534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.4185515534
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1834293988
Short name T514
Test name
Test status
Simulation time 169573784 ps
CPU time 0.92 seconds
Started Jun 26 06:21:24 PM PDT 24
Finished Jun 26 06:21:27 PM PDT 24
Peak memory 199904 kb
Host smart-5d0e632e-5d7f-48cb-b654-39f56ea428a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834293988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1834293988
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1422148856
Short name T355
Test name
Test status
Simulation time 1596505725 ps
CPU time 6.3 seconds
Started Jun 26 06:21:24 PM PDT 24
Finished Jun 26 06:21:32 PM PDT 24
Peak memory 200300 kb
Host smart-a0d3d8c2-d87b-46b2-a1f0-3d1174aa02a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422148856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1422148856
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.562527387
Short name T524
Test name
Test status
Simulation time 187233455 ps
CPU time 1.3 seconds
Started Jun 26 06:21:27 PM PDT 24
Finished Jun 26 06:21:30 PM PDT 24
Peak memory 200116 kb
Host smart-5b06d5fb-c9b1-4f98-8aeb-daacc080be0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562527387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.562527387
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.148918825
Short name T440
Test name
Test status
Simulation time 260988373 ps
CPU time 1.56 seconds
Started Jun 26 06:21:33 PM PDT 24
Finished Jun 26 06:21:37 PM PDT 24
Peak memory 200264 kb
Host smart-3bf54878-7f48-4cf4-b961-8123e768d044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148918825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.148918825
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.500283585
Short name T318
Test name
Test status
Simulation time 2541802995 ps
CPU time 10.01 seconds
Started Jun 26 06:21:35 PM PDT 24
Finished Jun 26 06:21:47 PM PDT 24
Peak memory 200644 kb
Host smart-56855d99-2136-49ac-8c56-cbc21f80beb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500283585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.500283585
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1327100867
Short name T443
Test name
Test status
Simulation time 139730352 ps
CPU time 1.78 seconds
Started Jun 26 06:21:28 PM PDT 24
Finished Jun 26 06:21:31 PM PDT 24
Peak memory 200292 kb
Host smart-d5087d54-a7ab-40d8-9b5f-299893f36805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327100867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1327100867
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.771530847
Short name T238
Test name
Test status
Simulation time 220080472 ps
CPU time 1.49 seconds
Started Jun 26 06:21:25 PM PDT 24
Finished Jun 26 06:21:28 PM PDT 24
Peak memory 200000 kb
Host smart-0409ed55-86d5-4ca1-83eb-34603e9fc931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771530847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.771530847
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3070371744
Short name T207
Test name
Test status
Simulation time 76528405 ps
CPU time 0.84 seconds
Started Jun 26 06:21:27 PM PDT 24
Finished Jun 26 06:21:30 PM PDT 24
Peak memory 199864 kb
Host smart-2d3a4d79-01a0-4f1f-92bb-bf0f56c311a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070371744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3070371744
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.173307790
Short name T344
Test name
Test status
Simulation time 2187791765 ps
CPU time 7.89 seconds
Started Jun 26 06:21:28 PM PDT 24
Finished Jun 26 06:21:38 PM PDT 24
Peak memory 217560 kb
Host smart-13000351-6470-4034-866c-be4396610bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173307790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.173307790
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1245873657
Short name T498
Test name
Test status
Simulation time 244408214 ps
CPU time 1.09 seconds
Started Jun 26 06:21:31 PM PDT 24
Finished Jun 26 06:21:33 PM PDT 24
Peak memory 217456 kb
Host smart-5bf41d3e-abe1-4137-a65f-1a7b167032b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245873657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1245873657
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1235808688
Short name T176
Test name
Test status
Simulation time 145159275 ps
CPU time 0.81 seconds
Started Jun 26 06:21:27 PM PDT 24
Finished Jun 26 06:21:29 PM PDT 24
Peak memory 199904 kb
Host smart-fd9da556-fed8-4e6c-93ac-f3bad5326ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235808688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1235808688
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2898816754
Short name T275
Test name
Test status
Simulation time 1054404240 ps
CPU time 5.46 seconds
Started Jun 26 06:21:24 PM PDT 24
Finished Jun 26 06:21:31 PM PDT 24
Peak memory 200408 kb
Host smart-08aab50c-98c6-4c34-8660-d02c116ad40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898816754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2898816754
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3854548024
Short name T187
Test name
Test status
Simulation time 153197503 ps
CPU time 1.4 seconds
Started Jun 26 06:21:31 PM PDT 24
Finished Jun 26 06:21:34 PM PDT 24
Peak memory 200084 kb
Host smart-bde0b2e8-9c01-418d-9925-b0e417263e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854548024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3854548024
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2232753141
Short name T44
Test name
Test status
Simulation time 255731629 ps
CPU time 1.61 seconds
Started Jun 26 06:21:26 PM PDT 24
Finished Jun 26 06:21:30 PM PDT 24
Peak memory 200296 kb
Host smart-c752b100-0db3-4d22-a82e-87494f677e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232753141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2232753141
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2115988222
Short name T526
Test name
Test status
Simulation time 10534149768 ps
CPU time 39.39 seconds
Started Jun 26 06:21:24 PM PDT 24
Finished Jun 26 06:22:04 PM PDT 24
Peak memory 200400 kb
Host smart-41a8c037-24ce-4996-934b-92586aab5831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115988222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2115988222
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3316015052
Short name T359
Test name
Test status
Simulation time 125740971 ps
CPU time 1.73 seconds
Started Jun 26 06:21:26 PM PDT 24
Finished Jun 26 06:21:30 PM PDT 24
Peak memory 200092 kb
Host smart-de2a0e9d-4a84-4205-845f-c835d8c89b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316015052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3316015052
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3682526957
Short name T247
Test name
Test status
Simulation time 140115343 ps
CPU time 1.09 seconds
Started Jun 26 06:21:27 PM PDT 24
Finished Jun 26 06:21:30 PM PDT 24
Peak memory 200104 kb
Host smart-f42cadc3-b58d-4997-b6c4-62379f2eea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682526957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3682526957
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2703413967
Short name T361
Test name
Test status
Simulation time 73233031 ps
CPU time 0.83 seconds
Started Jun 26 06:21:25 PM PDT 24
Finished Jun 26 06:21:27 PM PDT 24
Peak memory 199868 kb
Host smart-874f6557-f59b-4617-96cc-7d92739f56f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703413967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2703413967
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1153866771
Short name T38
Test name
Test status
Simulation time 1224507329 ps
CPU time 5.4 seconds
Started Jun 26 06:21:24 PM PDT 24
Finished Jun 26 06:21:31 PM PDT 24
Peak memory 217548 kb
Host smart-623783f3-e058-42af-b02c-cbbfe99aff64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153866771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1153866771
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2223491977
Short name T281
Test name
Test status
Simulation time 244829988 ps
CPU time 1.09 seconds
Started Jun 26 06:21:28 PM PDT 24
Finished Jun 26 06:21:31 PM PDT 24
Peak memory 217468 kb
Host smart-d09e1a83-57d2-42ab-a802-4b8ed0129aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223491977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2223491977
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.4287712921
Short name T427
Test name
Test status
Simulation time 101662320 ps
CPU time 0.89 seconds
Started Jun 26 06:21:25 PM PDT 24
Finished Jun 26 06:21:27 PM PDT 24
Peak memory 199908 kb
Host smart-cbebfc11-d97f-445a-9745-7ac13aa3f85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287712921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.4287712921
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1350454375
Short name T370
Test name
Test status
Simulation time 844376683 ps
CPU time 4.18 seconds
Started Jun 26 06:21:27 PM PDT 24
Finished Jun 26 06:21:33 PM PDT 24
Peak memory 200388 kb
Host smart-f23c44bc-e0f7-40ab-bcec-1a5412828241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350454375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1350454375
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3423145851
Short name T190
Test name
Test status
Simulation time 98116494 ps
CPU time 1.01 seconds
Started Jun 26 06:21:24 PM PDT 24
Finished Jun 26 06:21:27 PM PDT 24
Peak memory 200016 kb
Host smart-82038a4b-75bd-4a5a-a215-38b60e76d686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423145851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3423145851
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1122688388
Short name T22
Test name
Test status
Simulation time 258323733 ps
CPU time 1.54 seconds
Started Jun 26 06:21:27 PM PDT 24
Finished Jun 26 06:21:30 PM PDT 24
Peak memory 200296 kb
Host smart-4bd413b6-214a-48bd-99e4-7c7d1af05e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122688388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1122688388
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.60369401
Short name T530
Test name
Test status
Simulation time 9503106048 ps
CPU time 34.69 seconds
Started Jun 26 06:21:26 PM PDT 24
Finished Jun 26 06:22:02 PM PDT 24
Peak memory 208608 kb
Host smart-de334c7c-2760-48d5-8a5a-e6a1fa8eadd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60369401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.60369401
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.515479131
Short name T206
Test name
Test status
Simulation time 122163212 ps
CPU time 1.53 seconds
Started Jun 26 06:21:28 PM PDT 24
Finished Jun 26 06:21:31 PM PDT 24
Peak memory 200112 kb
Host smart-16f86ea2-14f8-403c-b418-53ccdbe65ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515479131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.515479131
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.164527581
Short name T307
Test name
Test status
Simulation time 159039659 ps
CPU time 1.24 seconds
Started Jun 26 06:21:27 PM PDT 24
Finished Jun 26 06:21:30 PM PDT 24
Peak memory 200524 kb
Host smart-b6c9122e-5bad-45a7-acb4-dedcd4d9e096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164527581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.164527581
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3590678093
Short name T392
Test name
Test status
Simulation time 65409923 ps
CPU time 0.76 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:21:36 PM PDT 24
Peak memory 199904 kb
Host smart-bb4b85c9-30a9-4756-9d4d-1c359960b260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590678093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3590678093
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.452456500
Short name T421
Test name
Test status
Simulation time 1903710379 ps
CPU time 8.28 seconds
Started Jun 26 06:21:36 PM PDT 24
Finished Jun 26 06:21:46 PM PDT 24
Peak memory 217564 kb
Host smart-1eaa0c4c-4316-40b4-a230-f076f7913241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452456500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.452456500
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1258017880
Short name T159
Test name
Test status
Simulation time 244359965 ps
CPU time 1.16 seconds
Started Jun 26 06:21:30 PM PDT 24
Finished Jun 26 06:21:32 PM PDT 24
Peak memory 217440 kb
Host smart-1c435631-be20-45d1-b4e1-7d005e6304c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258017880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1258017880
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.685161770
Short name T8
Test name
Test status
Simulation time 131623382 ps
CPU time 0.85 seconds
Started Jun 26 06:21:34 PM PDT 24
Finished Jun 26 06:21:36 PM PDT 24
Peak memory 199864 kb
Host smart-b258748e-8deb-4c02-87d6-e3155c459822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685161770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.685161770
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.40869269
Short name T417
Test name
Test status
Simulation time 1729375366 ps
CPU time 7.09 seconds
Started Jun 26 06:21:33 PM PDT 24
Finished Jun 26 06:21:42 PM PDT 24
Peak memory 200368 kb
Host smart-74cd71b8-bab7-4909-aab2-c47c35309aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40869269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.40869269
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2350416053
Short name T500
Test name
Test status
Simulation time 98662329 ps
CPU time 1.06 seconds
Started Jun 26 06:21:35 PM PDT 24
Finished Jun 26 06:21:38 PM PDT 24
Peak memory 200028 kb
Host smart-72cdc511-1ae7-4529-9f85-22ac10f790b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350416053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2350416053
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3826652990
Short name T508
Test name
Test status
Simulation time 247443067 ps
CPU time 1.68 seconds
Started Jun 26 06:21:26 PM PDT 24
Finished Jun 26 06:21:30 PM PDT 24
Peak memory 200276 kb
Host smart-98ec322e-e800-4ef4-a317-daf4fa59cd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826652990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3826652990
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1745730138
Short name T505
Test name
Test status
Simulation time 140241452 ps
CPU time 1.87 seconds
Started Jun 26 06:21:32 PM PDT 24
Finished Jun 26 06:21:35 PM PDT 24
Peak memory 200068 kb
Host smart-8d725597-5251-47da-9b88-e762809a78e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745730138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1745730138
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2389090558
Short name T319
Test name
Test status
Simulation time 154323529 ps
CPU time 1.19 seconds
Started Jun 26 06:21:35 PM PDT 24
Finished Jun 26 06:21:38 PM PDT 24
Peak memory 200092 kb
Host smart-4d317151-ed8f-4a17-8542-02bd17b9deaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389090558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2389090558
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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