Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7163

1

T1

1

T5

17

T6

27

auto[1]

10237

1

T1

1

T5

84

T6

30

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5411	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	5977	1			T1	1		T2	1		T3	1
reset_info_cp[2]	2650	1			T5	15		T6	7		T7	34
reset_info_cp[4]	3481	1			T5	19		T6	10		T7	73
reset_info_cp[8]	97	1			T7	3		T9	1		T12	2
reset_info_cp[16]	95	1			T7	2		T10	1		T26	1
reset_info_cp[32]	101	1			T7	2		T9	1		T12	1
reset_info_cp[64]	90	1			T11	1		T82	1		T95	1
reset_info_cp[128]	118	1			T5	1		T7	1		T12	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2842	1			T5	17		T6	13		T7	48
reset_info_cp[1]	auto[1]	2515	1			T5	9		T6	13		T7	52
reset_info_cp[2]	auto[0]	788	1			T6	3		T7	12		T11	3
reset_info_cp[2]	auto[1]	1862	1			T5	15		T6	4		T7	22
reset_info_cp[4]	auto[0]	1206	1			T6	5		T7	31		T11	6
reset_info_cp[4]	auto[1]	2275	1			T5	19		T6	5		T7	42
reset_info_cp[8]	auto[0]	40	1			T7	2		T82	1		T95	1
reset_info_cp[8]	auto[1]	57	1			T7	1		T9	1		T12	2
reset_info_cp[16]	auto[0]	36	1			T10	1		T26	1		T95	1
reset_info_cp[16]	auto[1]	59	1			T7	2		T27	1		T28	1
reset_info_cp[32]	auto[0]	40	1			T7	1		T145	1		T146	2
reset_info_cp[32]	auto[1]	61	1			T7	1		T9	1		T12	1
reset_info_cp[64]	auto[0]	36	1			T82	1		T144	1		T98	1
reset_info_cp[64]	auto[1]	54	1			T11	1		T95	1		T35	1
reset_info_cp[128]	auto[0]	53	1			T26	1		T95	1		T104	1
reset_info_cp[128]	auto[1]	65	1			T5	1		T7	1		T12	1