Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T541 /workspace/coverage/default/0.rstmgr_smoke.4058538816 Jun 27 05:40:32 PM PDT 24 Jun 27 05:40:34 PM PDT 24 206649239 ps
T542 /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1267458116 Jun 27 05:40:53 PM PDT 24 Jun 27 05:40:57 PM PDT 24 244703520 ps
T543 /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.159115715 Jun 27 05:42:23 PM PDT 24 Jun 27 05:42:30 PM PDT 24 243703034 ps
T544 /workspace/coverage/default/21.rstmgr_por_stretcher.3273391036 Jun 27 05:41:29 PM PDT 24 Jun 27 05:41:32 PM PDT 24 141406577 ps
T545 /workspace/coverage/default/7.rstmgr_reset.3700759211 Jun 27 05:41:06 PM PDT 24 Jun 27 05:41:13 PM PDT 24 1565910107 ps
T47 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.533156515 Jun 27 04:58:16 PM PDT 24 Jun 27 04:58:18 PM PDT 24 70081597 ps
T48 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1639300364 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:22 PM PDT 24 78938547 ps
T49 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2095857352 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:28 PM PDT 24 54106942 ps
T546 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.604547603 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:28 PM PDT 24 68816122 ps
T547 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.892088047 Jun 27 04:58:39 PM PDT 24 Jun 27 04:58:43 PM PDT 24 82787388 ps
T94 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1758670703 Jun 27 04:58:20 PM PDT 24 Jun 27 04:58:24 PM PDT 24 82274979 ps
T50 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2964331057 Jun 27 04:58:18 PM PDT 24 Jun 27 04:58:22 PM PDT 24 78075712 ps
T51 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2912668151 Jun 27 04:58:42 PM PDT 24 Jun 27 04:58:46 PM PDT 24 426526633 ps
T52 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1680222554 Jun 27 04:58:24 PM PDT 24 Jun 27 04:58:34 PM PDT 24 920630299 ps
T53 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3317993949 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:28 PM PDT 24 502706473 ps
T54 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2534304618 Jun 27 04:58:37 PM PDT 24 Jun 27 04:58:41 PM PDT 24 159564693 ps
T548 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3198956743 Jun 27 04:58:49 PM PDT 24 Jun 27 04:58:52 PM PDT 24 78914777 ps
T57 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2339649463 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:29 PM PDT 24 989867695 ps
T55 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2164492056 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:29 PM PDT 24 125441802 ps
T105 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.916370959 Jun 27 04:58:20 PM PDT 24 Jun 27 04:58:24 PM PDT 24 146282780 ps
T56 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.192295855 Jun 27 04:58:38 PM PDT 24 Jun 27 04:58:41 PM PDT 24 81825363 ps
T86 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1857404270 Jun 27 04:58:18 PM PDT 24 Jun 27 04:58:23 PM PDT 24 1011669600 ps
T106 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1869377962 Jun 27 04:58:23 PM PDT 24 Jun 27 04:58:31 PM PDT 24 60981145 ps
T87 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3396143091 Jun 27 04:58:24 PM PDT 24 Jun 27 04:58:33 PM PDT 24 107493981 ps
T549 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2566720013 Jun 27 04:58:18 PM PDT 24 Jun 27 04:58:24 PM PDT 24 485318408 ps
T88 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2830932421 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:28 PM PDT 24 148440247 ps
T89 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.926438615 Jun 27 04:58:48 PM PDT 24 Jun 27 04:58:52 PM PDT 24 118442799 ps
T550 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1409305596 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:30 PM PDT 24 64700211 ps
T119 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1268803638 Jun 27 04:58:23 PM PDT 24 Jun 27 04:58:32 PM PDT 24 800361959 ps
T90 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.260272366 Jun 27 04:58:20 PM PDT 24 Jun 27 04:58:26 PM PDT 24 103481156 ps
T113 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2783704177 Jun 27 04:58:36 PM PDT 24 Jun 27 04:58:39 PM PDT 24 208863634 ps
T124 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.524748338 Jun 27 04:58:49 PM PDT 24 Jun 27 04:58:54 PM PDT 24 461900546 ps
T107 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.6465190 Jun 27 04:58:40 PM PDT 24 Jun 27 04:58:44 PM PDT 24 132616699 ps
T551 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1167092614 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:26 PM PDT 24 800541603 ps
T123 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4165936235 Jun 27 04:58:20 PM PDT 24 Jun 27 04:58:24 PM PDT 24 183067035 ps
T552 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2056605037 Jun 27 04:58:37 PM PDT 24 Jun 27 04:58:40 PM PDT 24 188024244 ps
T114 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3978720298 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:25 PM PDT 24 392079332 ps
T108 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.573676049 Jun 27 04:58:37 PM PDT 24 Jun 27 04:58:39 PM PDT 24 223068085 ps
T553 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2133183597 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:32 PM PDT 24 487117124 ps
T554 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2037364378 Jun 27 04:58:40 PM PDT 24 Jun 27 04:58:45 PM PDT 24 151776220 ps
T122 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2545737147 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:24 PM PDT 24 208165600 ps
T555 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2367597344 Jun 27 04:58:20 PM PDT 24 Jun 27 04:58:25 PM PDT 24 125160710 ps
T556 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4279320144 Jun 27 04:58:37 PM PDT 24 Jun 27 04:58:40 PM PDT 24 258125330 ps
T109 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2264701591 Jun 27 04:58:43 PM PDT 24 Jun 27 04:58:47 PM PDT 24 152567921 ps
T121 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4210803806 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:26 PM PDT 24 593878130 ps
T557 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2220958470 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:29 PM PDT 24 107570556 ps
T110 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.836410562 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:29 PM PDT 24 115814533 ps
T558 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2282415723 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:27 PM PDT 24 107565133 ps
T111 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1952522362 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:23 PM PDT 24 272068653 ps
T139 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.769088244 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:28 PM PDT 24 479620117 ps
T559 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.610424701 Jun 27 04:58:37 PM PDT 24 Jun 27 04:58:40 PM PDT 24 136070875 ps
T112 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.26599865 Jun 27 04:58:24 PM PDT 24 Jun 27 04:58:32 PM PDT 24 86116694 ps
T560 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3422161610 Jun 27 04:58:39 PM PDT 24 Jun 27 04:58:43 PM PDT 24 133206024 ps
T561 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3572531795 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:31 PM PDT 24 481484386 ps
T562 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.737314749 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:28 PM PDT 24 66413494 ps
T140 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2447409400 Jun 27 04:58:35 PM PDT 24 Jun 27 04:58:38 PM PDT 24 793913586 ps
T563 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.459868558 Jun 27 04:58:48 PM PDT 24 Jun 27 04:58:52 PM PDT 24 436156721 ps
T564 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3701086542 Jun 27 04:58:23 PM PDT 24 Jun 27 04:58:32 PM PDT 24 448877267 ps
T565 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.281389763 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:30 PM PDT 24 113945928 ps
T566 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3045485831 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:30 PM PDT 24 253565491 ps
T567 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4135481048 Jun 27 04:58:39 PM PDT 24 Jun 27 04:58:45 PM PDT 24 529366186 ps
T568 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.360437592 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:22 PM PDT 24 99318834 ps
T569 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1993075685 Jun 27 04:58:20 PM PDT 24 Jun 27 04:58:26 PM PDT 24 198572639 ps
T570 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3939156021 Jun 27 04:58:23 PM PDT 24 Jun 27 04:58:31 PM PDT 24 148649199 ps
T571 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3083993812 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:30 PM PDT 24 132321933 ps
T115 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3658770711 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:25 PM PDT 24 791207594 ps
T572 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1830704441 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:30 PM PDT 24 201957056 ps
T573 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.415879656 Jun 27 04:58:20 PM PDT 24 Jun 27 04:58:27 PM PDT 24 320112873 ps
T574 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3549616777 Jun 27 04:58:38 PM PDT 24 Jun 27 04:58:41 PM PDT 24 84284244 ps
T575 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3174571329 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:25 PM PDT 24 219665582 ps
T576 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1776008179 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:30 PM PDT 24 254119225 ps
T577 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2630346110 Jun 27 04:58:18 PM PDT 24 Jun 27 04:58:20 PM PDT 24 142980572 ps
T578 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3212237293 Jun 27 04:58:18 PM PDT 24 Jun 27 04:58:21 PM PDT 24 110907867 ps
T579 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.814162343 Jun 27 04:58:25 PM PDT 24 Jun 27 04:58:36 PM PDT 24 665253587 ps
T580 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1170383748 Jun 27 04:58:23 PM PDT 24 Jun 27 04:58:32 PM PDT 24 343740738 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1573071723 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:28 PM PDT 24 63483803 ps
T582 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3502443751 Jun 27 04:58:39 PM PDT 24 Jun 27 04:58:42 PM PDT 24 91534852 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1879162218 Jun 27 04:58:20 PM PDT 24 Jun 27 04:58:26 PM PDT 24 106579780 ps
T584 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2388534179 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:22 PM PDT 24 78938592 ps
T118 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2048658103 Jun 27 04:58:18 PM PDT 24 Jun 27 04:58:23 PM PDT 24 947669209 ps
T585 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4041950491 Jun 27 04:57:58 PM PDT 24 Jun 27 04:58:03 PM PDT 24 342947387 ps
T586 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3816742013 Jun 27 04:58:48 PM PDT 24 Jun 27 04:58:52 PM PDT 24 137822147 ps
T587 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2282946619 Jun 27 04:58:18 PM PDT 24 Jun 27 04:58:21 PM PDT 24 81653371 ps
T588 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2956785344 Jun 27 04:58:43 PM PDT 24 Jun 27 04:58:48 PM PDT 24 149739753 ps
T589 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3137038082 Jun 27 04:58:48 PM PDT 24 Jun 27 04:58:53 PM PDT 24 267118005 ps
T590 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3987616584 Jun 27 04:58:17 PM PDT 24 Jun 27 04:58:19 PM PDT 24 180655720 ps
T591 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3456414426 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:28 PM PDT 24 145788152 ps
T120 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.928084895 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:24 PM PDT 24 718752775 ps
T592 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2886369186 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:26 PM PDT 24 65943584 ps
T593 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.422560165 Jun 27 04:58:41 PM PDT 24 Jun 27 04:58:45 PM PDT 24 74162341 ps
T594 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.14584028 Jun 27 04:58:23 PM PDT 24 Jun 27 04:58:30 PM PDT 24 70577640 ps
T595 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1076636235 Jun 27 04:58:23 PM PDT 24 Jun 27 04:58:33 PM PDT 24 934587605 ps
T596 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3976826060 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:27 PM PDT 24 78702082 ps
T597 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.491578022 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:23 PM PDT 24 212648283 ps
T141 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2886353518 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:30 PM PDT 24 949153995 ps
T598 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3759270227 Jun 27 04:58:46 PM PDT 24 Jun 27 04:58:51 PM PDT 24 132455675 ps
T599 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3875175993 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:26 PM PDT 24 80531658 ps
T600 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1466419322 Jun 27 04:58:36 PM PDT 24 Jun 27 04:58:38 PM PDT 24 86864036 ps
T601 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3809740893 Jun 27 04:58:25 PM PDT 24 Jun 27 04:58:33 PM PDT 24 96872723 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3220547659 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:29 PM PDT 24 476793285 ps
T603 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.567015590 Jun 27 04:58:47 PM PDT 24 Jun 27 04:58:51 PM PDT 24 103996712 ps
T116 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.200065268 Jun 27 04:58:24 PM PDT 24 Jun 27 04:58:33 PM PDT 24 412650687 ps
T604 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1826099639 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:29 PM PDT 24 209038629 ps
T605 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2462040325 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:31 PM PDT 24 214984251 ps
T606 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3233405659 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:30 PM PDT 24 131161108 ps
T607 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3652551633 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:28 PM PDT 24 78566978 ps
T608 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.456871041 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:28 PM PDT 24 132655499 ps
T609 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1960202445 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:24 PM PDT 24 149956894 ps
T610 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2257142468 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:28 PM PDT 24 135207800 ps
T611 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2956294446 Jun 27 04:58:20 PM PDT 24 Jun 27 04:58:25 PM PDT 24 98651336 ps
T117 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1429955725 Jun 27 04:58:38 PM PDT 24 Jun 27 04:58:43 PM PDT 24 967543926 ps
T612 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3871515136 Jun 27 04:58:18 PM PDT 24 Jun 27 04:58:25 PM PDT 24 810836959 ps
T613 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1418069879 Jun 27 04:58:19 PM PDT 24 Jun 27 04:58:24 PM PDT 24 426233256 ps
T614 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.994570085 Jun 27 04:58:21 PM PDT 24 Jun 27 04:58:27 PM PDT 24 127730216 ps
T615 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3196405802 Jun 27 04:58:23 PM PDT 24 Jun 27 04:58:31 PM PDT 24 131452503 ps
T616 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2795188037 Jun 27 04:58:42 PM PDT 24 Jun 27 04:58:46 PM PDT 24 69194193 ps
T617 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1969308080 Jun 27 04:58:20 PM PDT 24 Jun 27 04:58:26 PM PDT 24 803210055 ps
T618 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3041979073 Jun 27 04:58:20 PM PDT 24 Jun 27 04:58:25 PM PDT 24 98582104 ps
T619 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.529344754 Jun 27 04:58:22 PM PDT 24 Jun 27 04:58:31 PM PDT 24 254582660 ps
T620 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4108048449 Jun 27 04:58:40 PM PDT 24 Jun 27 04:58:47 PM PDT 24 1239038240 ps

Test location /workspace/coverage/default/19.rstmgr_stress_all.4251641416
Short name T7
Test name
Test status
Simulation time 7808269793 ps
CPU time 27.72 seconds
Started Jun 27 05:41:34 PM PDT 24
Finished Jun 27 05:42:05 PM PDT 24
Peak memory 208600 kb
Host smart-f0dc165a-9f8b-4558-b408-b36599e40776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251641416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.4251641416
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.545753524
Short name T3
Test name
Test status
Simulation time 419030982 ps
CPU time 2.39 seconds
Started Jun 27 05:41:08 PM PDT 24
Finished Jun 27 05:41:11 PM PDT 24
Peak memory 208288 kb
Host smart-89bf5812-dceb-4321-8a9f-ee3ce37ca4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545753524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.545753524
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2339649463
Short name T57
Test name
Test status
Simulation time 989867695 ps
CPU time 3.2 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:29 PM PDT 24
Peak memory 200432 kb
Host smart-61dbe730-1400-4f75-a8c4-a318068c8666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339649463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2339649463
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.945792127
Short name T63
Test name
Test status
Simulation time 16507961473 ps
CPU time 27.94 seconds
Started Jun 27 05:40:34 PM PDT 24
Finished Jun 27 05:41:03 PM PDT 24
Peak memory 217244 kb
Host smart-8ff6cf1d-9d2c-4d3b-89d1-c3c07d5a9858
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945792127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.945792127
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1516212815
Short name T5
Test name
Test status
Simulation time 2169178864 ps
CPU time 8.31 seconds
Started Jun 27 05:41:07 PM PDT 24
Finished Jun 27 05:41:17 PM PDT 24
Peak memory 217800 kb
Host smart-3fb3a301-55d4-489c-bf6a-59dd09a76417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516212815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1516212815
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2534304618
Short name T54
Test name
Test status
Simulation time 159564693 ps
CPU time 2.35 seconds
Started Jun 27 04:58:37 PM PDT 24
Finished Jun 27 04:58:41 PM PDT 24
Peak memory 208528 kb
Host smart-52dbef48-3eb6-4f64-9362-59d96880daa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534304618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2534304618
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3181694696
Short name T100
Test name
Test status
Simulation time 11379672622 ps
CPU time 44.71 seconds
Started Jun 27 05:41:27 PM PDT 24
Finished Jun 27 05:42:13 PM PDT 24
Peak memory 208600 kb
Host smart-90905c4a-f355-436e-b5bf-1418c72dbfb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181694696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3181694696
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3066823503
Short name T150
Test name
Test status
Simulation time 74575521 ps
CPU time 0.77 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:41:33 PM PDT 24
Peak memory 199820 kb
Host smart-52e809bb-d02e-45fe-a03c-edf9a2081b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066823503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3066823503
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2912668151
Short name T51
Test name
Test status
Simulation time 426526633 ps
CPU time 1.73 seconds
Started Jun 27 04:58:42 PM PDT 24
Finished Jun 27 04:58:46 PM PDT 24
Peak memory 200372 kb
Host smart-f1c43c95-b657-4f2f-89b5-05bed4fc7917
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912668151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2912668151
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1122613337
Short name T142
Test name
Test status
Simulation time 104277575 ps
CPU time 0.98 seconds
Started Jun 27 05:40:41 PM PDT 24
Finished Jun 27 05:40:43 PM PDT 24
Peak memory 199988 kb
Host smart-c5403137-b884-4d48-b697-c20e6816bab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122613337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1122613337
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.4135405983
Short name T27
Test name
Test status
Simulation time 1229042494 ps
CPU time 5.89 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:12 PM PDT 24
Peak memory 217732 kb
Host smart-a98ad263-aa1d-4a1d-8e08-2f54ea1bf215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135405983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.4135405983
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2758306761
Short name T145
Test name
Test status
Simulation time 10356229955 ps
CPU time 37.43 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:42:09 PM PDT 24
Peak memory 200388 kb
Host smart-95adf488-1f12-4355-8e0f-4709be1a1c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758306761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2758306761
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4279320144
Short name T556
Test name
Test status
Simulation time 258125330 ps
CPU time 2.02 seconds
Started Jun 27 04:58:37 PM PDT 24
Finished Jun 27 04:58:40 PM PDT 24
Peak memory 200172 kb
Host smart-886c3f77-1e0d-4cdb-98f3-00d2e33449a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279320144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4279320144
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.769088244
Short name T139
Test name
Test status
Simulation time 479620117 ps
CPU time 2.11 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 200372 kb
Host smart-79313d33-497a-40db-8b17-f12dc90aa2e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769088244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
769088244
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1246056850
Short name T180
Test name
Test status
Simulation time 65649644 ps
CPU time 0.76 seconds
Started Jun 27 05:41:13 PM PDT 24
Finished Jun 27 05:41:19 PM PDT 24
Peak memory 200044 kb
Host smart-c5978d79-4265-4c18-8494-9571aee85677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246056850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1246056850
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1429955725
Short name T117
Test name
Test status
Simulation time 967543926 ps
CPU time 3.08 seconds
Started Jun 27 04:58:38 PM PDT 24
Finished Jun 27 04:58:43 PM PDT 24
Peak memory 200292 kb
Host smart-bb2ad8f1-51ba-436d-bc25-9da87298689c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429955725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1429955725
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2095857352
Short name T49
Test name
Test status
Simulation time 54106942 ps
CPU time 0.73 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 200216 kb
Host smart-badbdfa4-4200-40a9-bdbc-2737cecb474d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095857352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2095857352
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3680789019
Short name T22
Test name
Test status
Simulation time 167611807 ps
CPU time 0.86 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:16 PM PDT 24
Peak memory 199884 kb
Host smart-49ad3d16-3748-4489-bf7f-4289a9ace643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680789019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3680789019
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1928143197
Short name T44
Test name
Test status
Simulation time 1893162823 ps
CPU time 7.06 seconds
Started Jun 27 05:40:33 PM PDT 24
Finished Jun 27 05:40:41 PM PDT 24
Peak memory 217740 kb
Host smart-3b2483ad-cc95-415a-bba6-f4a6ff768561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928143197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1928143197
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1268803638
Short name T119
Test name
Test status
Simulation time 800361959 ps
CPU time 2.83 seconds
Started Jun 27 04:58:23 PM PDT 24
Finished Jun 27 04:58:32 PM PDT 24
Peak memory 200448 kb
Host smart-547f8aeb-638b-4018-a1a8-8115a495a59e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268803638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1268803638
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2138674521
Short name T207
Test name
Test status
Simulation time 5144653196 ps
CPU time 22.57 seconds
Started Jun 27 05:41:15 PM PDT 24
Finished Jun 27 05:41:42 PM PDT 24
Peak memory 208576 kb
Host smart-68f969e0-04d0-487f-a28f-8b45073f3735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138674521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2138674521
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1960202445
Short name T609
Test name
Test status
Simulation time 149956894 ps
CPU time 2.08 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:24 PM PDT 24
Peak memory 200348 kb
Host smart-6fb20d28-3743-486b-9613-fa0602b5c2c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960202445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
960202445
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2566720013
Short name T549
Test name
Test status
Simulation time 485318408 ps
CPU time 5.34 seconds
Started Jun 27 04:58:18 PM PDT 24
Finished Jun 27 04:58:24 PM PDT 24
Peak memory 200248 kb
Host smart-de8afb7d-e4ee-465f-8d6f-7fbb635cedaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566720013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
566720013
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3041979073
Short name T618
Test name
Test status
Simulation time 98582104 ps
CPU time 0.81 seconds
Started Jun 27 04:58:20 PM PDT 24
Finished Jun 27 04:58:25 PM PDT 24
Peak memory 200220 kb
Host smart-20d472d5-fa15-48ea-8fb2-afa8b845bb7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041979073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
041979073
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.260272366
Short name T90
Test name
Test status
Simulation time 103481156 ps
CPU time 0.92 seconds
Started Jun 27 04:58:20 PM PDT 24
Finished Jun 27 04:58:26 PM PDT 24
Peak memory 200180 kb
Host smart-dab63b1d-e1b8-4cda-9fe3-b08c78f4b3fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260272366 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.260272366
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3652551633
Short name T607
Test name
Test status
Simulation time 78566978 ps
CPU time 0.85 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 200216 kb
Host smart-938c7023-4a4b-4872-a0f5-26eb6327a0e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652551633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3652551633
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2388534179
Short name T584
Test name
Test status
Simulation time 78938592 ps
CPU time 0.99 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:22 PM PDT 24
Peak memory 200276 kb
Host smart-91cbb9b0-0c9b-4acf-ac32-cb621052d5a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388534179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2388534179
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4041950491
Short name T585
Test name
Test status
Simulation time 342947387 ps
CPU time 2.19 seconds
Started Jun 27 04:57:58 PM PDT 24
Finished Jun 27 04:58:03 PM PDT 24
Peak memory 208372 kb
Host smart-6e700060-cb6e-4bb8-b0aa-2e0a7be41276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041950491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.4041950491
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2048658103
Short name T118
Test name
Test status
Simulation time 947669209 ps
CPU time 3.14 seconds
Started Jun 27 04:58:18 PM PDT 24
Finished Jun 27 04:58:23 PM PDT 24
Peak memory 200444 kb
Host smart-b637be6f-084f-4a0e-9069-db31adadf9c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048658103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2048658103
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.491578022
Short name T597
Test name
Test status
Simulation time 212648283 ps
CPU time 1.57 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:23 PM PDT 24
Peak memory 200356 kb
Host smart-398e6a80-a5ec-4640-a8db-ca6dd9e98d56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491578022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.491578022
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1167092614
Short name T551
Test name
Test status
Simulation time 800541603 ps
CPU time 4.47 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:26 PM PDT 24
Peak memory 200328 kb
Host smart-692b6423-3425-48fb-9d34-bf47ed553f67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167092614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
167092614
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2257142468
Short name T610
Test name
Test status
Simulation time 135207800 ps
CPU time 0.96 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 200224 kb
Host smart-033b47e6-1655-41f5-945c-90d34e8d65d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257142468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
257142468
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3212237293
Short name T578
Test name
Test status
Simulation time 110907867 ps
CPU time 0.97 seconds
Started Jun 27 04:58:18 PM PDT 24
Finished Jun 27 04:58:21 PM PDT 24
Peak memory 200328 kb
Host smart-94fead33-57e9-4bb1-9e5b-972687ba08c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212237293 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3212237293
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3875175993
Short name T599
Test name
Test status
Simulation time 80531658 ps
CPU time 0.83 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:26 PM PDT 24
Peak memory 200216 kb
Host smart-7bcd241e-e024-4a17-bcf2-f53cbc7e8a08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875175993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3875175993
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.994570085
Short name T614
Test name
Test status
Simulation time 127730216 ps
CPU time 1.27 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:27 PM PDT 24
Peak memory 200416 kb
Host smart-06bd1cf7-3e19-4fb5-838e-bbf766f6843e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994570085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.994570085
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.415879656
Short name T573
Test name
Test status
Simulation time 320112873 ps
CPU time 2.13 seconds
Started Jun 27 04:58:20 PM PDT 24
Finished Jun 27 04:58:27 PM PDT 24
Peak memory 208616 kb
Host smart-b88ceca1-1f5d-4f43-8431-685f837be2b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415879656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.415879656
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3083993812
Short name T571
Test name
Test status
Simulation time 132321933 ps
CPU time 1.09 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 208388 kb
Host smart-127a1012-4668-4a4c-a7a2-73ad6416ad10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083993812 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3083993812
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.737314749
Short name T562
Test name
Test status
Simulation time 66413494 ps
CPU time 0.79 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 200232 kb
Host smart-44f70353-2f9d-4c31-a6ad-c887f251a917
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737314749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.737314749
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3456414426
Short name T591
Test name
Test status
Simulation time 145788152 ps
CPU time 1.04 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 200096 kb
Host smart-810f647f-46c9-4abd-bfa9-46242f4def20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456414426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3456414426
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2462040325
Short name T605
Test name
Test status
Simulation time 214984251 ps
CPU time 1.77 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:31 PM PDT 24
Peak memory 208596 kb
Host smart-4da76361-2934-40f6-a2cb-01260eb19da0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462040325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2462040325
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3809740893
Short name T601
Test name
Test status
Simulation time 96872723 ps
CPU time 1 seconds
Started Jun 27 04:58:25 PM PDT 24
Finished Jun 27 04:58:33 PM PDT 24
Peak memory 208644 kb
Host smart-d6dd9f96-4de4-4485-bbaa-0bd3a9ea329e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809740893 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3809740893
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2956294446
Short name T611
Test name
Test status
Simulation time 98651336 ps
CPU time 1.3 seconds
Started Jun 27 04:58:20 PM PDT 24
Finished Jun 27 04:58:25 PM PDT 24
Peak memory 200596 kb
Host smart-3ba406e2-4020-4824-ae19-433a8699c842
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956294446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2956294446
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.814162343
Short name T579
Test name
Test status
Simulation time 665253587 ps
CPU time 3.93 seconds
Started Jun 27 04:58:25 PM PDT 24
Finished Jun 27 04:58:36 PM PDT 24
Peak memory 208508 kb
Host smart-18baced2-5d64-445a-ad1a-b4349895e05e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814162343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.814162343
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3317993949
Short name T53
Test name
Test status
Simulation time 502706473 ps
CPU time 1.98 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 200472 kb
Host smart-5ffb5aff-c9e1-48d3-b4dd-7ff1da7b1b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317993949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3317993949
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3196405802
Short name T615
Test name
Test status
Simulation time 131452503 ps
CPU time 1.43 seconds
Started Jun 27 04:58:23 PM PDT 24
Finished Jun 27 04:58:31 PM PDT 24
Peak memory 208572 kb
Host smart-65c33b25-75c0-47cd-8e5b-6030b79404c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196405802 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3196405802
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1869377962
Short name T106
Test name
Test status
Simulation time 60981145 ps
CPU time 0.79 seconds
Started Jun 27 04:58:23 PM PDT 24
Finished Jun 27 04:58:31 PM PDT 24
Peak memory 200100 kb
Host smart-1eee8a11-535c-4dd9-80e9-578cea7cfdca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869377962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1869377962
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.26599865
Short name T112
Test name
Test status
Simulation time 86116694 ps
CPU time 1 seconds
Started Jun 27 04:58:24 PM PDT 24
Finished Jun 27 04:58:32 PM PDT 24
Peak memory 200244 kb
Host smart-fb89f96e-1714-4d0d-91f1-aa48a7c2e4ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26599865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sam
e_csr_outstanding.26599865
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3396143091
Short name T87
Test name
Test status
Simulation time 107493981 ps
CPU time 1.53 seconds
Started Jun 27 04:58:24 PM PDT 24
Finished Jun 27 04:58:33 PM PDT 24
Peak memory 216628 kb
Host smart-e26479f4-6918-4485-9ec2-e49058cf95d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396143091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3396143091
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.200065268
Short name T116
Test name
Test status
Simulation time 412650687 ps
CPU time 1.81 seconds
Started Jun 27 04:58:24 PM PDT 24
Finished Jun 27 04:58:33 PM PDT 24
Peak memory 200392 kb
Host smart-6b42407a-47ad-4e70-a50f-50ba90ec48dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200065268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.200065268
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3816742013
Short name T586
Test name
Test status
Simulation time 137822147 ps
CPU time 1.02 seconds
Started Jun 27 04:58:48 PM PDT 24
Finished Jun 27 04:58:52 PM PDT 24
Peak memory 200320 kb
Host smart-23b2d9fa-3807-4057-b164-5ef35d7da1de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816742013 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3816742013
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.14584028
Short name T594
Test name
Test status
Simulation time 70577640 ps
CPU time 0.75 seconds
Started Jun 27 04:58:23 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 200144 kb
Host smart-677ee3e4-5ca3-464d-af30-8eff45597e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14584028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.14584028
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3939156021
Short name T570
Test name
Test status
Simulation time 148649199 ps
CPU time 1.09 seconds
Started Jun 27 04:58:23 PM PDT 24
Finished Jun 27 04:58:31 PM PDT 24
Peak memory 200124 kb
Host smart-4fb6e9b1-e4e6-4660-8332-dd0ee64ec092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939156021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3939156021
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3701086542
Short name T564
Test name
Test status
Simulation time 448877267 ps
CPU time 3.03 seconds
Started Jun 27 04:58:23 PM PDT 24
Finished Jun 27 04:58:32 PM PDT 24
Peak memory 208508 kb
Host smart-66c62b60-ea21-4e39-9506-f5500d2d4882
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701086542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3701086542
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1680222554
Short name T52
Test name
Test status
Simulation time 920630299 ps
CPU time 3.07 seconds
Started Jun 27 04:58:24 PM PDT 24
Finished Jun 27 04:58:34 PM PDT 24
Peak memory 200440 kb
Host smart-c3b626a6-faaa-442f-9d55-00707bd93077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680222554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1680222554
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2056605037
Short name T552
Test name
Test status
Simulation time 188024244 ps
CPU time 1.33 seconds
Started Jun 27 04:58:37 PM PDT 24
Finished Jun 27 04:58:40 PM PDT 24
Peak memory 208516 kb
Host smart-b9ee0bfe-92ea-451e-8879-21dda41bc92e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056605037 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2056605037
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.892088047
Short name T547
Test name
Test status
Simulation time 82787388 ps
CPU time 0.86 seconds
Started Jun 27 04:58:39 PM PDT 24
Finished Jun 27 04:58:43 PM PDT 24
Peak memory 200192 kb
Host smart-63ae119c-d15b-43a2-a89c-830fdd104f94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892088047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.892088047
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3759270227
Short name T598
Test name
Test status
Simulation time 132455675 ps
CPU time 1.34 seconds
Started Jun 27 04:58:46 PM PDT 24
Finished Jun 27 04:58:51 PM PDT 24
Peak memory 200392 kb
Host smart-ac2dda50-98da-48e5-9356-9b0158cb938c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759270227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3759270227
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.459868558
Short name T563
Test name
Test status
Simulation time 436156721 ps
CPU time 1.74 seconds
Started Jun 27 04:58:48 PM PDT 24
Finished Jun 27 04:58:52 PM PDT 24
Peak memory 200452 kb
Host smart-d91f7d10-a5cf-4f10-8300-6f4194cf7fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459868558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.459868558
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.610424701
Short name T559
Test name
Test status
Simulation time 136070875 ps
CPU time 1.14 seconds
Started Jun 27 04:58:37 PM PDT 24
Finished Jun 27 04:58:40 PM PDT 24
Peak memory 200280 kb
Host smart-1bec7449-7dc3-40f5-8636-9c81f41d18b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610424701 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.610424701
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2795188037
Short name T616
Test name
Test status
Simulation time 69194193 ps
CPU time 0.79 seconds
Started Jun 27 04:58:42 PM PDT 24
Finished Jun 27 04:58:46 PM PDT 24
Peak memory 200060 kb
Host smart-37177865-3405-41b7-8cc9-8fef18ebe15b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795188037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2795188037
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.573676049
Short name T108
Test name
Test status
Simulation time 223068085 ps
CPU time 1.39 seconds
Started Jun 27 04:58:37 PM PDT 24
Finished Jun 27 04:58:39 PM PDT 24
Peak memory 200460 kb
Host smart-e0b4e6a3-b21d-419f-a411-6b89fb016032
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573676049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.573676049
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4108048449
Short name T620
Test name
Test status
Simulation time 1239038240 ps
CPU time 3.82 seconds
Started Jun 27 04:58:40 PM PDT 24
Finished Jun 27 04:58:47 PM PDT 24
Peak memory 200436 kb
Host smart-e74d64ec-6fea-408d-8756-8f6e12a2e52a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108048449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.4108048449
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3422161610
Short name T560
Test name
Test status
Simulation time 133206024 ps
CPU time 1.46 seconds
Started Jun 27 04:58:39 PM PDT 24
Finished Jun 27 04:58:43 PM PDT 24
Peak memory 208644 kb
Host smart-4686f57a-5848-4100-a475-a1659862ceb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422161610 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3422161610
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3502443751
Short name T582
Test name
Test status
Simulation time 91534852 ps
CPU time 0.86 seconds
Started Jun 27 04:58:39 PM PDT 24
Finished Jun 27 04:58:42 PM PDT 24
Peak memory 200216 kb
Host smart-0074a510-c4a2-4fe6-91d8-065e16466f88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502443751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3502443751
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1466419322
Short name T600
Test name
Test status
Simulation time 86864036 ps
CPU time 0.94 seconds
Started Jun 27 04:58:36 PM PDT 24
Finished Jun 27 04:58:38 PM PDT 24
Peak memory 200276 kb
Host smart-816d739d-1926-43e9-9da8-fcbf16003786
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466419322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1466419322
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2783704177
Short name T113
Test name
Test status
Simulation time 208863634 ps
CPU time 1.74 seconds
Started Jun 27 04:58:36 PM PDT 24
Finished Jun 27 04:58:39 PM PDT 24
Peak memory 216456 kb
Host smart-765ba750-fc0d-422d-9220-234d145f1e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783704177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2783704177
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.926438615
Short name T89
Test name
Test status
Simulation time 118442799 ps
CPU time 1.18 seconds
Started Jun 27 04:58:48 PM PDT 24
Finished Jun 27 04:58:52 PM PDT 24
Peak memory 208556 kb
Host smart-86929310-fe55-456c-9d0c-98efc0cb60b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926438615 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.926438615
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3549616777
Short name T574
Test name
Test status
Simulation time 84284244 ps
CPU time 0.81 seconds
Started Jun 27 04:58:38 PM PDT 24
Finished Jun 27 04:58:41 PM PDT 24
Peak memory 200164 kb
Host smart-37798348-a7ba-4435-b8e4-f9f8b317c707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549616777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3549616777
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2264701591
Short name T109
Test name
Test status
Simulation time 152567921 ps
CPU time 1.17 seconds
Started Jun 27 04:58:43 PM PDT 24
Finished Jun 27 04:58:47 PM PDT 24
Peak memory 200276 kb
Host smart-c9b08103-4c70-4588-949e-cf49e3a4bf98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264701591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2264701591
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2956785344
Short name T588
Test name
Test status
Simulation time 149739753 ps
CPU time 1.99 seconds
Started Jun 27 04:58:43 PM PDT 24
Finished Jun 27 04:58:48 PM PDT 24
Peak memory 208540 kb
Host smart-37ba5d76-5ecd-4bca-a09b-4c560540c7b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956785344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2956785344
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.524748338
Short name T124
Test name
Test status
Simulation time 461900546 ps
CPU time 2.11 seconds
Started Jun 27 04:58:49 PM PDT 24
Finished Jun 27 04:58:54 PM PDT 24
Peak memory 200112 kb
Host smart-1214a1de-4be0-452f-a014-297ade752f45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524748338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.524748338
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2037364378
Short name T554
Test name
Test status
Simulation time 151776220 ps
CPU time 1.36 seconds
Started Jun 27 04:58:40 PM PDT 24
Finished Jun 27 04:58:45 PM PDT 24
Peak memory 208440 kb
Host smart-8000f8c6-1052-482b-871e-f54dabf7e0b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037364378 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2037364378
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.422560165
Short name T593
Test name
Test status
Simulation time 74162341 ps
CPU time 0.79 seconds
Started Jun 27 04:58:41 PM PDT 24
Finished Jun 27 04:58:45 PM PDT 24
Peak memory 200192 kb
Host smart-117b11c1-4b86-4f20-a063-6a70aca96b4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422560165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.422560165
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.6465190
Short name T107
Test name
Test status
Simulation time 132616699 ps
CPU time 1.24 seconds
Started Jun 27 04:58:40 PM PDT 24
Finished Jun 27 04:58:44 PM PDT 24
Peak memory 200468 kb
Host smart-044f18de-c5da-4af4-97f3-ab2f21f82fe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6465190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same
_csr_outstanding.6465190
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4135481048
Short name T567
Test name
Test status
Simulation time 529366186 ps
CPU time 3.56 seconds
Started Jun 27 04:58:39 PM PDT 24
Finished Jun 27 04:58:45 PM PDT 24
Peak memory 208572 kb
Host smart-02cf7e88-c057-4573-8784-438495d120ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135481048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.4135481048
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.567015590
Short name T603
Test name
Test status
Simulation time 103996712 ps
CPU time 1.14 seconds
Started Jun 27 04:58:47 PM PDT 24
Finished Jun 27 04:58:51 PM PDT 24
Peak memory 208528 kb
Host smart-a54d1a39-3353-4f53-aac4-1b884bd1bee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567015590 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.567015590
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3198956743
Short name T548
Test name
Test status
Simulation time 78914777 ps
CPU time 0.82 seconds
Started Jun 27 04:58:49 PM PDT 24
Finished Jun 27 04:58:52 PM PDT 24
Peak memory 199912 kb
Host smart-495a6128-383b-4d28-b885-ed0bc9c4854a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198956743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3198956743
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3137038082
Short name T589
Test name
Test status
Simulation time 267118005 ps
CPU time 1.59 seconds
Started Jun 27 04:58:48 PM PDT 24
Finished Jun 27 04:58:53 PM PDT 24
Peak memory 200376 kb
Host smart-ac4e6039-1882-4e68-b3bc-a50a3cca4cdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137038082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3137038082
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.192295855
Short name T56
Test name
Test status
Simulation time 81825363 ps
CPU time 1.19 seconds
Started Jun 27 04:58:38 PM PDT 24
Finished Jun 27 04:58:41 PM PDT 24
Peak memory 208320 kb
Host smart-2a0a718e-6cfb-4ffa-abde-f5cf5bf22662
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192295855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.192295855
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2447409400
Short name T140
Test name
Test status
Simulation time 793913586 ps
CPU time 2.68 seconds
Started Jun 27 04:58:35 PM PDT 24
Finished Jun 27 04:58:38 PM PDT 24
Peak memory 200412 kb
Host smart-1c11dde3-1214-4618-977c-6169c20ae9cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447409400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2447409400
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1879162218
Short name T583
Test name
Test status
Simulation time 106579780 ps
CPU time 1.26 seconds
Started Jun 27 04:58:20 PM PDT 24
Finished Jun 27 04:58:26 PM PDT 24
Peak memory 200340 kb
Host smart-f434e941-b825-4ee3-b461-df5c7889fca1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879162218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
879162218
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3572531795
Short name T561
Test name
Test status
Simulation time 481484386 ps
CPU time 5.63 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:31 PM PDT 24
Peak memory 200272 kb
Host smart-9cf72e23-6438-4859-b072-66695d7c788b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572531795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
572531795
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.456871041
Short name T608
Test name
Test status
Simulation time 132655499 ps
CPU time 0.96 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 200188 kb
Host smart-f23c9f32-d7ef-4409-a00c-e401b591646b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456871041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.456871041
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.281389763
Short name T565
Test name
Test status
Simulation time 113945928 ps
CPU time 0.88 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 200340 kb
Host smart-28d0bbd4-db97-4dc1-b42b-76b7f13146aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281389763 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.281389763
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1758670703
Short name T94
Test name
Test status
Simulation time 82274979 ps
CPU time 0.87 seconds
Started Jun 27 04:58:20 PM PDT 24
Finished Jun 27 04:58:24 PM PDT 24
Peak memory 200136 kb
Host smart-ef1c8c3d-acd2-4701-8006-1bb8fd90cb39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758670703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1758670703
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2282946619
Short name T587
Test name
Test status
Simulation time 81653371 ps
CPU time 0.95 seconds
Started Jun 27 04:58:18 PM PDT 24
Finished Jun 27 04:58:21 PM PDT 24
Peak memory 200032 kb
Host smart-e041f33d-3693-4e24-b620-c5dc6805aa69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282946619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2282946619
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3987616584
Short name T590
Test name
Test status
Simulation time 180655720 ps
CPU time 1.54 seconds
Started Jun 27 04:58:17 PM PDT 24
Finished Jun 27 04:58:19 PM PDT 24
Peak memory 208300 kb
Host smart-7c2bb2ce-1eef-4af3-8c85-eeb726710f00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987616584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3987616584
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1857404270
Short name T86
Test name
Test status
Simulation time 1011669600 ps
CPU time 3.2 seconds
Started Jun 27 04:58:18 PM PDT 24
Finished Jun 27 04:58:23 PM PDT 24
Peak memory 200328 kb
Host smart-8828fa30-ecc6-461d-bc46-cfc330a01622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857404270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1857404270
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2282415723
Short name T558
Test name
Test status
Simulation time 107565133 ps
CPU time 1.32 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:27 PM PDT 24
Peak memory 200336 kb
Host smart-6f654356-c42b-4d9a-944c-5bb374439107
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282415723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
282415723
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2133183597
Short name T553
Test name
Test status
Simulation time 487117124 ps
CPU time 5.85 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:32 PM PDT 24
Peak memory 200344 kb
Host smart-c0a0058c-82cd-4b95-92ee-c72735a7f79b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133183597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
133183597
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.360437592
Short name T568
Test name
Test status
Simulation time 99318834 ps
CPU time 0.81 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:22 PM PDT 24
Peak memory 200396 kb
Host smart-0d24f75c-6a5b-4543-8ba5-c38d37d173f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360437592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.360437592
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2830932421
Short name T88
Test name
Test status
Simulation time 148440247 ps
CPU time 1.1 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 210824 kb
Host smart-a19d5b33-7d0f-42d4-9c0a-11ccc1bdde84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830932421 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2830932421
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.533156515
Short name T47
Test name
Test status
Simulation time 70081597 ps
CPU time 0.78 seconds
Started Jun 27 04:58:16 PM PDT 24
Finished Jun 27 04:58:18 PM PDT 24
Peak memory 200216 kb
Host smart-135d7bef-8ba5-43b4-97cb-e5f349c56a50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533156515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.533156515
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3233405659
Short name T606
Test name
Test status
Simulation time 131161108 ps
CPU time 1.13 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 200124 kb
Host smart-7a047f10-f66c-481c-962b-55b0e6cb67d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233405659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3233405659
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4210803806
Short name T121
Test name
Test status
Simulation time 593878130 ps
CPU time 4.18 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:26 PM PDT 24
Peak memory 208520 kb
Host smart-330aed50-32aa-4285-857a-5e86f7547869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210803806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.4210803806
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2886353518
Short name T141
Test name
Test status
Simulation time 949153995 ps
CPU time 3.12 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 200420 kb
Host smart-9b8eecf2-b3c9-4099-af9e-822f5ed17ca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886353518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2886353518
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1826099639
Short name T604
Test name
Test status
Simulation time 209038629 ps
CPU time 1.54 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:29 PM PDT 24
Peak memory 200244 kb
Host smart-7292cd88-8119-40d3-b84a-b22b63d883d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826099639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
826099639
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3871515136
Short name T612
Test name
Test status
Simulation time 810836959 ps
CPU time 4.76 seconds
Started Jun 27 04:58:18 PM PDT 24
Finished Jun 27 04:58:25 PM PDT 24
Peak memory 200364 kb
Host smart-ab8542ae-ea70-4b9b-9998-88f205c3fe9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871515136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
871515136
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2630346110
Short name T577
Test name
Test status
Simulation time 142980572 ps
CPU time 0.95 seconds
Started Jun 27 04:58:18 PM PDT 24
Finished Jun 27 04:58:20 PM PDT 24
Peak memory 200032 kb
Host smart-66dddbeb-45de-41bf-af60-a0ef97ef40d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630346110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
630346110
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2367597344
Short name T555
Test name
Test status
Simulation time 125160710 ps
CPU time 0.96 seconds
Started Jun 27 04:58:20 PM PDT 24
Finished Jun 27 04:58:25 PM PDT 24
Peak memory 200300 kb
Host smart-39139107-ffa7-4e21-847d-7b4ece13bfdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367597344 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2367597344
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1639300364
Short name T48
Test name
Test status
Simulation time 78938547 ps
CPU time 0.79 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:22 PM PDT 24
Peak memory 199992 kb
Host smart-cdd46634-e7b9-4d1e-9e11-008335e3c0ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639300364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1639300364
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.836410562
Short name T110
Test name
Test status
Simulation time 115814533 ps
CPU time 1.02 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:29 PM PDT 24
Peak memory 200208 kb
Host smart-c57d6fe7-edcb-42fd-a245-5d67c2241ebe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836410562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.836410562
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3174571329
Short name T575
Test name
Test status
Simulation time 219665582 ps
CPU time 3.22 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:25 PM PDT 24
Peak memory 208508 kb
Host smart-bd198f2a-7203-4871-9d26-9c43cfa38a43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174571329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3174571329
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3220547659
Short name T602
Test name
Test status
Simulation time 476793285 ps
CPU time 2.06 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:29 PM PDT 24
Peak memory 200376 kb
Host smart-13d8ea75-85c4-4165-8d4f-a88024a1dfee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220547659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3220547659
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2545737147
Short name T122
Test name
Test status
Simulation time 208165600 ps
CPU time 2 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:24 PM PDT 24
Peak memory 208512 kb
Host smart-1f7252ba-2706-4dcd-9e4f-2c67eba2063b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545737147 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2545737147
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2964331057
Short name T50
Test name
Test status
Simulation time 78075712 ps
CPU time 0.81 seconds
Started Jun 27 04:58:18 PM PDT 24
Finished Jun 27 04:58:22 PM PDT 24
Peak memory 200148 kb
Host smart-9febea23-0130-44e2-8b77-d0b4c2fe9a15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964331057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2964331057
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3976826060
Short name T596
Test name
Test status
Simulation time 78702082 ps
CPU time 0.95 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:27 PM PDT 24
Peak memory 200276 kb
Host smart-7083d32b-8e4e-4fd3-82f9-9e505f5d61a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976826060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3976826060
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1776008179
Short name T576
Test name
Test status
Simulation time 254119225 ps
CPU time 1.84 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 208532 kb
Host smart-0ef417e8-1b6e-405e-9d92-4641ba83c0b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776008179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1776008179
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1969308080
Short name T617
Test name
Test status
Simulation time 803210055 ps
CPU time 2.68 seconds
Started Jun 27 04:58:20 PM PDT 24
Finished Jun 27 04:58:26 PM PDT 24
Peak memory 200360 kb
Host smart-ad4596f7-df62-4716-bfd0-459ee1cc819e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969308080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1969308080
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4165936235
Short name T123
Test name
Test status
Simulation time 183067035 ps
CPU time 1.27 seconds
Started Jun 27 04:58:20 PM PDT 24
Finished Jun 27 04:58:24 PM PDT 24
Peak memory 208504 kb
Host smart-ca55a860-7bb8-48bb-8fd4-6ada6d80b14f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165936235 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.4165936235
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.604547603
Short name T546
Test name
Test status
Simulation time 68816122 ps
CPU time 0.78 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 200156 kb
Host smart-b63f358e-6613-44ae-866a-0faafee1e9d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604547603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.604547603
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1830704441
Short name T572
Test name
Test status
Simulation time 201957056 ps
CPU time 1.43 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 200236 kb
Host smart-5d3c4b53-6d33-44eb-9b7b-2b610eef2251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830704441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1830704441
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1418069879
Short name T613
Test name
Test status
Simulation time 426233256 ps
CPU time 2.91 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:24 PM PDT 24
Peak memory 208284 kb
Host smart-4e117918-794a-4c1b-be06-e174dab92ce3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418069879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1418069879
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.928084895
Short name T120
Test name
Test status
Simulation time 718752775 ps
CPU time 2.26 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:24 PM PDT 24
Peak memory 200380 kb
Host smart-0794cada-9869-4a66-b741-be38b54ef70a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928084895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
928084895
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2164492056
Short name T55
Test name
Test status
Simulation time 125441802 ps
CPU time 1 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:29 PM PDT 24
Peak memory 209464 kb
Host smart-d43601b0-7a2a-4d0a-81a7-5619e52388ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164492056 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2164492056
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2886369186
Short name T592
Test name
Test status
Simulation time 65943584 ps
CPU time 0.74 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:26 PM PDT 24
Peak memory 200016 kb
Host smart-9b0c78b4-7caf-4a24-ac28-4ab338b412b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886369186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2886369186
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.916370959
Short name T105
Test name
Test status
Simulation time 146282780 ps
CPU time 1.11 seconds
Started Jun 27 04:58:20 PM PDT 24
Finished Jun 27 04:58:24 PM PDT 24
Peak memory 200264 kb
Host smart-7059a6f0-f55f-4b08-9c80-5903349b8228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916370959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.916370959
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3978720298
Short name T114
Test name
Test status
Simulation time 392079332 ps
CPU time 2.91 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:25 PM PDT 24
Peak memory 208600 kb
Host smart-a70f8af6-04fe-4755-b5a3-6ef10c63e7d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978720298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3978720298
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3658770711
Short name T115
Test name
Test status
Simulation time 791207594 ps
CPU time 2.83 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:25 PM PDT 24
Peak memory 200432 kb
Host smart-6d7333e2-d273-475c-9875-eead2b077559
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658770711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3658770711
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2220958470
Short name T557
Test name
Test status
Simulation time 107570556 ps
CPU time 0.93 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:29 PM PDT 24
Peak memory 200216 kb
Host smart-73917482-dc81-49cf-8b7f-d89ec097b85c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220958470 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2220958470
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1409305596
Short name T550
Test name
Test status
Simulation time 64700211 ps
CPU time 0.79 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 200160 kb
Host smart-4f0275aa-dca4-4573-9cf6-34de47f9acd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409305596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1409305596
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.529344754
Short name T619
Test name
Test status
Simulation time 254582660 ps
CPU time 1.7 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:31 PM PDT 24
Peak memory 200368 kb
Host smart-b6f96881-0a9a-443d-b812-359a9b9a7a63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529344754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.529344754
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3045485831
Short name T566
Test name
Test status
Simulation time 253565491 ps
CPU time 1.84 seconds
Started Jun 27 04:58:22 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 208476 kb
Host smart-8d295d4c-401f-450b-a2a3-5ef0dbf3a786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045485831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3045485831
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1993075685
Short name T569
Test name
Test status
Simulation time 198572639 ps
CPU time 1.25 seconds
Started Jun 27 04:58:20 PM PDT 24
Finished Jun 27 04:58:26 PM PDT 24
Peak memory 208348 kb
Host smart-323bd33b-c9c2-4c7c-8f14-7de44825e41c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993075685 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1993075685
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1573071723
Short name T581
Test name
Test status
Simulation time 63483803 ps
CPU time 0.76 seconds
Started Jun 27 04:58:21 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 200212 kb
Host smart-83ff994d-66a5-462b-9fff-ea63490bdf3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573071723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1573071723
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1952522362
Short name T111
Test name
Test status
Simulation time 272068653 ps
CPU time 1.46 seconds
Started Jun 27 04:58:19 PM PDT 24
Finished Jun 27 04:58:23 PM PDT 24
Peak memory 200156 kb
Host smart-0fe798e3-5d6d-4df0-b191-0829aee907db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952522362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1952522362
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1170383748
Short name T580
Test name
Test status
Simulation time 343740738 ps
CPU time 2.33 seconds
Started Jun 27 04:58:23 PM PDT 24
Finished Jun 27 04:58:32 PM PDT 24
Peak memory 208592 kb
Host smart-3a202f38-445d-4791-8e4a-bd0b5cc2005d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170383748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1170383748
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1076636235
Short name T595
Test name
Test status
Simulation time 934587605 ps
CPU time 3.21 seconds
Started Jun 27 04:58:23 PM PDT 24
Finished Jun 27 04:58:33 PM PDT 24
Peak memory 200432 kb
Host smart-3181e821-a94b-4dff-8096-ca6e9cd71df2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076636235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1076636235
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1473065830
Short name T223
Test name
Test status
Simulation time 56737637 ps
CPU time 0.72 seconds
Started Jun 27 05:40:40 PM PDT 24
Finished Jun 27 05:40:42 PM PDT 24
Peak memory 199780 kb
Host smart-c0960676-c940-4fce-8308-9aee58674694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473065830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1473065830
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3835526273
Short name T529
Test name
Test status
Simulation time 1212250326 ps
CPU time 5.49 seconds
Started Jun 27 05:40:31 PM PDT 24
Finished Jun 27 05:40:38 PM PDT 24
Peak memory 221688 kb
Host smart-dea0b305-073d-44b5-8423-632fd3b12281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835526273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3835526273
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3991720008
Short name T178
Test name
Test status
Simulation time 246529849 ps
CPU time 1.05 seconds
Started Jun 27 05:40:34 PM PDT 24
Finished Jun 27 05:40:36 PM PDT 24
Peak memory 217472 kb
Host smart-7ae47859-db96-4ba0-8cec-111cdb84dbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991720008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3991720008
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.642039508
Short name T390
Test name
Test status
Simulation time 143910439 ps
CPU time 0.88 seconds
Started Jun 27 05:40:33 PM PDT 24
Finished Jun 27 05:40:35 PM PDT 24
Peak memory 199800 kb
Host smart-f024819d-743e-4a13-9072-81ebd79068a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642039508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.642039508
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1559149492
Short name T387
Test name
Test status
Simulation time 1190831862 ps
CPU time 5.02 seconds
Started Jun 27 05:40:33 PM PDT 24
Finished Jun 27 05:40:40 PM PDT 24
Peak memory 200280 kb
Host smart-c0323b5b-6832-48c9-8f54-10ff4cec9225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559149492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1559149492
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.350976157
Short name T317
Test name
Test status
Simulation time 181125044 ps
CPU time 1.15 seconds
Started Jun 27 05:40:31 PM PDT 24
Finished Jun 27 05:40:34 PM PDT 24
Peak memory 200092 kb
Host smart-db71a2a1-3f72-4154-a118-7ae803e10b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350976157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.350976157
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.4058538816
Short name T541
Test name
Test status
Simulation time 206649239 ps
CPU time 1.5 seconds
Started Jun 27 05:40:32 PM PDT 24
Finished Jun 27 05:40:34 PM PDT 24
Peak memory 200328 kb
Host smart-95b44a2b-fa5d-48d1-81a2-2f7f9573524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058538816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.4058538816
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3623154050
Short name T129
Test name
Test status
Simulation time 10944419906 ps
CPU time 39.83 seconds
Started Jun 27 05:40:33 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 208584 kb
Host smart-fa9fdd8e-aff2-48b4-9f73-3ed661bfa6c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623154050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3623154050
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1901153639
Short name T4
Test name
Test status
Simulation time 126700214 ps
CPU time 1.5 seconds
Started Jun 27 05:40:41 PM PDT 24
Finished Jun 27 05:40:44 PM PDT 24
Peak memory 208152 kb
Host smart-dc445cce-6323-4d6a-bd6f-99929b7a14ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901153639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1901153639
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1391088914
Short name T342
Test name
Test status
Simulation time 294786851 ps
CPU time 1.64 seconds
Started Jun 27 05:40:32 PM PDT 24
Finished Jun 27 05:40:34 PM PDT 24
Peak memory 200264 kb
Host smart-fd4bfb21-3c77-4c9e-84d0-90fcd3c2a92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391088914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1391088914
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1320459457
Short name T199
Test name
Test status
Simulation time 68873208 ps
CPU time 0.76 seconds
Started Jun 27 05:40:52 PM PDT 24
Finished Jun 27 05:40:55 PM PDT 24
Peak memory 199860 kb
Host smart-2b286c39-85b5-488f-860f-b51b1fb27d73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320459457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1320459457
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3480951765
Short name T397
Test name
Test status
Simulation time 244791216 ps
CPU time 1.07 seconds
Started Jun 27 05:40:32 PM PDT 24
Finished Jun 27 05:40:34 PM PDT 24
Peak memory 217416 kb
Host smart-94f10814-95aa-4c22-a08e-bad20f06f056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480951765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3480951765
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3738761841
Short name T373
Test name
Test status
Simulation time 112039952 ps
CPU time 0.82 seconds
Started Jun 27 05:40:31 PM PDT 24
Finished Jun 27 05:40:33 PM PDT 24
Peak memory 199908 kb
Host smart-87332e7c-279d-4086-8365-98eec990a8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738761841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3738761841
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.508246557
Short name T527
Test name
Test status
Simulation time 896907309 ps
CPU time 4.12 seconds
Started Jun 27 05:40:32 PM PDT 24
Finished Jun 27 05:40:37 PM PDT 24
Peak memory 200380 kb
Host smart-5426a34c-6386-4082-b435-fd688395af0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508246557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.508246557
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2682457407
Short name T59
Test name
Test status
Simulation time 16496493146 ps
CPU time 30.12 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:41:24 PM PDT 24
Peak memory 217132 kb
Host smart-d3b29406-9ae6-4fa9-abf4-1480838c2425
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682457407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2682457407
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2047426374
Short name T131
Test name
Test status
Simulation time 252865582 ps
CPU time 1.53 seconds
Started Jun 27 05:40:32 PM PDT 24
Finished Jun 27 05:40:35 PM PDT 24
Peak memory 200284 kb
Host smart-6c074b66-b317-4a2a-9467-ccfebf3a2d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047426374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2047426374
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.577613618
Short name T204
Test name
Test status
Simulation time 1393246712 ps
CPU time 5.37 seconds
Started Jun 27 05:40:40 PM PDT 24
Finished Jun 27 05:40:46 PM PDT 24
Peak memory 200240 kb
Host smart-c83b7458-3598-4364-a82e-dfa996a6a050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577613618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.577613618
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1623106157
Short name T163
Test name
Test status
Simulation time 293780857 ps
CPU time 1.89 seconds
Started Jun 27 05:40:41 PM PDT 24
Finished Jun 27 05:40:44 PM PDT 24
Peak memory 200000 kb
Host smart-3dd3390f-06ec-43d5-9ff1-e2225b6b3f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623106157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1623106157
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1286957240
Short name T301
Test name
Test status
Simulation time 77570612 ps
CPU time 0.79 seconds
Started Jun 27 05:40:34 PM PDT 24
Finished Jun 27 05:40:36 PM PDT 24
Peak memory 200096 kb
Host smart-5b6e7feb-4812-47aa-ab5a-adfcf3804059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286957240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1286957240
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3618761695
Short name T336
Test name
Test status
Simulation time 70909497 ps
CPU time 0.76 seconds
Started Jun 27 05:41:14 PM PDT 24
Finished Jun 27 05:41:20 PM PDT 24
Peak memory 199856 kb
Host smart-6e6b9308-f7e5-4336-9c1a-b961b2cb120a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618761695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3618761695
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3854378429
Short name T516
Test name
Test status
Simulation time 1223547804 ps
CPU time 6.4 seconds
Started Jun 27 05:41:13 PM PDT 24
Finished Jun 27 05:41:25 PM PDT 24
Peak memory 217736 kb
Host smart-87011962-c2cb-4547-b27d-b83c4d01eca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854378429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3854378429
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1569388532
Short name T237
Test name
Test status
Simulation time 246743657 ps
CPU time 1.07 seconds
Started Jun 27 05:41:08 PM PDT 24
Finished Jun 27 05:41:12 PM PDT 24
Peak memory 217440 kb
Host smart-9ceb3dff-d43e-43d0-bb48-631be3a10459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569388532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1569388532
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2637628746
Short name T144
Test name
Test status
Simulation time 1327747933 ps
CPU time 5.42 seconds
Started Jun 27 05:41:08 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 200316 kb
Host smart-42a49d83-5cef-49e6-9c3b-2d659167d0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637628746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2637628746
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3563308606
Short name T222
Test name
Test status
Simulation time 164650579 ps
CPU time 1.22 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:17 PM PDT 24
Peak memory 200088 kb
Host smart-429afd93-3d4f-4058-bcb0-0c97af43aa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563308606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3563308606
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3048265336
Short name T258
Test name
Test status
Simulation time 240166700 ps
CPU time 1.57 seconds
Started Jun 27 05:41:07 PM PDT 24
Finished Jun 27 05:41:09 PM PDT 24
Peak memory 200276 kb
Host smart-40b4a5c4-9fe8-414f-82f1-97ee91d0209d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048265336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3048265336
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.242092017
Short name T485
Test name
Test status
Simulation time 92039882 ps
CPU time 0.9 seconds
Started Jun 27 05:41:14 PM PDT 24
Finished Jun 27 05:41:19 PM PDT 24
Peak memory 199880 kb
Host smart-a9e7bf3a-9faa-4b7a-a308-06cfe5afcb24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242092017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.242092017
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1849762617
Short name T46
Test name
Test status
Simulation time 146197055 ps
CPU time 1.77 seconds
Started Jun 27 05:41:08 PM PDT 24
Finished Jun 27 05:41:11 PM PDT 24
Peak memory 200032 kb
Host smart-0ce80abc-0442-45db-a7e0-19d935a6a0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849762617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1849762617
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2111766479
Short name T359
Test name
Test status
Simulation time 109490714 ps
CPU time 0.96 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:16 PM PDT 24
Peak memory 199988 kb
Host smart-53a58158-023e-42f7-9bd0-c256b83ccef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111766479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2111766479
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.37311526
Short name T460
Test name
Test status
Simulation time 56404246 ps
CPU time 0.75 seconds
Started Jun 27 05:41:07 PM PDT 24
Finished Jun 27 05:41:09 PM PDT 24
Peak memory 199876 kb
Host smart-336731f1-8718-42bf-8ce5-c0adf070949d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37311526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.37311526
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1567082781
Short name T379
Test name
Test status
Simulation time 2369640848 ps
CPU time 8.15 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:20 PM PDT 24
Peak memory 217140 kb
Host smart-6b63bce9-bb82-4ec6-a375-12d3700da487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567082781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1567082781
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.435742165
Short name T14
Test name
Test status
Simulation time 243987885 ps
CPU time 1.12 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:16 PM PDT 24
Peak memory 217416 kb
Host smart-6adbeb62-ecc6-4071-a829-5200ae749af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435742165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.435742165
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3329058663
Short name T283
Test name
Test status
Simulation time 145027455 ps
CPU time 0.91 seconds
Started Jun 27 05:41:16 PM PDT 24
Finished Jun 27 05:41:20 PM PDT 24
Peak memory 199876 kb
Host smart-2ac28b01-50d1-4a4c-acfb-2789dce23c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329058663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3329058663
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2516009531
Short name T360
Test name
Test status
Simulation time 1205668067 ps
CPU time 4.86 seconds
Started Jun 27 05:41:08 PM PDT 24
Finished Jun 27 05:41:16 PM PDT 24
Peak memory 200340 kb
Host smart-a53625ee-ffbc-4fd2-a09b-4a327d94a024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516009531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2516009531
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2932031991
Short name T314
Test name
Test status
Simulation time 110742491 ps
CPU time 1.08 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 200060 kb
Host smart-53f5f93f-5288-4b57-8e89-3988d52088e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932031991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2932031991
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2856995253
Short name T353
Test name
Test status
Simulation time 255360428 ps
CPU time 1.54 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 200224 kb
Host smart-b9228bc9-fd1d-46fe-b531-c2c0b6b88858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856995253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2856995253
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3850999491
Short name T339
Test name
Test status
Simulation time 5544986730 ps
CPU time 21.35 seconds
Started Jun 27 05:41:16 PM PDT 24
Finished Jun 27 05:41:41 PM PDT 24
Peak memory 209764 kb
Host smart-6fc7daca-c6a8-4968-b31c-e4990737a976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850999491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3850999491
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1944570923
Short name T386
Test name
Test status
Simulation time 80117591 ps
CPU time 0.79 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:16 PM PDT 24
Peak memory 199988 kb
Host smart-1b893f52-0119-433e-b9dc-1a8cba148b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944570923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1944570923
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.4067801682
Short name T468
Test name
Test status
Simulation time 59037175 ps
CPU time 0.73 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:17 PM PDT 24
Peak memory 199856 kb
Host smart-4197382c-83fa-4a7e-9083-51b0e82daf65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067801682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4067801682
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.828227689
Short name T36
Test name
Test status
Simulation time 1893469470 ps
CPU time 7.76 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:24 PM PDT 24
Peak memory 217428 kb
Host smart-48f9358a-8909-457a-9e51-b66c25fcc72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828227689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.828227689
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.309981001
Short name T218
Test name
Test status
Simulation time 243985605 ps
CPU time 1.18 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:18 PM PDT 24
Peak memory 217420 kb
Host smart-88cdc351-4015-4324-9435-7d4067d2ea20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309981001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.309981001
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2195234992
Short name T279
Test name
Test status
Simulation time 206743875 ps
CPU time 1 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 199900 kb
Host smart-ca7d3bac-bc9f-4c9b-8c5d-85d368fc95e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195234992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2195234992
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1805157940
Short name T456
Test name
Test status
Simulation time 1522289957 ps
CPU time 6.55 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:23 PM PDT 24
Peak memory 200316 kb
Host smart-4145c5cb-285c-4b84-a507-5785f61e2fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805157940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1805157940
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1538816137
Short name T281
Test name
Test status
Simulation time 143023686 ps
CPU time 1.17 seconds
Started Jun 27 05:41:12 PM PDT 24
Finished Jun 27 05:41:18 PM PDT 24
Peak memory 200088 kb
Host smart-ad3b7c0f-3eb1-45c6-8131-fdad47117f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538816137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1538816137
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2726110012
Short name T333
Test name
Test status
Simulation time 238695872 ps
CPU time 1.45 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:18 PM PDT 24
Peak memory 200172 kb
Host smart-afeb29a0-977b-4e07-bad4-18212305b3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726110012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2726110012
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3385086547
Short name T235
Test name
Test status
Simulation time 389484214 ps
CPU time 2.34 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 200088 kb
Host smart-9f34740e-c02f-4488-9618-1b785e9b66a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385086547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3385086547
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2297584403
Short name T531
Test name
Test status
Simulation time 68368777 ps
CPU time 0.81 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:16 PM PDT 24
Peak memory 200092 kb
Host smart-4171e2a6-b4f1-4f26-a0ec-63c21be630cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297584403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2297584403
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.310542697
Short name T434
Test name
Test status
Simulation time 73445495 ps
CPU time 0.81 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:13 PM PDT 24
Peak memory 199888 kb
Host smart-1f387553-8fc3-4130-bb19-86146852b581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310542697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.310542697
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2546933796
Short name T454
Test name
Test status
Simulation time 1895881068 ps
CPU time 7.57 seconds
Started Jun 27 05:41:16 PM PDT 24
Finished Jun 27 05:41:27 PM PDT 24
Peak memory 217420 kb
Host smart-10d5e2df-5257-428a-9b51-406e70b4e4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546933796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2546933796
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3701738895
Short name T315
Test name
Test status
Simulation time 243997592 ps
CPU time 1.13 seconds
Started Jun 27 05:41:13 PM PDT 24
Finished Jun 27 05:41:19 PM PDT 24
Peak memory 217428 kb
Host smart-c51f771d-80c4-4114-a010-43efd60728f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701738895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3701738895
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1107097751
Short name T318
Test name
Test status
Simulation time 197868416 ps
CPU time 0.92 seconds
Started Jun 27 05:41:16 PM PDT 24
Finished Jun 27 05:41:20 PM PDT 24
Peak memory 199900 kb
Host smart-0b684370-696f-40ea-850a-271773c0e767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107097751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1107097751
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1733172792
Short name T352
Test name
Test status
Simulation time 1657379364 ps
CPU time 6.04 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:19 PM PDT 24
Peak memory 200312 kb
Host smart-b02e458d-0905-4954-82e4-aa15662401aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733172792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1733172792
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3380570422
Short name T528
Test name
Test status
Simulation time 102818881 ps
CPU time 0.97 seconds
Started Jun 27 05:41:15 PM PDT 24
Finished Jun 27 05:41:20 PM PDT 24
Peak memory 200064 kb
Host smart-68d81d53-974a-477a-bd5c-14be0fe66b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380570422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3380570422
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3877258867
Short name T453
Test name
Test status
Simulation time 191708041 ps
CPU time 1.42 seconds
Started Jun 27 05:41:17 PM PDT 24
Finished Jun 27 05:41:21 PM PDT 24
Peak memory 200244 kb
Host smart-c8fe1d2b-8f71-4082-80ad-20a301173461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877258867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3877258867
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.667163239
Short name T535
Test name
Test status
Simulation time 11809254766 ps
CPU time 40.86 seconds
Started Jun 27 05:41:14 PM PDT 24
Finished Jun 27 05:41:59 PM PDT 24
Peak memory 208512 kb
Host smart-c5064519-3943-46f3-a5fb-fb71d61c43a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667163239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.667163239
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2439851518
Short name T495
Test name
Test status
Simulation time 137571315 ps
CPU time 1.88 seconds
Started Jun 27 05:41:16 PM PDT 24
Finished Jun 27 05:41:21 PM PDT 24
Peak memory 200028 kb
Host smart-01bc0453-588b-4940-9814-9ff163ccdf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439851518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2439851518
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2523087946
Short name T239
Test name
Test status
Simulation time 220374202 ps
CPU time 1.26 seconds
Started Jun 27 05:41:14 PM PDT 24
Finished Jun 27 05:41:20 PM PDT 24
Peak memory 200096 kb
Host smart-3356c9b5-861a-4606-b8fc-5a653fd01582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523087946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2523087946
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3138866837
Short name T186
Test name
Test status
Simulation time 89401333 ps
CPU time 0.83 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 199888 kb
Host smart-b86f6341-c3e1-44e0-922d-591d811606d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138866837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3138866837
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3481981690
Short name T43
Test name
Test status
Simulation time 2340625649 ps
CPU time 7.94 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:22 PM PDT 24
Peak memory 217296 kb
Host smart-b8f418d1-7647-4c16-adf1-473eea466c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481981690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3481981690
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.229733648
Short name T393
Test name
Test status
Simulation time 244407734 ps
CPU time 1.16 seconds
Started Jun 27 05:41:13 PM PDT 24
Finished Jun 27 05:41:19 PM PDT 24
Peak memory 217368 kb
Host smart-4e21a769-a349-4781-8abd-e0b01bab61a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229733648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.229733648
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1250166751
Short name T509
Test name
Test status
Simulation time 245115726 ps
CPU time 1 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 199912 kb
Host smart-63f6fa82-f7b4-4447-b42a-b6f499b1aafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250166751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1250166751
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2412940743
Short name T250
Test name
Test status
Simulation time 1525826250 ps
CPU time 6.17 seconds
Started Jun 27 05:41:14 PM PDT 24
Finished Jun 27 05:41:25 PM PDT 24
Peak memory 200388 kb
Host smart-c0f38304-c8b7-4442-a71a-2f0b6bbf644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412940743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2412940743
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2547206508
Short name T221
Test name
Test status
Simulation time 98862892 ps
CPU time 1.05 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:17 PM PDT 24
Peak memory 200068 kb
Host smart-c54a32d3-d787-4d87-a627-9ffc978d7204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547206508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2547206508
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3417941188
Short name T539
Test name
Test status
Simulation time 110868301 ps
CPU time 1.18 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:13 PM PDT 24
Peak memory 200260 kb
Host smart-05c26580-abf3-46ce-8760-62c2f2a8ddcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417941188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3417941188
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3813228885
Short name T302
Test name
Test status
Simulation time 1203879502 ps
CPU time 5.55 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:22 PM PDT 24
Peak memory 200244 kb
Host smart-9a89616c-baf0-45c0-9c92-f51531a4b0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813228885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3813228885
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3706729083
Short name T345
Test name
Test status
Simulation time 488447640 ps
CPU time 3.01 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:18 PM PDT 24
Peak memory 200148 kb
Host smart-23f390b8-419f-4e89-aa38-e84b71fe0a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706729083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3706729083
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1850181804
Short name T455
Test name
Test status
Simulation time 178953739 ps
CPU time 1.24 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:18 PM PDT 24
Peak memory 200068 kb
Host smart-b28cadc4-0450-45ad-b4ee-dc27504eea0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850181804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1850181804
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.4072366679
Short name T312
Test name
Test status
Simulation time 66945593 ps
CPU time 0.73 seconds
Started Jun 27 05:41:12 PM PDT 24
Finished Jun 27 05:41:18 PM PDT 24
Peak memory 199824 kb
Host smart-5582cdc3-319a-4c20-9b36-9b14a263a52e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072366679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.4072366679
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.4267312762
Short name T274
Test name
Test status
Simulation time 1215620941 ps
CPU time 5.93 seconds
Started Jun 27 05:41:12 PM PDT 24
Finished Jun 27 05:41:23 PM PDT 24
Peak memory 217712 kb
Host smart-7ea15ec1-b0fc-4afc-9e2a-1864ea620500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267312762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.4267312762
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3316485609
Short name T372
Test name
Test status
Simulation time 244193017 ps
CPU time 1.07 seconds
Started Jun 27 05:41:15 PM PDT 24
Finished Jun 27 05:41:20 PM PDT 24
Peak memory 217340 kb
Host smart-1364511a-210b-4b3e-a43c-9ca1508ce8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316485609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3316485609
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1462462660
Short name T275
Test name
Test status
Simulation time 239416525 ps
CPU time 0.96 seconds
Started Jun 27 05:41:12 PM PDT 24
Finished Jun 27 05:41:18 PM PDT 24
Peak memory 199884 kb
Host smart-1b68504d-1b22-4cd3-aa84-c05a76635259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462462660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1462462660
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1390993529
Short name T11
Test name
Test status
Simulation time 1531042736 ps
CPU time 6.82 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:22 PM PDT 24
Peak memory 200244 kb
Host smart-d83224bf-f0b9-4358-844a-df4faeba2972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390993529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1390993529
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1139246826
Short name T190
Test name
Test status
Simulation time 110316600 ps
CPU time 1 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:17 PM PDT 24
Peak memory 200032 kb
Host smart-6718d533-6800-4659-891e-b55c2db4225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139246826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1139246826
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1111818131
Short name T462
Test name
Test status
Simulation time 128279998 ps
CPU time 1.23 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 200172 kb
Host smart-548709fa-0c96-405a-b75e-f7be747c5289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111818131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1111818131
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.361708573
Short name T319
Test name
Test status
Simulation time 8966312357 ps
CPU time 32.74 seconds
Started Jun 27 05:41:14 PM PDT 24
Finished Jun 27 05:41:51 PM PDT 24
Peak memory 200288 kb
Host smart-43458883-52e3-446c-9a7f-c28d47509fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361708573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.361708573
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1013000461
Short name T198
Test name
Test status
Simulation time 319363349 ps
CPU time 1.99 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 200136 kb
Host smart-571d21a2-81d6-4bee-acf0-9b1676c90c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013000461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1013000461
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.292014923
Short name T515
Test name
Test status
Simulation time 65492625 ps
CPU time 0.83 seconds
Started Jun 27 05:41:34 PM PDT 24
Finished Jun 27 05:41:38 PM PDT 24
Peak memory 199876 kb
Host smart-b6838917-7118-4042-b5d8-8e05614852fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292014923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.292014923
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.4067574404
Short name T391
Test name
Test status
Simulation time 1228661285 ps
CPU time 6.1 seconds
Started Jun 27 05:41:13 PM PDT 24
Finished Jun 27 05:41:24 PM PDT 24
Peak memory 217660 kb
Host smart-4cf687db-f455-4423-8aef-3bfffdcc1248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067574404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.4067574404
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1646916587
Short name T183
Test name
Test status
Simulation time 244779449 ps
CPU time 1.03 seconds
Started Jun 27 05:41:32 PM PDT 24
Finished Jun 27 05:41:36 PM PDT 24
Peak memory 217456 kb
Host smart-7c301a7d-8ec4-4c84-b3ee-a48047edcc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646916587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1646916587
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.53429979
Short name T8
Test name
Test status
Simulation time 189239759 ps
CPU time 0.9 seconds
Started Jun 27 05:41:15 PM PDT 24
Finished Jun 27 05:41:20 PM PDT 24
Peak memory 199812 kb
Host smart-a54c1856-b323-41dc-8549-ae2917b58eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53429979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.53429979
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2310075661
Short name T26
Test name
Test status
Simulation time 1697118290 ps
CPU time 6.64 seconds
Started Jun 27 05:41:13 PM PDT 24
Finished Jun 27 05:41:25 PM PDT 24
Peak memory 200340 kb
Host smart-4ca159b7-44b8-45ee-9bb1-3ef3fc39c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310075661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2310075661
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3418195538
Short name T160
Test name
Test status
Simulation time 189455145 ps
CPU time 1.28 seconds
Started Jun 27 05:41:15 PM PDT 24
Finished Jun 27 05:41:20 PM PDT 24
Peak memory 200016 kb
Host smart-070fc74b-643e-47ec-ac63-ec533cfbf3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418195538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3418195538
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.610759976
Short name T497
Test name
Test status
Simulation time 200122442 ps
CPU time 1.35 seconds
Started Jun 27 05:41:12 PM PDT 24
Finished Jun 27 05:41:19 PM PDT 24
Peak memory 200244 kb
Host smart-2f6bccbd-64b6-4332-a0fa-1aead56c4f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610759976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.610759976
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.4020475478
Short name T526
Test name
Test status
Simulation time 3984271677 ps
CPU time 17.02 seconds
Started Jun 27 05:41:35 PM PDT 24
Finished Jun 27 05:41:55 PM PDT 24
Peak memory 216752 kb
Host smart-b6d3c578-35db-4b74-bb96-a7743ff96126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020475478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.4020475478
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2696973796
Short name T270
Test name
Test status
Simulation time 130994715 ps
CPU time 1.59 seconds
Started Jun 27 05:41:13 PM PDT 24
Finished Jun 27 05:41:19 PM PDT 24
Peak memory 208256 kb
Host smart-e1c653b4-1dc6-45f1-b1fc-77f761cf5b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696973796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2696973796
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1259194554
Short name T70
Test name
Test status
Simulation time 66372180 ps
CPU time 0.74 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:17 PM PDT 24
Peak memory 200092 kb
Host smart-b1d6b139-4c1a-4b16-9180-fbf9086e7638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259194554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1259194554
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1937474147
Short name T479
Test name
Test status
Simulation time 1894675428 ps
CPU time 7.75 seconds
Started Jun 27 05:41:27 PM PDT 24
Finished Jun 27 05:41:36 PM PDT 24
Peak memory 217752 kb
Host smart-54db0a08-c6f7-4a9e-832b-d2121c31a094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937474147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1937474147
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3844537166
Short name T494
Test name
Test status
Simulation time 243612217 ps
CPU time 1.06 seconds
Started Jun 27 05:41:35 PM PDT 24
Finished Jun 27 05:41:39 PM PDT 24
Peak memory 217448 kb
Host smart-e73f0600-2e5b-454b-8960-9c78381de8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844537166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3844537166
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.544550524
Short name T413
Test name
Test status
Simulation time 192898805 ps
CPU time 0.87 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:41:32 PM PDT 24
Peak memory 199844 kb
Host smart-9e7387fb-9c69-4804-aec0-e44271855238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544550524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.544550524
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1242065400
Short name T244
Test name
Test status
Simulation time 1388507804 ps
CPU time 6.08 seconds
Started Jun 27 05:41:28 PM PDT 24
Finished Jun 27 05:41:35 PM PDT 24
Peak memory 200396 kb
Host smart-7614c247-1de4-496e-9bde-9cc5ca8a9330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242065400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1242065400
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1008689080
Short name T293
Test name
Test status
Simulation time 95319801 ps
CPU time 0.95 seconds
Started Jun 27 05:41:25 PM PDT 24
Finished Jun 27 05:41:27 PM PDT 24
Peak memory 200092 kb
Host smart-eb76d4ab-d603-47a0-a150-bdb80be5b033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008689080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1008689080
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2928975882
Short name T45
Test name
Test status
Simulation time 191855753 ps
CPU time 1.43 seconds
Started Jun 27 05:41:34 PM PDT 24
Finished Jun 27 05:41:39 PM PDT 24
Peak memory 200276 kb
Host smart-e6ee835e-3fbd-485e-a054-3594215a5401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928975882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2928975882
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3237247681
Short name T285
Test name
Test status
Simulation time 7614548835 ps
CPU time 28.11 seconds
Started Jun 27 05:41:32 PM PDT 24
Finished Jun 27 05:42:03 PM PDT 24
Peak memory 216760 kb
Host smart-10018957-6644-496c-a676-3885a05aaef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237247681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3237247681
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4238143949
Short name T532
Test name
Test status
Simulation time 154745108 ps
CPU time 1.89 seconds
Started Jun 27 05:41:30 PM PDT 24
Finished Jun 27 05:41:34 PM PDT 24
Peak memory 200084 kb
Host smart-98ece455-ac3e-48fd-b359-98dbbf79f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238143949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4238143949
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2621799076
Short name T499
Test name
Test status
Simulation time 110063776 ps
CPU time 0.88 seconds
Started Jun 27 05:41:32 PM PDT 24
Finished Jun 27 05:41:36 PM PDT 24
Peak memory 200100 kb
Host smart-e067118a-62c8-4d74-893e-6a44911c65f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621799076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2621799076
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.4208881201
Short name T337
Test name
Test status
Simulation time 64830129 ps
CPU time 0.78 seconds
Started Jun 27 05:41:28 PM PDT 24
Finished Jun 27 05:41:31 PM PDT 24
Peak memory 199880 kb
Host smart-a30866c9-efe4-42c1-9ac7-5ee6f7bebf2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208881201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4208881201
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.387951725
Short name T31
Test name
Test status
Simulation time 1888757102 ps
CPU time 7.23 seconds
Started Jun 27 05:41:27 PM PDT 24
Finished Jun 27 05:41:35 PM PDT 24
Peak memory 221596 kb
Host smart-93ad4171-5ad6-449f-a666-f3b46637620b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387951725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.387951725
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.403443126
Short name T164
Test name
Test status
Simulation time 243690544 ps
CPU time 1.1 seconds
Started Jun 27 05:41:34 PM PDT 24
Finished Jun 27 05:41:38 PM PDT 24
Peak memory 217496 kb
Host smart-3b36c6cf-ab98-41c3-81b0-67492e6e19c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403443126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.403443126
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1413780491
Short name T439
Test name
Test status
Simulation time 207487300 ps
CPU time 0.9 seconds
Started Jun 27 05:41:30 PM PDT 24
Finished Jun 27 05:41:33 PM PDT 24
Peak memory 199840 kb
Host smart-b2245533-ace7-4e1c-b505-1eb2dee24ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413780491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1413780491
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.4085642556
Short name T385
Test name
Test status
Simulation time 698032859 ps
CPU time 3.97 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:41:35 PM PDT 24
Peak memory 200316 kb
Host smart-ea84c23d-7040-4bf3-9216-5e8b03e17b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085642556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.4085642556
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2509945843
Short name T376
Test name
Test status
Simulation time 170820145 ps
CPU time 1.35 seconds
Started Jun 27 05:41:34 PM PDT 24
Finished Jun 27 05:41:38 PM PDT 24
Peak memory 200100 kb
Host smart-678178e6-0729-41e0-8902-29df31d47d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509945843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2509945843
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.4176891055
Short name T403
Test name
Test status
Simulation time 245622277 ps
CPU time 1.47 seconds
Started Jun 27 05:41:34 PM PDT 24
Finished Jun 27 05:41:38 PM PDT 24
Peak memory 200288 kb
Host smart-509b609a-33f5-4553-9ac4-483356b50a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176891055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.4176891055
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.839844738
Short name T247
Test name
Test status
Simulation time 115943317 ps
CPU time 1.5 seconds
Started Jun 27 05:41:28 PM PDT 24
Finished Jun 27 05:41:31 PM PDT 24
Peak memory 200072 kb
Host smart-4f1b347c-9443-48e8-bb7a-63afd3d70ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839844738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.839844738
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2609146722
Short name T505
Test name
Test status
Simulation time 75663695 ps
CPU time 0.78 seconds
Started Jun 27 05:41:27 PM PDT 24
Finished Jun 27 05:41:29 PM PDT 24
Peak memory 200072 kb
Host smart-374c2b72-3896-4986-bb07-4ce40b49a375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609146722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2609146722
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1728411175
Short name T219
Test name
Test status
Simulation time 75781578 ps
CPU time 0.79 seconds
Started Jun 27 05:41:26 PM PDT 24
Finished Jun 27 05:41:28 PM PDT 24
Peak memory 199880 kb
Host smart-2845feff-378c-4255-b577-ef6af4633ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728411175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1728411175
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.683466054
Short name T354
Test name
Test status
Simulation time 2360293703 ps
CPU time 9.59 seconds
Started Jun 27 05:41:26 PM PDT 24
Finished Jun 27 05:41:37 PM PDT 24
Peak memory 217836 kb
Host smart-73aff1a7-3f6d-4576-a028-b8bd4acd4960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683466054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.683466054
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2760045090
Short name T68
Test name
Test status
Simulation time 244167733 ps
CPU time 1.05 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:41:33 PM PDT 24
Peak memory 217440 kb
Host smart-dd55baa8-1bc6-4878-99c8-d35469d81cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760045090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2760045090
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2450088580
Short name T540
Test name
Test status
Simulation time 241446592 ps
CPU time 0.98 seconds
Started Jun 27 05:41:28 PM PDT 24
Finished Jun 27 05:41:31 PM PDT 24
Peak memory 199932 kb
Host smart-ebf39731-55a2-4d89-9436-9582873a448c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450088580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2450088580
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3259884084
Short name T92
Test name
Test status
Simulation time 1106539848 ps
CPU time 5.74 seconds
Started Jun 27 05:41:35 PM PDT 24
Finished Jun 27 05:41:43 PM PDT 24
Peak memory 200392 kb
Host smart-f4ca5b5c-b18c-4fed-8013-a7b249ade6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259884084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3259884084
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2335495635
Short name T155
Test name
Test status
Simulation time 183817907 ps
CPU time 1.17 seconds
Started Jun 27 05:41:35 PM PDT 24
Finished Jun 27 05:41:39 PM PDT 24
Peak memory 200088 kb
Host smart-602daaab-a257-4fd9-841c-98d28e4e1da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335495635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2335495635
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1423961258
Short name T477
Test name
Test status
Simulation time 197068022 ps
CPU time 1.43 seconds
Started Jun 27 05:41:33 PM PDT 24
Finished Jun 27 05:41:37 PM PDT 24
Peak memory 200284 kb
Host smart-89a2bf69-6302-4095-8557-5f4bef6dfdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423961258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1423961258
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1590048375
Short name T295
Test name
Test status
Simulation time 119915368 ps
CPU time 1.53 seconds
Started Jun 27 05:41:35 PM PDT 24
Finished Jun 27 05:41:39 PM PDT 24
Peak memory 208252 kb
Host smart-076d1db2-bac3-4b7a-b6d6-8e3deb4bfaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590048375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1590048375
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1523350921
Short name T469
Test name
Test status
Simulation time 194789086 ps
CPU time 1.28 seconds
Started Jun 27 05:41:31 PM PDT 24
Finished Jun 27 05:41:35 PM PDT 24
Peak memory 200020 kb
Host smart-6e8e6efb-d70b-403d-ad06-a31e4fa82b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523350921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1523350921
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.10858938
Short name T398
Test name
Test status
Simulation time 84283037 ps
CPU time 0.83 seconds
Started Jun 27 05:40:48 PM PDT 24
Finished Jun 27 05:40:50 PM PDT 24
Peak memory 199880 kb
Host smart-7153b297-ae53-4878-bf46-ad79f153b9b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10858938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.10858938
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2784966595
Short name T442
Test name
Test status
Simulation time 1227866339 ps
CPU time 5.45 seconds
Started Jun 27 05:40:54 PM PDT 24
Finished Jun 27 05:41:02 PM PDT 24
Peak memory 221480 kb
Host smart-92a1e523-f8ab-49ff-8e5a-6fd120e99f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784966595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2784966595
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3581062798
Short name T402
Test name
Test status
Simulation time 244065258 ps
CPU time 1.12 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:40:53 PM PDT 24
Peak memory 217476 kb
Host smart-0afa4989-2900-4a8b-afb0-6496dc6a603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581062798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3581062798
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4293438879
Short name T213
Test name
Test status
Simulation time 96494930 ps
CPU time 0.8 seconds
Started Jun 27 05:40:49 PM PDT 24
Finished Jun 27 05:40:52 PM PDT 24
Peak memory 199936 kb
Host smart-93fc36a0-9696-4fae-a708-c06598f6e6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293438879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4293438879
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1603888215
Short name T441
Test name
Test status
Simulation time 1570327484 ps
CPU time 5.62 seconds
Started Jun 27 05:40:47 PM PDT 24
Finished Jun 27 05:40:54 PM PDT 24
Peak memory 200344 kb
Host smart-9c2d9633-d795-4598-8e98-7da978f5555a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603888215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1603888215
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.4104099873
Short name T60
Test name
Test status
Simulation time 16498712565 ps
CPU time 27.96 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:41:21 PM PDT 24
Peak memory 217040 kb
Host smart-ae2d6e63-9732-4890-9296-aa171b52d790
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104099873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.4104099873
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3219099318
Short name T392
Test name
Test status
Simulation time 139661736 ps
CPU time 1.12 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:40:54 PM PDT 24
Peak memory 200064 kb
Host smart-3dbaf9f0-7a5e-4775-b32a-1556ef6c0d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219099318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3219099318
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.76064288
Short name T512
Test name
Test status
Simulation time 190774089 ps
CPU time 1.38 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:55 PM PDT 24
Peak memory 200232 kb
Host smart-cd08848d-c5f7-42ea-bfc1-e6959ca2283d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76064288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.76064288
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3990383209
Short name T463
Test name
Test status
Simulation time 946589834 ps
CPU time 4.42 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:59 PM PDT 24
Peak memory 200264 kb
Host smart-cd5742c7-73cb-4da8-af6d-76376f1bb61f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990383209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3990383209
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1571897593
Short name T81
Test name
Test status
Simulation time 139121133 ps
CPU time 1.69 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:55 PM PDT 24
Peak memory 200028 kb
Host smart-386c99a6-ae82-4e51-bb7e-053ed82d2019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571897593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1571897593
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2472999564
Short name T384
Test name
Test status
Simulation time 118816066 ps
CPU time 0.98 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:55 PM PDT 24
Peak memory 200124 kb
Host smart-bc8d07b0-6615-4866-88ba-33ca0675bfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472999564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2472999564
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1616840303
Short name T253
Test name
Test status
Simulation time 71568796 ps
CPU time 0.77 seconds
Started Jun 27 05:41:30 PM PDT 24
Finished Jun 27 05:41:34 PM PDT 24
Peak memory 199808 kb
Host smart-878e772b-ea00-49d1-b8e2-d15d7284d570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616840303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1616840303
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3360415994
Short name T433
Test name
Test status
Simulation time 1881880726 ps
CPU time 6.73 seconds
Started Jun 27 05:41:33 PM PDT 24
Finished Jun 27 05:41:42 PM PDT 24
Peak memory 221612 kb
Host smart-9871918b-761d-4388-8f5b-591d97e6f9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360415994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3360415994
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1707248716
Short name T367
Test name
Test status
Simulation time 244278583 ps
CPU time 1.03 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:41:33 PM PDT 24
Peak memory 217264 kb
Host smart-4e000dcc-aaab-4b84-94df-a138367f162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707248716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1707248716
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3147002789
Short name T224
Test name
Test status
Simulation time 229945006 ps
CPU time 0.91 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:41:32 PM PDT 24
Peak memory 199904 kb
Host smart-3b7369b5-904c-4fd5-9f98-f4b1f1bf9fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147002789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3147002789
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2796221524
Short name T263
Test name
Test status
Simulation time 1037167103 ps
CPU time 4.36 seconds
Started Jun 27 05:41:26 PM PDT 24
Finished Jun 27 05:41:31 PM PDT 24
Peak memory 200280 kb
Host smart-c0b72668-b260-4645-8241-b5112c0b9fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796221524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2796221524
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.528525175
Short name T445
Test name
Test status
Simulation time 154481171 ps
CPU time 1.16 seconds
Started Jun 27 05:41:28 PM PDT 24
Finished Jun 27 05:41:31 PM PDT 24
Peak memory 200044 kb
Host smart-16691af1-277b-468f-8fe2-43377f241499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528525175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.528525175
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2926872693
Short name T85
Test name
Test status
Simulation time 113983498 ps
CPU time 1.14 seconds
Started Jun 27 05:41:33 PM PDT 24
Finished Jun 27 05:41:37 PM PDT 24
Peak memory 200192 kb
Host smart-7b25f162-e153-4c46-90e6-1c1247f111a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926872693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2926872693
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2739682386
Short name T172
Test name
Test status
Simulation time 291491694 ps
CPU time 1.92 seconds
Started Jun 27 05:41:33 PM PDT 24
Finished Jun 27 05:41:38 PM PDT 24
Peak memory 208288 kb
Host smart-8a3be7c4-2156-4611-9c28-203b7d728de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739682386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2739682386
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1494764592
Short name T523
Test name
Test status
Simulation time 153205426 ps
CPU time 1.34 seconds
Started Jun 27 05:41:26 PM PDT 24
Finished Jun 27 05:41:29 PM PDT 24
Peak memory 200296 kb
Host smart-994bb0f1-677f-4d5a-afbd-44520e675bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494764592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1494764592
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2247090278
Short name T151
Test name
Test status
Simulation time 79283009 ps
CPU time 0.81 seconds
Started Jun 27 05:41:35 PM PDT 24
Finished Jun 27 05:41:39 PM PDT 24
Peak memory 199880 kb
Host smart-94cb4b79-613a-42d9-9521-12f8aaef360b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247090278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2247090278
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3676805695
Short name T35
Test name
Test status
Simulation time 1216507060 ps
CPU time 5.58 seconds
Started Jun 27 05:41:31 PM PDT 24
Finished Jun 27 05:41:40 PM PDT 24
Peak memory 217764 kb
Host smart-c6db73d6-e81e-40bd-b5ac-4c7b50df6cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676805695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3676805695
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1237045747
Short name T426
Test name
Test status
Simulation time 244250524 ps
CPU time 1.1 seconds
Started Jun 27 05:41:35 PM PDT 24
Finished Jun 27 05:41:39 PM PDT 24
Peak memory 217460 kb
Host smart-ae8a63bf-a5ae-4097-8749-e49b4cfa3ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237045747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1237045747
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3273391036
Short name T544
Test name
Test status
Simulation time 141406577 ps
CPU time 0.8 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:41:32 PM PDT 24
Peak memory 199784 kb
Host smart-0301c018-cc92-42e0-8900-9f541199ba68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273391036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3273391036
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.493744494
Short name T428
Test name
Test status
Simulation time 1047750327 ps
CPU time 4.7 seconds
Started Jun 27 05:41:34 PM PDT 24
Finished Jun 27 05:41:42 PM PDT 24
Peak memory 200396 kb
Host smart-7b6bf229-81e3-441e-b397-32ff2ffa436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493744494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.493744494
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2756270857
Short name T255
Test name
Test status
Simulation time 105444467 ps
CPU time 1.06 seconds
Started Jun 27 05:41:35 PM PDT 24
Finished Jun 27 05:41:38 PM PDT 24
Peak memory 200088 kb
Host smart-61e58015-5636-4dde-93e9-403625cc9052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756270857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2756270857
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2863334295
Short name T268
Test name
Test status
Simulation time 187083186 ps
CPU time 1.31 seconds
Started Jun 27 05:41:27 PM PDT 24
Finished Jun 27 05:41:30 PM PDT 24
Peak memory 200304 kb
Host smart-d204b20a-cc94-4f60-9492-e633ad9c486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863334295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2863334295
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1192106321
Short name T507
Test name
Test status
Simulation time 3760680060 ps
CPU time 13.53 seconds
Started Jun 27 05:41:26 PM PDT 24
Finished Jun 27 05:41:41 PM PDT 24
Peak memory 200612 kb
Host smart-15615c82-a37c-48be-94c0-d980041c7822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192106321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1192106321
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3688090005
Short name T498
Test name
Test status
Simulation time 463373920 ps
CPU time 2.41 seconds
Started Jun 27 05:41:28 PM PDT 24
Finished Jun 27 05:41:31 PM PDT 24
Peak memory 208228 kb
Host smart-1d6a8ef8-1852-4670-875b-3f3a502de6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688090005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3688090005
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3724773083
Short name T401
Test name
Test status
Simulation time 70275252 ps
CPU time 0.73 seconds
Started Jun 27 05:41:33 PM PDT 24
Finished Jun 27 05:41:37 PM PDT 24
Peak memory 200104 kb
Host smart-64bf21f2-ccc0-489e-a898-94a28ced6f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724773083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3724773083
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3356541542
Short name T331
Test name
Test status
Simulation time 62729716 ps
CPU time 0.72 seconds
Started Jun 27 05:41:28 PM PDT 24
Finished Jun 27 05:41:31 PM PDT 24
Peak memory 199880 kb
Host smart-11768d19-d233-4828-8c4e-c81a625f735c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356541542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3356541542
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2034045883
Short name T471
Test name
Test status
Simulation time 1904666970 ps
CPU time 7.93 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:41:39 PM PDT 24
Peak memory 216696 kb
Host smart-7045fcdc-7312-4ccf-b9bc-18e98350f61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034045883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2034045883
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3044492720
Short name T2
Test name
Test status
Simulation time 244614659 ps
CPU time 1.15 seconds
Started Jun 27 05:41:33 PM PDT 24
Finished Jun 27 05:41:37 PM PDT 24
Peak memory 217360 kb
Host smart-29b50ece-a30c-4b87-8624-bdfe77373fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044492720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3044492720
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.4220710231
Short name T518
Test name
Test status
Simulation time 111659238 ps
CPU time 0.76 seconds
Started Jun 27 05:41:32 PM PDT 24
Finished Jun 27 05:41:35 PM PDT 24
Peak memory 199820 kb
Host smart-8f676518-c88a-4c38-ba8d-f9ab0c34b636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220710231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.4220710231
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3151141808
Short name T418
Test name
Test status
Simulation time 813411063 ps
CPU time 4.48 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:41:35 PM PDT 24
Peak memory 200548 kb
Host smart-4492eb3c-322f-4552-9b70-54dd1e88e964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151141808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3151141808
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2422021523
Short name T334
Test name
Test status
Simulation time 155780646 ps
CPU time 1.13 seconds
Started Jun 27 05:41:36 PM PDT 24
Finished Jun 27 05:41:39 PM PDT 24
Peak memory 200092 kb
Host smart-b246628a-c2ce-474c-8de0-c8747193e10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422021523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2422021523
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1346115876
Short name T522
Test name
Test status
Simulation time 189149336 ps
CPU time 1.35 seconds
Started Jun 27 05:41:32 PM PDT 24
Finished Jun 27 05:41:35 PM PDT 24
Peak memory 200192 kb
Host smart-e03d33f0-2e50-4a2f-a4eb-0d9a3676f5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346115876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1346115876
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2527679851
Short name T272
Test name
Test status
Simulation time 3598009951 ps
CPU time 17.59 seconds
Started Jun 27 05:41:28 PM PDT 24
Finished Jun 27 05:41:48 PM PDT 24
Peak memory 200460 kb
Host smart-2d93b144-8bb5-4333-85ca-637ff587e721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527679851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2527679851
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1515947474
Short name T76
Test name
Test status
Simulation time 142040090 ps
CPU time 1.61 seconds
Started Jun 27 05:41:32 PM PDT 24
Finished Jun 27 05:41:36 PM PDT 24
Peak memory 200000 kb
Host smart-39fd141c-8f67-40aa-968b-1de5e95e44cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515947474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1515947474
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.294272996
Short name T288
Test name
Test status
Simulation time 91859588 ps
CPU time 0.91 seconds
Started Jun 27 05:41:34 PM PDT 24
Finished Jun 27 05:41:37 PM PDT 24
Peak memory 200100 kb
Host smart-58ea72e7-f649-4213-8a18-5bcff10d3382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294272996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.294272996
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1322189439
Short name T153
Test name
Test status
Simulation time 72239748 ps
CPU time 0.86 seconds
Started Jun 27 05:41:37 PM PDT 24
Finished Jun 27 05:41:40 PM PDT 24
Peak memory 199884 kb
Host smart-933c5068-dfac-45fb-9f82-e76d3f79b9e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322189439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1322189439
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3419207400
Short name T41
Test name
Test status
Simulation time 1918803522 ps
CPU time 7.61 seconds
Started Jun 27 05:41:28 PM PDT 24
Finished Jun 27 05:41:37 PM PDT 24
Peak memory 217712 kb
Host smart-e82afa4f-ee8a-4f99-8a89-b3bd09886701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419207400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3419207400
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3493634309
Short name T158
Test name
Test status
Simulation time 244453649 ps
CPU time 1.08 seconds
Started Jun 27 05:41:31 PM PDT 24
Finished Jun 27 05:41:34 PM PDT 24
Peak memory 217404 kb
Host smart-68952fb0-e4e1-4aa8-9c49-28d7be8ba575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493634309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3493634309
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.4022584027
Short name T537
Test name
Test status
Simulation time 245732456 ps
CPU time 1 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:41:32 PM PDT 24
Peak memory 199880 kb
Host smart-829cad7f-fb89-4e2e-92c7-f9ccd021aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022584027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.4022584027
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2028278243
Short name T126
Test name
Test status
Simulation time 1851747427 ps
CPU time 7.21 seconds
Started Jun 27 05:41:36 PM PDT 24
Finished Jun 27 05:41:45 PM PDT 24
Peak memory 200344 kb
Host smart-371440b0-1340-4860-9066-6b00c1409a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028278243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2028278243
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1235430767
Short name T502
Test name
Test status
Simulation time 175189546 ps
CPU time 1.14 seconds
Started Jun 27 05:41:30 PM PDT 24
Finished Jun 27 05:41:34 PM PDT 24
Peak memory 199992 kb
Host smart-d407c881-1ac8-4b3b-aacf-9e22d1ddc68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235430767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1235430767
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2301771430
Short name T254
Test name
Test status
Simulation time 245620772 ps
CPU time 1.6 seconds
Started Jun 27 05:41:36 PM PDT 24
Finished Jun 27 05:41:40 PM PDT 24
Peak memory 200280 kb
Host smart-17786e95-cfdf-41a6-9947-9b736015b5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301771430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2301771430
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2753284973
Short name T348
Test name
Test status
Simulation time 3440435621 ps
CPU time 16.08 seconds
Started Jun 27 05:41:36 PM PDT 24
Finished Jun 27 05:41:54 PM PDT 24
Peak memory 208604 kb
Host smart-b3d588e1-d815-4261-bab3-0623e15936a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753284973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2753284973
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.274450123
Short name T504
Test name
Test status
Simulation time 343708031 ps
CPU time 1.94 seconds
Started Jun 27 05:41:29 PM PDT 24
Finished Jun 27 05:41:33 PM PDT 24
Peak memory 200104 kb
Host smart-bd3b9251-3c90-42d7-937e-5b5123a29ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274450123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.274450123
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3438709516
Short name T533
Test name
Test status
Simulation time 130856034 ps
CPU time 1.04 seconds
Started Jun 27 05:41:28 PM PDT 24
Finished Jun 27 05:41:31 PM PDT 24
Peak memory 200096 kb
Host smart-34014311-880c-44dc-8fed-511c2f761775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438709516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3438709516
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.688659698
Short name T429
Test name
Test status
Simulation time 87525801 ps
CPU time 0.89 seconds
Started Jun 27 05:41:38 PM PDT 24
Finished Jun 27 05:41:41 PM PDT 24
Peak memory 199884 kb
Host smart-d773590c-0c8d-45ec-88f6-d0a47ab9556d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688659698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.688659698
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3181571504
Short name T30
Test name
Test status
Simulation time 1225744981 ps
CPU time 5.7 seconds
Started Jun 27 05:41:39 PM PDT 24
Finished Jun 27 05:41:46 PM PDT 24
Peak memory 217696 kb
Host smart-ef01828f-2b1e-4918-91e2-b07d7de048f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181571504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3181571504
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3926155055
Short name T411
Test name
Test status
Simulation time 244203510 ps
CPU time 1.02 seconds
Started Jun 27 05:41:39 PM PDT 24
Finished Jun 27 05:41:42 PM PDT 24
Peak memory 217464 kb
Host smart-330eea6e-5134-4704-90ff-a4d7fa97b1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926155055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3926155055
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2775111304
Short name T282
Test name
Test status
Simulation time 78488225 ps
CPU time 0.72 seconds
Started Jun 27 05:41:30 PM PDT 24
Finished Jun 27 05:41:33 PM PDT 24
Peak memory 199880 kb
Host smart-18b94f88-bc0e-4e50-8321-417019825f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775111304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2775111304
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.826783179
Short name T130
Test name
Test status
Simulation time 1636037768 ps
CPU time 6.5 seconds
Started Jun 27 05:41:30 PM PDT 24
Finished Jun 27 05:41:38 PM PDT 24
Peak memory 200244 kb
Host smart-dc49982b-11fd-4bc1-9b17-bcabea0d309b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826783179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.826783179
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2557967925
Short name T296
Test name
Test status
Simulation time 108492937 ps
CPU time 1.07 seconds
Started Jun 27 05:41:38 PM PDT 24
Finished Jun 27 05:41:41 PM PDT 24
Peak memory 200096 kb
Host smart-c10869ca-0c75-43ad-89d5-a620922b59d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557967925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2557967925
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.992154961
Short name T181
Test name
Test status
Simulation time 188911612 ps
CPU time 1.31 seconds
Started Jun 27 05:41:32 PM PDT 24
Finished Jun 27 05:41:36 PM PDT 24
Peak memory 200252 kb
Host smart-1ba842cf-801f-415e-9706-6ac8778472c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992154961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.992154961
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.4024306382
Short name T380
Test name
Test status
Simulation time 9078429487 ps
CPU time 29.73 seconds
Started Jun 27 05:41:39 PM PDT 24
Finished Jun 27 05:42:11 PM PDT 24
Peak memory 200416 kb
Host smart-974f9fe2-8e81-4e4f-bf71-e607d69c5414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024306382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4024306382
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2289198824
Short name T78
Test name
Test status
Simulation time 126489909 ps
CPU time 1.54 seconds
Started Jun 27 05:41:30 PM PDT 24
Finished Jun 27 05:41:34 PM PDT 24
Peak memory 200060 kb
Host smart-f6d9d0bd-7637-4a74-90b1-de6637462247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289198824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2289198824
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2527955417
Short name T133
Test name
Test status
Simulation time 170116756 ps
CPU time 1.15 seconds
Started Jun 27 05:41:31 PM PDT 24
Finished Jun 27 05:41:35 PM PDT 24
Peak memory 199996 kb
Host smart-1ee44525-4562-4721-b849-d1fe6b21d97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527955417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2527955417
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2495577166
Short name T202
Test name
Test status
Simulation time 74951499 ps
CPU time 0.81 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:07 PM PDT 24
Peak memory 199880 kb
Host smart-d0d48045-64de-4f2c-b02d-3dad485cf827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495577166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2495577166
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2993511927
Short name T362
Test name
Test status
Simulation time 1226542257 ps
CPU time 5.53 seconds
Started Jun 27 05:42:05 PM PDT 24
Finished Jun 27 05:42:14 PM PDT 24
Peak memory 221672 kb
Host smart-3941d151-5297-4163-8d14-23adf55b3b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993511927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2993511927
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3798377093
Short name T96
Test name
Test status
Simulation time 243708068 ps
CPU time 1.07 seconds
Started Jun 27 05:42:00 PM PDT 24
Finished Jun 27 05:42:04 PM PDT 24
Peak memory 217400 kb
Host smart-9fcfda44-3fcc-4c2c-8ee4-e31af675e7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798377093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3798377093
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2789254213
Short name T256
Test name
Test status
Simulation time 184443105 ps
CPU time 0.97 seconds
Started Jun 27 05:42:04 PM PDT 24
Finished Jun 27 05:42:08 PM PDT 24
Peak memory 199900 kb
Host smart-3777847e-91f5-4e1e-95af-d9e36aa7df2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789254213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2789254213
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2851037379
Short name T466
Test name
Test status
Simulation time 1320658790 ps
CPU time 5.13 seconds
Started Jun 27 05:41:57 PM PDT 24
Finished Jun 27 05:42:03 PM PDT 24
Peak memory 200360 kb
Host smart-244f14b2-a790-44cf-8c49-f3ded7fe95ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851037379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2851037379
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.527665352
Short name T443
Test name
Test status
Simulation time 108235779 ps
CPU time 0.97 seconds
Started Jun 27 05:42:06 PM PDT 24
Finished Jun 27 05:42:10 PM PDT 24
Peak memory 200068 kb
Host smart-7a369462-7098-4db2-8832-ee121930fe69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527665352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.527665352
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.419537495
Short name T407
Test name
Test status
Simulation time 191826651 ps
CPU time 1.38 seconds
Started Jun 27 05:41:38 PM PDT 24
Finished Jun 27 05:41:42 PM PDT 24
Peak memory 200284 kb
Host smart-4cd9fe0b-de91-423d-843f-9f4869e3ff2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419537495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.419537495
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3888810070
Short name T103
Test name
Test status
Simulation time 6631503429 ps
CPU time 29.21 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:34 PM PDT 24
Peak memory 208624 kb
Host smart-dec4fc5e-ee06-41ee-8571-6bf5c7056e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888810070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3888810070
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3981864658
Short name T417
Test name
Test status
Simulation time 134243704 ps
CPU time 1.65 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:06 PM PDT 24
Peak memory 200052 kb
Host smart-290ecae3-0b4e-4eaa-9db9-af6bb6612850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981864658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3981864658
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2924196750
Short name T225
Test name
Test status
Simulation time 99070200 ps
CPU time 0.93 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:05 PM PDT 24
Peak memory 200096 kb
Host smart-9911bca1-5b0c-42f9-9279-6965ccc208ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924196750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2924196750
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3815872366
Short name T177
Test name
Test status
Simulation time 97526417 ps
CPU time 0.84 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:07 PM PDT 24
Peak memory 199808 kb
Host smart-536e665a-072c-45e9-818e-5b0b7f5cb9ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815872366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3815872366
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.202656058
Short name T438
Test name
Test status
Simulation time 243862698 ps
CPU time 1.11 seconds
Started Jun 27 05:41:58 PM PDT 24
Finished Jun 27 05:42:01 PM PDT 24
Peak memory 217380 kb
Host smart-5f58ee47-7d6f-498d-827e-b7b3301188b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202656058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.202656058
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3575487360
Short name T203
Test name
Test status
Simulation time 121656700 ps
CPU time 0.8 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:04 PM PDT 24
Peak memory 199932 kb
Host smart-42382882-58f9-44da-b7bd-3a0d89785b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575487360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3575487360
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1003822946
Short name T217
Test name
Test status
Simulation time 1564164874 ps
CPU time 6.62 seconds
Started Jun 27 05:42:00 PM PDT 24
Finished Jun 27 05:42:09 PM PDT 24
Peak memory 200352 kb
Host smart-7e274ea1-06b6-43b6-a543-d341144d52c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003822946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1003822946
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1466903388
Short name T266
Test name
Test status
Simulation time 176164653 ps
CPU time 1.21 seconds
Started Jun 27 05:42:03 PM PDT 24
Finished Jun 27 05:42:07 PM PDT 24
Peak memory 200040 kb
Host smart-16ea84ae-3937-4dcb-8418-8baa0b7a034c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466903388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1466903388
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.70683896
Short name T243
Test name
Test status
Simulation time 112859330 ps
CPU time 1.21 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:07 PM PDT 24
Peak memory 200264 kb
Host smart-a4374bf5-a94f-407a-a7fd-009c8fa9d7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70683896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.70683896
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2016007394
Short name T396
Test name
Test status
Simulation time 3379397464 ps
CPU time 12.13 seconds
Started Jun 27 05:42:03 PM PDT 24
Finished Jun 27 05:42:18 PM PDT 24
Peak memory 200308 kb
Host smart-addca5c3-707d-4a59-9b16-5b6007c9627b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016007394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2016007394
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3307837519
Short name T264
Test name
Test status
Simulation time 128036691 ps
CPU time 1.71 seconds
Started Jun 27 05:42:00 PM PDT 24
Finished Jun 27 05:42:05 PM PDT 24
Peak memory 200088 kb
Host smart-f458893c-a486-4d7f-818c-47de50cb71e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307837519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3307837519
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1291793214
Short name T146
Test name
Test status
Simulation time 261149650 ps
CPU time 1.65 seconds
Started Jun 27 05:42:00 PM PDT 24
Finished Jun 27 05:42:04 PM PDT 24
Peak memory 200348 kb
Host smart-36a1f90c-149c-4b90-a01e-4cbf5ac6d00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291793214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1291793214
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.463202786
Short name T61
Test name
Test status
Simulation time 67288403 ps
CPU time 0.8 seconds
Started Jun 27 05:42:04 PM PDT 24
Finished Jun 27 05:42:09 PM PDT 24
Peak memory 199852 kb
Host smart-35012e85-1e38-412a-a83d-6eff5529f8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463202786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.463202786
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1047413939
Short name T40
Test name
Test status
Simulation time 1229049215 ps
CPU time 5.56 seconds
Started Jun 27 05:42:07 PM PDT 24
Finished Jun 27 05:42:16 PM PDT 24
Peak memory 221648 kb
Host smart-aa6433d8-e0c0-48c9-8a48-ee4e50963c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047413939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1047413939
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.212656059
Short name T173
Test name
Test status
Simulation time 244166877 ps
CPU time 1.1 seconds
Started Jun 27 05:42:05 PM PDT 24
Finished Jun 27 05:42:10 PM PDT 24
Peak memory 217392 kb
Host smart-2605a013-6c70-4dbf-882c-fc8b5d5947e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212656059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.212656059
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1192246195
Short name T338
Test name
Test status
Simulation time 140912829 ps
CPU time 0.79 seconds
Started Jun 27 05:42:00 PM PDT 24
Finished Jun 27 05:42:03 PM PDT 24
Peak memory 199880 kb
Host smart-ac22f9a1-5a63-48de-beb5-e4ce7ceb4ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192246195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1192246195
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3087573989
Short name T104
Test name
Test status
Simulation time 774580274 ps
CPU time 4.02 seconds
Started Jun 27 05:41:58 PM PDT 24
Finished Jun 27 05:42:03 PM PDT 24
Peak memory 200288 kb
Host smart-ab74d706-6d70-43cc-bd4b-73083468b9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087573989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3087573989
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.4055407443
Short name T419
Test name
Test status
Simulation time 164107798 ps
CPU time 1.23 seconds
Started Jun 27 05:42:05 PM PDT 24
Finished Jun 27 05:42:10 PM PDT 24
Peak memory 200016 kb
Host smart-b462d9b9-de50-4625-8f36-ef83ae102566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055407443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.4055407443
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.4213410009
Short name T292
Test name
Test status
Simulation time 200027825 ps
CPU time 1.51 seconds
Started Jun 27 05:41:59 PM PDT 24
Finished Jun 27 05:42:02 PM PDT 24
Peak memory 200224 kb
Host smart-0ae57f1f-9402-4538-93e6-c79c81657882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213410009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.4213410009
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2025348166
Short name T482
Test name
Test status
Simulation time 3539020389 ps
CPU time 13.19 seconds
Started Jun 27 05:41:58 PM PDT 24
Finished Jun 27 05:42:13 PM PDT 24
Peak memory 208540 kb
Host smart-1c9e42ea-afbf-4280-b3c4-e02b49e6f195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025348166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2025348166
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1227405436
Short name T80
Test name
Test status
Simulation time 125733590 ps
CPU time 1.7 seconds
Started Jun 27 05:42:03 PM PDT 24
Finished Jun 27 05:42:09 PM PDT 24
Peak memory 200032 kb
Host smart-7555c6e6-7248-4a6b-811c-b93313915038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227405436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1227405436
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1514376823
Short name T530
Test name
Test status
Simulation time 94998476 ps
CPU time 0.94 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:04 PM PDT 24
Peak memory 200104 kb
Host smart-93ee3020-4f22-475b-b3cf-95934bfcc724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514376823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1514376823
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.928139941
Short name T62
Test name
Test status
Simulation time 64620312 ps
CPU time 0.82 seconds
Started Jun 27 05:42:09 PM PDT 24
Finished Jun 27 05:42:12 PM PDT 24
Peak memory 199880 kb
Host smart-5a3498ad-cacf-43f0-bffa-748c914c60a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928139941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.928139941
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2626061884
Short name T37
Test name
Test status
Simulation time 1884955270 ps
CPU time 8.03 seconds
Started Jun 27 05:42:00 PM PDT 24
Finished Jun 27 05:42:09 PM PDT 24
Peak memory 217620 kb
Host smart-5314b890-0613-4e75-9697-ce0d023c0099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626061884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2626061884
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.424483397
Short name T423
Test name
Test status
Simulation time 244567194 ps
CPU time 1.04 seconds
Started Jun 27 05:42:04 PM PDT 24
Finished Jun 27 05:42:08 PM PDT 24
Peak memory 217376 kb
Host smart-6dcf627f-42be-4e97-bb49-a3b639429a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424483397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.424483397
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.769320167
Short name T451
Test name
Test status
Simulation time 162897919 ps
CPU time 0.92 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:06 PM PDT 24
Peak memory 199612 kb
Host smart-5e7cdf45-a79c-4a39-8474-8ecc29940b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769320167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.769320167
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3533215466
Short name T99
Test name
Test status
Simulation time 806862336 ps
CPU time 4.37 seconds
Started Jun 27 05:42:04 PM PDT 24
Finished Jun 27 05:42:12 PM PDT 24
Peak memory 200564 kb
Host smart-2dafb48e-9ff5-44f8-b34b-11f2aff7a266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533215466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3533215466
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2548265057
Short name T182
Test name
Test status
Simulation time 98072931 ps
CPU time 1 seconds
Started Jun 27 05:42:06 PM PDT 24
Finished Jun 27 05:42:11 PM PDT 24
Peak memory 200064 kb
Host smart-52708670-89f8-490d-b816-de24f592c0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548265057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2548265057
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.4054390535
Short name T72
Test name
Test status
Simulation time 116743124 ps
CPU time 1.18 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:06 PM PDT 24
Peak memory 200304 kb
Host smart-0a5d64d1-8eea-41c4-9603-d3042e011b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054390535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.4054390535
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.679470799
Short name T132
Test name
Test status
Simulation time 176032557 ps
CPU time 1.26 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:06 PM PDT 24
Peak memory 199740 kb
Host smart-9abc6659-7641-4bae-87ad-7982fecad92a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679470799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.679470799
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3576074841
Short name T409
Test name
Test status
Simulation time 400918936 ps
CPU time 2.29 seconds
Started Jun 27 05:42:04 PM PDT 24
Finished Jun 27 05:42:10 PM PDT 24
Peak memory 200076 kb
Host smart-8ce0f31f-6dca-4b20-aa5e-87179cca4ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576074841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3576074841
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.4283879558
Short name T201
Test name
Test status
Simulation time 115733643 ps
CPU time 1.09 seconds
Started Jun 27 05:41:58 PM PDT 24
Finished Jun 27 05:42:01 PM PDT 24
Peak memory 200096 kb
Host smart-e22e1707-2fd8-4e24-9b50-1ef8874f951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283879558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.4283879558
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.460097486
Short name T306
Test name
Test status
Simulation time 70404628 ps
CPU time 0.78 seconds
Started Jun 27 05:42:04 PM PDT 24
Finished Jun 27 05:42:08 PM PDT 24
Peak memory 199828 kb
Host smart-0bcc609e-a30d-410c-a5ec-a1392056e998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460097486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.460097486
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1521734125
Short name T287
Test name
Test status
Simulation time 1894340544 ps
CPU time 7.25 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:11 PM PDT 24
Peak memory 217708 kb
Host smart-1156e868-6dbc-4ad5-9845-9d9befa14d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521734125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1521734125
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2270069611
Short name T356
Test name
Test status
Simulation time 252816557 ps
CPU time 1.1 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:07 PM PDT 24
Peak memory 217432 kb
Host smart-9a51de04-cee9-477f-baed-19b70e81710d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270069611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2270069611
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3113649242
Short name T231
Test name
Test status
Simulation time 87528393 ps
CPU time 0.82 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:05 PM PDT 24
Peak memory 199904 kb
Host smart-2d0dd08b-dc54-4c69-bd00-2ae3f3f7df14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113649242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3113649242
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3001809691
Short name T346
Test name
Test status
Simulation time 829495910 ps
CPU time 4.14 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:08 PM PDT 24
Peak memory 200316 kb
Host smart-22a17694-da7f-4132-9855-94ea8dc67412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001809691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3001809691
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.798968503
Short name T447
Test name
Test status
Simulation time 178906838 ps
CPU time 1.31 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:06 PM PDT 24
Peak memory 199796 kb
Host smart-4a5a22e5-db2c-460f-9c54-215e3913a5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798968503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.798968503
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.88856723
Short name T73
Test name
Test status
Simulation time 118571013 ps
CPU time 1.18 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:07 PM PDT 24
Peak memory 200280 kb
Host smart-9e6f934a-eb54-4143-ac99-372d4a8cbd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88856723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.88856723
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1049464412
Short name T102
Test name
Test status
Simulation time 9342738246 ps
CPU time 30.07 seconds
Started Jun 27 05:42:03 PM PDT 24
Finished Jun 27 05:42:37 PM PDT 24
Peak memory 200404 kb
Host smart-85d40601-e8f8-4ab8-9a31-5b13e15b567f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049464412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1049464412
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3273834201
Short name T321
Test name
Test status
Simulation time 333191145 ps
CPU time 2.35 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:06 PM PDT 24
Peak memory 200148 kb
Host smart-8f1cfdf8-dc93-4ff0-a561-625b95dff9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273834201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3273834201
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1594323370
Short name T464
Test name
Test status
Simulation time 271693638 ps
CPU time 1.65 seconds
Started Jun 27 05:42:04 PM PDT 24
Finished Jun 27 05:42:09 PM PDT 24
Peak memory 200300 kb
Host smart-edd7fa1b-b42d-4cb6-a975-d32d3efdcd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594323370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1594323370
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1830613475
Short name T24
Test name
Test status
Simulation time 66898324 ps
CPU time 0.82 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:54 PM PDT 24
Peak memory 199828 kb
Host smart-e01142be-cefa-4c2b-b2f4-88e0024df3c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830613475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1830613475
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1092719270
Short name T405
Test name
Test status
Simulation time 2178041485 ps
CPU time 7.26 seconds
Started Jun 27 05:40:49 PM PDT 24
Finished Jun 27 05:40:58 PM PDT 24
Peak memory 220816 kb
Host smart-e7446889-4632-4692-acb8-5424e746b5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092719270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1092719270
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1267458116
Short name T542
Test name
Test status
Simulation time 244703520 ps
CPU time 1.11 seconds
Started Jun 27 05:40:53 PM PDT 24
Finished Jun 27 05:40:57 PM PDT 24
Peak memory 216916 kb
Host smart-649db57f-cea1-4bda-af76-f75af5a63303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267458116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1267458116
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2740482877
Short name T324
Test name
Test status
Simulation time 82743346 ps
CPU time 0.73 seconds
Started Jun 27 05:40:48 PM PDT 24
Finished Jun 27 05:40:50 PM PDT 24
Peak memory 199900 kb
Host smart-e1333bb5-20b2-4e19-9d1e-7c39e6e1201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740482877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2740482877
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1852624801
Short name T91
Test name
Test status
Simulation time 800903436 ps
CPU time 4.12 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:58 PM PDT 24
Peak memory 200344 kb
Host smart-e5d785df-a0b7-4f11-a9f6-3e5aae57b84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852624801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1852624801
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.86813538
Short name T64
Test name
Test status
Simulation time 16925954744 ps
CPU time 24.45 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:41:17 PM PDT 24
Peak memory 218208 kb
Host smart-1f20b873-efe9-488d-b629-80fb2ddbf9c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86813538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.86813538
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2576003133
Short name T236
Test name
Test status
Simulation time 99980368 ps
CPU time 1.01 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:40:52 PM PDT 24
Peak memory 199976 kb
Host smart-b228486e-9712-4959-bde0-5de438736cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576003133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2576003133
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2214877542
Short name T341
Test name
Test status
Simulation time 125289383 ps
CPU time 1.23 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:40:54 PM PDT 24
Peak memory 200240 kb
Host smart-d8114e62-3a14-4b75-b977-4f3d9a1d41c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214877542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2214877542
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.848943333
Short name T276
Test name
Test status
Simulation time 1279544673 ps
CPU time 6.56 seconds
Started Jun 27 05:40:48 PM PDT 24
Finished Jun 27 05:40:56 PM PDT 24
Peak memory 208472 kb
Host smart-a22ebc28-a196-4356-a8ef-82afc8c6bd57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848943333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.848943333
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2884472978
Short name T383
Test name
Test status
Simulation time 333826201 ps
CPU time 2.03 seconds
Started Jun 27 05:40:46 PM PDT 24
Finished Jun 27 05:40:50 PM PDT 24
Peak memory 200012 kb
Host smart-76bbb7ad-8f5d-4d76-83c1-3cb2051c5c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884472978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2884472978
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2638989066
Short name T325
Test name
Test status
Simulation time 152622067 ps
CPU time 1.2 seconds
Started Jun 27 05:40:48 PM PDT 24
Finished Jun 27 05:40:51 PM PDT 24
Peak memory 200148 kb
Host smart-e032fa45-67a9-4b48-97d1-17cf8428f371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638989066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2638989066
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.422771410
Short name T378
Test name
Test status
Simulation time 64615513 ps
CPU time 0.75 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:07 PM PDT 24
Peak memory 199780 kb
Host smart-3919caf5-fb43-4624-b852-19cced71e9b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422771410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.422771410
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3685418566
Short name T415
Test name
Test status
Simulation time 1221296670 ps
CPU time 5.36 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:09 PM PDT 24
Peak memory 221696 kb
Host smart-1c57d906-e9f8-42ef-a358-4ac4aee3d47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685418566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3685418566
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1951304872
Short name T480
Test name
Test status
Simulation time 244039808 ps
CPU time 1.08 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:06 PM PDT 24
Peak memory 217464 kb
Host smart-18b9d625-fd26-4590-8aa0-042f83cef55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951304872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1951304872
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.644663965
Short name T261
Test name
Test status
Simulation time 223235784 ps
CPU time 0.91 seconds
Started Jun 27 05:42:03 PM PDT 24
Finished Jun 27 05:42:08 PM PDT 24
Peak memory 199824 kb
Host smart-2e479bf5-e076-4e6d-8118-b3ba7a5fc7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644663965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.644663965
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3257142366
Short name T304
Test name
Test status
Simulation time 1709837571 ps
CPU time 6.77 seconds
Started Jun 27 05:41:59 PM PDT 24
Finished Jun 27 05:42:07 PM PDT 24
Peak memory 200384 kb
Host smart-3d92bf44-5d34-4483-9490-d568f33ee6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257142366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3257142366
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1324876449
Short name T166
Test name
Test status
Simulation time 105985572 ps
CPU time 1.07 seconds
Started Jun 27 05:42:05 PM PDT 24
Finished Jun 27 05:42:10 PM PDT 24
Peak memory 200064 kb
Host smart-7f816bc7-bf9f-4ad0-a6a1-a719d820039b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324876449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1324876449
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2592658646
Short name T440
Test name
Test status
Simulation time 257823611 ps
CPU time 1.45 seconds
Started Jun 27 05:42:05 PM PDT 24
Finished Jun 27 05:42:10 PM PDT 24
Peak memory 200256 kb
Host smart-c9496bc3-be93-4215-a08a-95f60e58b855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592658646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2592658646
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1870585054
Short name T467
Test name
Test status
Simulation time 1378908880 ps
CPU time 7.9 seconds
Started Jun 27 05:42:03 PM PDT 24
Finished Jun 27 05:42:15 PM PDT 24
Peak memory 208520 kb
Host smart-d101dad6-c179-4a16-ae7d-2710e263a410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870585054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1870585054
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1703426467
Short name T69
Test name
Test status
Simulation time 312493447 ps
CPU time 2.07 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:06 PM PDT 24
Peak memory 208388 kb
Host smart-866374c1-f90d-418a-918b-1855805d74a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703426467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1703426467
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1791497874
Short name T311
Test name
Test status
Simulation time 236873458 ps
CPU time 1.39 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:06 PM PDT 24
Peak memory 200100 kb
Host smart-8dbe4b47-1915-4073-b891-1bb0466522c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791497874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1791497874
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3624011190
Short name T474
Test name
Test status
Simulation time 64654980 ps
CPU time 0.77 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:06 PM PDT 24
Peak memory 199752 kb
Host smart-0f65fe73-186f-4e59-9b7a-ddab6dbd973b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624011190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3624011190
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3255650163
Short name T355
Test name
Test status
Simulation time 2361553875 ps
CPU time 7.87 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:14 PM PDT 24
Peak memory 217796 kb
Host smart-e0011413-fe9f-4012-a724-1c58fac360e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255650163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3255650163
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3993439895
Short name T351
Test name
Test status
Simulation time 244250820 ps
CPU time 1.06 seconds
Started Jun 27 05:42:04 PM PDT 24
Finished Jun 27 05:42:08 PM PDT 24
Peak memory 217376 kb
Host smart-b017ec7c-ce31-4fc4-84b6-8a85d90b4a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993439895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3993439895
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1565334447
Short name T444
Test name
Test status
Simulation time 160856907 ps
CPU time 0.9 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:07 PM PDT 24
Peak memory 199832 kb
Host smart-15c38cae-483e-4cc1-aa06-44dd19727452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565334447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1565334447
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1515309468
Short name T448
Test name
Test status
Simulation time 1840414438 ps
CPU time 6.57 seconds
Started Jun 27 05:42:04 PM PDT 24
Finished Jun 27 05:42:14 PM PDT 24
Peak memory 200344 kb
Host smart-739977f5-d6c6-4889-a3a0-957f02ef9c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515309468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1515309468
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1123014672
Short name T13
Test name
Test status
Simulation time 147232754 ps
CPU time 1.21 seconds
Started Jun 27 05:42:06 PM PDT 24
Finished Jun 27 05:42:11 PM PDT 24
Peak memory 200064 kb
Host smart-6034efc3-039b-470a-97e1-a7e3da8032dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123014672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1123014672
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.278788108
Short name T478
Test name
Test status
Simulation time 109914839 ps
CPU time 1.16 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:06 PM PDT 24
Peak memory 200276 kb
Host smart-3e2e3670-d5af-405f-bef9-acd9e5b72d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278788108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.278788108
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2105815333
Short name T101
Test name
Test status
Simulation time 1171160032 ps
CPU time 5.57 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:11 PM PDT 24
Peak memory 208512 kb
Host smart-a224bf64-83e7-448a-952c-38e5a452b343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105815333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2105815333
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3107285696
Short name T154
Test name
Test status
Simulation time 280982234 ps
CPU time 2.06 seconds
Started Jun 27 05:42:02 PM PDT 24
Finished Jun 27 05:42:08 PM PDT 24
Peak memory 200052 kb
Host smart-2cb4d3e9-d080-4800-a657-0334fe7dd9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107285696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3107285696
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.742230463
Short name T10
Test name
Test status
Simulation time 68325731 ps
CPU time 0.77 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:04 PM PDT 24
Peak memory 200096 kb
Host smart-203e8069-cde8-4785-8141-7a50510eea9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742230463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.742230463
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2513376405
Short name T209
Test name
Test status
Simulation time 72958019 ps
CPU time 0.82 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:22 PM PDT 24
Peak memory 199860 kb
Host smart-e2a8b04c-041d-4756-9534-7aea4ccb7795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513376405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2513376405
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1089982998
Short name T39
Test name
Test status
Simulation time 2366040371 ps
CPU time 7.58 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:28 PM PDT 24
Peak memory 217832 kb
Host smart-d70aef57-deab-4423-b0c5-34725de46ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089982998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1089982998
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3501946465
Short name T377
Test name
Test status
Simulation time 243821781 ps
CPU time 1.14 seconds
Started Jun 27 05:42:19 PM PDT 24
Finished Jun 27 05:42:22 PM PDT 24
Peak memory 217456 kb
Host smart-b75b4a12-c9fa-4c1d-849e-3b1c0890e5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501946465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3501946465
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1405667687
Short name T18
Test name
Test status
Simulation time 212234107 ps
CPU time 0.9 seconds
Started Jun 27 05:42:01 PM PDT 24
Finished Jun 27 05:42:04 PM PDT 24
Peak memory 199868 kb
Host smart-0cefbaf3-d506-424a-9d66-9dcb34f23fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405667687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1405667687
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1211118419
Short name T74
Test name
Test status
Simulation time 1261116102 ps
CPU time 4.7 seconds
Started Jun 27 05:42:00 PM PDT 24
Finished Jun 27 05:42:07 PM PDT 24
Peak memory 200340 kb
Host smart-0a9edd76-0a8c-4974-80e5-89d041202cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211118419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1211118419
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2291213640
Short name T488
Test name
Test status
Simulation time 147953958 ps
CPU time 1.09 seconds
Started Jun 27 05:42:21 PM PDT 24
Finished Jun 27 05:42:25 PM PDT 24
Peak memory 200076 kb
Host smart-be2f9779-0255-42ba-9695-261de04304e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291213640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2291213640
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2166014286
Short name T538
Test name
Test status
Simulation time 194693387 ps
CPU time 1.41 seconds
Started Jun 27 05:42:04 PM PDT 24
Finished Jun 27 05:42:09 PM PDT 24
Peak memory 200500 kb
Host smart-803653b6-3058-45f4-83c9-0d86bd143f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166014286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2166014286
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.253050864
Short name T205
Test name
Test status
Simulation time 10440862580 ps
CPU time 37.26 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:43:06 PM PDT 24
Peak memory 209900 kb
Host smart-95044b2b-e450-4a9f-8650-dd4c1a46802b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253050864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.253050864
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3292562474
Short name T269
Test name
Test status
Simulation time 324413547 ps
CPU time 2.03 seconds
Started Jun 27 05:42:21 PM PDT 24
Finished Jun 27 05:42:27 PM PDT 24
Peak memory 200052 kb
Host smart-e13025a6-4a93-437b-b40b-91e5022e33fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292562474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3292562474
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.442604727
Short name T75
Test name
Test status
Simulation time 83189544 ps
CPU time 0.89 seconds
Started Jun 27 05:42:04 PM PDT 24
Finished Jun 27 05:42:08 PM PDT 24
Peak memory 200292 kb
Host smart-19ff69be-6161-464e-b459-607a3b5fe3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442604727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.442604727
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1270577709
Short name T191
Test name
Test status
Simulation time 65664859 ps
CPU time 0.72 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:31 PM PDT 24
Peak memory 199884 kb
Host smart-1ebdb1b9-cd38-4fe2-9758-58e1f16da3df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270577709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1270577709
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.897258037
Short name T33
Test name
Test status
Simulation time 2372168320 ps
CPU time 8.3 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:29 PM PDT 24
Peak memory 217880 kb
Host smart-42058158-d913-4c4b-8fd1-a7541ff8877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897258037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.897258037
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.517842535
Short name T210
Test name
Test status
Simulation time 243624475 ps
CPU time 1.02 seconds
Started Jun 27 05:42:20 PM PDT 24
Finished Jun 27 05:42:24 PM PDT 24
Peak memory 217452 kb
Host smart-5350743b-8be4-4851-b99d-a579afc07b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517842535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.517842535
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.4140174242
Short name T300
Test name
Test status
Simulation time 91856355 ps
CPU time 0.76 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:21 PM PDT 24
Peak memory 199920 kb
Host smart-25870988-a883-4597-8c51-61dea185a00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140174242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.4140174242
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1417014671
Short name T66
Test name
Test status
Simulation time 1031779076 ps
CPU time 4.84 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:26 PM PDT 24
Peak memory 200372 kb
Host smart-ab4d0252-52c1-4acd-9fc6-12b861250ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417014671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1417014671
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.4114775776
Short name T174
Test name
Test status
Simulation time 175164203 ps
CPU time 1.18 seconds
Started Jun 27 05:42:21 PM PDT 24
Finished Jun 27 05:42:26 PM PDT 24
Peak memory 200064 kb
Host smart-82d54f8e-a0f0-4b03-9a54-72643be9f86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114775776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.4114775776
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1232664431
Short name T77
Test name
Test status
Simulation time 200899570 ps
CPU time 1.54 seconds
Started Jun 27 05:42:17 PM PDT 24
Finished Jun 27 05:42:20 PM PDT 24
Peak memory 200224 kb
Host smart-c38fae40-9e03-4171-a5a0-9fffc01823f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232664431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1232664431
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3569600107
Short name T436
Test name
Test status
Simulation time 1885923817 ps
CPU time 8.17 seconds
Started Jun 27 05:42:19 PM PDT 24
Finished Jun 27 05:42:30 PM PDT 24
Peak memory 208536 kb
Host smart-7adb54d6-d8ab-4372-9e24-8c32e03b0633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569600107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3569600107
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3270524871
Short name T487
Test name
Test status
Simulation time 288371719 ps
CPU time 1.97 seconds
Started Jun 27 05:42:19 PM PDT 24
Finished Jun 27 05:42:24 PM PDT 24
Peak memory 200068 kb
Host smart-e4af21eb-cb82-4167-a4a9-24bcd7a8236d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270524871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3270524871
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1345010634
Short name T273
Test name
Test status
Simulation time 151817904 ps
CPU time 1.13 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:22 PM PDT 24
Peak memory 200092 kb
Host smart-4026a474-26f1-42fa-978b-71e7b167146c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345010634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1345010634
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1148756094
Short name T184
Test name
Test status
Simulation time 68207057 ps
CPU time 0.78 seconds
Started Jun 27 05:42:21 PM PDT 24
Finished Jun 27 05:42:26 PM PDT 24
Peak memory 199764 kb
Host smart-a2d82820-b2cb-4f47-a10a-5e89277409c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148756094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1148756094
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.4050399664
Short name T400
Test name
Test status
Simulation time 1224449848 ps
CPU time 5.85 seconds
Started Jun 27 05:42:19 PM PDT 24
Finished Jun 27 05:42:27 PM PDT 24
Peak memory 217692 kb
Host smart-3010ea8b-0c1c-41e7-aa29-fb52960a08a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050399664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.4050399664
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3763251005
Short name T375
Test name
Test status
Simulation time 244240183 ps
CPU time 1.05 seconds
Started Jun 27 05:42:22 PM PDT 24
Finished Jun 27 05:42:28 PM PDT 24
Peak memory 217376 kb
Host smart-ad5d2e9f-7182-4589-880a-b64a696d3141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763251005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3763251005
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.4241889517
Short name T506
Test name
Test status
Simulation time 168370354 ps
CPU time 0.87 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:21 PM PDT 24
Peak memory 199904 kb
Host smart-03cc2705-887b-440e-b11d-4d5bebb9c1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241889517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.4241889517
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1649943382
Short name T6
Test name
Test status
Simulation time 1722917211 ps
CPU time 6.6 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:36 PM PDT 24
Peak memory 200348 kb
Host smart-f763f0f4-691d-4410-9611-06f45c4d1bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649943382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1649943382
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3712859176
Short name T290
Test name
Test status
Simulation time 96997278 ps
CPU time 1.02 seconds
Started Jun 27 05:42:20 PM PDT 24
Finished Jun 27 05:42:25 PM PDT 24
Peak memory 200028 kb
Host smart-4a54fbd5-c146-4733-8e1c-628feffd0944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712859176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3712859176
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1968467186
Short name T189
Test name
Test status
Simulation time 198537300 ps
CPU time 1.4 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:22 PM PDT 24
Peak memory 200248 kb
Host smart-6a5394c1-6ebf-4f86-8219-8db66c2d4e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968467186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1968467186
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3252066076
Short name T369
Test name
Test status
Simulation time 1518466268 ps
CPU time 7.68 seconds
Started Jun 27 05:42:20 PM PDT 24
Finished Jun 27 05:42:32 PM PDT 24
Peak memory 200172 kb
Host smart-7e8c2b6b-6218-488c-b708-b1da0fb7e522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252066076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3252066076
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3089782588
Short name T234
Test name
Test status
Simulation time 123077460 ps
CPU time 1.6 seconds
Started Jun 27 05:42:19 PM PDT 24
Finished Jun 27 05:42:23 PM PDT 24
Peak memory 208300 kb
Host smart-df131629-a05e-44ee-8d9c-992157cd61fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089782588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3089782588
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3639243494
Short name T206
Test name
Test status
Simulation time 233781851 ps
CPU time 1.3 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:32 PM PDT 24
Peak memory 200072 kb
Host smart-7561fd33-9d2c-40cc-83d1-07be0f58f7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639243494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3639243494
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1073641852
Short name T299
Test name
Test status
Simulation time 67706982 ps
CPU time 0.78 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:29 PM PDT 24
Peak memory 199876 kb
Host smart-78fd0e3c-8337-4796-9d6c-525a2f7a03fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073641852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1073641852
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.566354480
Short name T42
Test name
Test status
Simulation time 2162474005 ps
CPU time 8.56 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:39 PM PDT 24
Peak memory 217660 kb
Host smart-626f7a27-51e1-41b1-81ce-04a44f72e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566354480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.566354480
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.777128747
Short name T361
Test name
Test status
Simulation time 244611560 ps
CPU time 1.08 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:22 PM PDT 24
Peak memory 217488 kb
Host smart-deabd552-4001-4c0a-8769-b8fee282e469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777128747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.777128747
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1893563793
Short name T307
Test name
Test status
Simulation time 159777519 ps
CPU time 0.82 seconds
Started Jun 27 05:42:17 PM PDT 24
Finished Jun 27 05:42:20 PM PDT 24
Peak memory 200088 kb
Host smart-fb2cac03-22db-4c65-a66e-2007821b35e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893563793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1893563793
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1887424516
Short name T127
Test name
Test status
Simulation time 1373630381 ps
CPU time 5.58 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:34 PM PDT 24
Peak memory 200340 kb
Host smart-2bc5073d-cf7c-4c8f-a3c9-11e561313883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887424516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1887424516
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.719735935
Short name T169
Test name
Test status
Simulation time 183202761 ps
CPU time 1.18 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:21 PM PDT 24
Peak memory 200032 kb
Host smart-b43557e0-fcdc-498c-a3ea-3b479639e0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719735935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.719735935
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2504986755
Short name T137
Test name
Test status
Simulation time 248456590 ps
CPU time 1.47 seconds
Started Jun 27 05:42:19 PM PDT 24
Finished Jun 27 05:42:23 PM PDT 24
Peak memory 200332 kb
Host smart-8bb42933-e8e6-4bbb-baa2-8c6f8c1618b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504986755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2504986755
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3463009021
Short name T12
Test name
Test status
Simulation time 5624665130 ps
CPU time 18.38 seconds
Started Jun 27 05:42:21 PM PDT 24
Finished Jun 27 05:42:44 PM PDT 24
Peak memory 208488 kb
Host smart-1c84fa49-d2ed-441a-ad8a-8e715a598ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463009021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3463009021
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3698971968
Short name T328
Test name
Test status
Simulation time 241152634 ps
CPU time 1.71 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:23 PM PDT 24
Peak memory 200048 kb
Host smart-4ca179f6-da1f-43cc-b93a-077e300e3b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698971968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3698971968
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1123030881
Short name T1
Test name
Test status
Simulation time 84275509 ps
CPU time 0.81 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:22 PM PDT 24
Peak memory 200112 kb
Host smart-d271b5c2-618c-4424-9ca8-76c389923b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123030881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1123030881
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2061221211
Short name T148
Test name
Test status
Simulation time 63071028 ps
CPU time 0.75 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:35 PM PDT 24
Peak memory 199884 kb
Host smart-af783c68-0373-48c3-b9e0-6e161769987f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061221211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2061221211
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.4038886013
Short name T350
Test name
Test status
Simulation time 1233122448 ps
CPU time 5.49 seconds
Started Jun 27 05:42:17 PM PDT 24
Finished Jun 27 05:42:25 PM PDT 24
Peak memory 217528 kb
Host smart-1488d9ba-e17c-4dad-8fdb-282c2f3f214d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038886013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.4038886013
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1220246801
Short name T97
Test name
Test status
Simulation time 244399314 ps
CPU time 1.04 seconds
Started Jun 27 05:42:21 PM PDT 24
Finished Jun 27 05:42:26 PM PDT 24
Peak memory 217388 kb
Host smart-402d3198-65b8-4d96-846e-bce93dc03ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220246801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1220246801
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3664026043
Short name T491
Test name
Test status
Simulation time 119286347 ps
CPU time 0.79 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:31 PM PDT 24
Peak memory 199908 kb
Host smart-5089598c-bce0-41cc-89f9-508793b2cbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664026043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3664026043
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1545369853
Short name T503
Test name
Test status
Simulation time 998167147 ps
CPU time 4.59 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:25 PM PDT 24
Peak memory 200344 kb
Host smart-2cf6feac-2f66-44a5-8b10-95cc682824f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545369853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1545369853
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2084350078
Short name T511
Test name
Test status
Simulation time 91829984 ps
CPU time 1 seconds
Started Jun 27 05:42:19 PM PDT 24
Finished Jun 27 05:42:23 PM PDT 24
Peak memory 200040 kb
Host smart-f8271a3d-1ca0-428e-bdc5-86c75a7ac860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084350078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2084350078
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3137930110
Short name T459
Test name
Test status
Simulation time 118287579 ps
CPU time 1.17 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:22 PM PDT 24
Peak memory 200484 kb
Host smart-fe9d1679-ebf1-4876-a277-c98e1c0d506c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137930110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3137930110
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.417591076
Short name T98
Test name
Test status
Simulation time 3669861742 ps
CPU time 17.68 seconds
Started Jun 27 05:42:22 PM PDT 24
Finished Jun 27 05:42:44 PM PDT 24
Peak memory 200344 kb
Host smart-3e6ecd69-0092-4ea6-976f-f44109ebba77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417591076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.417591076
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2721906891
Short name T481
Test name
Test status
Simulation time 132613600 ps
CPU time 1.64 seconds
Started Jun 27 05:42:21 PM PDT 24
Finished Jun 27 05:42:27 PM PDT 24
Peak memory 208204 kb
Host smart-6aa6ab1e-4b47-4524-9d37-32e9f1cb5893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721906891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2721906891
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3354383297
Short name T484
Test name
Test status
Simulation time 200745558 ps
CPU time 1.31 seconds
Started Jun 27 05:42:18 PM PDT 24
Finished Jun 27 05:42:22 PM PDT 24
Peak memory 200080 kb
Host smart-07a1843a-bef4-4004-8cdb-4cab238ee054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354383297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3354383297
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1950503870
Short name T308
Test name
Test status
Simulation time 78153799 ps
CPU time 0.79 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:31 PM PDT 24
Peak memory 199860 kb
Host smart-c9baf199-43f9-41a7-85e7-5cb814efdba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950503870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1950503870
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1705918623
Short name T29
Test name
Test status
Simulation time 1888914516 ps
CPU time 7.56 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:37 PM PDT 24
Peak memory 217340 kb
Host smart-bad853ad-6706-4b0b-85dd-23750bb8c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705918623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1705918623
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1063691639
Short name T310
Test name
Test status
Simulation time 248701330 ps
CPU time 1.06 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:32 PM PDT 24
Peak memory 217420 kb
Host smart-fe0a4a07-628b-49ca-9f2a-7d6406894a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063691639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1063691639
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2772420593
Short name T395
Test name
Test status
Simulation time 196441629 ps
CPU time 0.9 seconds
Started Jun 27 05:42:19 PM PDT 24
Finished Jun 27 05:42:23 PM PDT 24
Peak memory 199936 kb
Host smart-1494ecb0-bb1a-4782-a94f-f5dfaa266826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772420593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2772420593
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3234943506
Short name T297
Test name
Test status
Simulation time 1621130837 ps
CPU time 6.18 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:39 PM PDT 24
Peak memory 200316 kb
Host smart-c851aa10-1ebf-4afe-8f7a-aa1bb10a8e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234943506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3234943506
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2442330009
Short name T171
Test name
Test status
Simulation time 157496984 ps
CPU time 1.07 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:30 PM PDT 24
Peak memory 200064 kb
Host smart-9cbdb5af-0c1d-440b-ad9e-dc6f819c1b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442330009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2442330009
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1797773230
Short name T501
Test name
Test status
Simulation time 120987204 ps
CPU time 1.31 seconds
Started Jun 27 05:42:20 PM PDT 24
Finished Jun 27 05:42:25 PM PDT 24
Peak memory 200140 kb
Host smart-af887748-1837-44f9-afed-14ba27680b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797773230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1797773230
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2022937234
Short name T323
Test name
Test status
Simulation time 2040548504 ps
CPU time 7.96 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:38 PM PDT 24
Peak memory 216648 kb
Host smart-bbf8f02d-9cab-4f32-af6b-6a9c693d9f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022937234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2022937234
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1973424680
Short name T536
Test name
Test status
Simulation time 126364878 ps
CPU time 1.54 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:31 PM PDT 24
Peak memory 200056 kb
Host smart-1dcc8eef-5a7f-4826-aebe-dda4fd38cd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973424680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1973424680
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1692085919
Short name T476
Test name
Test status
Simulation time 111321052 ps
CPU time 1.03 seconds
Started Jun 27 05:42:22 PM PDT 24
Finished Jun 27 05:42:28 PM PDT 24
Peak memory 200020 kb
Host smart-eb6ecd98-6466-4a21-b35a-34d1736e3b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692085919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1692085919
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3585942215
Short name T493
Test name
Test status
Simulation time 65948008 ps
CPU time 0.75 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:32 PM PDT 24
Peak memory 199828 kb
Host smart-b3f5cf2f-b6d4-4d47-b678-ed173c407a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585942215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3585942215
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4220688408
Short name T28
Test name
Test status
Simulation time 1897167954 ps
CPU time 7.22 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:38 PM PDT 24
Peak memory 217580 kb
Host smart-584d21af-d95d-4d0b-8f3b-b34be8ada770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220688408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4220688408
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.159115715
Short name T543
Test name
Test status
Simulation time 243703034 ps
CPU time 1.03 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:30 PM PDT 24
Peak memory 217412 kb
Host smart-0596f60c-3255-4514-8e16-9fc6caf57da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159115715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.159115715
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1163822244
Short name T216
Test name
Test status
Simulation time 212578232 ps
CPU time 0.88 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:30 PM PDT 24
Peak memory 199900 kb
Host smart-3adc8467-ef5b-4491-a40a-f9ee7c050630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163822244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1163822244
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.102110831
Short name T93
Test name
Test status
Simulation time 1585258109 ps
CPU time 6.24 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:35 PM PDT 24
Peak memory 200324 kb
Host smart-ac08901d-0a01-4e10-b991-b6cd8f8ddb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102110831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.102110831
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.4184732351
Short name T316
Test name
Test status
Simulation time 92856729 ps
CPU time 0.99 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:32 PM PDT 24
Peak memory 200092 kb
Host smart-b18f3a3f-6d2f-41bc-a447-be7bfd08f812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184732351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.4184732351
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.964604822
Short name T366
Test name
Test status
Simulation time 112703417 ps
CPU time 1.18 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:33 PM PDT 24
Peak memory 200324 kb
Host smart-71eba030-dfc1-465e-9b98-4418cff63567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964604822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.964604822
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1704602110
Short name T200
Test name
Test status
Simulation time 336449158 ps
CPU time 1.88 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:33 PM PDT 24
Peak memory 200224 kb
Host smart-c2c1ae39-dfb5-46d3-b4a6-cd79233e0c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704602110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1704602110
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1692888510
Short name T303
Test name
Test status
Simulation time 161040514 ps
CPU time 1.82 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:32 PM PDT 24
Peak memory 200028 kb
Host smart-bca9f4f5-e04f-40e1-91ce-e4686c4701fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692888510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1692888510
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3390916004
Short name T510
Test name
Test status
Simulation time 220276778 ps
CPU time 1.38 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:33 PM PDT 24
Peak memory 200104 kb
Host smart-2a5e61f5-0018-4945-8248-2001ff3092a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390916004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3390916004
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.214856226
Short name T332
Test name
Test status
Simulation time 63857943 ps
CPU time 0.77 seconds
Started Jun 27 05:42:25 PM PDT 24
Finished Jun 27 05:42:34 PM PDT 24
Peak memory 199880 kb
Host smart-1f443248-6d88-4d82-923c-b441f2057b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214856226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.214856226
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.352317882
Short name T457
Test name
Test status
Simulation time 1232744471 ps
CPU time 5.52 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:37 PM PDT 24
Peak memory 217344 kb
Host smart-a1e5df80-6097-4e1a-85b2-b83d3d3364c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352317882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.352317882
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.511391602
Short name T404
Test name
Test status
Simulation time 244152902 ps
CPU time 1.12 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:34 PM PDT 24
Peak memory 217464 kb
Host smart-f647b434-6b03-41f7-aa00-c0f4aabf4ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511391602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.511391602
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2130768965
Short name T368
Test name
Test status
Simulation time 130403160 ps
CPU time 0.8 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:35 PM PDT 24
Peak memory 199660 kb
Host smart-01477375-422b-4f87-96ec-aff662298eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130768965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2130768965
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1928970191
Short name T125
Test name
Test status
Simulation time 1539621174 ps
CPU time 6.32 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:38 PM PDT 24
Peak memory 200356 kb
Host smart-3e057a9e-6fd0-4227-854e-d3be5a914b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928970191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1928970191
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1844319078
Short name T534
Test name
Test status
Simulation time 100870005 ps
CPU time 1.01 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:35 PM PDT 24
Peak memory 199856 kb
Host smart-63d4c934-d99e-4984-b62b-f45c9f3c07b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844319078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1844319078
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1011393484
Short name T161
Test name
Test status
Simulation time 207830132 ps
CPU time 1.35 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:34 PM PDT 24
Peak memory 200220 kb
Host smart-dc58ce42-88de-4bd4-bcdf-2b44fe7092dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011393484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1011393484
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.164507230
Short name T435
Test name
Test status
Simulation time 3831191569 ps
CPU time 14.38 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:49 PM PDT 24
Peak memory 208628 kb
Host smart-f2615617-22e2-475f-b247-f24d8276234b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164507230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.164507230
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.41690756
Short name T465
Test name
Test status
Simulation time 468195946 ps
CPU time 2.61 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:37 PM PDT 24
Peak memory 200040 kb
Host smart-7e56cf5d-e786-4282-b3d0-d90bc015addd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41690756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.41690756
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4087050337
Short name T215
Test name
Test status
Simulation time 218371265 ps
CPU time 1.33 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:32 PM PDT 24
Peak memory 200108 kb
Host smart-dc6abafa-59e7-4570-86bb-bf51baed1e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087050337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4087050337
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3897137389
Short name T260
Test name
Test status
Simulation time 148368437 ps
CPU time 0.93 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:55 PM PDT 24
Peak memory 199880 kb
Host smart-94d6bd86-1948-454f-ad05-89d0b6b51288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897137389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3897137389
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3461621075
Short name T34
Test name
Test status
Simulation time 2373226234 ps
CPU time 7.69 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:41:00 PM PDT 24
Peak memory 217768 kb
Host smart-d2046f59-cb98-4e91-8c4a-e97a527cbc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461621075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3461621075
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1705848820
Short name T240
Test name
Test status
Simulation time 244068753 ps
CPU time 1.21 seconds
Started Jun 27 05:40:52 PM PDT 24
Finished Jun 27 05:40:56 PM PDT 24
Peak memory 217276 kb
Host smart-269f238c-63ee-4b4e-9c94-a22f536b35ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705848820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1705848820
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1542922571
Short name T19
Test name
Test status
Simulation time 210741657 ps
CPU time 0.93 seconds
Started Jun 27 05:40:52 PM PDT 24
Finished Jun 27 05:40:56 PM PDT 24
Peak memory 199880 kb
Host smart-0a9379bc-6a72-4627-b5fa-1c0e71b5aa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542922571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1542922571
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1271730846
Short name T320
Test name
Test status
Simulation time 919713272 ps
CPU time 4.92 seconds
Started Jun 27 05:40:49 PM PDT 24
Finished Jun 27 05:40:56 PM PDT 24
Peak memory 200344 kb
Host smart-1a077cd6-75cb-4e6a-b2de-3ee32e583575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271730846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1271730846
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.552160365
Short name T58
Test name
Test status
Simulation time 8296051030 ps
CPU time 13.85 seconds
Started Jun 27 05:40:52 PM PDT 24
Finished Jun 27 05:41:09 PM PDT 24
Peak memory 217168 kb
Host smart-9cbed8e4-7158-411e-a8d0-be6e2b629a66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552160365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.552160365
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2050059
Short name T329
Test name
Test status
Simulation time 159495474 ps
CPU time 1.23 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:55 PM PDT 24
Peak memory 200280 kb
Host smart-7a0b6af1-250b-4892-b828-26ea05b21a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2050059
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1841284619
Short name T513
Test name
Test status
Simulation time 118951634 ps
CPU time 1.22 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:55 PM PDT 24
Peak memory 200332 kb
Host smart-d5af491d-978e-4986-a7fc-e32dc0088227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841284619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1841284619
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3375903937
Short name T458
Test name
Test status
Simulation time 7921509437 ps
CPU time 28.57 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:41:22 PM PDT 24
Peak memory 209640 kb
Host smart-67762d72-43f3-48ae-8d5d-4ce663679fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375903937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3375903937
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3357112963
Short name T399
Test name
Test status
Simulation time 137748307 ps
CPU time 1.79 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:40:54 PM PDT 24
Peak memory 200092 kb
Host smart-bad491d3-e523-4dff-8c10-4eea879ead64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357112963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3357112963
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3912965516
Short name T192
Test name
Test status
Simulation time 124609640 ps
CPU time 1.14 seconds
Started Jun 27 05:40:53 PM PDT 24
Finished Jun 27 05:40:57 PM PDT 24
Peak memory 199984 kb
Host smart-55a9f461-6d7d-4cb5-84b6-0329b5d8179c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912965516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3912965516
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3883591840
Short name T220
Test name
Test status
Simulation time 75161085 ps
CPU time 0.76 seconds
Started Jun 27 05:42:27 PM PDT 24
Finished Jun 27 05:42:36 PM PDT 24
Peak memory 199860 kb
Host smart-473c410b-8222-402e-87bd-934ecdb71edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883591840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3883591840
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1859001513
Short name T371
Test name
Test status
Simulation time 1232407454 ps
CPU time 5.51 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:40 PM PDT 24
Peak memory 217736 kb
Host smart-8ef3035a-ffad-4bc2-9c3f-9abcceb6b205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859001513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1859001513
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1566661063
Short name T427
Test name
Test status
Simulation time 243909297 ps
CPU time 1.08 seconds
Started Jun 27 05:42:27 PM PDT 24
Finished Jun 27 05:42:36 PM PDT 24
Peak memory 217320 kb
Host smart-6eaa7dfc-93bb-4649-b900-7a93cb840d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566661063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1566661063
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1993588786
Short name T23
Test name
Test status
Simulation time 167197837 ps
CPU time 0.94 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:35 PM PDT 24
Peak memory 199844 kb
Host smart-7aa892ef-f284-4896-b600-7466a2fb3e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993588786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1993588786
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3345558232
Short name T230
Test name
Test status
Simulation time 1606218694 ps
CPU time 6.39 seconds
Started Jun 27 05:42:25 PM PDT 24
Finished Jun 27 05:42:39 PM PDT 24
Peak memory 200344 kb
Host smart-6be545c3-427c-474d-be03-384d6d6f8e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345558232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3345558232
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2719355246
Short name T388
Test name
Test status
Simulation time 149945511 ps
CPU time 1.15 seconds
Started Jun 27 05:42:21 PM PDT 24
Finished Jun 27 05:42:27 PM PDT 24
Peak memory 200100 kb
Host smart-de8b0c8d-4871-4198-9a9c-0c724a1d66f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719355246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2719355246
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.376167666
Short name T461
Test name
Test status
Simulation time 206819718 ps
CPU time 1.36 seconds
Started Jun 27 05:42:25 PM PDT 24
Finished Jun 27 05:42:35 PM PDT 24
Peak memory 200284 kb
Host smart-ce97439b-7da9-4ad1-b55a-05c944e7f49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376167666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.376167666
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.663489695
Short name T309
Test name
Test status
Simulation time 1676793415 ps
CPU time 6.61 seconds
Started Jun 27 05:42:27 PM PDT 24
Finished Jun 27 05:42:42 PM PDT 24
Peak memory 200296 kb
Host smart-5cdc9d8a-a539-4a8d-a0d8-34ea9b8a6cf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663489695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.663489695
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.976914180
Short name T176
Test name
Test status
Simulation time 140237753 ps
CPU time 1.77 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:36 PM PDT 24
Peak memory 199980 kb
Host smart-869e211c-958d-412e-8826-f0b40b6b2df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976914180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.976914180
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.4033062287
Short name T473
Test name
Test status
Simulation time 85120156 ps
CPU time 0.82 seconds
Started Jun 27 05:42:25 PM PDT 24
Finished Jun 27 05:42:34 PM PDT 24
Peak memory 200100 kb
Host smart-a6e3f63a-03f5-44aa-b269-76269be472dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033062287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.4033062287
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.4256559701
Short name T425
Test name
Test status
Simulation time 59614845 ps
CPU time 0.71 seconds
Started Jun 27 05:42:27 PM PDT 24
Finished Jun 27 05:42:36 PM PDT 24
Peak memory 199888 kb
Host smart-f4b6fbcb-91b0-4d92-8276-8ee2b6f5be58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256559701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.4256559701
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.4221464899
Short name T475
Test name
Test status
Simulation time 2372923397 ps
CPU time 8.53 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:42 PM PDT 24
Peak memory 217840 kb
Host smart-b3a41a6a-a866-4904-8d46-364f78803169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221464899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.4221464899
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3719430447
Short name T242
Test name
Test status
Simulation time 244609789 ps
CPU time 1.09 seconds
Started Jun 27 05:42:27 PM PDT 24
Finished Jun 27 05:42:37 PM PDT 24
Peak memory 217428 kb
Host smart-b7ddb6f5-a888-4f28-9792-04ed77947ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719430447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3719430447
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4036721882
Short name T17
Test name
Test status
Simulation time 186158622 ps
CPU time 0.94 seconds
Started Jun 27 05:42:27 PM PDT 24
Finished Jun 27 05:42:37 PM PDT 24
Peak memory 199868 kb
Host smart-5cd58fe3-722b-4aad-9d7f-1cad68890960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036721882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4036721882
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1129910315
Short name T492
Test name
Test status
Simulation time 1702674279 ps
CPU time 6.67 seconds
Started Jun 27 05:42:27 PM PDT 24
Finished Jun 27 05:42:42 PM PDT 24
Peak memory 200316 kb
Host smart-15acfd12-3ab9-4b0f-83ce-2dba6a44a990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129910315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1129910315
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1065548964
Short name T241
Test name
Test status
Simulation time 96197740 ps
CPU time 1.06 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:36 PM PDT 24
Peak memory 200096 kb
Host smart-f44819fc-c75c-4f25-99cb-ad6984e602e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065548964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1065548964
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.416243774
Short name T421
Test name
Test status
Simulation time 108482740 ps
CPU time 1.13 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:35 PM PDT 24
Peak memory 200172 kb
Host smart-17ff0567-17e1-4599-a84e-2039aa2f5f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416243774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.416243774
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3413219040
Short name T248
Test name
Test status
Simulation time 2959933493 ps
CPU time 10.61 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:45 PM PDT 24
Peak memory 208500 kb
Host smart-aeea2532-5255-456a-abc2-506e048ab238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413219040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3413219040
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1832776511
Short name T344
Test name
Test status
Simulation time 317027421 ps
CPU time 2.16 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:36 PM PDT 24
Peak memory 200020 kb
Host smart-beabbe0d-176d-48f0-94c8-04351edc875d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832776511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1832776511
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.715932879
Short name T520
Test name
Test status
Simulation time 240324118 ps
CPU time 1.38 seconds
Started Jun 27 05:42:21 PM PDT 24
Finished Jun 27 05:42:26 PM PDT 24
Peak memory 200116 kb
Host smart-036c23e1-2116-4ac2-99ad-a8248e7b1967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715932879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.715932879
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3567800632
Short name T246
Test name
Test status
Simulation time 63859104 ps
CPU time 0.74 seconds
Started Jun 27 05:42:22 PM PDT 24
Finished Jun 27 05:42:28 PM PDT 24
Peak memory 199868 kb
Host smart-fe74bcbd-cfbc-4d34-8a09-d25fc5cbbfac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567800632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3567800632
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1065796692
Short name T38
Test name
Test status
Simulation time 1219003181 ps
CPU time 5.64 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:40 PM PDT 24
Peak memory 216836 kb
Host smart-e2505067-0e89-4c47-aa58-966cafcb7996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065796692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1065796692
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3765870178
Short name T152
Test name
Test status
Simulation time 244122661 ps
CPU time 1.16 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:32 PM PDT 24
Peak memory 217464 kb
Host smart-70401aca-f012-42c3-9ae7-73247ac86b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765870178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3765870178
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2068079956
Short name T21
Test name
Test status
Simulation time 146785623 ps
CPU time 0.79 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:35 PM PDT 24
Peak memory 199904 kb
Host smart-d67f4884-039c-41d6-a3e3-de1441a0b2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068079956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2068079956
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2681293577
Short name T25
Test name
Test status
Simulation time 1176256474 ps
CPU time 4.63 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:34 PM PDT 24
Peak memory 200328 kb
Host smart-43851499-ee5d-44df-9069-57117d5a9ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681293577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2681293577
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3044736308
Short name T65
Test name
Test status
Simulation time 100896876 ps
CPU time 1 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:32 PM PDT 24
Peak memory 200064 kb
Host smart-815b7fa5-d97c-4db4-be91-0b6d67975e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044736308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3044736308
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1093720330
Short name T349
Test name
Test status
Simulation time 113531056 ps
CPU time 1.23 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:36 PM PDT 24
Peak memory 200328 kb
Host smart-6d47b75f-9561-4243-8e4c-ab5a654f2281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093720330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1093720330
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2137266027
Short name T389
Test name
Test status
Simulation time 10718696214 ps
CPU time 35.44 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:43:09 PM PDT 24
Peak memory 200452 kb
Host smart-a7515a96-87ae-4742-8b3e-17c729023094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137266027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2137266027
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1312731240
Short name T245
Test name
Test status
Simulation time 119946567 ps
CPU time 1.48 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:31 PM PDT 24
Peak memory 200100 kb
Host smart-52960f1a-cbae-47ea-b8e9-72e412129631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312731240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1312731240
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1782524448
Short name T277
Test name
Test status
Simulation time 240698934 ps
CPU time 1.43 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:31 PM PDT 24
Peak memory 200284 kb
Host smart-87af4f1f-814a-49fc-9970-170e0ccf8654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782524448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1782524448
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.41237864
Short name T525
Test name
Test status
Simulation time 88568700 ps
CPU time 0.84 seconds
Started Jun 27 05:42:26 PM PDT 24
Finished Jun 27 05:42:35 PM PDT 24
Peak memory 199888 kb
Host smart-1291ee79-3a4e-4b82-8b0e-44059ef29fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41237864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.41237864
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1036253343
Short name T408
Test name
Test status
Simulation time 2376549397 ps
CPU time 8.48 seconds
Started Jun 27 05:42:25 PM PDT 24
Finished Jun 27 05:42:41 PM PDT 24
Peak memory 221632 kb
Host smart-196f2646-b098-45bb-87ce-e5f8adddd18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036253343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1036253343
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1965904561
Short name T365
Test name
Test status
Simulation time 243817803 ps
CPU time 1.06 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:34 PM PDT 24
Peak memory 217476 kb
Host smart-b7570392-b61b-435c-b5b5-24b857dbc281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965904561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1965904561
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3093076520
Short name T500
Test name
Test status
Simulation time 128983640 ps
CPU time 0.85 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:30 PM PDT 24
Peak memory 199848 kb
Host smart-a81f249e-2115-463b-9a3e-5175cf05fa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093076520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3093076520
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.840160649
Short name T394
Test name
Test status
Simulation time 1417623062 ps
CPU time 5.82 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:36 PM PDT 24
Peak memory 200384 kb
Host smart-fe5a0e16-6ed3-400c-961b-d2c91df7376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840160649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.840160649
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2409472086
Short name T159
Test name
Test status
Simulation time 103939470 ps
CPU time 1 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:31 PM PDT 24
Peak memory 200100 kb
Host smart-b53c1986-a123-4f89-ac55-977f98b60378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409472086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2409472086
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1152777467
Short name T175
Test name
Test status
Simulation time 112441261 ps
CPU time 1.19 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:31 PM PDT 24
Peak memory 200280 kb
Host smart-de8d6d72-5e91-40f5-a5c1-b3342580aed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152777467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1152777467
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3749710671
Short name T357
Test name
Test status
Simulation time 3930302326 ps
CPU time 16.03 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:47 PM PDT 24
Peak memory 208612 kb
Host smart-8a28bdc6-bb5b-4d3e-bf5b-68df420f0115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749710671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3749710671
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.558010993
Short name T496
Test name
Test status
Simulation time 360541174 ps
CPU time 2.03 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:33 PM PDT 24
Peak memory 200108 kb
Host smart-3d7be9ff-f171-4e6f-8bbb-84079730bfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558010993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.558010993
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3710261853
Short name T167
Test name
Test status
Simulation time 174079291 ps
CPU time 1.14 seconds
Started Jun 27 05:42:23 PM PDT 24
Finished Jun 27 05:42:30 PM PDT 24
Peak memory 200040 kb
Host smart-5e85ff60-ca39-4701-9abb-fa4ff820aa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710261853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3710261853
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1397320730
Short name T249
Test name
Test status
Simulation time 65160964 ps
CPU time 0.79 seconds
Started Jun 27 05:42:37 PM PDT 24
Finished Jun 27 05:42:42 PM PDT 24
Peak memory 199860 kb
Host smart-83ca18e3-403a-4a1a-8818-17913028a53f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397320730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1397320730
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3177467818
Short name T257
Test name
Test status
Simulation time 2169170918 ps
CPU time 7.98 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:54 PM PDT 24
Peak memory 221592 kb
Host smart-cae2d2eb-7ddf-4d4d-80f3-fa8b29844cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177467818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3177467818
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.748777922
Short name T156
Test name
Test status
Simulation time 244107031 ps
CPU time 1.15 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:49 PM PDT 24
Peak memory 217480 kb
Host smart-5b2106d0-bc9d-4e86-97ac-ae9566bc61eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748777922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.748777922
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.4151124894
Short name T382
Test name
Test status
Simulation time 88904074 ps
CPU time 0.78 seconds
Started Jun 27 05:42:39 PM PDT 24
Finished Jun 27 05:42:44 PM PDT 24
Peak memory 199880 kb
Host smart-63c419c5-b12f-4f26-a520-8030e846a2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151124894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4151124894
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3895820734
Short name T128
Test name
Test status
Simulation time 1862994486 ps
CPU time 6.67 seconds
Started Jun 27 05:42:46 PM PDT 24
Finished Jun 27 05:42:57 PM PDT 24
Peak memory 200300 kb
Host smart-84f1ae2e-abe8-439a-afd6-2ef37724bea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895820734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3895820734
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2180101246
Short name T162
Test name
Test status
Simulation time 103855573 ps
CPU time 0.96 seconds
Started Jun 27 05:42:50 PM PDT 24
Finished Jun 27 05:42:54 PM PDT 24
Peak memory 200004 kb
Host smart-5399c566-454c-4584-a472-db5ad1688123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180101246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2180101246
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.398503963
Short name T313
Test name
Test status
Simulation time 196612851 ps
CPU time 1.4 seconds
Started Jun 27 05:42:24 PM PDT 24
Finished Jun 27 05:42:33 PM PDT 24
Peak memory 200284 kb
Host smart-2901d132-692b-42c9-b52c-be2822559678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398503963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.398503963
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1791762422
Short name T259
Test name
Test status
Simulation time 1237757711 ps
CPU time 6.22 seconds
Started Jun 27 05:42:40 PM PDT 24
Finished Jun 27 05:42:50 PM PDT 24
Peak memory 200348 kb
Host smart-83cbe3dc-c235-4c61-a13b-4d83d026ba69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791762422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1791762422
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3550539600
Short name T138
Test name
Test status
Simulation time 542873932 ps
CPU time 2.83 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:49 PM PDT 24
Peak memory 199532 kb
Host smart-cc051515-3205-4d73-a865-97dcd6f569e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550539600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3550539600
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3002851063
Short name T226
Test name
Test status
Simulation time 78743749 ps
CPU time 0.78 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:46 PM PDT 24
Peak memory 200028 kb
Host smart-69dfe6e7-02f8-43f0-ae33-7f5e171efd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002851063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3002851063
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3226530490
Short name T211
Test name
Test status
Simulation time 56123344 ps
CPU time 0.71 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:47 PM PDT 24
Peak memory 199884 kb
Host smart-2674e18f-1d7d-4a97-b2a0-743e4288025f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226530490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3226530490
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2150223575
Short name T452
Test name
Test status
Simulation time 1236079026 ps
CPU time 5.74 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:51 PM PDT 24
Peak memory 217044 kb
Host smart-677bdded-744b-4803-ba28-ef1d809e9bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150223575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2150223575
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.988410332
Short name T284
Test name
Test status
Simulation time 243949810 ps
CPU time 1.17 seconds
Started Jun 27 05:42:38 PM PDT 24
Finished Jun 27 05:42:44 PM PDT 24
Peak memory 217428 kb
Host smart-fdcb5f59-da72-4328-9b93-b7240cbf5028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988410332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.988410332
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2624110371
Short name T15
Test name
Test status
Simulation time 123032241 ps
CPU time 0.79 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:46 PM PDT 24
Peak memory 199904 kb
Host smart-70c275bf-f68f-489b-ae15-988d2d1ec582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624110371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2624110371
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3262070794
Short name T252
Test name
Test status
Simulation time 934458129 ps
CPU time 4.68 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:50 PM PDT 24
Peak memory 200348 kb
Host smart-43053102-61f2-4b25-b6a7-4f84d1a7c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262070794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3262070794
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2958865519
Short name T170
Test name
Test status
Simulation time 168156497 ps
CPU time 1.16 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:47 PM PDT 24
Peak memory 199984 kb
Host smart-5db6b580-48a7-4c98-ba1a-bd4eca94a770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958865519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2958865519
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1516969948
Short name T420
Test name
Test status
Simulation time 205529319 ps
CPU time 1.33 seconds
Started Jun 27 05:42:47 PM PDT 24
Finished Jun 27 05:42:53 PM PDT 24
Peak memory 200192 kb
Host smart-1ed75a9e-69ee-48f6-a69c-6cfd7aa6d172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516969948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1516969948
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3180855006
Short name T519
Test name
Test status
Simulation time 2469679109 ps
CPU time 8.8 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:54 PM PDT 24
Peak memory 200452 kb
Host smart-f99898aa-4627-4ce6-b0b6-c72f34113c58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180855006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3180855006
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.255110594
Short name T193
Test name
Test status
Simulation time 429661206 ps
CPU time 2.3 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:49 PM PDT 24
Peak memory 208296 kb
Host smart-829c9ce1-517f-4d75-a4f2-786ca89dd045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255110594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.255110594
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.789541313
Short name T381
Test name
Test status
Simulation time 82153367 ps
CPU time 0.8 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:46 PM PDT 24
Peak memory 200096 kb
Host smart-2c759692-eb43-4726-b9c2-39d5f57c7647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789541313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.789541313
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3020212367
Short name T374
Test name
Test status
Simulation time 69165677 ps
CPU time 0.71 seconds
Started Jun 27 05:42:51 PM PDT 24
Finished Jun 27 05:42:54 PM PDT 24
Peak memory 199796 kb
Host smart-c82a66f8-ba41-46a0-94ff-e3393ad2c68d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020212367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3020212367
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3999435791
Short name T278
Test name
Test status
Simulation time 1882388175 ps
CPU time 7.02 seconds
Started Jun 27 05:42:38 PM PDT 24
Finished Jun 27 05:42:49 PM PDT 24
Peak memory 221700 kb
Host smart-cc048c8d-09a1-4d27-aa99-9a922bf8b235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999435791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3999435791
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.4260653079
Short name T147
Test name
Test status
Simulation time 243790980 ps
CPU time 1.13 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:46 PM PDT 24
Peak memory 217456 kb
Host smart-b7a1ac62-1cb1-4c2c-8b69-ebc2ad58026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260653079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.4260653079
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3268017890
Short name T20
Test name
Test status
Simulation time 99408398 ps
CPU time 0.75 seconds
Started Jun 27 05:42:40 PM PDT 24
Finished Jun 27 05:42:45 PM PDT 24
Peak memory 199908 kb
Host smart-a7ee2a0d-7125-44d0-9e68-c80b3078af1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268017890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3268017890
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3561731401
Short name T232
Test name
Test status
Simulation time 989127022 ps
CPU time 4.8 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:52 PM PDT 24
Peak memory 200344 kb
Host smart-8a17309e-a2dd-4b9c-8fdf-f2284ef8ab0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561731401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3561731401
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2266887885
Short name T422
Test name
Test status
Simulation time 168945485 ps
CPU time 1.21 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:47 PM PDT 24
Peak memory 200088 kb
Host smart-b90ae4f0-42fc-42e3-a231-a03f39551668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266887885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2266887885
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1157619495
Short name T136
Test name
Test status
Simulation time 252988975 ps
CPU time 1.47 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:49 PM PDT 24
Peak memory 200288 kb
Host smart-25bf35cb-fd87-4c17-9bc7-531829ce028f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157619495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1157619495
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1012651577
Short name T286
Test name
Test status
Simulation time 1994843768 ps
CPU time 9.68 seconds
Started Jun 27 05:42:38 PM PDT 24
Finished Jun 27 05:42:52 PM PDT 24
Peak memory 200320 kb
Host smart-c0d73e81-ba50-4053-95d3-fdfccbae61cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012651577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1012651577
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2262042453
Short name T326
Test name
Test status
Simulation time 265200587 ps
CPU time 1.79 seconds
Started Jun 27 05:42:39 PM PDT 24
Finished Jun 27 05:42:45 PM PDT 24
Peak memory 200088 kb
Host smart-3a42cfd3-0cf7-4271-bf41-ee2659d22773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262042453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2262042453
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2058967759
Short name T187
Test name
Test status
Simulation time 165831174 ps
CPU time 1.32 seconds
Started Jun 27 05:42:46 PM PDT 24
Finished Jun 27 05:42:52 PM PDT 24
Peak memory 200212 kb
Host smart-d7e88ce3-bdeb-4f2c-a958-b5d7dbc629b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058967759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2058967759
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1654884488
Short name T343
Test name
Test status
Simulation time 63277141 ps
CPU time 0.72 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:47 PM PDT 24
Peak memory 199880 kb
Host smart-ed10b056-187b-44d3-9326-8191cfc25e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654884488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1654884488
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2084652753
Short name T449
Test name
Test status
Simulation time 2342167028 ps
CPU time 8.57 seconds
Started Jun 27 05:42:47 PM PDT 24
Finished Jun 27 05:43:00 PM PDT 24
Peak memory 217724 kb
Host smart-e58cc14e-2807-461e-9f31-a7f8dc04a2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084652753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2084652753
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3144448708
Short name T370
Test name
Test status
Simulation time 244620489 ps
CPU time 1.04 seconds
Started Jun 27 05:42:36 PM PDT 24
Finished Jun 27 05:42:41 PM PDT 24
Peak memory 217404 kb
Host smart-21c91689-2cf9-4259-8b06-b2aebde62b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144448708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3144448708
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2616344474
Short name T483
Test name
Test status
Simulation time 237695081 ps
CPU time 0.95 seconds
Started Jun 27 05:42:35 PM PDT 24
Finished Jun 27 05:42:40 PM PDT 24
Peak memory 199892 kb
Host smart-263a79a7-8b37-461b-a3a2-0995d75d3589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616344474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2616344474
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.384755870
Short name T437
Test name
Test status
Simulation time 1391118698 ps
CPU time 5.81 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:52 PM PDT 24
Peak memory 200036 kb
Host smart-851f773b-79a5-4352-861f-7908d52b553b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384755870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.384755870
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1532120469
Short name T185
Test name
Test status
Simulation time 145820431 ps
CPU time 1.08 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:47 PM PDT 24
Peak memory 200088 kb
Host smart-c7bf3452-70e4-47a1-b878-e964a0782d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532120469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1532120469
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4189908720
Short name T305
Test name
Test status
Simulation time 244446708 ps
CPU time 1.44 seconds
Started Jun 27 05:42:50 PM PDT 24
Finished Jun 27 05:42:54 PM PDT 24
Peak memory 200192 kb
Host smart-61d46aeb-b3f5-437c-9683-f3cf4ef9867f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189908720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4189908720
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.402729836
Short name T79
Test name
Test status
Simulation time 316820752 ps
CPU time 1.85 seconds
Started Jun 27 05:42:46 PM PDT 24
Finished Jun 27 05:42:53 PM PDT 24
Peak memory 200192 kb
Host smart-3db7e464-736a-4ed0-9087-416c522cb48b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402729836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.402729836
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2401557985
Short name T84
Test name
Test status
Simulation time 389874656 ps
CPU time 2.63 seconds
Started Jun 27 05:42:37 PM PDT 24
Finished Jun 27 05:42:44 PM PDT 24
Peak memory 200056 kb
Host smart-f343cf27-7209-4551-9a58-e6690b019e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401557985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2401557985
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2425390159
Short name T508
Test name
Test status
Simulation time 200191059 ps
CPU time 1.26 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:49 PM PDT 24
Peak memory 200108 kb
Host smart-dd794d37-06af-4589-a362-d9049303c5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425390159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2425390159
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1615279527
Short name T165
Test name
Test status
Simulation time 56161250 ps
CPU time 0.75 seconds
Started Jun 27 05:42:47 PM PDT 24
Finished Jun 27 05:42:52 PM PDT 24
Peak memory 199796 kb
Host smart-74824375-cfe1-4aa8-9633-61e86696e1da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615279527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1615279527
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3645330613
Short name T327
Test name
Test status
Simulation time 1216091310 ps
CPU time 5.43 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:51 PM PDT 24
Peak memory 217552 kb
Host smart-6649a959-1b2f-40b9-a92b-a482a08eeba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645330613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3645330613
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1311092065
Short name T432
Test name
Test status
Simulation time 243827263 ps
CPU time 1.09 seconds
Started Jun 27 05:42:43 PM PDT 24
Finished Jun 27 05:42:49 PM PDT 24
Peak memory 217456 kb
Host smart-7ddca028-5f62-4244-845d-68ec36af673e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311092065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1311092065
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1978359297
Short name T16
Test name
Test status
Simulation time 122897740 ps
CPU time 0.81 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:47 PM PDT 24
Peak memory 199904 kb
Host smart-758a7f42-f7a9-4bba-9ff0-ff6f19675641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978359297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1978359297
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1493108275
Short name T364
Test name
Test status
Simulation time 1572123205 ps
CPU time 6.23 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:53 PM PDT 24
Peak memory 200356 kb
Host smart-b5dc8b15-21f1-487b-9c01-200434c5b20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493108275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1493108275
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.218108942
Short name T406
Test name
Test status
Simulation time 106022386 ps
CPU time 1.05 seconds
Started Jun 27 05:42:36 PM PDT 24
Finished Jun 27 05:42:41 PM PDT 24
Peak memory 200092 kb
Host smart-675670a1-b21f-4453-9739-37c06e37190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218108942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.218108942
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2265077340
Short name T265
Test name
Test status
Simulation time 187653257 ps
CPU time 1.44 seconds
Started Jun 27 05:42:35 PM PDT 24
Finished Jun 27 05:42:41 PM PDT 24
Peak memory 200280 kb
Host smart-1e1bf546-a509-46b0-9cc3-073e8c7e40d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265077340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2265077340
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3837612853
Short name T135
Test name
Test status
Simulation time 220748521 ps
CPU time 1.46 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:48 PM PDT 24
Peak memory 199500 kb
Host smart-6b4625de-c2da-4da3-99fe-90ae69d1462d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837612853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3837612853
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2474365531
Short name T267
Test name
Test status
Simulation time 128115082 ps
CPU time 1.52 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:47 PM PDT 24
Peak memory 200128 kb
Host smart-07be3e8a-11e9-4e24-973d-d25e8d0cbe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474365531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2474365531
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1083205305
Short name T197
Test name
Test status
Simulation time 216611673 ps
CPU time 1.3 seconds
Started Jun 27 05:42:33 PM PDT 24
Finished Jun 27 05:42:40 PM PDT 24
Peak memory 200068 kb
Host smart-2ab62356-999a-4502-a57f-fe7ff09fcac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083205305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1083205305
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.4067254560
Short name T196
Test name
Test status
Simulation time 70482625 ps
CPU time 0.75 seconds
Started Jun 27 05:42:47 PM PDT 24
Finished Jun 27 05:42:52 PM PDT 24
Peak memory 199796 kb
Host smart-da833550-9982-44c1-8fff-8ed0836c2cbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067254560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4067254560
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3622210892
Short name T9
Test name
Test status
Simulation time 1882831386 ps
CPU time 6.91 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:53 PM PDT 24
Peak memory 217544 kb
Host smart-b155c137-8a13-4d8a-82cd-09562af92056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622210892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3622210892
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2796593478
Short name T322
Test name
Test status
Simulation time 244493332 ps
CPU time 1.12 seconds
Started Jun 27 05:42:38 PM PDT 24
Finished Jun 27 05:42:43 PM PDT 24
Peak memory 217428 kb
Host smart-e91c0e72-dc34-470c-bb99-6b2b5d033bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796593478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2796593478
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2386122866
Short name T410
Test name
Test status
Simulation time 182164582 ps
CPU time 0.83 seconds
Started Jun 27 05:42:35 PM PDT 24
Finished Jun 27 05:42:40 PM PDT 24
Peak memory 199852 kb
Host smart-54e505b4-92fb-418e-b970-0720f53f4eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386122866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2386122866
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.768623491
Short name T424
Test name
Test status
Simulation time 1509495284 ps
CPU time 6.02 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:52 PM PDT 24
Peak memory 199828 kb
Host smart-ac7df41c-e226-4af9-9959-457773592657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768623491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.768623491
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1741101061
Short name T143
Test name
Test status
Simulation time 167666893 ps
CPU time 1.2 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:48 PM PDT 24
Peak memory 200088 kb
Host smart-1ad83162-2418-4068-b2d6-323f83a9170d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741101061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1741101061
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.201099197
Short name T67
Test name
Test status
Simulation time 118539434 ps
CPU time 1.21 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:47 PM PDT 24
Peak memory 200276 kb
Host smart-48f3c352-262b-484c-a921-d38594be389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201099197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.201099197
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2271757213
Short name T294
Test name
Test status
Simulation time 10277405135 ps
CPU time 32.75 seconds
Started Jun 27 05:42:51 PM PDT 24
Finished Jun 27 05:43:26 PM PDT 24
Peak memory 200320 kb
Host smart-972e77ad-e4df-478c-84ca-2cd7ac2330e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271757213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2271757213
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1702551586
Short name T233
Test name
Test status
Simulation time 138483257 ps
CPU time 1.64 seconds
Started Jun 27 05:42:41 PM PDT 24
Finished Jun 27 05:42:47 PM PDT 24
Peak memory 200080 kb
Host smart-984f0e7d-fbc9-4ced-98e2-1a98bb348978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702551586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1702551586
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1409101664
Short name T416
Test name
Test status
Simulation time 86162822 ps
CPU time 0.88 seconds
Started Jun 27 05:42:42 PM PDT 24
Finished Jun 27 05:42:47 PM PDT 24
Peak memory 199972 kb
Host smart-a454d2d4-7a67-4a3a-8b88-304df299481c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409101664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1409101664
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1706925383
Short name T347
Test name
Test status
Simulation time 90022185 ps
CPU time 0.81 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:40:54 PM PDT 24
Peak memory 199844 kb
Host smart-f3de7ae2-0b1e-4541-b3d2-1de442d412aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706925383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1706925383
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3707063186
Short name T280
Test name
Test status
Simulation time 2179763951 ps
CPU time 8.73 seconds
Started Jun 27 05:40:47 PM PDT 24
Finished Jun 27 05:40:57 PM PDT 24
Peak memory 217796 kb
Host smart-013bff3b-61e6-4679-bb7b-f58fe94befb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707063186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3707063186
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1917605412
Short name T330
Test name
Test status
Simulation time 245107749 ps
CPU time 1.07 seconds
Started Jun 27 05:40:49 PM PDT 24
Finished Jun 27 05:40:51 PM PDT 24
Peak memory 217400 kb
Host smart-5f89fbdb-c6a0-43d9-81a3-621be2a83f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917605412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1917605412
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.253222849
Short name T472
Test name
Test status
Simulation time 157995270 ps
CPU time 0.83 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:55 PM PDT 24
Peak memory 199800 kb
Host smart-9938ee7a-9601-4aeb-a3d8-7e6352065448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253222849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.253222849
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1798605095
Short name T517
Test name
Test status
Simulation time 927665231 ps
CPU time 4.83 seconds
Started Jun 27 05:45:07 PM PDT 24
Finished Jun 27 05:45:36 PM PDT 24
Peak memory 200416 kb
Host smart-f8331ecf-4c81-4132-bf5d-780b6aea6bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798605095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1798605095
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2327456905
Short name T168
Test name
Test status
Simulation time 159774974 ps
CPU time 1.19 seconds
Started Jun 27 05:40:52 PM PDT 24
Finished Jun 27 05:40:56 PM PDT 24
Peak memory 200068 kb
Host smart-06d9465e-7aa6-462d-ae5a-dae88a84c968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327456905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2327456905
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.147094170
Short name T251
Test name
Test status
Simulation time 194528007 ps
CPU time 1.59 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:40:54 PM PDT 24
Peak memory 200284 kb
Host smart-aba901c9-2680-4850-9def-25047a064c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147094170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.147094170
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.4100879841
Short name T412
Test name
Test status
Simulation time 8111267764 ps
CPU time 31.88 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:41:24 PM PDT 24
Peak memory 208608 kb
Host smart-86bb8755-80a4-4d9f-ac5d-553a6c3945c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100879841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.4100879841
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1210177859
Short name T298
Test name
Test status
Simulation time 542527798 ps
CPU time 2.74 seconds
Started Jun 27 05:40:54 PM PDT 24
Finished Jun 27 05:40:59 PM PDT 24
Peak memory 199908 kb
Host smart-fe9a8d76-15d3-4c23-9dc8-9c4f20d12878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210177859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1210177859
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3735841702
Short name T521
Test name
Test status
Simulation time 134897558 ps
CPU time 1.18 seconds
Started Jun 27 05:40:48 PM PDT 24
Finished Jun 27 05:40:51 PM PDT 24
Peak memory 200024 kb
Host smart-e6fdc66d-fc6e-4bdc-8244-e330a5f35b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735841702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3735841702
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2026272520
Short name T335
Test name
Test status
Simulation time 84747185 ps
CPU time 0.87 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:40:53 PM PDT 24
Peak memory 199868 kb
Host smart-d152c4de-a9db-4b65-8336-f9031936f00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026272520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2026272520
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1209813356
Short name T358
Test name
Test status
Simulation time 1218955070 ps
CPU time 5.45 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:40:59 PM PDT 24
Peak memory 221560 kb
Host smart-bd6e6577-e9b0-4d2b-99aa-7f91d98fbffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209813356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1209813356
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1071027401
Short name T414
Test name
Test status
Simulation time 248608036 ps
CPU time 1.01 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:55 PM PDT 24
Peak memory 217444 kb
Host smart-c9e06875-bda0-4458-a480-135854a395bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071027401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1071027401
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3862613973
Short name T340
Test name
Test status
Simulation time 210568469 ps
CPU time 0.95 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:40:54 PM PDT 24
Peak memory 200088 kb
Host smart-73011788-2bd6-4d02-8e9f-8d184c6b787e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862613973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3862613973
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1484324028
Short name T238
Test name
Test status
Simulation time 1294830059 ps
CPU time 5.44 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:59 PM PDT 24
Peak memory 200228 kb
Host smart-a5e092a5-ba8d-42f3-98da-6347d4babb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484324028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1484324028
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.9928142
Short name T71
Test name
Test status
Simulation time 102858913 ps
CPU time 1.01 seconds
Started Jun 27 05:40:52 PM PDT 24
Finished Jun 27 05:40:56 PM PDT 24
Peak memory 199180 kb
Host smart-33bbe760-b355-4ca5-a4dd-cf524adf04cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9928142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.9928142
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3164182619
Short name T134
Test name
Test status
Simulation time 235319678 ps
CPU time 1.52 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:40:56 PM PDT 24
Peak memory 200280 kb
Host smart-a58ce245-03da-4cb9-bd90-24536006a0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164182619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3164182619
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1412749437
Short name T95
Test name
Test status
Simulation time 3524133663 ps
CPU time 15.9 seconds
Started Jun 27 05:40:51 PM PDT 24
Finished Jun 27 05:41:10 PM PDT 24
Peak memory 210204 kb
Host smart-a3d663a2-c58b-4b00-b37c-4da7cedb6ac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412749437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1412749437
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1983029188
Short name T486
Test name
Test status
Simulation time 357691862 ps
CPU time 2.21 seconds
Started Jun 27 05:40:52 PM PDT 24
Finished Jun 27 05:40:57 PM PDT 24
Peak memory 199300 kb
Host smart-772a0f4b-aec0-4c95-b874-7ccb33179bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983029188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1983029188
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.491133527
Short name T470
Test name
Test status
Simulation time 87320310 ps
CPU time 0.88 seconds
Started Jun 27 05:40:52 PM PDT 24
Finished Jun 27 05:40:56 PM PDT 24
Peak memory 199992 kb
Host smart-2e57b80f-4fe5-4ed3-aaa3-df81cc87021b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491133527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.491133527
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1287340426
Short name T149
Test name
Test status
Simulation time 68737665 ps
CPU time 0.77 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 199828 kb
Host smart-7d4a2c1a-3043-4a4d-9618-b5f21ad38eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287340426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1287340426
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1432531676
Short name T430
Test name
Test status
Simulation time 244411200 ps
CPU time 1.08 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 217396 kb
Host smart-c3252060-d6d3-487b-87be-22cc33f9607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432531676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1432531676
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3991787840
Short name T431
Test name
Test status
Simulation time 118859083 ps
CPU time 0.85 seconds
Started Jun 27 05:40:53 PM PDT 24
Finished Jun 27 05:40:57 PM PDT 24
Peak memory 200068 kb
Host smart-9bb23bfe-8751-4e6e-aae3-b7d0e83d928b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991787840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3991787840
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3700759211
Short name T545
Test name
Test status
Simulation time 1565910107 ps
CPU time 6.41 seconds
Started Jun 27 05:41:06 PM PDT 24
Finished Jun 27 05:41:13 PM PDT 24
Peak memory 200344 kb
Host smart-d48cedc6-bfbc-4aa2-b22b-eb263b95f2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700759211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3700759211
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3899731159
Short name T229
Test name
Test status
Simulation time 103236545 ps
CPU time 1.05 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 200292 kb
Host smart-ad790336-3ca7-4af1-bd4d-93e3461dbdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899731159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3899731159
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3409558309
Short name T157
Test name
Test status
Simulation time 196700542 ps
CPU time 1.39 seconds
Started Jun 27 05:40:50 PM PDT 24
Finished Jun 27 05:40:55 PM PDT 24
Peak memory 200252 kb
Host smart-53c3db2f-fbfc-4d39-bf6a-6ee1e67925ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409558309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3409558309
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1782752464
Short name T450
Test name
Test status
Simulation time 4802532300 ps
CPU time 24.45 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:40 PM PDT 24
Peak memory 200360 kb
Host smart-6ca5799e-3447-4f41-a6bc-0f19e9a46d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782752464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1782752464
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2989574719
Short name T262
Test name
Test status
Simulation time 276203791 ps
CPU time 1.98 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 200084 kb
Host smart-abdbaabf-a486-49ef-8920-0d72e4799567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989574719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2989574719
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1393628697
Short name T82
Test name
Test status
Simulation time 144813933 ps
CPU time 1.16 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 200096 kb
Host smart-e5d86ecd-9746-45c4-9844-0e0014404c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393628697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1393628697
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3099990850
Short name T188
Test name
Test status
Simulation time 75950610 ps
CPU time 0.78 seconds
Started Jun 27 05:41:07 PM PDT 24
Finished Jun 27 05:41:09 PM PDT 24
Peak memory 199860 kb
Host smart-fdaeadc8-9da3-4f3c-80e2-16208dc31bc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099990850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3099990850
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.4102960009
Short name T514
Test name
Test status
Simulation time 2360173862 ps
CPU time 8.61 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:25 PM PDT 24
Peak memory 221692 kb
Host smart-daefd6c8-5182-4c8b-b692-3e2ff86d1272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102960009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4102960009
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3678627114
Short name T228
Test name
Test status
Simulation time 244159681 ps
CPU time 1.11 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 217468 kb
Host smart-80805e7b-2b57-47d4-ad41-e20b5cb66de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678627114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3678627114
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2233148430
Short name T289
Test name
Test status
Simulation time 127943116 ps
CPU time 0.82 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 199848 kb
Host smart-7c775f07-e546-4501-9a9e-aab91fd7d686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233148430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2233148430
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.49000535
Short name T446
Test name
Test status
Simulation time 835418368 ps
CPU time 4.64 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:18 PM PDT 24
Peak memory 200344 kb
Host smart-7335281a-a1ce-448e-bbc8-901932c49a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49000535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.49000535
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4058546271
Short name T212
Test name
Test status
Simulation time 139166678 ps
CPU time 1.2 seconds
Started Jun 27 05:41:08 PM PDT 24
Finished Jun 27 05:41:11 PM PDT 24
Peak memory 200068 kb
Host smart-d87bfd09-b511-4224-b86d-aff002a5cdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058546271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4058546271
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1930328498
Short name T489
Test name
Test status
Simulation time 247115684 ps
CPU time 1.53 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 200296 kb
Host smart-7524db25-1e3d-46c1-bee1-c0612ac75f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930328498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1930328498
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2619715546
Short name T214
Test name
Test status
Simulation time 663119456 ps
CPU time 3.38 seconds
Started Jun 27 05:41:08 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 200212 kb
Host smart-216aae19-e2d4-4ab0-bec7-d004d02bc17a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619715546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2619715546
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.985710503
Short name T291
Test name
Test status
Simulation time 422245247 ps
CPU time 2.42 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 208260 kb
Host smart-d7cf6954-0d8d-4d98-9386-d99c9003e1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985710503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.985710503
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1656826819
Short name T195
Test name
Test status
Simulation time 128236071 ps
CPU time 1.17 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 200052 kb
Host smart-59ac0d16-dfb9-4028-ba87-5c469dd8d5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656826819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1656826819
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3548675951
Short name T179
Test name
Test status
Simulation time 74487102 ps
CPU time 0.81 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 199868 kb
Host smart-061218f6-034f-4d3d-8ce2-66894b8b5359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548675951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3548675951
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.237551348
Short name T32
Test name
Test status
Simulation time 1890798267 ps
CPU time 8.27 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:22 PM PDT 24
Peak memory 217596 kb
Host smart-cbc607bc-fa3a-4cc7-aa02-ae74ed32208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237551348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.237551348
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2591339100
Short name T271
Test name
Test status
Simulation time 244534858 ps
CPU time 1.03 seconds
Started Jun 27 05:41:08 PM PDT 24
Finished Jun 27 05:41:10 PM PDT 24
Peak memory 217424 kb
Host smart-45681721-7ba2-46b0-8c3d-4732ccc40dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591339100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2591339100
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3444666906
Short name T227
Test name
Test status
Simulation time 107825610 ps
CPU time 0.78 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:16 PM PDT 24
Peak memory 199852 kb
Host smart-8d639c8f-5dcc-4fa8-bb9e-37a698ad2dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444666906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3444666906
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2115068016
Short name T490
Test name
Test status
Simulation time 2112085841 ps
CPU time 7.24 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:23 PM PDT 24
Peak memory 200236 kb
Host smart-afcc5e1d-a96b-47b7-a596-427de4a990a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115068016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2115068016
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2439548369
Short name T524
Test name
Test status
Simulation time 97165806 ps
CPU time 1 seconds
Started Jun 27 05:41:10 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 200040 kb
Host smart-74441286-09f6-423b-a59c-cfb3280b02af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439548369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2439548369
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1551716006
Short name T83
Test name
Test status
Simulation time 258908488 ps
CPU time 1.63 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 200224 kb
Host smart-60005f24-4ccf-47df-b561-70f4751ae9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551716006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1551716006
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.73015774
Short name T363
Test name
Test status
Simulation time 6121922882 ps
CPU time 26 seconds
Started Jun 27 05:41:11 PM PDT 24
Finished Jun 27 05:41:42 PM PDT 24
Peak memory 200368 kb
Host smart-9af35cea-701d-4db3-b592-7078421a2606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73015774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.73015774
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1689051270
Short name T194
Test name
Test status
Simulation time 146246539 ps
CPU time 1.74 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:13 PM PDT 24
Peak memory 208180 kb
Host smart-27d6276f-947e-4e47-9b8b-e3b3a3bfd56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689051270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1689051270
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2365876563
Short name T208
Test name
Test status
Simulation time 85748492 ps
CPU time 0.85 seconds
Started Jun 27 05:41:09 PM PDT 24
Finished Jun 27 05:41:14 PM PDT 24
Peak memory 200084 kb
Host smart-1b7c7e97-b92b-40cb-af96-e27142452527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365876563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2365876563
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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