Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7853

1

T1

23

T3

24

T5

18

auto[1]

10738

1

T1

23

T3

19

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5851	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6234	1			T1	21		T2	1		T3	15
reset_info_cp[2]	2817	1			T1	6		T3	10		T4	1
reset_info_cp[4]	3741	1			T1	6		T3	10		T4	1
reset_info_cp[8]	98	1			T9	1		T11	1		T22	1
reset_info_cp[16]	113	1			T1	1		T29	1		T74	1
reset_info_cp[32]	119	1			T5	2		T9	1		T10	1
reset_info_cp[64]	114	1			T10	2		T29	1		T77	3
reset_info_cp[128]	124	1			T5	1		T9	1		T10	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2949	1			T1	7		T3	3		T5	18
reset_info_cp[1]	auto[1]	2665	1			T1	13		T3	11		T4	1
reset_info_cp[2]	auto[0]	844	1			T1	3		T3	7		T74	3
reset_info_cp[2]	auto[1]	1973	1			T1	3		T3	3		T4	1
reset_info_cp[4]	auto[0]	1347	1			T1	3		T3	9		T74	8
reset_info_cp[4]	auto[1]	2394	1			T1	3		T3	1		T4	1
reset_info_cp[8]	auto[0]	49	1			T78	1		T82	2		T87	1
reset_info_cp[8]	auto[1]	49	1			T9	1		T11	1		T22	1
reset_info_cp[16]	auto[0]	52	1			T1	1		T74	1		T77	1
reset_info_cp[16]	auto[1]	61	1			T29	1		T82	4		T33	1
reset_info_cp[32]	auto[0]	53	1			T77	1		T79	1		T78	1
reset_info_cp[32]	auto[1]	66	1			T5	2		T9	1		T10	1
reset_info_cp[64]	auto[0]	40	1			T77	3		T82	1		T106	1
reset_info_cp[64]	auto[1]	74	1			T10	2		T29	1		T114	1
reset_info_cp[128]	auto[0]	48	1			T83	1		T149	1		T150	2
reset_info_cp[128]	auto[1]	76	1			T5	1		T9	1		T10	1