Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T537 /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2360424096 Jun 28 05:59:17 PM PDT 24 Jun 28 05:59:46 PM PDT 24 2343803005 ps
T538 /workspace/coverage/default/47.rstmgr_sw_rst.520994043 Jun 28 06:00:00 PM PDT 24 Jun 28 06:00:07 PM PDT 24 360581864 ps
T539 /workspace/coverage/default/28.rstmgr_stress_all.759504837 Jun 28 05:59:09 PM PDT 24 Jun 28 05:59:33 PM PDT 24 2742925087 ps
T540 /workspace/coverage/default/41.rstmgr_alert_test.1226936924 Jun 28 05:59:38 PM PDT 24 Jun 28 05:59:48 PM PDT 24 66109670 ps
T541 /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2055619976 Jun 28 05:59:10 PM PDT 24 Jun 28 05:59:27 PM PDT 24 244703875 ps
T48 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.680715420 Jun 28 05:57:07 PM PDT 24 Jun 28 05:57:10 PM PDT 24 144244520 ps
T54 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3928142687 Jun 28 05:57:00 PM PDT 24 Jun 28 05:57:06 PM PDT 24 176693864 ps
T55 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3643309458 Jun 28 05:57:09 PM PDT 24 Jun 28 05:57:14 PM PDT 24 230028586 ps
T49 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3196198948 Jun 28 05:56:48 PM PDT 24 Jun 28 05:56:53 PM PDT 24 506918672 ps
T50 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2046465779 Jun 28 05:56:59 PM PDT 24 Jun 28 05:57:02 PM PDT 24 243737372 ps
T51 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.785309960 Jun 28 05:57:01 PM PDT 24 Jun 28 05:57:04 PM PDT 24 120400872 ps
T62 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.682588349 Jun 28 05:56:59 PM PDT 24 Jun 28 05:57:01 PM PDT 24 200286687 ps
T56 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3803768367 Jun 28 05:57:00 PM PDT 24 Jun 28 05:57:05 PM PDT 24 492945862 ps
T542 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1477863194 Jun 28 05:56:59 PM PDT 24 Jun 28 05:57:01 PM PDT 24 99947491 ps
T92 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3646735568 Jun 28 05:57:17 PM PDT 24 Jun 28 05:57:21 PM PDT 24 522169129 ps
T93 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4094206190 Jun 28 05:56:59 PM PDT 24 Jun 28 05:57:03 PM PDT 24 779954566 ps
T97 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2824227584 Jun 28 05:57:16 PM PDT 24 Jun 28 05:57:19 PM PDT 24 418733586 ps
T543 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3407065410 Jun 28 05:56:57 PM PDT 24 Jun 28 05:57:00 PM PDT 24 100898282 ps
T118 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3667219756 Jun 28 05:57:08 PM PDT 24 Jun 28 05:57:12 PM PDT 24 158988317 ps
T119 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4050096384 Jun 28 05:57:11 PM PDT 24 Jun 28 05:57:15 PM PDT 24 137313848 ps
T94 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1359710891 Jun 28 05:57:08 PM PDT 24 Jun 28 05:57:15 PM PDT 24 445917731 ps
T120 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1037201562 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:14 PM PDT 24 66119891 ps
T544 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3626946589 Jun 28 05:56:58 PM PDT 24 Jun 28 05:57:01 PM PDT 24 146944430 ps
T121 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3408314731 Jun 28 05:57:08 PM PDT 24 Jun 28 05:57:13 PM PDT 24 110816379 ps
T95 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3060338782 Jun 28 05:56:47 PM PDT 24 Jun 28 05:56:52 PM PDT 24 920005367 ps
T102 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1963395951 Jun 28 05:57:09 PM PDT 24 Jun 28 05:57:15 PM PDT 24 424692655 ps
T122 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1272781013 Jun 28 05:56:46 PM PDT 24 Jun 28 05:56:49 PM PDT 24 122526451 ps
T96 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.163755481 Jun 28 05:57:09 PM PDT 24 Jun 28 05:57:14 PM PDT 24 138490540 ps
T98 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.877871837 Jun 28 05:57:08 PM PDT 24 Jun 28 05:57:15 PM PDT 24 895241418 ps
T99 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1644735937 Jun 28 05:57:17 PM PDT 24 Jun 28 05:57:20 PM PDT 24 124689548 ps
T545 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3331820651 Jun 28 05:57:00 PM PDT 24 Jun 28 05:57:12 PM PDT 24 2293877671 ps
T100 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.375404932 Jun 28 05:57:23 PM PDT 24 Jun 28 05:57:25 PM PDT 24 188861576 ps
T546 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.522363234 Jun 28 05:57:18 PM PDT 24 Jun 28 05:57:20 PM PDT 24 84898425 ps
T101 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3447177167 Jun 28 05:57:01 PM PDT 24 Jun 28 05:57:07 PM PDT 24 400031686 ps
T547 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2101235890 Jun 28 05:57:12 PM PDT 24 Jun 28 05:57:16 PM PDT 24 66362905 ps
T548 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3194550175 Jun 28 05:57:00 PM PDT 24 Jun 28 05:57:05 PM PDT 24 405826767 ps
T134 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.928579923 Jun 28 05:57:08 PM PDT 24 Jun 28 05:57:13 PM PDT 24 176121323 ps
T123 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.891262988 Jun 28 05:57:08 PM PDT 24 Jun 28 05:57:11 PM PDT 24 75908468 ps
T124 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1090402248 Jun 28 05:57:17 PM PDT 24 Jun 28 05:57:20 PM PDT 24 276316342 ps
T133 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3949087433 Jun 28 05:57:22 PM PDT 24 Jun 28 05:57:27 PM PDT 24 535949685 ps
T125 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.461904091 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:14 PM PDT 24 83995788 ps
T126 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.240948805 Jun 28 05:57:00 PM PDT 24 Jun 28 05:57:04 PM PDT 24 278319647 ps
T549 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1868787728 Jun 28 05:57:07 PM PDT 24 Jun 28 05:57:10 PM PDT 24 106622963 ps
T550 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2792483979 Jun 28 05:57:16 PM PDT 24 Jun 28 05:57:19 PM PDT 24 144030450 ps
T551 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2621235136 Jun 28 05:56:58 PM PDT 24 Jun 28 05:57:01 PM PDT 24 106981863 ps
T552 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1694853139 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:15 PM PDT 24 83785537 ps
T553 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2124108427 Jun 28 05:57:07 PM PDT 24 Jun 28 05:57:12 PM PDT 24 442692595 ps
T147 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.287755981 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:15 PM PDT 24 477163951 ps
T554 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3475668628 Jun 28 05:57:17 PM PDT 24 Jun 28 05:57:20 PM PDT 24 190773031 ps
T555 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.595710219 Jun 28 05:56:59 PM PDT 24 Jun 28 05:57:02 PM PDT 24 201491851 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4289708488 Jun 28 05:57:00 PM PDT 24 Jun 28 05:57:04 PM PDT 24 66279501 ps
T557 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3544248262 Jun 28 05:57:08 PM PDT 24 Jun 28 05:57:15 PM PDT 24 516067438 ps
T128 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2849827844 Jun 28 05:57:16 PM PDT 24 Jun 28 05:57:21 PM PDT 24 932457229 ps
T558 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.422357557 Jun 28 05:56:47 PM PDT 24 Jun 28 05:56:51 PM PDT 24 137036115 ps
T131 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3160810140 Jun 28 05:56:59 PM PDT 24 Jun 28 05:57:03 PM PDT 24 770574971 ps
T559 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1743613714 Jun 28 05:57:12 PM PDT 24 Jun 28 05:57:17 PM PDT 24 207107306 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1584689471 Jun 28 05:57:00 PM PDT 24 Jun 28 05:57:04 PM PDT 24 136567405 ps
T561 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.670554808 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:15 PM PDT 24 232860673 ps
T562 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2788371202 Jun 28 05:57:18 PM PDT 24 Jun 28 05:57:21 PM PDT 24 119118006 ps
T130 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1345529635 Jun 28 05:57:09 PM PDT 24 Jun 28 05:57:17 PM PDT 24 1092423157 ps
T563 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.692950995 Jun 28 05:56:58 PM PDT 24 Jun 28 05:57:01 PM PDT 24 119288194 ps
T129 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2043065728 Jun 28 05:57:12 PM PDT 24 Jun 28 05:57:19 PM PDT 24 947085596 ps
T564 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3229892299 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:14 PM PDT 24 195163845 ps
T565 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3629429364 Jun 28 05:57:08 PM PDT 24 Jun 28 05:57:11 PM PDT 24 79191117 ps
T566 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3299041458 Jun 28 05:57:06 PM PDT 24 Jun 28 05:57:09 PM PDT 24 77610291 ps
T567 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.266082389 Jun 28 05:57:09 PM PDT 24 Jun 28 05:57:13 PM PDT 24 125897453 ps
T568 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4029545792 Jun 28 05:57:07 PM PDT 24 Jun 28 05:57:11 PM PDT 24 232655508 ps
T569 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4121048585 Jun 28 05:57:18 PM PDT 24 Jun 28 05:57:21 PM PDT 24 242666030 ps
T570 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2496053750 Jun 28 05:57:18 PM PDT 24 Jun 28 05:57:21 PM PDT 24 185784231 ps
T571 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3572392210 Jun 28 05:57:05 PM PDT 24 Jun 28 05:57:09 PM PDT 24 195915953 ps
T572 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3724667376 Jun 28 05:57:12 PM PDT 24 Jun 28 05:57:18 PM PDT 24 315615151 ps
T573 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2818541712 Jun 28 05:57:08 PM PDT 24 Jun 28 05:57:12 PM PDT 24 147319682 ps
T574 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2077839944 Jun 28 05:57:17 PM PDT 24 Jun 28 05:57:22 PM PDT 24 888659861 ps
T575 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.325853309 Jun 28 05:57:18 PM PDT 24 Jun 28 05:57:22 PM PDT 24 273121926 ps
T576 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2961159525 Jun 28 05:57:00 PM PDT 24 Jun 28 05:57:03 PM PDT 24 123624619 ps
T577 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2163977247 Jun 28 05:56:47 PM PDT 24 Jun 28 05:56:55 PM PDT 24 485070700 ps
T578 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2949383443 Jun 28 05:57:01 PM PDT 24 Jun 28 05:57:10 PM PDT 24 485655175 ps
T579 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.41149922 Jun 28 05:57:17 PM PDT 24 Jun 28 05:57:19 PM PDT 24 80123424 ps
T580 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2106341469 Jun 28 05:57:18 PM PDT 24 Jun 28 05:57:21 PM PDT 24 70986403 ps
T581 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2093823939 Jun 28 05:56:58 PM PDT 24 Jun 28 05:57:01 PM PDT 24 120956072 ps
T582 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4257876157 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:15 PM PDT 24 120947557 ps
T583 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4289039706 Jun 28 05:57:13 PM PDT 24 Jun 28 05:57:17 PM PDT 24 81160603 ps
T584 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2270289783 Jun 28 05:56:57 PM PDT 24 Jun 28 05:56:59 PM PDT 24 64820475 ps
T585 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1780375461 Jun 28 05:57:16 PM PDT 24 Jun 28 05:57:22 PM PDT 24 1467214709 ps
T586 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2595681718 Jun 28 05:56:49 PM PDT 24 Jun 28 05:56:53 PM PDT 24 87621630 ps
T587 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.903889327 Jun 28 05:56:58 PM PDT 24 Jun 28 05:57:08 PM PDT 24 1552216312 ps
T588 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2411161565 Jun 28 05:57:07 PM PDT 24 Jun 28 05:57:11 PM PDT 24 117912051 ps
T589 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.259572447 Jun 28 05:57:12 PM PDT 24 Jun 28 05:57:17 PM PDT 24 407411993 ps
T590 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3914719327 Jun 28 05:57:15 PM PDT 24 Jun 28 05:57:18 PM PDT 24 63524258 ps
T591 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4105629935 Jun 28 05:56:58 PM PDT 24 Jun 28 05:57:00 PM PDT 24 112942546 ps
T592 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4258618511 Jun 28 05:57:09 PM PDT 24 Jun 28 05:57:13 PM PDT 24 75075074 ps
T593 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2563886666 Jun 28 05:57:06 PM PDT 24 Jun 28 05:57:10 PM PDT 24 478735865 ps
T594 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3789351613 Jun 28 05:57:09 PM PDT 24 Jun 28 05:57:16 PM PDT 24 428043089 ps
T595 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2189494494 Jun 28 05:56:50 PM PDT 24 Jun 28 05:56:53 PM PDT 24 70573155 ps
T596 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.204614206 Jun 28 05:57:09 PM PDT 24 Jun 28 05:57:15 PM PDT 24 211189201 ps
T597 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.207860922 Jun 28 05:57:01 PM PDT 24 Jun 28 05:57:04 PM PDT 24 68700495 ps
T598 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.558327985 Jun 28 05:57:01 PM PDT 24 Jun 28 05:57:05 PM PDT 24 226915341 ps
T599 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1418583189 Jun 28 05:56:59 PM PDT 24 Jun 28 05:57:03 PM PDT 24 157860155 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.246860309 Jun 28 05:56:50 PM PDT 24 Jun 28 05:56:55 PM PDT 24 310996796 ps
T601 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.290246181 Jun 28 05:57:07 PM PDT 24 Jun 28 05:57:11 PM PDT 24 63495463 ps
T602 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1428313443 Jun 28 05:57:17 PM PDT 24 Jun 28 05:57:21 PM PDT 24 232745576 ps
T603 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1334276583 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:15 PM PDT 24 82327463 ps
T604 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2564142264 Jun 28 05:57:22 PM PDT 24 Jun 28 05:57:24 PM PDT 24 63990050 ps
T605 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.925960751 Jun 28 05:57:09 PM PDT 24 Jun 28 05:57:14 PM PDT 24 169573249 ps
T606 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3093305698 Jun 28 05:57:16 PM PDT 24 Jun 28 05:57:21 PM PDT 24 492077567 ps
T607 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3661246763 Jun 28 05:57:08 PM PDT 24 Jun 28 05:57:14 PM PDT 24 435525060 ps
T608 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1703867956 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:14 PM PDT 24 54242133 ps
T609 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4044212217 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:15 PM PDT 24 122868395 ps
T610 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1520046125 Jun 28 05:57:01 PM PDT 24 Jun 28 05:57:05 PM PDT 24 71693468 ps
T611 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1049266485 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:15 PM PDT 24 103581501 ps
T612 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2937121774 Jun 28 05:57:18 PM PDT 24 Jun 28 05:57:22 PM PDT 24 241202004 ps
T613 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.774018563 Jun 28 05:57:07 PM PDT 24 Jun 28 05:57:11 PM PDT 24 431075371 ps
T132 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.449361369 Jun 28 05:57:10 PM PDT 24 Jun 28 05:57:16 PM PDT 24 945039469 ps
T614 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2601001305 Jun 28 05:56:46 PM PDT 24 Jun 28 05:56:49 PM PDT 24 234522908 ps
T615 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3847922946 Jun 28 05:56:46 PM PDT 24 Jun 28 05:56:51 PM PDT 24 505708542 ps
T616 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3869591697 Jun 28 05:57:00 PM PDT 24 Jun 28 05:57:12 PM PDT 24 2288472941 ps
T617 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2599967320 Jun 28 05:56:59 PM PDT 24 Jun 28 05:57:04 PM PDT 24 428582224 ps
T618 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2233421482 Jun 28 05:57:18 PM PDT 24 Jun 28 05:57:22 PM PDT 24 132112841 ps
T619 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3553927901 Jun 28 05:57:01 PM PDT 24 Jun 28 05:57:06 PM PDT 24 194830664 ps
T620 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1915597556 Jun 28 05:57:18 PM PDT 24 Jun 28 05:57:22 PM PDT 24 216441309 ps

Test location /workspace/coverage/default/0.rstmgr_smoke.2769785732
Short name T6
Test name
Test status
Simulation time 257367983 ps
CPU time 1.5 seconds
Started Jun 28 05:57:17 PM PDT 24
Finished Jun 28 05:57:20 PM PDT 24
Peak memory 200220 kb
Host smart-db68b9f2-8024-4b37-a72e-e27d073db06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769785732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2769785732
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1736694462
Short name T45
Test name
Test status
Simulation time 368238044 ps
CPU time 2.33 seconds
Started Jun 28 05:59:02 PM PDT 24
Finished Jun 28 05:59:05 PM PDT 24
Peak memory 208284 kb
Host smart-7a3b802e-6550-4d79-98e8-0f9b4c978cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736694462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1736694462
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1060860666
Short name T9
Test name
Test status
Simulation time 1900757209 ps
CPU time 7.2 seconds
Started Jun 28 05:59:27 PM PDT 24
Finished Jun 28 05:59:52 PM PDT 24
Peak memory 217732 kb
Host smart-886523d7-ccee-4630-8213-4c3d0fe3d507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060860666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1060860666
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.682588349
Short name T62
Test name
Test status
Simulation time 200286687 ps
CPU time 1.34 seconds
Started Jun 28 05:56:59 PM PDT 24
Finished Jun 28 05:57:01 PM PDT 24
Peak memory 208548 kb
Host smart-8791fd7a-009a-473a-b93f-f71db3e2208d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682588349 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.682588349
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.612247916
Short name T64
Test name
Test status
Simulation time 8563759058 ps
CPU time 12.79 seconds
Started Jun 28 05:58:13 PM PDT 24
Finished Jun 28 05:58:27 PM PDT 24
Peak memory 217120 kb
Host smart-f0f6a485-fcde-4dcf-9056-a1363849611d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612247916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.612247916
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3746502160
Short name T77
Test name
Test status
Simulation time 5437487805 ps
CPU time 24.18 seconds
Started Jun 28 05:59:00 PM PDT 24
Finished Jun 28 05:59:25 PM PDT 24
Peak memory 208648 kb
Host smart-59cc30f8-9b96-4644-88eb-ad45c79c4b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746502160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3746502160
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3060338782
Short name T95
Test name
Test status
Simulation time 920005367 ps
CPU time 3.45 seconds
Started Jun 28 05:56:47 PM PDT 24
Finished Jun 28 05:56:52 PM PDT 24
Peak memory 200432 kb
Host smart-da3a9e33-2080-4bfb-a1a9-51629a49cdb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060338782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3060338782
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2778772418
Short name T160
Test name
Test status
Simulation time 84406132 ps
CPU time 0.81 seconds
Started Jun 28 05:58:28 PM PDT 24
Finished Jun 28 05:58:30 PM PDT 24
Peak memory 199872 kb
Host smart-ea551fc1-bf6e-4d48-a10a-2b8c48cd9831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778772418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2778772418
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.928579923
Short name T134
Test name
Test status
Simulation time 176121323 ps
CPU time 2.45 seconds
Started Jun 28 05:57:08 PM PDT 24
Finished Jun 28 05:57:13 PM PDT 24
Peak memory 208556 kb
Host smart-0d2194dc-3bc8-4db9-a42c-ad1c72002cf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928579923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.928579923
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.123265613
Short name T111
Test name
Test status
Simulation time 7712211840 ps
CPU time 25.76 seconds
Started Jun 28 05:59:48 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 200396 kb
Host smart-ad1e9b1a-f944-4897-b401-b2d02780c8e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123265613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.123265613
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1019840135
Short name T151
Test name
Test status
Simulation time 171788480 ps
CPU time 1.21 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:12 PM PDT 24
Peak memory 200092 kb
Host smart-866566bf-c9ab-431d-b674-94ed69c24f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019840135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1019840135
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2044182943
Short name T24
Test name
Test status
Simulation time 1226879891 ps
CPU time 5.47 seconds
Started Jun 28 05:58:28 PM PDT 24
Finished Jun 28 05:58:34 PM PDT 24
Peak memory 221636 kb
Host smart-c40c335c-387f-4f81-adad-7193408a069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044182943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2044182943
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.207805882
Short name T150
Test name
Test status
Simulation time 170567729 ps
CPU time 1.41 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 200224 kb
Host smart-3b9b9b21-2de3-4096-ad71-ef283ca1a12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207805882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.207805882
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2086408179
Short name T42
Test name
Test status
Simulation time 2383309429 ps
CPU time 8.01 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 217772 kb
Host smart-dfd22af3-f46e-4b1e-80f1-a015e2093188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086408179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2086408179
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3010200002
Short name T90
Test name
Test status
Simulation time 7642334365 ps
CPU time 38.19 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:43 PM PDT 24
Peak memory 208612 kb
Host smart-58115829-887e-4c8a-bc0d-102fc74801e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010200002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3010200002
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3928142687
Short name T54
Test name
Test status
Simulation time 176693864 ps
CPU time 2.61 seconds
Started Jun 28 05:57:00 PM PDT 24
Finished Jun 28 05:57:06 PM PDT 24
Peak memory 208560 kb
Host smart-8a9a75c0-ccce-41f8-9dbe-ca9d90f5a049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928142687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3928142687
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2043065728
Short name T129
Test name
Test status
Simulation time 947085596 ps
CPU time 3.1 seconds
Started Jun 28 05:57:12 PM PDT 24
Finished Jun 28 05:57:19 PM PDT 24
Peak memory 200072 kb
Host smart-81c32001-9ff1-46fb-a373-2c24871b3b21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043065728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2043065728
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1272781013
Short name T122
Test name
Test status
Simulation time 122526451 ps
CPU time 1.13 seconds
Started Jun 28 05:56:46 PM PDT 24
Finished Jun 28 05:56:49 PM PDT 24
Peak memory 200296 kb
Host smart-69f5ad59-ba17-4565-acd7-0b784aa12730
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272781013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1272781013
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1240417924
Short name T14
Test name
Test status
Simulation time 114277178 ps
CPU time 0.82 seconds
Started Jun 28 05:57:19 PM PDT 24
Finished Jun 28 05:57:22 PM PDT 24
Peak memory 199892 kb
Host smart-f3e027ab-464e-4be6-8df5-0386838f6819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240417924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1240417924
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3196198948
Short name T49
Test name
Test status
Simulation time 506918672 ps
CPU time 2.01 seconds
Started Jun 28 05:56:48 PM PDT 24
Finished Jun 28 05:56:53 PM PDT 24
Peak memory 200444 kb
Host smart-336d6c71-1b26-492f-b5d7-237a38f147e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196198948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3196198948
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2601001305
Short name T614
Test name
Test status
Simulation time 234522908 ps
CPU time 1.63 seconds
Started Jun 28 05:56:46 PM PDT 24
Finished Jun 28 05:56:49 PM PDT 24
Peak memory 200420 kb
Host smart-a5fd81a1-9669-47b9-b0f5-f4997d56f4fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601001305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
601001305
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2163977247
Short name T577
Test name
Test status
Simulation time 485070700 ps
CPU time 5.68 seconds
Started Jun 28 05:56:47 PM PDT 24
Finished Jun 28 05:56:55 PM PDT 24
Peak memory 200252 kb
Host smart-f60f75fa-65cd-407f-a28a-a6add88267d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163977247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
163977247
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2595681718
Short name T586
Test name
Test status
Simulation time 87621630 ps
CPU time 0.78 seconds
Started Jun 28 05:56:49 PM PDT 24
Finished Jun 28 05:56:53 PM PDT 24
Peak memory 200232 kb
Host smart-68d6c1a6-b5cb-4d66-8472-0ddaee11bd41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595681718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
595681718
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.422357557
Short name T558
Test name
Test status
Simulation time 137036115 ps
CPU time 1.49 seconds
Started Jun 28 05:56:47 PM PDT 24
Finished Jun 28 05:56:51 PM PDT 24
Peak memory 208672 kb
Host smart-72d4e4a3-bc68-4ff2-852a-3980c59fc223
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422357557 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.422357557
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2189494494
Short name T595
Test name
Test status
Simulation time 70573155 ps
CPU time 0.83 seconds
Started Jun 28 05:56:50 PM PDT 24
Finished Jun 28 05:56:53 PM PDT 24
Peak memory 200044 kb
Host smart-ec766b9e-d1e2-4ff4-87a5-240acf1893d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189494494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2189494494
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3847922946
Short name T615
Test name
Test status
Simulation time 505708542 ps
CPU time 3.53 seconds
Started Jun 28 05:56:46 PM PDT 24
Finished Jun 28 05:56:51 PM PDT 24
Peak memory 208596 kb
Host smart-0e29aefa-5287-4b1d-a3e3-017e1d3471f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847922946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3847922946
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3407065410
Short name T543
Test name
Test status
Simulation time 100898282 ps
CPU time 1.42 seconds
Started Jun 28 05:56:57 PM PDT 24
Finished Jun 28 05:57:00 PM PDT 24
Peak memory 200296 kb
Host smart-68f8b347-6dd6-469b-9716-b525fed310ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407065410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
407065410
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3331820651
Short name T545
Test name
Test status
Simulation time 2293877671 ps
CPU time 10.45 seconds
Started Jun 28 05:57:00 PM PDT 24
Finished Jun 28 05:57:12 PM PDT 24
Peak memory 200436 kb
Host smart-1bc20b22-2c70-49de-ab5d-ce392238079a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331820651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
331820651
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1477863194
Short name T542
Test name
Test status
Simulation time 99947491 ps
CPU time 0.84 seconds
Started Jun 28 05:56:59 PM PDT 24
Finished Jun 28 05:57:01 PM PDT 24
Peak memory 200240 kb
Host smart-4aa19148-747d-44e8-8abd-26bb056a40d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477863194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
477863194
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.595710219
Short name T555
Test name
Test status
Simulation time 201491851 ps
CPU time 1.47 seconds
Started Jun 28 05:56:59 PM PDT 24
Finished Jun 28 05:57:02 PM PDT 24
Peak memory 211312 kb
Host smart-7e9a1f83-eaa0-4223-bea9-9108f7b59191
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595710219 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.595710219
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4289708488
Short name T556
Test name
Test status
Simulation time 66279501 ps
CPU time 0.85 seconds
Started Jun 28 05:57:00 PM PDT 24
Finished Jun 28 05:57:04 PM PDT 24
Peak memory 200224 kb
Host smart-00b59d1f-afdc-4635-982f-fe281b9664d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289708488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.4289708488
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1584689471
Short name T560
Test name
Test status
Simulation time 136567405 ps
CPU time 1.19 seconds
Started Jun 28 05:57:00 PM PDT 24
Finished Jun 28 05:57:04 PM PDT 24
Peak memory 200220 kb
Host smart-890cdd6a-5622-4efc-8c59-e057d99e15c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584689471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1584689471
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.246860309
Short name T600
Test name
Test status
Simulation time 310996796 ps
CPU time 2.48 seconds
Started Jun 28 05:56:50 PM PDT 24
Finished Jun 28 05:56:55 PM PDT 24
Peak memory 208620 kb
Host smart-173f3951-646a-4274-a540-ec7ea27a2749
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246860309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.246860309
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.204614206
Short name T596
Test name
Test status
Simulation time 211189201 ps
CPU time 2.1 seconds
Started Jun 28 05:57:09 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 208772 kb
Host smart-ec0f2f0e-e872-4331-b5d0-370c7155fbac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204614206 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.204614206
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1694853139
Short name T552
Test name
Test status
Simulation time 83785537 ps
CPU time 0.87 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 200196 kb
Host smart-b24d4b9e-f0ef-4f0b-93d6-dc63b2cac872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694853139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1694853139
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1334276583
Short name T603
Test name
Test status
Simulation time 82327463 ps
CPU time 0.95 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 200280 kb
Host smart-3bf543a0-8012-4f40-9701-a49d34838991
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334276583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1334276583
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3724667376
Short name T572
Test name
Test status
Simulation time 315615151 ps
CPU time 2.39 seconds
Started Jun 28 05:57:12 PM PDT 24
Finished Jun 28 05:57:18 PM PDT 24
Peak memory 208540 kb
Host smart-75cb3b85-c014-4f5b-82cd-7f44240bbfe3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724667376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3724667376
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.449361369
Short name T132
Test name
Test status
Simulation time 945039469 ps
CPU time 2.93 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:16 PM PDT 24
Peak memory 200416 kb
Host smart-d9ee7bf9-8a1f-42fe-bed3-3f88823e9d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449361369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.449361369
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1868787728
Short name T549
Test name
Test status
Simulation time 106622963 ps
CPU time 0.95 seconds
Started Jun 28 05:57:07 PM PDT 24
Finished Jun 28 05:57:10 PM PDT 24
Peak memory 200296 kb
Host smart-37922a77-1fba-46a8-9508-b86dca40ae2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868787728 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1868787728
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.290246181
Short name T601
Test name
Test status
Simulation time 63495463 ps
CPU time 0.79 seconds
Started Jun 28 05:57:07 PM PDT 24
Finished Jun 28 05:57:11 PM PDT 24
Peak memory 200224 kb
Host smart-e7eeab26-4f42-4f70-aa1c-df805115ae39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290246181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.290246181
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3667219756
Short name T118
Test name
Test status
Simulation time 158988317 ps
CPU time 1.16 seconds
Started Jun 28 05:57:08 PM PDT 24
Finished Jun 28 05:57:12 PM PDT 24
Peak memory 200292 kb
Host smart-9506c430-ece8-4c8e-af2a-5c93f5ccc606
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667219756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3667219756
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1359710891
Short name T94
Test name
Test status
Simulation time 445917731 ps
CPU time 2.91 seconds
Started Jun 28 05:57:08 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 216644 kb
Host smart-03fe08cf-10c5-48c1-a8f3-64432e4259be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359710891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1359710891
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1345529635
Short name T130
Test name
Test status
Simulation time 1092423157 ps
CPU time 3.62 seconds
Started Jun 28 05:57:09 PM PDT 24
Finished Jun 28 05:57:17 PM PDT 24
Peak memory 200452 kb
Host smart-be451086-68be-476f-aae6-d4c7c0ae2f31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345529635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1345529635
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4044212217
Short name T609
Test name
Test status
Simulation time 122868395 ps
CPU time 1.37 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 208456 kb
Host smart-13ad3b1b-99c1-4828-a258-0eeba8e88ae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044212217 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.4044212217
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1703867956
Short name T608
Test name
Test status
Simulation time 54242133 ps
CPU time 0.75 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:14 PM PDT 24
Peak memory 200136 kb
Host smart-cbc0e6f7-9027-4f1b-a6b1-50bba921b7f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703867956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1703867956
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3572392210
Short name T571
Test name
Test status
Simulation time 195915953 ps
CPU time 1.43 seconds
Started Jun 28 05:57:05 PM PDT 24
Finished Jun 28 05:57:09 PM PDT 24
Peak memory 200392 kb
Host smart-20427482-78cf-488a-aa1d-ec7177977f06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572392210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3572392210
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3643309458
Short name T55
Test name
Test status
Simulation time 230028586 ps
CPU time 1.93 seconds
Started Jun 28 05:57:09 PM PDT 24
Finished Jun 28 05:57:14 PM PDT 24
Peak memory 208536 kb
Host smart-01744747-86f0-47ce-b909-92a542bcaf19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643309458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3643309458
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.259572447
Short name T589
Test name
Test status
Simulation time 407411993 ps
CPU time 1.77 seconds
Started Jun 28 05:57:12 PM PDT 24
Finished Jun 28 05:57:17 PM PDT 24
Peak memory 200416 kb
Host smart-f8dd988d-ecca-47b2-8909-5e948841597d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259572447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.259572447
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3229892299
Short name T564
Test name
Test status
Simulation time 195163845 ps
CPU time 1.33 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:14 PM PDT 24
Peak memory 208388 kb
Host smart-efda3c38-75bd-4958-b2d4-31bb6991b1f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229892299 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3229892299
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3299041458
Short name T566
Test name
Test status
Simulation time 77610291 ps
CPU time 0.73 seconds
Started Jun 28 05:57:06 PM PDT 24
Finished Jun 28 05:57:09 PM PDT 24
Peak memory 199916 kb
Host smart-31981d17-ad1d-445f-b66a-68a324a6ccf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299041458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3299041458
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.461904091
Short name T125
Test name
Test status
Simulation time 83995788 ps
CPU time 1 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:14 PM PDT 24
Peak memory 200200 kb
Host smart-7ad82cdd-7367-469a-9c1f-e0ce4ab3b00f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461904091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.461904091
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3789351613
Short name T594
Test name
Test status
Simulation time 428043089 ps
CPU time 3.19 seconds
Started Jun 28 05:57:09 PM PDT 24
Finished Jun 28 05:57:16 PM PDT 24
Peak memory 208468 kb
Host smart-191600d6-0d85-49ac-ba32-5bfc0f27f16a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789351613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3789351613
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.287755981
Short name T147
Test name
Test status
Simulation time 477163951 ps
CPU time 2.09 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 200432 kb
Host smart-de56218b-ad19-4a19-9230-8691a844fa55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287755981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.287755981
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4257876157
Short name T582
Test name
Test status
Simulation time 120947557 ps
CPU time 0.96 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 200356 kb
Host smart-31cc0256-4084-4687-9176-ef16aeea69f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257876157 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.4257876157
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3629429364
Short name T565
Test name
Test status
Simulation time 79191117 ps
CPU time 0.81 seconds
Started Jun 28 05:57:08 PM PDT 24
Finished Jun 28 05:57:11 PM PDT 24
Peak memory 200220 kb
Host smart-c7f0b072-dc94-4cda-905c-53383cac6242
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629429364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3629429364
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4050096384
Short name T119
Test name
Test status
Simulation time 137313848 ps
CPU time 1.38 seconds
Started Jun 28 05:57:11 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 200412 kb
Host smart-0741762e-6fb7-4fab-a59e-17f10fe27dbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050096384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.4050096384
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2563886666
Short name T593
Test name
Test status
Simulation time 478735865 ps
CPU time 1.96 seconds
Started Jun 28 05:57:06 PM PDT 24
Finished Jun 28 05:57:10 PM PDT 24
Peak memory 200384 kb
Host smart-7b82d71e-b321-4765-8198-74651f56f1b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563886666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2563886666
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.375404932
Short name T100
Test name
Test status
Simulation time 188861576 ps
CPU time 1.18 seconds
Started Jun 28 05:57:23 PM PDT 24
Finished Jun 28 05:57:25 PM PDT 24
Peak memory 209884 kb
Host smart-e88fecd3-7980-4c5d-ba6a-8135c4d9ab2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375404932 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.375404932
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.41149922
Short name T579
Test name
Test status
Simulation time 80123424 ps
CPU time 0.8 seconds
Started Jun 28 05:57:17 PM PDT 24
Finished Jun 28 05:57:19 PM PDT 24
Peak memory 200136 kb
Host smart-b2c3fcc4-8f91-4482-a712-742e5f1b0c04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41149922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.41149922
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1090402248
Short name T124
Test name
Test status
Simulation time 276316342 ps
CPU time 1.64 seconds
Started Jun 28 05:57:17 PM PDT 24
Finished Jun 28 05:57:20 PM PDT 24
Peak memory 200408 kb
Host smart-1cc8f0a4-4bdf-4eee-9f16-dc3ef515356b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090402248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1090402248
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1915597556
Short name T620
Test name
Test status
Simulation time 216441309 ps
CPU time 1.91 seconds
Started Jun 28 05:57:18 PM PDT 24
Finished Jun 28 05:57:22 PM PDT 24
Peak memory 216592 kb
Host smart-9fc313c4-5720-471f-8884-993aab051680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915597556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1915597556
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2824227584
Short name T97
Test name
Test status
Simulation time 418733586 ps
CPU time 1.91 seconds
Started Jun 28 05:57:16 PM PDT 24
Finished Jun 28 05:57:19 PM PDT 24
Peak memory 200428 kb
Host smart-0e1e6808-da0d-4d80-9007-c9326ca6b9dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824227584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2824227584
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2496053750
Short name T570
Test name
Test status
Simulation time 185784231 ps
CPU time 1.26 seconds
Started Jun 28 05:57:18 PM PDT 24
Finished Jun 28 05:57:21 PM PDT 24
Peak memory 200268 kb
Host smart-919d9ece-f1a5-44b2-bf01-92b68c4c1c87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496053750 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2496053750
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2106341469
Short name T580
Test name
Test status
Simulation time 70986403 ps
CPU time 0.78 seconds
Started Jun 28 05:57:18 PM PDT 24
Finished Jun 28 05:57:21 PM PDT 24
Peak memory 200224 kb
Host smart-0387553d-14fc-4240-9111-f72d0b57b6ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106341469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2106341469
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2937121774
Short name T612
Test name
Test status
Simulation time 241202004 ps
CPU time 1.49 seconds
Started Jun 28 05:57:18 PM PDT 24
Finished Jun 28 05:57:22 PM PDT 24
Peak memory 200476 kb
Host smart-8930ea6f-5f7b-427e-8861-fddafbd91ec7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937121774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2937121774
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3093305698
Short name T606
Test name
Test status
Simulation time 492077567 ps
CPU time 3.38 seconds
Started Jun 28 05:57:16 PM PDT 24
Finished Jun 28 05:57:21 PM PDT 24
Peak memory 211372 kb
Host smart-abd14c03-d03b-4adf-9eab-d0e91726d79b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093305698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3093305698
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1780375461
Short name T585
Test name
Test status
Simulation time 1467214709 ps
CPU time 4.13 seconds
Started Jun 28 05:57:16 PM PDT 24
Finished Jun 28 05:57:22 PM PDT 24
Peak memory 200436 kb
Host smart-87237fac-974b-41b7-a221-72880579ea61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780375461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1780375461
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2788371202
Short name T562
Test name
Test status
Simulation time 119118006 ps
CPU time 1 seconds
Started Jun 28 05:57:18 PM PDT 24
Finished Jun 28 05:57:21 PM PDT 24
Peak memory 209576 kb
Host smart-d04b0352-c05c-4b36-a653-f6e840bf28f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788371202 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2788371202
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2564142264
Short name T604
Test name
Test status
Simulation time 63990050 ps
CPU time 0.76 seconds
Started Jun 28 05:57:22 PM PDT 24
Finished Jun 28 05:57:24 PM PDT 24
Peak memory 200220 kb
Host smart-3468f1dd-b324-4e90-93a7-67ed0e765e4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564142264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2564142264
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2792483979
Short name T550
Test name
Test status
Simulation time 144030450 ps
CPU time 1.1 seconds
Started Jun 28 05:57:16 PM PDT 24
Finished Jun 28 05:57:19 PM PDT 24
Peak memory 200256 kb
Host smart-7250acb7-6a36-4fc8-86a6-a8f39e0d2b70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792483979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2792483979
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2233421482
Short name T618
Test name
Test status
Simulation time 132112841 ps
CPU time 1.95 seconds
Started Jun 28 05:57:18 PM PDT 24
Finished Jun 28 05:57:22 PM PDT 24
Peak memory 216576 kb
Host smart-627c1b22-fd3c-406d-8979-147223ad6f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233421482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2233421482
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2077839944
Short name T574
Test name
Test status
Simulation time 888659861 ps
CPU time 3.04 seconds
Started Jun 28 05:57:17 PM PDT 24
Finished Jun 28 05:57:22 PM PDT 24
Peak memory 200432 kb
Host smart-81a6afc8-8982-44ae-b621-681328d92272
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077839944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2077839944
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3475668628
Short name T554
Test name
Test status
Simulation time 190773031 ps
CPU time 1.84 seconds
Started Jun 28 05:57:17 PM PDT 24
Finished Jun 28 05:57:20 PM PDT 24
Peak memory 208688 kb
Host smart-88a46eb7-2531-40ea-bd58-687735ed4fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475668628 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3475668628
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3914719327
Short name T590
Test name
Test status
Simulation time 63524258 ps
CPU time 0.9 seconds
Started Jun 28 05:57:15 PM PDT 24
Finished Jun 28 05:57:18 PM PDT 24
Peak memory 200356 kb
Host smart-b3070690-dc2d-4a61-84a4-c6157e0cf161
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914719327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3914719327
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1428313443
Short name T602
Test name
Test status
Simulation time 232745576 ps
CPU time 1.48 seconds
Started Jun 28 05:57:17 PM PDT 24
Finished Jun 28 05:57:21 PM PDT 24
Peak memory 200400 kb
Host smart-0d1c0415-b105-4860-9ec8-c463d80042e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428313443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1428313443
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3949087433
Short name T133
Test name
Test status
Simulation time 535949685 ps
CPU time 3.38 seconds
Started Jun 28 05:57:22 PM PDT 24
Finished Jun 28 05:57:27 PM PDT 24
Peak memory 208556 kb
Host smart-775aea17-3721-4012-a5bd-c5fcadac90e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949087433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3949087433
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3646735568
Short name T92
Test name
Test status
Simulation time 522169129 ps
CPU time 1.96 seconds
Started Jun 28 05:57:17 PM PDT 24
Finished Jun 28 05:57:21 PM PDT 24
Peak memory 200492 kb
Host smart-b2c10ebc-9fb2-4d98-81fc-3cee3401729c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646735568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3646735568
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1644735937
Short name T99
Test name
Test status
Simulation time 124689548 ps
CPU time 0.94 seconds
Started Jun 28 05:57:17 PM PDT 24
Finished Jun 28 05:57:20 PM PDT 24
Peak memory 200360 kb
Host smart-91eb117b-6d74-4acd-8011-c280e203ffb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644735937 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1644735937
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.522363234
Short name T546
Test name
Test status
Simulation time 84898425 ps
CPU time 0.87 seconds
Started Jun 28 05:57:18 PM PDT 24
Finished Jun 28 05:57:20 PM PDT 24
Peak memory 200152 kb
Host smart-0e0643bf-1f47-4467-8ad9-8ca7477a2c3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522363234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.522363234
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4121048585
Short name T569
Test name
Test status
Simulation time 242666030 ps
CPU time 1.55 seconds
Started Jun 28 05:57:18 PM PDT 24
Finished Jun 28 05:57:21 PM PDT 24
Peak memory 200476 kb
Host smart-35b6b340-80b4-4053-8740-53317eeccd7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121048585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.4121048585
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.325853309
Short name T575
Test name
Test status
Simulation time 273121926 ps
CPU time 1.89 seconds
Started Jun 28 05:57:18 PM PDT 24
Finished Jun 28 05:57:22 PM PDT 24
Peak memory 200352 kb
Host smart-86f49f66-e6f7-441d-86eb-d427e3ff5787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325853309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.325853309
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2849827844
Short name T128
Test name
Test status
Simulation time 932457229 ps
CPU time 3.2 seconds
Started Jun 28 05:57:16 PM PDT 24
Finished Jun 28 05:57:21 PM PDT 24
Peak memory 200480 kb
Host smart-f1c31003-e170-4b32-bba7-1d1539e190e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849827844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2849827844
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3626946589
Short name T544
Test name
Test status
Simulation time 146944430 ps
CPU time 2 seconds
Started Jun 28 05:56:58 PM PDT 24
Finished Jun 28 05:57:01 PM PDT 24
Peak memory 200368 kb
Host smart-453ab24b-bbaf-4303-b3b9-bb4d010d6050
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626946589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
626946589
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3869591697
Short name T616
Test name
Test status
Simulation time 2288472941 ps
CPU time 9.81 seconds
Started Jun 28 05:57:00 PM PDT 24
Finished Jun 28 05:57:12 PM PDT 24
Peak memory 200488 kb
Host smart-d7282b3a-625d-4f2a-9d9a-123aa3a48a44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869591697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
869591697
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2621235136
Short name T551
Test name
Test status
Simulation time 106981863 ps
CPU time 0.86 seconds
Started Jun 28 05:56:58 PM PDT 24
Finished Jun 28 05:57:01 PM PDT 24
Peak memory 200228 kb
Host smart-57d6b7d7-e2d1-4404-8ace-cac8cf52950a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621235136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
621235136
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3553927901
Short name T619
Test name
Test status
Simulation time 194830664 ps
CPU time 1.2 seconds
Started Jun 28 05:57:01 PM PDT 24
Finished Jun 28 05:57:06 PM PDT 24
Peak memory 208532 kb
Host smart-2ae25c63-c28a-4652-84e9-f74cb0272ece
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553927901 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3553927901
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.207860922
Short name T597
Test name
Test status
Simulation time 68700495 ps
CPU time 0.84 seconds
Started Jun 28 05:57:01 PM PDT 24
Finished Jun 28 05:57:04 PM PDT 24
Peak memory 200216 kb
Host smart-d6c36b34-d208-4364-9b88-84ec8d16b6d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207860922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.207860922
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.240948805
Short name T126
Test name
Test status
Simulation time 278319647 ps
CPU time 1.68 seconds
Started Jun 28 05:57:00 PM PDT 24
Finished Jun 28 05:57:04 PM PDT 24
Peak memory 200400 kb
Host smart-0bb45754-f973-4741-84c6-7a1c78e46b40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240948805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.240948805
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3803768367
Short name T56
Test name
Test status
Simulation time 492945862 ps
CPU time 1.92 seconds
Started Jun 28 05:57:00 PM PDT 24
Finished Jun 28 05:57:05 PM PDT 24
Peak memory 200444 kb
Host smart-3e6b8047-e331-4927-af48-cd4037ad1bc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803768367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3803768367
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4105629935
Short name T591
Test name
Test status
Simulation time 112942546 ps
CPU time 1.32 seconds
Started Jun 28 05:56:58 PM PDT 24
Finished Jun 28 05:57:00 PM PDT 24
Peak memory 200384 kb
Host smart-af49e613-1fc4-4d2b-9189-488458c481d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105629935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
105629935
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.903889327
Short name T587
Test name
Test status
Simulation time 1552216312 ps
CPU time 8.66 seconds
Started Jun 28 05:56:58 PM PDT 24
Finished Jun 28 05:57:08 PM PDT 24
Peak memory 200384 kb
Host smart-896f9a26-5863-427b-8fde-d47b1ce65846
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903889327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.903889327
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2961159525
Short name T576
Test name
Test status
Simulation time 123624619 ps
CPU time 0.93 seconds
Started Jun 28 05:57:00 PM PDT 24
Finished Jun 28 05:57:03 PM PDT 24
Peak memory 200208 kb
Host smart-6e5d2f82-5214-4d8f-8cd6-43169e6c587b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961159525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
961159525
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2270289783
Short name T584
Test name
Test status
Simulation time 64820475 ps
CPU time 0.79 seconds
Started Jun 28 05:56:57 PM PDT 24
Finished Jun 28 05:56:59 PM PDT 24
Peak memory 200224 kb
Host smart-80800833-0a7e-420d-a39a-780254911dc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270289783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2270289783
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2046465779
Short name T50
Test name
Test status
Simulation time 243737372 ps
CPU time 1.75 seconds
Started Jun 28 05:56:59 PM PDT 24
Finished Jun 28 05:57:02 PM PDT 24
Peak memory 200420 kb
Host smart-0e0c8c03-932d-4379-9d3e-897e9fffeaf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046465779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2046465779
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.692950995
Short name T563
Test name
Test status
Simulation time 119288194 ps
CPU time 1.64 seconds
Started Jun 28 05:56:58 PM PDT 24
Finished Jun 28 05:57:01 PM PDT 24
Peak memory 211028 kb
Host smart-462dd242-f753-4ad1-b47a-c71e5f84862d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692950995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.692950995
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3160810140
Short name T131
Test name
Test status
Simulation time 770574971 ps
CPU time 2.72 seconds
Started Jun 28 05:56:59 PM PDT 24
Finished Jun 28 05:57:03 PM PDT 24
Peak memory 200448 kb
Host smart-b5dc950f-0c2c-446c-a4b0-6b035c7107e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160810140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3160810140
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3194550175
Short name T548
Test name
Test status
Simulation time 405826767 ps
CPU time 2.5 seconds
Started Jun 28 05:57:00 PM PDT 24
Finished Jun 28 05:57:05 PM PDT 24
Peak memory 200380 kb
Host smart-b5b0a8dd-270d-4f90-82ed-335f49338c2c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194550175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
194550175
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2949383443
Short name T578
Test name
Test status
Simulation time 485655175 ps
CPU time 5.8 seconds
Started Jun 28 05:57:01 PM PDT 24
Finished Jun 28 05:57:10 PM PDT 24
Peak memory 200376 kb
Host smart-7539e81b-2e90-4265-9b00-ec31b6467c78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949383443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
949383443
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.785309960
Short name T51
Test name
Test status
Simulation time 120400872 ps
CPU time 0.91 seconds
Started Jun 28 05:57:01 PM PDT 24
Finished Jun 28 05:57:04 PM PDT 24
Peak memory 200228 kb
Host smart-55919f7e-88c8-4eda-a18c-ce1093c45294
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785309960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.785309960
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2093823939
Short name T581
Test name
Test status
Simulation time 120956072 ps
CPU time 1.04 seconds
Started Jun 28 05:56:58 PM PDT 24
Finished Jun 28 05:57:01 PM PDT 24
Peak memory 200276 kb
Host smart-313b5388-a40a-4aa1-b53b-c27a88862305
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093823939 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2093823939
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1520046125
Short name T610
Test name
Test status
Simulation time 71693468 ps
CPU time 0.91 seconds
Started Jun 28 05:57:01 PM PDT 24
Finished Jun 28 05:57:05 PM PDT 24
Peak memory 200224 kb
Host smart-359a0de2-68c8-44e7-842b-4b5f459190b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520046125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1520046125
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.558327985
Short name T598
Test name
Test status
Simulation time 226915341 ps
CPU time 1.59 seconds
Started Jun 28 05:57:01 PM PDT 24
Finished Jun 28 05:57:05 PM PDT 24
Peak memory 200404 kb
Host smart-ba88ca48-e719-41e4-a9e8-ddd8d8e42217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558327985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.558327985
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3447177167
Short name T101
Test name
Test status
Simulation time 400031686 ps
CPU time 2.92 seconds
Started Jun 28 05:57:01 PM PDT 24
Finished Jun 28 05:57:07 PM PDT 24
Peak memory 208596 kb
Host smart-ac37c9e8-935e-4e83-a549-cd8a397c3765
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447177167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3447177167
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4094206190
Short name T93
Test name
Test status
Simulation time 779954566 ps
CPU time 2.95 seconds
Started Jun 28 05:56:59 PM PDT 24
Finished Jun 28 05:57:03 PM PDT 24
Peak memory 200440 kb
Host smart-dee0ca97-1b0f-4c95-ac36-8dae6e86a053
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094206190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.4094206190
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.925960751
Short name T605
Test name
Test status
Simulation time 169573249 ps
CPU time 1.67 seconds
Started Jun 28 05:57:09 PM PDT 24
Finished Jun 28 05:57:14 PM PDT 24
Peak memory 213872 kb
Host smart-014a0bd1-b6fb-4004-ab47-14c05dba8379
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925960751 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.925960751
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.891262988
Short name T123
Test name
Test status
Simulation time 75908468 ps
CPU time 0.84 seconds
Started Jun 28 05:57:08 PM PDT 24
Finished Jun 28 05:57:11 PM PDT 24
Peak memory 200176 kb
Host smart-af0a5f7a-6be2-44b1-b6e0-af153a317c35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891262988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.891262988
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.266082389
Short name T567
Test name
Test status
Simulation time 125897453 ps
CPU time 1.26 seconds
Started Jun 28 05:57:09 PM PDT 24
Finished Jun 28 05:57:13 PM PDT 24
Peak memory 200496 kb
Host smart-d3238129-3d1b-40b7-b349-e32b78d8786c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266082389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.266082389
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1418583189
Short name T599
Test name
Test status
Simulation time 157860155 ps
CPU time 2.31 seconds
Started Jun 28 05:56:59 PM PDT 24
Finished Jun 28 05:57:03 PM PDT 24
Peak memory 208428 kb
Host smart-e785ab04-b585-477c-983e-105b5ebc5d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418583189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1418583189
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2599967320
Short name T617
Test name
Test status
Simulation time 428582224 ps
CPU time 2.07 seconds
Started Jun 28 05:56:59 PM PDT 24
Finished Jun 28 05:57:04 PM PDT 24
Peak memory 200488 kb
Host smart-e80791b0-43f2-40b2-9075-d7a5e039a90b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599967320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2599967320
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.163755481
Short name T96
Test name
Test status
Simulation time 138490540 ps
CPU time 1.42 seconds
Started Jun 28 05:57:09 PM PDT 24
Finished Jun 28 05:57:14 PM PDT 24
Peak memory 208528 kb
Host smart-996d4a4a-b132-42f7-84a8-bfbe670e6f1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163755481 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.163755481
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1037201562
Short name T120
Test name
Test status
Simulation time 66119891 ps
CPU time 0.78 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:14 PM PDT 24
Peak memory 200220 kb
Host smart-b58c0a30-0d4d-47b4-b1e3-4fed7ba98ad8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037201562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1037201562
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3408314731
Short name T121
Test name
Test status
Simulation time 110816379 ps
CPU time 1.28 seconds
Started Jun 28 05:57:08 PM PDT 24
Finished Jun 28 05:57:13 PM PDT 24
Peak memory 200476 kb
Host smart-09b6700e-d968-41e6-a7cb-822464025d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408314731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3408314731
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3544248262
Short name T557
Test name
Test status
Simulation time 516067438 ps
CPU time 3.91 seconds
Started Jun 28 05:57:08 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 212260 kb
Host smart-a96e4e04-b33b-4703-bd48-20fc53a92228
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544248262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3544248262
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.877871837
Short name T98
Test name
Test status
Simulation time 895241418 ps
CPU time 3.17 seconds
Started Jun 28 05:57:08 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 200376 kb
Host smart-16a961a0-eaf4-4c44-a8dd-5d28ec6d78c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877871837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
877871837
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.680715420
Short name T48
Test name
Test status
Simulation time 144244520 ps
CPU time 1.22 seconds
Started Jun 28 05:57:07 PM PDT 24
Finished Jun 28 05:57:10 PM PDT 24
Peak memory 208532 kb
Host smart-2dd98c38-cc45-4a38-a368-bb107cdbc8c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680715420 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.680715420
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2101235890
Short name T547
Test name
Test status
Simulation time 66362905 ps
CPU time 0.76 seconds
Started Jun 28 05:57:12 PM PDT 24
Finished Jun 28 05:57:16 PM PDT 24
Peak memory 199720 kb
Host smart-a749015d-0eaa-4a63-97c8-8008fa253244
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101235890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2101235890
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.670554808
Short name T561
Test name
Test status
Simulation time 232860673 ps
CPU time 1.59 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 200456 kb
Host smart-9d5fd3b8-2f43-4b95-a87b-ea2692dde72c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670554808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.670554808
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3661246763
Short name T607
Test name
Test status
Simulation time 435525060 ps
CPU time 3.15 seconds
Started Jun 28 05:57:08 PM PDT 24
Finished Jun 28 05:57:14 PM PDT 24
Peak memory 212136 kb
Host smart-1250255d-1090-404c-b89e-766c45f5d3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661246763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3661246763
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1963395951
Short name T102
Test name
Test status
Simulation time 424692655 ps
CPU time 1.95 seconds
Started Jun 28 05:57:09 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 200436 kb
Host smart-5ed9e7c9-6ae1-4e0b-a3d9-6e4a641d4423
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963395951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1963395951
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1743613714
Short name T559
Test name
Test status
Simulation time 207107306 ps
CPU time 1.26 seconds
Started Jun 28 05:57:12 PM PDT 24
Finished Jun 28 05:57:17 PM PDT 24
Peak memory 208528 kb
Host smart-6cc34a72-2fe0-4730-9680-ad4476396daf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743613714 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1743613714
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4289039706
Short name T583
Test name
Test status
Simulation time 81160603 ps
CPU time 0.8 seconds
Started Jun 28 05:57:13 PM PDT 24
Finished Jun 28 05:57:17 PM PDT 24
Peak memory 200224 kb
Host smart-0acc77d6-a5f0-4398-b16b-7cadef1916eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289039706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4289039706
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2818541712
Short name T573
Test name
Test status
Simulation time 147319682 ps
CPU time 1.13 seconds
Started Jun 28 05:57:08 PM PDT 24
Finished Jun 28 05:57:12 PM PDT 24
Peak memory 200268 kb
Host smart-3712901c-a351-4dd2-8587-3d1c2f763c69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818541712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2818541712
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2124108427
Short name T553
Test name
Test status
Simulation time 442692595 ps
CPU time 2.9 seconds
Started Jun 28 05:57:07 PM PDT 24
Finished Jun 28 05:57:12 PM PDT 24
Peak memory 208488 kb
Host smart-7f8d289e-5ec4-4f65-9dcc-9f4dcd44ac57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124108427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2124108427
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.774018563
Short name T613
Test name
Test status
Simulation time 431075371 ps
CPU time 1.74 seconds
Started Jun 28 05:57:07 PM PDT 24
Finished Jun 28 05:57:11 PM PDT 24
Peak memory 200496 kb
Host smart-8e5f7d83-99eb-4fa7-b79c-c864a4c61acc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774018563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
774018563
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1049266485
Short name T611
Test name
Test status
Simulation time 103581501 ps
CPU time 1.09 seconds
Started Jun 28 05:57:10 PM PDT 24
Finished Jun 28 05:57:15 PM PDT 24
Peak memory 208520 kb
Host smart-e1085a86-4116-4332-94ed-7e622b4d7731
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049266485 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1049266485
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4258618511
Short name T592
Test name
Test status
Simulation time 75075074 ps
CPU time 0.8 seconds
Started Jun 28 05:57:09 PM PDT 24
Finished Jun 28 05:57:13 PM PDT 24
Peak memory 200316 kb
Host smart-e3add77c-e415-4417-99e2-f8fa061bfc25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258618511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.4258618511
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4029545792
Short name T568
Test name
Test status
Simulation time 232655508 ps
CPU time 1.52 seconds
Started Jun 28 05:57:07 PM PDT 24
Finished Jun 28 05:57:11 PM PDT 24
Peak memory 208592 kb
Host smart-cc264af0-81ff-48da-8aa7-37353bf1598a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029545792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.4029545792
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2411161565
Short name T588
Test name
Test status
Simulation time 117912051 ps
CPU time 1.67 seconds
Started Jun 28 05:57:07 PM PDT 24
Finished Jun 28 05:57:11 PM PDT 24
Peak memory 208536 kb
Host smart-39c6c701-8a44-4d85-befb-4c84e61615d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411161565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2411161565
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.4149352148
Short name T5
Test name
Test status
Simulation time 1227255752 ps
CPU time 5.7 seconds
Started Jun 28 05:58:25 PM PDT 24
Finished Jun 28 05:58:31 PM PDT 24
Peak memory 217676 kb
Host smart-981c5f31-400f-42c0-9339-125d7552372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149352148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.4149352148
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.700619785
Short name T287
Test name
Test status
Simulation time 243982923 ps
CPU time 1.1 seconds
Started Jun 28 05:58:28 PM PDT 24
Finished Jun 28 05:58:30 PM PDT 24
Peak memory 217396 kb
Host smart-afeb8976-5950-4cbe-abfb-74a24e4963f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700619785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.700619785
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3656499947
Short name T286
Test name
Test status
Simulation time 1083744677 ps
CPU time 5.02 seconds
Started Jun 28 05:57:19 PM PDT 24
Finished Jun 28 05:57:26 PM PDT 24
Peak memory 200388 kb
Host smart-327110d0-2568-4804-8edf-b78c2f9cbbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656499947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3656499947
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3777197373
Short name T343
Test name
Test status
Simulation time 170649554 ps
CPU time 1.19 seconds
Started Jun 28 05:58:27 PM PDT 24
Finished Jun 28 05:58:29 PM PDT 24
Peak memory 200096 kb
Host smart-2c36eb6a-beaa-4022-ae99-57554fd98bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777197373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3777197373
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1235717355
Short name T189
Test name
Test status
Simulation time 619446084 ps
CPU time 2.7 seconds
Started Jun 28 05:58:14 PM PDT 24
Finished Jun 28 05:58:17 PM PDT 24
Peak memory 200308 kb
Host smart-660407be-e322-40ad-af9b-ef4a5145fad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235717355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1235717355
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.147692264
Short name T85
Test name
Test status
Simulation time 118905293 ps
CPU time 1.45 seconds
Started Jun 28 05:58:24 PM PDT 24
Finished Jun 28 05:58:26 PM PDT 24
Peak memory 200080 kb
Host smart-fea95708-c190-4274-8675-06987618cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147692264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.147692264
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2200020590
Short name T463
Test name
Test status
Simulation time 229025221 ps
CPU time 1.32 seconds
Started Jun 28 05:58:15 PM PDT 24
Finished Jun 28 05:58:16 PM PDT 24
Peak memory 200076 kb
Host smart-7e9153ef-9fe5-43cd-b5c8-e354d8dc5f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200020590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2200020590
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1171095515
Short name T534
Test name
Test status
Simulation time 63707595 ps
CPU time 0.73 seconds
Started Jun 28 05:58:27 PM PDT 24
Finished Jun 28 05:58:28 PM PDT 24
Peak memory 199872 kb
Host smart-980a959e-5a1c-43ea-9e9b-9a46a4c14943
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171095515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1171095515
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2623881438
Short name T269
Test name
Test status
Simulation time 1896334080 ps
CPU time 6.63 seconds
Started Jun 28 05:58:11 PM PDT 24
Finished Jun 28 05:58:18 PM PDT 24
Peak memory 216764 kb
Host smart-c8b6fa7a-085f-4c8d-9010-3cd85fd1a7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623881438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2623881438
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.726896900
Short name T372
Test name
Test status
Simulation time 244118873 ps
CPU time 1.11 seconds
Started Jun 28 05:58:28 PM PDT 24
Finished Jun 28 05:58:30 PM PDT 24
Peak memory 217380 kb
Host smart-e6a35499-cd55-492a-b187-359924f2343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726896900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.726896900
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1674762965
Short name T165
Test name
Test status
Simulation time 236239029 ps
CPU time 1 seconds
Started Jun 28 05:58:27 PM PDT 24
Finished Jun 28 05:58:29 PM PDT 24
Peak memory 199900 kb
Host smart-4962d25d-a6f8-4745-8bdc-6836eadfcc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674762965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1674762965
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1863198371
Short name T502
Test name
Test status
Simulation time 763699542 ps
CPU time 3.9 seconds
Started Jun 28 05:58:13 PM PDT 24
Finished Jun 28 05:58:18 PM PDT 24
Peak memory 200288 kb
Host smart-0cfac56f-1a18-4402-aeba-bca05d3092d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863198371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1863198371
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3226966267
Short name T58
Test name
Test status
Simulation time 16515293245 ps
CPU time 26.41 seconds
Started Jun 28 05:58:14 PM PDT 24
Finished Jun 28 05:58:41 PM PDT 24
Peak memory 218188 kb
Host smart-792fb249-f3bd-472f-b079-5cc503ed7664
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226966267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3226966267
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1420445672
Short name T243
Test name
Test status
Simulation time 151958207 ps
CPU time 1.05 seconds
Started Jun 28 05:58:27 PM PDT 24
Finished Jun 28 05:58:29 PM PDT 24
Peak memory 200044 kb
Host smart-37210408-495f-4ec5-be7a-e0fbd8f01429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420445672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1420445672
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1873621930
Short name T397
Test name
Test status
Simulation time 109899646 ps
CPU time 1.21 seconds
Started Jun 28 05:58:10 PM PDT 24
Finished Jun 28 05:58:12 PM PDT 24
Peak memory 200260 kb
Host smart-2c774ad8-ed74-4690-bec6-f1cbfd442915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873621930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1873621930
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1459310940
Short name T214
Test name
Test status
Simulation time 420067778 ps
CPU time 1.84 seconds
Started Jun 28 05:58:13 PM PDT 24
Finished Jun 28 05:58:15 PM PDT 24
Peak memory 200220 kb
Host smart-dd6f6f1e-6763-4173-8ad4-f4e43e155637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459310940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1459310940
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.4076959276
Short name T493
Test name
Test status
Simulation time 149452585 ps
CPU time 2 seconds
Started Jun 28 05:58:26 PM PDT 24
Finished Jun 28 05:58:28 PM PDT 24
Peak memory 200088 kb
Host smart-34ee8142-4e6b-4a17-9c2a-c1c794d9f009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076959276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.4076959276
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3461243056
Short name T213
Test name
Test status
Simulation time 156163708 ps
CPU time 1.1 seconds
Started Jun 28 05:58:27 PM PDT 24
Finished Jun 28 05:58:29 PM PDT 24
Peak memory 200092 kb
Host smart-c7a9ced6-68a8-4641-8dda-fc87af5a3359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461243056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3461243056
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.4094085811
Short name T355
Test name
Test status
Simulation time 68117136 ps
CPU time 0.82 seconds
Started Jun 28 05:59:16 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 199880 kb
Host smart-7b94ad0c-fb5d-4fed-a59f-994310a815e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094085811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.4094085811
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.661312945
Short name T371
Test name
Test status
Simulation time 1216045638 ps
CPU time 5.57 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 217696 kb
Host smart-76a1032f-c3e2-43b0-8492-b3e5a6f6f4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661312945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.661312945
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2117509438
Short name T70
Test name
Test status
Simulation time 245368782 ps
CPU time 1.06 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 217448 kb
Host smart-ba68f55a-997d-4d66-80e2-2e11b97e5175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117509438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2117509438
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.835013902
Short name T369
Test name
Test status
Simulation time 80665193 ps
CPU time 0.75 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:21 PM PDT 24
Peak memory 199900 kb
Host smart-a521d504-2fcd-4cff-8676-5c0c949b94ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835013902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.835013902
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.739740069
Short name T506
Test name
Test status
Simulation time 998365156 ps
CPU time 4.84 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200268 kb
Host smart-12d70304-5712-4450-9246-79b9fff10e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739740069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.739740069
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4014016352
Short name T532
Test name
Test status
Simulation time 146118652 ps
CPU time 1.13 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200020 kb
Host smart-263d7adc-1096-4e4d-8557-c6c6448b12e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014016352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4014016352
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.4061789925
Short name T52
Test name
Test status
Simulation time 113775676 ps
CPU time 1.16 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200184 kb
Host smart-d1cbc4f3-f080-41a8-a7d1-a0c112de4ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061789925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.4061789925
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1702194825
Short name T87
Test name
Test status
Simulation time 8783512973 ps
CPU time 30.35 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 06:00:01 PM PDT 24
Peak memory 200412 kb
Host smart-64155ebf-2898-49df-a421-4f655cc31d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702194825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1702194825
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2489933002
Short name T410
Test name
Test status
Simulation time 134022199 ps
CPU time 1.66 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 200008 kb
Host smart-dd092df6-e782-4512-ab8c-657a250df69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489933002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2489933002
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1804574485
Short name T233
Test name
Test status
Simulation time 203689589 ps
CPU time 1.34 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200008 kb
Host smart-fbaaba1b-e95f-49d3-bb3a-eac3fb758a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804574485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1804574485
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1935894116
Short name T72
Test name
Test status
Simulation time 74529608 ps
CPU time 0.79 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 199712 kb
Host smart-7faf2dfc-9dc0-4bd0-94a9-a880e57827ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935894116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1935894116
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.389389017
Short name T450
Test name
Test status
Simulation time 243987853 ps
CPU time 1.07 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 217416 kb
Host smart-26691159-007c-40de-b59a-111eca4d332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389389017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.389389017
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3641063453
Short name T503
Test name
Test status
Simulation time 94036899 ps
CPU time 0.79 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 199904 kb
Host smart-e7a7534c-d84e-4858-9abf-e22643e87c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641063453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3641063453
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2094509944
Short name T115
Test name
Test status
Simulation time 1439677310 ps
CPU time 6.29 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200320 kb
Host smart-4c53b862-a5e6-48a1-8b4d-726208843028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094509944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2094509944
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1436543929
Short name T417
Test name
Test status
Simulation time 178037843 ps
CPU time 1.3 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200084 kb
Host smart-486ae55c-c9ac-40e9-ab98-6376c93e1922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436543929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1436543929
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.4236102429
Short name T198
Test name
Test status
Simulation time 261200700 ps
CPU time 1.6 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200280 kb
Host smart-49f89966-4583-4198-9ab9-8131acfa510d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236102429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.4236102429
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1382730447
Short name T256
Test name
Test status
Simulation time 7833252212 ps
CPU time 27.32 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 06:00:02 PM PDT 24
Peak memory 208616 kb
Host smart-faeae707-4799-409a-ad30-ca978555f056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382730447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1382730447
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.4180260751
Short name T481
Test name
Test status
Simulation time 150865449 ps
CPU time 1.77 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200084 kb
Host smart-bcda05e2-5111-4e4b-aed7-a6a0c5a501be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180260751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.4180260751
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2944300743
Short name T144
Test name
Test status
Simulation time 64859112 ps
CPU time 0.79 seconds
Started Jun 28 05:59:16 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 200100 kb
Host smart-9a8bed4a-386f-43b3-8b18-f012cf903275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944300743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2944300743
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1526620599
Short name T306
Test name
Test status
Simulation time 62864409 ps
CPU time 0.75 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:10 PM PDT 24
Peak memory 199888 kb
Host smart-ae86b1be-a3a1-419f-92bb-a94e29c4659a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526620599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1526620599
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2360424096
Short name T537
Test name
Test status
Simulation time 2343803005 ps
CPU time 7.97 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:46 PM PDT 24
Peak memory 217768 kb
Host smart-ec621826-7fa4-4cd1-8ea0-a3b1fb55a865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360424096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2360424096
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1414370781
Short name T490
Test name
Test status
Simulation time 244955249 ps
CPU time 1.08 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:09 PM PDT 24
Peak memory 217424 kb
Host smart-65e90f7d-921a-4926-9772-fd62284d486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414370781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1414370781
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1508778320
Short name T408
Test name
Test status
Simulation time 147730371 ps
CPU time 0.9 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 199872 kb
Host smart-fa9290f1-afe1-4bfe-9cb3-5647022144de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508778320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1508778320
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.4149622217
Short name T105
Test name
Test status
Simulation time 951824766 ps
CPU time 5.44 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 200208 kb
Host smart-f2097d6a-9224-4cbe-9181-246c21cd1005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149622217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.4149622217
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1164559361
Short name T489
Test name
Test status
Simulation time 183073794 ps
CPU time 1.22 seconds
Started Jun 28 05:59:18 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 200040 kb
Host smart-6af970a1-aad3-4316-87f1-2c3ae7fcf4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164559361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1164559361
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2475567785
Short name T288
Test name
Test status
Simulation time 124872005 ps
CPU time 1.2 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200244 kb
Host smart-51107969-edca-41e2-b4dd-11b197b45c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475567785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2475567785
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.802085642
Short name T139
Test name
Test status
Simulation time 1979883532 ps
CPU time 6.96 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:18 PM PDT 24
Peak memory 200312 kb
Host smart-6b88e355-f2d5-4bf9-92b4-ca2f1a0ccda5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802085642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.802085642
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3537814043
Short name T495
Test name
Test status
Simulation time 279542203 ps
CPU time 1.8 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200080 kb
Host smart-89cbb221-287b-42f8-92b3-3b8c8a400cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537814043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3537814043
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.64251057
Short name T224
Test name
Test status
Simulation time 194747755 ps
CPU time 1.29 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200092 kb
Host smart-7d4dea64-9bf7-4e97-90b7-2a4cfc6303e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64251057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.64251057
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1402207245
Short name T69
Test name
Test status
Simulation time 79499557 ps
CPU time 0.78 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:25 PM PDT 24
Peak memory 199880 kb
Host smart-9b672a75-5585-4a2a-9f0e-ce0566d9bbef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402207245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1402207245
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1119448047
Short name T485
Test name
Test status
Simulation time 1225917279 ps
CPU time 5.46 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:10 PM PDT 24
Peak memory 217720 kb
Host smart-642d827a-6cbd-4fa6-a686-b86298c3722b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119448047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1119448047
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.4252057258
Short name T357
Test name
Test status
Simulation time 245399341 ps
CPU time 1.12 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 217456 kb
Host smart-2d38087e-819e-4694-a4b6-e89130431391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252057258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.4252057258
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.253270735
Short name T365
Test name
Test status
Simulation time 101124398 ps
CPU time 0.78 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 199896 kb
Host smart-d816e603-01a0-4187-97a1-ebee9e3f1eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253270735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.253270735
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2833504253
Short name T453
Test name
Test status
Simulation time 1535831443 ps
CPU time 6.18 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:18 PM PDT 24
Peak memory 200360 kb
Host smart-21638aa1-f25d-4222-a746-fd9673b80b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833504253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2833504253
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3744123969
Short name T170
Test name
Test status
Simulation time 115453654 ps
CPU time 1.16 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:10 PM PDT 24
Peak memory 200368 kb
Host smart-193c1210-5194-4c31-a9ca-727dd12628c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744123969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3744123969
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3142316267
Short name T310
Test name
Test status
Simulation time 2117003720 ps
CPU time 9.99 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 208964 kb
Host smart-e0179a6d-8bb9-4782-9db7-cff6150ec874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142316267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3142316267
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2742396018
Short name T317
Test name
Test status
Simulation time 128111669 ps
CPU time 1.63 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:07 PM PDT 24
Peak memory 200128 kb
Host smart-fcd8bf3b-c286-45da-bdd2-7e261c956d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742396018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2742396018
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2171044562
Short name T195
Test name
Test status
Simulation time 234951807 ps
CPU time 1.45 seconds
Started Jun 28 05:59:07 PM PDT 24
Finished Jun 28 05:59:17 PM PDT 24
Peak memory 200224 kb
Host smart-ac4053a0-d85e-4fd0-8496-cbbb55e6c9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171044562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2171044562
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2855063502
Short name T428
Test name
Test status
Simulation time 101081908 ps
CPU time 0.84 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 199856 kb
Host smart-712b563f-b863-4c91-b8a6-18af64c189ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855063502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2855063502
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1869147851
Short name T486
Test name
Test status
Simulation time 1875748718 ps
CPU time 7.6 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 217356 kb
Host smart-dccc95f7-7a42-4e1d-89b9-068ddbb60415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869147851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1869147851
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3855570899
Short name T291
Test name
Test status
Simulation time 244911983 ps
CPU time 1.07 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 217628 kb
Host smart-c324b124-acba-4ad0-bfea-9d6afd1f0b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855570899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3855570899
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2833131843
Short name T526
Test name
Test status
Simulation time 210534240 ps
CPU time 0.89 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:25 PM PDT 24
Peak memory 199904 kb
Host smart-846f4db1-c7bb-4ba8-b2e4-ea6745117eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833131843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2833131843
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1511625486
Short name T108
Test name
Test status
Simulation time 866283195 ps
CPU time 4.02 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200344 kb
Host smart-d584d98c-afb3-42f2-858f-06d6f96990e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511625486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1511625486
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.4237389582
Short name T367
Test name
Test status
Simulation time 109323089 ps
CPU time 1.07 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 200256 kb
Host smart-bbd2be7f-3d4d-4e19-867a-b192ccb1fede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237389582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.4237389582
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.751445048
Short name T178
Test name
Test status
Simulation time 113531403 ps
CPU time 1.11 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:25 PM PDT 24
Peak memory 200324 kb
Host smart-83e43091-db64-4e86-9e00-8f54842e8148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751445048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.751445048
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3148654623
Short name T82
Test name
Test status
Simulation time 7942421675 ps
CPU time 32.45 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:58 PM PDT 24
Peak memory 200332 kb
Host smart-ffad7efc-b0ce-4927-bc63-80a99fd6760e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148654623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3148654623
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1578474967
Short name T338
Test name
Test status
Simulation time 364585067 ps
CPU time 2.31 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:22 PM PDT 24
Peak memory 200012 kb
Host smart-9b0eb115-5e1a-45f3-b4f5-14003728cf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578474967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1578474967
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1433478751
Short name T465
Test name
Test status
Simulation time 94244926 ps
CPU time 0.89 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 199848 kb
Host smart-72d7d22f-6040-44f0-8084-b86f8297c783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433478751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1433478751
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1912612482
Short name T25
Test name
Test status
Simulation time 2358957415 ps
CPU time 8.3 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 221608 kb
Host smart-f4722e4b-f624-4184-b5f2-7fcaa68769ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912612482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1912612482
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.4042752557
Short name T231
Test name
Test status
Simulation time 246700561 ps
CPU time 1.05 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 217336 kb
Host smart-828d0006-8a60-469d-b60e-9d8949300c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042752557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.4042752557
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3751314016
Short name T437
Test name
Test status
Simulation time 131236022 ps
CPU time 0.76 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 199836 kb
Host smart-7fa71561-42c3-4bdd-8639-c6790eab0ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751314016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3751314016
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.739276011
Short name T342
Test name
Test status
Simulation time 782364327 ps
CPU time 4.36 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 200340 kb
Host smart-875263b9-c0a5-4adb-9b13-9fe247d05c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739276011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.739276011
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.373132534
Short name T309
Test name
Test status
Simulation time 170993640 ps
CPU time 1.23 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 199988 kb
Host smart-904ce292-d2ba-44c7-93c0-fe4ae5d2d1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373132534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.373132534
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.4252930493
Short name T305
Test name
Test status
Simulation time 203242726 ps
CPU time 1.44 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200240 kb
Host smart-e3b75e35-ef0d-4e8f-a9ec-bd48b1dc212f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252930493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4252930493
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1607894039
Short name T238
Test name
Test status
Simulation time 1756249813 ps
CPU time 7.15 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:41 PM PDT 24
Peak memory 208528 kb
Host smart-fa5986a5-22da-405c-9625-6803a4176c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607894039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1607894039
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1870085847
Short name T427
Test name
Test status
Simulation time 252081529 ps
CPU time 1.77 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:26 PM PDT 24
Peak memory 200016 kb
Host smart-5d288dd8-d80a-4e3d-bdb2-4f926cdec6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870085847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1870085847
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2359199846
Short name T260
Test name
Test status
Simulation time 154364621 ps
CPU time 1.21 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200068 kb
Host smart-9228f9c9-3e7a-4c25-8222-163e562f4209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359199846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2359199846
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3457707943
Short name T431
Test name
Test status
Simulation time 68989220 ps
CPU time 0.8 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 199800 kb
Host smart-58fa26a4-a3c0-4653-9f97-a95c9664ab85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457707943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3457707943
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.434543588
Short name T23
Test name
Test status
Simulation time 1224504471 ps
CPU time 5.84 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 217456 kb
Host smart-97134dea-8433-4352-9ff4-a153b4a2510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434543588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.434543588
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.883612945
Short name T363
Test name
Test status
Simulation time 244625582 ps
CPU time 1.03 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 217188 kb
Host smart-723acc8b-62f0-459b-bb05-300434405820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883612945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.883612945
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.4081243659
Short name T406
Test name
Test status
Simulation time 178817272 ps
CPU time 0.9 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 199868 kb
Host smart-734b3763-93ec-41fe-9c68-08d03e617c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081243659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.4081243659
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2785357247
Short name T109
Test name
Test status
Simulation time 1411089600 ps
CPU time 6.29 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:36 PM PDT 24
Peak memory 200336 kb
Host smart-47518510-cd2e-4d9c-9d3c-0656e09fdb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785357247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2785357247
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3099461108
Short name T358
Test name
Test status
Simulation time 107531991 ps
CPU time 1.02 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 200084 kb
Host smart-ccbfc1e5-3e18-4d12-9b36-0ee9371ef18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099461108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3099461108
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1019608179
Short name T510
Test name
Test status
Simulation time 253613967 ps
CPU time 1.51 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200244 kb
Host smart-170d958d-18a6-46d8-a1cc-01e3b7d08c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019608179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1019608179
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2256244003
Short name T452
Test name
Test status
Simulation time 12336378647 ps
CPU time 42.21 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 06:00:16 PM PDT 24
Peak memory 208608 kb
Host smart-ef2a0fe7-5db2-4b7f-926b-d2d6837faa68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256244003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2256244003
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1068296424
Short name T225
Test name
Test status
Simulation time 343540503 ps
CPU time 2.09 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 199996 kb
Host smart-b7de17ba-16ad-403e-a88f-8f79d1f610da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068296424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1068296424
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.4134916811
Short name T385
Test name
Test status
Simulation time 147957281 ps
CPU time 1.1 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200036 kb
Host smart-61fdf6e6-6219-4d6c-84c0-181dbdd1db9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134916811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.4134916811
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2248577965
Short name T319
Test name
Test status
Simulation time 91198527 ps
CPU time 0.78 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 199824 kb
Host smart-74de9e71-910f-4a71-92b8-8b0e8225e0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248577965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2248577965
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3988860633
Short name T455
Test name
Test status
Simulation time 2372172732 ps
CPU time 7.92 seconds
Started Jun 28 05:59:16 PM PDT 24
Finished Jun 28 05:59:45 PM PDT 24
Peak memory 217736 kb
Host smart-5bc55908-58fb-4fde-bf4d-111e2f5ba6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988860633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3988860633
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.4089542321
Short name T341
Test name
Test status
Simulation time 244411143 ps
CPU time 1.07 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:22 PM PDT 24
Peak memory 217452 kb
Host smart-168d08d8-e3ab-4af0-aa20-3755b6612ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089542321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.4089542321
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3304017912
Short name T18
Test name
Test status
Simulation time 146113173 ps
CPU time 0.81 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 199872 kb
Host smart-7972cd9e-0c7a-418b-a42a-fed366c82e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304017912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3304017912
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2914747984
Short name T3
Test name
Test status
Simulation time 731237242 ps
CPU time 3.77 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 200208 kb
Host smart-e9fb2fac-800b-4457-8ce9-d4caa1583bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914747984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2914747984
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2822371358
Short name T523
Test name
Test status
Simulation time 179911715 ps
CPU time 1.17 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200084 kb
Host smart-42065ad8-9174-4935-a4cb-6366c8030cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822371358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2822371358
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1517310483
Short name T331
Test name
Test status
Simulation time 257564551 ps
CPU time 1.64 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:37 PM PDT 24
Peak memory 200248 kb
Host smart-58757a01-3024-4084-b1b6-3ea606dd86dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517310483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1517310483
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3962946064
Short name T333
Test name
Test status
Simulation time 5981454100 ps
CPU time 27.8 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:58 PM PDT 24
Peak memory 200408 kb
Host smart-975add58-8f91-4d2b-b39a-284972e382c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962946064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3962946064
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1559205809
Short name T484
Test name
Test status
Simulation time 148743257 ps
CPU time 1.79 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:37 PM PDT 24
Peak memory 200084 kb
Host smart-56919aac-0a4f-427c-aabf-a436f097a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559205809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1559205809
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.120147549
Short name T349
Test name
Test status
Simulation time 104333139 ps
CPU time 1.01 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 199984 kb
Host smart-99526ddd-4c5b-4102-a4c3-4ccef462b918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120147549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.120147549
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3118910666
Short name T311
Test name
Test status
Simulation time 74281952 ps
CPU time 0.8 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 199816 kb
Host smart-d77b55fc-db5d-4beb-90a6-d773c62ac5f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118910666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3118910666
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.488027897
Short name T22
Test name
Test status
Simulation time 1214823177 ps
CPU time 5.89 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:26 PM PDT 24
Peak memory 217476 kb
Host smart-4f93a785-4465-4f15-a07d-541fe02ba0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488027897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.488027897
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.248575671
Short name T155
Test name
Test status
Simulation time 243032781 ps
CPU time 1.08 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 217464 kb
Host smart-66288a33-17c5-4dad-bb8e-a4f48ba468e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248575671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.248575671
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1788145160
Short name T177
Test name
Test status
Simulation time 131707117 ps
CPU time 0.79 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:12 PM PDT 24
Peak memory 199892 kb
Host smart-d030f861-f039-41f1-9d18-720ac5184a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788145160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1788145160
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.407702658
Short name T387
Test name
Test status
Simulation time 1084840219 ps
CPU time 4.58 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:17 PM PDT 24
Peak memory 200348 kb
Host smart-6c81528c-cb14-4dd0-99fd-9f697a58656b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407702658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.407702658
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2549823417
Short name T267
Test name
Test status
Simulation time 141314649 ps
CPU time 1.18 seconds
Started Jun 28 05:59:07 PM PDT 24
Finished Jun 28 05:59:18 PM PDT 24
Peak memory 200204 kb
Host smart-2a23e05f-3336-43e4-9afe-800b59560b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549823417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2549823417
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1067223981
Short name T423
Test name
Test status
Simulation time 191198797 ps
CPU time 1.36 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:13 PM PDT 24
Peak memory 200260 kb
Host smart-67669d2a-438b-435d-9630-362d4b1171de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067223981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1067223981
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2057828237
Short name T193
Test name
Test status
Simulation time 3098508429 ps
CPU time 13.46 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200408 kb
Host smart-e51df56a-ad42-46a8-aa2a-11bd24e4004e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057828237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2057828237
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.5759233
Short name T346
Test name
Test status
Simulation time 282698756 ps
CPU time 1.79 seconds
Started Jun 28 05:59:07 PM PDT 24
Finished Jun 28 05:59:18 PM PDT 24
Peak memory 200104 kb
Host smart-62115239-b9ef-4238-ba63-15bca81b95c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5759233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.5759233
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1956575114
Short name T425
Test name
Test status
Simulation time 211407339 ps
CPU time 1.44 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 200092 kb
Host smart-abeb4cfa-38f6-4239-a4b5-6d835b6fe40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956575114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1956575114
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1059205716
Short name T392
Test name
Test status
Simulation time 89818697 ps
CPU time 0.81 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 199812 kb
Host smart-27986b16-b0a4-4a5e-8727-b1c43c62fd86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059205716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1059205716
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2574842303
Short name T226
Test name
Test status
Simulation time 1904416672 ps
CPU time 7.75 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:41 PM PDT 24
Peak memory 217228 kb
Host smart-17977bd4-a255-4f4e-9ebf-ad32469186be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574842303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2574842303
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1910481306
Short name T420
Test name
Test status
Simulation time 244874557 ps
CPU time 1.2 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 217400 kb
Host smart-1c7be851-bf35-4dc1-9355-6a9e2e478c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910481306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1910481306
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.220312652
Short name T328
Test name
Test status
Simulation time 187693083 ps
CPU time 0.85 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:20 PM PDT 24
Peak memory 199900 kb
Host smart-5bb78430-19ad-408e-a88d-5641b31f1fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220312652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.220312652
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1637301026
Short name T207
Test name
Test status
Simulation time 729780598 ps
CPU time 3.84 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 200216 kb
Host smart-6f9fcafa-c6b9-4b50-8009-ae7be53a8492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637301026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1637301026
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2119324427
Short name T376
Test name
Test status
Simulation time 176657598 ps
CPU time 1.27 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:25 PM PDT 24
Peak memory 200012 kb
Host smart-5e97e549-070f-480a-bb76-a0829a802738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119324427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2119324427
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2533286350
Short name T184
Test name
Test status
Simulation time 197985767 ps
CPU time 1.47 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200276 kb
Host smart-d6ecfbc1-5d94-45d4-98d8-7ed16c71441d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533286350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2533286350
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.82745647
Short name T511
Test name
Test status
Simulation time 9411348600 ps
CPU time 35.89 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 06:00:07 PM PDT 24
Peak memory 208644 kb
Host smart-8863c28e-5baa-40cf-9fcd-8d230b4f62a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82745647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.82745647
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1234812208
Short name T402
Test name
Test status
Simulation time 138690605 ps
CPU time 1.69 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 208148 kb
Host smart-04b6f683-8cf9-41cf-9d59-0c127c054b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234812208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1234812208
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2666957727
Short name T229
Test name
Test status
Simulation time 152491934 ps
CPU time 1.26 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 200100 kb
Host smart-8b1ad73c-a6e5-47c9-9778-a3c35a5861ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666957727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2666957727
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3149969556
Short name T158
Test name
Test status
Simulation time 71206553 ps
CPU time 0.75 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:10 PM PDT 24
Peak memory 200000 kb
Host smart-1da752a2-1d85-4d68-a814-24c805891caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149969556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3149969556
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3802606654
Short name T390
Test name
Test status
Simulation time 245200350 ps
CPU time 1.17 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:06 PM PDT 24
Peak memory 217452 kb
Host smart-8e84af16-66fa-427a-ba41-ce93b8c6aebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802606654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3802606654
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3836354232
Short name T518
Test name
Test status
Simulation time 192780793 ps
CPU time 0.93 seconds
Started Jun 28 05:58:26 PM PDT 24
Finished Jun 28 05:58:28 PM PDT 24
Peak memory 199900 kb
Host smart-64836c59-4de0-4a9d-a703-ab06357e5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836354232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3836354232
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3281856116
Short name T295
Test name
Test status
Simulation time 1872578703 ps
CPU time 6.27 seconds
Started Jun 28 05:58:27 PM PDT 24
Finished Jun 28 05:58:34 PM PDT 24
Peak memory 200340 kb
Host smart-659d9cf0-cef3-4aab-a8bd-ef406e1e7f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281856116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3281856116
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2391244833
Short name T57
Test name
Test status
Simulation time 8273756306 ps
CPU time 15.16 seconds
Started Jun 28 05:59:16 PM PDT 24
Finished Jun 28 05:59:52 PM PDT 24
Peak memory 217180 kb
Host smart-308ba3f8-faa9-4dfd-9f3e-363d33b3e8b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391244833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2391244833
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3371601464
Short name T382
Test name
Test status
Simulation time 140326688 ps
CPU time 1.14 seconds
Started Jun 28 05:58:14 PM PDT 24
Finished Jun 28 05:58:15 PM PDT 24
Peak memory 200036 kb
Host smart-0554610e-74b8-4bc3-b542-158215d482af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371601464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3371601464
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3460245562
Short name T202
Test name
Test status
Simulation time 243786131 ps
CPU time 1.55 seconds
Started Jun 28 05:58:10 PM PDT 24
Finished Jun 28 05:58:13 PM PDT 24
Peak memory 200272 kb
Host smart-d1275ef0-494b-41c9-a600-7fb8ec9f0e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460245562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3460245562
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2115945598
Short name T322
Test name
Test status
Simulation time 146122179 ps
CPU time 1.88 seconds
Started Jun 28 05:58:28 PM PDT 24
Finished Jun 28 05:58:31 PM PDT 24
Peak memory 200080 kb
Host smart-650dd1cb-2876-45e2-a0ec-7b4a0f5da3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115945598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2115945598
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1464125375
Short name T185
Test name
Test status
Simulation time 163485098 ps
CPU time 1.22 seconds
Started Jun 28 05:58:21 PM PDT 24
Finished Jun 28 05:58:23 PM PDT 24
Peak memory 200092 kb
Host smart-a5719a29-d408-4f8a-8d30-6b460b7dcd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464125375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1464125375
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1499721671
Short name T161
Test name
Test status
Simulation time 108279181 ps
CPU time 0.86 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 199884 kb
Host smart-b4b4cf04-5d35-4e5e-b248-c115270ccf48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499721671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1499721671
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.280642250
Short name T38
Test name
Test status
Simulation time 1888130271 ps
CPU time 7.68 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:37 PM PDT 24
Peak memory 217676 kb
Host smart-05ebf084-7034-4734-9e95-4f3d32f37dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280642250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.280642250
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3735506642
Short name T419
Test name
Test status
Simulation time 245079783 ps
CPU time 1.01 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 217452 kb
Host smart-9be9b42b-4681-4530-abbb-3120bafbd53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735506642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3735506642
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2108833792
Short name T313
Test name
Test status
Simulation time 96286183 ps
CPU time 0.78 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 199660 kb
Host smart-838e2f09-4eb1-4814-b2f5-5c0b3668f751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108833792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2108833792
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2172293319
Short name T1
Test name
Test status
Simulation time 1715793472 ps
CPU time 5.79 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:41 PM PDT 24
Peak memory 200284 kb
Host smart-8e312648-3ea5-4f6e-9bd1-faac54f77178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172293319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2172293319
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2723841682
Short name T271
Test name
Test status
Simulation time 111072639 ps
CPU time 1.07 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 199972 kb
Host smart-d3ef9233-3330-4ba4-8eb1-0c3b494a8f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723841682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2723841682
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1829455268
Short name T201
Test name
Test status
Simulation time 224151896 ps
CPU time 1.36 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200208 kb
Host smart-821e05a8-a647-4132-9a7f-e594d5746268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829455268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1829455268
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1613367019
Short name T403
Test name
Test status
Simulation time 1903972368 ps
CPU time 7.52 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 200344 kb
Host smart-a5f3d37a-1d31-4558-847b-4883296bc8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613367019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1613367019
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1763263961
Short name T71
Test name
Test status
Simulation time 383983673 ps
CPU time 2.28 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:37 PM PDT 24
Peak memory 208300 kb
Host smart-e8001b36-0202-45b8-aba4-311ae29d949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763263961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1763263961
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.959215042
Short name T375
Test name
Test status
Simulation time 124356935 ps
CPU time 0.95 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 200092 kb
Host smart-49ffc6f0-94a9-4fd6-a020-1d875ed75da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959215042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.959215042
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.438367327
Short name T112
Test name
Test status
Simulation time 69947734 ps
CPU time 0.76 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:36 PM PDT 24
Peak memory 199876 kb
Host smart-30d9d803-b8c7-43a7-8983-397a8bb38010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438367327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.438367327
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.4205565872
Short name T276
Test name
Test status
Simulation time 2367847472 ps
CPU time 8.24 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:42 PM PDT 24
Peak memory 217896 kb
Host smart-e916ea0b-d4f0-4b6f-b934-88deb753538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205565872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.4205565872
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3174614336
Short name T433
Test name
Test status
Simulation time 245077451 ps
CPU time 1.07 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 217448 kb
Host smart-01c87530-6082-4d9f-ba77-bb89ca27b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174614336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3174614336
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.714201257
Short name T405
Test name
Test status
Simulation time 200524553 ps
CPU time 0.84 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 199884 kb
Host smart-7379e52d-ee3b-4956-a233-88d35bb1692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714201257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.714201257
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3780405725
Short name T383
Test name
Test status
Simulation time 872911993 ps
CPU time 4.5 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:37 PM PDT 24
Peak memory 200344 kb
Host smart-bd422d7b-955e-455d-a0b3-581f87bc9587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780405725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3780405725
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3114895275
Short name T215
Test name
Test status
Simulation time 176988885 ps
CPU time 1.34 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200004 kb
Host smart-d2cfbb7b-5ef4-44a6-83cf-1a389e496426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114895275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3114895275
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1290553081
Short name T146
Test name
Test status
Simulation time 246148463 ps
CPU time 1.45 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 200248 kb
Host smart-406d48b9-2e9f-421e-9ac2-3fb2248bfbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290553081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1290553081
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1895351245
Short name T137
Test name
Test status
Simulation time 2468883983 ps
CPU time 8.74 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:44 PM PDT 24
Peak memory 208652 kb
Host smart-3b1f0e9a-0b85-4faf-a6aa-96fb7ccd4591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895351245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1895351245
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.659363127
Short name T290
Test name
Test status
Simulation time 460746606 ps
CPU time 2.36 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 200088 kb
Host smart-6649859c-1eaa-4681-9f52-7ffd02b2279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659363127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.659363127
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2421712144
Short name T285
Test name
Test status
Simulation time 247493048 ps
CPU time 1.43 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 199772 kb
Host smart-26a8be18-7fd7-4597-abfe-12360b53da24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421712144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2421712144
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2599102935
Short name T444
Test name
Test status
Simulation time 68245033 ps
CPU time 0.75 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:20 PM PDT 24
Peak memory 199888 kb
Host smart-f53cd307-993a-4713-bb00-601831eab07c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599102935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2599102935
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3745820207
Short name T35
Test name
Test status
Simulation time 1896261295 ps
CPU time 7.17 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 217804 kb
Host smart-46676d85-9d39-4fdd-afd0-60d72bbe323f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745820207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3745820207
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1433514236
Short name T488
Test name
Test status
Simulation time 243996224 ps
CPU time 1.07 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:31 PM PDT 24
Peak memory 217392 kb
Host smart-d5948151-60f5-418b-92c6-6d4fd1a7dc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433514236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1433514236
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2168352268
Short name T16
Test name
Test status
Simulation time 220276882 ps
CPU time 0.91 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 199140 kb
Host smart-5ebd6c77-da87-432a-ac31-5871842f459c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168352268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2168352268
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1802171817
Short name T106
Test name
Test status
Simulation time 1781677690 ps
CPU time 6.87 seconds
Started Jun 28 05:59:18 PM PDT 24
Finished Jun 28 05:59:45 PM PDT 24
Peak memory 200328 kb
Host smart-c829e90c-5865-4a43-91d5-2dcf97d69714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802171817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1802171817
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1153717164
Short name T335
Test name
Test status
Simulation time 169989316 ps
CPU time 1.16 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 200088 kb
Host smart-aa35f891-70c9-4579-a362-a53111f3ca94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153717164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1153717164
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.201478364
Short name T314
Test name
Test status
Simulation time 114580086 ps
CPU time 1.12 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:36 PM PDT 24
Peak memory 200276 kb
Host smart-e070097d-7437-448f-b859-fc7dbeb8d904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201478364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.201478364
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3712372226
Short name T344
Test name
Test status
Simulation time 8652775794 ps
CPU time 30.82 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:43 PM PDT 24
Peak memory 208596 kb
Host smart-d38810eb-599d-4f11-b207-ea11ea7653b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712372226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3712372226
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1863703633
Short name T519
Test name
Test status
Simulation time 476663449 ps
CPU time 2.69 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:41 PM PDT 24
Peak memory 200068 kb
Host smart-26b72290-6378-45b1-a700-91d96a17f64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863703633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1863703633
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1903018970
Short name T149
Test name
Test status
Simulation time 120279627 ps
CPU time 1.03 seconds
Started Jun 28 05:59:16 PM PDT 24
Finished Jun 28 05:59:37 PM PDT 24
Peak memory 200100 kb
Host smart-7a31da1e-cf33-4bec-911b-5d4396b8c063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903018970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1903018970
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.572049865
Short name T208
Test name
Test status
Simulation time 92649446 ps
CPU time 0.83 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 199876 kb
Host smart-c426191e-d994-456c-949a-8ffc466f675a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572049865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.572049865
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.276159839
Short name T26
Test name
Test status
Simulation time 1901830095 ps
CPU time 6.86 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:31 PM PDT 24
Peak memory 221632 kb
Host smart-332f56bc-5684-41c3-970b-7327109f9f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276159839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.276159839
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.566979002
Short name T164
Test name
Test status
Simulation time 243902003 ps
CPU time 1.09 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 217456 kb
Host smart-9e8150e8-e280-48f9-b88c-c51148f0cb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566979002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.566979002
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1110861172
Short name T536
Test name
Test status
Simulation time 193912293 ps
CPU time 0.9 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:10 PM PDT 24
Peak memory 199908 kb
Host smart-618d0f1f-d823-45a1-9de3-dcae916a384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110861172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1110861172
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2341727131
Short name T104
Test name
Test status
Simulation time 951837723 ps
CPU time 4.82 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:14 PM PDT 24
Peak memory 200340 kb
Host smart-9ef7b14f-ea2e-4eb4-913f-414dafdb7e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341727131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2341727131
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.596048811
Short name T436
Test name
Test status
Simulation time 151193164 ps
CPU time 1.12 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:12 PM PDT 24
Peak memory 200096 kb
Host smart-da2ceb36-a16e-4da5-b053-a1f1648eee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596048811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.596048811
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.682925992
Short name T337
Test name
Test status
Simulation time 195732626 ps
CPU time 1.35 seconds
Started Jun 28 05:59:07 PM PDT 24
Finished Jun 28 05:59:18 PM PDT 24
Peak memory 200276 kb
Host smart-ae6b0a49-8044-4b60-ae60-36db94c26a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682925992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.682925992
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.993884118
Short name T348
Test name
Test status
Simulation time 2545060777 ps
CPU time 12.65 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:36 PM PDT 24
Peak memory 200420 kb
Host smart-074cf77c-f301-4aee-939e-b8be3382b599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993884118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.993884118
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.114472002
Short name T301
Test name
Test status
Simulation time 549042107 ps
CPU time 3.08 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:14 PM PDT 24
Peak memory 200072 kb
Host smart-4bb66df6-2243-4c78-a156-c3f18b2b32cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114472002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.114472002
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1001802201
Short name T516
Test name
Test status
Simulation time 261817702 ps
CPU time 1.47 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:14 PM PDT 24
Peak memory 200200 kb
Host smart-9c36617a-3a8e-4785-8f39-f40357084094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001802201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1001802201
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.4064534983
Short name T156
Test name
Test status
Simulation time 69275258 ps
CPU time 0.73 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 199860 kb
Host smart-f0deed44-9372-4eb2-ac01-93fd8739f05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064534983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.4064534983
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1807712790
Short name T514
Test name
Test status
Simulation time 1900787961 ps
CPU time 7.4 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:41 PM PDT 24
Peak memory 217576 kb
Host smart-3b45d13c-c32c-4361-8907-4b978f3d493e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807712790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1807712790
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2055619976
Short name T541
Test name
Test status
Simulation time 244703875 ps
CPU time 1.01 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 217400 kb
Host smart-aa74465f-d65f-4b56-858a-282b17dee215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055619976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2055619976
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3435884685
Short name T302
Test name
Test status
Simulation time 81730777 ps
CPU time 0.77 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 199804 kb
Host smart-c69628da-616b-4c48-8410-21f5e4945558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435884685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3435884685
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3366117682
Short name T176
Test name
Test status
Simulation time 1256217278 ps
CPU time 5.23 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 200248 kb
Host smart-acec3548-ecdb-4197-8f20-01c4cf064e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366117682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3366117682
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.152868462
Short name T478
Test name
Test status
Simulation time 172480787 ps
CPU time 1.17 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200252 kb
Host smart-a548ced8-b665-4c02-a449-0ea49eb83a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152868462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.152868462
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3055146357
Short name T446
Test name
Test status
Simulation time 112122502 ps
CPU time 1.15 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 200296 kb
Host smart-aca05099-b5da-4ea3-8116-2efb594d3922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055146357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3055146357
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2353973275
Short name T239
Test name
Test status
Simulation time 2056496785 ps
CPU time 8.41 seconds
Started Jun 28 05:59:02 PM PDT 24
Finished Jun 28 05:59:11 PM PDT 24
Peak memory 200548 kb
Host smart-7808ac88-ad7e-4928-8eb6-1945a9969ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353973275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2353973275
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.991553444
Short name T345
Test name
Test status
Simulation time 388874128 ps
CPU time 2.76 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 200100 kb
Host smart-76aa116c-08de-4251-ace9-41d0a6baf041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991553444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.991553444
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.273917392
Short name T517
Test name
Test status
Simulation time 222624102 ps
CPU time 1.27 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:25 PM PDT 24
Peak memory 200088 kb
Host smart-5b2ed13d-2be5-4443-8270-f4623c718861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273917392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.273917392
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2356836297
Short name T499
Test name
Test status
Simulation time 58150597 ps
CPU time 0.78 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 199748 kb
Host smart-5153e85f-3936-4573-9109-addbf557abe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356836297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2356836297
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.4133469950
Short name T491
Test name
Test status
Simulation time 1917126748 ps
CPU time 7.33 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 217388 kb
Host smart-2403f48d-4c02-4796-a46c-ae05437bcad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133469950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.4133469950
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.999498065
Short name T183
Test name
Test status
Simulation time 244773459 ps
CPU time 1.05 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 217452 kb
Host smart-0e1c5773-a88a-4d87-8b88-d03e97e4bf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999498065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.999498065
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3313492392
Short name T236
Test name
Test status
Simulation time 101484966 ps
CPU time 0.78 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 199524 kb
Host smart-59639c7a-9537-42ab-ad05-307e617bff78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313492392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3313492392
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3470602903
Short name T180
Test name
Test status
Simulation time 856618669 ps
CPU time 4.19 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 200320 kb
Host smart-54f80280-192c-480f-9444-b350ba8e7027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470602903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3470602903
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.105515456
Short name T162
Test name
Test status
Simulation time 114624042 ps
CPU time 1 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200060 kb
Host smart-f9d457cc-ff34-472f-9268-328022406c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105515456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.105515456
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3735038428
Short name T254
Test name
Test status
Simulation time 188529663 ps
CPU time 1.31 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200252 kb
Host smart-13b45903-91a4-4a11-995a-b4000e52449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735038428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3735038428
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2672650323
Short name T475
Test name
Test status
Simulation time 1646462648 ps
CPU time 6.35 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 200344 kb
Host smart-284b1c31-6153-4997-886e-59467b0d45fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672650323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2672650323
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.812147236
Short name T477
Test name
Test status
Simulation time 110698933 ps
CPU time 1.39 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 200088 kb
Host smart-65ff38ec-e856-4594-ad7f-ab24b58f61a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812147236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.812147236
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1929588781
Short name T80
Test name
Test status
Simulation time 80992764 ps
CPU time 0.93 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:36 PM PDT 24
Peak memory 200092 kb
Host smart-791cfa46-05a6-4e06-a9e5-74ffb60fca53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929588781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1929588781
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3525530838
Short name T154
Test name
Test status
Simulation time 70190629 ps
CPU time 0.77 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:36 PM PDT 24
Peak memory 199884 kb
Host smart-aeca0db0-8738-48c7-832b-65228d4abed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525530838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3525530838
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.311066577
Short name T263
Test name
Test status
Simulation time 1895495859 ps
CPU time 7.35 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:42 PM PDT 24
Peak memory 221584 kb
Host smart-cb78e2bc-30b7-440c-b8d0-87b97dd96832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311066577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.311066577
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1450570368
Short name T181
Test name
Test status
Simulation time 244575996 ps
CPU time 1.06 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 217452 kb
Host smart-2b13dc35-3974-45df-8b9b-7966355421a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450570368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1450570368
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.725957591
Short name T409
Test name
Test status
Simulation time 100993265 ps
CPU time 0.75 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 199896 kb
Host smart-0089c2d1-e65d-428c-aba4-bdcebc6b35f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725957591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.725957591
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.207022276
Short name T439
Test name
Test status
Simulation time 899375179 ps
CPU time 4.18 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 200356 kb
Host smart-1672519a-026e-4ade-b2a9-4fa744cd8b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207022276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.207022276
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2590895163
Short name T379
Test name
Test status
Simulation time 113830805 ps
CPU time 1.12 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:36 PM PDT 24
Peak memory 200072 kb
Host smart-8d9be4db-4791-4c3f-8c61-af4ed62ef84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590895163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2590895163
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.278994825
Short name T336
Test name
Test status
Simulation time 118108464 ps
CPU time 1.23 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200240 kb
Host smart-6b30ccc0-64f6-4989-a2dd-74c3799934fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278994825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.278994825
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2694588161
Short name T359
Test name
Test status
Simulation time 4808314207 ps
CPU time 20.9 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:56 PM PDT 24
Peak memory 200252 kb
Host smart-add0626e-7acd-4a5c-b17e-d6756caf883c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694588161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2694588161
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3205962950
Short name T389
Test name
Test status
Simulation time 119358163 ps
CPU time 1.59 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 207992 kb
Host smart-e8fbff01-5741-4f0b-83ee-3e6009424175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205962950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3205962950
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3599409471
Short name T466
Test name
Test status
Simulation time 159749452 ps
CPU time 1.12 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 199900 kb
Host smart-546a6138-7dbe-46c7-bb13-f42b421a7860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599409471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3599409471
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1012435909
Short name T31
Test name
Test status
Simulation time 60455150 ps
CPU time 0.74 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:21 PM PDT 24
Peak memory 199748 kb
Host smart-21fd7b31-8583-4aa5-9482-ffdc3b2bdb78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012435909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1012435909
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.648217077
Short name T33
Test name
Test status
Simulation time 2177297210 ps
CPU time 7.93 seconds
Started Jun 28 05:59:16 PM PDT 24
Finished Jun 28 05:59:45 PM PDT 24
Peak memory 216900 kb
Host smart-e633e29e-70eb-445b-963b-21caff6c32b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648217077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.648217077
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.144234643
Short name T232
Test name
Test status
Simulation time 246403770 ps
CPU time 1.07 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:13 PM PDT 24
Peak memory 217440 kb
Host smart-1573d341-4d08-476f-8fbf-6e32a870c815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144234643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.144234643
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2785060118
Short name T274
Test name
Test status
Simulation time 215457426 ps
CPU time 0.98 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:36 PM PDT 24
Peak memory 199900 kb
Host smart-7b842d6f-b59f-4b88-b4ab-e8667d798da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785060118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2785060118
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1697116212
Short name T73
Test name
Test status
Simulation time 1825543904 ps
CPU time 6.37 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 200336 kb
Host smart-80457436-cb59-44fb-9eaf-883ebbdb768c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697116212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1697116212
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.548209368
Short name T222
Test name
Test status
Simulation time 151650192 ps
CPU time 1.12 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 200100 kb
Host smart-872c96d7-dd6e-486b-abdd-b9f51e9b608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548209368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.548209368
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2692087799
Short name T142
Test name
Test status
Simulation time 241401328 ps
CPU time 1.63 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:36 PM PDT 24
Peak memory 200248 kb
Host smart-1b553566-0d3f-4943-8951-e6e005b207a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692087799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2692087799
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1726845544
Short name T464
Test name
Test status
Simulation time 503954490 ps
CPU time 3.21 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:26 PM PDT 24
Peak memory 200276 kb
Host smart-f2d86511-acf6-4da1-82c3-dee6fc853466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726845544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1726845544
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.164133965
Short name T212
Test name
Test status
Simulation time 448119869 ps
CPU time 2.48 seconds
Started Jun 28 05:59:16 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 200028 kb
Host smart-de7d4d86-91b2-4eab-abff-33fddd7a4183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164133965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.164133965
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.4018267699
Short name T192
Test name
Test status
Simulation time 137246686 ps
CPU time 1.15 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:09 PM PDT 24
Peak memory 200100 kb
Host smart-00f4a240-13e9-43a7-9615-2d3b53cd58a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018267699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.4018267699
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1783867484
Short name T182
Test name
Test status
Simulation time 64117611 ps
CPU time 0.78 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 199884 kb
Host smart-3384144c-7f9b-40aa-9dfe-3d17a53451f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783867484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1783867484
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3536045633
Short name T221
Test name
Test status
Simulation time 2362708923 ps
CPU time 7.88 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:26 PM PDT 24
Peak memory 217764 kb
Host smart-c2a75f8c-f3f5-457e-a8e5-0aaf75dc2314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536045633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3536045633
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1157705881
Short name T169
Test name
Test status
Simulation time 244874475 ps
CPU time 1.08 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:21 PM PDT 24
Peak memory 217448 kb
Host smart-a90e2c62-da76-4b19-9283-6145c9ee2d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157705881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1157705881
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1881311369
Short name T424
Test name
Test status
Simulation time 234231710 ps
CPU time 0.91 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:20 PM PDT 24
Peak memory 199904 kb
Host smart-8dc46867-d94d-4fa8-be7e-7735bd547366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881311369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1881311369
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2442946651
Short name T277
Test name
Test status
Simulation time 1491506807 ps
CPU time 6.25 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:17 PM PDT 24
Peak memory 200376 kb
Host smart-aec3a05d-ac27-42f0-987a-7d51bf85f66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442946651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2442946651
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2780009141
Short name T426
Test name
Test status
Simulation time 103366137 ps
CPU time 1.02 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:15 PM PDT 24
Peak memory 200072 kb
Host smart-1690b04d-0b16-4f91-a40f-056d4b881895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780009141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2780009141
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1520493471
Short name T505
Test name
Test status
Simulation time 114951950 ps
CPU time 1.17 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:22 PM PDT 24
Peak memory 200208 kb
Host smart-a273b1b1-671f-40f9-8d52-33f0b39aa856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520493471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1520493471
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.759504837
Short name T539
Test name
Test status
Simulation time 2742925087 ps
CPU time 10.32 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:33 PM PDT 24
Peak memory 208604 kb
Host smart-2a161035-2c90-4fc3-a8a8-20215d78a12d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759504837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.759504837
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2730784652
Short name T497
Test name
Test status
Simulation time 119569596 ps
CPU time 1.6 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:13 PM PDT 24
Peak memory 200120 kb
Host smart-82779bed-07cf-428b-8058-a4891107273e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730784652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2730784652
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.4185930776
Short name T143
Test name
Test status
Simulation time 75409316 ps
CPU time 0.81 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 200012 kb
Host smart-74cf55fb-7d9d-438d-8c0d-e9bb6540d208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185930776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.4185930776
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.273331303
Short name T304
Test name
Test status
Simulation time 56114324 ps
CPU time 0.74 seconds
Started Jun 28 05:58:38 PM PDT 24
Finished Jun 28 05:58:40 PM PDT 24
Peak memory 199876 kb
Host smart-738e5190-3d31-4611-bc4d-66a931663662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273331303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.273331303
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.81007500
Short name T509
Test name
Test status
Simulation time 1900998922 ps
CPU time 7.61 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 217652 kb
Host smart-db7d562c-69e8-47a4-ac1e-4334c846ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81007500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.81007500
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2530397032
Short name T334
Test name
Test status
Simulation time 244790687 ps
CPU time 1.12 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 217448 kb
Host smart-dd73e7aa-7be7-4da3-a5e0-24d26ab0505a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530397032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2530397032
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3577110340
Short name T364
Test name
Test status
Simulation time 86573267 ps
CPU time 0.77 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 199808 kb
Host smart-e655fcc6-7671-4ef5-a0b9-a244ea59cd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577110340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3577110340
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.4222454654
Short name T127
Test name
Test status
Simulation time 1307632807 ps
CPU time 5.42 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 200344 kb
Host smart-2eda5164-8766-48af-8363-1314afc788bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222454654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.4222454654
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3727830222
Short name T483
Test name
Test status
Simulation time 162438907 ps
CPU time 1.11 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 200092 kb
Host smart-d9c20a58-a9cc-4059-8e79-7bc2d6fa902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727830222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3727830222
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.614094470
Short name T487
Test name
Test status
Simulation time 122236567 ps
CPU time 1.25 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200184 kb
Host smart-8bd20b9d-d9e8-476b-8d9e-e6f83ddbf922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614094470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.614094470
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1535399246
Short name T297
Test name
Test status
Simulation time 3271547969 ps
CPU time 14.59 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:41 PM PDT 24
Peak memory 200328 kb
Host smart-b7cbd804-9674-4bae-8c82-0cca912abf12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535399246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1535399246
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1905138386
Short name T205
Test name
Test status
Simulation time 314326841 ps
CPU time 2.3 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 200308 kb
Host smart-97f079e5-bf08-4241-85b1-7d3fc59ed44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905138386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1905138386
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3616368867
Short name T65
Test name
Test status
Simulation time 278125068 ps
CPU time 1.47 seconds
Started Jun 28 05:59:16 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 199932 kb
Host smart-d28a4b90-7f3d-4f5a-929e-8a6c5decc416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616368867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3616368867
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3695304797
Short name T418
Test name
Test status
Simulation time 61457550 ps
CPU time 0.75 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:06 PM PDT 24
Peak memory 199924 kb
Host smart-8c9fd98e-7523-46a4-b400-dde02fea631d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695304797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3695304797
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.58688818
Short name T10
Test name
Test status
Simulation time 1891844671 ps
CPU time 7.66 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:16 PM PDT 24
Peak memory 221600 kb
Host smart-fc9d159d-5f20-4753-9676-b354dde6bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58688818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.58688818
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3454110644
Short name T186
Test name
Test status
Simulation time 244282132 ps
CPU time 1.1 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:12 PM PDT 24
Peak memory 217380 kb
Host smart-2aa9e072-1c08-4825-aa91-df75e4acbbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454110644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3454110644
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1428895082
Short name T404
Test name
Test status
Simulation time 149494136 ps
CPU time 0.85 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:10 PM PDT 24
Peak memory 199900 kb
Host smart-503b8777-865b-4861-8aa5-aa78fbca3755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428895082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1428895082
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2393150505
Short name T315
Test name
Test status
Simulation time 2193724118 ps
CPU time 7.79 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:17 PM PDT 24
Peak memory 200452 kb
Host smart-92010b8e-c852-4f0c-8442-07f4c523d151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393150505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2393150505
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3238379335
Short name T59
Test name
Test status
Simulation time 8427939866 ps
CPU time 12.56 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:29 PM PDT 24
Peak memory 217168 kb
Host smart-ad531544-6fac-47b4-bf12-75e7b2e5bc5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238379335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3238379335
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2338107037
Short name T421
Test name
Test status
Simulation time 144530216 ps
CPU time 1.16 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:07 PM PDT 24
Peak memory 200092 kb
Host smart-5167bb16-6052-48d1-b4af-4b149169d13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338107037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2338107037
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1666382767
Short name T81
Test name
Test status
Simulation time 108864032 ps
CPU time 1.16 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:12 PM PDT 24
Peak memory 200280 kb
Host smart-765efa1c-de3d-4466-97ed-0c30dccca0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666382767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1666382767
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.271676700
Short name T329
Test name
Test status
Simulation time 108237705 ps
CPU time 1.15 seconds
Started Jun 28 05:58:58 PM PDT 24
Finished Jun 28 05:59:00 PM PDT 24
Peak memory 199860 kb
Host smart-da97f4ca-92d0-4fcd-84e6-77fd7bbc673f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271676700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.271676700
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1564083311
Short name T303
Test name
Test status
Simulation time 95203489 ps
CPU time 0.87 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 200088 kb
Host smart-d381a82d-c50c-41ee-a95f-7e27c8471e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564083311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1564083311
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1313539846
Short name T381
Test name
Test status
Simulation time 79731542 ps
CPU time 0.82 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 199872 kb
Host smart-e1bba319-a17f-4212-9792-4018b58a708a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313539846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1313539846
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2960190008
Short name T43
Test name
Test status
Simulation time 1879536584 ps
CPU time 7.69 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:41 PM PDT 24
Peak memory 221592 kb
Host smart-0e2e4191-3bc9-412d-bd63-9e8955ab09ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960190008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2960190008
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2683667905
Short name T199
Test name
Test status
Simulation time 243737921 ps
CPU time 1.1 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 217460 kb
Host smart-a726c937-7190-4d67-a228-efc9c5d43193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683667905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2683667905
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3271438585
Short name T240
Test name
Test status
Simulation time 105862719 ps
CPU time 0.78 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 199536 kb
Host smart-ccd28944-5163-41f5-aa55-da86f003edeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271438585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3271438585
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1829899968
Short name T258
Test name
Test status
Simulation time 689455798 ps
CPU time 3.95 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 200276 kb
Host smart-dcaedfab-5d87-4ad5-8e7e-8634e77604e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829899968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1829899968
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3752225870
Short name T312
Test name
Test status
Simulation time 171156332 ps
CPU time 1.17 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 200076 kb
Host smart-b23fd08e-7b69-48d4-98f8-524ca04446a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752225870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3752225870
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2180980866
Short name T53
Test name
Test status
Simulation time 245333960 ps
CPU time 1.55 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200208 kb
Host smart-1dcfab5c-2dcf-4f85-b660-6015e4b4de40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180980866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2180980866
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1270843449
Short name T138
Test name
Test status
Simulation time 3519065935 ps
CPU time 11.72 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:42 PM PDT 24
Peak memory 208452 kb
Host smart-d3201f5b-a7d9-494e-87f4-c764f12ada3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270843449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1270843449
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1926676625
Short name T248
Test name
Test status
Simulation time 346618406 ps
CPU time 2.21 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:33 PM PDT 24
Peak memory 208280 kb
Host smart-1048c8d1-bd87-4612-b082-8330afcc3233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926676625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1926676625
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2698758365
Short name T216
Test name
Test status
Simulation time 151498003 ps
CPU time 1.16 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 200096 kb
Host smart-a1dfb9c3-6ec3-4fd9-8d7a-e1d67a678fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698758365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2698758365
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3771419508
Short name T401
Test name
Test status
Simulation time 65493606 ps
CPU time 0.76 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:37 PM PDT 24
Peak memory 199880 kb
Host smart-6aa5d522-bd96-4af0-89a3-d287648f3679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771419508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3771419508
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2799898810
Short name T251
Test name
Test status
Simulation time 2359674031 ps
CPU time 8.94 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:42 PM PDT 24
Peak memory 217632 kb
Host smart-18733fd7-4fcc-422e-827c-d49d2a2578b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799898810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2799898810
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3165994494
Short name T41
Test name
Test status
Simulation time 243981308 ps
CPU time 1.12 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 217468 kb
Host smart-7f14850e-9965-4f4d-9a1d-7d380312a2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165994494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3165994494
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.840699927
Short name T12
Test name
Test status
Simulation time 103150514 ps
CPU time 0.76 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:10 PM PDT 24
Peak memory 199900 kb
Host smart-a217b324-ecd9-4738-934f-23c1ed19a9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840699927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.840699927
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2879306670
Short name T280
Test name
Test status
Simulation time 746363208 ps
CPU time 4.08 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 200312 kb
Host smart-c0ce3200-d673-4f43-bcb5-f6b7cb372b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879306670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2879306670
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1375117755
Short name T443
Test name
Test status
Simulation time 144732199 ps
CPU time 1.16 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 199924 kb
Host smart-ab8adfff-046e-40ab-972e-8bbace7fede9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375117755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1375117755
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2533214377
Short name T194
Test name
Test status
Simulation time 261499365 ps
CPU time 1.46 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 200276 kb
Host smart-647ba9a0-cd2c-4473-9072-17c4e413b658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533214377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2533214377
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2109517872
Short name T474
Test name
Test status
Simulation time 3725897231 ps
CPU time 17.42 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:51 PM PDT 24
Peak memory 208436 kb
Host smart-9587babf-3703-4ead-8714-54a92d651e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109517872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2109517872
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.16543117
Short name T278
Test name
Test status
Simulation time 321831451 ps
CPU time 1.93 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 199900 kb
Host smart-a3c7cdbf-acb2-4cbc-8117-5ce4dfbde03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16543117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.16543117
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.664665434
Short name T245
Test name
Test status
Simulation time 144194511 ps
CPU time 1.18 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 199776 kb
Host smart-a116b922-7569-4b59-b3b3-821f72d91b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664665434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.664665434
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3274831943
Short name T476
Test name
Test status
Simulation time 71694196 ps
CPU time 0.78 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 199852 kb
Host smart-776e1e7f-fc5e-4120-8136-bd9563c077ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274831943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3274831943
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1550191776
Short name T34
Test name
Test status
Simulation time 1887161123 ps
CPU time 6.79 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:45 PM PDT 24
Peak memory 217724 kb
Host smart-2fae8ab5-4100-4eac-b832-5a09631f89b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550191776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1550191776
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.572107871
Short name T388
Test name
Test status
Simulation time 244740867 ps
CPU time 1.02 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 217452 kb
Host smart-cf7153ee-4cd7-4edd-91f6-3bdfcf383c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572107871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.572107871
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.4242323370
Short name T520
Test name
Test status
Simulation time 75403111 ps
CPU time 0.75 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:07 PM PDT 24
Peak memory 199892 kb
Host smart-d27ee191-134b-4681-b4d0-2d9d040693ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242323370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.4242323370
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.381239785
Short name T429
Test name
Test status
Simulation time 897707369 ps
CPU time 4.96 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 200320 kb
Host smart-f867690c-1c31-4b24-aa6b-4c919664690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381239785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.381239785
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2616431953
Short name T167
Test name
Test status
Simulation time 179238607 ps
CPU time 1.18 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 200092 kb
Host smart-57dfa1b7-54f9-49d6-8646-252c5b8638c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616431953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2616431953
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2700978715
Short name T468
Test name
Test status
Simulation time 256999809 ps
CPU time 1.42 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200280 kb
Host smart-71763481-7ba3-402d-b93b-f0fb6c19dae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700978715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2700978715
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1111002293
Short name T135
Test name
Test status
Simulation time 12875096974 ps
CPU time 44.89 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:56 PM PDT 24
Peak memory 208588 kb
Host smart-4b7d932d-4af9-4e80-9bdf-a8350e062fe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111002293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1111002293
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.669703007
Short name T393
Test name
Test status
Simulation time 140998273 ps
CPU time 1.7 seconds
Started Jun 28 05:59:16 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 200040 kb
Host smart-7e912376-de3c-421b-9534-09e99df9424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669703007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.669703007
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.140752854
Short name T152
Test name
Test status
Simulation time 70749109 ps
CPU time 0.78 seconds
Started Jun 28 05:59:18 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 200076 kb
Host smart-3aa20596-bcda-48aa-9f83-4053482da548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140752854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.140752854
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.502880704
Short name T219
Test name
Test status
Simulation time 74232667 ps
CPU time 0.77 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:21 PM PDT 24
Peak memory 199808 kb
Host smart-78e4811c-359a-4c66-9bf2-dd20567297a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502880704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.502880704
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2204018514
Short name T273
Test name
Test status
Simulation time 1887411185 ps
CPU time 7.06 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:19 PM PDT 24
Peak memory 216792 kb
Host smart-d4da66e1-0553-4592-9dae-5fa4fedfc52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204018514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2204018514
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2794636341
Short name T462
Test name
Test status
Simulation time 243904853 ps
CPU time 1.11 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 217432 kb
Host smart-8d544730-207d-4450-ae11-7b2acc304e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794636341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2794636341
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2198641704
Short name T15
Test name
Test status
Simulation time 223856322 ps
CPU time 0.93 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 199908 kb
Host smart-0bab7570-721c-4f06-93fe-bca0583f7bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198641704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2198641704
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1264026375
Short name T407
Test name
Test status
Simulation time 1402123806 ps
CPU time 5.86 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:25 PM PDT 24
Peak memory 200208 kb
Host smart-7bfea9da-7974-4a2f-9412-45b06aa0a54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264026375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1264026375
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3578618324
Short name T512
Test name
Test status
Simulation time 143994734 ps
CPU time 1.1 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:24 PM PDT 24
Peak memory 200004 kb
Host smart-3ceb9760-c69c-4403-9b4b-74679da14e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578618324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3578618324
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3937863052
Short name T292
Test name
Test status
Simulation time 258608427 ps
CPU time 1.51 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:11 PM PDT 24
Peak memory 200276 kb
Host smart-3af3e551-aa15-4ccc-854e-ac2ffe34700a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937863052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3937863052
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2957555391
Short name T422
Test name
Test status
Simulation time 1502792672 ps
CPU time 5.75 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 200248 kb
Host smart-9f667415-afbf-489a-b1d8-e3b90dbeb140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957555391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2957555391
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1356639198
Short name T321
Test name
Test status
Simulation time 115277219 ps
CPU time 1.59 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:16 PM PDT 24
Peak memory 200068 kb
Host smart-63cb1cd9-875f-4d62-bf8f-1aec15655717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356639198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1356639198
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2032447475
Short name T470
Test name
Test status
Simulation time 155862008 ps
CPU time 1.28 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:18 PM PDT 24
Peak memory 200428 kb
Host smart-074948d0-7253-4d70-96f9-3156fd03ea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032447475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2032447475
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2405118836
Short name T196
Test name
Test status
Simulation time 63412714 ps
CPU time 0.73 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:27 PM PDT 24
Peak memory 199596 kb
Host smart-5e23b449-3032-4359-9b54-8dffe7612c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405118836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2405118836
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2761476793
Short name T354
Test name
Test status
Simulation time 2344392379 ps
CPU time 8.18 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:29 PM PDT 24
Peak memory 221756 kb
Host smart-2dc720bb-94cb-413f-96b9-a1c3ed48a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761476793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2761476793
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1421933762
Short name T179
Test name
Test status
Simulation time 246201080 ps
CPU time 1.04 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:31 PM PDT 24
Peak memory 217612 kb
Host smart-4be80419-f626-4edf-b1f6-525088f56045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421933762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1421933762
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1422298651
Short name T513
Test name
Test status
Simulation time 84576152 ps
CPU time 0.74 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:21 PM PDT 24
Peak memory 199904 kb
Host smart-15613a76-9cf4-4f94-aa1f-e4252dc84c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422298651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1422298651
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2284788913
Short name T460
Test name
Test status
Simulation time 1423870409 ps
CPU time 5.84 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 200344 kb
Host smart-feea3708-3fb1-4659-88ef-2c712dd5cd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284788913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2284788913
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1148355165
Short name T275
Test name
Test status
Simulation time 112739800 ps
CPU time 1.04 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:21 PM PDT 24
Peak memory 200092 kb
Host smart-0c10c5fa-48da-49a7-afba-5d0c054b307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148355165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1148355165
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1119702505
Short name T246
Test name
Test status
Simulation time 125039147 ps
CPU time 1.24 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200132 kb
Host smart-fb02d95d-99b6-4d29-9e08-174bf1c5f05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119702505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1119702505
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.222996865
Short name T368
Test name
Test status
Simulation time 1193575389 ps
CPU time 5.58 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200356 kb
Host smart-98f698c9-63e7-4149-b50a-fd9158cb0de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222996865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.222996865
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.201872808
Short name T66
Test name
Test status
Simulation time 151319180 ps
CPU time 1.93 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200088 kb
Host smart-05b52966-389c-4cff-9eda-151c2ceeb137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201872808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.201872808
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1073156459
Short name T83
Test name
Test status
Simulation time 168025616 ps
CPU time 1.31 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200192 kb
Host smart-faefdbb8-74a5-45b2-ad25-e5bb8f658c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073156459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1073156459
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.215985580
Short name T399
Test name
Test status
Simulation time 85866515 ps
CPU time 0.84 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 199664 kb
Host smart-e17341c1-9d92-4524-a917-e875b10961bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215985580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.215985580
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3682169889
Short name T11
Test name
Test status
Simulation time 2362052662 ps
CPU time 8.75 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:14 PM PDT 24
Peak memory 217856 kb
Host smart-8f87f149-3a66-4ae4-99ae-4b9a22b038ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682169889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3682169889
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1299647349
Short name T318
Test name
Test status
Simulation time 247571670 ps
CPU time 1.04 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 217176 kb
Host smart-db2cae8b-6645-4824-9199-ef6278d5b3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299647349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1299647349
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3193834401
Short name T173
Test name
Test status
Simulation time 74415018 ps
CPU time 0.76 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:29 PM PDT 24
Peak memory 199904 kb
Host smart-116a2c7d-19d3-474a-b7f4-ca3d52bf3f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193834401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3193834401
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.620188732
Short name T244
Test name
Test status
Simulation time 828540468 ps
CPU time 4.17 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 200344 kb
Host smart-316eaa11-4fc1-4d86-91ba-b540a91380e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620188732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.620188732
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1672095748
Short name T284
Test name
Test status
Simulation time 180819595 ps
CPU time 1.23 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 199792 kb
Host smart-9fa49166-c9f4-434f-8851-0ca4e73543dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672095748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1672095748
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.354619090
Short name T529
Test name
Test status
Simulation time 118700323 ps
CPU time 1.14 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200188 kb
Host smart-ae8c0aa9-2f05-4585-b12a-c15daad00795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354619090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.354619090
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2744025811
Short name T440
Test name
Test status
Simulation time 3372609077 ps
CPU time 15.67 seconds
Started Jun 28 05:59:18 PM PDT 24
Finished Jun 28 05:59:54 PM PDT 24
Peak memory 208548 kb
Host smart-d3d0f70b-5cf0-4cf1-8bf3-1cc7222a800b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744025811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2744025811
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3389021287
Short name T172
Test name
Test status
Simulation time 296070676 ps
CPU time 2.06 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:31 PM PDT 24
Peak memory 208232 kb
Host smart-b0637a78-f346-4761-90a7-ed20b7355a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389021287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3389021287
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3465435474
Short name T350
Test name
Test status
Simulation time 270986676 ps
CPU time 1.55 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200088 kb
Host smart-a8e81f17-890a-4f67-ae1a-7783449f9e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465435474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3465435474
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.886015862
Short name T394
Test name
Test status
Simulation time 69149531 ps
CPU time 0.75 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 199876 kb
Host smart-69cfce25-3f4e-483c-96b2-67f10bdfe304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886015862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.886015862
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3513341430
Short name T28
Test name
Test status
Simulation time 1230201047 ps
CPU time 5.65 seconds
Started Jun 28 05:59:16 PM PDT 24
Finished Jun 28 05:59:42 PM PDT 24
Peak memory 217624 kb
Host smart-68d9145f-8e72-499a-a0fe-3882c2a5c8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513341430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3513341430
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3130964387
Short name T378
Test name
Test status
Simulation time 244397816 ps
CPU time 1.08 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:13 PM PDT 24
Peak memory 217448 kb
Host smart-88816e2f-71cd-4b74-9ea9-e8f6925036ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130964387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3130964387
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1235521102
Short name T8
Test name
Test status
Simulation time 209917397 ps
CPU time 0.94 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 199716 kb
Host smart-7030a6c0-3820-491c-ad2e-945b35db45ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235521102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1235521102
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.443844515
Short name T396
Test name
Test status
Simulation time 1825167648 ps
CPU time 6.49 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 200340 kb
Host smart-144201f5-bfa6-4172-a289-dbb38591a665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443844515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.443844515
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1175047074
Short name T174
Test name
Test status
Simulation time 107622751 ps
CPU time 0.99 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:29 PM PDT 24
Peak memory 200084 kb
Host smart-dbab4558-fbc1-4081-a3f3-0001baa04d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175047074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1175047074
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1840347355
Short name T281
Test name
Test status
Simulation time 199982016 ps
CPU time 1.43 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 200276 kb
Host smart-cdb9cfe7-7250-45da-958a-34fb8e29e80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840347355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1840347355
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3813999491
Short name T504
Test name
Test status
Simulation time 10911495867 ps
CPU time 43.36 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 208608 kb
Host smart-4968e20c-cf10-4ee7-942d-542d05f2bf6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813999491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3813999491
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1211475761
Short name T469
Test name
Test status
Simulation time 357287939 ps
CPU time 2.33 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:33 PM PDT 24
Peak memory 200084 kb
Host smart-efbbea84-7667-4c1a-8ed8-6c3facb9c37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211475761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1211475761
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2498649042
Short name T432
Test name
Test status
Simulation time 117121871 ps
CPU time 1.03 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:34 PM PDT 24
Peak memory 200064 kb
Host smart-ddc63617-1d4d-480c-9829-46bbf8d68815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498649042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2498649042
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.525248816
Short name T255
Test name
Test status
Simulation time 69497444 ps
CPU time 0.78 seconds
Started Jun 28 05:59:22 PM PDT 24
Finished Jun 28 05:59:43 PM PDT 24
Peak memory 199864 kb
Host smart-03403448-adcc-403e-9445-362571b9669b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525248816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.525248816
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1342823341
Short name T268
Test name
Test status
Simulation time 2372302432 ps
CPU time 7.88 seconds
Started Jun 28 05:59:22 PM PDT 24
Finished Jun 28 05:59:49 PM PDT 24
Peak memory 217812 kb
Host smart-a9b6a0f0-448f-45fd-b9fd-2bba68fb6cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342823341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1342823341
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3158075878
Short name T330
Test name
Test status
Simulation time 244815948 ps
CPU time 1.04 seconds
Started Jun 28 05:59:27 PM PDT 24
Finished Jun 28 05:59:45 PM PDT 24
Peak memory 217420 kb
Host smart-80ef6364-1a13-4b07-ac65-c7248078d6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158075878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3158075878
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2029249663
Short name T19
Test name
Test status
Simulation time 177535452 ps
CPU time 0.88 seconds
Started Jun 28 05:59:15 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 199900 kb
Host smart-f62a2812-dc17-4c7a-9ce0-fe369f6e0c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029249663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2029249663
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1341775812
Short name T107
Test name
Test status
Simulation time 829623417 ps
CPU time 4.01 seconds
Started Jun 28 05:59:14 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 200340 kb
Host smart-e9e5e2e3-72cc-4fd7-b2bf-b162f68e14ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341775812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1341775812
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.52880303
Short name T210
Test name
Test status
Simulation time 175814715 ps
CPU time 1.15 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 200100 kb
Host smart-dfd45b39-ac21-432c-bee1-cac11c7d8620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52880303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.52880303
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2392899016
Short name T20
Test name
Test status
Simulation time 112488224 ps
CPU time 1.14 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:08 PM PDT 24
Peak memory 200284 kb
Host smart-ce4a648d-9eb4-49b0-81f9-d97eaf65d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392899016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2392899016
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2427348091
Short name T507
Test name
Test status
Simulation time 7274622009 ps
CPU time 30.61 seconds
Started Jun 28 05:59:28 PM PDT 24
Finished Jun 28 06:00:15 PM PDT 24
Peak memory 208604 kb
Host smart-ddb490c6-02a4-4900-99a4-0d58a83b3561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427348091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2427348091
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1554030248
Short name T324
Test name
Test status
Simulation time 121401397 ps
CPU time 1.69 seconds
Started Jun 28 05:59:27 PM PDT 24
Finished Jun 28 05:59:46 PM PDT 24
Peak memory 208324 kb
Host smart-484692aa-e8a5-40a5-9d97-449bb4e8cef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554030248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1554030248
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1497455649
Short name T298
Test name
Test status
Simulation time 155866781 ps
CPU time 1.18 seconds
Started Jun 28 05:59:28 PM PDT 24
Finished Jun 28 05:59:46 PM PDT 24
Peak memory 200100 kb
Host smart-03f48a1a-f4a3-4aeb-b36c-5f123884f14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497455649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1497455649
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1919919960
Short name T479
Test name
Test status
Simulation time 194705700 ps
CPU time 1.06 seconds
Started Jun 28 05:59:20 PM PDT 24
Finished Jun 28 05:59:42 PM PDT 24
Peak memory 199880 kb
Host smart-6de6f387-fc20-45a9-bcf2-712a3fdaa261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919919960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1919919960
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4017606916
Short name T37
Test name
Test status
Simulation time 1880538268 ps
CPU time 7.25 seconds
Started Jun 28 05:59:20 PM PDT 24
Finished Jun 28 05:59:47 PM PDT 24
Peak memory 221720 kb
Host smart-6e5ed076-403e-4694-8ff9-1dbd44cda0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017606916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4017606916
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1024801474
Short name T262
Test name
Test status
Simulation time 243697370 ps
CPU time 1.06 seconds
Started Jun 28 05:59:27 PM PDT 24
Finished Jun 28 05:59:45 PM PDT 24
Peak memory 217420 kb
Host smart-603f10b2-de59-4222-aae9-67af2f77c1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024801474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1024801474
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.997088123
Short name T17
Test name
Test status
Simulation time 228123082 ps
CPU time 0.99 seconds
Started Jun 28 05:59:26 PM PDT 24
Finished Jun 28 05:59:45 PM PDT 24
Peak memory 199900 kb
Host smart-5a5d8a09-2e9a-4c47-a990-a241a8e5fe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997088123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.997088123
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.112204718
Short name T339
Test name
Test status
Simulation time 938294931 ps
CPU time 4.64 seconds
Started Jun 28 05:59:25 PM PDT 24
Finished Jun 28 05:59:48 PM PDT 24
Peak memory 200268 kb
Host smart-5d025e43-7d88-4024-ab90-19c791592875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112204718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.112204718
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.618187838
Short name T32
Test name
Test status
Simulation time 185581384 ps
CPU time 1.15 seconds
Started Jun 28 05:59:28 PM PDT 24
Finished Jun 28 05:59:46 PM PDT 24
Peak memory 200096 kb
Host smart-dab380a3-ce90-47d2-a0f9-d7c661411263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618187838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.618187838
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2341659872
Short name T141
Test name
Test status
Simulation time 258068762 ps
CPU time 1.62 seconds
Started Jun 28 05:59:19 PM PDT 24
Finished Jun 28 05:59:41 PM PDT 24
Peak memory 200296 kb
Host smart-a76b3ecd-6692-40ca-b585-c2f190e4440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341659872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2341659872
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2498047139
Short name T430
Test name
Test status
Simulation time 13653390739 ps
CPU time 49.89 seconds
Started Jun 28 05:59:18 PM PDT 24
Finished Jun 28 06:00:28 PM PDT 24
Peak memory 200396 kb
Host smart-387bca13-c9f9-47fd-99b6-0f15115e0582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498047139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2498047139
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2679000908
Short name T472
Test name
Test status
Simulation time 278985685 ps
CPU time 1.96 seconds
Started Jun 28 05:59:18 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 200088 kb
Host smart-2aee1bd2-39a0-4389-9969-a7b823e9856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679000908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2679000908
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.4237796370
Short name T203
Test name
Test status
Simulation time 204856824 ps
CPU time 1.3 seconds
Started Jun 28 05:59:20 PM PDT 24
Finished Jun 28 05:59:42 PM PDT 24
Peak memory 200092 kb
Host smart-fe04eabd-1a79-423f-ba3f-6539a801fb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237796370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.4237796370
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.415274979
Short name T166
Test name
Test status
Simulation time 61779730 ps
CPU time 0.74 seconds
Started Jun 28 05:59:28 PM PDT 24
Finished Jun 28 05:59:45 PM PDT 24
Peak memory 199880 kb
Host smart-267a3085-4303-4580-8092-f2c77b87d2b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415274979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.415274979
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1337033287
Short name T416
Test name
Test status
Simulation time 244584000 ps
CPU time 1.17 seconds
Started Jun 28 05:59:19 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 217480 kb
Host smart-52451cd3-66de-4b78-a3b1-7ab667b93884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337033287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1337033287
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.663050656
Short name T361
Test name
Test status
Simulation time 133732240 ps
CPU time 0.84 seconds
Started Jun 28 05:59:19 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 199896 kb
Host smart-35efe923-fbbd-4c84-84ef-17fbc28c4e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663050656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.663050656
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3541628110
Short name T412
Test name
Test status
Simulation time 1004536881 ps
CPU time 4.78 seconds
Started Jun 28 05:59:27 PM PDT 24
Finished Jun 28 05:59:49 PM PDT 24
Peak memory 200288 kb
Host smart-f63d56d8-22ce-43ba-9c10-4e1931fd7a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541628110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3541628110
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3815575866
Short name T325
Test name
Test status
Simulation time 166995265 ps
CPU time 1.13 seconds
Started Jun 28 05:59:22 PM PDT 24
Finished Jun 28 05:59:43 PM PDT 24
Peak memory 200072 kb
Host smart-f93b66b7-01f5-44c1-bee6-beeff0d0cef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815575866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3815575866
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2705293381
Short name T370
Test name
Test status
Simulation time 123648420 ps
CPU time 1.32 seconds
Started Jun 28 05:59:22 PM PDT 24
Finished Jun 28 05:59:43 PM PDT 24
Peak memory 200200 kb
Host smart-a04db48d-0136-4b4c-bd39-60632d751155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705293381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2705293381
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.264327419
Short name T235
Test name
Test status
Simulation time 383320059 ps
CPU time 2 seconds
Started Jun 28 05:59:20 PM PDT 24
Finished Jun 28 05:59:43 PM PDT 24
Peak memory 200276 kb
Host smart-da5f3449-6ee9-4c7e-9209-d2b39b96785f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264327419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.264327419
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4051689395
Short name T91
Test name
Test status
Simulation time 124614891 ps
CPU time 1.46 seconds
Started Jun 28 05:59:25 PM PDT 24
Finished Jun 28 05:59:45 PM PDT 24
Peak memory 199996 kb
Host smart-b35981a3-42be-4703-a934-3faea8310405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051689395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4051689395
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3470639842
Short name T78
Test name
Test status
Simulation time 163867210 ps
CPU time 1.47 seconds
Started Jun 28 05:59:18 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 200304 kb
Host smart-60845899-0a01-42c1-a762-5a18f0473a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470639842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3470639842
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.301981289
Short name T362
Test name
Test status
Simulation time 70313110 ps
CPU time 0.82 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 199856 kb
Host smart-0671740e-6164-46bd-853f-95683ce0f1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301981289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.301981289
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.289416170
Short name T441
Test name
Test status
Simulation time 2376424492 ps
CPU time 8.54 seconds
Started Jun 28 05:59:03 PM PDT 24
Finished Jun 28 05:59:13 PM PDT 24
Peak memory 217808 kb
Host smart-9e280b60-11c8-4e8d-9b25-c67411494163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289416170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.289416170
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3199772713
Short name T261
Test name
Test status
Simulation time 246909405 ps
CPU time 1.04 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:40 PM PDT 24
Peak memory 217472 kb
Host smart-dc5db82d-dd5b-4434-ac91-5fc469f11624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199772713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3199772713
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2373158114
Short name T223
Test name
Test status
Simulation time 223408966 ps
CPU time 1 seconds
Started Jun 28 05:59:03 PM PDT 24
Finished Jun 28 05:59:05 PM PDT 24
Peak memory 199820 kb
Host smart-aead229a-c9ee-45f7-b4df-2c74ce56f84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373158114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2373158114
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1703662583
Short name T74
Test name
Test status
Simulation time 1314573595 ps
CPU time 5.31 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 200316 kb
Host smart-3e286c5e-5f20-481e-a0a4-16834d48f96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703662583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1703662583
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1944356
Short name T63
Test name
Test status
Simulation time 16502988193 ps
CPU time 28.45 seconds
Started Jun 28 05:59:03 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 217584 kb
Host smart-f456b970-c922-4664-a28f-ebbef9d0a9a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1944356
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1530457094
Short name T148
Test name
Test status
Simulation time 97454369 ps
CPU time 1.04 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:08 PM PDT 24
Peak memory 200112 kb
Host smart-8005373a-f0f0-40de-ab40-3adc26e86f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530457094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1530457094
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3645430729
Short name T377
Test name
Test status
Simulation time 118023582 ps
CPU time 1.19 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 200304 kb
Host smart-44aa29d2-db51-4543-a84c-2d414148f3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645430729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3645430729
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3852271048
Short name T270
Test name
Test status
Simulation time 6190156880 ps
CPU time 25.71 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:31 PM PDT 24
Peak memory 208524 kb
Host smart-233a7063-c169-4711-9d79-8aad632e6e86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852271048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3852271048
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3430905767
Short name T197
Test name
Test status
Simulation time 368570205 ps
CPU time 2.33 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:14 PM PDT 24
Peak memory 200084 kb
Host smart-2cd14d25-1d15-4496-b30c-3e09c945262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430905767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3430905767
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3755048503
Short name T253
Test name
Test status
Simulation time 158522902 ps
CPU time 1.13 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:32 PM PDT 24
Peak memory 200088 kb
Host smart-9a476bef-8336-4d30-9e34-00a7285ac62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755048503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3755048503
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.928568954
Short name T299
Test name
Test status
Simulation time 68994716 ps
CPU time 0.74 seconds
Started Jun 28 05:59:40 PM PDT 24
Finished Jun 28 05:59:49 PM PDT 24
Peak memory 199864 kb
Host smart-e8c0efba-8619-4b3c-8e1b-fcf2147c46ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928568954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.928568954
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.684774929
Short name T413
Test name
Test status
Simulation time 1886339148 ps
CPU time 7.25 seconds
Started Jun 28 05:59:31 PM PDT 24
Finished Jun 28 05:59:53 PM PDT 24
Peak memory 217736 kb
Host smart-fceea3fa-71ba-43a3-809c-fd5a7bf00285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684774929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.684774929
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2647395454
Short name T524
Test name
Test status
Simulation time 244656949 ps
CPU time 1.15 seconds
Started Jun 28 05:59:30 PM PDT 24
Finished Jun 28 05:59:47 PM PDT 24
Peak memory 217436 kb
Host smart-66483971-8b9e-401b-ac90-e3c9aaa6d270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647395454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2647395454
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2488061599
Short name T190
Test name
Test status
Simulation time 230784747 ps
CPU time 1.03 seconds
Started Jun 28 05:59:21 PM PDT 24
Finished Jun 28 05:59:43 PM PDT 24
Peak memory 199900 kb
Host smart-6dc03cdc-1d6d-4fac-93e5-9705c4f01e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488061599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2488061599
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3491149677
Short name T103
Test name
Test status
Simulation time 1013321148 ps
CPU time 4.91 seconds
Started Jun 28 05:59:48 PM PDT 24
Finished Jun 28 05:59:56 PM PDT 24
Peak memory 200336 kb
Host smart-5407d1e8-75ae-4c50-af02-7a01121ca0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491149677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3491149677
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.4115781659
Short name T282
Test name
Test status
Simulation time 100734333 ps
CPU time 0.98 seconds
Started Jun 28 05:59:52 PM PDT 24
Finished Jun 28 05:59:55 PM PDT 24
Peak memory 200060 kb
Host smart-dba98d16-5c1e-4ea0-9117-fcff8bf5b741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115781659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.4115781659
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2206019238
Short name T4
Test name
Test status
Simulation time 111075972 ps
CPU time 1.15 seconds
Started Jun 28 05:59:27 PM PDT 24
Finished Jun 28 05:59:45 PM PDT 24
Peak memory 200224 kb
Host smart-b96e9d40-d24e-45e2-9a93-bc184ff2feff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206019238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2206019238
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2341562887
Short name T249
Test name
Test status
Simulation time 6517495921 ps
CPU time 28.39 seconds
Started Jun 28 05:59:52 PM PDT 24
Finished Jun 28 06:00:22 PM PDT 24
Peak memory 208620 kb
Host smart-7212d3b4-ca45-4e9b-bd71-c11adb562270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341562887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2341562887
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.76033296
Short name T47
Test name
Test status
Simulation time 382868918 ps
CPU time 2.24 seconds
Started Jun 28 05:59:44 PM PDT 24
Finished Jun 28 05:59:52 PM PDT 24
Peak memory 200080 kb
Host smart-bb639bfb-7a46-43c1-b96b-fb125dedecc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76033296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.76033296
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3940343315
Short name T380
Test name
Test status
Simulation time 71329880 ps
CPU time 0.79 seconds
Started Jun 28 05:59:52 PM PDT 24
Finished Jun 28 05:59:55 PM PDT 24
Peak memory 200060 kb
Host smart-4a1562ef-05f9-4b0b-b693-05eb1b46b9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940343315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3940343315
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1226936924
Short name T540
Test name
Test status
Simulation time 66109670 ps
CPU time 0.78 seconds
Started Jun 28 05:59:38 PM PDT 24
Finished Jun 28 05:59:48 PM PDT 24
Peak memory 199872 kb
Host smart-0ca9b640-c8d7-462d-b365-0ccb998c3391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226936924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1226936924
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3430804602
Short name T29
Test name
Test status
Simulation time 1883925904 ps
CPU time 8.04 seconds
Started Jun 28 05:59:52 PM PDT 24
Finished Jun 28 06:00:02 PM PDT 24
Peak memory 217644 kb
Host smart-05ebe482-d0f8-4ce5-9c13-20c8c4e037a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430804602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3430804602
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2210352057
Short name T447
Test name
Test status
Simulation time 244408123 ps
CPU time 1.04 seconds
Started Jun 28 05:59:39 PM PDT 24
Finished Jun 28 05:59:50 PM PDT 24
Peak memory 217432 kb
Host smart-27f29d26-ccc9-43b6-8295-e8bc6e8d3609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210352057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2210352057
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1287484707
Short name T445
Test name
Test status
Simulation time 174705340 ps
CPU time 0.85 seconds
Started Jun 28 05:59:38 PM PDT 24
Finished Jun 28 05:59:49 PM PDT 24
Peak memory 199892 kb
Host smart-47d6b2c8-d426-47b7-8e53-f91588b4cd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287484707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1287484707
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3614399353
Short name T117
Test name
Test status
Simulation time 796993442 ps
CPU time 4.28 seconds
Started Jun 28 05:59:39 PM PDT 24
Finished Jun 28 05:59:52 PM PDT 24
Peak memory 200492 kb
Host smart-3b782c02-3031-4477-b766-365ab022bf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614399353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3614399353
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3729888727
Short name T153
Test name
Test status
Simulation time 100025953 ps
CPU time 0.96 seconds
Started Jun 28 05:59:52 PM PDT 24
Finished Jun 28 05:59:55 PM PDT 24
Peak memory 200060 kb
Host smart-905b5628-4616-4327-84a1-195df540d25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729888727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3729888727
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1578587989
Short name T515
Test name
Test status
Simulation time 115314221 ps
CPU time 1.2 seconds
Started Jun 28 05:59:47 PM PDT 24
Finished Jun 28 05:59:52 PM PDT 24
Peak memory 200224 kb
Host smart-571ca2f0-13f6-40ef-98ae-54001444f74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578587989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1578587989
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3085046088
Short name T308
Test name
Test status
Simulation time 4358280768 ps
CPU time 16.64 seconds
Started Jun 28 05:59:52 PM PDT 24
Finished Jun 28 06:00:11 PM PDT 24
Peak memory 216292 kb
Host smart-bb67cdb8-d2ec-4524-82e4-c59fe0d20bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085046088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3085046088
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3804155542
Short name T257
Test name
Test status
Simulation time 122988337 ps
CPU time 1.6 seconds
Started Jun 28 05:59:47 PM PDT 24
Finished Jun 28 05:59:53 PM PDT 24
Peak memory 208320 kb
Host smart-0bbc2706-daeb-45a4-8904-92606f042d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804155542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3804155542
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1962910793
Short name T456
Test name
Test status
Simulation time 105860321 ps
CPU time 0.94 seconds
Started Jun 28 05:59:38 PM PDT 24
Finished Jun 28 05:59:49 PM PDT 24
Peak memory 200084 kb
Host smart-ca2adbec-64d6-4447-b945-d170f9dae694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962910793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1962910793
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2352970594
Short name T60
Test name
Test status
Simulation time 86287178 ps
CPU time 0.81 seconds
Started Jun 28 05:59:40 PM PDT 24
Finished Jun 28 05:59:49 PM PDT 24
Peak memory 199868 kb
Host smart-9cb1e8aa-77d7-460d-87bd-06622658f9a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352970594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2352970594
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2310690012
Short name T44
Test name
Test status
Simulation time 1216039570 ps
CPU time 5.57 seconds
Started Jun 28 05:59:52 PM PDT 24
Finished Jun 28 05:59:59 PM PDT 24
Peak memory 221600 kb
Host smart-09582776-fcbb-45cb-8921-416839bc1c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310690012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2310690012
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.866117542
Short name T400
Test name
Test status
Simulation time 243999965 ps
CPU time 1.06 seconds
Started Jun 28 05:59:40 PM PDT 24
Finished Jun 28 05:59:50 PM PDT 24
Peak memory 217432 kb
Host smart-de094502-c187-4975-b450-454e27410172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866117542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.866117542
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.904410988
Short name T384
Test name
Test status
Simulation time 206324175 ps
CPU time 0.94 seconds
Started Jun 28 05:59:52 PM PDT 24
Finished Jun 28 05:59:55 PM PDT 24
Peak memory 199836 kb
Host smart-fdc6298d-6850-4f8a-b795-d40fe28757ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904410988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.904410988
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1010148621
Short name T411
Test name
Test status
Simulation time 1677547052 ps
CPU time 6.17 seconds
Started Jun 28 05:59:52 PM PDT 24
Finished Jun 28 06:00:00 PM PDT 24
Peak memory 200316 kb
Host smart-3cf8b443-b7d1-48c9-be04-7f38bcf85b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010148621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1010148621
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3009751287
Short name T398
Test name
Test status
Simulation time 144820671 ps
CPU time 1.11 seconds
Started Jun 28 05:59:39 PM PDT 24
Finished Jun 28 05:59:50 PM PDT 24
Peak memory 200072 kb
Host smart-9cc7c571-1cc2-424b-a995-3975afd917b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009751287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3009751287
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2822031666
Short name T89
Test name
Test status
Simulation time 202315305 ps
CPU time 1.37 seconds
Started Jun 28 05:59:30 PM PDT 24
Finished Jun 28 05:59:47 PM PDT 24
Peak memory 200264 kb
Host smart-bb172bd7-ad7f-4ee7-9b37-707db5c00eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822031666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2822031666
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3180312466
Short name T473
Test name
Test status
Simulation time 141273315 ps
CPU time 1.76 seconds
Started Jun 28 05:59:48 PM PDT 24
Finished Jun 28 05:59:53 PM PDT 24
Peak memory 200044 kb
Host smart-58695747-081e-434d-b57c-c729f34dc3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180312466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3180312466
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.846277147
Short name T79
Test name
Test status
Simulation time 139736133 ps
CPU time 1.04 seconds
Started Jun 28 05:59:38 PM PDT 24
Finished Jun 28 05:59:49 PM PDT 24
Peak memory 200204 kb
Host smart-9b6752d7-bbb0-4073-a541-e588128efadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846277147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.846277147
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2765306876
Short name T163
Test name
Test status
Simulation time 97581244 ps
CPU time 0.89 seconds
Started Jun 28 05:59:56 PM PDT 24
Finished Jun 28 06:00:00 PM PDT 24
Peak memory 199868 kb
Host smart-368f05fa-f608-4e69-8fc0-2727aa150283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765306876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2765306876
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1363815867
Short name T36
Test name
Test status
Simulation time 2361505727 ps
CPU time 8.55 seconds
Started Jun 28 05:59:56 PM PDT 24
Finished Jun 28 06:00:07 PM PDT 24
Peak memory 217888 kb
Host smart-cafa2762-298e-4866-9acb-1729b512aee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363815867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1363815867
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.758695227
Short name T76
Test name
Test status
Simulation time 243412719 ps
CPU time 1.19 seconds
Started Jun 28 05:59:58 PM PDT 24
Finished Jun 28 06:00:02 PM PDT 24
Peak memory 217432 kb
Host smart-1f3397b1-c721-4973-a72a-0b58e9fa7e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758695227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.758695227
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3436090884
Short name T2
Test name
Test status
Simulation time 115824749 ps
CPU time 0.82 seconds
Started Jun 28 05:59:44 PM PDT 24
Finished Jun 28 05:59:51 PM PDT 24
Peak memory 199908 kb
Host smart-dbb88060-6d4e-4f8e-8ae2-6bd42d9dafcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436090884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3436090884
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1270519947
Short name T352
Test name
Test status
Simulation time 1479880035 ps
CPU time 6.01 seconds
Started Jun 28 05:59:47 PM PDT 24
Finished Jun 28 05:59:57 PM PDT 24
Peak memory 200328 kb
Host smart-c5d398bc-1cf1-4512-8e7b-2bd57957855f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270519947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1270519947
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3955553767
Short name T159
Test name
Test status
Simulation time 147873295 ps
CPU time 1.11 seconds
Started Jun 28 05:59:46 PM PDT 24
Finished Jun 28 05:59:51 PM PDT 24
Peak memory 200084 kb
Host smart-df4419c3-3d0c-467e-9e65-ecd053c7e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955553767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3955553767
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3834588757
Short name T347
Test name
Test status
Simulation time 122580739 ps
CPU time 1.22 seconds
Started Jun 28 05:59:52 PM PDT 24
Finished Jun 28 05:59:55 PM PDT 24
Peak memory 200204 kb
Host smart-396b5c8b-e87e-48ee-af22-0002f61553ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834588757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3834588757
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2607222192
Short name T294
Test name
Test status
Simulation time 2179539227 ps
CPU time 11.16 seconds
Started Jun 28 06:00:00 PM PDT 24
Finished Jun 28 06:00:15 PM PDT 24
Peak memory 200472 kb
Host smart-b537e9a5-fedb-426d-84be-b5770c33ce89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607222192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2607222192
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2380381967
Short name T220
Test name
Test status
Simulation time 403278485 ps
CPU time 2.24 seconds
Started Jun 28 05:59:44 PM PDT 24
Finished Jun 28 05:59:52 PM PDT 24
Peak memory 208288 kb
Host smart-e3a936af-0027-4899-b433-268a3c7b432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380381967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2380381967
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3828743751
Short name T30
Test name
Test status
Simulation time 88915900 ps
CPU time 0.97 seconds
Started Jun 28 05:59:43 PM PDT 24
Finished Jun 28 05:59:51 PM PDT 24
Peak memory 200096 kb
Host smart-3c9e0e19-a7c0-4707-867e-a73523d1e2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828743751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3828743751
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2996273985
Short name T459
Test name
Test status
Simulation time 63192367 ps
CPU time 0.76 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:04 PM PDT 24
Peak memory 199876 kb
Host smart-7c998e6b-ba54-4748-aaf5-f41e37549626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996273985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2996273985
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1820505761
Short name T27
Test name
Test status
Simulation time 1902917799 ps
CPU time 8.09 seconds
Started Jun 28 05:59:55 PM PDT 24
Finished Jun 28 06:00:05 PM PDT 24
Peak memory 229880 kb
Host smart-8f1ea285-32c9-4682-9335-a931fa124dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820505761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1820505761
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2389636289
Short name T218
Test name
Test status
Simulation time 243861506 ps
CPU time 1.11 seconds
Started Jun 28 05:59:56 PM PDT 24
Finished Jun 28 05:59:59 PM PDT 24
Peak memory 217388 kb
Host smart-a003e31f-7dbe-4242-b334-ef7e0e12cc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389636289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2389636289
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3005120393
Short name T500
Test name
Test status
Simulation time 86939192 ps
CPU time 0.78 seconds
Started Jun 28 05:59:56 PM PDT 24
Finished Jun 28 05:59:59 PM PDT 24
Peak memory 199900 kb
Host smart-2318d3bb-7627-4942-b618-f86de8e54cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005120393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3005120393
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3197256364
Short name T264
Test name
Test status
Simulation time 894744726 ps
CPU time 4.79 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:08 PM PDT 24
Peak memory 200328 kb
Host smart-d3ef9b25-0a02-4155-89c5-956ebbaa2a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197256364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3197256364
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1006800985
Short name T175
Test name
Test status
Simulation time 182106505 ps
CPU time 1.26 seconds
Started Jun 28 05:59:58 PM PDT 24
Finished Jun 28 06:00:03 PM PDT 24
Peak memory 200096 kb
Host smart-551054e4-8de6-42d2-ba96-99a41feb6999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006800985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1006800985
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1923843812
Short name T533
Test name
Test status
Simulation time 251538438 ps
CPU time 1.54 seconds
Started Jun 28 05:59:56 PM PDT 24
Finished Jun 28 06:00:00 PM PDT 24
Peak memory 200196 kb
Host smart-5a52d342-2ede-48fe-8280-70dca1cb94c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923843812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1923843812
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.52451350
Short name T356
Test name
Test status
Simulation time 322025366 ps
CPU time 1.65 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:06 PM PDT 24
Peak memory 200276 kb
Host smart-dc956690-48ff-4650-8067-4271aff40e9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52451350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.52451350
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.951230579
Short name T46
Test name
Test status
Simulation time 472368946 ps
CPU time 2.76 seconds
Started Jun 28 06:00:05 PM PDT 24
Finished Jun 28 06:00:10 PM PDT 24
Peak memory 200076 kb
Host smart-7122312b-16fc-4919-9f67-ac1f743e03f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951230579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.951230579
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.744725697
Short name T266
Test name
Test status
Simulation time 77579105 ps
CPU time 0.91 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:05 PM PDT 24
Peak memory 200000 kb
Host smart-c89cacfb-8c2c-44d1-ae1d-3414911921c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744725697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.744725697
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3721015782
Short name T438
Test name
Test status
Simulation time 83649805 ps
CPU time 0.85 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:04 PM PDT 24
Peak memory 199872 kb
Host smart-76a7399c-4b05-420d-b48f-637b7311d06e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721015782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3721015782
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3069221615
Short name T435
Test name
Test status
Simulation time 2350142633 ps
CPU time 8.32 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:12 PM PDT 24
Peak memory 217688 kb
Host smart-a13b6042-27a8-4f2c-a3a3-63ed51337d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069221615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3069221615
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2516508951
Short name T200
Test name
Test status
Simulation time 244488820 ps
CPU time 1.15 seconds
Started Jun 28 06:00:04 PM PDT 24
Finished Jun 28 06:00:08 PM PDT 24
Peak memory 217444 kb
Host smart-9b277d65-51b9-423a-8fcf-fe060cab77d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516508951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2516508951
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2830480725
Short name T326
Test name
Test status
Simulation time 176204366 ps
CPU time 0.93 seconds
Started Jun 28 06:00:01 PM PDT 24
Finished Jun 28 06:00:06 PM PDT 24
Peak memory 199244 kb
Host smart-1df26fef-6b59-4fb5-bee2-f6d705b719ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830480725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2830480725
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2532446351
Short name T366
Test name
Test status
Simulation time 1342073221 ps
CPU time 5.64 seconds
Started Jun 28 05:59:58 PM PDT 24
Finished Jun 28 06:00:07 PM PDT 24
Peak memory 200492 kb
Host smart-3ad7b38c-dbe1-4663-afee-b58d2436291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532446351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2532446351
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1675648836
Short name T434
Test name
Test status
Simulation time 106915687 ps
CPU time 0.99 seconds
Started Jun 28 05:59:56 PM PDT 24
Finished Jun 28 06:00:00 PM PDT 24
Peak memory 200088 kb
Host smart-a65df864-0d7b-4f5d-bc85-b3a45c398a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675648836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1675648836
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1765828425
Short name T68
Test name
Test status
Simulation time 202541201 ps
CPU time 1.39 seconds
Started Jun 28 05:59:56 PM PDT 24
Finished Jun 28 05:59:59 PM PDT 24
Peak memory 200264 kb
Host smart-4715e5a5-ead3-4bce-aa2d-47e6c7534ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765828425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1765828425
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.642791756
Short name T531
Test name
Test status
Simulation time 472658418 ps
CPU time 2.59 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:07 PM PDT 24
Peak memory 200224 kb
Host smart-5b5c4460-f49b-4657-b92e-2ca53e79f0b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642791756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.642791756
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.408987068
Short name T527
Test name
Test status
Simulation time 136911764 ps
CPU time 1.66 seconds
Started Jun 28 06:00:01 PM PDT 24
Finished Jun 28 06:00:07 PM PDT 24
Peak memory 208284 kb
Host smart-616086d6-4371-46a4-92de-b7420a70048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408987068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.408987068
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2868620020
Short name T241
Test name
Test status
Simulation time 155815225 ps
CPU time 1.4 seconds
Started Jun 28 05:59:55 PM PDT 24
Finished Jun 28 05:59:58 PM PDT 24
Peak memory 200304 kb
Host smart-ffe34376-ddc1-4c48-92dd-47db3d3378eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868620020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2868620020
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.4066837684
Short name T457
Test name
Test status
Simulation time 69111484 ps
CPU time 0.91 seconds
Started Jun 28 06:00:05 PM PDT 24
Finished Jun 28 06:00:09 PM PDT 24
Peak memory 199876 kb
Host smart-d42d997c-fe03-4791-856c-6b6e7e9a6145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066837684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.4066837684
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1583608444
Short name T272
Test name
Test status
Simulation time 1912510044 ps
CPU time 6.78 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:10 PM PDT 24
Peak memory 217368 kb
Host smart-b07d85b3-fa39-4b22-a911-f8c409143586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583608444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1583608444
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2583769784
Short name T289
Test name
Test status
Simulation time 244158347 ps
CPU time 1.05 seconds
Started Jun 28 05:59:57 PM PDT 24
Finished Jun 28 06:00:01 PM PDT 24
Peak memory 217452 kb
Host smart-524f687c-6687-479b-b920-38430dae8c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583769784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2583769784
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.85308861
Short name T259
Test name
Test status
Simulation time 140524097 ps
CPU time 0.83 seconds
Started Jun 28 05:59:57 PM PDT 24
Finished Jun 28 06:00:01 PM PDT 24
Peak memory 199896 kb
Host smart-280db325-3828-456e-850b-577cc3a5615a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85308861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.85308861
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.730404120
Short name T204
Test name
Test status
Simulation time 874630832 ps
CPU time 4.25 seconds
Started Jun 28 06:00:00 PM PDT 24
Finished Jun 28 06:00:09 PM PDT 24
Peak memory 200344 kb
Host smart-b92930e0-3865-4b53-8d57-15628d5c2c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730404120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.730404120
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2461094178
Short name T114
Test name
Test status
Simulation time 137522340 ps
CPU time 1.17 seconds
Started Jun 28 05:59:58 PM PDT 24
Finished Jun 28 06:00:03 PM PDT 24
Peak memory 200096 kb
Host smart-179af434-c164-4439-8b45-c9d41db2690d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461094178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2461094178
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1873157218
Short name T373
Test name
Test status
Simulation time 235448257 ps
CPU time 1.59 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:04 PM PDT 24
Peak memory 200264 kb
Host smart-a368440d-73ad-4b34-a428-6a230fdee255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873157218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1873157218
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2231704147
Short name T521
Test name
Test status
Simulation time 6855670404 ps
CPU time 23.3 seconds
Started Jun 28 05:59:56 PM PDT 24
Finished Jun 28 06:00:22 PM PDT 24
Peak memory 200452 kb
Host smart-6e17672f-798f-4022-a731-866e2c0509aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231704147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2231704147
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2085304100
Short name T265
Test name
Test status
Simulation time 156162978 ps
CPU time 1.82 seconds
Started Jun 28 05:59:53 PM PDT 24
Finished Jun 28 05:59:57 PM PDT 24
Peak memory 200088 kb
Host smart-9cf225bc-30c1-4e17-948f-6c780043c399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085304100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2085304100
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1184983938
Short name T528
Test name
Test status
Simulation time 75369335 ps
CPU time 0.81 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:05 PM PDT 24
Peak memory 200104 kb
Host smart-ee5b2cde-41ff-4b5d-8567-8871d6f20dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184983938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1184983938
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1707032339
Short name T451
Test name
Test status
Simulation time 80652348 ps
CPU time 0.76 seconds
Started Jun 28 05:59:57 PM PDT 24
Finished Jun 28 06:00:01 PM PDT 24
Peak memory 199840 kb
Host smart-2cd1230d-2407-4660-91b7-591604b5a4a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707032339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1707032339
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3903741232
Short name T461
Test name
Test status
Simulation time 1232999536 ps
CPU time 5.59 seconds
Started Jun 28 06:00:05 PM PDT 24
Finished Jun 28 06:00:13 PM PDT 24
Peak memory 217356 kb
Host smart-9d1d5f9d-3c8d-4fcf-898b-8ee024cba05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903741232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3903741232
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3062262175
Short name T113
Test name
Test status
Simulation time 243899351 ps
CPU time 1.14 seconds
Started Jun 28 05:59:56 PM PDT 24
Finished Jun 28 06:00:00 PM PDT 24
Peak memory 217452 kb
Host smart-119d8f44-ea84-4252-8a7c-24ec4f2dd357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062262175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3062262175
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3001067426
Short name T448
Test name
Test status
Simulation time 136067676 ps
CPU time 0.84 seconds
Started Jun 28 06:00:05 PM PDT 24
Finished Jun 28 06:00:08 PM PDT 24
Peak memory 199896 kb
Host smart-79eb1ec7-33ad-4aae-ba8a-b9b11cdf722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001067426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3001067426
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2694819654
Short name T283
Test name
Test status
Simulation time 1153956821 ps
CPU time 4.9 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:08 PM PDT 24
Peak memory 200332 kb
Host smart-4ea38341-edd6-4787-a151-afd1de790cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694819654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2694819654
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3637512724
Short name T501
Test name
Test status
Simulation time 171201729 ps
CPU time 1.2 seconds
Started Jun 28 05:59:58 PM PDT 24
Finished Jun 28 06:00:03 PM PDT 24
Peak memory 200204 kb
Host smart-44721a66-60de-4ea2-9bce-1ae6a746e533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637512724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3637512724
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3126053
Short name T21
Test name
Test status
Simulation time 119041004 ps
CPU time 1.21 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:04 PM PDT 24
Peak memory 199956 kb
Host smart-c5ddacb3-c8c0-4583-a3b6-09e0fedd8f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3126053
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.852237108
Short name T86
Test name
Test status
Simulation time 5474859628 ps
CPU time 20.08 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:23 PM PDT 24
Peak memory 208600 kb
Host smart-cd26e406-30a4-423c-a45b-5fcbf10b9368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852237108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.852237108
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.520994043
Short name T538
Test name
Test status
Simulation time 360581864 ps
CPU time 2.02 seconds
Started Jun 28 06:00:00 PM PDT 24
Finished Jun 28 06:00:07 PM PDT 24
Peak memory 200084 kb
Host smart-2f86859b-7236-4bc5-b034-9c5b7ef4d1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520994043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.520994043
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3514042014
Short name T191
Test name
Test status
Simulation time 207864538 ps
CPU time 1.33 seconds
Started Jun 28 05:59:59 PM PDT 24
Finished Jun 28 06:00:04 PM PDT 24
Peak memory 200084 kb
Host smart-4422aacc-3b3b-446b-94ef-7259a8f28c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514042014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3514042014
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3323891203
Short name T332
Test name
Test status
Simulation time 64938166 ps
CPU time 0.74 seconds
Started Jun 28 06:00:00 PM PDT 24
Finished Jun 28 06:00:06 PM PDT 24
Peak memory 199884 kb
Host smart-a6200872-9f60-403b-af7f-f9700d7974b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323891203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3323891203
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3387700857
Short name T395
Test name
Test status
Simulation time 1233080103 ps
CPU time 5.49 seconds
Started Jun 28 06:00:00 PM PDT 24
Finished Jun 28 06:00:09 PM PDT 24
Peak memory 217680 kb
Host smart-057ea5f7-80f1-47ca-aba5-dc8bb8be2e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387700857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3387700857
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3983235431
Short name T7
Test name
Test status
Simulation time 243825317 ps
CPU time 1.09 seconds
Started Jun 28 05:59:58 PM PDT 24
Finished Jun 28 06:00:03 PM PDT 24
Peak memory 217596 kb
Host smart-41098392-67e5-4273-9cf9-d323c843623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983235431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3983235431
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2213377065
Short name T228
Test name
Test status
Simulation time 116403974 ps
CPU time 0.81 seconds
Started Jun 28 06:00:01 PM PDT 24
Finished Jun 28 06:00:06 PM PDT 24
Peak memory 199116 kb
Host smart-5e0b0326-c347-4ed5-812b-287a09e8e3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213377065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2213377065
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.4281155369
Short name T415
Test name
Test status
Simulation time 1044421540 ps
CPU time 5.33 seconds
Started Jun 28 06:00:00 PM PDT 24
Finished Jun 28 06:00:11 PM PDT 24
Peak memory 200344 kb
Host smart-9a040e25-e72e-48ee-b193-e699db488859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281155369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4281155369
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3394418574
Short name T353
Test name
Test status
Simulation time 99200632 ps
CPU time 1.23 seconds
Started Jun 28 05:59:57 PM PDT 24
Finished Jun 28 06:00:02 PM PDT 24
Peak memory 200076 kb
Host smart-58422808-c5d8-47b8-b1a6-18e3f0e1aad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394418574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3394418574
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3729580400
Short name T237
Test name
Test status
Simulation time 125448309 ps
CPU time 1.24 seconds
Started Jun 28 06:00:01 PM PDT 24
Finished Jun 28 06:00:07 PM PDT 24
Peak memory 200284 kb
Host smart-e4414663-072b-4f80-9673-50a5cc90d736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729580400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3729580400
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3934071628
Short name T323
Test name
Test status
Simulation time 8189428114 ps
CPU time 28.82 seconds
Started Jun 28 05:59:56 PM PDT 24
Finished Jun 28 06:00:27 PM PDT 24
Peak memory 208608 kb
Host smart-2290edd6-a47b-414c-bb99-e5d136973b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934071628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3934071628
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1079448013
Short name T340
Test name
Test status
Simulation time 427444862 ps
CPU time 2.37 seconds
Started Jun 28 06:00:01 PM PDT 24
Finished Jun 28 06:00:08 PM PDT 24
Peak memory 208328 kb
Host smart-f0d79934-90ef-461b-84a0-541d6d4240c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079448013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1079448013
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3835273847
Short name T458
Test name
Test status
Simulation time 127320626 ps
CPU time 1.12 seconds
Started Jun 28 06:00:00 PM PDT 24
Finished Jun 28 06:00:05 PM PDT 24
Peak memory 200096 kb
Host smart-5bf377ea-e64e-4ebf-9041-0057baafe075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835273847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3835273847
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2014720147
Short name T467
Test name
Test status
Simulation time 73704147 ps
CPU time 0.8 seconds
Started Jun 28 06:00:10 PM PDT 24
Finished Jun 28 06:00:15 PM PDT 24
Peak memory 199808 kb
Host smart-cfd4d6a4-de48-4904-bfb9-9d29297bad6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014720147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2014720147
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1317172802
Short name T449
Test name
Test status
Simulation time 1892428736 ps
CPU time 7.32 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:22 PM PDT 24
Peak memory 221668 kb
Host smart-50f5d2d4-b395-4e4e-a721-9205f8e7541c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317172802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1317172802
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2552142368
Short name T187
Test name
Test status
Simulation time 244244988 ps
CPU time 1.1 seconds
Started Jun 28 06:00:13 PM PDT 24
Finished Jun 28 06:00:19 PM PDT 24
Peak memory 217420 kb
Host smart-7d8a898c-a4eb-4dd6-9b50-e0f33031ab32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552142368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2552142368
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3249534229
Short name T227
Test name
Test status
Simulation time 228959165 ps
CPU time 0.95 seconds
Started Jun 28 06:00:00 PM PDT 24
Finished Jun 28 06:00:06 PM PDT 24
Peak memory 199920 kb
Host smart-55e0b876-99cb-479a-b9f8-cc879fadccfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249534229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3249534229
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.462196415
Short name T522
Test name
Test status
Simulation time 1291881910 ps
CPU time 5.04 seconds
Started Jun 28 06:00:00 PM PDT 24
Finished Jun 28 06:00:09 PM PDT 24
Peak memory 200388 kb
Host smart-b6835809-d73e-4ed6-ac40-d35b75f48fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462196415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.462196415
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.93224520
Short name T206
Test name
Test status
Simulation time 141451153 ps
CPU time 1.13 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:13 PM PDT 24
Peak memory 200100 kb
Host smart-3e28edca-0b16-4f3a-b54f-6e339431b2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93224520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.93224520
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2336698177
Short name T498
Test name
Test status
Simulation time 198745358 ps
CPU time 1.39 seconds
Started Jun 28 05:59:57 PM PDT 24
Finished Jun 28 06:00:01 PM PDT 24
Peak memory 200276 kb
Host smart-c64e1f02-5338-44d3-9515-1dda4ae42e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336698177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2336698177
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2025435480
Short name T252
Test name
Test status
Simulation time 5472612804 ps
CPU time 25.47 seconds
Started Jun 28 06:00:08 PM PDT 24
Finished Jun 28 06:00:36 PM PDT 24
Peak memory 208604 kb
Host smart-72c7b633-b805-4b94-8fa8-078adc2028ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025435480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2025435480
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2736592793
Short name T374
Test name
Test status
Simulation time 250583887 ps
CPU time 1.8 seconds
Started Jun 28 06:00:08 PM PDT 24
Finished Jun 28 06:00:13 PM PDT 24
Peak memory 200084 kb
Host smart-34e2ff1e-e8d2-4e31-b15c-04f6d8176400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736592793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2736592793
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3089342882
Short name T316
Test name
Test status
Simulation time 163401016 ps
CPU time 1.21 seconds
Started Jun 28 06:00:00 PM PDT 24
Finished Jun 28 06:00:05 PM PDT 24
Peak memory 200096 kb
Host smart-a2c7d348-1d56-4429-896c-c1d10e6e9d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089342882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3089342882
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3894894162
Short name T157
Test name
Test status
Simulation time 83981068 ps
CPU time 0.78 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:14 PM PDT 24
Peak memory 199896 kb
Host smart-f5df5ffc-00d1-4c18-acc9-668c82471333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894894162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3894894162
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.507589657
Short name T480
Test name
Test status
Simulation time 1230032213 ps
CPU time 5.99 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:26 PM PDT 24
Peak memory 217732 kb
Host smart-60320d0d-7f46-44cb-8785-ccaed345cc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507589657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.507589657
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.154895116
Short name T230
Test name
Test status
Simulation time 243943019 ps
CPU time 1.09 seconds
Started Jun 28 05:59:00 PM PDT 24
Finished Jun 28 05:59:02 PM PDT 24
Peak memory 217452 kb
Host smart-e64fe000-293f-4e1c-82d2-a97d7abbb962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154895116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.154895116
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.753156066
Short name T293
Test name
Test status
Simulation time 182410037 ps
CPU time 0.86 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:31 PM PDT 24
Peak memory 199900 kb
Host smart-48b03ce3-3171-46f4-98b9-30f5cd316c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753156066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.753156066
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.345819222
Short name T386
Test name
Test status
Simulation time 839782797 ps
CPU time 4.39 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:17 PM PDT 24
Peak memory 200412 kb
Host smart-075415d0-380e-4ff0-aef7-6994fab7b4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345819222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.345819222
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2607724912
Short name T279
Test name
Test status
Simulation time 169997710 ps
CPU time 1.21 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:13 PM PDT 24
Peak memory 200096 kb
Host smart-84a23741-ad1b-4ba9-b44e-6fca704da39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607724912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2607724912
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2954895408
Short name T496
Test name
Test status
Simulation time 125074973 ps
CPU time 1.2 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:11 PM PDT 24
Peak memory 200284 kb
Host smart-b4deb516-9b15-4fbb-b402-99b4eba9dd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954895408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2954895408
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3636298648
Short name T250
Test name
Test status
Simulation time 1116373927 ps
CPU time 5.35 seconds
Started Jun 28 05:59:03 PM PDT 24
Finished Jun 28 05:59:09 PM PDT 24
Peak memory 200344 kb
Host smart-5a902342-b871-42cf-9139-ab716af8e558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636298648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3636298648
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1579408993
Short name T494
Test name
Test status
Simulation time 479068306 ps
CPU time 2.52 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:14 PM PDT 24
Peak memory 199956 kb
Host smart-51fe9392-14e7-43af-aabe-00196574468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579408993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1579408993
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1034173601
Short name T351
Test name
Test status
Simulation time 223998537 ps
CPU time 1.35 seconds
Started Jun 28 05:58:58 PM PDT 24
Finished Jun 28 05:59:00 PM PDT 24
Peak memory 200072 kb
Host smart-51572c60-154e-48bc-bc43-ad873f390336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034173601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1034173601
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1400938231
Short name T217
Test name
Test status
Simulation time 53866143 ps
CPU time 0.8 seconds
Started Jun 28 05:59:07 PM PDT 24
Finished Jun 28 05:59:16 PM PDT 24
Peak memory 200024 kb
Host smart-c4c06b9e-878c-4fba-b118-9d13c1babfcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400938231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1400938231
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.614426343
Short name T39
Test name
Test status
Simulation time 1913754007 ps
CPU time 7.07 seconds
Started Jun 28 05:59:03 PM PDT 24
Finished Jun 28 05:59:12 PM PDT 24
Peak memory 217344 kb
Host smart-ee24d93b-c11d-4241-9473-ff78afdeea0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614426343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.614426343
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2510312546
Short name T508
Test name
Test status
Simulation time 244070763 ps
CPU time 1.06 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:09 PM PDT 24
Peak memory 217548 kb
Host smart-1e1052cf-66be-4392-adec-a5c00bd0697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510312546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2510312546
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.862614153
Short name T414
Test name
Test status
Simulation time 218328740 ps
CPU time 0.97 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:22 PM PDT 24
Peak memory 199824 kb
Host smart-10cd2c73-99a3-49e7-a31e-a8c8d48243c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862614153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.862614153
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2530894674
Short name T391
Test name
Test status
Simulation time 745951331 ps
CPU time 4.23 seconds
Started Jun 28 05:59:13 PM PDT 24
Finished Jun 28 05:59:37 PM PDT 24
Peak memory 199904 kb
Host smart-49d17adf-6b56-40f1-84a7-fe65d635e724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530894674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2530894674
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.983480588
Short name T168
Test name
Test status
Simulation time 144780962 ps
CPU time 1.1 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:11 PM PDT 24
Peak memory 200100 kb
Host smart-5484a2d9-c0a0-4917-a3d1-bc645dd946b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983480588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.983480588
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1098544015
Short name T67
Test name
Test status
Simulation time 119814778 ps
CPU time 1.19 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:09 PM PDT 24
Peak memory 200320 kb
Host smart-e98fdb57-4f4a-4ed0-a16a-7da7c5634128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098544015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1098544015
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3917011353
Short name T188
Test name
Test status
Simulation time 367124792 ps
CPU time 2.54 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:15 PM PDT 24
Peak memory 200084 kb
Host smart-0b2ef8eb-c144-49a3-9f29-181c6b946606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917011353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3917011353
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4052511960
Short name T171
Test name
Test status
Simulation time 87362611 ps
CPU time 0.84 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:17 PM PDT 24
Peak memory 200088 kb
Host smart-a5c9ca3d-1931-4f58-94f2-544a0174d30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052511960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4052511960
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1084417295
Short name T209
Test name
Test status
Simulation time 80317121 ps
CPU time 0.81 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:06 PM PDT 24
Peak memory 199884 kb
Host smart-e13e077d-fb8b-49d3-9758-0099c1495157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084417295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1084417295
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2752209467
Short name T247
Test name
Test status
Simulation time 1229616233 ps
CPU time 5.74 seconds
Started Jun 28 05:59:07 PM PDT 24
Finished Jun 28 05:59:22 PM PDT 24
Peak memory 217724 kb
Host smart-31c56676-0cff-4cbf-8a3f-041ceb999d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752209467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2752209467
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.194175710
Short name T535
Test name
Test status
Simulation time 244363818 ps
CPU time 1.1 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:06 PM PDT 24
Peak memory 217456 kb
Host smart-bc7aa4f2-63ed-47cc-ab78-d49cde6ede37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194175710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.194175710
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.715331177
Short name T13
Test name
Test status
Simulation time 220694532 ps
CPU time 0.96 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 199884 kb
Host smart-fc1a013e-d865-4398-89b3-56fd9e4b62f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715331177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.715331177
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.748100773
Short name T327
Test name
Test status
Simulation time 1421746535 ps
CPU time 5.73 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:14 PM PDT 24
Peak memory 200368 kb
Host smart-0bf79705-5c7d-4e00-b84c-18d67edaa15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748100773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.748100773
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3946788550
Short name T320
Test name
Test status
Simulation time 106947453 ps
CPU time 1.02 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:20 PM PDT 24
Peak memory 200096 kb
Host smart-ba65d2e1-c780-4ebb-ba63-35c961c31f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946788550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3946788550
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1881197315
Short name T307
Test name
Test status
Simulation time 234959047 ps
CPU time 1.43 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:11 PM PDT 24
Peak memory 200264 kb
Host smart-27a79e74-981b-46fa-a5a0-c05129b3dea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881197315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1881197315
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2245734455
Short name T140
Test name
Test status
Simulation time 2092044827 ps
CPU time 7.49 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:17 PM PDT 24
Peak memory 200340 kb
Host smart-3ff11fdd-6735-4866-aa54-7c01ecef10a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245734455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2245734455
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3912783354
Short name T88
Test name
Test status
Simulation time 331233256 ps
CPU time 2.5 seconds
Started Jun 28 05:59:03 PM PDT 24
Finished Jun 28 05:59:07 PM PDT 24
Peak memory 200092 kb
Host smart-9f82c5e8-1dcd-4016-8d9a-6bf5cdb72cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912783354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3912783354
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3475540929
Short name T454
Test name
Test status
Simulation time 157580893 ps
CPU time 1.34 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:16 PM PDT 24
Peak memory 200376 kb
Host smart-4455188d-1e5c-47b8-be09-2182cfc99789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475540929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3475540929
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1237437021
Short name T296
Test name
Test status
Simulation time 63358212 ps
CPU time 0.79 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:14 PM PDT 24
Peak memory 199900 kb
Host smart-e9111ff5-38ac-4790-8a6b-57f36b41a960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237437021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1237437021
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1004742291
Short name T471
Test name
Test status
Simulation time 1888411091 ps
CPU time 6.82 seconds
Started Jun 28 05:59:11 PM PDT 24
Finished Jun 28 05:59:33 PM PDT 24
Peak memory 217668 kb
Host smart-46374933-7ef0-4fb7-857f-a00694b169ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004742291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1004742291
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2404204397
Short name T40
Test name
Test status
Simulation time 243830106 ps
CPU time 1.1 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:15 PM PDT 24
Peak memory 217464 kb
Host smart-d4277fb7-931c-4028-bba1-b2d966e60195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404204397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2404204397
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1841431485
Short name T211
Test name
Test status
Simulation time 215024806 ps
CPU time 1.02 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:14 PM PDT 24
Peak memory 199904 kb
Host smart-2ee8917c-c836-4a6d-84e3-a36d7835e704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841431485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1841431485
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2053368719
Short name T442
Test name
Test status
Simulation time 1993756363 ps
CPU time 7.62 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:20 PM PDT 24
Peak memory 200512 kb
Host smart-9acbb1db-b20e-4fae-8252-fbeba90ec4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053368719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2053368719
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4227841476
Short name T492
Test name
Test status
Simulation time 110439570 ps
CPU time 1.03 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:21 PM PDT 24
Peak memory 200092 kb
Host smart-864ec711-6cdd-45b6-ae8d-ec1f53a41693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227841476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4227841476
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2626736647
Short name T300
Test name
Test status
Simulation time 188162398 ps
CPU time 1.32 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:13 PM PDT 24
Peak memory 200204 kb
Host smart-aa05dca0-fc38-468d-a3f6-a3ba1c12b343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626736647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2626736647
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3322739824
Short name T136
Test name
Test status
Simulation time 12587550370 ps
CPU time 41.28 seconds
Started Jun 28 05:59:06 PM PDT 24
Finished Jun 28 05:59:53 PM PDT 24
Peak memory 208604 kb
Host smart-26a60a94-d30c-46a2-a40f-b6c7330b5b65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322739824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3322739824
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3122404002
Short name T84
Test name
Test status
Simulation time 115781827 ps
CPU time 1.58 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:09 PM PDT 24
Peak memory 200124 kb
Host smart-92733af0-47bc-480e-b908-6570c3bb300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122404002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3122404002
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3717655541
Short name T482
Test name
Test status
Simulation time 146157582 ps
CPU time 1.08 seconds
Started Jun 28 05:59:05 PM PDT 24
Finished Jun 28 05:59:10 PM PDT 24
Peak memory 200084 kb
Host smart-c26c89b2-48e7-4eba-9626-7b2da86ae94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717655541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3717655541
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2694736237
Short name T61
Test name
Test status
Simulation time 72869239 ps
CPU time 0.78 seconds
Started Jun 28 05:59:17 PM PDT 24
Finished Jun 28 05:59:39 PM PDT 24
Peak memory 199868 kb
Host smart-edf44b2c-6e53-40f0-bfec-55e767312b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694736237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2694736237
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2184611519
Short name T525
Test name
Test status
Simulation time 1223824227 ps
CPU time 5.44 seconds
Started Jun 28 05:59:09 PM PDT 24
Finished Jun 28 05:59:28 PM PDT 24
Peak memory 221552 kb
Host smart-c6e2d407-5a3a-4a83-a1e5-2e421be800a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184611519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2184611519
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1305998325
Short name T234
Test name
Test status
Simulation time 244538619 ps
CPU time 1.11 seconds
Started Jun 28 05:59:12 PM PDT 24
Finished Jun 28 05:59:30 PM PDT 24
Peak memory 217452 kb
Host smart-8202b6a0-5189-4c4f-8cae-581f3685a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305998325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1305998325
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.907439185
Short name T242
Test name
Test status
Simulation time 85105686 ps
CPU time 0.83 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:21 PM PDT 24
Peak memory 199904 kb
Host smart-ebcd424c-f2f8-4174-9f76-1be97bde5e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907439185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.907439185
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3846986115
Short name T116
Test name
Test status
Simulation time 778778365 ps
CPU time 4.25 seconds
Started Jun 28 05:59:03 PM PDT 24
Finished Jun 28 05:59:08 PM PDT 24
Peak memory 200352 kb
Host smart-fb9c45c4-3ab8-405e-8cc9-4bf66d286705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846986115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3846986115
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.4037684104
Short name T75
Test name
Test status
Simulation time 106735734 ps
CPU time 0.97 seconds
Started Jun 28 05:59:08 PM PDT 24
Finished Jun 28 05:59:20 PM PDT 24
Peak memory 200092 kb
Host smart-2e2bba2d-aab7-45d7-b583-77244fc2371c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037684104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.4037684104
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1225207941
Short name T530
Test name
Test status
Simulation time 113983725 ps
CPU time 1.2 seconds
Started Jun 28 05:59:04 PM PDT 24
Finished Jun 28 05:59:07 PM PDT 24
Peak memory 200280 kb
Host smart-41668f4b-4c02-46bc-9ce8-9cbda88d541e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225207941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1225207941
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.756574985
Short name T110
Test name
Test status
Simulation time 7615470129 ps
CPU time 26.31 seconds
Started Jun 28 05:59:10 PM PDT 24
Finished Jun 28 05:59:53 PM PDT 24
Peak memory 200404 kb
Host smart-85ca3b6d-5e6c-451a-9159-1d821775e203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756574985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.756574985
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3276804477
Short name T145
Test name
Test status
Simulation time 392154413 ps
CPU time 2.03 seconds
Started Jun 28 05:59:07 PM PDT 24
Finished Jun 28 05:59:19 PM PDT 24
Peak memory 200080 kb
Host smart-ec9f6cf4-189d-41d7-bc4b-7ec8bfbc9006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276804477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3276804477
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.733510079
Short name T360
Test name
Test status
Simulation time 201900883 ps
CPU time 1.34 seconds
Started Jun 28 05:59:07 PM PDT 24
Finished Jun 28 05:59:16 PM PDT 24
Peak memory 200196 kb
Host smart-d33d539b-7652-4b18-8ded-7cbe821af483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733510079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.733510079
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%