Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8215

1

T1

18

T2

8

T3

32

auto[1]

11087

1

T1

1

T2

1

T3

26

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5971	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6510	1			T1	1		T2	1		T3	19
reset_info_cp[2]	2994	1			T3	12		T4	1		T8	16
reset_info_cp[4]	3930	1			T3	9		T4	1		T8	18
reset_info_cp[8]	108	1			T2	1		T10	2		T40	4
reset_info_cp[16]	113	1			T1	2		T2	1		T10	1
reset_info_cp[32]	101	1			T8	1		T10	1		T40	2
reset_info_cp[64]	91	1			T10	1		T12	1		T40	1
reset_info_cp[128]	104	1			T3	1		T10	3		T12	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3147	1			T3	7		T8	17		T10	54
reset_info_cp[1]	auto[1]	2743	1			T3	11		T4	1		T8	9
reset_info_cp[2]	auto[0]	936	1			T3	6		T10	24		T25	6
reset_info_cp[2]	auto[1]	2058	1			T3	6		T4	1		T8	16
reset_info_cp[4]	auto[0]	1391	1			T3	6		T10	30		T25	6
reset_info_cp[4]	auto[1]	2539	1			T3	3		T4	1		T8	18
reset_info_cp[8]	auto[0]	49	1			T2	1		T10	1		T40	3
reset_info_cp[8]	auto[1]	59	1			T10	1		T40	1		T70	2
reset_info_cp[16]	auto[0]	44	1			T1	2		T2	1		T10	1
reset_info_cp[16]	auto[1]	69	1			T12	2		T70	1		T86	1
reset_info_cp[32]	auto[0]	45	1			T40	1		T41	1		T69	1
reset_info_cp[32]	auto[1]	56	1			T8	1		T10	1		T40	1
reset_info_cp[64]	auto[0]	37	1			T10	1		T40	1		T71	1
reset_info_cp[64]	auto[1]	54	1			T12	1		T70	1		T26	1
reset_info_cp[128]	auto[0]	44	1			T3	1		T10	3		T40	1
reset_info_cp[128]	auto[1]	60	1			T12	1		T40	2		T26	3