Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T542 /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4162401935 Jun 29 06:27:03 PM PDT 24 Jun 29 06:27:10 PM PDT 24 1214030519 ps
T543 /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3379770147 Jun 29 06:26:23 PM PDT 24 Jun 29 06:26:25 PM PDT 24 99995966 ps
T544 /workspace/coverage/default/42.rstmgr_alert_test.905191572 Jun 29 06:27:03 PM PDT 24 Jun 29 06:27:04 PM PDT 24 65904482 ps
T545 /workspace/coverage/default/20.rstmgr_stress_all.779484162 Jun 29 06:26:12 PM PDT 24 Jun 29 06:26:23 PM PDT 24 1888995258 ps
T546 /workspace/coverage/default/5.rstmgr_stress_all.1760943729 Jun 29 06:25:40 PM PDT 24 Jun 29 06:25:55 PM PDT 24 3754928765 ps
T56 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3770123605 Jun 29 06:21:31 PM PDT 24 Jun 29 06:21:32 PM PDT 24 78738395 ps
T57 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3584329770 Jun 29 06:21:48 PM PDT 24 Jun 29 06:21:51 PM PDT 24 420200108 ps
T58 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4132267628 Jun 29 06:21:46 PM PDT 24 Jun 29 06:21:48 PM PDT 24 509122332 ps
T60 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4187634745 Jun 29 06:21:28 PM PDT 24 Jun 29 06:21:30 PM PDT 24 203536251 ps
T92 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2868072958 Jun 29 06:21:49 PM PDT 24 Jun 29 06:21:51 PM PDT 24 102108306 ps
T61 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1126585926 Jun 29 06:21:19 PM PDT 24 Jun 29 06:21:20 PM PDT 24 117905045 ps
T547 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.912577218 Jun 29 06:21:30 PM PDT 24 Jun 29 06:21:31 PM PDT 24 135190540 ps
T93 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2298602439 Jun 29 06:21:20 PM PDT 24 Jun 29 06:21:21 PM PDT 24 77119263 ps
T102 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.4243585324 Jun 29 06:21:30 PM PDT 24 Jun 29 06:21:33 PM PDT 24 420624926 ps
T548 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3293885664 Jun 29 06:21:46 PM PDT 24 Jun 29 06:21:47 PM PDT 24 76856581 ps
T549 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2747998414 Jun 29 06:21:29 PM PDT 24 Jun 29 06:21:30 PM PDT 24 64649104 ps
T62 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3311205988 Jun 29 06:21:47 PM PDT 24 Jun 29 06:21:49 PM PDT 24 210488276 ps
T94 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3827018190 Jun 29 06:21:55 PM PDT 24 Jun 29 06:21:56 PM PDT 24 142998971 ps
T75 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2744388241 Jun 29 06:21:35 PM PDT 24 Jun 29 06:21:37 PM PDT 24 194448658 ps
T128 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3842865312 Jun 29 06:21:19 PM PDT 24 Jun 29 06:21:30 PM PDT 24 2296041788 ps
T76 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.731368065 Jun 29 06:21:21 PM PDT 24 Jun 29 06:21:23 PM PDT 24 195615400 ps
T63 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2507741878 Jun 29 06:21:42 PM PDT 24 Jun 29 06:21:45 PM PDT 24 762292827 ps
T64 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.192180577 Jun 29 06:21:52 PM PDT 24 Jun 29 06:21:54 PM PDT 24 489280072 ps
T77 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1116440378 Jun 29 06:21:37 PM PDT 24 Jun 29 06:21:40 PM PDT 24 811081983 ps
T78 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3094626486 Jun 29 06:21:36 PM PDT 24 Jun 29 06:21:38 PM PDT 24 105285093 ps
T79 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.931901013 Jun 29 06:21:34 PM PDT 24 Jun 29 06:21:36 PM PDT 24 185617584 ps
T95 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2703479560 Jun 29 06:21:39 PM PDT 24 Jun 29 06:21:41 PM PDT 24 177398282 ps
T96 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1836760113 Jun 29 06:21:45 PM PDT 24 Jun 29 06:21:47 PM PDT 24 115115065 ps
T80 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2062407548 Jun 29 06:21:39 PM PDT 24 Jun 29 06:21:41 PM PDT 24 98372569 ps
T103 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2661866827 Jun 29 06:21:31 PM PDT 24 Jun 29 06:21:35 PM PDT 24 534284513 ps
T97 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3345336315 Jun 29 06:21:18 PM PDT 24 Jun 29 06:21:19 PM PDT 24 90110055 ps
T115 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.352895521 Jun 29 06:21:28 PM PDT 24 Jun 29 06:21:30 PM PDT 24 646745005 ps
T550 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3715318787 Jun 29 06:21:32 PM PDT 24 Jun 29 06:21:33 PM PDT 24 101454810 ps
T98 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.731674656 Jun 29 06:21:34 PM PDT 24 Jun 29 06:21:35 PM PDT 24 134822278 ps
T107 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1370200262 Jun 29 06:21:21 PM PDT 24 Jun 29 06:21:24 PM PDT 24 386150054 ps
T551 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2930983384 Jun 29 06:21:29 PM PDT 24 Jun 29 06:21:32 PM PDT 24 507998547 ps
T114 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2688847341 Jun 29 06:21:40 PM PDT 24 Jun 29 06:21:43 PM PDT 24 427625601 ps
T116 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.311511176 Jun 29 06:21:30 PM PDT 24 Jun 29 06:21:34 PM PDT 24 763070320 ps
T99 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1893814088 Jun 29 06:21:29 PM PDT 24 Jun 29 06:21:31 PM PDT 24 141000073 ps
T108 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1794302432 Jun 29 06:21:35 PM PDT 24 Jun 29 06:21:38 PM PDT 24 279736188 ps
T112 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.621540742 Jun 29 06:21:30 PM PDT 24 Jun 29 06:21:33 PM PDT 24 477530641 ps
T113 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4134596721 Jun 29 06:21:48 PM PDT 24 Jun 29 06:21:51 PM PDT 24 291773575 ps
T100 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4150061326 Jun 29 06:21:36 PM PDT 24 Jun 29 06:21:37 PM PDT 24 157912212 ps
T104 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2646997847 Jun 29 06:21:27 PM PDT 24 Jun 29 06:21:31 PM PDT 24 494990003 ps
T552 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.804132978 Jun 29 06:21:19 PM PDT 24 Jun 29 06:21:22 PM PDT 24 348955240 ps
T553 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4014962665 Jun 29 06:21:39 PM PDT 24 Jun 29 06:21:41 PM PDT 24 192983954 ps
T105 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.752681855 Jun 29 06:21:30 PM PDT 24 Jun 29 06:21:33 PM PDT 24 495109578 ps
T554 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3666054412 Jun 29 06:21:47 PM PDT 24 Jun 29 06:21:49 PM PDT 24 495872958 ps
T101 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.163798675 Jun 29 06:21:32 PM PDT 24 Jun 29 06:21:33 PM PDT 24 125899520 ps
T555 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1441481099 Jun 29 06:21:21 PM PDT 24 Jun 29 06:21:26 PM PDT 24 792709965 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3880865975 Jun 29 06:21:19 PM PDT 24 Jun 29 06:21:22 PM PDT 24 352443120 ps
T110 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3280565281 Jun 29 06:21:48 PM PDT 24 Jun 29 06:21:51 PM PDT 24 1093549399 ps
T557 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2589355423 Jun 29 06:21:20 PM PDT 24 Jun 29 06:21:23 PM PDT 24 215442471 ps
T558 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.925806999 Jun 29 06:21:29 PM PDT 24 Jun 29 06:21:31 PM PDT 24 224829793 ps
T559 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.624453689 Jun 29 06:21:38 PM PDT 24 Jun 29 06:21:40 PM PDT 24 74207958 ps
T106 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1444682569 Jun 29 06:21:41 PM PDT 24 Jun 29 06:21:44 PM PDT 24 188819780 ps
T127 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.116983252 Jun 29 06:21:19 PM PDT 24 Jun 29 06:21:23 PM PDT 24 1010296664 ps
T560 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3811608328 Jun 29 06:21:35 PM PDT 24 Jun 29 06:21:37 PM PDT 24 129909540 ps
T561 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4133957962 Jun 29 06:21:40 PM PDT 24 Jun 29 06:21:41 PM PDT 24 74029242 ps
T562 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1805280966 Jun 29 06:21:36 PM PDT 24 Jun 29 06:21:37 PM PDT 24 115697091 ps
T563 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1683634046 Jun 29 06:21:31 PM PDT 24 Jun 29 06:21:32 PM PDT 24 120198913 ps
T564 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2117247305 Jun 29 06:21:27 PM PDT 24 Jun 29 06:21:29 PM PDT 24 206444553 ps
T111 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4048198523 Jun 29 06:21:20 PM PDT 24 Jun 29 06:21:24 PM PDT 24 782169650 ps
T565 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2085182071 Jun 29 06:21:54 PM PDT 24 Jun 29 06:21:56 PM PDT 24 248320980 ps
T566 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3182590267 Jun 29 06:21:44 PM PDT 24 Jun 29 06:21:45 PM PDT 24 83399841 ps
T567 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.970060335 Jun 29 06:21:36 PM PDT 24 Jun 29 06:21:39 PM PDT 24 468001348 ps
T568 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3212486894 Jun 29 06:21:30 PM PDT 24 Jun 29 06:21:35 PM PDT 24 584582115 ps
T569 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1314982874 Jun 29 06:21:34 PM PDT 24 Jun 29 06:21:38 PM PDT 24 872587730 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1602844769 Jun 29 06:21:30 PM PDT 24 Jun 29 06:21:31 PM PDT 24 83784945 ps
T571 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3582938739 Jun 29 06:21:21 PM PDT 24 Jun 29 06:21:22 PM PDT 24 145957275 ps
T572 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3062896402 Jun 29 06:21:36 PM PDT 24 Jun 29 06:21:38 PM PDT 24 210191795 ps
T573 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1496876670 Jun 29 06:21:20 PM PDT 24 Jun 29 06:21:24 PM PDT 24 959501275 ps
T574 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.480504380 Jun 29 06:21:35 PM PDT 24 Jun 29 06:21:38 PM PDT 24 211399021 ps
T575 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2715897504 Jun 29 06:21:39 PM PDT 24 Jun 29 06:21:43 PM PDT 24 1049287294 ps
T576 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1332170250 Jun 29 06:21:48 PM PDT 24 Jun 29 06:21:50 PM PDT 24 192362553 ps
T577 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3536232024 Jun 29 06:21:29 PM PDT 24 Jun 29 06:21:36 PM PDT 24 1179783607 ps
T578 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3183164483 Jun 29 06:21:19 PM PDT 24 Jun 29 06:21:20 PM PDT 24 118106098 ps
T579 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2955153945 Jun 29 06:21:35 PM PDT 24 Jun 29 06:21:36 PM PDT 24 58773132 ps
T580 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1213250347 Jun 29 06:21:49 PM PDT 24 Jun 29 06:21:50 PM PDT 24 126230158 ps
T581 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.574191474 Jun 29 06:21:48 PM PDT 24 Jun 29 06:21:49 PM PDT 24 66488281 ps
T582 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3183301248 Jun 29 06:21:20 PM PDT 24 Jun 29 06:21:23 PM PDT 24 213704316 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.182893589 Jun 29 06:21:19 PM PDT 24 Jun 29 06:21:21 PM PDT 24 98116364 ps
T584 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2584036091 Jun 29 06:21:46 PM PDT 24 Jun 29 06:21:47 PM PDT 24 185110934 ps
T585 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2989954640 Jun 29 06:21:28 PM PDT 24 Jun 29 06:21:31 PM PDT 24 178439965 ps
T586 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2179579737 Jun 29 06:21:52 PM PDT 24 Jun 29 06:21:54 PM PDT 24 147624547 ps
T587 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1492172975 Jun 29 06:21:20 PM PDT 24 Jun 29 06:21:21 PM PDT 24 60579284 ps
T588 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1710093516 Jun 29 06:21:47 PM PDT 24 Jun 29 06:21:49 PM PDT 24 214689398 ps
T589 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.763281731 Jun 29 06:21:36 PM PDT 24 Jun 29 06:21:40 PM PDT 24 575067584 ps
T590 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1400885730 Jun 29 06:21:46 PM PDT 24 Jun 29 06:21:49 PM PDT 24 124202646 ps
T591 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3400587664 Jun 29 06:21:41 PM PDT 24 Jun 29 06:21:43 PM PDT 24 79536420 ps
T592 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4200704535 Jun 29 06:21:28 PM PDT 24 Jun 29 06:21:29 PM PDT 24 188819479 ps
T593 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2456137099 Jun 29 06:21:52 PM PDT 24 Jun 29 06:21:53 PM PDT 24 61405620 ps
T594 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2530579945 Jun 29 06:21:48 PM PDT 24 Jun 29 06:21:49 PM PDT 24 60119202 ps
T595 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.703813322 Jun 29 06:21:50 PM PDT 24 Jun 29 06:21:52 PM PDT 24 145483243 ps
T596 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1578467540 Jun 29 06:21:49 PM PDT 24 Jun 29 06:21:51 PM PDT 24 417199224 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2552180079 Jun 29 06:21:28 PM PDT 24 Jun 29 06:21:33 PM PDT 24 807164432 ps
T109 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4224140540 Jun 29 06:21:27 PM PDT 24 Jun 29 06:21:31 PM PDT 24 784202273 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.619309895 Jun 29 06:21:20 PM PDT 24 Jun 29 06:21:23 PM PDT 24 263417473 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1799246989 Jun 29 06:21:20 PM PDT 24 Jun 29 06:21:27 PM PDT 24 477778667 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.431040166 Jun 29 06:21:20 PM PDT 24 Jun 29 06:21:21 PM PDT 24 97452687 ps
T601 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3230239715 Jun 29 06:21:28 PM PDT 24 Jun 29 06:21:30 PM PDT 24 82163419 ps
T602 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1125879283 Jun 29 06:21:19 PM PDT 24 Jun 29 06:21:20 PM PDT 24 121782785 ps
T603 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3423909275 Jun 29 06:21:36 PM PDT 24 Jun 29 06:21:37 PM PDT 24 127325087 ps
T604 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3758654010 Jun 29 06:21:35 PM PDT 24 Jun 29 06:21:39 PM PDT 24 195661090 ps
T605 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1444215546 Jun 29 06:21:23 PM PDT 24 Jun 29 06:21:25 PM PDT 24 102577333 ps
T606 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.730675662 Jun 29 06:21:44 PM PDT 24 Jun 29 06:21:45 PM PDT 24 93647429 ps
T607 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2028953054 Jun 29 06:21:44 PM PDT 24 Jun 29 06:21:45 PM PDT 24 62818364 ps
T608 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1472794279 Jun 29 06:21:20 PM PDT 24 Jun 29 06:21:21 PM PDT 24 72488645 ps
T609 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2693181350 Jun 29 06:21:20 PM PDT 24 Jun 29 06:21:23 PM PDT 24 225500298 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1125945977 Jun 29 06:21:29 PM PDT 24 Jun 29 06:21:30 PM PDT 24 183695656 ps
T611 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.48794998 Jun 29 06:21:39 PM PDT 24 Jun 29 06:21:41 PM PDT 24 73777584 ps
T612 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1360650928 Jun 29 06:21:47 PM PDT 24 Jun 29 06:21:49 PM PDT 24 137828971 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.422175461 Jun 29 06:21:28 PM PDT 24 Jun 29 06:21:30 PM PDT 24 78530407 ps
T614 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1961226277 Jun 29 06:21:37 PM PDT 24 Jun 29 06:21:39 PM PDT 24 66496951 ps
T615 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.617083360 Jun 29 06:21:48 PM PDT 24 Jun 29 06:21:49 PM PDT 24 186581565 ps
T616 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3297566839 Jun 29 06:21:31 PM PDT 24 Jun 29 06:21:33 PM PDT 24 83440880 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3309800432 Jun 29 06:21:31 PM PDT 24 Jun 29 06:21:33 PM PDT 24 190833021 ps
T618 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2112793529 Jun 29 06:21:37 PM PDT 24 Jun 29 06:21:38 PM PDT 24 69743519 ps
T619 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3849690899 Jun 29 06:21:35 PM PDT 24 Jun 29 06:21:37 PM PDT 24 223156269 ps
T620 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2155624226 Jun 29 06:21:47 PM PDT 24 Jun 29 06:21:49 PM PDT 24 215655102 ps

Test location /workspace/coverage/default/19.rstmgr_stress_all.2447895671
Short name T10
Test name
Test status
Simulation time 5866363769 ps
CPU time 27.42 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 208608 kb
Host smart-55b5c403-550a-48bd-bc86-61c7db285bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447895671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2447895671
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.4252161659
Short name T35
Test name
Test status
Simulation time 525668690 ps
CPU time 2.92 seconds
Started Jun 29 06:26:52 PM PDT 24
Finished Jun 29 06:26:56 PM PDT 24
Peak memory 200084 kb
Host smart-d2d4e68b-6c80-47c2-b181-37fb0b36d3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252161659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.4252161659
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3584329770
Short name T57
Test name
Test status
Simulation time 420200108 ps
CPU time 1.79 seconds
Started Jun 29 06:21:48 PM PDT 24
Finished Jun 29 06:21:51 PM PDT 24
Peak memory 200424 kb
Host smart-31c7c539-cd14-464f-a094-8ff9f8029e67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584329770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3584329770
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.647271912
Short name T23
Test name
Test status
Simulation time 16556044536 ps
CPU time 29.79 seconds
Started Jun 29 06:25:36 PM PDT 24
Finished Jun 29 06:26:06 PM PDT 24
Peak memory 217136 kb
Host smart-12bae638-a649-4463-952e-87cfa9c527c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647271912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.647271912
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3171959720
Short name T26
Test name
Test status
Simulation time 1222627671 ps
CPU time 5.86 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:18 PM PDT 24
Peak memory 221628 kb
Host smart-ea88765d-fad9-4dea-b5e6-2f1a268fa736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171959720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3171959720
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2744388241
Short name T75
Test name
Test status
Simulation time 194448658 ps
CPU time 2.16 seconds
Started Jun 29 06:21:35 PM PDT 24
Finished Jun 29 06:21:37 PM PDT 24
Peak memory 208696 kb
Host smart-772bbef9-ec52-4740-9467-3dd8f86ad316
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744388241 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2744388241
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2207948275
Short name T37
Test name
Test status
Simulation time 107955422 ps
CPU time 1.05 seconds
Started Jun 29 06:26:04 PM PDT 24
Finished Jun 29 06:26:06 PM PDT 24
Peak memory 200060 kb
Host smart-505421cd-11bb-4a06-a664-777e60d926b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207948275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2207948275
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2507741878
Short name T63
Test name
Test status
Simulation time 762292827 ps
CPU time 2.67 seconds
Started Jun 29 06:21:42 PM PDT 24
Finished Jun 29 06:21:45 PM PDT 24
Peak memory 200256 kb
Host smart-6a65cd9f-1a83-4262-bc78-349adfe146a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507741878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2507741878
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3683954839
Short name T5
Test name
Test status
Simulation time 79070901 ps
CPU time 0.83 seconds
Started Jun 29 06:25:33 PM PDT 24
Finished Jun 29 06:25:34 PM PDT 24
Peak memory 199840 kb
Host smart-960cf9d9-41df-4ca2-a113-6ac0602eb7b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683954839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3683954839
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3824801652
Short name T85
Test name
Test status
Simulation time 1957132919 ps
CPU time 7.98 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:19 PM PDT 24
Peak memory 200324 kb
Host smart-c10d7663-7324-461c-90ac-896f6d4c7915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824801652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3824801652
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2264850754
Short name T46
Test name
Test status
Simulation time 1220504924 ps
CPU time 5.93 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:25:57 PM PDT 24
Peak memory 217776 kb
Host smart-f6f5e885-da20-443c-a681-238d5d851ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264850754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2264850754
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3247007374
Short name T186
Test name
Test status
Simulation time 125651936 ps
CPU time 1.19 seconds
Started Jun 29 06:25:34 PM PDT 24
Finished Jun 29 06:25:35 PM PDT 24
Peak memory 200096 kb
Host smart-264a3fac-7b1b-4b24-a175-6c929df1489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247007374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3247007374
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1370200262
Short name T107
Test name
Test status
Simulation time 386150054 ps
CPU time 2.9 seconds
Started Jun 29 06:21:21 PM PDT 24
Finished Jun 29 06:21:24 PM PDT 24
Peak memory 208556 kb
Host smart-a9db7433-db4a-4fa5-a523-4383ddbef2dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370200262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1370200262
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.116983252
Short name T127
Test name
Test status
Simulation time 1010296664 ps
CPU time 3.3 seconds
Started Jun 29 06:21:19 PM PDT 24
Finished Jun 29 06:21:23 PM PDT 24
Peak memory 200440 kb
Host smart-af8ae8fe-01a7-442a-9bf5-4bb6269bade2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116983252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
116983252
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.700795456
Short name T286
Test name
Test status
Simulation time 7376719326 ps
CPU time 35.31 seconds
Started Jun 29 06:25:29 PM PDT 24
Finished Jun 29 06:26:05 PM PDT 24
Peak memory 208608 kb
Host smart-e08f599b-a525-4105-9292-971c90ca918f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700795456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.700795456
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1710093516
Short name T588
Test name
Test status
Simulation time 214689398 ps
CPU time 1.79 seconds
Started Jun 29 06:21:47 PM PDT 24
Finished Jun 29 06:21:49 PM PDT 24
Peak memory 208448 kb
Host smart-79ab6b6d-2acd-409e-bb22-bb77141e92ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710093516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1710093516
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2298602439
Short name T93
Test name
Test status
Simulation time 77119263 ps
CPU time 0.87 seconds
Started Jun 29 06:21:20 PM PDT 24
Finished Jun 29 06:21:21 PM PDT 24
Peak memory 200160 kb
Host smart-ac7cb295-e8de-499f-b393-28c5b958dba7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298602439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2298602439
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3679858832
Short name T22
Test name
Test status
Simulation time 123610461 ps
CPU time 0.83 seconds
Started Jun 29 06:25:29 PM PDT 24
Finished Jun 29 06:25:30 PM PDT 24
Peak memory 199848 kb
Host smart-478b6b11-b0a6-4821-9c94-3a2707f05652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679858832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3679858832
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1215854652
Short name T27
Test name
Test status
Simulation time 1224698410 ps
CPU time 6 seconds
Started Jun 29 06:25:58 PM PDT 24
Finished Jun 29 06:26:04 PM PDT 24
Peak memory 221676 kb
Host smart-a7e7cb5a-aaa8-4c38-8b58-cf56e5b2b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215854652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1215854652
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4048198523
Short name T111
Test name
Test status
Simulation time 782169650 ps
CPU time 2.92 seconds
Started Jun 29 06:21:20 PM PDT 24
Finished Jun 29 06:21:24 PM PDT 24
Peak memory 200500 kb
Host smart-3c3fc151-b01b-430d-8a4d-a5f305420537
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048198523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.4048198523
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.804132978
Short name T552
Test name
Test status
Simulation time 348955240 ps
CPU time 2.32 seconds
Started Jun 29 06:21:19 PM PDT 24
Finished Jun 29 06:21:22 PM PDT 24
Peak memory 200380 kb
Host smart-0c2ed39c-0821-47f8-b44e-3a4c3fbd0681
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804132978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.804132978
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1799246989
Short name T599
Test name
Test status
Simulation time 477778667 ps
CPU time 6.36 seconds
Started Jun 29 06:21:20 PM PDT 24
Finished Jun 29 06:21:27 PM PDT 24
Peak memory 200384 kb
Host smart-0d83fd6f-da8b-48c6-bcbc-2d38a18ce8d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799246989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
799246989
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3183164483
Short name T578
Test name
Test status
Simulation time 118106098 ps
CPU time 0.89 seconds
Started Jun 29 06:21:19 PM PDT 24
Finished Jun 29 06:21:20 PM PDT 24
Peak memory 200148 kb
Host smart-c2d9ca87-c3ac-4b25-a223-31b1a770e9df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183164483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
183164483
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.731368065
Short name T76
Test name
Test status
Simulation time 195615400 ps
CPU time 1.41 seconds
Started Jun 29 06:21:21 PM PDT 24
Finished Jun 29 06:21:23 PM PDT 24
Peak memory 208504 kb
Host smart-2b0820d2-eb1b-493d-a59c-9b61bfd4e4ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731368065 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.731368065
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2589355423
Short name T557
Test name
Test status
Simulation time 215442471 ps
CPU time 1.48 seconds
Started Jun 29 06:21:20 PM PDT 24
Finished Jun 29 06:21:23 PM PDT 24
Peak memory 200424 kb
Host smart-1e25c9d5-357d-4f75-8d29-c67f1aad3a9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589355423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2589355423
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.619309895
Short name T598
Test name
Test status
Simulation time 263417473 ps
CPU time 2.22 seconds
Started Jun 29 06:21:20 PM PDT 24
Finished Jun 29 06:21:23 PM PDT 24
Peak memory 216640 kb
Host smart-e4148683-4ad4-4777-b1b2-98700c6a17b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619309895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.619309895
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3880865975
Short name T556
Test name
Test status
Simulation time 352443120 ps
CPU time 2.46 seconds
Started Jun 29 06:21:19 PM PDT 24
Finished Jun 29 06:21:22 PM PDT 24
Peak memory 200436 kb
Host smart-a61058cf-9efa-44cb-b0eb-83ada583702c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880865975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
880865975
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1441481099
Short name T555
Test name
Test status
Simulation time 792709965 ps
CPU time 4.5 seconds
Started Jun 29 06:21:21 PM PDT 24
Finished Jun 29 06:21:26 PM PDT 24
Peak memory 200444 kb
Host smart-efc53547-2b57-45b4-87bf-91b89cbda287
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441481099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
441481099
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.431040166
Short name T600
Test name
Test status
Simulation time 97452687 ps
CPU time 0.87 seconds
Started Jun 29 06:21:20 PM PDT 24
Finished Jun 29 06:21:21 PM PDT 24
Peak memory 200212 kb
Host smart-69c3f2dd-8c08-42ba-a637-bbc90e80ea6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431040166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.431040166
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1126585926
Short name T61
Test name
Test status
Simulation time 117905045 ps
CPU time 1.03 seconds
Started Jun 29 06:21:19 PM PDT 24
Finished Jun 29 06:21:20 PM PDT 24
Peak memory 200348 kb
Host smart-25ff2d31-31c3-4d31-a137-ba42ad696ee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126585926 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1126585926
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1472794279
Short name T608
Test name
Test status
Simulation time 72488645 ps
CPU time 0.82 seconds
Started Jun 29 06:21:20 PM PDT 24
Finished Jun 29 06:21:21 PM PDT 24
Peak memory 200136 kb
Host smart-5766b4b2-a5a5-419c-a59e-f08c31c61260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472794279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1472794279
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1125879283
Short name T602
Test name
Test status
Simulation time 121782785 ps
CPU time 1.11 seconds
Started Jun 29 06:21:19 PM PDT 24
Finished Jun 29 06:21:20 PM PDT 24
Peak memory 200288 kb
Host smart-c555d674-eab5-4168-9ced-e6ac0d783523
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125879283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1125879283
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.931901013
Short name T79
Test name
Test status
Simulation time 185617584 ps
CPU time 1.24 seconds
Started Jun 29 06:21:34 PM PDT 24
Finished Jun 29 06:21:36 PM PDT 24
Peak memory 208552 kb
Host smart-36851ad7-af93-43c5-b335-628e6f5083d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931901013 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.931901013
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3400587664
Short name T591
Test name
Test status
Simulation time 79536420 ps
CPU time 0.84 seconds
Started Jun 29 06:21:41 PM PDT 24
Finished Jun 29 06:21:43 PM PDT 24
Peak memory 200044 kb
Host smart-a4d0ef44-e915-4970-818b-1eef972a70eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400587664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3400587664
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3423909275
Short name T603
Test name
Test status
Simulation time 127325087 ps
CPU time 1.28 seconds
Started Jun 29 06:21:36 PM PDT 24
Finished Jun 29 06:21:37 PM PDT 24
Peak memory 200408 kb
Host smart-2c1e9344-35fd-4c6e-b5d5-237ffef05f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423909275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3423909275
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3758654010
Short name T604
Test name
Test status
Simulation time 195661090 ps
CPU time 2.72 seconds
Started Jun 29 06:21:35 PM PDT 24
Finished Jun 29 06:21:39 PM PDT 24
Peak memory 208564 kb
Host smart-30074048-f889-463d-b854-f64b30670870
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758654010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3758654010
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1116440378
Short name T77
Test name
Test status
Simulation time 811081983 ps
CPU time 2.83 seconds
Started Jun 29 06:21:37 PM PDT 24
Finished Jun 29 06:21:40 PM PDT 24
Peak memory 200444 kb
Host smart-e9444b5d-09d1-4ed4-aa36-aec28d2e043c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116440378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1116440378
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3094626486
Short name T78
Test name
Test status
Simulation time 105285093 ps
CPU time 0.96 seconds
Started Jun 29 06:21:36 PM PDT 24
Finished Jun 29 06:21:38 PM PDT 24
Peak memory 200360 kb
Host smart-97f1a788-5fba-44b4-93d9-b4c7147cec83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094626486 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3094626486
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.624453689
Short name T559
Test name
Test status
Simulation time 74207958 ps
CPU time 0.87 seconds
Started Jun 29 06:21:38 PM PDT 24
Finished Jun 29 06:21:40 PM PDT 24
Peak memory 200416 kb
Host smart-79dd690a-49d4-481a-90b3-af8d23573ec1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624453689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.624453689
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4150061326
Short name T100
Test name
Test status
Simulation time 157912212 ps
CPU time 1.26 seconds
Started Jun 29 06:21:36 PM PDT 24
Finished Jun 29 06:21:37 PM PDT 24
Peak memory 200280 kb
Host smart-066452cf-a7d3-4ec3-8f99-cf0e1d058fcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150061326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.4150061326
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3849690899
Short name T619
Test name
Test status
Simulation time 223156269 ps
CPU time 1.76 seconds
Started Jun 29 06:21:35 PM PDT 24
Finished Jun 29 06:21:37 PM PDT 24
Peak memory 208516 kb
Host smart-49fc7ebc-dbce-41fc-94e9-39082cd37954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849690899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3849690899
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2715897504
Short name T575
Test name
Test status
Simulation time 1049287294 ps
CPU time 3.25 seconds
Started Jun 29 06:21:39 PM PDT 24
Finished Jun 29 06:21:43 PM PDT 24
Peak memory 200496 kb
Host smart-0f701d34-ab40-4265-aeaa-a2c6e8be6861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715897504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2715897504
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2062407548
Short name T80
Test name
Test status
Simulation time 98372569 ps
CPU time 0.98 seconds
Started Jun 29 06:21:39 PM PDT 24
Finished Jun 29 06:21:41 PM PDT 24
Peak memory 200360 kb
Host smart-cac99f37-4470-4db0-bf00-b8b48b3d2704
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062407548 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2062407548
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2955153945
Short name T579
Test name
Test status
Simulation time 58773132 ps
CPU time 0.72 seconds
Started Jun 29 06:21:35 PM PDT 24
Finished Jun 29 06:21:36 PM PDT 24
Peak memory 200052 kb
Host smart-d2957c29-6368-4da5-9ccd-d0729904f752
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955153945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2955153945
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.731674656
Short name T98
Test name
Test status
Simulation time 134822278 ps
CPU time 1.33 seconds
Started Jun 29 06:21:34 PM PDT 24
Finished Jun 29 06:21:35 PM PDT 24
Peak memory 200332 kb
Host smart-ff95ee7f-ca7c-48c4-8c61-bc7bb6988845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731674656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.731674656
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.763281731
Short name T589
Test name
Test status
Simulation time 575067584 ps
CPU time 3.93 seconds
Started Jun 29 06:21:36 PM PDT 24
Finished Jun 29 06:21:40 PM PDT 24
Peak memory 208568 kb
Host smart-c66b34b9-b1d7-455b-a31a-2a8333305f77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763281731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.763281731
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1314982874
Short name T569
Test name
Test status
Simulation time 872587730 ps
CPU time 3.43 seconds
Started Jun 29 06:21:34 PM PDT 24
Finished Jun 29 06:21:38 PM PDT 24
Peak memory 200432 kb
Host smart-1ea7aba5-9a41-401d-87e8-b7420e3b41d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314982874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1314982874
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2112793529
Short name T618
Test name
Test status
Simulation time 69743519 ps
CPU time 0.79 seconds
Started Jun 29 06:21:37 PM PDT 24
Finished Jun 29 06:21:38 PM PDT 24
Peak memory 200228 kb
Host smart-98d24431-fd26-4c46-b986-7dd1ae80379a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112793529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2112793529
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2703479560
Short name T95
Test name
Test status
Simulation time 177398282 ps
CPU time 1.41 seconds
Started Jun 29 06:21:39 PM PDT 24
Finished Jun 29 06:21:41 PM PDT 24
Peak memory 200288 kb
Host smart-132bd62e-ee71-4463-aa0b-453a5fcbc814
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703479560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2703479560
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3062896402
Short name T572
Test name
Test status
Simulation time 210191795 ps
CPU time 1.66 seconds
Started Jun 29 06:21:36 PM PDT 24
Finished Jun 29 06:21:38 PM PDT 24
Peak memory 208444 kb
Host smart-9d3e542a-8c9d-4c0f-9c7e-e83392b04d68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062896402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3062896402
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.970060335
Short name T567
Test name
Test status
Simulation time 468001348 ps
CPU time 2.05 seconds
Started Jun 29 06:21:36 PM PDT 24
Finished Jun 29 06:21:39 PM PDT 24
Peak memory 200500 kb
Host smart-85853c7f-c00b-45f6-8162-9444e4ddf31d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970060335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.970060335
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.617083360
Short name T615
Test name
Test status
Simulation time 186581565 ps
CPU time 1.28 seconds
Started Jun 29 06:21:48 PM PDT 24
Finished Jun 29 06:21:49 PM PDT 24
Peak memory 208552 kb
Host smart-1e1d1837-4b77-4531-be0e-7f6f97c1d941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617083360 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.617083360
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.574191474
Short name T581
Test name
Test status
Simulation time 66488281 ps
CPU time 0.84 seconds
Started Jun 29 06:21:48 PM PDT 24
Finished Jun 29 06:21:49 PM PDT 24
Peak memory 200200 kb
Host smart-0505ce2e-4acd-4f5e-a3a3-5982bf692550
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574191474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.574191474
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1213250347
Short name T580
Test name
Test status
Simulation time 126230158 ps
CPU time 1.19 seconds
Started Jun 29 06:21:49 PM PDT 24
Finished Jun 29 06:21:50 PM PDT 24
Peak memory 200288 kb
Host smart-ef95b3fc-d1e8-4b75-b13c-188cef23d600
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213250347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1213250347
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1444682569
Short name T106
Test name
Test status
Simulation time 188819780 ps
CPU time 2.47 seconds
Started Jun 29 06:21:41 PM PDT 24
Finished Jun 29 06:21:44 PM PDT 24
Peak memory 208448 kb
Host smart-74f04067-b350-4682-9609-a3c11503b59e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444682569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1444682569
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3666054412
Short name T554
Test name
Test status
Simulation time 495872958 ps
CPU time 2.06 seconds
Started Jun 29 06:21:47 PM PDT 24
Finished Jun 29 06:21:49 PM PDT 24
Peak memory 200432 kb
Host smart-d7d0a2d7-cd48-4139-9cc0-ef71f428b932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666054412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3666054412
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2584036091
Short name T584
Test name
Test status
Simulation time 185110934 ps
CPU time 1.26 seconds
Started Jun 29 06:21:46 PM PDT 24
Finished Jun 29 06:21:47 PM PDT 24
Peak memory 200332 kb
Host smart-195f420f-6c6f-4804-8b5c-440b9067c2ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584036091 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2584036091
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2530579945
Short name T594
Test name
Test status
Simulation time 60119202 ps
CPU time 0.8 seconds
Started Jun 29 06:21:48 PM PDT 24
Finished Jun 29 06:21:49 PM PDT 24
Peak memory 200228 kb
Host smart-05558f9b-e9e3-4201-b7ef-2a31f5a3507e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530579945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2530579945
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1836760113
Short name T96
Test name
Test status
Simulation time 115115065 ps
CPU time 1.03 seconds
Started Jun 29 06:21:45 PM PDT 24
Finished Jun 29 06:21:47 PM PDT 24
Peak memory 200188 kb
Host smart-609bd6df-e6c9-4144-bc81-f344e1a443c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836760113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1836760113
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2155624226
Short name T620
Test name
Test status
Simulation time 215655102 ps
CPU time 1.91 seconds
Started Jun 29 06:21:47 PM PDT 24
Finished Jun 29 06:21:49 PM PDT 24
Peak memory 210524 kb
Host smart-92b25972-3550-4630-bf54-156b9e3e765f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155624226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2155624226
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3280565281
Short name T110
Test name
Test status
Simulation time 1093549399 ps
CPU time 2.97 seconds
Started Jun 29 06:21:48 PM PDT 24
Finished Jun 29 06:21:51 PM PDT 24
Peak memory 200404 kb
Host smart-8aec2990-4e4c-4fda-9e6a-4792d1b868a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280565281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3280565281
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1332170250
Short name T576
Test name
Test status
Simulation time 192362553 ps
CPU time 1.32 seconds
Started Jun 29 06:21:48 PM PDT 24
Finished Jun 29 06:21:50 PM PDT 24
Peak memory 208468 kb
Host smart-24fb6c50-fa9d-4275-a082-1e26143fb9e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332170250 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1332170250
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.730675662
Short name T606
Test name
Test status
Simulation time 93647429 ps
CPU time 0.86 seconds
Started Jun 29 06:21:44 PM PDT 24
Finished Jun 29 06:21:45 PM PDT 24
Peak memory 200200 kb
Host smart-278124e5-9df6-4e8b-8dcb-70fc270a2e16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730675662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.730675662
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2868072958
Short name T92
Test name
Test status
Simulation time 102108306 ps
CPU time 1.41 seconds
Started Jun 29 06:21:49 PM PDT 24
Finished Jun 29 06:21:51 PM PDT 24
Peak memory 200420 kb
Host smart-5e963ff8-991c-4193-9639-415def90af5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868072958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2868072958
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4134596721
Short name T113
Test name
Test status
Simulation time 291773575 ps
CPU time 2.08 seconds
Started Jun 29 06:21:48 PM PDT 24
Finished Jun 29 06:21:51 PM PDT 24
Peak memory 208560 kb
Host smart-6c16c84b-c570-4328-ae4d-a04cf6e2040c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134596721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.4134596721
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1578467540
Short name T596
Test name
Test status
Simulation time 417199224 ps
CPU time 1.92 seconds
Started Jun 29 06:21:49 PM PDT 24
Finished Jun 29 06:21:51 PM PDT 24
Peak memory 200432 kb
Host smart-70d93ac2-5f44-4557-af2f-6207338892c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578467540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1578467540
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.703813322
Short name T595
Test name
Test status
Simulation time 145483243 ps
CPU time 1.18 seconds
Started Jun 29 06:21:50 PM PDT 24
Finished Jun 29 06:21:52 PM PDT 24
Peak memory 208508 kb
Host smart-95be4200-fde7-4dd4-bbad-5adf3c32d9bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703813322 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.703813322
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2028953054
Short name T607
Test name
Test status
Simulation time 62818364 ps
CPU time 0.77 seconds
Started Jun 29 06:21:44 PM PDT 24
Finished Jun 29 06:21:45 PM PDT 24
Peak memory 200228 kb
Host smart-d3050be0-d7c7-49c2-8747-de27d02ac9bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028953054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2028953054
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1360650928
Short name T612
Test name
Test status
Simulation time 137828971 ps
CPU time 1.36 seconds
Started Jun 29 06:21:47 PM PDT 24
Finished Jun 29 06:21:49 PM PDT 24
Peak memory 200476 kb
Host smart-57e812c0-3b89-4b7f-9ab8-db6cef7f1112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360650928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1360650928
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4132267628
Short name T58
Test name
Test status
Simulation time 509122332 ps
CPU time 1.96 seconds
Started Jun 29 06:21:46 PM PDT 24
Finished Jun 29 06:21:48 PM PDT 24
Peak memory 200432 kb
Host smart-2180da28-e031-4952-92b2-67a516306c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132267628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.4132267628
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3311205988
Short name T62
Test name
Test status
Simulation time 210488276 ps
CPU time 1.59 seconds
Started Jun 29 06:21:47 PM PDT 24
Finished Jun 29 06:21:49 PM PDT 24
Peak memory 212016 kb
Host smart-c8732a33-ccb7-4902-b734-5df40f89ab31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311205988 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3311205988
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3293885664
Short name T548
Test name
Test status
Simulation time 76856581 ps
CPU time 0.81 seconds
Started Jun 29 06:21:46 PM PDT 24
Finished Jun 29 06:21:47 PM PDT 24
Peak memory 200160 kb
Host smart-2a8c36e8-eb6d-4ddf-b354-4b57b50d7e31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293885664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3293885664
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3182590267
Short name T566
Test name
Test status
Simulation time 83399841 ps
CPU time 0.99 seconds
Started Jun 29 06:21:44 PM PDT 24
Finished Jun 29 06:21:45 PM PDT 24
Peak memory 200184 kb
Host smart-e9882ea9-97e5-48f0-8123-c8394fd7e290
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182590267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3182590267
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1400885730
Short name T590
Test name
Test status
Simulation time 124202646 ps
CPU time 1.82 seconds
Started Jun 29 06:21:46 PM PDT 24
Finished Jun 29 06:21:49 PM PDT 24
Peak memory 208528 kb
Host smart-9cbac60b-2d1f-4c19-82da-00a596b12a0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400885730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1400885730
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2179579737
Short name T586
Test name
Test status
Simulation time 147624547 ps
CPU time 1.17 seconds
Started Jun 29 06:21:52 PM PDT 24
Finished Jun 29 06:21:54 PM PDT 24
Peak memory 200352 kb
Host smart-ec39c6e2-f70a-412e-aab7-2c34ece3f89e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179579737 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2179579737
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2456137099
Short name T593
Test name
Test status
Simulation time 61405620 ps
CPU time 0.83 seconds
Started Jun 29 06:21:52 PM PDT 24
Finished Jun 29 06:21:53 PM PDT 24
Peak memory 200228 kb
Host smart-07da5d5d-78f4-4b85-9af7-5c53b73fba5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456137099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2456137099
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3827018190
Short name T94
Test name
Test status
Simulation time 142998971 ps
CPU time 1.13 seconds
Started Jun 29 06:21:55 PM PDT 24
Finished Jun 29 06:21:56 PM PDT 24
Peak memory 200288 kb
Host smart-c5765354-e5cb-4706-b912-508dfe05a316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827018190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3827018190
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2085182071
Short name T565
Test name
Test status
Simulation time 248320980 ps
CPU time 1.83 seconds
Started Jun 29 06:21:54 PM PDT 24
Finished Jun 29 06:21:56 PM PDT 24
Peak memory 208560 kb
Host smart-fffc9e4a-584f-4e3c-845d-eed9eb239d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085182071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2085182071
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.192180577
Short name T64
Test name
Test status
Simulation time 489280072 ps
CPU time 1.94 seconds
Started Jun 29 06:21:52 PM PDT 24
Finished Jun 29 06:21:54 PM PDT 24
Peak memory 200448 kb
Host smart-1e264d85-90e1-46ff-99a0-23c60fb79251
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192180577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.192180577
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3183301248
Short name T582
Test name
Test status
Simulation time 213704316 ps
CPU time 1.75 seconds
Started Jun 29 06:21:20 PM PDT 24
Finished Jun 29 06:21:23 PM PDT 24
Peak memory 200340 kb
Host smart-86c779a8-f6ca-4a12-9b56-d700aa5df5f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183301248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
183301248
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3842865312
Short name T128
Test name
Test status
Simulation time 2296041788 ps
CPU time 10.12 seconds
Started Jun 29 06:21:19 PM PDT 24
Finished Jun 29 06:21:30 PM PDT 24
Peak memory 200336 kb
Host smart-37988a6b-4973-431b-af44-c512fcccb7f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842865312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
842865312
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3582938739
Short name T571
Test name
Test status
Simulation time 145957275 ps
CPU time 0.99 seconds
Started Jun 29 06:21:21 PM PDT 24
Finished Jun 29 06:21:22 PM PDT 24
Peak memory 200240 kb
Host smart-244df563-2268-446c-b865-78a89ecfb5bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582938739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
582938739
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2693181350
Short name T609
Test name
Test status
Simulation time 225500298 ps
CPU time 1.46 seconds
Started Jun 29 06:21:20 PM PDT 24
Finished Jun 29 06:21:23 PM PDT 24
Peak memory 208672 kb
Host smart-c58ece3c-f586-4e1b-9303-2565aa226b76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693181350 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2693181350
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1492172975
Short name T587
Test name
Test status
Simulation time 60579284 ps
CPU time 0.77 seconds
Started Jun 29 06:21:20 PM PDT 24
Finished Jun 29 06:21:21 PM PDT 24
Peak memory 200160 kb
Host smart-66a0627e-fc6a-4e62-8d81-9b87e096dffe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492172975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1492172975
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3345336315
Short name T97
Test name
Test status
Simulation time 90110055 ps
CPU time 1.03 seconds
Started Jun 29 06:21:18 PM PDT 24
Finished Jun 29 06:21:19 PM PDT 24
Peak memory 200184 kb
Host smart-b2abc0c7-78d8-4a23-bcc6-bac09174bfdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345336315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3345336315
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.182893589
Short name T583
Test name
Test status
Simulation time 98116364 ps
CPU time 1.34 seconds
Started Jun 29 06:21:19 PM PDT 24
Finished Jun 29 06:21:21 PM PDT 24
Peak memory 208516 kb
Host smart-89150c8d-5aeb-4e9a-b101-96b0eaf11bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182893589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.182893589
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1496876670
Short name T573
Test name
Test status
Simulation time 959501275 ps
CPU time 3.47 seconds
Started Jun 29 06:21:20 PM PDT 24
Finished Jun 29 06:21:24 PM PDT 24
Peak memory 200428 kb
Host smart-983a9a1b-c48d-4d44-8bba-a8b6268cbc1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496876670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1496876670
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3309800432
Short name T617
Test name
Test status
Simulation time 190833021 ps
CPU time 1.53 seconds
Started Jun 29 06:21:31 PM PDT 24
Finished Jun 29 06:21:33 PM PDT 24
Peak memory 200300 kb
Host smart-049a20ee-8565-4d57-99e3-abead9b5b7d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309800432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
309800432
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2552180079
Short name T597
Test name
Test status
Simulation time 807164432 ps
CPU time 4.45 seconds
Started Jun 29 06:21:28 PM PDT 24
Finished Jun 29 06:21:33 PM PDT 24
Peak memory 200372 kb
Host smart-9607e678-a0a8-4f3e-a1b9-8fc686374533
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552180079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
552180079
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.912577218
Short name T547
Test name
Test status
Simulation time 135190540 ps
CPU time 0.93 seconds
Started Jun 29 06:21:30 PM PDT 24
Finished Jun 29 06:21:31 PM PDT 24
Peak memory 200240 kb
Host smart-2f11e094-e2ea-4c16-a16f-05439350b621
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912577218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.912577218
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2117247305
Short name T564
Test name
Test status
Simulation time 206444553 ps
CPU time 1.34 seconds
Started Jun 29 06:21:27 PM PDT 24
Finished Jun 29 06:21:29 PM PDT 24
Peak memory 208552 kb
Host smart-9258b307-d434-4afa-adcb-559add8fd94a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117247305 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2117247305
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1602844769
Short name T570
Test name
Test status
Simulation time 83784945 ps
CPU time 0.82 seconds
Started Jun 29 06:21:30 PM PDT 24
Finished Jun 29 06:21:31 PM PDT 24
Peak memory 200228 kb
Host smart-96716008-68a1-41d5-a45a-239e9e4aa01a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602844769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1602844769
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1125945977
Short name T610
Test name
Test status
Simulation time 183695656 ps
CPU time 1.37 seconds
Started Jun 29 06:21:29 PM PDT 24
Finished Jun 29 06:21:30 PM PDT 24
Peak memory 200416 kb
Host smart-dc15c591-bcbd-4f33-b17a-43ab18586e79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125945977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1125945977
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1444215546
Short name T605
Test name
Test status
Simulation time 102577333 ps
CPU time 1.46 seconds
Started Jun 29 06:21:23 PM PDT 24
Finished Jun 29 06:21:25 PM PDT 24
Peak memory 200560 kb
Host smart-eac9f718-0f8f-42f1-b388-12979a13ed1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444215546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1444215546
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4224140540
Short name T109
Test name
Test status
Simulation time 784202273 ps
CPU time 3.05 seconds
Started Jun 29 06:21:27 PM PDT 24
Finished Jun 29 06:21:31 PM PDT 24
Peak memory 200428 kb
Host smart-4ba78b1c-5da6-4570-a04e-3b6c76c9351b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224140540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.4224140540
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.4243585324
Short name T102
Test name
Test status
Simulation time 420624926 ps
CPU time 2.69 seconds
Started Jun 29 06:21:30 PM PDT 24
Finished Jun 29 06:21:33 PM PDT 24
Peak memory 200392 kb
Host smart-2153aa4e-2a2c-4f4f-9027-703e195130ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243585324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.4
243585324
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3536232024
Short name T577
Test name
Test status
Simulation time 1179783607 ps
CPU time 5.75 seconds
Started Jun 29 06:21:29 PM PDT 24
Finished Jun 29 06:21:36 PM PDT 24
Peak memory 200372 kb
Host smart-12f5500c-a8d3-4447-b78a-a426b76f5398
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536232024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
536232024
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3715318787
Short name T550
Test name
Test status
Simulation time 101454810 ps
CPU time 0.89 seconds
Started Jun 29 06:21:32 PM PDT 24
Finished Jun 29 06:21:33 PM PDT 24
Peak memory 200204 kb
Host smart-1a504509-c994-4551-a317-d84ca69df8aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715318787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
715318787
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1683634046
Short name T563
Test name
Test status
Simulation time 120198913 ps
CPU time 0.95 seconds
Started Jun 29 06:21:31 PM PDT 24
Finished Jun 29 06:21:32 PM PDT 24
Peak memory 200348 kb
Host smart-19dbcbb0-169c-44ad-b679-98c3f2acfe52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683634046 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1683634046
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.422175461
Short name T613
Test name
Test status
Simulation time 78530407 ps
CPU time 0.84 seconds
Started Jun 29 06:21:28 PM PDT 24
Finished Jun 29 06:21:30 PM PDT 24
Peak memory 200200 kb
Host smart-d4e5b864-5ac4-454a-a9f4-a1214caf6f67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422175461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.422175461
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.925806999
Short name T558
Test name
Test status
Simulation time 224829793 ps
CPU time 1.54 seconds
Started Jun 29 06:21:29 PM PDT 24
Finished Jun 29 06:21:31 PM PDT 24
Peak memory 200412 kb
Host smart-37ec4935-5572-4b80-b13c-564b8902a2fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925806999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.925806999
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3212486894
Short name T568
Test name
Test status
Simulation time 584582115 ps
CPU time 4.22 seconds
Started Jun 29 06:21:30 PM PDT 24
Finished Jun 29 06:21:35 PM PDT 24
Peak memory 208572 kb
Host smart-29de3a82-526d-4c55-96ac-c28ba9de3f12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212486894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3212486894
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.352895521
Short name T115
Test name
Test status
Simulation time 646745005 ps
CPU time 2.18 seconds
Started Jun 29 06:21:28 PM PDT 24
Finished Jun 29 06:21:30 PM PDT 24
Peak memory 200384 kb
Host smart-ac1ac556-7b9d-4c4c-8162-7ea7c888fe96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352895521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
352895521
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2989954640
Short name T585
Test name
Test status
Simulation time 178439965 ps
CPU time 1.66 seconds
Started Jun 29 06:21:28 PM PDT 24
Finished Jun 29 06:21:31 PM PDT 24
Peak memory 213840 kb
Host smart-83fc959d-46a6-4a75-b0e3-d3f7472fc211
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989954640 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2989954640
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2747998414
Short name T549
Test name
Test status
Simulation time 64649104 ps
CPU time 0.78 seconds
Started Jun 29 06:21:29 PM PDT 24
Finished Jun 29 06:21:30 PM PDT 24
Peak memory 200228 kb
Host smart-3a5beedd-0420-48a9-8978-65ef6aa18c5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747998414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2747998414
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3297566839
Short name T616
Test name
Test status
Simulation time 83440880 ps
CPU time 1.06 seconds
Started Jun 29 06:21:31 PM PDT 24
Finished Jun 29 06:21:33 PM PDT 24
Peak memory 200228 kb
Host smart-82fdc016-d825-4f33-a2ad-620b4815d980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297566839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3297566839
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.752681855
Short name T105
Test name
Test status
Simulation time 495109578 ps
CPU time 3.03 seconds
Started Jun 29 06:21:30 PM PDT 24
Finished Jun 29 06:21:33 PM PDT 24
Peak memory 208580 kb
Host smart-ee6ae6e1-53c2-4e90-9aef-6bdd719de881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752681855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.752681855
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2930983384
Short name T551
Test name
Test status
Simulation time 507998547 ps
CPU time 2.26 seconds
Started Jun 29 06:21:29 PM PDT 24
Finished Jun 29 06:21:32 PM PDT 24
Peak memory 200512 kb
Host smart-d6378a51-b86b-4d84-845a-f860977e8547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930983384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2930983384
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4200704535
Short name T592
Test name
Test status
Simulation time 188819479 ps
CPU time 1.39 seconds
Started Jun 29 06:21:28 PM PDT 24
Finished Jun 29 06:21:29 PM PDT 24
Peak memory 208448 kb
Host smart-1644d5e1-073c-45a9-ac51-0c79ffd6d132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200704535 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.4200704535
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3230239715
Short name T601
Test name
Test status
Simulation time 82163419 ps
CPU time 0.9 seconds
Started Jun 29 06:21:28 PM PDT 24
Finished Jun 29 06:21:30 PM PDT 24
Peak memory 200220 kb
Host smart-57ce0832-8279-4e5d-908b-bb0f3b65d287
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230239715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3230239715
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.163798675
Short name T101
Test name
Test status
Simulation time 125899520 ps
CPU time 1.34 seconds
Started Jun 29 06:21:32 PM PDT 24
Finished Jun 29 06:21:33 PM PDT 24
Peak memory 200432 kb
Host smart-4881a521-42fa-4b12-be74-749ee47d7917
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163798675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.163798675
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2646997847
Short name T104
Test name
Test status
Simulation time 494990003 ps
CPU time 3.67 seconds
Started Jun 29 06:21:27 PM PDT 24
Finished Jun 29 06:21:31 PM PDT 24
Peak memory 212628 kb
Host smart-019b464a-6592-4239-8cef-8c9b3f9148d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646997847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2646997847
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.311511176
Short name T116
Test name
Test status
Simulation time 763070320 ps
CPU time 2.79 seconds
Started Jun 29 06:21:30 PM PDT 24
Finished Jun 29 06:21:34 PM PDT 24
Peak memory 200432 kb
Host smart-dd088727-a819-4724-abaf-12df0fcf1974
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311511176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
311511176
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4187634745
Short name T60
Test name
Test status
Simulation time 203536251 ps
CPU time 1.31 seconds
Started Jun 29 06:21:28 PM PDT 24
Finished Jun 29 06:21:30 PM PDT 24
Peak memory 208520 kb
Host smart-5fa2508d-3014-4f36-9827-b46150a54e40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187634745 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.4187634745
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3770123605
Short name T56
Test name
Test status
Simulation time 78738395 ps
CPU time 0.85 seconds
Started Jun 29 06:21:31 PM PDT 24
Finished Jun 29 06:21:32 PM PDT 24
Peak memory 200020 kb
Host smart-02076086-6c7c-4cbd-b249-6a902066478f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770123605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3770123605
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1893814088
Short name T99
Test name
Test status
Simulation time 141000073 ps
CPU time 1.2 seconds
Started Jun 29 06:21:29 PM PDT 24
Finished Jun 29 06:21:31 PM PDT 24
Peak memory 200292 kb
Host smart-7469f887-a07f-43fb-a5d2-d602ca1fe282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893814088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1893814088
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2661866827
Short name T103
Test name
Test status
Simulation time 534284513 ps
CPU time 3.6 seconds
Started Jun 29 06:21:31 PM PDT 24
Finished Jun 29 06:21:35 PM PDT 24
Peak memory 216476 kb
Host smart-7ba97705-6f7e-4722-a246-4c7f2aed7dce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661866827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2661866827
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.621540742
Short name T112
Test name
Test status
Simulation time 477530641 ps
CPU time 1.89 seconds
Started Jun 29 06:21:30 PM PDT 24
Finished Jun 29 06:21:33 PM PDT 24
Peak memory 200604 kb
Host smart-8b23a4f9-5e60-4fca-80ff-63dafd814e6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621540742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
621540742
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4014962665
Short name T553
Test name
Test status
Simulation time 192983954 ps
CPU time 1.31 seconds
Started Jun 29 06:21:39 PM PDT 24
Finished Jun 29 06:21:41 PM PDT 24
Peak memory 208884 kb
Host smart-e287b472-8835-4bb8-b5ff-aee7c2f0ad89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014962665 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.4014962665
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4133957962
Short name T561
Test name
Test status
Simulation time 74029242 ps
CPU time 0.88 seconds
Started Jun 29 06:21:40 PM PDT 24
Finished Jun 29 06:21:41 PM PDT 24
Peak memory 200228 kb
Host smart-a52ec250-e250-473f-afb6-1bcbef833db2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133957962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4133957962
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.48794998
Short name T611
Test name
Test status
Simulation time 73777584 ps
CPU time 1 seconds
Started Jun 29 06:21:39 PM PDT 24
Finished Jun 29 06:21:41 PM PDT 24
Peak memory 200276 kb
Host smart-1b22cace-7663-4f9d-83eb-a78a791cd169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48794998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same
_csr_outstanding.48794998
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1794302432
Short name T108
Test name
Test status
Simulation time 279736188 ps
CPU time 2.22 seconds
Started Jun 29 06:21:35 PM PDT 24
Finished Jun 29 06:21:38 PM PDT 24
Peak memory 211268 kb
Host smart-fdd15fc4-b583-4310-b009-f2e54e67e1ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794302432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1794302432
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2688847341
Short name T114
Test name
Test status
Simulation time 427625601 ps
CPU time 1.75 seconds
Started Jun 29 06:21:40 PM PDT 24
Finished Jun 29 06:21:43 PM PDT 24
Peak memory 200228 kb
Host smart-73295563-599c-4ffc-9244-ff0ee2ff5565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688847341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2688847341
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1805280966
Short name T562
Test name
Test status
Simulation time 115697091 ps
CPU time 1.05 seconds
Started Jun 29 06:21:36 PM PDT 24
Finished Jun 29 06:21:37 PM PDT 24
Peak memory 200268 kb
Host smart-4566a1ab-e809-4916-9874-ea59a46e9fcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805280966 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1805280966
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1961226277
Short name T614
Test name
Test status
Simulation time 66496951 ps
CPU time 0.84 seconds
Started Jun 29 06:21:37 PM PDT 24
Finished Jun 29 06:21:39 PM PDT 24
Peak memory 200188 kb
Host smart-a601c19d-162c-4983-9368-9f96104858c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961226277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1961226277
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3811608328
Short name T560
Test name
Test status
Simulation time 129909540 ps
CPU time 1.06 seconds
Started Jun 29 06:21:35 PM PDT 24
Finished Jun 29 06:21:37 PM PDT 24
Peak memory 200292 kb
Host smart-44563ac3-d25c-44b7-a29f-ea113bf856ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811608328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3811608328
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.480504380
Short name T574
Test name
Test status
Simulation time 211399021 ps
CPU time 3.15 seconds
Started Jun 29 06:21:35 PM PDT 24
Finished Jun 29 06:21:38 PM PDT 24
Peak memory 208564 kb
Host smart-908ff54a-6724-4e2c-8b00-4144339a9b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480504380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.480504380
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.242564346
Short name T432
Test name
Test status
Simulation time 1221833212 ps
CPU time 5.65 seconds
Started Jun 29 06:25:28 PM PDT 24
Finished Jun 29 06:25:34 PM PDT 24
Peak memory 221488 kb
Host smart-c95dc83a-a7b7-43c2-90b4-4728dcf2cffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242564346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.242564346
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3955094250
Short name T306
Test name
Test status
Simulation time 244033159 ps
CPU time 1.1 seconds
Started Jun 29 06:25:28 PM PDT 24
Finished Jun 29 06:25:30 PM PDT 24
Peak memory 217504 kb
Host smart-9b1179d8-cfeb-44c7-b94c-08d3b40af0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955094250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3955094250
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.4116241788
Short name T181
Test name
Test status
Simulation time 96945801 ps
CPU time 0.78 seconds
Started Jun 29 06:25:21 PM PDT 24
Finished Jun 29 06:25:23 PM PDT 24
Peak memory 199900 kb
Host smart-fcbf5857-798f-4df1-8970-757094e78af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116241788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4116241788
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3931148514
Short name T532
Test name
Test status
Simulation time 820088911 ps
CPU time 4.22 seconds
Started Jun 29 06:25:21 PM PDT 24
Finished Jun 29 06:25:26 PM PDT 24
Peak memory 200276 kb
Host smart-d86ff20d-a853-41ca-b9ee-4b9103beed3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931148514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3931148514
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1254177859
Short name T53
Test name
Test status
Simulation time 16902632601 ps
CPU time 26.13 seconds
Started Jun 29 06:25:28 PM PDT 24
Finished Jun 29 06:25:55 PM PDT 24
Peak memory 218248 kb
Host smart-b037ba12-c2e1-40f9-ac2b-c0e3959bc7c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254177859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1254177859
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2332302995
Short name T307
Test name
Test status
Simulation time 155858803 ps
CPU time 1.29 seconds
Started Jun 29 06:25:29 PM PDT 24
Finished Jun 29 06:25:31 PM PDT 24
Peak memory 200008 kb
Host smart-5264893f-d152-4b71-b457-c40d62c869ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332302995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2332302995
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3898862860
Short name T408
Test name
Test status
Simulation time 117690891 ps
CPU time 1.19 seconds
Started Jun 29 06:25:22 PM PDT 24
Finished Jun 29 06:25:24 PM PDT 24
Peak memory 200300 kb
Host smart-010e0825-9554-4412-a893-eba452406b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898862860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3898862860
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2525361278
Short name T341
Test name
Test status
Simulation time 395736660 ps
CPU time 2.34 seconds
Started Jun 29 06:25:30 PM PDT 24
Finished Jun 29 06:25:32 PM PDT 24
Peak memory 200280 kb
Host smart-55c4d295-8276-4afa-aca3-3e0193450b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525361278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2525361278
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.166996951
Short name T197
Test name
Test status
Simulation time 262746927 ps
CPU time 1.84 seconds
Started Jun 29 06:25:31 PM PDT 24
Finished Jun 29 06:25:33 PM PDT 24
Peak memory 200076 kb
Host smart-a83d783d-e8ab-42b9-8435-89bac550a9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166996951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.166996951
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2716038428
Short name T250
Test name
Test status
Simulation time 201208190 ps
CPU time 1.25 seconds
Started Jun 29 06:25:31 PM PDT 24
Finished Jun 29 06:25:33 PM PDT 24
Peak memory 200076 kb
Host smart-4367c60d-3ac1-4e55-a09f-567e8c42bf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716038428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2716038428
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1731138568
Short name T123
Test name
Test status
Simulation time 87487865 ps
CPU time 0.85 seconds
Started Jun 29 06:25:31 PM PDT 24
Finished Jun 29 06:25:32 PM PDT 24
Peak memory 199876 kb
Host smart-df3292f0-f63e-473a-82a0-461aa022402d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731138568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1731138568
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3662040147
Short name T301
Test name
Test status
Simulation time 1230957693 ps
CPU time 5.51 seconds
Started Jun 29 06:25:29 PM PDT 24
Finished Jun 29 06:25:35 PM PDT 24
Peak memory 221108 kb
Host smart-280b5e24-8b47-4876-87b5-bfb15342fb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662040147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3662040147
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3527538140
Short name T536
Test name
Test status
Simulation time 244112422 ps
CPU time 1.13 seconds
Started Jun 29 06:25:32 PM PDT 24
Finished Jun 29 06:25:34 PM PDT 24
Peak memory 217452 kb
Host smart-00eff976-2f95-4b86-91aa-4ac53f0a0bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527538140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3527538140
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2092435583
Short name T512
Test name
Test status
Simulation time 1620585874 ps
CPU time 6.28 seconds
Started Jun 29 06:25:33 PM PDT 24
Finished Jun 29 06:25:39 PM PDT 24
Peak memory 200364 kb
Host smart-14781323-76fc-4a16-b834-ac528e7d91e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092435583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2092435583
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.4047882123
Short name T67
Test name
Test status
Simulation time 18976257330 ps
CPU time 28.74 seconds
Started Jun 29 06:25:28 PM PDT 24
Finished Jun 29 06:25:58 PM PDT 24
Peak memory 217436 kb
Host smart-9140e887-952e-4b45-9e58-8aac63e2ec94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047882123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4047882123
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2999312721
Short name T225
Test name
Test status
Simulation time 111274871 ps
CPU time 1.15 seconds
Started Jun 29 06:25:32 PM PDT 24
Finished Jun 29 06:25:34 PM PDT 24
Peak memory 200092 kb
Host smart-53db4eca-495d-4870-9482-81f65c7af68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999312721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2999312721
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1372178233
Short name T520
Test name
Test status
Simulation time 246741633 ps
CPU time 1.58 seconds
Started Jun 29 06:25:31 PM PDT 24
Finished Jun 29 06:25:33 PM PDT 24
Peak memory 200204 kb
Host smart-7a6caa27-6f41-48c6-9cf3-52a05078d5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372178233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1372178233
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2702422210
Short name T289
Test name
Test status
Simulation time 275197352 ps
CPU time 1.92 seconds
Started Jun 29 06:25:29 PM PDT 24
Finished Jun 29 06:25:32 PM PDT 24
Peak memory 200092 kb
Host smart-852d2039-3625-4fb5-b041-56bad90098a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702422210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2702422210
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2517028527
Short name T322
Test name
Test status
Simulation time 100688407 ps
CPU time 0.85 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:25:52 PM PDT 24
Peak memory 199888 kb
Host smart-1ce2a113-0cba-42b4-a77a-fa79a701ea90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517028527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2517028527
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3799238510
Short name T313
Test name
Test status
Simulation time 1227077867 ps
CPU time 5.42 seconds
Started Jun 29 06:25:50 PM PDT 24
Finished Jun 29 06:25:56 PM PDT 24
Peak memory 217256 kb
Host smart-a2ea96f2-fc2c-4965-a39b-8a307c99d924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799238510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3799238510
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2847373520
Short name T295
Test name
Test status
Simulation time 246029345 ps
CPU time 1 seconds
Started Jun 29 06:25:49 PM PDT 24
Finished Jun 29 06:25:51 PM PDT 24
Peak memory 217460 kb
Host smart-0f6d03f9-04af-4f4c-a1a8-e3145345719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847373520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2847373520
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.747570922
Short name T18
Test name
Test status
Simulation time 119124767 ps
CPU time 0.83 seconds
Started Jun 29 06:25:55 PM PDT 24
Finished Jun 29 06:25:56 PM PDT 24
Peak memory 199904 kb
Host smart-8de3d5f9-7867-40ec-ac72-f50e046d39c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747570922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.747570922
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1554904778
Short name T537
Test name
Test status
Simulation time 924998352 ps
CPU time 4.89 seconds
Started Jun 29 06:25:53 PM PDT 24
Finished Jun 29 06:25:59 PM PDT 24
Peak memory 200324 kb
Host smart-2e2b754a-6a11-491e-a386-0297113d1f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554904778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1554904778
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.548924927
Short name T278
Test name
Test status
Simulation time 178410370 ps
CPU time 1.2 seconds
Started Jun 29 06:25:53 PM PDT 24
Finished Jun 29 06:25:55 PM PDT 24
Peak memory 200076 kb
Host smart-4c91a45e-8207-4f9e-85b8-1ba256bdc36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548924927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.548924927
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.839369528
Short name T144
Test name
Test status
Simulation time 227481656 ps
CPU time 1.38 seconds
Started Jun 29 06:25:53 PM PDT 24
Finished Jun 29 06:25:55 PM PDT 24
Peak memory 200204 kb
Host smart-4c938940-12c0-4f42-8e4e-bd0f126b7b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839369528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.839369528
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2781719024
Short name T73
Test name
Test status
Simulation time 1020789256 ps
CPU time 5.69 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:25:57 PM PDT 24
Peak memory 200344 kb
Host smart-64aa64ec-e407-47d6-a3cf-afc775e2f777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781719024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2781719024
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1455350841
Short name T476
Test name
Test status
Simulation time 488873706 ps
CPU time 2.8 seconds
Started Jun 29 06:25:52 PM PDT 24
Finished Jun 29 06:25:56 PM PDT 24
Peak memory 200044 kb
Host smart-7faf1b8e-6496-429e-bf0e-a73bda852317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455350841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1455350841
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2970733339
Short name T164
Test name
Test status
Simulation time 96690963 ps
CPU time 0.95 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 200024 kb
Host smart-c320725e-c2e6-4fd3-8742-20a589876fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970733339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2970733339
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1590344553
Short name T137
Test name
Test status
Simulation time 66828672 ps
CPU time 0.79 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 199792 kb
Host smart-d7a7d74e-c686-42e7-a937-55d39f483d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590344553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1590344553
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.816527828
Short name T395
Test name
Test status
Simulation time 1901337042 ps
CPU time 8.27 seconds
Started Jun 29 06:25:52 PM PDT 24
Finished Jun 29 06:26:01 PM PDT 24
Peak memory 221560 kb
Host smart-8a11ed75-e036-4f52-bd85-5a05d743d1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816527828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.816527828
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3402083648
Short name T505
Test name
Test status
Simulation time 244080009 ps
CPU time 1.14 seconds
Started Jun 29 06:25:53 PM PDT 24
Finished Jun 29 06:25:55 PM PDT 24
Peak memory 217452 kb
Host smart-25bcce0c-b184-4852-8b2a-2686dd399322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402083648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3402083648
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.533306639
Short name T531
Test name
Test status
Simulation time 221081696 ps
CPU time 0.99 seconds
Started Jun 29 06:25:56 PM PDT 24
Finished Jun 29 06:25:57 PM PDT 24
Peak memory 200092 kb
Host smart-1a9b3976-5c74-4f43-b20d-16ab310abbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533306639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.533306639
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4146041524
Short name T403
Test name
Test status
Simulation time 1139449218 ps
CPU time 4.84 seconds
Started Jun 29 06:25:53 PM PDT 24
Finished Jun 29 06:25:59 PM PDT 24
Peak memory 200352 kb
Host smart-86104531-f419-4380-a943-ed0b478cc465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146041524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4146041524
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1631706081
Short name T280
Test name
Test status
Simulation time 183995394 ps
CPU time 1.18 seconds
Started Jun 29 06:25:53 PM PDT 24
Finished Jun 29 06:25:55 PM PDT 24
Peak memory 200088 kb
Host smart-2902ba44-9326-4676-9ed1-28dc16cf5814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631706081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1631706081
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1938257648
Short name T343
Test name
Test status
Simulation time 253617966 ps
CPU time 1.78 seconds
Started Jun 29 06:25:50 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 200276 kb
Host smart-a0ef12b9-db65-4da1-9b66-e890dfb795aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938257648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1938257648
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2918728458
Short name T442
Test name
Test status
Simulation time 4053736997 ps
CPU time 14.96 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:26:07 PM PDT 24
Peak memory 210324 kb
Host smart-7d5763ce-6ec2-4a56-a153-d392bba31262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918728458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2918728458
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2034016168
Short name T172
Test name
Test status
Simulation time 148234350 ps
CPU time 1.95 seconds
Started Jun 29 06:25:53 PM PDT 24
Finished Jun 29 06:25:56 PM PDT 24
Peak memory 200084 kb
Host smart-727b0986-2b9c-4ac2-ba1a-62b259636867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034016168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2034016168
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.745841223
Short name T438
Test name
Test status
Simulation time 137361093 ps
CPU time 1.17 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 200096 kb
Host smart-890a7d3f-e99d-427c-b034-d1fe8e3e0b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745841223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.745841223
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2321704947
Short name T259
Test name
Test status
Simulation time 73281669 ps
CPU time 0.81 seconds
Started Jun 29 06:25:52 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 199872 kb
Host smart-325054bb-bbec-43ab-aa6d-eed95ad4daaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321704947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2321704947
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.135681345
Short name T485
Test name
Test status
Simulation time 2365931868 ps
CPU time 8.96 seconds
Started Jun 29 06:25:53 PM PDT 24
Finished Jun 29 06:26:02 PM PDT 24
Peak memory 217892 kb
Host smart-17a20b0e-eac6-4882-a8e4-0a79fa68d36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135681345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.135681345
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3800681687
Short name T407
Test name
Test status
Simulation time 244152211 ps
CPU time 1.18 seconds
Started Jun 29 06:25:52 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 217464 kb
Host smart-350112eb-20a1-44ee-9313-e72ab6d2e81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800681687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3800681687
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.789557976
Short name T312
Test name
Test status
Simulation time 176818821 ps
CPU time 0.99 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 199904 kb
Host smart-83820920-c564-444a-8bf8-459f1d94587f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789557976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.789557976
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3730725437
Short name T231
Test name
Test status
Simulation time 824878514 ps
CPU time 4.26 seconds
Started Jun 29 06:25:48 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 200332 kb
Host smart-34543e7a-a5c3-41b3-a960-013a4c2430df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730725437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3730725437
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2311187108
Short name T283
Test name
Test status
Simulation time 152865504 ps
CPU time 1.15 seconds
Started Jun 29 06:25:52 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 200032 kb
Host smart-61863dec-cce2-4462-ab92-79c99740d3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311187108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2311187108
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3196965458
Short name T347
Test name
Test status
Simulation time 118413575 ps
CPU time 1.28 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:25:52 PM PDT 24
Peak memory 200276 kb
Host smart-a7a6538c-ebf7-464b-bba2-84c72ffe9d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196965458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3196965458
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2728064703
Short name T212
Test name
Test status
Simulation time 12842625006 ps
CPU time 45.36 seconds
Started Jun 29 06:25:52 PM PDT 24
Finished Jun 29 06:26:38 PM PDT 24
Peak memory 200412 kb
Host smart-48507c94-bc61-4d9c-ad70-dc6a3281d2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728064703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2728064703
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1122674234
Short name T380
Test name
Test status
Simulation time 509994002 ps
CPU time 2.78 seconds
Started Jun 29 06:25:53 PM PDT 24
Finished Jun 29 06:25:57 PM PDT 24
Peak memory 200084 kb
Host smart-4b818b5e-709a-41b1-a7f1-26868e304939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122674234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1122674234
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1468599711
Short name T324
Test name
Test status
Simulation time 223374594 ps
CPU time 1.41 seconds
Started Jun 29 06:25:54 PM PDT 24
Finished Jun 29 06:25:56 PM PDT 24
Peak memory 200068 kb
Host smart-30338527-f448-4b55-8651-d7ffc73191f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468599711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1468599711
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.790423839
Short name T370
Test name
Test status
Simulation time 57448462 ps
CPU time 0.74 seconds
Started Jun 29 06:25:59 PM PDT 24
Finished Jun 29 06:26:00 PM PDT 24
Peak memory 199856 kb
Host smart-76f1c498-e67b-4546-92e5-dbd6713cc8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790423839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.790423839
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.17087658
Short name T266
Test name
Test status
Simulation time 1928413252 ps
CPU time 7.3 seconds
Started Jun 29 06:25:52 PM PDT 24
Finished Jun 29 06:26:01 PM PDT 24
Peak memory 217572 kb
Host smart-e844c256-75f8-4504-94f5-95ca0d22a641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17087658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.17087658
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2903699781
Short name T264
Test name
Test status
Simulation time 244566355 ps
CPU time 1.19 seconds
Started Jun 29 06:26:10 PM PDT 24
Finished Jun 29 06:26:12 PM PDT 24
Peak memory 217292 kb
Host smart-a9ad1d90-b379-486e-8914-a06750801e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903699781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2903699781
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2187476961
Short name T409
Test name
Test status
Simulation time 96161261 ps
CPU time 0.78 seconds
Started Jun 29 06:25:53 PM PDT 24
Finished Jun 29 06:25:54 PM PDT 24
Peak memory 199844 kb
Host smart-13ed0ca5-d5af-433d-803d-a09338f1b48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187476961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2187476961
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1924290402
Short name T207
Test name
Test status
Simulation time 1568624459 ps
CPU time 6.87 seconds
Started Jun 29 06:25:50 PM PDT 24
Finished Jun 29 06:25:57 PM PDT 24
Peak memory 200348 kb
Host smart-efebfa4d-4713-475d-8db1-4a6e588a2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924290402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1924290402
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4024670810
Short name T417
Test name
Test status
Simulation time 105328784 ps
CPU time 1 seconds
Started Jun 29 06:25:49 PM PDT 24
Finished Jun 29 06:25:50 PM PDT 24
Peak memory 200088 kb
Host smart-68b78793-afad-4194-8971-9abee69d3df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024670810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.4024670810
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.755323814
Short name T471
Test name
Test status
Simulation time 198572456 ps
CPU time 1.37 seconds
Started Jun 29 06:26:05 PM PDT 24
Finished Jun 29 06:26:06 PM PDT 24
Peak memory 200132 kb
Host smart-9d4c1b1f-b49e-4ffe-93ac-b52e179c3e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755323814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.755323814
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3497701675
Short name T118
Test name
Test status
Simulation time 2262883266 ps
CPU time 8.71 seconds
Started Jun 29 06:25:59 PM PDT 24
Finished Jun 29 06:26:08 PM PDT 24
Peak memory 200408 kb
Host smart-806ec829-5340-45b5-93d3-7478c17e8b3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497701675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3497701675
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3323236653
Short name T535
Test name
Test status
Simulation time 139166467 ps
CPU time 1.75 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 200084 kb
Host smart-c4dc29f7-856c-4c6a-a2c9-19b91fe36061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323236653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3323236653
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2565758130
Short name T448
Test name
Test status
Simulation time 257524903 ps
CPU time 1.68 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 200096 kb
Host smart-59fd8aa6-fed5-4d93-84b6-40e64882fa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565758130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2565758130
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1576160018
Short name T326
Test name
Test status
Simulation time 64572834 ps
CPU time 0.79 seconds
Started Jun 29 06:25:58 PM PDT 24
Finished Jun 29 06:25:59 PM PDT 24
Peak memory 199876 kb
Host smart-38c8f25d-e57a-4a96-b51d-fc2c0f2014dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576160018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1576160018
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3169124933
Short name T263
Test name
Test status
Simulation time 1900966784 ps
CPU time 8.05 seconds
Started Jun 29 06:25:57 PM PDT 24
Finished Jun 29 06:26:06 PM PDT 24
Peak memory 217736 kb
Host smart-f3d7c298-50b6-4fca-b52a-2ad8160fcf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169124933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3169124933
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.224878603
Short name T453
Test name
Test status
Simulation time 244986574 ps
CPU time 1.1 seconds
Started Jun 29 06:25:56 PM PDT 24
Finished Jun 29 06:25:58 PM PDT 24
Peak memory 217404 kb
Host smart-52d45922-8476-4035-929a-b3c1a73e247a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224878603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.224878603
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1692609371
Short name T421
Test name
Test status
Simulation time 183117459 ps
CPU time 0.87 seconds
Started Jun 29 06:26:10 PM PDT 24
Finished Jun 29 06:26:12 PM PDT 24
Peak memory 199740 kb
Host smart-bd1342cb-c12b-46a4-acf0-071e61adb12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692609371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1692609371
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2708479310
Short name T294
Test name
Test status
Simulation time 912284781 ps
CPU time 4.73 seconds
Started Jun 29 06:26:10 PM PDT 24
Finished Jun 29 06:26:16 PM PDT 24
Peak memory 200228 kb
Host smart-d074b77e-feaf-4123-8101-e97f40b7c8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708479310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2708479310
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3104742161
Short name T190
Test name
Test status
Simulation time 107784585 ps
CPU time 1.05 seconds
Started Jun 29 06:25:57 PM PDT 24
Finished Jun 29 06:25:59 PM PDT 24
Peak memory 200088 kb
Host smart-25c583b0-2182-476b-981e-79a1e2c5c5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104742161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3104742161
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3999855068
Short name T145
Test name
Test status
Simulation time 238453281 ps
CPU time 1.52 seconds
Started Jun 29 06:25:58 PM PDT 24
Finished Jun 29 06:26:00 PM PDT 24
Peak memory 200280 kb
Host smart-e68b4a80-6625-4dcb-abc4-9a31264a35d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999855068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3999855068
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1443872370
Short name T509
Test name
Test status
Simulation time 238749099 ps
CPU time 1.52 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:13 PM PDT 24
Peak memory 199984 kb
Host smart-bf616f76-5ff3-42fe-bc43-f4e8d18c30c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443872370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1443872370
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3996206907
Short name T459
Test name
Test status
Simulation time 136825346 ps
CPU time 1.72 seconds
Started Jun 29 06:26:01 PM PDT 24
Finished Jun 29 06:26:03 PM PDT 24
Peak memory 208252 kb
Host smart-c36824b0-ed8a-4a35-affd-4f37e862b75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996206907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3996206907
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1036641013
Short name T497
Test name
Test status
Simulation time 110790854 ps
CPU time 0.95 seconds
Started Jun 29 06:26:10 PM PDT 24
Finished Jun 29 06:26:11 PM PDT 24
Peak memory 199936 kb
Host smart-5dd15f00-b07b-4387-b13c-d98c0db408c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036641013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1036641013
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1525620189
Short name T493
Test name
Test status
Simulation time 58821405 ps
CPU time 0.74 seconds
Started Jun 29 06:25:55 PM PDT 24
Finished Jun 29 06:25:56 PM PDT 24
Peak memory 199876 kb
Host smart-d15644af-21e4-406f-be7f-d8161a89596c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525620189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1525620189
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1414038998
Short name T265
Test name
Test status
Simulation time 243776913 ps
CPU time 1.14 seconds
Started Jun 29 06:25:57 PM PDT 24
Finished Jun 29 06:25:59 PM PDT 24
Peak memory 217428 kb
Host smart-775af3c0-3b34-484f-8356-fb09b784b0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414038998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1414038998
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2128149053
Short name T500
Test name
Test status
Simulation time 162824978 ps
CPU time 0.86 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:13 PM PDT 24
Peak memory 199800 kb
Host smart-fafd8b1f-53e7-433d-8081-af1e6437d49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128149053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2128149053
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3745465429
Short name T426
Test name
Test status
Simulation time 1154954666 ps
CPU time 5.07 seconds
Started Jun 29 06:25:56 PM PDT 24
Finished Jun 29 06:26:02 PM PDT 24
Peak memory 200344 kb
Host smart-55d163dd-7e03-467f-a685-d999507ae016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745465429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3745465429
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1583923454
Short name T297
Test name
Test status
Simulation time 94324462 ps
CPU time 0.95 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:12 PM PDT 24
Peak memory 199928 kb
Host smart-c5c41311-1494-491f-80e3-8e8f42c56cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583923454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1583923454
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3270658669
Short name T381
Test name
Test status
Simulation time 251484280 ps
CPU time 1.54 seconds
Started Jun 29 06:25:57 PM PDT 24
Finished Jun 29 06:25:59 PM PDT 24
Peak memory 200280 kb
Host smart-91e2b32c-bcb5-4690-bdae-8cc28cb8e677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270658669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3270658669
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.298212346
Short name T386
Test name
Test status
Simulation time 4935322540 ps
CPU time 24.62 seconds
Started Jun 29 06:25:57 PM PDT 24
Finished Jun 29 06:26:22 PM PDT 24
Peak memory 208620 kb
Host smart-830e2e2d-1c1d-4ff6-a4b0-f07c34869f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298212346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.298212346
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2585177357
Short name T274
Test name
Test status
Simulation time 126617097 ps
CPU time 1.66 seconds
Started Jun 29 06:25:58 PM PDT 24
Finished Jun 29 06:26:00 PM PDT 24
Peak memory 200084 kb
Host smart-91d1d946-fe29-4a30-9cf9-169864d16229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585177357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2585177357
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1604659889
Short name T69
Test name
Test status
Simulation time 177455058 ps
CPU time 1.2 seconds
Started Jun 29 06:25:57 PM PDT 24
Finished Jun 29 06:25:59 PM PDT 24
Peak memory 200096 kb
Host smart-492ddc3a-4cc5-4127-b4d5-b71f222dc811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604659889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1604659889
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3796408864
Short name T525
Test name
Test status
Simulation time 82742621 ps
CPU time 0.85 seconds
Started Jun 29 06:26:08 PM PDT 24
Finished Jun 29 06:26:09 PM PDT 24
Peak memory 199876 kb
Host smart-7a45d1b6-ef79-448d-8b7e-5570c894645b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796408864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3796408864
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.36466254
Short name T196
Test name
Test status
Simulation time 2179723183 ps
CPU time 9.34 seconds
Started Jun 29 06:26:07 PM PDT 24
Finished Jun 29 06:26:17 PM PDT 24
Peak memory 221748 kb
Host smart-0ef06740-2ded-4d12-a91f-5f2ed3f38dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36466254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.36466254
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3451261635
Short name T435
Test name
Test status
Simulation time 243572746 ps
CPU time 1.22 seconds
Started Jun 29 06:26:05 PM PDT 24
Finished Jun 29 06:26:06 PM PDT 24
Peak memory 217452 kb
Host smart-698e3e4c-62a5-445c-9524-e99d6ff401bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451261635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3451261635
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3976718945
Short name T194
Test name
Test status
Simulation time 198943376 ps
CPU time 0.89 seconds
Started Jun 29 06:26:06 PM PDT 24
Finished Jun 29 06:26:07 PM PDT 24
Peak memory 199900 kb
Host smart-f2c51a00-04e6-4738-9a9a-89d7118e5cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976718945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3976718945
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.445135868
Short name T414
Test name
Test status
Simulation time 1735219927 ps
CPU time 8.3 seconds
Started Jun 29 06:26:05 PM PDT 24
Finished Jun 29 06:26:14 PM PDT 24
Peak memory 200356 kb
Host smart-af088e9f-bba0-4059-a4d3-248b00034f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445135868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.445135868
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1052597683
Short name T475
Test name
Test status
Simulation time 98790997 ps
CPU time 1.06 seconds
Started Jun 29 06:26:07 PM PDT 24
Finished Jun 29 06:26:09 PM PDT 24
Peak memory 200088 kb
Host smart-e9b0d245-987a-4599-9787-2f1ed082265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052597683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1052597683
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3319751744
Short name T290
Test name
Test status
Simulation time 229747387 ps
CPU time 1.57 seconds
Started Jun 29 06:25:59 PM PDT 24
Finished Jun 29 06:26:01 PM PDT 24
Peak memory 200280 kb
Host smart-856632ad-ac9c-41fc-b053-69f927040c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319751744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3319751744
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2943618419
Short name T276
Test name
Test status
Simulation time 7733930797 ps
CPU time 26.4 seconds
Started Jun 29 06:26:03 PM PDT 24
Finished Jun 29 06:26:30 PM PDT 24
Peak memory 200408 kb
Host smart-ef8bf5e7-d737-4692-b914-de66dc2a472f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943618419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2943618419
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3685089643
Short name T148
Test name
Test status
Simulation time 142441936 ps
CPU time 1.94 seconds
Started Jun 29 06:26:04 PM PDT 24
Finished Jun 29 06:26:06 PM PDT 24
Peak memory 199996 kb
Host smart-9159a658-8055-4097-9fea-6b7997103d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685089643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3685089643
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.729933356
Short name T339
Test name
Test status
Simulation time 134775505 ps
CPU time 1.05 seconds
Started Jun 29 06:26:07 PM PDT 24
Finished Jun 29 06:26:08 PM PDT 24
Peak memory 200064 kb
Host smart-93dc00bf-de34-4bed-a087-999180097bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729933356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.729933356
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1003009786
Short name T243
Test name
Test status
Simulation time 75827944 ps
CPU time 0.81 seconds
Started Jun 29 06:26:04 PM PDT 24
Finished Jun 29 06:26:05 PM PDT 24
Peak memory 199876 kb
Host smart-4afb0329-461e-4b1e-991f-790549442717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003009786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1003009786
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.455137312
Short name T344
Test name
Test status
Simulation time 1230332298 ps
CPU time 6.47 seconds
Started Jun 29 06:26:05 PM PDT 24
Finished Jun 29 06:26:12 PM PDT 24
Peak memory 217736 kb
Host smart-dd887e6a-10e8-4d90-a8bd-36cb4dad823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455137312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.455137312
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3162725024
Short name T365
Test name
Test status
Simulation time 244325367 ps
CPU time 1.2 seconds
Started Jun 29 06:26:12 PM PDT 24
Finished Jun 29 06:26:14 PM PDT 24
Peak memory 217360 kb
Host smart-9f8ec151-7be4-486a-a45c-f8770caa06fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162725024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3162725024
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2797884573
Short name T15
Test name
Test status
Simulation time 201832133 ps
CPU time 0.91 seconds
Started Jun 29 06:26:04 PM PDT 24
Finished Jun 29 06:26:05 PM PDT 24
Peak memory 199900 kb
Host smart-3b919a61-6f19-40b3-8e96-c370250f0e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797884573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2797884573
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1190402724
Short name T352
Test name
Test status
Simulation time 1061575265 ps
CPU time 5.36 seconds
Started Jun 29 06:26:03 PM PDT 24
Finished Jun 29 06:26:09 PM PDT 24
Peak memory 200332 kb
Host smart-eea0ef18-66fe-43a6-8a4e-11c38afc686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190402724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1190402724
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.73423122
Short name T377
Test name
Test status
Simulation time 118161095 ps
CPU time 1.32 seconds
Started Jun 29 06:26:05 PM PDT 24
Finished Jun 29 06:26:07 PM PDT 24
Peak memory 200292 kb
Host smart-c79689fe-a2af-4bfe-ae8e-7a0ce5acf0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73423122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.73423122
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1838102184
Short name T288
Test name
Test status
Simulation time 11787743917 ps
CPU time 45.49 seconds
Started Jun 29 06:26:04 PM PDT 24
Finished Jun 29 06:26:50 PM PDT 24
Peak memory 208516 kb
Host smart-cd79482b-821a-446d-8289-1ac2f5747049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838102184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1838102184
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.369229875
Short name T416
Test name
Test status
Simulation time 416612366 ps
CPU time 2.7 seconds
Started Jun 29 06:26:04 PM PDT 24
Finished Jun 29 06:26:07 PM PDT 24
Peak memory 208284 kb
Host smart-d24e4264-e4b1-4077-baba-c3722130e9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369229875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.369229875
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3288490054
Short name T142
Test name
Test status
Simulation time 216206295 ps
CPU time 1.38 seconds
Started Jun 29 06:26:05 PM PDT 24
Finished Jun 29 06:26:07 PM PDT 24
Peak memory 200096 kb
Host smart-1a6a4d1a-c29c-405c-af93-6e2a132b1b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288490054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3288490054
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1976515017
Short name T139
Test name
Test status
Simulation time 62031000 ps
CPU time 0.77 seconds
Started Jun 29 06:26:12 PM PDT 24
Finished Jun 29 06:26:13 PM PDT 24
Peak memory 199872 kb
Host smart-6144d001-4c7c-433f-aa47-b0b3a89cacaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976515017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1976515017
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2768972163
Short name T175
Test name
Test status
Simulation time 244159618 ps
CPU time 1.13 seconds
Started Jun 29 06:26:10 PM PDT 24
Finished Jun 29 06:26:11 PM PDT 24
Peak memory 217452 kb
Host smart-a077a09b-f4bc-42c1-b7c1-29c67d1c2d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768972163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2768972163
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3109338139
Short name T247
Test name
Test status
Simulation time 193984590 ps
CPU time 0.96 seconds
Started Jun 29 06:26:04 PM PDT 24
Finished Jun 29 06:26:06 PM PDT 24
Peak memory 199856 kb
Host smart-3fe1535f-cb20-444f-a85f-0ac19680b904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109338139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3109338139
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1938159544
Short name T183
Test name
Test status
Simulation time 1612451344 ps
CPU time 7.12 seconds
Started Jun 29 06:26:05 PM PDT 24
Finished Jun 29 06:26:12 PM PDT 24
Peak memory 200344 kb
Host smart-2fcf0ef9-dd7b-482e-9283-7bc4916986f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938159544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1938159544
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1314470760
Short name T11
Test name
Test status
Simulation time 106869768 ps
CPU time 1.02 seconds
Started Jun 29 06:26:15 PM PDT 24
Finished Jun 29 06:26:17 PM PDT 24
Peak memory 200088 kb
Host smart-61c703d7-b259-48da-9c66-605dabd82252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314470760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1314470760
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.260874857
Short name T446
Test name
Test status
Simulation time 256363362 ps
CPU time 1.62 seconds
Started Jun 29 06:26:04 PM PDT 24
Finished Jun 29 06:26:06 PM PDT 24
Peak memory 200292 kb
Host smart-77ac400c-7eed-491f-bedc-6321afa30f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260874857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.260874857
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1373161241
Short name T484
Test name
Test status
Simulation time 7833892124 ps
CPU time 27.74 seconds
Started Jun 29 06:26:16 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 208572 kb
Host smart-52ff5f25-82ea-4a5b-b84a-1ee8ec317fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373161241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1373161241
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3610455897
Short name T503
Test name
Test status
Simulation time 339619480 ps
CPU time 2.22 seconds
Started Jun 29 06:26:15 PM PDT 24
Finished Jun 29 06:26:18 PM PDT 24
Peak memory 200084 kb
Host smart-753d655a-70e2-4c0a-b133-a0e08227bdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610455897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3610455897
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1742787144
Short name T129
Test name
Test status
Simulation time 91530661 ps
CPU time 0.91 seconds
Started Jun 29 06:26:14 PM PDT 24
Finished Jun 29 06:26:16 PM PDT 24
Peak memory 200096 kb
Host smart-ae9f0375-a0b9-4eee-b5c3-1f1f840aab9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742787144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1742787144
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1864170150
Short name T311
Test name
Test status
Simulation time 95030687 ps
CPU time 0.82 seconds
Started Jun 29 06:26:22 PM PDT 24
Finished Jun 29 06:26:24 PM PDT 24
Peak memory 199800 kb
Host smart-a788ed05-c1ed-4c42-b7ab-a5345fcdbb18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864170150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1864170150
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.554083130
Short name T43
Test name
Test status
Simulation time 1232007941 ps
CPU time 5.52 seconds
Started Jun 29 06:26:15 PM PDT 24
Finished Jun 29 06:26:21 PM PDT 24
Peak memory 221608 kb
Host smart-d109db25-f520-4877-be70-7fc74b7bcb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554083130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.554083130
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3948899425
Short name T340
Test name
Test status
Simulation time 244994003 ps
CPU time 1.19 seconds
Started Jun 29 06:26:10 PM PDT 24
Finished Jun 29 06:26:12 PM PDT 24
Peak memory 217392 kb
Host smart-c295da04-e440-4c30-9ac4-bf4950aba789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948899425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3948899425
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1630790996
Short name T477
Test name
Test status
Simulation time 91956068 ps
CPU time 0.79 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:13 PM PDT 24
Peak memory 199900 kb
Host smart-f16f65cf-d692-4183-b9e3-089b25ab8ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630790996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1630790996
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.287893122
Short name T42
Test name
Test status
Simulation time 187162338 ps
CPU time 1.26 seconds
Started Jun 29 06:26:12 PM PDT 24
Finished Jun 29 06:26:14 PM PDT 24
Peak memory 200084 kb
Host smart-ece0b3df-4a36-4e6f-af29-e5df45e058ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287893122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.287893122
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3825653979
Short name T49
Test name
Test status
Simulation time 259159679 ps
CPU time 1.73 seconds
Started Jun 29 06:26:10 PM PDT 24
Finished Jun 29 06:26:13 PM PDT 24
Peak memory 200284 kb
Host smart-aa5f67e6-6c90-4b15-abc1-4d57a6ca6a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825653979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3825653979
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3843068141
Short name T210
Test name
Test status
Simulation time 372528215 ps
CPU time 2.18 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:14 PM PDT 24
Peak memory 200040 kb
Host smart-9ccdf034-9efb-4d08-bebd-e5b7e84aa868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843068141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3843068141
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2968447503
Short name T318
Test name
Test status
Simulation time 161081965 ps
CPU time 1.11 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:13 PM PDT 24
Peak memory 200096 kb
Host smart-adf879cd-6936-43e1-a933-bd7d12f9f3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968447503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2968447503
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1748311378
Short name T369
Test name
Test status
Simulation time 94529364 ps
CPU time 0.93 seconds
Started Jun 29 06:25:29 PM PDT 24
Finished Jun 29 06:25:31 PM PDT 24
Peak memory 199872 kb
Host smart-8c67aeb6-9f51-44b1-b454-0de238db76aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748311378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1748311378
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2228773627
Short name T28
Test name
Test status
Simulation time 1216200660 ps
CPU time 5.85 seconds
Started Jun 29 06:25:30 PM PDT 24
Finished Jun 29 06:25:37 PM PDT 24
Peak memory 216752 kb
Host smart-006542aa-af63-433f-b821-87b3785e1864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228773627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2228773627
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.4281662777
Short name T514
Test name
Test status
Simulation time 243787138 ps
CPU time 1.11 seconds
Started Jun 29 06:25:32 PM PDT 24
Finished Jun 29 06:25:34 PM PDT 24
Peak memory 217384 kb
Host smart-a68e42eb-72dc-4149-9aca-89c557c97454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281662777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.4281662777
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2021007100
Short name T21
Test name
Test status
Simulation time 160866685 ps
CPU time 0.86 seconds
Started Jun 29 06:25:27 PM PDT 24
Finished Jun 29 06:25:28 PM PDT 24
Peak memory 199912 kb
Host smart-c55efaf0-9944-424b-b3fd-c39246fbb27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021007100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2021007100
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1245921910
Short name T412
Test name
Test status
Simulation time 918163082 ps
CPU time 4.76 seconds
Started Jun 29 06:25:29 PM PDT 24
Finished Jun 29 06:25:34 PM PDT 24
Peak memory 200344 kb
Host smart-c39bc289-012a-41a6-9f55-60ff5e52f3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245921910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1245921910
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3945801007
Short name T66
Test name
Test status
Simulation time 16947532918 ps
CPU time 25.85 seconds
Started Jun 29 06:25:31 PM PDT 24
Finished Jun 29 06:25:58 PM PDT 24
Peak memory 217216 kb
Host smart-1291d32b-b91e-40a3-a68f-1bd8be5e7382
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945801007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3945801007
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.721993987
Short name T376
Test name
Test status
Simulation time 110830564 ps
CPU time 1.01 seconds
Started Jun 29 06:25:30 PM PDT 24
Finished Jun 29 06:25:31 PM PDT 24
Peak memory 200084 kb
Host smart-753198c2-2314-42f5-94e2-70fbea925df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721993987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.721993987
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.427232163
Short name T325
Test name
Test status
Simulation time 191828956 ps
CPU time 1.45 seconds
Started Jun 29 06:25:30 PM PDT 24
Finished Jun 29 06:25:32 PM PDT 24
Peak memory 200292 kb
Host smart-627ba5ed-d0ff-4a81-8484-4638cfde7389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427232163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.427232163
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1372283855
Short name T89
Test name
Test status
Simulation time 12130915970 ps
CPU time 43.75 seconds
Started Jun 29 06:25:32 PM PDT 24
Finished Jun 29 06:26:16 PM PDT 24
Peak memory 208604 kb
Host smart-6360d382-868c-48ff-bf0b-cca14ba163b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372283855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1372283855
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1623331028
Short name T353
Test name
Test status
Simulation time 137985528 ps
CPU time 1.8 seconds
Started Jun 29 06:25:33 PM PDT 24
Finished Jun 29 06:25:35 PM PDT 24
Peak memory 200056 kb
Host smart-2a78edde-ef16-4183-bbc4-a07e6b6ca73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623331028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1623331028
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2012566377
Short name T431
Test name
Test status
Simulation time 212153857 ps
CPU time 1.32 seconds
Started Jun 29 06:25:30 PM PDT 24
Finished Jun 29 06:25:32 PM PDT 24
Peak memory 200096 kb
Host smart-e768d3c5-d46c-422c-ace2-b87bc5856fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012566377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2012566377
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1191692882
Short name T132
Test name
Test status
Simulation time 84574606 ps
CPU time 0.88 seconds
Started Jun 29 06:26:12 PM PDT 24
Finished Jun 29 06:26:13 PM PDT 24
Peak memory 199876 kb
Host smart-60789acd-4f0d-4829-8833-07a2ff2da338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191692882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1191692882
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2662836486
Short name T444
Test name
Test status
Simulation time 1229249833 ps
CPU time 5.68 seconds
Started Jun 29 06:26:12 PM PDT 24
Finished Jun 29 06:26:19 PM PDT 24
Peak memory 217784 kb
Host smart-8fff5e8b-d7d8-428b-bd41-5cf5e72b591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662836486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2662836486
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3349376305
Short name T428
Test name
Test status
Simulation time 244571376 ps
CPU time 1.17 seconds
Started Jun 29 06:26:15 PM PDT 24
Finished Jun 29 06:26:17 PM PDT 24
Peak memory 217360 kb
Host smart-8fc1671f-f5df-41ae-a663-6c59d38f6e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349376305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3349376305
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3938084197
Short name T217
Test name
Test status
Simulation time 141117937 ps
CPU time 0.92 seconds
Started Jun 29 06:26:12 PM PDT 24
Finished Jun 29 06:26:14 PM PDT 24
Peak memory 199900 kb
Host smart-3929f65e-f6bf-4511-8962-e42b2fbe4a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938084197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3938084197
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1572939858
Short name T3
Test name
Test status
Simulation time 962448846 ps
CPU time 5.24 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:18 PM PDT 24
Peak memory 200344 kb
Host smart-22de45f7-f824-450f-8592-63ff56bb7f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572939858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1572939858
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2297112249
Short name T441
Test name
Test status
Simulation time 143320803 ps
CPU time 1.14 seconds
Started Jun 29 06:26:15 PM PDT 24
Finished Jun 29 06:26:17 PM PDT 24
Peak memory 200048 kb
Host smart-d6b4c27f-9246-4810-b864-b339bf70f2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297112249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2297112249
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.4097393254
Short name T302
Test name
Test status
Simulation time 248209045 ps
CPU time 1.65 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:13 PM PDT 24
Peak memory 200276 kb
Host smart-9da4c79a-487c-452f-a57b-1eb6743b5ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097393254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.4097393254
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.779484162
Short name T545
Test name
Test status
Simulation time 1888995258 ps
CPU time 9.88 seconds
Started Jun 29 06:26:12 PM PDT 24
Finished Jun 29 06:26:23 PM PDT 24
Peak memory 209916 kb
Host smart-3702f729-f92e-4b40-b5cc-ab44fda8f1f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779484162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.779484162
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2108069399
Short name T354
Test name
Test status
Simulation time 143706651 ps
CPU time 1.75 seconds
Started Jun 29 06:26:12 PM PDT 24
Finished Jun 29 06:26:15 PM PDT 24
Peak memory 208280 kb
Host smart-4d5c4224-0a47-468e-9020-6174b0ab07f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108069399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2108069399
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.378163669
Short name T498
Test name
Test status
Simulation time 76439960 ps
CPU time 0.88 seconds
Started Jun 29 06:26:13 PM PDT 24
Finished Jun 29 06:26:15 PM PDT 24
Peak memory 200004 kb
Host smart-b401de6d-0469-459d-a9c3-3b037a2db861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378163669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.378163669
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2548556039
Short name T392
Test name
Test status
Simulation time 58408708 ps
CPU time 0.77 seconds
Started Jun 29 06:26:14 PM PDT 24
Finished Jun 29 06:26:16 PM PDT 24
Peak memory 199876 kb
Host smart-e6c8c095-19ea-4921-9759-000445d66409
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548556039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2548556039
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2096252466
Short name T12
Test name
Test status
Simulation time 1226339223 ps
CPU time 6.27 seconds
Started Jun 29 06:26:12 PM PDT 24
Finished Jun 29 06:26:19 PM PDT 24
Peak memory 217624 kb
Host smart-c524ed65-1ec9-4d05-95ad-91d26f95fb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096252466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2096252466
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.822484366
Short name T479
Test name
Test status
Simulation time 244780036 ps
CPU time 1.07 seconds
Started Jun 29 06:26:20 PM PDT 24
Finished Jun 29 06:26:22 PM PDT 24
Peak memory 217400 kb
Host smart-0a3c702e-8399-4e5f-8b9a-6dc2d6f936a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822484366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.822484366
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1324332005
Short name T193
Test name
Test status
Simulation time 145952989 ps
CPU time 0.89 seconds
Started Jun 29 06:26:15 PM PDT 24
Finished Jun 29 06:26:17 PM PDT 24
Peak memory 199900 kb
Host smart-55d19b8b-4b3d-425c-8668-4f2e41ec757d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324332005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1324332005
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1687590300
Short name T126
Test name
Test status
Simulation time 886207110 ps
CPU time 5.05 seconds
Started Jun 29 06:26:14 PM PDT 24
Finished Jun 29 06:26:20 PM PDT 24
Peak memory 200252 kb
Host smart-7da7f61c-4a93-4278-9e65-e6768046f3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687590300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1687590300
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.4042510680
Short name T275
Test name
Test status
Simulation time 141738109 ps
CPU time 1.21 seconds
Started Jun 29 06:26:12 PM PDT 24
Finished Jun 29 06:26:14 PM PDT 24
Peak memory 200016 kb
Host smart-d2ed06d3-3d8a-473b-8104-1867bade8564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042510680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.4042510680
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1138328994
Short name T59
Test name
Test status
Simulation time 263814964 ps
CPU time 1.55 seconds
Started Jun 29 06:26:15 PM PDT 24
Finished Jun 29 06:26:17 PM PDT 24
Peak memory 200236 kb
Host smart-23eabc4e-32a2-4605-913f-ad9b9845d50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138328994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1138328994
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3416710021
Short name T375
Test name
Test status
Simulation time 1443745628 ps
CPU time 5.69 seconds
Started Jun 29 06:26:15 PM PDT 24
Finished Jun 29 06:26:21 PM PDT 24
Peak memory 200344 kb
Host smart-cd0fcd1d-49e4-418d-96aa-64985c4ce71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416710021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3416710021
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.202461732
Short name T140
Test name
Test status
Simulation time 384873803 ps
CPU time 2.1 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:14 PM PDT 24
Peak memory 200088 kb
Host smart-d08534ca-d2a9-4fbf-8d03-a882654fac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202461732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.202461732
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2688833734
Short name T332
Test name
Test status
Simulation time 243875984 ps
CPU time 1.5 seconds
Started Jun 29 06:26:11 PM PDT 24
Finished Jun 29 06:26:13 PM PDT 24
Peak memory 200340 kb
Host smart-e0ecce8f-64f5-4b88-89d0-f70ce4dac55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688833734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2688833734
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3673351652
Short name T180
Test name
Test status
Simulation time 64107094 ps
CPU time 0.81 seconds
Started Jun 29 06:26:19 PM PDT 24
Finished Jun 29 06:26:20 PM PDT 24
Peak memory 199784 kb
Host smart-67b1a749-0a48-4af6-bb2a-7071f3394e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673351652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3673351652
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.697882620
Short name T541
Test name
Test status
Simulation time 1890920161 ps
CPU time 7.88 seconds
Started Jun 29 06:26:21 PM PDT 24
Finished Jun 29 06:26:29 PM PDT 24
Peak memory 221632 kb
Host smart-67632723-33b2-47bd-84c8-3f8cabfabaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697882620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.697882620
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1904649752
Short name T256
Test name
Test status
Simulation time 244440921 ps
CPU time 1.05 seconds
Started Jun 29 06:26:20 PM PDT 24
Finished Jun 29 06:26:22 PM PDT 24
Peak memory 217460 kb
Host smart-b99cf6d7-a460-4683-99d2-f2feb761b625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904649752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1904649752
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.104944409
Short name T480
Test name
Test status
Simulation time 163833316 ps
CPU time 0.84 seconds
Started Jun 29 06:26:20 PM PDT 24
Finished Jun 29 06:26:22 PM PDT 24
Peak memory 199816 kb
Host smart-380c05b7-8c46-4717-bca3-dd7fd453392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104944409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.104944409
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.572176910
Short name T271
Test name
Test status
Simulation time 1158249360 ps
CPU time 5.08 seconds
Started Jun 29 06:26:20 PM PDT 24
Finished Jun 29 06:26:26 PM PDT 24
Peak memory 200328 kb
Host smart-eee48e14-bd84-4ea5-a298-aceba2883c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572176910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.572176910
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3379770147
Short name T543
Test name
Test status
Simulation time 99995966 ps
CPU time 1.03 seconds
Started Jun 29 06:26:23 PM PDT 24
Finished Jun 29 06:26:25 PM PDT 24
Peak memory 200068 kb
Host smart-ee6eb881-05eb-4e53-ba43-87906d9d3f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379770147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3379770147
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3338705122
Short name T54
Test name
Test status
Simulation time 208458082 ps
CPU time 1.43 seconds
Started Jun 29 06:26:22 PM PDT 24
Finished Jun 29 06:26:25 PM PDT 24
Peak memory 200224 kb
Host smart-3d024f45-060a-4afa-8909-a7864e9280f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338705122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3338705122
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1011909924
Short name T449
Test name
Test status
Simulation time 4394986821 ps
CPU time 20.34 seconds
Started Jun 29 06:26:24 PM PDT 24
Finished Jun 29 06:26:45 PM PDT 24
Peak memory 200452 kb
Host smart-71e957be-d436-4ebf-a429-0e2bf15bf458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011909924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1011909924
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3758358362
Short name T540
Test name
Test status
Simulation time 125313877 ps
CPU time 1.6 seconds
Started Jun 29 06:26:22 PM PDT 24
Finished Jun 29 06:26:25 PM PDT 24
Peak memory 208232 kb
Host smart-eeb935e2-7b1c-4e23-8bb8-1bf63ba3d310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758358362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3758358362
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1957195418
Short name T71
Test name
Test status
Simulation time 109983460 ps
CPU time 1.02 seconds
Started Jun 29 06:26:21 PM PDT 24
Finished Jun 29 06:26:22 PM PDT 24
Peak memory 200096 kb
Host smart-92e9f428-6641-418d-8438-1ba3629a8409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957195418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1957195418
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.21336183
Short name T65
Test name
Test status
Simulation time 67703342 ps
CPU time 0.81 seconds
Started Jun 29 06:26:21 PM PDT 24
Finished Jun 29 06:26:23 PM PDT 24
Peak memory 199884 kb
Host smart-e0de9cae-12a0-4923-9f7c-6e0ff36f2a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21336183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.21336183
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1004125675
Short name T235
Test name
Test status
Simulation time 1896835133 ps
CPU time 7.71 seconds
Started Jun 29 06:26:20 PM PDT 24
Finished Jun 29 06:26:28 PM PDT 24
Peak memory 221612 kb
Host smart-0b4f1266-3ce1-42eb-9bbd-038bd48b12e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004125675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1004125675
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1474619988
Short name T351
Test name
Test status
Simulation time 243662346 ps
CPU time 1.13 seconds
Started Jun 29 06:26:22 PM PDT 24
Finished Jun 29 06:26:25 PM PDT 24
Peak memory 217468 kb
Host smart-83b10985-5a60-41a9-9591-78ca5b27922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474619988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1474619988
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2465737619
Short name T447
Test name
Test status
Simulation time 95109749 ps
CPU time 0.87 seconds
Started Jun 29 06:26:22 PM PDT 24
Finished Jun 29 06:26:24 PM PDT 24
Peak memory 199900 kb
Host smart-cfe2f6a7-bea7-4da2-a31c-79e851472a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465737619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2465737619
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2671848089
Short name T360
Test name
Test status
Simulation time 835129666 ps
CPU time 4.02 seconds
Started Jun 29 06:26:19 PM PDT 24
Finished Jun 29 06:26:23 PM PDT 24
Peak memory 200388 kb
Host smart-856b98c6-1d1a-45c0-8289-ed879b650446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671848089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2671848089
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3473305524
Short name T236
Test name
Test status
Simulation time 110235103 ps
CPU time 1.08 seconds
Started Jun 29 06:26:22 PM PDT 24
Finished Jun 29 06:26:24 PM PDT 24
Peak memory 200032 kb
Host smart-50f9740d-f43e-4e2d-baa8-9dc77e5fd1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473305524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3473305524
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.26478455
Short name T413
Test name
Test status
Simulation time 202773020 ps
CPU time 1.46 seconds
Started Jun 29 06:26:22 PM PDT 24
Finished Jun 29 06:26:25 PM PDT 24
Peak memory 200292 kb
Host smart-ab3c0ff0-cc7f-4671-90a0-a25c854ce90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26478455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.26478455
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.206934552
Short name T39
Test name
Test status
Simulation time 278109924 ps
CPU time 1.53 seconds
Started Jun 29 06:26:21 PM PDT 24
Finished Jun 29 06:26:23 PM PDT 24
Peak memory 200060 kb
Host smart-abeb43f0-9cb7-4b3b-8ba2-5474ffafdaf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206934552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.206934552
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1856700024
Short name T309
Test name
Test status
Simulation time 423983683 ps
CPU time 2.84 seconds
Started Jun 29 06:26:23 PM PDT 24
Finished Jun 29 06:26:27 PM PDT 24
Peak memory 200096 kb
Host smart-47cd7da6-bbeb-47a8-a55a-37b494fd9753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856700024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1856700024
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.60036018
Short name T518
Test name
Test status
Simulation time 215406612 ps
CPU time 1.29 seconds
Started Jun 29 06:26:20 PM PDT 24
Finished Jun 29 06:26:22 PM PDT 24
Peak memory 200072 kb
Host smart-37d9a0ae-d7cd-4f6a-b596-6fc9e086be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60036018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.60036018
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3474046780
Short name T24
Test name
Test status
Simulation time 66327123 ps
CPU time 0.78 seconds
Started Jun 29 06:26:18 PM PDT 24
Finished Jun 29 06:26:19 PM PDT 24
Peak memory 199852 kb
Host smart-7f0876fa-1f7f-461f-9f86-af84084a4487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474046780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3474046780
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3759624429
Short name T36
Test name
Test status
Simulation time 1881345755 ps
CPU time 7.23 seconds
Started Jun 29 06:26:20 PM PDT 24
Finished Jun 29 06:26:27 PM PDT 24
Peak memory 217736 kb
Host smart-8becd4d7-08b1-4166-8c69-a658a9df5b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759624429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3759624429
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.122917110
Short name T258
Test name
Test status
Simulation time 244447018 ps
CPU time 1.07 seconds
Started Jun 29 06:26:22 PM PDT 24
Finished Jun 29 06:26:25 PM PDT 24
Peak memory 217392 kb
Host smart-efb8d3e1-f217-49bb-b548-517ecf72b4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122917110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.122917110
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1723503610
Short name T523
Test name
Test status
Simulation time 91945293 ps
CPU time 0.76 seconds
Started Jun 29 06:26:21 PM PDT 24
Finished Jun 29 06:26:23 PM PDT 24
Peak memory 199840 kb
Host smart-f29acd0a-98c2-4fe0-9b8a-4dab71bb8c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723503610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1723503610
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3379167666
Short name T346
Test name
Test status
Simulation time 1681371382 ps
CPU time 7.06 seconds
Started Jun 29 06:26:23 PM PDT 24
Finished Jun 29 06:26:31 PM PDT 24
Peak memory 200388 kb
Host smart-df36fce4-e82b-4cd5-864a-10b57951fab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379167666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3379167666
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.824561814
Short name T146
Test name
Test status
Simulation time 163197279 ps
CPU time 1.14 seconds
Started Jun 29 06:26:20 PM PDT 24
Finished Jun 29 06:26:21 PM PDT 24
Peak memory 200096 kb
Host smart-57dffe75-1d2a-4357-bd0d-654b6d9eeff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824561814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.824561814
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2438417915
Short name T411
Test name
Test status
Simulation time 255445263 ps
CPU time 1.54 seconds
Started Jun 29 06:26:21 PM PDT 24
Finished Jun 29 06:26:23 PM PDT 24
Peak memory 200276 kb
Host smart-9ef4ec77-4f5f-4e1c-9aae-5ce70a64f46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438417915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2438417915
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.822640448
Short name T469
Test name
Test status
Simulation time 6824876667 ps
CPU time 30.73 seconds
Started Jun 29 06:26:22 PM PDT 24
Finished Jun 29 06:26:54 PM PDT 24
Peak memory 208604 kb
Host smart-ebeb939d-8195-4822-b819-ce111f791661
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822640448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.822640448
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2414767539
Short name T299
Test name
Test status
Simulation time 339494651 ps
CPU time 2.36 seconds
Started Jun 29 06:26:21 PM PDT 24
Finished Jun 29 06:26:24 PM PDT 24
Peak memory 200084 kb
Host smart-b2c71bbe-22c3-47b0-a812-48baeadbd923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414767539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2414767539
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1061279052
Short name T384
Test name
Test status
Simulation time 184787863 ps
CPU time 1.24 seconds
Started Jun 29 06:26:20 PM PDT 24
Finished Jun 29 06:26:22 PM PDT 24
Peak memory 200096 kb
Host smart-d5a63e57-15f5-4ccf-a412-6f726a4c89d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061279052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1061279052
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2794996721
Short name T323
Test name
Test status
Simulation time 57830085 ps
CPU time 0.8 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 199784 kb
Host smart-563c3aa1-8437-4ad4-9e18-4531d0ba1bd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794996721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2794996721
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2801571917
Short name T488
Test name
Test status
Simulation time 2163873187 ps
CPU time 8.23 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:42 PM PDT 24
Peak memory 217796 kb
Host smart-be3d55b8-30d9-449c-8552-e7ae12e62a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801571917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2801571917
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4139361476
Short name T51
Test name
Test status
Simulation time 243693027 ps
CPU time 1.2 seconds
Started Jun 29 06:26:30 PM PDT 24
Finished Jun 29 06:26:33 PM PDT 24
Peak memory 217428 kb
Host smart-1dbb3a92-ae8d-4c6d-bfd0-8a728370b1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139361476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4139361476
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2996299749
Short name T364
Test name
Test status
Simulation time 200699727 ps
CPU time 0.96 seconds
Started Jun 29 06:26:20 PM PDT 24
Finished Jun 29 06:26:21 PM PDT 24
Peak memory 199900 kb
Host smart-c9028dba-d260-4497-b99e-2c6420b59c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996299749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2996299749
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.4237126379
Short name T391
Test name
Test status
Simulation time 1328285757 ps
CPU time 5.15 seconds
Started Jun 29 06:26:21 PM PDT 24
Finished Jun 29 06:26:27 PM PDT 24
Peak memory 200348 kb
Host smart-c9381767-556e-476c-9c29-43f2aa3fb0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237126379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.4237126379
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3721220642
Short name T4
Test name
Test status
Simulation time 142235251 ps
CPU time 1.14 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 200032 kb
Host smart-62f7cbc5-64ea-407b-805d-d8c498fd5cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721220642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3721220642
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1284525867
Short name T138
Test name
Test status
Simulation time 113571509 ps
CPU time 1.25 seconds
Started Jun 29 06:26:21 PM PDT 24
Finished Jun 29 06:26:22 PM PDT 24
Peak memory 200276 kb
Host smart-c3a1c22c-b17b-4790-9c05-fb932e576681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284525867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1284525867
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1809703436
Short name T315
Test name
Test status
Simulation time 9799116746 ps
CPU time 41.53 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:27:16 PM PDT 24
Peak memory 208576 kb
Host smart-b13ea79b-8480-4a88-b7c0-475c8cf666c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809703436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1809703436
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1361132257
Short name T492
Test name
Test status
Simulation time 550447053 ps
CPU time 2.83 seconds
Started Jun 29 06:26:20 PM PDT 24
Finished Jun 29 06:26:23 PM PDT 24
Peak memory 200084 kb
Host smart-96219dc0-86f3-4a7a-bc4b-8e76f84a09ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361132257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1361132257
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.828858914
Short name T472
Test name
Test status
Simulation time 109246130 ps
CPU time 1.01 seconds
Started Jun 29 06:26:22 PM PDT 24
Finished Jun 29 06:26:24 PM PDT 24
Peak memory 200096 kb
Host smart-64b87944-e14a-4a0b-84eb-2163b8ff0976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828858914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.828858914
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3190340161
Short name T338
Test name
Test status
Simulation time 63703138 ps
CPU time 0.75 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:33 PM PDT 24
Peak memory 199864 kb
Host smart-cfe15aca-9a78-4fe2-ba6f-263e37617d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190340161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3190340161
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3628954946
Short name T34
Test name
Test status
Simulation time 1236503427 ps
CPU time 6 seconds
Started Jun 29 06:26:30 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 221584 kb
Host smart-40ec7ee1-cbd6-4454-915a-7680fba0fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628954946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3628954946
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2374768722
Short name T199
Test name
Test status
Simulation time 244696290 ps
CPU time 1.07 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 217452 kb
Host smart-a500a518-f450-47f9-97c4-a6cb5381a713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374768722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2374768722
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1487171947
Short name T20
Test name
Test status
Simulation time 210915637 ps
CPU time 0.98 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:26:36 PM PDT 24
Peak memory 199900 kb
Host smart-9f828884-6bdd-4b36-b6fc-42f09f667197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487171947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1487171947
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1563894990
Short name T238
Test name
Test status
Simulation time 2029847630 ps
CPU time 8.13 seconds
Started Jun 29 06:26:30 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 200388 kb
Host smart-9a9e7ac3-033b-4858-96ed-91034afe4307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563894990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1563894990
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.710777092
Short name T245
Test name
Test status
Simulation time 178107340 ps
CPU time 1.21 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 200108 kb
Host smart-d8211898-811b-4fac-9cf6-0712de8c2631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710777092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.710777092
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.4171172781
Short name T171
Test name
Test status
Simulation time 203447344 ps
CPU time 1.44 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:35 PM PDT 24
Peak memory 200280 kb
Host smart-c2141460-b2fa-4e24-8e5f-5799d8f2c3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171172781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4171172781
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1656854708
Short name T358
Test name
Test status
Simulation time 7782597734 ps
CPU time 29.48 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:27:01 PM PDT 24
Peak memory 210304 kb
Host smart-ac6a6bb5-fe79-40ca-87e0-639a89bdb5d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656854708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1656854708
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3143576886
Short name T424
Test name
Test status
Simulation time 129748208 ps
CPU time 1.81 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 208276 kb
Host smart-5befaec3-bef5-4daf-bf47-2ead0c156277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143576886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3143576886
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3344579657
Short name T328
Test name
Test status
Simulation time 83955262 ps
CPU time 0.9 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:33 PM PDT 24
Peak memory 200096 kb
Host smart-bfbda0ca-9bb5-4fa8-8b62-4156a2ade2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344579657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3344579657
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2394404129
Short name T359
Test name
Test status
Simulation time 72109742 ps
CPU time 0.82 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 199872 kb
Host smart-a74b50df-172f-425f-95b9-835ac295a543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394404129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2394404129
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3010905681
Short name T268
Test name
Test status
Simulation time 1882619411 ps
CPU time 7.27 seconds
Started Jun 29 06:26:35 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 221628 kb
Host smart-97273f79-dcc4-41ca-b1e6-6ee4fb300ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010905681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3010905681
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.769708944
Short name T483
Test name
Test status
Simulation time 244451505 ps
CPU time 1.06 seconds
Started Jun 29 06:26:30 PM PDT 24
Finished Jun 29 06:26:32 PM PDT 24
Peak memory 217448 kb
Host smart-732761c8-0d3a-4a2b-bc5c-d261e28d2cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769708944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.769708944
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3875104902
Short name T397
Test name
Test status
Simulation time 231416194 ps
CPU time 0.91 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 199880 kb
Host smart-95f96904-4a01-438f-b935-4d28f0143c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875104902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3875104902
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3690651426
Short name T82
Test name
Test status
Simulation time 892993311 ps
CPU time 4.63 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 200332 kb
Host smart-dbd3271c-eabc-4d89-9660-1dcbddeda371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690651426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3690651426
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2198599666
Short name T167
Test name
Test status
Simulation time 95956529 ps
CPU time 0.99 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:26:36 PM PDT 24
Peak memory 200088 kb
Host smart-6a72796e-0dc3-479a-9cea-ef9da327740f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198599666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2198599666
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.945086478
Short name T215
Test name
Test status
Simulation time 123947685 ps
CPU time 1.29 seconds
Started Jun 29 06:26:30 PM PDT 24
Finished Jun 29 06:26:32 PM PDT 24
Peak memory 200200 kb
Host smart-3f852cd2-83f8-457c-912f-8ffdfdac74f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945086478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.945086478
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3363333368
Short name T90
Test name
Test status
Simulation time 3093131595 ps
CPU time 11.62 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:43 PM PDT 24
Peak memory 200408 kb
Host smart-e8b92198-3113-424d-abfb-831230e4a27f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363333368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3363333368
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.240208563
Short name T366
Test name
Test status
Simulation time 121738673 ps
CPU time 1.59 seconds
Started Jun 29 06:26:29 PM PDT 24
Finished Jun 29 06:26:32 PM PDT 24
Peak memory 208328 kb
Host smart-669f6c90-5ba7-4591-a91c-b6eebf14db70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240208563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.240208563
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2055646896
Short name T321
Test name
Test status
Simulation time 233832029 ps
CPU time 1.43 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:35 PM PDT 24
Peak memory 200096 kb
Host smart-5b8f83ed-6bbe-45b2-b505-d5531d5e3625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055646896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2055646896
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1657841372
Short name T130
Test name
Test status
Simulation time 89454627 ps
CPU time 0.82 seconds
Started Jun 29 06:26:30 PM PDT 24
Finished Jun 29 06:26:32 PM PDT 24
Peak memory 199876 kb
Host smart-262e247c-002c-4c26-baec-61403616e591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657841372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1657841372
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3685127013
Short name T502
Test name
Test status
Simulation time 1226532189 ps
CPU time 5.99 seconds
Started Jun 29 06:26:30 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 216856 kb
Host smart-1f82fd74-d447-41c2-a945-009442284614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685127013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3685127013
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.351756981
Short name T398
Test name
Test status
Simulation time 243453588 ps
CPU time 1.07 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:35 PM PDT 24
Peak memory 217456 kb
Host smart-2608370e-cf9d-4d42-ad1c-0622ae4aa4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351756981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.351756981
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.645990153
Short name T458
Test name
Test status
Simulation time 122999029 ps
CPU time 0.82 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:26:35 PM PDT 24
Peak memory 199916 kb
Host smart-f373bc63-1fcb-43e1-bfab-3d4ec600c8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645990153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.645990153
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3682430581
Short name T356
Test name
Test status
Simulation time 851672253 ps
CPU time 5.02 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:26:40 PM PDT 24
Peak memory 200344 kb
Host smart-0c4fecc7-f750-400d-a254-3c3fb6bee0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682430581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3682430581
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2312453729
Short name T200
Test name
Test status
Simulation time 98367760 ps
CPU time 1.05 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:36 PM PDT 24
Peak memory 200088 kb
Host smart-89af97f7-2f7d-4b6e-9c08-dbfbb6ca382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312453729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2312453729
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.451434583
Short name T226
Test name
Test status
Simulation time 119829662 ps
CPU time 1.3 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 200292 kb
Host smart-1475b363-e2f5-45a2-b19a-02a13a8c4945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451434583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.451434583
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2678606510
Short name T425
Test name
Test status
Simulation time 5925571159 ps
CPU time 27.44 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:27:03 PM PDT 24
Peak memory 208596 kb
Host smart-3bd13482-e328-482d-adef-c002696adbe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678606510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2678606510
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.95001013
Short name T179
Test name
Test status
Simulation time 336037985 ps
CPU time 2.19 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 200088 kb
Host smart-8c5d5a6a-639e-4cf6-92e7-b9f117f811b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95001013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.95001013
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2452861626
Short name T327
Test name
Test status
Simulation time 119158508 ps
CPU time 1.03 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 200056 kb
Host smart-2bd47bd4-de38-49f7-8ac0-06efd35e99df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452861626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2452861626
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3885004273
Short name T48
Test name
Test status
Simulation time 69615085 ps
CPU time 0.84 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 199872 kb
Host smart-e1ad6fa6-f894-4b60-a9de-2aa00e129b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885004273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3885004273
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3868446540
Short name T29
Test name
Test status
Simulation time 2340843672 ps
CPU time 8.28 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 217300 kb
Host smart-ddcc08f7-337f-44cb-bc48-556deb8366da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868446540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3868446540
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3327357284
Short name T528
Test name
Test status
Simulation time 244583545 ps
CPU time 1.08 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:33 PM PDT 24
Peak memory 217452 kb
Host smart-4af7504d-a06c-461e-8401-9fdc185c5855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327357284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3327357284
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2591677821
Short name T333
Test name
Test status
Simulation time 94455108 ps
CPU time 0.78 seconds
Started Jun 29 06:26:30 PM PDT 24
Finished Jun 29 06:26:31 PM PDT 24
Peak memory 199900 kb
Host smart-fa3de822-b8dc-40ae-bf6a-e0666647a2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591677821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2591677821
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1026413223
Short name T50
Test name
Test status
Simulation time 833659220 ps
CPU time 3.92 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 200344 kb
Host smart-d9552bbc-299e-405e-ac64-0ddb332f8af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026413223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1026413223
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1638347330
Short name T195
Test name
Test status
Simulation time 159494849 ps
CPU time 1.31 seconds
Started Jun 29 06:26:29 PM PDT 24
Finished Jun 29 06:26:31 PM PDT 24
Peak memory 200088 kb
Host smart-459b0134-a793-4dbb-ae61-e81c64121789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638347330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1638347330
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1432269829
Short name T445
Test name
Test status
Simulation time 240824182 ps
CPU time 1.54 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 200292 kb
Host smart-23f335cf-c61a-4f39-b1bd-cb69ab1fcc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432269829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1432269829
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1340437915
Short name T176
Test name
Test status
Simulation time 2725133027 ps
CPU time 12.69 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:46 PM PDT 24
Peak memory 200424 kb
Host smart-dd72453a-f466-4686-abae-645f1e1ea719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340437915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1340437915
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2160754445
Short name T427
Test name
Test status
Simulation time 379108705 ps
CPU time 2.46 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 200084 kb
Host smart-33fc6ea0-6e7d-4578-97d9-7d8e7181d6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160754445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2160754445
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1694458921
Short name T300
Test name
Test status
Simulation time 175859251 ps
CPU time 1.27 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 200084 kb
Host smart-e9481f4f-6c5b-472b-82ec-5f0b92f6beec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694458921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1694458921
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1412997711
Short name T473
Test name
Test status
Simulation time 68565450 ps
CPU time 0.8 seconds
Started Jun 29 06:25:40 PM PDT 24
Finished Jun 29 06:25:41 PM PDT 24
Peak memory 199876 kb
Host smart-0671dc11-29ad-44ab-9353-13cd14351caf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412997711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1412997711
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1480781523
Short name T305
Test name
Test status
Simulation time 1226544808 ps
CPU time 5.69 seconds
Started Jun 29 06:25:41 PM PDT 24
Finished Jun 29 06:25:47 PM PDT 24
Peak memory 221680 kb
Host smart-6f38cbeb-0914-4c29-b297-5532bf407a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480781523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1480781523
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1824287792
Short name T467
Test name
Test status
Simulation time 246541167 ps
CPU time 1.09 seconds
Started Jun 29 06:25:38 PM PDT 24
Finished Jun 29 06:25:40 PM PDT 24
Peak memory 217468 kb
Host smart-8d63d30f-aacb-481f-a894-7765ecb468e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824287792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1824287792
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3081316005
Short name T229
Test name
Test status
Simulation time 174906163 ps
CPU time 0.9 seconds
Started Jun 29 06:25:28 PM PDT 24
Finished Jun 29 06:25:30 PM PDT 24
Peak memory 199900 kb
Host smart-d1b3c980-e813-4277-99b8-6526890316ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081316005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3081316005
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3089705868
Short name T440
Test name
Test status
Simulation time 1364083999 ps
CPU time 5.67 seconds
Started Jun 29 06:25:29 PM PDT 24
Finished Jun 29 06:25:35 PM PDT 24
Peak memory 200404 kb
Host smart-244a9b26-84a8-44d5-b6b1-b9c56e452880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089705868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3089705868
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3753760331
Short name T443
Test name
Test status
Simulation time 104156018 ps
CPU time 0.97 seconds
Started Jun 29 06:25:36 PM PDT 24
Finished Jun 29 06:25:38 PM PDT 24
Peak memory 200004 kb
Host smart-c2830925-a770-4ee2-b285-144ddf4f4c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753760331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3753760331
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.292844721
Short name T287
Test name
Test status
Simulation time 113482182 ps
CPU time 1.22 seconds
Started Jun 29 06:25:30 PM PDT 24
Finished Jun 29 06:25:32 PM PDT 24
Peak memory 200292 kb
Host smart-578a8399-0886-42a1-845b-83d2e214042e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292844721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.292844721
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3653838096
Short name T373
Test name
Test status
Simulation time 3436144333 ps
CPU time 16.57 seconds
Started Jun 29 06:25:39 PM PDT 24
Finished Jun 29 06:25:56 PM PDT 24
Peak memory 208608 kb
Host smart-79fd2f00-9eb1-4d67-b6cb-f64120765b85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653838096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3653838096
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.864620955
Short name T314
Test name
Test status
Simulation time 145986736 ps
CPU time 2.01 seconds
Started Jun 29 06:25:37 PM PDT 24
Finished Jun 29 06:25:39 PM PDT 24
Peak memory 200036 kb
Host smart-c7143388-6f3a-4042-9928-4b821fc11447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864620955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.864620955
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2110390528
Short name T371
Test name
Test status
Simulation time 131731281 ps
CPU time 1.1 seconds
Started Jun 29 06:25:28 PM PDT 24
Finished Jun 29 06:25:30 PM PDT 24
Peak memory 200092 kb
Host smart-ad4c5a21-0437-435d-baab-69c73aec771a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110390528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2110390528
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3962005585
Short name T255
Test name
Test status
Simulation time 56522456 ps
CPU time 0.76 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:36 PM PDT 24
Peak memory 199876 kb
Host smart-4190601e-4033-4c6a-b169-455bb0bc384a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962005585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3962005585
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1158800113
Short name T491
Test name
Test status
Simulation time 1885249427 ps
CPU time 7.23 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:26:42 PM PDT 24
Peak memory 221716 kb
Host smart-b0b35be0-d028-4f38-9fa6-68641e628b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158800113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1158800113
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2475209758
Short name T486
Test name
Test status
Simulation time 244981885 ps
CPU time 1.06 seconds
Started Jun 29 06:26:39 PM PDT 24
Finished Jun 29 06:26:41 PM PDT 24
Peak memory 217452 kb
Host smart-37e0d788-b2cf-4e97-b411-8302a31d2eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475209758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2475209758
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.4146595630
Short name T463
Test name
Test status
Simulation time 109452944 ps
CPU time 0.79 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:33 PM PDT 24
Peak memory 199900 kb
Host smart-411bf4e5-f40a-44d7-9f4d-1bd72d9e667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146595630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.4146595630
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1977367319
Short name T214
Test name
Test status
Simulation time 1794718887 ps
CPU time 7.93 seconds
Started Jun 29 06:26:30 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 200340 kb
Host smart-42f3da3b-0c51-4556-a88f-22cc88122663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977367319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1977367319
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2460439658
Short name T482
Test name
Test status
Simulation time 172147388 ps
CPU time 1.19 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:33 PM PDT 24
Peak memory 200088 kb
Host smart-ecba1839-b7c2-4ecf-a25c-0a5315ec49c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460439658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2460439658
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1435424239
Short name T455
Test name
Test status
Simulation time 229273015 ps
CPU time 1.6 seconds
Started Jun 29 06:26:31 PM PDT 24
Finished Jun 29 06:26:35 PM PDT 24
Peak memory 200284 kb
Host smart-64fe20cc-1d89-494a-833e-476a3adc4502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435424239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1435424239
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3607008659
Short name T87
Test name
Test status
Simulation time 4150772556 ps
CPU time 18.69 seconds
Started Jun 29 06:26:37 PM PDT 24
Finished Jun 29 06:26:57 PM PDT 24
Peak memory 208572 kb
Host smart-65a1b391-b490-4102-9384-fa1d2d1c2d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607008659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3607008659
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2066094064
Short name T378
Test name
Test status
Simulation time 138070076 ps
CPU time 1.86 seconds
Started Jun 29 06:26:29 PM PDT 24
Finished Jun 29 06:26:32 PM PDT 24
Peak memory 200084 kb
Host smart-cb2d02f2-6ab9-4fd8-991b-7e474c8d711b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066094064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2066094064
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1255848698
Short name T382
Test name
Test status
Simulation time 192611757 ps
CPU time 1.2 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:26:36 PM PDT 24
Peak memory 200068 kb
Host smart-b9a257c9-e499-4f5a-8dd9-6f0605c9173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255848698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1255848698
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.126005251
Short name T310
Test name
Test status
Simulation time 64950952 ps
CPU time 0.79 seconds
Started Jun 29 06:26:40 PM PDT 24
Finished Jun 29 06:26:41 PM PDT 24
Peak memory 199892 kb
Host smart-597427d7-c5ad-487b-9aec-96f28dbe9f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126005251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.126005251
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1745160436
Short name T320
Test name
Test status
Simulation time 1219865224 ps
CPU time 6.13 seconds
Started Jun 29 06:26:38 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 217676 kb
Host smart-e20bfc38-4315-49bf-abff-fbf3c6721d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745160436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1745160436
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.64385128
Short name T522
Test name
Test status
Simulation time 244661966 ps
CPU time 1.07 seconds
Started Jun 29 06:26:37 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 217364 kb
Host smart-22ef3f0c-b193-4b3b-9916-feecad62ed57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64385128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.64385128
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.4167374490
Short name T14
Test name
Test status
Simulation time 162455863 ps
CPU time 0.9 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 199904 kb
Host smart-55b54309-f61a-47bf-9831-bfb476c71b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167374490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.4167374490
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.973295767
Short name T260
Test name
Test status
Simulation time 759320538 ps
CPU time 4.05 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 200368 kb
Host smart-00fba779-7ebe-413f-8c4c-e23e4bbbe5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973295767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.973295767
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.182014672
Short name T154
Test name
Test status
Simulation time 108904798 ps
CPU time 1.03 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:35 PM PDT 24
Peak memory 200076 kb
Host smart-c3fdf747-dc80-43ca-8bb0-226e35ba2d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182014672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.182014672
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2832895016
Short name T156
Test name
Test status
Simulation time 197624976 ps
CPU time 1.45 seconds
Started Jun 29 06:26:41 PM PDT 24
Finished Jun 29 06:26:43 PM PDT 24
Peak memory 200292 kb
Host smart-f3e81600-6b71-482b-b523-60447fc57fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832895016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2832895016
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3991160921
Short name T461
Test name
Test status
Simulation time 1289954878 ps
CPU time 6.34 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:42 PM PDT 24
Peak memory 200348 kb
Host smart-87c92988-138a-401c-936a-6cdfc6f2a2ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991160921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3991160921
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.95943220
Short name T489
Test name
Test status
Simulation time 309400464 ps
CPU time 2.3 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:38 PM PDT 24
Peak memory 208328 kb
Host smart-1907bc27-9a8c-4e53-8238-0065b2a91132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95943220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.95943220
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3478554066
Short name T316
Test name
Test status
Simulation time 265332595 ps
CPU time 1.54 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:26:36 PM PDT 24
Peak memory 200300 kb
Host smart-0ecbb711-6e53-4940-93e9-775df8b86b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478554066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3478554066
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1047808093
Short name T173
Test name
Test status
Simulation time 68323070 ps
CPU time 0.85 seconds
Started Jun 29 06:26:35 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 199888 kb
Host smart-6a01495b-9a25-4080-870c-1aa837b532e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047808093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1047808093
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3004767152
Short name T420
Test name
Test status
Simulation time 2361595793 ps
CPU time 8.23 seconds
Started Jun 29 06:26:41 PM PDT 24
Finished Jun 29 06:26:50 PM PDT 24
Peak memory 217868 kb
Host smart-21ef8d0f-46c7-4604-811f-3ad88f4365db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004767152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3004767152
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1926677185
Short name T133
Test name
Test status
Simulation time 243733871 ps
CPU time 1.16 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 217468 kb
Host smart-9ad424dc-b991-4170-8c42-ba2230db689e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926677185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1926677185
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1627782277
Short name T410
Test name
Test status
Simulation time 98110197 ps
CPU time 0.75 seconds
Started Jun 29 06:26:40 PM PDT 24
Finished Jun 29 06:26:41 PM PDT 24
Peak memory 199912 kb
Host smart-48380533-61aa-4376-93de-3d8775b20e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627782277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1627782277
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2084541889
Short name T91
Test name
Test status
Simulation time 1343008693 ps
CPU time 5.71 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:41 PM PDT 24
Peak memory 200348 kb
Host smart-f3736f3d-e2db-44a9-9ee7-1eee5d770296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084541889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2084541889
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.348271056
Short name T201
Test name
Test status
Simulation time 103242934 ps
CPU time 1.04 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 200096 kb
Host smart-469d01f9-236b-46f7-a743-fff8cf4b2a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348271056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.348271056
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.39331028
Short name T372
Test name
Test status
Simulation time 118776892 ps
CPU time 1.32 seconds
Started Jun 29 06:26:40 PM PDT 24
Finished Jun 29 06:26:42 PM PDT 24
Peak memory 200336 kb
Host smart-1ce0bfdc-3bc1-4218-825b-191f622132c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39331028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.39331028
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1453653595
Short name T120
Test name
Test status
Simulation time 2401851462 ps
CPU time 10.7 seconds
Started Jun 29 06:26:36 PM PDT 24
Finished Jun 29 06:26:48 PM PDT 24
Peak memory 200408 kb
Host smart-4b813297-9aee-4a01-956e-593088622294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453653595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1453653595
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.544176443
Short name T270
Test name
Test status
Simulation time 134991959 ps
CPU time 1.75 seconds
Started Jun 29 06:26:36 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 208328 kb
Host smart-5cab4593-f055-42e3-a4a8-592cfb8d68bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544176443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.544176443
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2299946041
Short name T296
Test name
Test status
Simulation time 134371256 ps
CPU time 1.15 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 200096 kb
Host smart-78e9387d-b64a-409e-873e-5f9329b42ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299946041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2299946041
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1740448405
Short name T396
Test name
Test status
Simulation time 87119471 ps
CPU time 0.85 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 199876 kb
Host smart-0f543296-5944-4924-acf2-f1b75476b49b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740448405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1740448405
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.961650032
Short name T460
Test name
Test status
Simulation time 2357013450 ps
CPU time 8.09 seconds
Started Jun 29 06:26:37 PM PDT 24
Finished Jun 29 06:26:46 PM PDT 24
Peak memory 217836 kb
Host smart-eedc0c73-75fe-4e50-afb5-5a2e7731209a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961650032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.961650032
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3284129559
Short name T517
Test name
Test status
Simulation time 243663270 ps
CPU time 1.21 seconds
Started Jun 29 06:26:36 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 217392 kb
Host smart-84d73685-4cb7-4f03-bbb7-91c1809c2d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284129559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3284129559
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3223744482
Short name T533
Test name
Test status
Simulation time 138528751 ps
CPU time 0.86 seconds
Started Jun 29 06:26:35 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 199900 kb
Host smart-1aff6917-7402-43a9-b40e-62d8924ec131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223744482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3223744482
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.710344520
Short name T418
Test name
Test status
Simulation time 1690216518 ps
CPU time 6.27 seconds
Started Jun 29 06:26:37 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 200316 kb
Host smart-c6b82c4a-1da5-41fe-86e6-708baa951bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710344520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.710344520
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3258461310
Short name T355
Test name
Test status
Simulation time 114621201 ps
CPU time 1.09 seconds
Started Jun 29 06:26:35 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 200088 kb
Host smart-aa2c4084-c470-478c-b568-348383d72b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258461310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3258461310
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.92999056
Short name T177
Test name
Test status
Simulation time 229358386 ps
CPU time 1.65 seconds
Started Jun 29 06:26:35 PM PDT 24
Finished Jun 29 06:26:38 PM PDT 24
Peak memory 200288 kb
Host smart-d70defa0-80f3-4dcb-a6dc-e60cabfc63b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92999056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.92999056
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2416874746
Short name T121
Test name
Test status
Simulation time 10690499972 ps
CPU time 44.39 seconds
Started Jun 29 06:26:36 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 200352 kb
Host smart-fb1c7e53-4d09-4890-9775-38997c1b3398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416874746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2416874746
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.606118925
Short name T389
Test name
Test status
Simulation time 423209473 ps
CPU time 2.27 seconds
Started Jun 29 06:26:37 PM PDT 24
Finished Jun 29 06:26:40 PM PDT 24
Peak memory 208284 kb
Host smart-02f77930-28a7-4f52-a303-5c50731d2ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606118925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.606118925
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.716783768
Short name T211
Test name
Test status
Simulation time 180238501 ps
CPU time 1.21 seconds
Started Jun 29 06:26:32 PM PDT 24
Finished Jun 29 06:26:36 PM PDT 24
Peak memory 200096 kb
Host smart-5f6e87c8-e3e6-43d7-a2ab-f3c6f83bf1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716783768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.716783768
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.719909284
Short name T203
Test name
Test status
Simulation time 71524836 ps
CPU time 0.78 seconds
Started Jun 29 06:26:40 PM PDT 24
Finished Jun 29 06:26:41 PM PDT 24
Peak memory 199896 kb
Host smart-3819d9f4-bdbd-4dab-bb09-2603a750a2c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719909284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.719909284
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.447732671
Short name T206
Test name
Test status
Simulation time 1900798838 ps
CPU time 7.79 seconds
Started Jun 29 06:26:38 PM PDT 24
Finished Jun 29 06:26:46 PM PDT 24
Peak memory 217716 kb
Host smart-f6b55bfb-bb8f-4826-8c30-ae0de3c8b34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447732671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.447732671
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2568886987
Short name T155
Test name
Test status
Simulation time 244536162 ps
CPU time 1.1 seconds
Started Jun 29 06:26:37 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 217452 kb
Host smart-5b261a66-eb41-4d58-8c86-710492d67f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568886987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2568886987
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3928681162
Short name T19
Test name
Test status
Simulation time 208207082 ps
CPU time 0.87 seconds
Started Jun 29 06:26:40 PM PDT 24
Finished Jun 29 06:26:41 PM PDT 24
Peak memory 199912 kb
Host smart-b15184d5-1004-4376-90c0-c58f17663a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928681162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3928681162
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1519958848
Short name T117
Test name
Test status
Simulation time 2138667027 ps
CPU time 8.35 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 200288 kb
Host smart-5afbb1fc-056f-4233-8dbd-82efecedc70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519958848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1519958848
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3699168953
Short name T165
Test name
Test status
Simulation time 110915375 ps
CPU time 1.17 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 200088 kb
Host smart-bd9caf1d-c746-4215-9688-0d47380e0248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699168953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3699168953
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.4248819741
Short name T399
Test name
Test status
Simulation time 121106834 ps
CPU time 1.26 seconds
Started Jun 29 06:26:35 PM PDT 24
Finished Jun 29 06:26:38 PM PDT 24
Peak memory 200276 kb
Host smart-9ea23e64-002b-425b-9067-64c39c1e4b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248819741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.4248819741
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1215691770
Short name T239
Test name
Test status
Simulation time 1876756098 ps
CPU time 7.13 seconds
Started Jun 29 06:26:35 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 200348 kb
Host smart-f88c656e-582f-4e82-b8dc-da852e7ee708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215691770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1215691770
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.335500998
Short name T277
Test name
Test status
Simulation time 389780817 ps
CPU time 2.42 seconds
Started Jun 29 06:26:35 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 208328 kb
Host smart-f34df334-4e5e-4c0b-95c1-47a5bd5e65a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335500998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.335500998
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1565376851
Short name T204
Test name
Test status
Simulation time 167898724 ps
CPU time 1.2 seconds
Started Jun 29 06:26:35 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 200076 kb
Host smart-8c02bad3-be06-47a1-9af0-a1e2e877a61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565376851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1565376851
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.4148299765
Short name T189
Test name
Test status
Simulation time 70357401 ps
CPU time 0.8 seconds
Started Jun 29 06:26:33 PM PDT 24
Finished Jun 29 06:26:35 PM PDT 24
Peak memory 199872 kb
Host smart-c4875820-3391-49bf-8936-d3071d629ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148299765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.4148299765
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1711482035
Short name T241
Test name
Test status
Simulation time 2350379137 ps
CPU time 8.63 seconds
Started Jun 29 06:26:34 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 217820 kb
Host smart-bc37fedd-4d52-48cc-92b8-ee8ea07f8c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711482035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1711482035
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3537462370
Short name T153
Test name
Test status
Simulation time 244498943 ps
CPU time 1.21 seconds
Started Jun 29 06:26:38 PM PDT 24
Finished Jun 29 06:26:40 PM PDT 24
Peak memory 217448 kb
Host smart-aa24f05c-2492-4709-8745-449dbf7b7e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537462370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3537462370
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1926010312
Short name T248
Test name
Test status
Simulation time 119733033 ps
CPU time 0.84 seconds
Started Jun 29 06:26:37 PM PDT 24
Finished Jun 29 06:26:38 PM PDT 24
Peak memory 199816 kb
Host smart-167c5513-58ce-4eaf-a245-0fe1ecc784ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926010312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1926010312
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1068919051
Short name T41
Test name
Test status
Simulation time 1472503157 ps
CPU time 5.75 seconds
Started Jun 29 06:26:36 PM PDT 24
Finished Jun 29 06:26:43 PM PDT 24
Peak memory 200388 kb
Host smart-89caa9bf-f9fc-486f-b11e-56ee6f1bec3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068919051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1068919051
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.509710868
Short name T394
Test name
Test status
Simulation time 109480084 ps
CPU time 1.01 seconds
Started Jun 29 06:26:37 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 199888 kb
Host smart-34924913-23cc-44bd-9bc2-2803a140313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509710868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.509710868
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2546487616
Short name T184
Test name
Test status
Simulation time 230913812 ps
CPU time 1.47 seconds
Started Jun 29 06:26:35 PM PDT 24
Finished Jun 29 06:26:38 PM PDT 24
Peak memory 200280 kb
Host smart-aafb2a06-8857-4af3-9041-a93fb3be99df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546487616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2546487616
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3356663620
Short name T182
Test name
Test status
Simulation time 4934148378 ps
CPU time 19.73 seconds
Started Jun 29 06:26:39 PM PDT 24
Finished Jun 29 06:26:59 PM PDT 24
Peak memory 200408 kb
Host smart-efb1317a-19d4-4f64-aea7-f3d0fe0750d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356663620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3356663620
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3912158942
Short name T162
Test name
Test status
Simulation time 360242906 ps
CPU time 2.21 seconds
Started Jun 29 06:26:37 PM PDT 24
Finished Jun 29 06:26:40 PM PDT 24
Peak memory 200040 kb
Host smart-d11e0b93-a47e-40f1-ba3c-e23559dfe76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912158942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3912158942
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.713150399
Short name T474
Test name
Test status
Simulation time 150775317 ps
CPU time 1.07 seconds
Started Jun 29 06:26:37 PM PDT 24
Finished Jun 29 06:26:39 PM PDT 24
Peak memory 199880 kb
Host smart-98bdc316-679e-46a1-8240-28d36aa4b723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713150399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.713150399
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.4100966751
Short name T487
Test name
Test status
Simulation time 56152146 ps
CPU time 0.72 seconds
Started Jun 29 06:26:43 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 199872 kb
Host smart-48b1b2bd-f5b5-4457-8fab-a40a88e9c426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100966751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.4100966751
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.326464276
Short name T279
Test name
Test status
Simulation time 1901380062 ps
CPU time 8.02 seconds
Started Jun 29 06:26:42 PM PDT 24
Finished Jun 29 06:26:51 PM PDT 24
Peak memory 221584 kb
Host smart-ae89d81b-ca6b-42b7-a789-ef153e0b9532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326464276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.326464276
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1447297656
Short name T456
Test name
Test status
Simulation time 243453961 ps
CPU time 1.1 seconds
Started Jun 29 06:26:45 PM PDT 24
Finished Jun 29 06:26:46 PM PDT 24
Peak memory 217452 kb
Host smart-abac165a-758f-4d24-aa03-2a49b11b9e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447297656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1447297656
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3547513164
Short name T419
Test name
Test status
Simulation time 93114665 ps
CPU time 0.82 seconds
Started Jun 29 06:27:39 PM PDT 24
Finished Jun 29 06:27:41 PM PDT 24
Peak memory 199852 kb
Host smart-fd9712b5-999d-4ce7-873f-3996bd19e454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547513164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3547513164
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3696199468
Short name T335
Test name
Test status
Simulation time 1469916508 ps
CPU time 6.65 seconds
Started Jun 29 06:26:46 PM PDT 24
Finished Jun 29 06:26:53 PM PDT 24
Peak memory 200320 kb
Host smart-8acd2fad-c527-4877-8793-e596da9fa6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696199468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3696199468
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2783919656
Short name T188
Test name
Test status
Simulation time 151664356 ps
CPU time 1.16 seconds
Started Jun 29 06:26:42 PM PDT 24
Finished Jun 29 06:26:43 PM PDT 24
Peak memory 200052 kb
Host smart-2f038d5e-f5dd-404b-8af3-3e7f3e01434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783919656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2783919656
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3394809966
Short name T74
Test name
Test status
Simulation time 254907800 ps
CPU time 1.58 seconds
Started Jun 29 06:26:42 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 200280 kb
Host smart-2db10b18-0a1a-4b89-8847-d20d2c2edf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394809966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3394809966
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1986214244
Short name T119
Test name
Test status
Simulation time 10445985519 ps
CPU time 36.49 seconds
Started Jun 29 06:26:50 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 208560 kb
Host smart-74e8968a-be98-406c-9bb0-015ec122afae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986214244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1986214244
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1068072863
Short name T147
Test name
Test status
Simulation time 124856309 ps
CPU time 1.58 seconds
Started Jun 29 06:26:42 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 208256 kb
Host smart-dfcf4937-9ac1-4353-a9e4-eb0e10e39539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068072863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1068072863
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.765553810
Short name T401
Test name
Test status
Simulation time 234279292 ps
CPU time 1.4 seconds
Started Jun 29 06:26:41 PM PDT 24
Finished Jun 29 06:26:43 PM PDT 24
Peak memory 200300 kb
Host smart-6dae99b2-9c88-4860-bf99-c28a217839cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765553810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.765553810
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1608407422
Short name T462
Test name
Test status
Simulation time 62530845 ps
CPU time 0.81 seconds
Started Jun 29 06:26:42 PM PDT 24
Finished Jun 29 06:26:43 PM PDT 24
Peak memory 199828 kb
Host smart-381552d3-0932-4cf5-b733-dc877d387b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608407422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1608407422
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1999306325
Short name T45
Test name
Test status
Simulation time 1221216975 ps
CPU time 6.07 seconds
Started Jun 29 06:26:47 PM PDT 24
Finished Jun 29 06:26:53 PM PDT 24
Peak memory 217480 kb
Host smart-d674ede0-d433-4bfd-aaf3-758b3e068dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999306325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1999306325
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1694849652
Short name T529
Test name
Test status
Simulation time 244273764 ps
CPU time 1.08 seconds
Started Jun 29 06:26:45 PM PDT 24
Finished Jun 29 06:26:46 PM PDT 24
Peak memory 217456 kb
Host smart-aadd6007-bb25-4922-b9f2-08f397c8c467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694849652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1694849652
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3147410726
Short name T524
Test name
Test status
Simulation time 94534486 ps
CPU time 0.77 seconds
Started Jun 29 06:26:41 PM PDT 24
Finished Jun 29 06:26:42 PM PDT 24
Peak memory 199896 kb
Host smart-4f2fcf1e-d300-48f1-a1cf-9b110aeefc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147410726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3147410726
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1533737494
Short name T134
Test name
Test status
Simulation time 786695477 ps
CPU time 3.96 seconds
Started Jun 29 06:26:45 PM PDT 24
Finished Jun 29 06:26:50 PM PDT 24
Peak memory 200356 kb
Host smart-6aa62fbe-50a5-4f23-9cf2-1fc1960f8434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533737494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1533737494
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.669135210
Short name T227
Test name
Test status
Simulation time 115527716 ps
CPU time 1.05 seconds
Started Jun 29 06:26:45 PM PDT 24
Finished Jun 29 06:26:47 PM PDT 24
Peak memory 200068 kb
Host smart-0e73b762-e90a-42d1-9b3d-6ae33d798c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669135210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.669135210
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2117903712
Short name T405
Test name
Test status
Simulation time 241780747 ps
CPU time 1.57 seconds
Started Jun 29 06:26:42 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 200276 kb
Host smart-5b1e47fc-75cc-45d4-9423-c2fef03dbc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117903712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2117903712
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4018028950
Short name T357
Test name
Test status
Simulation time 18184921711 ps
CPU time 62.74 seconds
Started Jun 29 06:26:43 PM PDT 24
Finished Jun 29 06:27:47 PM PDT 24
Peak memory 200316 kb
Host smart-fce0b28a-26c4-4211-b6c0-23dbb3f77231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018028950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4018028950
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.578556464
Short name T429
Test name
Test status
Simulation time 486998651 ps
CPU time 2.91 seconds
Started Jun 29 06:26:42 PM PDT 24
Finished Jun 29 06:26:45 PM PDT 24
Peak memory 200000 kb
Host smart-27e8863c-ae67-4477-9320-dbc86c99588d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578556464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.578556464
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.4275032639
Short name T192
Test name
Test status
Simulation time 128778925 ps
CPU time 1.13 seconds
Started Jun 29 06:26:41 PM PDT 24
Finished Jun 29 06:26:42 PM PDT 24
Peak memory 200052 kb
Host smart-6799a6c5-0fcb-4c67-aae5-32312ffa95db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275032639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.4275032639
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3253555737
Short name T317
Test name
Test status
Simulation time 58021441 ps
CPU time 0.69 seconds
Started Jun 29 06:26:53 PM PDT 24
Finished Jun 29 06:26:54 PM PDT 24
Peak memory 199868 kb
Host smart-c00502d4-4108-4c6c-9d5b-96c738bdb290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253555737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3253555737
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4151472456
Short name T30
Test name
Test status
Simulation time 1889005513 ps
CPU time 7.4 seconds
Started Jun 29 06:26:42 PM PDT 24
Finished Jun 29 06:26:50 PM PDT 24
Peak memory 221624 kb
Host smart-0785d3d6-e120-4d94-a5de-2185b2c40d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151472456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4151472456
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1062551857
Short name T122
Test name
Test status
Simulation time 243999725 ps
CPU time 1.2 seconds
Started Jun 29 06:26:51 PM PDT 24
Finished Jun 29 06:26:53 PM PDT 24
Peak memory 217452 kb
Host smart-86c92612-c996-4b14-a900-e4da928501bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062551857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1062551857
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4071361075
Short name T282
Test name
Test status
Simulation time 231914080 ps
CPU time 0.93 seconds
Started Jun 29 06:26:45 PM PDT 24
Finished Jun 29 06:26:46 PM PDT 24
Peak memory 199872 kb
Host smart-39980688-329f-45c6-800c-8c45743e553b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071361075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4071361075
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2235100802
Short name T86
Test name
Test status
Simulation time 719335517 ps
CPU time 3.88 seconds
Started Jun 29 06:26:44 PM PDT 24
Finished Jun 29 06:26:48 PM PDT 24
Peak memory 200344 kb
Host smart-29f1f66c-3d18-49ca-8fb9-101ec5f71af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235100802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2235100802
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2986376445
Short name T273
Test name
Test status
Simulation time 181196293 ps
CPU time 1.21 seconds
Started Jun 29 06:26:41 PM PDT 24
Finished Jun 29 06:26:43 PM PDT 24
Peak memory 200044 kb
Host smart-94886215-98ca-430b-9611-a662640506a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986376445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2986376445
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3160920272
Short name T220
Test name
Test status
Simulation time 253606470 ps
CPU time 1.51 seconds
Started Jun 29 06:26:43 PM PDT 24
Finished Jun 29 06:26:46 PM PDT 24
Peak memory 200280 kb
Host smart-05e94f3a-763e-4250-b06f-cdd0a0979789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160920272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3160920272
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2331834766
Short name T436
Test name
Test status
Simulation time 324408914 ps
CPU time 2.17 seconds
Started Jun 29 06:26:53 PM PDT 24
Finished Jun 29 06:26:56 PM PDT 24
Peak memory 208436 kb
Host smart-00115e17-7fbc-469e-ba83-72d73dea7987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331834766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2331834766
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1072569299
Short name T47
Test name
Test status
Simulation time 413541567 ps
CPU time 2.36 seconds
Started Jun 29 06:26:44 PM PDT 24
Finished Jun 29 06:26:47 PM PDT 24
Peak memory 200084 kb
Host smart-cf311e6f-d87b-4640-a677-a386fab9a946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072569299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1072569299
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3223884589
Short name T521
Test name
Test status
Simulation time 156827153 ps
CPU time 1.15 seconds
Started Jun 29 06:26:42 PM PDT 24
Finished Jun 29 06:26:44 PM PDT 24
Peak memory 200096 kb
Host smart-b9d17c1e-c39c-4fbf-af56-f956b93b098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223884589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3223884589
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2338511729
Short name T160
Test name
Test status
Simulation time 67155273 ps
CPU time 0.8 seconds
Started Jun 29 06:26:52 PM PDT 24
Finished Jun 29 06:26:53 PM PDT 24
Peak memory 199876 kb
Host smart-a55f3880-e100-4c1b-9d16-5a58483db183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338511729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2338511729
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4195186238
Short name T330
Test name
Test status
Simulation time 2169125330 ps
CPU time 8.77 seconds
Started Jun 29 06:26:52 PM PDT 24
Finished Jun 29 06:27:01 PM PDT 24
Peak memory 217804 kb
Host smart-2ed07ced-0c30-4ee9-b261-a48961c6fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195186238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4195186238
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2663435553
Short name T38
Test name
Test status
Simulation time 243664054 ps
CPU time 1.2 seconds
Started Jun 29 06:26:56 PM PDT 24
Finished Jun 29 06:26:58 PM PDT 24
Peak memory 217476 kb
Host smart-bc1c25cf-05b6-484c-9c7a-41c99a91fa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663435553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2663435553
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1829272185
Short name T361
Test name
Test status
Simulation time 119860862 ps
CPU time 0.82 seconds
Started Jun 29 06:26:55 PM PDT 24
Finished Jun 29 06:26:57 PM PDT 24
Peak memory 199900 kb
Host smart-3549c49b-5396-4540-b3a9-7528c632db65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829272185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1829272185
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1252949019
Short name T450
Test name
Test status
Simulation time 1846633569 ps
CPU time 7.44 seconds
Started Jun 29 06:26:52 PM PDT 24
Finished Jun 29 06:27:00 PM PDT 24
Peak memory 200340 kb
Host smart-098a030f-2567-43e3-9115-03366dc85fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252949019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1252949019
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3295811845
Short name T336
Test name
Test status
Simulation time 184206070 ps
CPU time 1.27 seconds
Started Jun 29 06:26:54 PM PDT 24
Finished Jun 29 06:26:56 PM PDT 24
Peak memory 200096 kb
Host smart-e8442a8e-851b-4387-b10d-3b32f84dd925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295811845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3295811845
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2487065713
Short name T400
Test name
Test status
Simulation time 251316562 ps
CPU time 1.65 seconds
Started Jun 29 06:26:55 PM PDT 24
Finished Jun 29 06:26:57 PM PDT 24
Peak memory 200280 kb
Host smart-0b548603-6580-40ee-bbcb-13b2b4d2d634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487065713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2487065713
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2852784952
Short name T538
Test name
Test status
Simulation time 8030921942 ps
CPU time 30.4 seconds
Started Jun 29 06:26:59 PM PDT 24
Finished Jun 29 06:27:30 PM PDT 24
Peak memory 209576 kb
Host smart-76e78a08-c989-450d-8384-12b2a01175a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852784952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2852784952
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1974277750
Short name T298
Test name
Test status
Simulation time 133704013 ps
CPU time 1.8 seconds
Started Jun 29 06:26:52 PM PDT 24
Finished Jun 29 06:26:55 PM PDT 24
Peak memory 200084 kb
Host smart-01678bdf-07b0-486a-a908-7051ac369fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974277750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1974277750
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1658250556
Short name T269
Test name
Test status
Simulation time 85290102 ps
CPU time 0.91 seconds
Started Jun 29 06:26:55 PM PDT 24
Finished Jun 29 06:26:57 PM PDT 24
Peak memory 200096 kb
Host smart-d87f7880-49f8-4d24-b324-de846458e1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658250556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1658250556
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2767017265
Short name T349
Test name
Test status
Simulation time 69573676 ps
CPU time 0.78 seconds
Started Jun 29 06:25:41 PM PDT 24
Finished Jun 29 06:25:42 PM PDT 24
Peak memory 199872 kb
Host smart-733f86bd-2c6e-4936-bba3-9a695878d05c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767017265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2767017265
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.640606020
Short name T334
Test name
Test status
Simulation time 1208697427 ps
CPU time 5.7 seconds
Started Jun 29 06:25:37 PM PDT 24
Finished Jun 29 06:25:43 PM PDT 24
Peak memory 217392 kb
Host smart-3f7b2e43-3eae-40be-84aa-b5d894119c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640606020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.640606020
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1355271278
Short name T510
Test name
Test status
Simulation time 244284566 ps
CPU time 1.16 seconds
Started Jun 29 06:25:37 PM PDT 24
Finished Jun 29 06:25:38 PM PDT 24
Peak memory 217452 kb
Host smart-bf98bbc3-11cf-4457-9e67-4647165ac5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355271278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1355271278
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1663870172
Short name T6
Test name
Test status
Simulation time 144606079 ps
CPU time 0.87 seconds
Started Jun 29 06:25:38 PM PDT 24
Finished Jun 29 06:25:39 PM PDT 24
Peak memory 199900 kb
Host smart-8549142a-952d-4e5d-9986-498e8a476482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663870172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1663870172
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3329374896
Short name T213
Test name
Test status
Simulation time 750537760 ps
CPU time 4.45 seconds
Started Jun 29 06:25:41 PM PDT 24
Finished Jun 29 06:25:46 PM PDT 24
Peak memory 200360 kb
Host smart-3bac7c86-703d-4d8e-b99a-d21dbebf4c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329374896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3329374896
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3810584054
Short name T7
Test name
Test status
Simulation time 16538371845 ps
CPU time 27.56 seconds
Started Jun 29 06:25:37 PM PDT 24
Finished Jun 29 06:26:05 PM PDT 24
Peak memory 217104 kb
Host smart-1a0d08a2-555e-4d0e-9ad4-401c04ac65fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810584054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3810584054
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1986554636
Short name T388
Test name
Test status
Simulation time 154666021 ps
CPU time 1.14 seconds
Started Jun 29 06:25:38 PM PDT 24
Finished Jun 29 06:25:40 PM PDT 24
Peak memory 200092 kb
Host smart-c4109331-8f36-4303-b173-48ffee03aed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986554636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1986554636
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3183383341
Short name T454
Test name
Test status
Simulation time 258287489 ps
CPU time 1.49 seconds
Started Jun 29 06:25:40 PM PDT 24
Finished Jun 29 06:25:41 PM PDT 24
Peak memory 200300 kb
Host smart-eba26d9f-29a1-41b3-a5bb-69688665b8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183383341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3183383341
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2385152564
Short name T70
Test name
Test status
Simulation time 4969246143 ps
CPU time 22.11 seconds
Started Jun 29 06:25:38 PM PDT 24
Finished Jun 29 06:26:01 PM PDT 24
Peak memory 208608 kb
Host smart-730157a8-064c-4b2f-88ad-4288f92b3b11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385152564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2385152564
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.4152361664
Short name T451
Test name
Test status
Simulation time 342572699 ps
CPU time 2.02 seconds
Started Jun 29 06:25:38 PM PDT 24
Finished Jun 29 06:25:40 PM PDT 24
Peak memory 200092 kb
Host smart-c51da0f1-8f83-4160-a972-05aa3c3a3861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152361664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.4152361664
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1886196396
Short name T135
Test name
Test status
Simulation time 200120254 ps
CPU time 1.33 seconds
Started Jun 29 06:25:38 PM PDT 24
Finished Jun 29 06:25:40 PM PDT 24
Peak memory 200040 kb
Host smart-76bd2d97-df6d-415e-b9eb-6529196aaf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886196396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1886196396
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2541442167
Short name T178
Test name
Test status
Simulation time 73606283 ps
CPU time 0.8 seconds
Started Jun 29 06:26:51 PM PDT 24
Finished Jun 29 06:26:53 PM PDT 24
Peak memory 199876 kb
Host smart-bf6c4af9-c856-458d-9c7b-a266703bfa2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541442167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2541442167
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.829147682
Short name T8
Test name
Test status
Simulation time 1225413012 ps
CPU time 5.68 seconds
Started Jun 29 06:26:53 PM PDT 24
Finished Jun 29 06:26:59 PM PDT 24
Peak memory 217652 kb
Host smart-fe3c1f37-add8-4271-bd0c-db67efa933ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829147682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.829147682
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3522268644
Short name T254
Test name
Test status
Simulation time 244441557 ps
CPU time 1.11 seconds
Started Jun 29 06:26:54 PM PDT 24
Finished Jun 29 06:26:55 PM PDT 24
Peak memory 217360 kb
Host smart-f031877d-6e87-47b5-91fd-f2ed8beb1666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522268644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3522268644
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.4040250701
Short name T507
Test name
Test status
Simulation time 117166313 ps
CPU time 0.81 seconds
Started Jun 29 06:26:53 PM PDT 24
Finished Jun 29 06:26:55 PM PDT 24
Peak memory 199912 kb
Host smart-7310f8b9-b5bc-4138-9ad4-0b861f42a47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040250701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.4040250701
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2839857827
Short name T25
Test name
Test status
Simulation time 1726585577 ps
CPU time 7.88 seconds
Started Jun 29 06:26:52 PM PDT 24
Finished Jun 29 06:27:01 PM PDT 24
Peak memory 200316 kb
Host smart-6675e3c7-52fb-4eef-aeab-7dc507ab1e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839857827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2839857827
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1263349953
Short name T501
Test name
Test status
Simulation time 146695631 ps
CPU time 1.13 seconds
Started Jun 29 06:26:51 PM PDT 24
Finished Jun 29 06:26:53 PM PDT 24
Peak memory 200016 kb
Host smart-2932a00c-216b-42b5-99de-dfbdeb75ad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263349953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1263349953
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2042472865
Short name T125
Test name
Test status
Simulation time 240079972 ps
CPU time 1.5 seconds
Started Jun 29 06:26:55 PM PDT 24
Finished Jun 29 06:26:57 PM PDT 24
Peak memory 200248 kb
Host smart-02775223-cee4-44ca-9595-c97f0cdb83f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042472865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2042472865
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3306944888
Short name T534
Test name
Test status
Simulation time 1178907573 ps
CPU time 5.99 seconds
Started Jun 29 06:26:52 PM PDT 24
Finished Jun 29 06:26:59 PM PDT 24
Peak memory 200388 kb
Host smart-ae3de196-26e0-46ea-99cd-b4946b50a898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306944888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3306944888
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2893814662
Short name T1
Test name
Test status
Simulation time 155316322 ps
CPU time 1.32 seconds
Started Jun 29 06:26:51 PM PDT 24
Finished Jun 29 06:26:53 PM PDT 24
Peak memory 200312 kb
Host smart-0ae51ee7-3d69-466e-8b16-75a193dbb48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893814662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2893814662
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.905482417
Short name T234
Test name
Test status
Simulation time 165246040 ps
CPU time 0.99 seconds
Started Jun 29 06:26:55 PM PDT 24
Finished Jun 29 06:26:57 PM PDT 24
Peak memory 199884 kb
Host smart-685ca033-794a-4dd4-9daa-2cd29b2aa8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905482417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.905482417
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2652789470
Short name T308
Test name
Test status
Simulation time 2352791312 ps
CPU time 8.46 seconds
Started Jun 29 06:26:50 PM PDT 24
Finished Jun 29 06:26:59 PM PDT 24
Peak memory 217944 kb
Host smart-d5271ac3-9937-4753-93e3-8d2704910764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652789470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2652789470
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.690498724
Short name T9
Test name
Test status
Simulation time 243782760 ps
CPU time 1.09 seconds
Started Jun 29 06:26:53 PM PDT 24
Finished Jun 29 06:26:55 PM PDT 24
Peak memory 217384 kb
Host smart-a24c5022-26f0-4812-9145-9bc74f919cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690498724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.690498724
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.991968369
Short name T168
Test name
Test status
Simulation time 206458510 ps
CPU time 1 seconds
Started Jun 29 06:26:55 PM PDT 24
Finished Jun 29 06:26:57 PM PDT 24
Peak memory 199904 kb
Host smart-6ab42c7f-5cf1-446f-a525-992c02e1f991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991968369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.991968369
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.479248379
Short name T81
Test name
Test status
Simulation time 1626170037 ps
CPU time 6.07 seconds
Started Jun 29 06:26:51 PM PDT 24
Finished Jun 29 06:26:58 PM PDT 24
Peak memory 200356 kb
Host smart-16daa493-e170-41ab-9bd7-2cfd12ae3c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479248379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.479248379
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2277076992
Short name T141
Test name
Test status
Simulation time 113575201 ps
CPU time 1.06 seconds
Started Jun 29 06:26:53 PM PDT 24
Finished Jun 29 06:26:55 PM PDT 24
Peak memory 200100 kb
Host smart-193ea8c0-dc0b-4fab-ad2b-8bdcb96bac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277076992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2277076992
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2819801520
Short name T291
Test name
Test status
Simulation time 204948526 ps
CPU time 1.56 seconds
Started Jun 29 06:26:59 PM PDT 24
Finished Jun 29 06:27:01 PM PDT 24
Peak memory 199576 kb
Host smart-d0e4608d-929d-42a9-a77e-502a3f65df02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819801520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2819801520
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.975598154
Short name T253
Test name
Test status
Simulation time 8886887999 ps
CPU time 35.17 seconds
Started Jun 29 06:26:58 PM PDT 24
Finished Jun 29 06:27:33 PM PDT 24
Peak memory 208580 kb
Host smart-94149824-7316-44d5-801b-223412b256e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975598154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.975598154
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3153205082
Short name T191
Test name
Test status
Simulation time 552943948 ps
CPU time 2.98 seconds
Started Jun 29 06:26:51 PM PDT 24
Finished Jun 29 06:26:55 PM PDT 24
Peak memory 200056 kb
Host smart-17696610-30c7-479f-ad5d-386780e47f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153205082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3153205082
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2259645193
Short name T209
Test name
Test status
Simulation time 283080103 ps
CPU time 1.67 seconds
Started Jun 29 06:26:52 PM PDT 24
Finished Jun 29 06:26:55 PM PDT 24
Peak memory 200300 kb
Host smart-309f744a-a9cb-49a4-9416-581e13e37a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259645193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2259645193
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.905191572
Short name T544
Test name
Test status
Simulation time 65904482 ps
CPU time 0.81 seconds
Started Jun 29 06:27:03 PM PDT 24
Finished Jun 29 06:27:04 PM PDT 24
Peak memory 199880 kb
Host smart-9acd7d9e-c23b-453b-87ca-8ce8c63c2aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905191572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.905191572
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2005530797
Short name T31
Test name
Test status
Simulation time 2359877572 ps
CPU time 8.45 seconds
Started Jun 29 06:26:57 PM PDT 24
Finished Jun 29 06:27:06 PM PDT 24
Peak memory 217892 kb
Host smart-35372552-697d-4630-a09e-344b8421d336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005530797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2005530797
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.259854041
Short name T499
Test name
Test status
Simulation time 244997291 ps
CPU time 1.18 seconds
Started Jun 29 06:27:04 PM PDT 24
Finished Jun 29 06:27:06 PM PDT 24
Peak memory 217420 kb
Host smart-1ab0da2c-fbd0-4d8e-8b7d-625e4df3710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259854041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.259854041
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2677911706
Short name T496
Test name
Test status
Simulation time 105075680 ps
CPU time 0.85 seconds
Started Jun 29 06:26:54 PM PDT 24
Finished Jun 29 06:26:55 PM PDT 24
Peak memory 199900 kb
Host smart-7f6b532a-be68-4f7d-8be2-313c8e6addfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677911706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2677911706
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3195109472
Short name T185
Test name
Test status
Simulation time 1030661396 ps
CPU time 5.13 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:06 PM PDT 24
Peak memory 200356 kb
Host smart-3f79aa87-db8d-4974-a7ed-5564acec0fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195109472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3195109472
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.16792167
Short name T319
Test name
Test status
Simulation time 151993962 ps
CPU time 1.21 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:03 PM PDT 24
Peak memory 200020 kb
Host smart-6007ce96-e3ed-4f4f-8a5b-5f50b93841f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16792167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.16792167
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1031448353
Short name T284
Test name
Test status
Simulation time 190152370 ps
CPU time 1.41 seconds
Started Jun 29 06:26:55 PM PDT 24
Finished Jun 29 06:26:57 PM PDT 24
Peak memory 200280 kb
Host smart-a4a84c8f-b07b-447e-a596-67b09c53ddd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031448353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1031448353
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.4190732037
Short name T481
Test name
Test status
Simulation time 10123276959 ps
CPU time 36.11 seconds
Started Jun 29 06:26:58 PM PDT 24
Finished Jun 29 06:27:34 PM PDT 24
Peak memory 208608 kb
Host smart-fd050e48-f7ce-4d73-8b99-a4fae3cd4089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190732037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4190732037
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3267156477
Short name T422
Test name
Test status
Simulation time 147859390 ps
CPU time 2.08 seconds
Started Jun 29 06:27:03 PM PDT 24
Finished Jun 29 06:27:06 PM PDT 24
Peak memory 200084 kb
Host smart-5540cfba-0401-4a0e-a469-2fafc2dffc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267156477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3267156477
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1743554560
Short name T13
Test name
Test status
Simulation time 107081124 ps
CPU time 0.93 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:02 PM PDT 24
Peak memory 200096 kb
Host smart-c2d41c04-b5f5-47cb-80f9-5a5cbd02cdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743554560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1743554560
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3902099409
Short name T393
Test name
Test status
Simulation time 54783964 ps
CPU time 0.74 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:02 PM PDT 24
Peak memory 199864 kb
Host smart-f408ab23-d887-4e4f-9ddb-fc8740693222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902099409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3902099409
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2974055306
Short name T33
Test name
Test status
Simulation time 1879662565 ps
CPU time 8.37 seconds
Started Jun 29 06:26:58 PM PDT 24
Finished Jun 29 06:27:08 PM PDT 24
Peak memory 221596 kb
Host smart-43739362-4956-4527-9803-ee0d6d7753a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974055306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2974055306
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.4134386436
Short name T152
Test name
Test status
Simulation time 244156391 ps
CPU time 1.08 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:02 PM PDT 24
Peak memory 217484 kb
Host smart-b8d42e3b-18ee-4327-9301-8535fc0a4b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134386436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.4134386436
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2917231553
Short name T262
Test name
Test status
Simulation time 163536239 ps
CPU time 0.96 seconds
Started Jun 29 06:26:59 PM PDT 24
Finished Jun 29 06:27:01 PM PDT 24
Peak memory 199900 kb
Host smart-df3e6c73-18ac-4aa9-acc6-41c69d693176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917231553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2917231553
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3450287488
Short name T478
Test name
Test status
Simulation time 760869031 ps
CPU time 4.35 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:05 PM PDT 24
Peak memory 200344 kb
Host smart-a872b984-d154-4be5-884b-9cb208d2fd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450287488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3450287488
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3204298639
Short name T216
Test name
Test status
Simulation time 147409022 ps
CPU time 1.22 seconds
Started Jun 29 06:27:04 PM PDT 24
Finished Jun 29 06:27:05 PM PDT 24
Peak memory 200088 kb
Host smart-b0ea7ab9-9c73-4f78-8dec-be1609a2c055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204298639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3204298639
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2944569443
Short name T218
Test name
Test status
Simulation time 198112582 ps
CPU time 1.47 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:02 PM PDT 24
Peak memory 200276 kb
Host smart-736150b4-7d7a-4d6e-8a8a-fb0a9c48b8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944569443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2944569443
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1411557129
Short name T504
Test name
Test status
Simulation time 4141931320 ps
CPU time 15.21 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:16 PM PDT 24
Peak memory 200412 kb
Host smart-8853a33e-1968-494a-9aca-c5a13c5dc842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411557129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1411557129
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3560257213
Short name T232
Test name
Test status
Simulation time 118415536 ps
CPU time 1.55 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:03 PM PDT 24
Peak memory 200028 kb
Host smart-4af81ed7-c23b-4e7e-b414-dc3858123f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560257213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3560257213
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3383067485
Short name T468
Test name
Test status
Simulation time 197243288 ps
CPU time 1.32 seconds
Started Jun 29 06:26:57 PM PDT 24
Finished Jun 29 06:26:59 PM PDT 24
Peak memory 200096 kb
Host smart-29e8ee41-99b7-4db2-9dbb-676bfc1cb97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383067485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3383067485
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3328326052
Short name T374
Test name
Test status
Simulation time 84647851 ps
CPU time 0.85 seconds
Started Jun 29 06:26:58 PM PDT 24
Finished Jun 29 06:26:59 PM PDT 24
Peak memory 199876 kb
Host smart-51302be6-86a6-4f89-8063-1854cdc5e038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328326052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3328326052
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1804598923
Short name T44
Test name
Test status
Simulation time 1903461524 ps
CPU time 7.28 seconds
Started Jun 29 06:27:02 PM PDT 24
Finished Jun 29 06:27:10 PM PDT 24
Peak memory 221688 kb
Host smart-51d744e4-daa9-4de4-ad3e-3a5289150040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804598923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1804598923
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.362285004
Short name T519
Test name
Test status
Simulation time 244498696 ps
CPU time 1.07 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:02 PM PDT 24
Peak memory 217428 kb
Host smart-34ad5461-8f14-4f5b-9c2c-e7908b6b1e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362285004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.362285004
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1352063956
Short name T16
Test name
Test status
Simulation time 179413858 ps
CPU time 0.94 seconds
Started Jun 29 06:26:59 PM PDT 24
Finished Jun 29 06:27:01 PM PDT 24
Peak memory 199900 kb
Host smart-196e695d-9263-451a-aa68-2e0b8042f91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352063956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1352063956
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3349088132
Short name T84
Test name
Test status
Simulation time 906043722 ps
CPU time 4.51 seconds
Started Jun 29 06:27:03 PM PDT 24
Finished Jun 29 06:27:08 PM PDT 24
Peak memory 200344 kb
Host smart-d4a0f1fb-60df-466b-963e-a512b7ad7c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349088132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3349088132
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2202785073
Short name T437
Test name
Test status
Simulation time 102648528 ps
CPU time 1.08 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:02 PM PDT 24
Peak memory 200064 kb
Host smart-9095d2b5-4c1c-47ad-b69a-d24d68037a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202785073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2202785073
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.611800267
Short name T150
Test name
Test status
Simulation time 198695869 ps
CPU time 1.45 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:03 PM PDT 24
Peak memory 200196 kb
Host smart-fd8eee00-cbd2-4913-967e-d82d3a3f40a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611800267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.611800267
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.777786168
Short name T88
Test name
Test status
Simulation time 4220432444 ps
CPU time 15.14 seconds
Started Jun 29 06:27:02 PM PDT 24
Finished Jun 29 06:27:17 PM PDT 24
Peak memory 208608 kb
Host smart-250a07dc-4f48-4beb-a71e-7908840fe71f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777786168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.777786168
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2886309287
Short name T52
Test name
Test status
Simulation time 137861978 ps
CPU time 1.85 seconds
Started Jun 29 06:27:10 PM PDT 24
Finished Jun 29 06:27:12 PM PDT 24
Peak memory 200292 kb
Host smart-68abe684-333f-40ae-8f80-39eed003e46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886309287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2886309287
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.898373369
Short name T230
Test name
Test status
Simulation time 97287686 ps
CPU time 0.92 seconds
Started Jun 29 06:27:03 PM PDT 24
Finished Jun 29 06:27:05 PM PDT 24
Peak memory 200064 kb
Host smart-c83ff785-59a7-4d81-818f-4581a4e2b2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898373369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.898373369
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.504890564
Short name T362
Test name
Test status
Simulation time 59913099 ps
CPU time 0.79 seconds
Started Jun 29 06:27:01 PM PDT 24
Finished Jun 29 06:27:02 PM PDT 24
Peak memory 199896 kb
Host smart-45fb7348-b14f-4d9f-b855-57f735a38696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504890564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.504890564
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1787325462
Short name T516
Test name
Test status
Simulation time 2364873093 ps
CPU time 9.09 seconds
Started Jun 29 06:26:59 PM PDT 24
Finished Jun 29 06:27:09 PM PDT 24
Peak memory 217668 kb
Host smart-318f60b4-3982-480f-b84b-309f2482ff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787325462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1787325462
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1722246434
Short name T385
Test name
Test status
Simulation time 245288355 ps
CPU time 1.12 seconds
Started Jun 29 06:27:01 PM PDT 24
Finished Jun 29 06:27:03 PM PDT 24
Peak memory 217452 kb
Host smart-7d067d87-e097-4fd9-9aef-c6bd68dad822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722246434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1722246434
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1494465486
Short name T202
Test name
Test status
Simulation time 152232609 ps
CPU time 0.84 seconds
Started Jun 29 06:26:58 PM PDT 24
Finished Jun 29 06:27:00 PM PDT 24
Peak memory 199912 kb
Host smart-dd3f5c9f-bc14-407b-8f79-70bbfc873a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494465486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1494465486
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3628032854
Short name T187
Test name
Test status
Simulation time 1267293212 ps
CPU time 4.89 seconds
Started Jun 29 06:27:06 PM PDT 24
Finished Jun 29 06:27:11 PM PDT 24
Peak memory 200308 kb
Host smart-be80fd12-cb75-4844-af35-1972acd4abd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628032854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3628032854
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1206625769
Short name T252
Test name
Test status
Simulation time 99244685 ps
CPU time 1.02 seconds
Started Jun 29 06:26:59 PM PDT 24
Finished Jun 29 06:27:01 PM PDT 24
Peak memory 200088 kb
Host smart-7dce7247-410f-4cd4-88de-0c3ea1273081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206625769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1206625769
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1559384872
Short name T530
Test name
Test status
Simulation time 115274064 ps
CPU time 1.18 seconds
Started Jun 29 06:27:03 PM PDT 24
Finished Jun 29 06:27:05 PM PDT 24
Peak memory 200280 kb
Host smart-37c15487-736b-43a8-98e0-5937299cd659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559384872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1559384872
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3380799959
Short name T404
Test name
Test status
Simulation time 9774691522 ps
CPU time 36.39 seconds
Started Jun 29 06:27:03 PM PDT 24
Finished Jun 29 06:27:40 PM PDT 24
Peak memory 210340 kb
Host smart-08f62207-c932-41ab-a4aa-744dabf7ab21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380799959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3380799959
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3767683064
Short name T161
Test name
Test status
Simulation time 109039485 ps
CPU time 1.53 seconds
Started Jun 29 06:27:06 PM PDT 24
Finished Jun 29 06:27:08 PM PDT 24
Peak memory 200044 kb
Host smart-46716a27-6f28-4ba4-bb4a-6332227960ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767683064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3767683064
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1779690426
Short name T246
Test name
Test status
Simulation time 138736078 ps
CPU time 1.11 seconds
Started Jun 29 06:26:59 PM PDT 24
Finished Jun 29 06:27:01 PM PDT 24
Peak memory 200008 kb
Host smart-0b1389eb-f250-438b-975c-26ff201e00b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779690426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1779690426
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.194334811
Short name T151
Test name
Test status
Simulation time 69689838 ps
CPU time 0.88 seconds
Started Jun 29 06:26:58 PM PDT 24
Finished Jun 29 06:27:00 PM PDT 24
Peak memory 199884 kb
Host smart-2ae19254-40e1-4322-a1eb-cdbbfa17dc84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194334811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.194334811
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4162401935
Short name T542
Test name
Test status
Simulation time 1214030519 ps
CPU time 5.59 seconds
Started Jun 29 06:27:03 PM PDT 24
Finished Jun 29 06:27:10 PM PDT 24
Peak memory 217472 kb
Host smart-984e6de2-def8-4659-9246-d800beaa3c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162401935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4162401935
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3976745252
Short name T292
Test name
Test status
Simulation time 245124693 ps
CPU time 1.12 seconds
Started Jun 29 06:27:04 PM PDT 24
Finished Jun 29 06:27:06 PM PDT 24
Peak memory 216864 kb
Host smart-9cec9800-24c5-48be-a853-d4366a83ca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976745252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3976745252
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.4289165053
Short name T439
Test name
Test status
Simulation time 154618601 ps
CPU time 0.91 seconds
Started Jun 29 06:27:04 PM PDT 24
Finished Jun 29 06:27:05 PM PDT 24
Peak memory 199900 kb
Host smart-06ef8ad4-55aa-404b-b91d-f7721753e631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289165053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.4289165053
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3084686310
Short name T452
Test name
Test status
Simulation time 2051496036 ps
CPU time 8.13 seconds
Started Jun 29 06:27:04 PM PDT 24
Finished Jun 29 06:27:13 PM PDT 24
Peak memory 199524 kb
Host smart-df3718f5-ab38-4bfc-9163-163c5de67f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084686310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3084686310
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.942829122
Short name T363
Test name
Test status
Simulation time 143693156 ps
CPU time 1.15 seconds
Started Jun 29 06:27:02 PM PDT 24
Finished Jun 29 06:27:04 PM PDT 24
Peak memory 199984 kb
Host smart-546d0aae-6844-4734-b8a9-835441315f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942829122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.942829122
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.123734051
Short name T136
Test name
Test status
Simulation time 111998493 ps
CPU time 1.2 seconds
Started Jun 29 06:26:59 PM PDT 24
Finished Jun 29 06:27:01 PM PDT 24
Peak memory 200292 kb
Host smart-dc73ad45-4228-4cee-8d5b-6ade1673ea5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123734051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.123734051
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1293457904
Short name T293
Test name
Test status
Simulation time 1750120360 ps
CPU time 7.94 seconds
Started Jun 29 06:26:59 PM PDT 24
Finished Jun 29 06:27:08 PM PDT 24
Peak memory 200252 kb
Host smart-091ea635-2ec0-4fcb-aca6-e5831c0cbc2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293457904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1293457904
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.251134885
Short name T72
Test name
Test status
Simulation time 120827675 ps
CPU time 1.64 seconds
Started Jun 29 06:26:59 PM PDT 24
Finished Jun 29 06:27:01 PM PDT 24
Peak memory 200088 kb
Host smart-c9685883-8d39-42fc-b2d9-7e3a3313631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251134885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.251134885
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.4031560783
Short name T157
Test name
Test status
Simulation time 163985010 ps
CPU time 1.16 seconds
Started Jun 29 06:27:01 PM PDT 24
Finished Jun 29 06:27:03 PM PDT 24
Peak memory 200096 kb
Host smart-5fbc1f1f-ef3b-4e97-9b65-2b428150a41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031560783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4031560783
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2910358433
Short name T143
Test name
Test status
Simulation time 86407828 ps
CPU time 0.82 seconds
Started Jun 29 06:27:09 PM PDT 24
Finished Jun 29 06:27:11 PM PDT 24
Peak memory 200084 kb
Host smart-f41eaff3-dc5b-439f-ab77-4b0f6630452e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910358433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2910358433
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1690126977
Short name T32
Test name
Test status
Simulation time 1226878120 ps
CPU time 5.75 seconds
Started Jun 29 06:27:05 PM PDT 24
Finished Jun 29 06:27:11 PM PDT 24
Peak memory 217644 kb
Host smart-31c4c569-5f69-41df-bd22-0afdcf2b501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690126977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1690126977
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.955585854
Short name T434
Test name
Test status
Simulation time 245692030 ps
CPU time 1.12 seconds
Started Jun 29 06:27:10 PM PDT 24
Finished Jun 29 06:27:12 PM PDT 24
Peak memory 217644 kb
Host smart-5bdf9a4f-86b9-4c33-8db3-ec64ff2266ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955585854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.955585854
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3413914050
Short name T402
Test name
Test status
Simulation time 219526750 ps
CPU time 0.97 seconds
Started Jun 29 06:27:02 PM PDT 24
Finished Jun 29 06:27:04 PM PDT 24
Peak memory 199824 kb
Host smart-36804698-efc0-4b41-b1a7-86aab35bac24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413914050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3413914050
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.623367484
Short name T228
Test name
Test status
Simulation time 1455412046 ps
CPU time 6.57 seconds
Started Jun 29 06:27:01 PM PDT 24
Finished Jun 29 06:27:08 PM PDT 24
Peak memory 200344 kb
Host smart-0a67c5e2-63e1-4370-976a-ce10bf6fe301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623367484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.623367484
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.289551807
Short name T174
Test name
Test status
Simulation time 151650465 ps
CPU time 1.14 seconds
Started Jun 29 06:27:09 PM PDT 24
Finished Jun 29 06:27:11 PM PDT 24
Peak memory 200292 kb
Host smart-e38e85b4-f4b7-4dbf-8ebb-1e01d38a0884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289551807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.289551807
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.399248412
Short name T244
Test name
Test status
Simulation time 121411532 ps
CPU time 1.23 seconds
Started Jun 29 06:27:03 PM PDT 24
Finished Jun 29 06:27:05 PM PDT 24
Peak memory 200288 kb
Host smart-3119b4d1-d75c-44e9-b75e-cce28b322be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399248412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.399248412
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.910100466
Short name T221
Test name
Test status
Simulation time 3871857456 ps
CPU time 18.56 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:20 PM PDT 24
Peak memory 200356 kb
Host smart-fbba866b-3dfe-4bce-93f0-d08a934b092f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910100466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.910100466
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.4150079346
Short name T513
Test name
Test status
Simulation time 340738170 ps
CPU time 2.35 seconds
Started Jun 29 06:27:01 PM PDT 24
Finished Jun 29 06:27:04 PM PDT 24
Peak memory 200084 kb
Host smart-c990c9fb-79d2-41e1-8ae4-901e6c85643c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150079346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.4150079346
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2301002679
Short name T415
Test name
Test status
Simulation time 91075820 ps
CPU time 0.95 seconds
Started Jun 29 06:27:02 PM PDT 24
Finished Jun 29 06:27:04 PM PDT 24
Peak memory 200096 kb
Host smart-b1090091-e06e-4287-a557-cf867ab7e4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301002679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2301002679
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3472290315
Short name T539
Test name
Test status
Simulation time 68855930 ps
CPU time 0.82 seconds
Started Jun 29 06:27:05 PM PDT 24
Finished Jun 29 06:27:06 PM PDT 24
Peak memory 199876 kb
Host smart-61b903ac-3747-49b3-8de6-7af8a6539a4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472290315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3472290315
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3226809866
Short name T526
Test name
Test status
Simulation time 2346424004 ps
CPU time 7.99 seconds
Started Jun 29 06:27:07 PM PDT 24
Finished Jun 29 06:27:16 PM PDT 24
Peak memory 221684 kb
Host smart-fbac3821-e046-438e-a4fe-455c0e03dd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226809866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3226809866
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3498853543
Short name T350
Test name
Test status
Simulation time 245203639 ps
CPU time 1.1 seconds
Started Jun 29 06:27:07 PM PDT 24
Finished Jun 29 06:27:08 PM PDT 24
Peak memory 217444 kb
Host smart-198dacd1-fa5d-4421-9f06-692fb8864eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498853543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3498853543
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2962835922
Short name T223
Test name
Test status
Simulation time 115068240 ps
CPU time 0.81 seconds
Started Jun 29 06:27:10 PM PDT 24
Finished Jun 29 06:27:12 PM PDT 24
Peak memory 200092 kb
Host smart-59824ab9-0d45-4e66-aaf6-21eb2b93c0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962835922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2962835922
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.4191189887
Short name T208
Test name
Test status
Simulation time 1124533578 ps
CPU time 5.72 seconds
Started Jun 29 06:27:00 PM PDT 24
Finished Jun 29 06:27:07 PM PDT 24
Peak memory 200340 kb
Host smart-fb9aec8a-0862-4c92-95b6-c38cb26050bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191189887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4191189887
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1881881312
Short name T242
Test name
Test status
Simulation time 136867942 ps
CPU time 1.1 seconds
Started Jun 29 06:27:08 PM PDT 24
Finished Jun 29 06:27:09 PM PDT 24
Peak memory 200088 kb
Host smart-f843f6cc-ea51-445d-b3dc-58837d8cf322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881881312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1881881312
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1570644906
Short name T387
Test name
Test status
Simulation time 219580953 ps
CPU time 1.49 seconds
Started Jun 29 06:27:10 PM PDT 24
Finished Jun 29 06:27:12 PM PDT 24
Peak memory 200488 kb
Host smart-69d4ade7-003a-40cc-a6f2-34d8405424b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570644906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1570644906
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.672694004
Short name T465
Test name
Test status
Simulation time 5433904397 ps
CPU time 20.44 seconds
Started Jun 29 06:27:09 PM PDT 24
Finished Jun 29 06:27:31 PM PDT 24
Peak memory 208604 kb
Host smart-51e56d65-dd9c-419c-a2f5-668da70bc6d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672694004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.672694004
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.444792766
Short name T406
Test name
Test status
Simulation time 138743914 ps
CPU time 1.9 seconds
Started Jun 29 06:27:01 PM PDT 24
Finished Jun 29 06:27:04 PM PDT 24
Peak memory 200088 kb
Host smart-86219966-5673-4b45-9de3-ba980bd4a54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444792766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.444792766
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2853353222
Short name T2
Test name
Test status
Simulation time 112744644 ps
CPU time 1.08 seconds
Started Jun 29 06:27:01 PM PDT 24
Finished Jun 29 06:27:03 PM PDT 24
Peak memory 200096 kb
Host smart-ed64c348-12e9-475b-9774-5a29852e88d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853353222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2853353222
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3318570877
Short name T367
Test name
Test status
Simulation time 60824044 ps
CPU time 0.76 seconds
Started Jun 29 06:27:07 PM PDT 24
Finished Jun 29 06:27:08 PM PDT 24
Peak memory 199844 kb
Host smart-e914dcff-9418-4b19-9944-d49d940ff1fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318570877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3318570877
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1982313432
Short name T219
Test name
Test status
Simulation time 1899962422 ps
CPU time 8.01 seconds
Started Jun 29 06:27:06 PM PDT 24
Finished Jun 29 06:27:14 PM PDT 24
Peak memory 221648 kb
Host smart-cc8a7b28-ae58-4b3c-9fdc-6e254e39c519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982313432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1982313432
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3350811126
Short name T166
Test name
Test status
Simulation time 250361158 ps
CPU time 1.07 seconds
Started Jun 29 06:27:10 PM PDT 24
Finished Jun 29 06:27:12 PM PDT 24
Peak memory 218236 kb
Host smart-73d47031-ca68-4301-9915-7dd08c34217a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350811126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3350811126
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1730637310
Short name T17
Test name
Test status
Simulation time 122158679 ps
CPU time 0.8 seconds
Started Jun 29 06:27:05 PM PDT 24
Finished Jun 29 06:27:06 PM PDT 24
Peak memory 199904 kb
Host smart-3bbde8da-53bb-4594-b0b7-0915b7605f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730637310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1730637310
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3478783319
Short name T237
Test name
Test status
Simulation time 1655048130 ps
CPU time 6.45 seconds
Started Jun 29 06:27:06 PM PDT 24
Finished Jun 29 06:27:13 PM PDT 24
Peak memory 200388 kb
Host smart-5a427889-c63a-4751-8dee-78c9917a6c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478783319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3478783319
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2685960214
Short name T464
Test name
Test status
Simulation time 155538349 ps
CPU time 1.26 seconds
Started Jun 29 06:27:09 PM PDT 24
Finished Jun 29 06:27:11 PM PDT 24
Peak memory 200056 kb
Host smart-b9b0a084-c606-4c86-bb5b-dddd006f96fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685960214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2685960214
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2854616374
Short name T158
Test name
Test status
Simulation time 123238345 ps
CPU time 1.28 seconds
Started Jun 29 06:27:09 PM PDT 24
Finished Jun 29 06:27:12 PM PDT 24
Peak memory 200280 kb
Host smart-90f27d59-0be7-4dcd-9383-622891910bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854616374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2854616374
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3756135529
Short name T329
Test name
Test status
Simulation time 251407830 ps
CPU time 1.55 seconds
Started Jun 29 06:27:08 PM PDT 24
Finished Jun 29 06:27:10 PM PDT 24
Peak memory 199996 kb
Host smart-cfb7a80d-0ce3-4037-a836-b3b86505d0c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756135529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3756135529
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.4156439872
Short name T342
Test name
Test status
Simulation time 142147584 ps
CPU time 1.71 seconds
Started Jun 29 06:27:06 PM PDT 24
Finished Jun 29 06:27:08 PM PDT 24
Peak memory 200056 kb
Host smart-e4c0ea08-bf33-4e86-9b86-b196a3e48907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156439872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.4156439872
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1458713678
Short name T337
Test name
Test status
Simulation time 86149295 ps
CPU time 0.85 seconds
Started Jun 29 06:27:10 PM PDT 24
Finished Jun 29 06:27:12 PM PDT 24
Peak memory 200036 kb
Host smart-87157561-a2e1-4224-a28c-e51581c7f968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458713678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1458713678
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3575200887
Short name T233
Test name
Test status
Simulation time 72235795 ps
CPU time 0.82 seconds
Started Jun 29 06:25:41 PM PDT 24
Finished Jun 29 06:25:42 PM PDT 24
Peak memory 199876 kb
Host smart-96259efd-b350-4c14-b2e6-86358d79b9f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575200887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3575200887
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3357802507
Short name T515
Test name
Test status
Simulation time 2180925721 ps
CPU time 7.99 seconds
Started Jun 29 06:25:37 PM PDT 24
Finished Jun 29 06:25:46 PM PDT 24
Peak memory 221480 kb
Host smart-fc4a12bd-a93a-4bb5-8ef8-cb44d412d4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357802507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3357802507
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1717170720
Short name T68
Test name
Test status
Simulation time 243874688 ps
CPU time 1.08 seconds
Started Jun 29 06:25:41 PM PDT 24
Finished Jun 29 06:25:42 PM PDT 24
Peak memory 217376 kb
Host smart-dc35d8f3-6107-4734-a09f-711b75136d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717170720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1717170720
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1339317007
Short name T331
Test name
Test status
Simulation time 182075103 ps
CPU time 0.89 seconds
Started Jun 29 06:25:37 PM PDT 24
Finished Jun 29 06:25:38 PM PDT 24
Peak memory 199888 kb
Host smart-1b574d95-61d2-4e6a-9425-7c5ec2a0aad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339317007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1339317007
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1217945749
Short name T348
Test name
Test status
Simulation time 2039291062 ps
CPU time 7.67 seconds
Started Jun 29 06:25:37 PM PDT 24
Finished Jun 29 06:25:45 PM PDT 24
Peak memory 200320 kb
Host smart-0814f316-08f4-4911-92d6-712de4231e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217945749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1217945749
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3312210818
Short name T466
Test name
Test status
Simulation time 153244876 ps
CPU time 1.23 seconds
Started Jun 29 06:25:38 PM PDT 24
Finished Jun 29 06:25:40 PM PDT 24
Peak memory 200008 kb
Host smart-a30f3c3a-68fc-4f0b-a015-0a024b02df42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312210818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3312210818
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.713799006
Short name T169
Test name
Test status
Simulation time 197696548 ps
CPU time 1.42 seconds
Started Jun 29 06:25:39 PM PDT 24
Finished Jun 29 06:25:41 PM PDT 24
Peak memory 200228 kb
Host smart-b306fb7e-4f35-420a-80af-e4983664d3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713799006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.713799006
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1760943729
Short name T546
Test name
Test status
Simulation time 3754928765 ps
CPU time 14.98 seconds
Started Jun 29 06:25:40 PM PDT 24
Finished Jun 29 06:25:55 PM PDT 24
Peak memory 200356 kb
Host smart-259638a7-7935-41d0-ab91-829f65df9979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760943729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1760943729
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1819997791
Short name T527
Test name
Test status
Simulation time 384250756 ps
CPU time 2.73 seconds
Started Jun 29 06:25:40 PM PDT 24
Finished Jun 29 06:25:43 PM PDT 24
Peak memory 200088 kb
Host smart-346d8d8b-0986-4de7-aa6f-62ab4c2cd0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819997791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1819997791
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3485752848
Short name T205
Test name
Test status
Simulation time 82787034 ps
CPU time 0.82 seconds
Started Jun 29 06:25:46 PM PDT 24
Finished Jun 29 06:25:47 PM PDT 24
Peak memory 200096 kb
Host smart-5dc33589-2962-4749-8aae-af5962af3fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485752848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3485752848
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.117913315
Short name T198
Test name
Test status
Simulation time 58983378 ps
CPU time 0.77 seconds
Started Jun 29 06:25:45 PM PDT 24
Finished Jun 29 06:25:47 PM PDT 24
Peak memory 199884 kb
Host smart-dc61480b-037d-4e1c-8be4-03c62660ea8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117913315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.117913315
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1175044360
Short name T494
Test name
Test status
Simulation time 1893833604 ps
CPU time 7.57 seconds
Started Jun 29 06:25:47 PM PDT 24
Finished Jun 29 06:25:55 PM PDT 24
Peak memory 217712 kb
Host smart-0746ff13-f4f2-46ef-b31d-fe791aa660d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175044360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1175044360
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3187381324
Short name T124
Test name
Test status
Simulation time 244415318 ps
CPU time 1.1 seconds
Started Jun 29 06:25:44 PM PDT 24
Finished Jun 29 06:25:46 PM PDT 24
Peak memory 217476 kb
Host smart-2aff225e-7d55-4167-a0b5-29c92fa434a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187381324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3187381324
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2906844109
Short name T390
Test name
Test status
Simulation time 158695838 ps
CPU time 0.82 seconds
Started Jun 29 06:25:48 PM PDT 24
Finished Jun 29 06:25:49 PM PDT 24
Peak memory 199900 kb
Host smart-a47f03d5-c89d-4617-ba21-a279281ec5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906844109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2906844109
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.4264379670
Short name T423
Test name
Test status
Simulation time 1316500469 ps
CPU time 5.2 seconds
Started Jun 29 06:25:43 PM PDT 24
Finished Jun 29 06:25:49 PM PDT 24
Peak memory 200272 kb
Host smart-b2d702bc-d5c8-4f96-b3c8-3e8fd80ff0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264379670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4264379670
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3783296244
Short name T272
Test name
Test status
Simulation time 109900798 ps
CPU time 1 seconds
Started Jun 29 06:25:45 PM PDT 24
Finished Jun 29 06:25:46 PM PDT 24
Peak memory 200072 kb
Host smart-7c56b544-b98d-4f45-9c05-6895b068ab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783296244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3783296244
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2825619653
Short name T170
Test name
Test status
Simulation time 110114695 ps
CPU time 1.14 seconds
Started Jun 29 06:25:43 PM PDT 24
Finished Jun 29 06:25:44 PM PDT 24
Peak memory 200296 kb
Host smart-25763b9e-694c-4595-9ea8-a29c52242279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825619653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2825619653
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3307936746
Short name T490
Test name
Test status
Simulation time 973407109 ps
CPU time 4.71 seconds
Started Jun 29 06:25:43 PM PDT 24
Finished Jun 29 06:25:49 PM PDT 24
Peak memory 200256 kb
Host smart-55e53dac-a818-45a5-b823-0ddf9734107f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307936746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3307936746
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.834697253
Short name T149
Test name
Test status
Simulation time 149952701 ps
CPU time 1.94 seconds
Started Jun 29 06:25:44 PM PDT 24
Finished Jun 29 06:25:47 PM PDT 24
Peak memory 200088 kb
Host smart-1bbe9271-2739-4881-b657-7575f20479a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834697253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.834697253
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1682779998
Short name T508
Test name
Test status
Simulation time 92147879 ps
CPU time 0.96 seconds
Started Jun 29 06:25:42 PM PDT 24
Finished Jun 29 06:25:44 PM PDT 24
Peak memory 200096 kb
Host smart-b6663bdb-ed57-47f7-9792-0c471b84ae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682779998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1682779998
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1298909477
Short name T224
Test name
Test status
Simulation time 61484110 ps
CPU time 0.72 seconds
Started Jun 29 06:25:45 PM PDT 24
Finished Jun 29 06:25:47 PM PDT 24
Peak memory 199820 kb
Host smart-5d7e8a52-c623-4049-b912-5cbe7e231f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298909477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1298909477
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3491914361
Short name T281
Test name
Test status
Simulation time 245494241 ps
CPU time 1.09 seconds
Started Jun 29 06:25:44 PM PDT 24
Finished Jun 29 06:25:46 PM PDT 24
Peak memory 217452 kb
Host smart-5a3e194f-cc8b-4a33-820f-96886742856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491914361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3491914361
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2864682283
Short name T240
Test name
Test status
Simulation time 188860650 ps
CPU time 0.92 seconds
Started Jun 29 06:25:44 PM PDT 24
Finished Jun 29 06:25:46 PM PDT 24
Peak memory 199900 kb
Host smart-3f63609a-57aa-4e79-9fb0-f3c75c7e48a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864682283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2864682283
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.148219789
Short name T383
Test name
Test status
Simulation time 2038755770 ps
CPU time 8.95 seconds
Started Jun 29 06:25:43 PM PDT 24
Finished Jun 29 06:25:53 PM PDT 24
Peak memory 200332 kb
Host smart-5fba8a08-29e6-4371-b225-b14485e6010d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148219789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.148219789
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3920092892
Short name T131
Test name
Test status
Simulation time 182024593 ps
CPU time 1.4 seconds
Started Jun 29 06:25:46 PM PDT 24
Finished Jun 29 06:25:49 PM PDT 24
Peak memory 200092 kb
Host smart-c172eff3-a6f2-41b0-808c-fd4343312517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920092892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3920092892
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4294236288
Short name T430
Test name
Test status
Simulation time 188916716 ps
CPU time 1.59 seconds
Started Jun 29 06:25:44 PM PDT 24
Finished Jun 29 06:25:46 PM PDT 24
Peak memory 200300 kb
Host smart-ad154152-9eaa-41e8-aacc-9be00d0b6342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294236288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4294236288
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3179330496
Short name T40
Test name
Test status
Simulation time 7931600759 ps
CPU time 29.15 seconds
Started Jun 29 06:25:46 PM PDT 24
Finished Jun 29 06:26:16 PM PDT 24
Peak memory 215772 kb
Host smart-0cad73cc-b66a-429d-acaf-7db1b107404a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179330496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3179330496
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1169847015
Short name T55
Test name
Test status
Simulation time 148661586 ps
CPU time 2.05 seconds
Started Jun 29 06:25:45 PM PDT 24
Finished Jun 29 06:25:48 PM PDT 24
Peak memory 199920 kb
Host smart-c5a46ce5-10ac-4af7-b2d4-cc6945ef6b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169847015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1169847015
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3012683165
Short name T379
Test name
Test status
Simulation time 142875096 ps
CPU time 1.07 seconds
Started Jun 29 06:25:43 PM PDT 24
Finished Jun 29 06:25:45 PM PDT 24
Peak memory 200096 kb
Host smart-d37e01ac-e02f-499e-800e-c76bb7b98cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012683165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3012683165
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2575602411
Short name T285
Test name
Test status
Simulation time 65483612 ps
CPU time 0.8 seconds
Started Jun 29 06:25:43 PM PDT 24
Finished Jun 29 06:25:44 PM PDT 24
Peak memory 199824 kb
Host smart-193ee399-25a3-42a9-b473-49a979dea9d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575602411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2575602411
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1034513277
Short name T249
Test name
Test status
Simulation time 2169460105 ps
CPU time 8.9 seconds
Started Jun 29 06:25:45 PM PDT 24
Finished Jun 29 06:25:55 PM PDT 24
Peak memory 221524 kb
Host smart-70298126-8779-45b6-a1e6-42439db5b120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034513277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1034513277
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1029759378
Short name T267
Test name
Test status
Simulation time 243953997 ps
CPU time 1.19 seconds
Started Jun 29 06:25:45 PM PDT 24
Finished Jun 29 06:25:46 PM PDT 24
Peak memory 217456 kb
Host smart-d81c494e-b1d0-4df6-857a-f5592e1f4b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029759378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1029759378
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3450654460
Short name T257
Test name
Test status
Simulation time 125456412 ps
CPU time 0.8 seconds
Started Jun 29 06:25:43 PM PDT 24
Finished Jun 29 06:25:44 PM PDT 24
Peak memory 199816 kb
Host smart-682fd024-c727-4de4-a508-40b7d68344b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450654460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3450654460
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3350323389
Short name T83
Test name
Test status
Simulation time 1305463944 ps
CPU time 5.67 seconds
Started Jun 29 06:25:46 PM PDT 24
Finished Jun 29 06:25:52 PM PDT 24
Peak memory 199384 kb
Host smart-1f585e6e-628b-4dac-9c61-49768e90508b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350323389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3350323389
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2124252212
Short name T345
Test name
Test status
Simulation time 116521753 ps
CPU time 1.04 seconds
Started Jun 29 06:25:49 PM PDT 24
Finished Jun 29 06:25:51 PM PDT 24
Peak memory 200288 kb
Host smart-988efefc-fae2-4aa9-8dd3-2d1f7b50608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124252212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2124252212
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1515104451
Short name T251
Test name
Test status
Simulation time 111697582 ps
CPU time 1.19 seconds
Started Jun 29 06:25:46 PM PDT 24
Finished Jun 29 06:25:48 PM PDT 24
Peak memory 200300 kb
Host smart-64428b83-f2aa-4bf3-8d20-40fa1fa40cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515104451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1515104451
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.566643943
Short name T304
Test name
Test status
Simulation time 6173754589 ps
CPU time 24.37 seconds
Started Jun 29 06:25:47 PM PDT 24
Finished Jun 29 06:26:12 PM PDT 24
Peak memory 200408 kb
Host smart-7fd78e31-9b99-4de0-bb45-b23efceed54c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566643943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.566643943
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2443228449
Short name T261
Test name
Test status
Simulation time 499206936 ps
CPU time 3.34 seconds
Started Jun 29 06:25:46 PM PDT 24
Finished Jun 29 06:25:50 PM PDT 24
Peak memory 200132 kb
Host smart-b4160fdb-de6d-421f-a22a-3ed321ae8de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443228449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2443228449
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.879033023
Short name T470
Test name
Test status
Simulation time 99280887 ps
CPU time 0.9 seconds
Started Jun 29 06:25:50 PM PDT 24
Finished Jun 29 06:25:51 PM PDT 24
Peak memory 200288 kb
Host smart-fbade975-cd5f-4909-87b0-7af761f730ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879033023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.879033023
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2950440427
Short name T368
Test name
Test status
Simulation time 67031797 ps
CPU time 0.79 seconds
Started Jun 29 06:25:55 PM PDT 24
Finished Jun 29 06:25:56 PM PDT 24
Peak memory 199876 kb
Host smart-205b0c63-4b90-4f00-8026-a7b09487ccdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950440427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2950440427
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4118538597
Short name T457
Test name
Test status
Simulation time 1223536628 ps
CPU time 5.58 seconds
Started Jun 29 06:25:52 PM PDT 24
Finished Jun 29 06:25:58 PM PDT 24
Peak memory 217732 kb
Host smart-8cb51b2d-f9ea-4f82-8c79-f6c06bb85e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118538597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4118538597
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.371562314
Short name T433
Test name
Test status
Simulation time 244527747 ps
CPU time 1.15 seconds
Started Jun 29 06:25:55 PM PDT 24
Finished Jun 29 06:25:57 PM PDT 24
Peak memory 217464 kb
Host smart-725bf364-4566-41a6-9a30-d8015cc7bb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371562314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.371562314
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3322162128
Short name T506
Test name
Test status
Simulation time 73443582 ps
CPU time 0.82 seconds
Started Jun 29 06:25:44 PM PDT 24
Finished Jun 29 06:25:45 PM PDT 24
Peak memory 199900 kb
Host smart-ef7b8a0e-5114-4777-b681-232e60c6a12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322162128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3322162128
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3515697268
Short name T511
Test name
Test status
Simulation time 2012416259 ps
CPU time 8.34 seconds
Started Jun 29 06:25:45 PM PDT 24
Finished Jun 29 06:25:54 PM PDT 24
Peak memory 200344 kb
Host smart-b65b255f-cc30-4738-80a2-5f26331aa96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515697268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3515697268
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.691762733
Short name T159
Test name
Test status
Simulation time 152416064 ps
CPU time 1.17 seconds
Started Jun 29 06:25:43 PM PDT 24
Finished Jun 29 06:25:45 PM PDT 24
Peak memory 200096 kb
Host smart-02ac1fce-5582-4495-955e-c57be9319b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691762733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.691762733
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3050406138
Short name T163
Test name
Test status
Simulation time 240367422 ps
CPU time 1.51 seconds
Started Jun 29 06:25:45 PM PDT 24
Finished Jun 29 06:25:47 PM PDT 24
Peak memory 200276 kb
Host smart-2e5f76c6-580e-43aa-b5c0-375980920385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050406138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3050406138
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3341388052
Short name T222
Test name
Test status
Simulation time 5996207184 ps
CPU time 25.02 seconds
Started Jun 29 06:25:51 PM PDT 24
Finished Jun 29 06:26:16 PM PDT 24
Peak memory 200452 kb
Host smart-b523a89e-abdc-425f-9668-ef7145de235b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341388052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3341388052
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.380184700
Short name T495
Test name
Test status
Simulation time 359777092 ps
CPU time 2.26 seconds
Started Jun 29 06:25:46 PM PDT 24
Finished Jun 29 06:25:49 PM PDT 24
Peak memory 208352 kb
Host smart-c0e3d6bb-4f25-4007-b428-d9dcd7031aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380184700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.380184700
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.207064081
Short name T303
Test name
Test status
Simulation time 148196259 ps
CPU time 1.11 seconds
Started Jun 29 06:25:50 PM PDT 24
Finished Jun 29 06:25:52 PM PDT 24
Peak memory 200288 kb
Host smart-9a0659eb-b947-41ff-a3d4-d0df5c84cdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207064081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.207064081
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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