Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8342

1

T2

21

T7

102

T10

34

auto[1]

11247

1

T2

80

T3

4

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6024	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6613	1			T1	1		T2	27		T3	2
reset_info_cp[2]	3020	1			T2	20		T3	1		T4	1
reset_info_cp[4]	3973	1			T2	10		T3	1		T4	1
reset_info_cp[8]	107	1			T7	2		T22	1		T24	3
reset_info_cp[16]	110	1			T2	1		T7	2		T10	1
reset_info_cp[32]	126	1			T7	1		T11	1		T22	4
reset_info_cp[64]	132	1			T2	1		T7	2		T11	1
reset_info_cp[128]	103	1			T2	1		T7	1		T9	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3150	1			T2	21		T7	30		T10	10
reset_info_cp[1]	auto[1]	2844	1			T2	5		T3	1		T4	1
reset_info_cp[2]	auto[0]	964	1			T7	16		T10	3		T22	37
reset_info_cp[2]	auto[1]	2056	1			T2	20		T3	1		T4	1
reset_info_cp[4]	auto[0]	1498	1			T7	20		T10	7		T22	56
reset_info_cp[4]	auto[1]	2475	1			T2	10		T3	1		T4	1
reset_info_cp[8]	auto[0]	56	1			T7	2		T22	1		T24	3
reset_info_cp[8]	auto[1]	51	1			T48	1		T92	1		T116	1
reset_info_cp[16]	auto[0]	44	1			T7	1		T10	1		T22	1
reset_info_cp[16]	auto[1]	66	1			T2	1		T7	1		T22	1
reset_info_cp[32]	auto[0]	53	1			T11	1		T22	1		T24	1
reset_info_cp[32]	auto[1]	73	1			T7	1		T22	3		T105	1
reset_info_cp[64]	auto[0]	44	1			T11	1		T22	1		T57	1
reset_info_cp[64]	auto[1]	88	1			T2	1		T7	2		T22	1
reset_info_cp[128]	auto[0]	35	1			T7	1		T22	2		T47	1
reset_info_cp[128]	auto[1]	68	1			T2	1		T9	1		T22	2