Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 619
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T537 /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.339775175 Jun 30 05:06:01 PM PDT 24 Jun 30 05:06:03 PM PDT 24 121371278 ps
T538 /workspace/coverage/default/13.rstmgr_stress_all.2928217988 Jun 30 05:05:00 PM PDT 24 Jun 30 05:05:07 PM PDT 24 1486288988 ps
T539 /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3451168262 Jun 30 05:05:15 PM PDT 24 Jun 30 05:05:18 PM PDT 24 172699545 ps
T540 /workspace/coverage/default/36.rstmgr_smoke.2318055967 Jun 30 05:05:50 PM PDT 24 Jun 30 05:05:52 PM PDT 24 191361961 ps
T63 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.739845185 Jun 30 05:46:30 PM PDT 24 Jun 30 05:46:32 PM PDT 24 81701318 ps
T64 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1169575971 Jun 30 05:46:35 PM PDT 24 Jun 30 05:46:38 PM PDT 24 109984197 ps
T65 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.108900404 Jun 30 05:46:30 PM PDT 24 Jun 30 05:46:37 PM PDT 24 484749550 ps
T127 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.209535611 Jun 30 05:46:28 PM PDT 24 Jun 30 05:46:30 PM PDT 24 69688258 ps
T68 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3253641132 Jun 30 05:46:26 PM PDT 24 Jun 30 05:46:28 PM PDT 24 188399445 ps
T69 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1729997826 Jun 30 05:46:21 PM PDT 24 Jun 30 05:46:25 PM PDT 24 876242662 ps
T71 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2511199275 Jun 30 05:46:26 PM PDT 24 Jun 30 05:46:28 PM PDT 24 577579675 ps
T70 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3568441120 Jun 30 05:46:30 PM PDT 24 Jun 30 05:46:32 PM PDT 24 106023974 ps
T117 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3973742347 Jun 30 05:46:29 PM PDT 24 Jun 30 05:46:32 PM PDT 24 84621259 ps
T72 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3891074732 Jun 30 05:46:23 PM PDT 24 Jun 30 05:46:27 PM PDT 24 465362963 ps
T96 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2345290599 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:30 PM PDT 24 480915290 ps
T541 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.140964540 Jun 30 05:46:35 PM PDT 24 Jun 30 05:46:37 PM PDT 24 92540666 ps
T118 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1274494422 Jun 30 05:46:26 PM PDT 24 Jun 30 05:46:27 PM PDT 24 73117950 ps
T119 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1396247331 Jun 30 05:46:16 PM PDT 24 Jun 30 05:46:19 PM PDT 24 242315583 ps
T120 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3680427962 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:29 PM PDT 24 96243027 ps
T102 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.773396203 Jun 30 05:46:28 PM PDT 24 Jun 30 05:46:32 PM PDT 24 913988783 ps
T121 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.484631784 Jun 30 05:46:29 PM PDT 24 Jun 30 05:46:32 PM PDT 24 246861536 ps
T97 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2719197347 Jun 30 05:46:20 PM PDT 24 Jun 30 05:46:24 PM PDT 24 784704999 ps
T98 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1751463504 Jun 30 05:46:30 PM PDT 24 Jun 30 05:46:35 PM PDT 24 922464432 ps
T122 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3291899030 Jun 30 05:46:28 PM PDT 24 Jun 30 05:46:30 PM PDT 24 72275006 ps
T542 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.483602110 Jun 30 05:46:17 PM PDT 24 Jun 30 05:46:24 PM PDT 24 489198842 ps
T123 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.949651584 Jun 30 05:46:35 PM PDT 24 Jun 30 05:46:37 PM PDT 24 129737521 ps
T99 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1787621904 Jun 30 05:46:31 PM PDT 24 Jun 30 05:46:35 PM PDT 24 265160735 ps
T100 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3728898870 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:32 PM PDT 24 493700888 ps
T124 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3614865470 Jun 30 05:46:19 PM PDT 24 Jun 30 05:46:21 PM PDT 24 215119575 ps
T101 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3633441804 Jun 30 05:46:28 PM PDT 24 Jun 30 05:46:31 PM PDT 24 422737326 ps
T103 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2120209285 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:32 PM PDT 24 468538580 ps
T104 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1621517213 Jun 30 05:46:35 PM PDT 24 Jun 30 05:46:38 PM PDT 24 182865920 ps
T125 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2423061825 Jun 30 05:46:32 PM PDT 24 Jun 30 05:46:34 PM PDT 24 82607705 ps
T126 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2650148186 Jun 30 05:46:16 PM PDT 24 Jun 30 05:46:18 PM PDT 24 117580929 ps
T543 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.631091944 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:31 PM PDT 24 784209711 ps
T128 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.698092539 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:31 PM PDT 24 1152914587 ps
T132 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3348877534 Jun 30 05:46:26 PM PDT 24 Jun 30 05:46:29 PM PDT 24 140581190 ps
T544 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.505517952 Jun 30 05:46:33 PM PDT 24 Jun 30 05:46:35 PM PDT 24 110778744 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1370813117 Jun 30 05:46:26 PM PDT 24 Jun 30 05:46:28 PM PDT 24 213623073 ps
T546 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3180836498 Jun 30 05:46:26 PM PDT 24 Jun 30 05:46:29 PM PDT 24 423407590 ps
T131 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3054764643 Jun 30 05:46:28 PM PDT 24 Jun 30 05:46:32 PM PDT 24 143200348 ps
T129 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3756092649 Jun 30 05:46:18 PM PDT 24 Jun 30 05:46:21 PM PDT 24 492877884 ps
T547 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.670441712 Jun 30 05:46:36 PM PDT 24 Jun 30 05:46:38 PM PDT 24 112821916 ps
T548 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2550592863 Jun 30 05:46:26 PM PDT 24 Jun 30 05:46:27 PM PDT 24 102453030 ps
T549 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1868021758 Jun 30 05:46:32 PM PDT 24 Jun 30 05:46:35 PM PDT 24 172655373 ps
T550 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.185747805 Jun 30 05:46:33 PM PDT 24 Jun 30 05:46:35 PM PDT 24 207731966 ps
T551 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4156627028 Jun 30 05:46:35 PM PDT 24 Jun 30 05:46:38 PM PDT 24 482442459 ps
T552 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1777490929 Jun 30 05:46:26 PM PDT 24 Jun 30 05:46:28 PM PDT 24 90113207 ps
T553 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1139764311 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:31 PM PDT 24 351083990 ps
T554 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3254556137 Jun 30 05:46:23 PM PDT 24 Jun 30 05:46:24 PM PDT 24 148498036 ps
T555 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2795715654 Jun 30 05:46:23 PM PDT 24 Jun 30 05:46:25 PM PDT 24 144705705 ps
T556 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3464012395 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:33 PM PDT 24 1166872093 ps
T557 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2013859065 Jun 30 05:46:32 PM PDT 24 Jun 30 05:46:36 PM PDT 24 479627497 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.683034783 Jun 30 05:46:18 PM PDT 24 Jun 30 05:46:21 PM PDT 24 92858993 ps
T559 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2490103354 Jun 30 05:46:26 PM PDT 24 Jun 30 05:46:28 PM PDT 24 153027087 ps
T560 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.793251164 Jun 30 05:46:28 PM PDT 24 Jun 30 05:46:31 PM PDT 24 150278955 ps
T561 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.926857204 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:31 PM PDT 24 189531535 ps
T562 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.567261565 Jun 30 05:46:22 PM PDT 24 Jun 30 05:46:25 PM PDT 24 384831104 ps
T563 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.649039027 Jun 30 05:46:29 PM PDT 24 Jun 30 05:46:32 PM PDT 24 182620460 ps
T564 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.387021338 Jun 30 05:46:32 PM PDT 24 Jun 30 05:46:35 PM PDT 24 95029206 ps
T565 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.27460754 Jun 30 05:46:35 PM PDT 24 Jun 30 05:46:37 PM PDT 24 70568608 ps
T566 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.482057639 Jun 30 05:46:24 PM PDT 24 Jun 30 05:46:26 PM PDT 24 235534394 ps
T567 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3047020941 Jun 30 05:46:31 PM PDT 24 Jun 30 05:46:33 PM PDT 24 59403483 ps
T568 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3074298800 Jun 30 05:46:35 PM PDT 24 Jun 30 05:46:38 PM PDT 24 228320972 ps
T569 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4063264142 Jun 30 05:46:35 PM PDT 24 Jun 30 05:46:38 PM PDT 24 483776391 ps
T570 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2853889449 Jun 30 05:46:33 PM PDT 24 Jun 30 05:46:35 PM PDT 24 106692834 ps
T571 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4250378183 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:29 PM PDT 24 78829539 ps
T572 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4268850677 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:29 PM PDT 24 113941293 ps
T573 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1929036824 Jun 30 05:46:16 PM PDT 24 Jun 30 05:46:18 PM PDT 24 222959163 ps
T574 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.938780639 Jun 30 05:46:23 PM PDT 24 Jun 30 05:46:26 PM PDT 24 132249555 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4217402714 Jun 30 05:46:19 PM PDT 24 Jun 30 05:46:21 PM PDT 24 128652455 ps
T576 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.315367023 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:29 PM PDT 24 70322090 ps
T577 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2694508756 Jun 30 05:46:33 PM PDT 24 Jun 30 05:46:36 PM PDT 24 398987183 ps
T578 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.861158484 Jun 30 05:46:35 PM PDT 24 Jun 30 05:46:39 PM PDT 24 915497121 ps
T579 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2110457842 Jun 30 05:46:25 PM PDT 24 Jun 30 05:46:26 PM PDT 24 143855638 ps
T580 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1911981860 Jun 30 05:46:21 PM PDT 24 Jun 30 05:46:22 PM PDT 24 97737482 ps
T581 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3326171305 Jun 30 05:46:18 PM PDT 24 Jun 30 05:46:21 PM PDT 24 365451300 ps
T582 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3199083503 Jun 30 05:46:18 PM PDT 24 Jun 30 05:46:22 PM PDT 24 780237652 ps
T130 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1400105407 Jun 30 05:46:28 PM PDT 24 Jun 30 05:46:33 PM PDT 24 869371970 ps
T583 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1479286705 Jun 30 05:46:29 PM PDT 24 Jun 30 05:46:31 PM PDT 24 63689589 ps
T584 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.957487614 Jun 30 05:46:28 PM PDT 24 Jun 30 05:46:31 PM PDT 24 111651480 ps
T585 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1787449464 Jun 30 05:46:24 PM PDT 24 Jun 30 05:46:26 PM PDT 24 105782368 ps
T586 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.979555374 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:29 PM PDT 24 91908352 ps
T587 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1956413893 Jun 30 05:46:29 PM PDT 24 Jun 30 05:46:31 PM PDT 24 69813585 ps
T588 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2852177159 Jun 30 05:46:34 PM PDT 24 Jun 30 05:46:36 PM PDT 24 142449977 ps
T589 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1653220241 Jun 30 05:46:29 PM PDT 24 Jun 30 05:46:31 PM PDT 24 85866310 ps
T590 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2360099257 Jun 30 05:46:22 PM PDT 24 Jun 30 05:46:23 PM PDT 24 113815145 ps
T591 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2221830202 Jun 30 05:46:29 PM PDT 24 Jun 30 05:46:32 PM PDT 24 185699633 ps
T592 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4005681821 Jun 30 05:46:28 PM PDT 24 Jun 30 05:46:31 PM PDT 24 190816006 ps
T593 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3619453874 Jun 30 05:46:32 PM PDT 24 Jun 30 05:46:35 PM PDT 24 194914410 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1324686388 Jun 30 05:46:17 PM PDT 24 Jun 30 05:46:20 PM PDT 24 329702482 ps
T595 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.451433120 Jun 30 05:46:34 PM PDT 24 Jun 30 05:46:36 PM PDT 24 186375594 ps
T596 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1291866677 Jun 30 05:46:28 PM PDT 24 Jun 30 05:46:31 PM PDT 24 244572644 ps
T597 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2337154366 Jun 30 05:46:32 PM PDT 24 Jun 30 05:46:37 PM PDT 24 184456386 ps
T598 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2891095030 Jun 30 05:46:32 PM PDT 24 Jun 30 05:46:36 PM PDT 24 203785502 ps
T108 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.456677260 Jun 30 05:46:17 PM PDT 24 Jun 30 05:46:19 PM PDT 24 55030570 ps
T599 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3327098404 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:30 PM PDT 24 488108808 ps
T109 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.9841002 Jun 30 05:46:39 PM PDT 24 Jun 30 05:46:42 PM PDT 24 413153529 ps
T600 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.888371363 Jun 30 05:46:33 PM PDT 24 Jun 30 05:46:35 PM PDT 24 65624141 ps
T601 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3144384640 Jun 30 05:46:26 PM PDT 24 Jun 30 05:46:28 PM PDT 24 57953568 ps
T602 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3930016532 Jun 30 05:46:28 PM PDT 24 Jun 30 05:46:31 PM PDT 24 149232246 ps
T110 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.431937233 Jun 30 05:46:29 PM PDT 24 Jun 30 05:46:31 PM PDT 24 77357921 ps
T603 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3159687408 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:30 PM PDT 24 183400481 ps
T604 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3189535629 Jun 30 05:46:17 PM PDT 24 Jun 30 05:46:25 PM PDT 24 487124498 ps
T605 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2676458227 Jun 30 05:46:29 PM PDT 24 Jun 30 05:46:31 PM PDT 24 62492690 ps
T606 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4077935511 Jun 30 05:46:35 PM PDT 24 Jun 30 05:46:39 PM PDT 24 365860097 ps
T607 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3221234847 Jun 30 05:46:18 PM PDT 24 Jun 30 05:46:20 PM PDT 24 86606073 ps
T608 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3689283689 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:30 PM PDT 24 204444125 ps
T609 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4247790691 Jun 30 05:46:35 PM PDT 24 Jun 30 05:46:37 PM PDT 24 77404326 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.920879476 Jun 30 05:46:19 PM PDT 24 Jun 30 05:46:22 PM PDT 24 121826013 ps
T611 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1752666834 Jun 30 05:46:30 PM PDT 24 Jun 30 05:46:32 PM PDT 24 96416150 ps
T612 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4184059712 Jun 30 05:46:17 PM PDT 24 Jun 30 05:46:20 PM PDT 24 108120145 ps
T613 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.576388112 Jun 30 05:46:32 PM PDT 24 Jun 30 05:46:35 PM PDT 24 104447535 ps
T614 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3518257177 Jun 30 05:46:29 PM PDT 24 Jun 30 05:46:32 PM PDT 24 109815945 ps
T615 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2343659179 Jun 30 05:46:20 PM PDT 24 Jun 30 05:46:22 PM PDT 24 108453724 ps
T616 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.705583209 Jun 30 05:46:27 PM PDT 24 Jun 30 05:46:30 PM PDT 24 423909086 ps
T617 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1942335013 Jun 30 05:46:18 PM PDT 24 Jun 30 05:46:21 PM PDT 24 184825640 ps
T618 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3152660552 Jun 30 05:46:19 PM PDT 24 Jun 30 05:46:26 PM PDT 24 486542492 ps
T619 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2005184080 Jun 30 05:46:32 PM PDT 24 Jun 30 05:46:34 PM PDT 24 81406934 ps

Test location /workspace/coverage/default/37.rstmgr_stress_all.777722523
Short name T7
Test name
Test status
Simulation time 7398724170 ps
CPU time 26.4 seconds
Started Jun 30 05:05:58 PM PDT 24
Finished Jun 30 05:06:24 PM PDT 24
Peak memory 210152 kb
Host smart-66bc928d-57ba-483f-8692-9bd3f8573dc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777722523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.777722523
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3896323175
Short name T20
Test name
Test status
Simulation time 348410444 ps
CPU time 2.13 seconds
Started Jun 30 05:06:02 PM PDT 24
Finished Jun 30 05:06:05 PM PDT 24
Peak memory 200044 kb
Host smart-e8180501-6427-4dbc-900f-c39716e6aa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896323175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3896323175
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3568441120
Short name T70
Test name
Test status
Simulation time 106023974 ps
CPU time 1.06 seconds
Started Jun 30 05:46:30 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 211080 kb
Host smart-805e9e92-23d4-41e3-8862-b425d5e99d85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568441120 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3568441120
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1269225307
Short name T74
Test name
Test status
Simulation time 8407729803 ps
CPU time 13.97 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:04:50 PM PDT 24
Peak memory 217336 kb
Host smart-bb1ee98a-5a9b-47be-b8cf-9d5601e3e4f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269225307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1269225307
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2363907912
Short name T26
Test name
Test status
Simulation time 1216082010 ps
CPU time 5.5 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:30 PM PDT 24
Peak memory 217216 kb
Host smart-61520341-c707-4a16-8271-541f3050adce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363907912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2363907912
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1751463504
Short name T98
Test name
Test status
Simulation time 922464432 ps
CPU time 3.59 seconds
Started Jun 30 05:46:30 PM PDT 24
Finished Jun 30 05:46:35 PM PDT 24
Peak memory 200468 kb
Host smart-cbcfc2aa-d1d8-4eb4-ba79-70eab189bceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751463504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1751463504
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1996353623
Short name T22
Test name
Test status
Simulation time 7509682743 ps
CPU time 34.22 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:50 PM PDT 24
Peak memory 208588 kb
Host smart-9679690d-c945-477b-9c1d-ed833b2a7ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996353623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1996353623
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3891074732
Short name T72
Test name
Test status
Simulation time 465362963 ps
CPU time 3.52 seconds
Started Jun 30 05:46:23 PM PDT 24
Finished Jun 30 05:46:27 PM PDT 24
Peak memory 208520 kb
Host smart-d98ca367-2407-44b2-bc24-e2807a992097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891074732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3891074732
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2943098270
Short name T162
Test name
Test status
Simulation time 142165242 ps
CPU time 1.13 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:38 PM PDT 24
Peak memory 199980 kb
Host smart-e8deb753-12a5-416a-9bb0-112eb36a01bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943098270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2943098270
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.227370878
Short name T78
Test name
Test status
Simulation time 82082295 ps
CPU time 0.87 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:17 PM PDT 24
Peak memory 199780 kb
Host smart-2a542398-c66a-4d1a-a7c1-ce143c17fe59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227370878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.227370878
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1698184691
Short name T2
Test name
Test status
Simulation time 2366425838 ps
CPU time 8.28 seconds
Started Jun 30 05:04:59 PM PDT 24
Finished Jun 30 05:05:08 PM PDT 24
Peak memory 217792 kb
Host smart-fb825eed-f86a-46ff-88d7-04c0490a7c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698184691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1698184691
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1116976139
Short name T83
Test name
Test status
Simulation time 220622106 ps
CPU time 1.36 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:17 PM PDT 24
Peak memory 199960 kb
Host smart-73dc839e-39ee-4973-8348-b0c5cf3447b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116976139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1116976139
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3973742347
Short name T117
Test name
Test status
Simulation time 84621259 ps
CPU time 1.08 seconds
Started Jun 30 05:46:29 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 200260 kb
Host smart-059a8837-b97f-42a5-9f37-678907e870cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973742347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3973742347
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.567261565
Short name T562
Test name
Test status
Simulation time 384831104 ps
CPU time 2.84 seconds
Started Jun 30 05:46:22 PM PDT 24
Finished Jun 30 05:46:25 PM PDT 24
Peak memory 208536 kb
Host smart-c6f117f4-7cdc-4d43-a2f2-99d9e8df6494
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567261565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.567261565
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1400105407
Short name T130
Test name
Test status
Simulation time 869371970 ps
CPU time 2.94 seconds
Started Jun 30 05:46:28 PM PDT 24
Finished Jun 30 05:46:33 PM PDT 24
Peak memory 200420 kb
Host smart-9346ba05-4211-42ad-8aca-17796ba773e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400105407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1400105407
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3156982504
Short name T6
Test name
Test status
Simulation time 76572211 ps
CPU time 0.76 seconds
Started Jun 30 05:04:54 PM PDT 24
Finished Jun 30 05:04:56 PM PDT 24
Peak memory 199728 kb
Host smart-d32e7005-3b26-40c6-86a7-101eaa9a6d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156982504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3156982504
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1603318334
Short name T51
Test name
Test status
Simulation time 1891953772 ps
CPU time 7.12 seconds
Started Jun 30 05:04:27 PM PDT 24
Finished Jun 30 05:04:35 PM PDT 24
Peak memory 221504 kb
Host smart-ebbf2d9f-c0fc-4946-bb33-2d90cd69ce32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603318334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1603318334
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3756092649
Short name T129
Test name
Test status
Simulation time 492877884 ps
CPU time 2.06 seconds
Started Jun 30 05:46:18 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 200428 kb
Host smart-224eefdb-c0e8-4f55-8790-a1669bb28e25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756092649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3756092649
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4184059712
Short name T612
Test name
Test status
Simulation time 108120145 ps
CPU time 1.38 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:20 PM PDT 24
Peak memory 200368 kb
Host smart-52fbb5d7-ea05-49d0-a222-9caf480d0e21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184059712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
184059712
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.108900404
Short name T65
Test name
Test status
Simulation time 484749550 ps
CPU time 5.77 seconds
Started Jun 30 05:46:30 PM PDT 24
Finished Jun 30 05:46:37 PM PDT 24
Peak memory 200372 kb
Host smart-a776e274-980f-4658-9a81-eaf1d226b1f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108900404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.108900404
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1787449464
Short name T585
Test name
Test status
Simulation time 105782368 ps
CPU time 0.85 seconds
Started Jun 30 05:46:24 PM PDT 24
Finished Jun 30 05:46:26 PM PDT 24
Peak memory 200228 kb
Host smart-03fc3547-8e81-4083-bb59-663e1d57c782
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787449464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
787449464
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2360099257
Short name T590
Test name
Test status
Simulation time 113815145 ps
CPU time 1.12 seconds
Started Jun 30 05:46:22 PM PDT 24
Finished Jun 30 05:46:23 PM PDT 24
Peak memory 208420 kb
Host smart-02e043af-11d4-4fcd-8135-935e512c8bae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360099257 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2360099257
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.739845185
Short name T63
Test name
Test status
Simulation time 81701318 ps
CPU time 0.88 seconds
Started Jun 30 05:46:30 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 200228 kb
Host smart-2039b22c-0f6f-446c-bc99-1e3e93d06ca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739845185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.739845185
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1396247331
Short name T119
Test name
Test status
Simulation time 242315583 ps
CPU time 1.59 seconds
Started Jun 30 05:46:16 PM PDT 24
Finished Jun 30 05:46:19 PM PDT 24
Peak memory 200452 kb
Host smart-969c137e-fd24-4f28-950c-ab337aa56050
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396247331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1396247331
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1729997826
Short name T69
Test name
Test status
Simulation time 876242662 ps
CPU time 3.43 seconds
Started Jun 30 05:46:21 PM PDT 24
Finished Jun 30 05:46:25 PM PDT 24
Peak memory 200416 kb
Host smart-84a54aa7-af95-4d6e-ac2e-5ca2759b2db7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729997826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1729997826
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2795715654
Short name T555
Test name
Test status
Simulation time 144705705 ps
CPU time 2.08 seconds
Started Jun 30 05:46:23 PM PDT 24
Finished Jun 30 05:46:25 PM PDT 24
Peak memory 200360 kb
Host smart-03a6c81a-ae4a-48df-9f23-a3ff4e6d539c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795715654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
795715654
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.483602110
Short name T542
Test name
Test status
Simulation time 489198842 ps
CPU time 5.93 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:24 PM PDT 24
Peak memory 200368 kb
Host smart-8819cb63-105a-42c5-83e5-1befaa032794
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483602110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.483602110
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4217402714
Short name T575
Test name
Test status
Simulation time 128652455 ps
CPU time 0.89 seconds
Started Jun 30 05:46:19 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 200228 kb
Host smart-0186c27c-1254-4b21-95d9-18f11a79fe1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217402714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4
217402714
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1942335013
Short name T617
Test name
Test status
Simulation time 184825640 ps
CPU time 1.29 seconds
Started Jun 30 05:46:18 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 210320 kb
Host smart-af0fac88-e1b6-4071-a6e4-6a0fec043744
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942335013 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1942335013
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.456677260
Short name T108
Test name
Test status
Simulation time 55030570 ps
CPU time 0.78 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:19 PM PDT 24
Peak memory 200164 kb
Host smart-2fb0de12-bce1-4e85-8a8e-9ad537d3175d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456677260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.456677260
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2650148186
Short name T126
Test name
Test status
Simulation time 117580929 ps
CPU time 1.1 seconds
Started Jun 30 05:46:16 PM PDT 24
Finished Jun 30 05:46:18 PM PDT 24
Peak memory 200280 kb
Host smart-100b804f-ad59-420a-b093-1955f2f40ac1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650148186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2650148186
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1324686388
Short name T594
Test name
Test status
Simulation time 329702482 ps
CPU time 2.53 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:20 PM PDT 24
Peak memory 216704 kb
Host smart-de109ba6-8f08-4a75-84dc-79d7a105fb65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324686388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1324686388
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4005681821
Short name T592
Test name
Test status
Simulation time 190816006 ps
CPU time 1.93 seconds
Started Jun 30 05:46:28 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 208688 kb
Host smart-de4f3ddb-2504-4f62-98b0-0f1045826982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005681821 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.4005681821
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4250378183
Short name T571
Test name
Test status
Simulation time 78829539 ps
CPU time 0.83 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:29 PM PDT 24
Peak memory 200232 kb
Host smart-15434220-f4af-4fc5-be29-96741e14b3d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250378183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4250378183
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1291866677
Short name T596
Test name
Test status
Simulation time 244572644 ps
CPU time 1.54 seconds
Started Jun 30 05:46:28 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200272 kb
Host smart-da7d7400-fb8d-4a74-8907-1b9441ac6ef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291866677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1291866677
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.926857204
Short name T561
Test name
Test status
Simulation time 189531535 ps
CPU time 1.66 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 210644 kb
Host smart-c763fff1-ecc3-4508-b597-55b69ff5abaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926857204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.926857204
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3159687408
Short name T603
Test name
Test status
Simulation time 183400481 ps
CPU time 1.81 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:30 PM PDT 24
Peak memory 208680 kb
Host smart-1d57bfbc-4384-49e0-8fe9-a8dbe86109a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159687408 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3159687408
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.209535611
Short name T127
Test name
Test status
Simulation time 69688258 ps
CPU time 0.77 seconds
Started Jun 30 05:46:28 PM PDT 24
Finished Jun 30 05:46:30 PM PDT 24
Peak memory 200104 kb
Host smart-da86592d-4c7b-4eaa-a9c0-4dcb9df5fc52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209535611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.209535611
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3680427962
Short name T120
Test name
Test status
Simulation time 96243027 ps
CPU time 1.16 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:29 PM PDT 24
Peak memory 200396 kb
Host smart-1c39e121-bc0c-496e-9003-b08c847723be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680427962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3680427962
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.387021338
Short name T564
Test name
Test status
Simulation time 95029206 ps
CPU time 1.39 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 05:46:35 PM PDT 24
Peak memory 208536 kb
Host smart-285cc38f-e5f2-4cb6-bd21-ca06253bfc34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387021338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.387021338
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.631091944
Short name T543
Test name
Test status
Simulation time 784209711 ps
CPU time 3 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200412 kb
Host smart-835af423-bbc7-4274-aa94-d13e4788ed7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631091944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.631091944
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2550592863
Short name T548
Test name
Test status
Simulation time 102453030 ps
CPU time 0.92 seconds
Started Jun 30 05:46:26 PM PDT 24
Finished Jun 30 05:46:27 PM PDT 24
Peak memory 200316 kb
Host smart-39df1c9c-c738-44e2-9756-3d7d5b4f766c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550592863 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2550592863
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2676458227
Short name T605
Test name
Test status
Simulation time 62492690 ps
CPU time 0.73 seconds
Started Jun 30 05:46:29 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200096 kb
Host smart-1fdf17cb-8e26-4bcf-bee6-1af1b6ced1ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676458227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2676458227
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3930016532
Short name T602
Test name
Test status
Simulation time 149232246 ps
CPU time 1.17 seconds
Started Jun 30 05:46:28 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200284 kb
Host smart-88a5a166-1864-4793-bb35-ca5ecfee30d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930016532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3930016532
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.957487614
Short name T584
Test name
Test status
Simulation time 111651480 ps
CPU time 1.67 seconds
Started Jun 30 05:46:28 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 208396 kb
Host smart-17c83bd7-b3bf-4faa-a9a7-7f1f702710d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957487614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.957487614
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3327098404
Short name T599
Test name
Test status
Simulation time 488108808 ps
CPU time 1.9 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:30 PM PDT 24
Peak memory 200480 kb
Host smart-3216d394-9670-460b-aa4d-65de8c3be0b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327098404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3327098404
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.185747805
Short name T550
Test name
Test status
Simulation time 207731966 ps
CPU time 1.34 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 05:46:35 PM PDT 24
Peak memory 208520 kb
Host smart-4658f878-ec35-44a6-baa3-89c96f16a340
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185747805 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.185747805
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1479286705
Short name T583
Test name
Test status
Simulation time 63689589 ps
CPU time 0.84 seconds
Started Jun 30 05:46:29 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200220 kb
Host smart-82333e64-4ded-45f4-8f5e-02dbd0eff59f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479286705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1479286705
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.484631784
Short name T121
Test name
Test status
Simulation time 246861536 ps
CPU time 1.61 seconds
Started Jun 30 05:46:29 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 200416 kb
Host smart-6d3f3223-8e34-44c9-9380-0826f5d123a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484631784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.484631784
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2891095030
Short name T598
Test name
Test status
Simulation time 203785502 ps
CPU time 1.8 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 05:46:36 PM PDT 24
Peak memory 216764 kb
Host smart-4c4ff69b-330f-4d4c-a9de-b9b02746ce95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891095030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2891095030
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3180836498
Short name T546
Test name
Test status
Simulation time 423407590 ps
CPU time 1.94 seconds
Started Jun 30 05:46:26 PM PDT 24
Finished Jun 30 05:46:29 PM PDT 24
Peak memory 200368 kb
Host smart-2f836c58-7802-434a-97ac-e1dff1a0faa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180836498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3180836498
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4268850677
Short name T572
Test name
Test status
Simulation time 113941293 ps
CPU time 0.92 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:29 PM PDT 24
Peak memory 200288 kb
Host smart-fc4284b6-ea69-4661-aff2-d9adc4e67704
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268850677 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.4268850677
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.979555374
Short name T586
Test name
Test status
Simulation time 91908352 ps
CPU time 0.85 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:29 PM PDT 24
Peak memory 200220 kb
Host smart-ffc84dd3-d691-4f0f-a1ce-d9949ceff149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979555374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.979555374
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1653220241
Short name T589
Test name
Test status
Simulation time 85866310 ps
CPU time 1.1 seconds
Started Jun 30 05:46:29 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200276 kb
Host smart-fd4fabd5-7120-4b0e-bbf7-2544ac834127
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653220241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1653220241
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3728898870
Short name T100
Test name
Test status
Simulation time 493700888 ps
CPU time 3.3 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 208552 kb
Host smart-6ef26621-e21c-4596-90b4-65bc8652764b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728898870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3728898870
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.861158484
Short name T578
Test name
Test status
Simulation time 915497121 ps
CPU time 3.3 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 05:46:39 PM PDT 24
Peak memory 200504 kb
Host smart-d076d7bb-6416-4faa-ac41-c3f0edf4dd21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861158484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.861158484
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2853889449
Short name T570
Test name
Test status
Simulation time 106692834 ps
CPU time 0.94 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 05:46:35 PM PDT 24
Peak memory 200236 kb
Host smart-b3b233cd-2e7d-4b47-80c8-4ce22f7f8d53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853889449 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2853889449
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.140964540
Short name T541
Test name
Test status
Simulation time 92540666 ps
CPU time 0.86 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 05:46:37 PM PDT 24
Peak memory 200236 kb
Host smart-a63b43ef-6d7d-4cee-9ca9-95fb47320a58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140964540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.140964540
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2337154366
Short name T597
Test name
Test status
Simulation time 184456386 ps
CPU time 2.67 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 05:46:37 PM PDT 24
Peak memory 208568 kb
Host smart-cb6c919a-8eea-465b-a077-7a96faf9f702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337154366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2337154366
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4063264142
Short name T569
Test name
Test status
Simulation time 483776391 ps
CPU time 1.94 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 05:46:38 PM PDT 24
Peak memory 200440 kb
Host smart-53ffa7c6-687c-4e82-9c92-e3b11a1fc27c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063264142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.4063264142
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3619453874
Short name T593
Test name
Test status
Simulation time 194914410 ps
CPU time 1.95 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 05:46:35 PM PDT 24
Peak memory 208700 kb
Host smart-4337213e-62a9-4a1e-a685-b121463f1497
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619453874 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3619453874
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3047020941
Short name T567
Test name
Test status
Simulation time 59403483 ps
CPU time 0.84 seconds
Started Jun 30 05:46:31 PM PDT 24
Finished Jun 30 05:46:33 PM PDT 24
Peak memory 200224 kb
Host smart-cb3b2eba-1e06-47d0-a658-0ed6a23f783a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047020941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3047020941
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3074298800
Short name T568
Test name
Test status
Simulation time 228320972 ps
CPU time 1.54 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 05:46:38 PM PDT 24
Peak memory 200204 kb
Host smart-87ed6118-e4b4-44ef-8d51-38a2253acc2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074298800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3074298800
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4077935511
Short name T606
Test name
Test status
Simulation time 365860097 ps
CPU time 2.49 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 05:46:39 PM PDT 24
Peak memory 208456 kb
Host smart-a52b0a34-3daf-4717-a915-54cfd5db27b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077935511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.4077935511
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4156627028
Short name T551
Test name
Test status
Simulation time 482442459 ps
CPU time 2.06 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 05:46:38 PM PDT 24
Peak memory 200380 kb
Host smart-868c5c88-e177-4f03-8681-65acd37dac8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156627028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.4156627028
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2852177159
Short name T588
Test name
Test status
Simulation time 142449977 ps
CPU time 1.08 seconds
Started Jun 30 05:46:34 PM PDT 24
Finished Jun 30 05:46:36 PM PDT 24
Peak memory 210164 kb
Host smart-a50634a2-b417-4a25-a722-ee63bb1ff884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852177159 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2852177159
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.27460754
Short name T565
Test name
Test status
Simulation time 70568608 ps
CPU time 0.82 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 05:46:37 PM PDT 24
Peak memory 200072 kb
Host smart-af02fa03-82c6-4da7-860b-f38cedc4b538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27460754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.27460754
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.949651584
Short name T123
Test name
Test status
Simulation time 129737521 ps
CPU time 1.2 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 05:46:37 PM PDT 24
Peak memory 200476 kb
Host smart-80b7ee76-2bfe-44a9-bc03-5a128096b24c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949651584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.949651584
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1752666834
Short name T611
Test name
Test status
Simulation time 96416150 ps
CPU time 1.37 seconds
Started Jun 30 05:46:30 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 200336 kb
Host smart-1ea2fd8c-177b-428b-a1c2-870eee7ccf0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752666834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1752666834
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2345290599
Short name T96
Test name
Test status
Simulation time 480915290 ps
CPU time 1.97 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:30 PM PDT 24
Peak memory 200360 kb
Host smart-8f9fef86-6a7b-43d7-bb59-a7979e950927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345290599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2345290599
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.451433120
Short name T595
Test name
Test status
Simulation time 186375594 ps
CPU time 1.22 seconds
Started Jun 30 05:46:34 PM PDT 24
Finished Jun 30 05:46:36 PM PDT 24
Peak memory 208544 kb
Host smart-ff71eeb7-cf55-4b34-b388-0028235130f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451433120 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.451433120
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.888371363
Short name T600
Test name
Test status
Simulation time 65624141 ps
CPU time 0.75 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 05:46:35 PM PDT 24
Peak memory 200156 kb
Host smart-a37487ba-a246-4ab1-8047-7b7aed9e42fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888371363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.888371363
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2423061825
Short name T125
Test name
Test status
Simulation time 82607705 ps
CPU time 1.11 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 05:46:34 PM PDT 24
Peak memory 200284 kb
Host smart-8d32da1e-66c0-495c-9d4c-4c575b73a338
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423061825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2423061825
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1621517213
Short name T104
Test name
Test status
Simulation time 182865920 ps
CPU time 1.6 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 05:46:38 PM PDT 24
Peak memory 208468 kb
Host smart-899b1ebe-8829-47ad-9016-bdd0e86aeb68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621517213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1621517213
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3633441804
Short name T101
Test name
Test status
Simulation time 422737326 ps
CPU time 1.74 seconds
Started Jun 30 05:46:28 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200432 kb
Host smart-42ca2b41-396e-43c5-9d04-cb08ecb78e6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633441804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3633441804
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1169575971
Short name T64
Test name
Test status
Simulation time 109984197 ps
CPU time 0.99 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 05:46:38 PM PDT 24
Peak memory 200564 kb
Host smart-70b7334e-6b88-43b3-bf09-53457b488f88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169575971 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1169575971
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4247790691
Short name T609
Test name
Test status
Simulation time 77404326 ps
CPU time 0.81 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 05:46:37 PM PDT 24
Peak memory 200236 kb
Host smart-924ec87e-29fb-4a2a-89bd-a0601c0e3664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247790691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.4247790691
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1868021758
Short name T549
Test name
Test status
Simulation time 172655373 ps
CPU time 1.33 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 05:46:35 PM PDT 24
Peak memory 200412 kb
Host smart-3e96de4c-0ca8-4200-a786-1dfe30e6c179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868021758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1868021758
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.670441712
Short name T547
Test name
Test status
Simulation time 112821916 ps
CPU time 1.6 seconds
Started Jun 30 05:46:36 PM PDT 24
Finished Jun 30 05:46:38 PM PDT 24
Peak memory 208788 kb
Host smart-55f8d783-13d9-45bf-bfb3-0c4fb0e93c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670441712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.670441712
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2694508756
Short name T577
Test name
Test status
Simulation time 398987183 ps
CPU time 1.77 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 05:46:36 PM PDT 24
Peak memory 200432 kb
Host smart-5f750409-a461-416e-a609-93db9d9ebddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694508756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2694508756
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.9841002
Short name T109
Test name
Test status
Simulation time 413153529 ps
CPU time 2.63 seconds
Started Jun 30 05:46:39 PM PDT 24
Finished Jun 30 05:46:42 PM PDT 24
Peak memory 208540 kb
Host smart-b8fb369f-4829-447c-b7d5-a449f3e3a578
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9841002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.9841002
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3152660552
Short name T618
Test name
Test status
Simulation time 486542492 ps
CPU time 5.9 seconds
Started Jun 30 05:46:19 PM PDT 24
Finished Jun 30 05:46:26 PM PDT 24
Peak memory 200368 kb
Host smart-0989c520-85ba-460b-9d60-e478f0c9f1bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152660552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
152660552
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3254556137
Short name T554
Test name
Test status
Simulation time 148498036 ps
CPU time 0.96 seconds
Started Jun 30 05:46:23 PM PDT 24
Finished Jun 30 05:46:24 PM PDT 24
Peak memory 200228 kb
Host smart-de70fb28-d6cf-4839-9e57-3ce40e3d304f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254556137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
254556137
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2343659179
Short name T615
Test name
Test status
Simulation time 108453724 ps
CPU time 1.11 seconds
Started Jun 30 05:46:20 PM PDT 24
Finished Jun 30 05:46:22 PM PDT 24
Peak memory 208540 kb
Host smart-45523ea6-33e6-4da2-a41a-d0143d1b40f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343659179 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2343659179
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3221234847
Short name T607
Test name
Test status
Simulation time 86606073 ps
CPU time 0.86 seconds
Started Jun 30 05:46:18 PM PDT 24
Finished Jun 30 05:46:20 PM PDT 24
Peak memory 200196 kb
Host smart-7903f3d4-d630-4c22-a7d6-35f0aa26000b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221234847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3221234847
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.683034783
Short name T558
Test name
Test status
Simulation time 92858993 ps
CPU time 1.03 seconds
Started Jun 30 05:46:18 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 200260 kb
Host smart-de33848b-7139-45c4-9cef-9239a526d38a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683034783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.683034783
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3199083503
Short name T582
Test name
Test status
Simulation time 780237652 ps
CPU time 2.78 seconds
Started Jun 30 05:46:18 PM PDT 24
Finished Jun 30 05:46:22 PM PDT 24
Peak memory 200416 kb
Host smart-c03dacc0-3918-4465-8706-4734fb43ecae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199083503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3199083503
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3326171305
Short name T581
Test name
Test status
Simulation time 365451300 ps
CPU time 2.44 seconds
Started Jun 30 05:46:18 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 200324 kb
Host smart-ec3b6068-bc50-42ef-8d80-9b9a5dec5f6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326171305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
326171305
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3189535629
Short name T604
Test name
Test status
Simulation time 487124498 ps
CPU time 6.32 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:25 PM PDT 24
Peak memory 208536 kb
Host smart-6f4052bf-76cc-4aea-b225-ab4e896c8fb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189535629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
189535629
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1911981860
Short name T580
Test name
Test status
Simulation time 97737482 ps
CPU time 0.86 seconds
Started Jun 30 05:46:21 PM PDT 24
Finished Jun 30 05:46:22 PM PDT 24
Peak memory 200208 kb
Host smart-99b1b321-ab35-4aae-b771-c1cfe150df5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911981860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
911981860
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.920879476
Short name T610
Test name
Test status
Simulation time 121826013 ps
CPU time 1.04 seconds
Started Jun 30 05:46:19 PM PDT 24
Finished Jun 30 05:46:22 PM PDT 24
Peak memory 200344 kb
Host smart-1896f99a-6d38-4a40-becb-7e21778b82e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920879476 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.920879476
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3291899030
Short name T122
Test name
Test status
Simulation time 72275006 ps
CPU time 0.84 seconds
Started Jun 30 05:46:28 PM PDT 24
Finished Jun 30 05:46:30 PM PDT 24
Peak memory 200184 kb
Host smart-b8b27e87-350b-4e28-98f7-6ffac3bdc4a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291899030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3291899030
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3614865470
Short name T124
Test name
Test status
Simulation time 215119575 ps
CPU time 1.5 seconds
Started Jun 30 05:46:19 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 200376 kb
Host smart-e3dff9f0-6974-4ad0-97b2-7b869c244eab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614865470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3614865470
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1929036824
Short name T573
Test name
Test status
Simulation time 222959163 ps
CPU time 1.85 seconds
Started Jun 30 05:46:16 PM PDT 24
Finished Jun 30 05:46:18 PM PDT 24
Peak memory 200344 kb
Host smart-37966778-24bf-4701-afd6-4369a7398ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929036824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1929036824
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2719197347
Short name T97
Test name
Test status
Simulation time 784704999 ps
CPU time 2.93 seconds
Started Jun 30 05:46:20 PM PDT 24
Finished Jun 30 05:46:24 PM PDT 24
Peak memory 200420 kb
Host smart-4fe93e65-899c-45ca-b7a3-529a714e444f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719197347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2719197347
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1139764311
Short name T553
Test name
Test status
Simulation time 351083990 ps
CPU time 2.43 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200364 kb
Host smart-3d29deb3-ccca-4927-b88f-a21ed3ee50fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139764311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
139764311
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3464012395
Short name T556
Test name
Test status
Simulation time 1166872093 ps
CPU time 4.95 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:33 PM PDT 24
Peak memory 200384 kb
Host smart-c85978e0-fdb2-49d4-a49c-fa5b5c551e6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464012395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
464012395
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.793251164
Short name T560
Test name
Test status
Simulation time 150278955 ps
CPU time 0.94 seconds
Started Jun 30 05:46:28 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200216 kb
Host smart-1fcb8b69-2f88-4601-af15-f65ba1b33e48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793251164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.793251164
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3689283689
Short name T608
Test name
Test status
Simulation time 204444125 ps
CPU time 1.36 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:30 PM PDT 24
Peak memory 208496 kb
Host smart-5a85b886-678e-4c87-80b8-7ade8e0e176c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689283689 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3689283689
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.431937233
Short name T110
Test name
Test status
Simulation time 77357921 ps
CPU time 0.81 seconds
Started Jun 30 05:46:29 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200224 kb
Host smart-4936707f-c890-4728-b773-a8a52fd4cd10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431937233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.431937233
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1370813117
Short name T545
Test name
Test status
Simulation time 213623073 ps
CPU time 1.53 seconds
Started Jun 30 05:46:26 PM PDT 24
Finished Jun 30 05:46:28 PM PDT 24
Peak memory 200456 kb
Host smart-968be03c-3409-4e39-9e54-5c9eeaad828e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370813117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1370813117
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.938780639
Short name T574
Test name
Test status
Simulation time 132249555 ps
CPU time 1.93 seconds
Started Jun 30 05:46:23 PM PDT 24
Finished Jun 30 05:46:26 PM PDT 24
Peak memory 200324 kb
Host smart-fb38a072-6410-44c9-99f6-2ff8da43d453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938780639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.938780639
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.698092539
Short name T128
Test name
Test status
Simulation time 1152914587 ps
CPU time 3.61 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200412 kb
Host smart-f393216a-c62a-4145-afee-59b862b04a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698092539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
698092539
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1956413893
Short name T587
Test name
Test status
Simulation time 69813585 ps
CPU time 0.77 seconds
Started Jun 30 05:46:29 PM PDT 24
Finished Jun 30 05:46:31 PM PDT 24
Peak memory 200216 kb
Host smart-3b4bfad2-b3c9-42ff-8b33-174659d54a8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956413893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1956413893
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3518257177
Short name T614
Test name
Test status
Simulation time 109815945 ps
CPU time 1.25 seconds
Started Jun 30 05:46:29 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 200364 kb
Host smart-022cfd18-8772-41cc-957d-43e1b142825f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518257177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3518257177
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2120209285
Short name T103
Test name
Test status
Simulation time 468538580 ps
CPU time 3.64 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 208548 kb
Host smart-9d07da52-4e04-44c5-bffd-53110df5a113
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120209285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2120209285
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2511199275
Short name T71
Test name
Test status
Simulation time 577579675 ps
CPU time 2.07 seconds
Started Jun 30 05:46:26 PM PDT 24
Finished Jun 30 05:46:28 PM PDT 24
Peak memory 200428 kb
Host smart-282dd17c-bb96-46c7-8280-392de883cf74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511199275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2511199275
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3253641132
Short name T68
Test name
Test status
Simulation time 188399445 ps
CPU time 1.37 seconds
Started Jun 30 05:46:26 PM PDT 24
Finished Jun 30 05:46:28 PM PDT 24
Peak memory 200348 kb
Host smart-d846786b-c42a-4a17-b02a-a61cb27dd6a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253641132 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3253641132
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3144384640
Short name T601
Test name
Test status
Simulation time 57953568 ps
CPU time 0.81 seconds
Started Jun 30 05:46:26 PM PDT 24
Finished Jun 30 05:46:28 PM PDT 24
Peak memory 200204 kb
Host smart-a6d88fbe-d87a-4f05-acee-e6b27e812366
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144384640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3144384640
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2110457842
Short name T579
Test name
Test status
Simulation time 143855638 ps
CPU time 1.14 seconds
Started Jun 30 05:46:25 PM PDT 24
Finished Jun 30 05:46:26 PM PDT 24
Peak memory 200224 kb
Host smart-5f235e38-998f-4d2c-b449-09924d536054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110457842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2110457842
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1787621904
Short name T99
Test name
Test status
Simulation time 265160735 ps
CPU time 2.21 seconds
Started Jun 30 05:46:31 PM PDT 24
Finished Jun 30 05:46:35 PM PDT 24
Peak memory 208552 kb
Host smart-c9030875-9622-4c93-a691-f05c30ae974b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787621904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1787621904
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.705583209
Short name T616
Test name
Test status
Simulation time 423909086 ps
CPU time 2.02 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:30 PM PDT 24
Peak memory 200448 kb
Host smart-7d44b70c-b11b-48ce-af3b-3f86e62c7106
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705583209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
705583209
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.576388112
Short name T613
Test name
Test status
Simulation time 104447535 ps
CPU time 0.94 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 05:46:35 PM PDT 24
Peak memory 200356 kb
Host smart-1482f779-acaa-46e3-b8cf-fcd7264dce13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576388112 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.576388112
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2005184080
Short name T619
Test name
Test status
Simulation time 81406934 ps
CPU time 0.84 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 05:46:34 PM PDT 24
Peak memory 200216 kb
Host smart-0235caea-2724-4ec4-9f5f-2356255f4fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005184080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2005184080
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.505517952
Short name T544
Test name
Test status
Simulation time 110778744 ps
CPU time 1.02 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 05:46:35 PM PDT 24
Peak memory 200228 kb
Host smart-91ed1060-a50d-4da6-a5ca-0ad15cce1600
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505517952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.505517952
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2221830202
Short name T591
Test name
Test status
Simulation time 185699633 ps
CPU time 1.52 seconds
Started Jun 30 05:46:29 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 208608 kb
Host smart-83ec4c6f-4cd9-4573-88d6-74a8fa17f0be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221830202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2221830202
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2013859065
Short name T557
Test name
Test status
Simulation time 479627497 ps
CPU time 1.91 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 05:46:36 PM PDT 24
Peak memory 200404 kb
Host smart-f2e07ac4-baeb-40a4-a66d-188819922ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013859065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2013859065
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.649039027
Short name T563
Test name
Test status
Simulation time 182620460 ps
CPU time 1.82 seconds
Started Jun 30 05:46:29 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 208616 kb
Host smart-a64e7268-1deb-4493-b231-9d6cf99c7c4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649039027 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.649039027
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.315367023
Short name T576
Test name
Test status
Simulation time 70322090 ps
CPU time 0.78 seconds
Started Jun 30 05:46:27 PM PDT 24
Finished Jun 30 05:46:29 PM PDT 24
Peak memory 200164 kb
Host smart-c51d34c5-1610-46fc-9825-2869c7e46250
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315367023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.315367023
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1274494422
Short name T118
Test name
Test status
Simulation time 73117950 ps
CPU time 0.97 seconds
Started Jun 30 05:46:26 PM PDT 24
Finished Jun 30 05:46:27 PM PDT 24
Peak memory 200292 kb
Host smart-a8cebedb-a739-4e9f-bebf-911d27167d38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274494422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1274494422
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3348877534
Short name T132
Test name
Test status
Simulation time 140581190 ps
CPU time 2.01 seconds
Started Jun 30 05:46:26 PM PDT 24
Finished Jun 30 05:46:29 PM PDT 24
Peak memory 208484 kb
Host smart-dfd96151-7b3c-4cd7-bace-2a43af2650ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348877534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3348877534
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.773396203
Short name T102
Test name
Test status
Simulation time 913988783 ps
CPU time 2.92 seconds
Started Jun 30 05:46:28 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 200444 kb
Host smart-ab63d6a9-ae3d-4328-ac97-a990033fb1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773396203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
773396203
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2490103354
Short name T559
Test name
Test status
Simulation time 153027087 ps
CPU time 1.52 seconds
Started Jun 30 05:46:26 PM PDT 24
Finished Jun 30 05:46:28 PM PDT 24
Peak memory 208628 kb
Host smart-4d5dc5f6-3645-40c3-979e-ca59a6ac6d15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490103354 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2490103354
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1777490929
Short name T552
Test name
Test status
Simulation time 90113207 ps
CPU time 0.91 seconds
Started Jun 30 05:46:26 PM PDT 24
Finished Jun 30 05:46:28 PM PDT 24
Peak memory 200216 kb
Host smart-1a39c583-88a7-4712-93b3-9e8a6e0a5fd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777490929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1777490929
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.482057639
Short name T566
Test name
Test status
Simulation time 235534394 ps
CPU time 1.43 seconds
Started Jun 30 05:46:24 PM PDT 24
Finished Jun 30 05:46:26 PM PDT 24
Peak memory 200428 kb
Host smart-6cd24953-ebfe-4b51-9e9b-64b435ef1027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482057639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.482057639
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3054764643
Short name T131
Test name
Test status
Simulation time 143200348 ps
CPU time 2.16 seconds
Started Jun 30 05:46:28 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 211940 kb
Host smart-e7725db1-8213-4e09-bbc1-236ef3470ca2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054764643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3054764643
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2642159757
Short name T369
Test name
Test status
Simulation time 63070812 ps
CPU time 0.74 seconds
Started Jun 30 05:04:28 PM PDT 24
Finished Jun 30 05:04:29 PM PDT 24
Peak memory 199760 kb
Host smart-9593b930-5ebd-45f0-9c34-ebb1b7d8f71b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642159757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2642159757
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1541409077
Short name T213
Test name
Test status
Simulation time 244709274 ps
CPU time 1.1 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:28 PM PDT 24
Peak memory 217376 kb
Host smart-8e830b80-6c32-433c-9a4e-0b296292d618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541409077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1541409077
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.4256043596
Short name T209
Test name
Test status
Simulation time 134653945 ps
CPU time 0.8 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:28 PM PDT 24
Peak memory 199824 kb
Host smart-a54bc1fc-004a-47b6-be30-868b3c873cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256043596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4256043596
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3139850536
Short name T10
Test name
Test status
Simulation time 1872173996 ps
CPU time 6.35 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:33 PM PDT 24
Peak memory 200268 kb
Host smart-9b59b92b-6752-49c5-bde7-019492d01319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139850536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3139850536
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1180666478
Short name T75
Test name
Test status
Simulation time 16519825097 ps
CPU time 29.64 seconds
Started Jun 30 05:04:27 PM PDT 24
Finished Jun 30 05:04:57 PM PDT 24
Peak memory 218116 kb
Host smart-23f5187d-b767-4809-8ea7-bd2783edc0e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180666478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1180666478
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.533847727
Short name T431
Test name
Test status
Simulation time 98154985 ps
CPU time 1.02 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:28 PM PDT 24
Peak memory 199984 kb
Host smart-64f78dba-cc40-499a-ae59-b810165bab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533847727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.533847727
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2828206610
Short name T368
Test name
Test status
Simulation time 189697868 ps
CPU time 1.34 seconds
Started Jun 30 05:04:25 PM PDT 24
Finished Jun 30 05:04:27 PM PDT 24
Peak memory 200116 kb
Host smart-32837923-a6eb-48ab-8ed1-dd3a6e849ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828206610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2828206610
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1104108864
Short name T400
Test name
Test status
Simulation time 12975379916 ps
CPU time 49.13 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:05:16 PM PDT 24
Peak memory 200376 kb
Host smart-61805435-8998-4490-ace5-613d7d246a2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104108864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1104108864
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1087964093
Short name T371
Test name
Test status
Simulation time 457285083 ps
CPU time 2.54 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:29 PM PDT 24
Peak memory 199984 kb
Host smart-7ab0b23d-7285-4251-8d92-b0c9b871e63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087964093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1087964093
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3714574099
Short name T137
Test name
Test status
Simulation time 127457033 ps
CPU time 1.14 seconds
Started Jun 30 05:04:25 PM PDT 24
Finished Jun 30 05:04:27 PM PDT 24
Peak memory 199996 kb
Host smart-937692ee-d564-46ea-b1a5-f01df8e1377b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714574099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3714574099
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4157540841
Short name T491
Test name
Test status
Simulation time 69949538 ps
CPU time 0.75 seconds
Started Jun 30 05:04:34 PM PDT 24
Finished Jun 30 05:04:35 PM PDT 24
Peak memory 199796 kb
Host smart-451dd932-a8f9-426f-8dd3-80e12e0b4f9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157540841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4157540841
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.639787745
Short name T512
Test name
Test status
Simulation time 1231949490 ps
CPU time 5.51 seconds
Started Jun 30 05:04:28 PM PDT 24
Finished Jun 30 05:04:34 PM PDT 24
Peak memory 217580 kb
Host smart-b996c57b-5fc7-4836-8dbb-ca340dc85c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639787745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.639787745
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3208371870
Short name T88
Test name
Test status
Simulation time 270149840 ps
CPU time 1.11 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:04:38 PM PDT 24
Peak memory 217396 kb
Host smart-a15e9d06-859d-4a3a-b72b-cb00d14004c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208371870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3208371870
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2863725486
Short name T408
Test name
Test status
Simulation time 239615085 ps
CPU time 0.99 seconds
Started Jun 30 05:04:30 PM PDT 24
Finished Jun 30 05:04:32 PM PDT 24
Peak memory 199824 kb
Host smart-c291db64-eebd-45c6-9c81-afc9d3aea0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863725486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2863725486
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1331801053
Short name T533
Test name
Test status
Simulation time 1567077702 ps
CPU time 6.4 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:33 PM PDT 24
Peak memory 200268 kb
Host smart-a1febb88-2498-44be-abf4-37a0f5d65728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331801053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1331801053
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2130880229
Short name T79
Test name
Test status
Simulation time 8301855231 ps
CPU time 16.42 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:54 PM PDT 24
Peak memory 217084 kb
Host smart-9c9de773-7e91-46a0-9ee6-bdfc1bcbf412
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130880229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2130880229
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2442297847
Short name T413
Test name
Test status
Simulation time 103031413 ps
CPU time 1.04 seconds
Started Jun 30 05:04:27 PM PDT 24
Finished Jun 30 05:04:29 PM PDT 24
Peak memory 200312 kb
Host smart-eff13a85-aef4-4333-ad6a-469335df17f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442297847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2442297847
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2431657326
Short name T179
Test name
Test status
Simulation time 111662524 ps
CPU time 1.2 seconds
Started Jun 30 05:04:25 PM PDT 24
Finished Jun 30 05:04:26 PM PDT 24
Peak memory 200180 kb
Host smart-c85829c6-07b7-48ea-a24d-df59112e8096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431657326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2431657326
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3720197855
Short name T513
Test name
Test status
Simulation time 2925463851 ps
CPU time 13.51 seconds
Started Jun 30 05:04:34 PM PDT 24
Finished Jun 30 05:04:48 PM PDT 24
Peak memory 210044 kb
Host smart-628fe650-e38e-4802-8a4d-50cfeceed769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720197855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3720197855
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1790156649
Short name T483
Test name
Test status
Simulation time 144457598 ps
CPU time 1.79 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:29 PM PDT 24
Peak memory 200036 kb
Host smart-8a5eb9f7-df0d-4364-8597-e4273cb23bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790156649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1790156649
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3373077174
Short name T274
Test name
Test status
Simulation time 171870223 ps
CPU time 1.15 seconds
Started Jun 30 05:04:25 PM PDT 24
Finished Jun 30 05:04:26 PM PDT 24
Peak memory 200012 kb
Host smart-2e134cc6-1e85-46b5-a354-a9ad4406fec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373077174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3373077174
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.416031334
Short name T234
Test name
Test status
Simulation time 82533632 ps
CPU time 0.9 seconds
Started Jun 30 05:05:02 PM PDT 24
Finished Jun 30 05:05:04 PM PDT 24
Peak memory 199760 kb
Host smart-bc20b1ed-6aff-4391-9849-83d045d19465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416031334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.416031334
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.67040947
Short name T380
Test name
Test status
Simulation time 244083717 ps
CPU time 1.13 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 217672 kb
Host smart-8687b82c-9f22-481b-9297-052148c53171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67040947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.67040947
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3549646697
Short name T434
Test name
Test status
Simulation time 1893083885 ps
CPU time 6.87 seconds
Started Jun 30 05:04:53 PM PDT 24
Finished Jun 30 05:05:01 PM PDT 24
Peak memory 200240 kb
Host smart-14f3308e-7352-476c-acff-b652e06acd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549646697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3549646697
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3320257414
Short name T178
Test name
Test status
Simulation time 158938926 ps
CPU time 1.18 seconds
Started Jun 30 05:04:54 PM PDT 24
Finished Jun 30 05:04:56 PM PDT 24
Peak memory 199996 kb
Host smart-aef113aa-e4d9-4b26-9505-6129bfb4717c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320257414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3320257414
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3008048211
Short name T323
Test name
Test status
Simulation time 201148597 ps
CPU time 1.39 seconds
Started Jun 30 05:04:58 PM PDT 24
Finished Jun 30 05:05:00 PM PDT 24
Peak memory 200196 kb
Host smart-1876bc5a-20c4-481b-8f4b-359738354743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008048211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3008048211
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2089857694
Short name T411
Test name
Test status
Simulation time 11835616359 ps
CPU time 40.8 seconds
Started Jun 30 05:05:03 PM PDT 24
Finished Jun 30 05:05:45 PM PDT 24
Peak memory 208504 kb
Host smart-94745d5c-c24e-4763-83bc-220d4953f21c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089857694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2089857694
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3368916500
Short name T226
Test name
Test status
Simulation time 149372734 ps
CPU time 1.77 seconds
Started Jun 30 05:04:54 PM PDT 24
Finished Jun 30 05:04:56 PM PDT 24
Peak memory 199956 kb
Host smart-ab6e9760-84db-4a8e-a400-3a6d9a6923d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368916500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3368916500
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.497334041
Short name T142
Test name
Test status
Simulation time 116696864 ps
CPU time 0.86 seconds
Started Jun 30 05:04:51 PM PDT 24
Finished Jun 30 05:04:53 PM PDT 24
Peak memory 199792 kb
Host smart-18b21701-cb66-4a86-97a0-f4fb9008a286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497334041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.497334041
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3124509963
Short name T141
Test name
Test status
Simulation time 62408516 ps
CPU time 0.77 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:02 PM PDT 24
Peak memory 199820 kb
Host smart-2de5d62f-61fd-4d7d-add0-d239b1dfe484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124509963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3124509963
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.614853796
Short name T27
Test name
Test status
Simulation time 2365754304 ps
CPU time 8.18 seconds
Started Jun 30 05:05:03 PM PDT 24
Finished Jun 30 05:05:12 PM PDT 24
Peak memory 221472 kb
Host smart-33dbadeb-26a7-4e70-a63b-291c222ee6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614853796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.614853796
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.8695251
Short name T346
Test name
Test status
Simulation time 244286002 ps
CPU time 1.15 seconds
Started Jun 30 05:05:03 PM PDT 24
Finished Jun 30 05:05:05 PM PDT 24
Peak memory 217288 kb
Host smart-9acc840f-f7f5-41cc-998b-cf7defd63e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8695251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.8695251
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.74930055
Short name T392
Test name
Test status
Simulation time 138484249 ps
CPU time 0.88 seconds
Started Jun 30 05:05:01 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 199820 kb
Host smart-2fca9e14-241d-4513-8736-8143fcdf93cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74930055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.74930055
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4128904130
Short name T133
Test name
Test status
Simulation time 1996415833 ps
CPU time 7.72 seconds
Started Jun 30 05:05:01 PM PDT 24
Finished Jun 30 05:05:10 PM PDT 24
Peak memory 200264 kb
Host smart-7a97b646-889e-45b7-94f6-b472a5aa3fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128904130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4128904130
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2638300495
Short name T5
Test name
Test status
Simulation time 156955707 ps
CPU time 1.22 seconds
Started Jun 30 05:04:59 PM PDT 24
Finished Jun 30 05:05:01 PM PDT 24
Peak memory 199996 kb
Host smart-b11f23cd-3c8c-4061-b8c6-e7bdafeecf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638300495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2638300495
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.861167845
Short name T340
Test name
Test status
Simulation time 117320341 ps
CPU time 1.21 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:02 PM PDT 24
Peak memory 200200 kb
Host smart-00344e87-1bdd-4000-b78b-68d95a458d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861167845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.861167845
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1134034497
Short name T421
Test name
Test status
Simulation time 4382153567 ps
CPU time 19.82 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:21 PM PDT 24
Peak memory 208520 kb
Host smart-6307881a-a227-40e2-9e49-67712e6fe506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134034497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1134034497
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.300058671
Short name T520
Test name
Test status
Simulation time 132319222 ps
CPU time 1.65 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 208196 kb
Host smart-5b023bb1-28f6-464c-b6a5-9ee39804d777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300058671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.300058671
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2690024013
Short name T357
Test name
Test status
Simulation time 93949322 ps
CPU time 0.88 seconds
Started Jun 30 05:04:59 PM PDT 24
Finished Jun 30 05:05:01 PM PDT 24
Peak memory 200008 kb
Host smart-38b753f4-d314-4e1f-97be-3e82b3a05437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690024013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2690024013
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3978663234
Short name T322
Test name
Test status
Simulation time 202189883 ps
CPU time 1.06 seconds
Started Jun 30 05:05:03 PM PDT 24
Finished Jun 30 05:05:05 PM PDT 24
Peak memory 199804 kb
Host smart-73088299-84ee-43dc-8c4a-5604f0ace907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978663234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3978663234
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3251510855
Short name T484
Test name
Test status
Simulation time 1220117982 ps
CPU time 6.07 seconds
Started Jun 30 05:05:01 PM PDT 24
Finished Jun 30 05:05:08 PM PDT 24
Peak memory 221476 kb
Host smart-414deacf-a4be-4564-928e-587af1160d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251510855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3251510855
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.82864730
Short name T514
Test name
Test status
Simulation time 244238411 ps
CPU time 1.08 seconds
Started Jun 30 05:05:01 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 217380 kb
Host smart-b3d7be10-32d4-40ac-bbfe-08750ae277e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82864730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.82864730
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.408096043
Short name T242
Test name
Test status
Simulation time 90942007 ps
CPU time 0.77 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 199816 kb
Host smart-d00a676a-a47b-4401-b241-d48ea4b4b09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408096043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.408096043
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3445048795
Short name T396
Test name
Test status
Simulation time 1309800605 ps
CPU time 5.06 seconds
Started Jun 30 05:04:59 PM PDT 24
Finished Jun 30 05:05:04 PM PDT 24
Peak memory 200312 kb
Host smart-62ed5cd4-6978-454b-b469-613ec5a06761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445048795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3445048795
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3791163369
Short name T495
Test name
Test status
Simulation time 168287063 ps
CPU time 1.24 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 199988 kb
Host smart-634186a9-b39a-46c0-a233-111d475bd8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791163369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3791163369
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1445369293
Short name T529
Test name
Test status
Simulation time 117486705 ps
CPU time 1.21 seconds
Started Jun 30 05:05:01 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 200128 kb
Host smart-8c11eb81-f1f1-4378-b800-abd194f7ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445369293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1445369293
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.293324388
Short name T241
Test name
Test status
Simulation time 6017572345 ps
CPU time 26.15 seconds
Started Jun 30 05:05:01 PM PDT 24
Finished Jun 30 05:05:29 PM PDT 24
Peak memory 200332 kb
Host smart-e0eb92d5-93e1-40e8-b116-173d6d28ac01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293324388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.293324388
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.4289622846
Short name T91
Test name
Test status
Simulation time 353993156 ps
CPU time 2.35 seconds
Started Jun 30 05:05:03 PM PDT 24
Finished Jun 30 05:05:07 PM PDT 24
Peak memory 199924 kb
Host smart-081ff020-2111-4cba-9882-220aa9b6a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289622846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.4289622846
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3524796197
Short name T139
Test name
Test status
Simulation time 103693805 ps
CPU time 0.94 seconds
Started Jun 30 05:05:01 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 199936 kb
Host smart-47b250ab-dde7-407f-8793-df196b28330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524796197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3524796197
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1184949732
Short name T164
Test name
Test status
Simulation time 67163431 ps
CPU time 0.82 seconds
Started Jun 30 05:05:03 PM PDT 24
Finished Jun 30 05:05:05 PM PDT 24
Peak memory 199712 kb
Host smart-7fbc3a33-9dea-4a4e-b89a-c1fb0090db7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184949732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1184949732
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.4040635223
Short name T248
Test name
Test status
Simulation time 1211668054 ps
CPU time 5.47 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:06 PM PDT 24
Peak memory 217156 kb
Host smart-bb505f29-945d-42af-96d9-0d7f9eeb17b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040635223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.4040635223
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.373309058
Short name T300
Test name
Test status
Simulation time 244648855 ps
CPU time 1.03 seconds
Started Jun 30 05:05:03 PM PDT 24
Finished Jun 30 05:05:06 PM PDT 24
Peak memory 217420 kb
Host smart-9675b5a8-b6de-4718-9874-7ec2bfd740d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373309058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.373309058
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1256371076
Short name T390
Test name
Test status
Simulation time 104111292 ps
CPU time 0.79 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:01 PM PDT 24
Peak memory 199828 kb
Host smart-8d8c9a26-e4a5-4175-98cc-a01ba10d77d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256371076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1256371076
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1756531762
Short name T456
Test name
Test status
Simulation time 1237000462 ps
CPU time 4.98 seconds
Started Jun 30 05:04:59 PM PDT 24
Finished Jun 30 05:05:05 PM PDT 24
Peak memory 200260 kb
Host smart-4c11de21-2a79-4ab8-b9db-bbcc07d79e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756531762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1756531762
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1814315991
Short name T163
Test name
Test status
Simulation time 116164903 ps
CPU time 1.13 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 200008 kb
Host smart-54ea65ae-7f67-4f2a-b2a4-3942a2630e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814315991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1814315991
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.162489365
Short name T171
Test name
Test status
Simulation time 117872041 ps
CPU time 1.2 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:02 PM PDT 24
Peak memory 200192 kb
Host smart-3a008822-aac2-4ea3-ab4e-6923a28e7b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162489365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.162489365
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2928217988
Short name T538
Test name
Test status
Simulation time 1486288988 ps
CPU time 5.74 seconds
Started Jun 30 05:05:00 PM PDT 24
Finished Jun 30 05:05:07 PM PDT 24
Peak memory 200176 kb
Host smart-3ef5d8f9-9ff2-49cb-9237-5674a4b5ae40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928217988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2928217988
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.516042656
Short name T157
Test name
Test status
Simulation time 134365723 ps
CPU time 1.7 seconds
Started Jun 30 05:05:03 PM PDT 24
Finished Jun 30 05:05:06 PM PDT 24
Peak memory 200012 kb
Host smart-4b541f12-30d4-42e1-9aaf-49447901b50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516042656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.516042656
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2665988808
Short name T194
Test name
Test status
Simulation time 237315760 ps
CPU time 1.42 seconds
Started Jun 30 05:05:01 PM PDT 24
Finished Jun 30 05:05:04 PM PDT 24
Peak memory 200200 kb
Host smart-b2dffe33-437a-4f6e-8c27-e07b086d1c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665988808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2665988808
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2682617368
Short name T270
Test name
Test status
Simulation time 94249035 ps
CPU time 0.83 seconds
Started Jun 30 05:05:07 PM PDT 24
Finished Jun 30 05:05:09 PM PDT 24
Peak memory 199792 kb
Host smart-666298e1-fc3e-41bd-9831-021497425d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682617368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2682617368
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.27385122
Short name T25
Test name
Test status
Simulation time 1881804592 ps
CPU time 7.33 seconds
Started Jun 30 05:05:08 PM PDT 24
Finished Jun 30 05:05:16 PM PDT 24
Peak memory 217552 kb
Host smart-5d99709f-d8b4-46e2-b523-180dc9827204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27385122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.27385122
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3852349304
Short name T448
Test name
Test status
Simulation time 243828128 ps
CPU time 1.11 seconds
Started Jun 30 05:05:14 PM PDT 24
Finished Jun 30 05:05:16 PM PDT 24
Peak memory 217312 kb
Host smart-45bdf4f1-2082-4524-afd4-9ba9054a3e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852349304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3852349304
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2637990373
Short name T17
Test name
Test status
Simulation time 119908594 ps
CPU time 0.81 seconds
Started Jun 30 05:05:01 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 199828 kb
Host smart-b8ddb8f5-2206-4fea-8851-0df496e07cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637990373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2637990373
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1434838476
Short name T134
Test name
Test status
Simulation time 1940512575 ps
CPU time 7.16 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:24 PM PDT 24
Peak memory 200260 kb
Host smart-ba694b56-168f-4271-9794-cf8f97fdbe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434838476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1434838476
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3451168262
Short name T539
Test name
Test status
Simulation time 172699545 ps
CPU time 1.29 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:18 PM PDT 24
Peak memory 200300 kb
Host smart-6b28707b-b0ba-457c-8745-fc8cecc61493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451168262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3451168262
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1027375431
Short name T314
Test name
Test status
Simulation time 130491032 ps
CPU time 1.18 seconds
Started Jun 30 05:05:01 PM PDT 24
Finished Jun 30 05:05:04 PM PDT 24
Peak memory 200196 kb
Host smart-ffdc19b8-7413-4699-b986-4f3d426c1327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027375431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1027375431
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3356765329
Short name T114
Test name
Test status
Simulation time 5039121696 ps
CPU time 18.16 seconds
Started Jun 30 05:05:13 PM PDT 24
Finished Jun 30 05:05:32 PM PDT 24
Peak memory 200256 kb
Host smart-44079f8b-4c18-4170-ab28-de66ccf58889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356765329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3356765329
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1101589363
Short name T286
Test name
Test status
Simulation time 341402501 ps
CPU time 2.38 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:20 PM PDT 24
Peak memory 199956 kb
Host smart-6fee85d0-7dc1-4a8a-8c6f-d3619e324beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101589363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1101589363
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1643812403
Short name T90
Test name
Test status
Simulation time 128370078 ps
CPU time 1.06 seconds
Started Jun 30 05:05:12 PM PDT 24
Finished Jun 30 05:05:13 PM PDT 24
Peak memory 200020 kb
Host smart-24b0e181-6314-40e2-bae6-18d90cc0619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643812403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1643812403
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3851368754
Short name T86
Test name
Test status
Simulation time 82522035 ps
CPU time 0.81 seconds
Started Jun 30 05:05:14 PM PDT 24
Finished Jun 30 05:05:16 PM PDT 24
Peak memory 199796 kb
Host smart-557e63bc-a1e7-41f1-8548-d0d713c8911b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851368754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3851368754
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2318765927
Short name T54
Test name
Test status
Simulation time 1222627682 ps
CPU time 6.24 seconds
Started Jun 30 05:05:10 PM PDT 24
Finished Jun 30 05:05:16 PM PDT 24
Peak memory 216868 kb
Host smart-8a83eba1-ba82-48e5-81c8-3abc17878b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318765927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2318765927
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.66644481
Short name T58
Test name
Test status
Simulation time 244745494 ps
CPU time 1.06 seconds
Started Jun 30 05:05:13 PM PDT 24
Finished Jun 30 05:05:15 PM PDT 24
Peak memory 217336 kb
Host smart-64026e9e-6ab7-41a8-bdb1-4945715ddc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66644481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.66644481
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1052635145
Short name T225
Test name
Test status
Simulation time 150037835 ps
CPU time 0.81 seconds
Started Jun 30 05:05:07 PM PDT 24
Finished Jun 30 05:05:09 PM PDT 24
Peak memory 199840 kb
Host smart-0574d84e-9248-48bc-9cf5-41fc8f2c6b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052635145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1052635145
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2675014498
Short name T298
Test name
Test status
Simulation time 824865684 ps
CPU time 4.25 seconds
Started Jun 30 05:05:10 PM PDT 24
Finished Jun 30 05:05:15 PM PDT 24
Peak memory 200248 kb
Host smart-0375ddac-dba3-43a4-a983-4180c279b5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675014498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2675014498
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2873832462
Short name T493
Test name
Test status
Simulation time 179992187 ps
CPU time 1.22 seconds
Started Jun 30 05:05:12 PM PDT 24
Finished Jun 30 05:05:14 PM PDT 24
Peak memory 200012 kb
Host smart-408490eb-f10a-42e5-8b74-79d79faff102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873832462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2873832462
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2395754053
Short name T338
Test name
Test status
Simulation time 117066861 ps
CPU time 1.19 seconds
Started Jun 30 05:05:14 PM PDT 24
Finished Jun 30 05:05:16 PM PDT 24
Peak memory 200248 kb
Host smart-ab51e31c-d032-45e2-a940-fa6deb552cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395754053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2395754053
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2790983506
Short name T446
Test name
Test status
Simulation time 8207254787 ps
CPU time 31.44 seconds
Started Jun 30 05:05:12 PM PDT 24
Finished Jun 30 05:05:44 PM PDT 24
Peak memory 200404 kb
Host smart-5b6597e5-40d2-472e-9b6a-ffb529202e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790983506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2790983506
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1617438474
Short name T473
Test name
Test status
Simulation time 250708638 ps
CPU time 1.76 seconds
Started Jun 30 05:05:14 PM PDT 24
Finished Jun 30 05:05:16 PM PDT 24
Peak memory 199996 kb
Host smart-f8077c58-70c0-4362-949f-d09690aceeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617438474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1617438474
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2667931912
Short name T229
Test name
Test status
Simulation time 152333374 ps
CPU time 1.05 seconds
Started Jun 30 05:05:11 PM PDT 24
Finished Jun 30 05:05:13 PM PDT 24
Peak memory 199964 kb
Host smart-0c78cfcd-ca41-45b1-81b0-185ebe0cee44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667931912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2667931912
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.415354678
Short name T45
Test name
Test status
Simulation time 1889170338 ps
CPU time 8.25 seconds
Started Jun 30 05:05:08 PM PDT 24
Finished Jun 30 05:05:17 PM PDT 24
Peak memory 217592 kb
Host smart-a911c1d7-ef24-4a9b-a41b-27ecf99d18a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415354678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.415354678
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1403118953
Short name T73
Test name
Test status
Simulation time 246281193 ps
CPU time 1.05 seconds
Started Jun 30 05:05:10 PM PDT 24
Finished Jun 30 05:05:12 PM PDT 24
Peak memory 217344 kb
Host smart-172ee16e-ffc5-4fd7-b2f4-b543ba4f2494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403118953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1403118953
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3517527949
Short name T445
Test name
Test status
Simulation time 138235380 ps
CPU time 0.82 seconds
Started Jun 30 05:05:14 PM PDT 24
Finished Jun 30 05:05:16 PM PDT 24
Peak memory 199736 kb
Host smart-d9cd616a-0499-4fbb-8fbe-a3fd5efbe73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517527949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3517527949
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2882847271
Short name T106
Test name
Test status
Simulation time 1158453035 ps
CPU time 5.22 seconds
Started Jun 30 05:05:10 PM PDT 24
Finished Jun 30 05:05:16 PM PDT 24
Peak memory 200280 kb
Host smart-69f9aee8-c2a6-40af-883b-d8cb790cac72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882847271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2882847271
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2701607090
Short name T447
Test name
Test status
Simulation time 107582830 ps
CPU time 1.04 seconds
Started Jun 30 05:05:14 PM PDT 24
Finished Jun 30 05:05:15 PM PDT 24
Peak memory 199996 kb
Host smart-07151ea3-efd0-404d-98f8-da0dbe95c3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701607090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2701607090
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2136210957
Short name T507
Test name
Test status
Simulation time 196570006 ps
CPU time 1.48 seconds
Started Jun 30 05:05:11 PM PDT 24
Finished Jun 30 05:05:13 PM PDT 24
Peak memory 200180 kb
Host smart-ead6fcc0-54aa-4195-990c-165e6d874bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136210957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2136210957
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3622241284
Short name T487
Test name
Test status
Simulation time 4459492462 ps
CPU time 19.11 seconds
Started Jun 30 05:05:08 PM PDT 24
Finished Jun 30 05:05:28 PM PDT 24
Peak memory 208512 kb
Host smart-96674fc8-dda3-479a-a7de-35c6776d2615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622241284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3622241284
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2320255020
Short name T219
Test name
Test status
Simulation time 339411645 ps
CPU time 2.27 seconds
Started Jun 30 05:05:07 PM PDT 24
Finished Jun 30 05:05:10 PM PDT 24
Peak memory 199960 kb
Host smart-f50e81b2-b288-4759-a920-eddbf714bd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320255020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2320255020
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.4007205736
Short name T39
Test name
Test status
Simulation time 76203430 ps
CPU time 0.87 seconds
Started Jun 30 05:05:10 PM PDT 24
Finished Jun 30 05:05:12 PM PDT 24
Peak memory 199920 kb
Host smart-4904fb0f-45ce-423c-a8a5-579514904f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007205736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.4007205736
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1635483279
Short name T296
Test name
Test status
Simulation time 81040491 ps
CPU time 0.82 seconds
Started Jun 30 05:05:17 PM PDT 24
Finished Jun 30 05:05:19 PM PDT 24
Peak memory 199816 kb
Host smart-c2c07920-6a2a-4461-b2ad-48b384c86b42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635483279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1635483279
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.496743979
Short name T359
Test name
Test status
Simulation time 1228323171 ps
CPU time 5.55 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:31 PM PDT 24
Peak memory 221448 kb
Host smart-0c7def55-f523-499b-b823-ecc74e9919d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496743979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.496743979
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.641730796
Short name T308
Test name
Test status
Simulation time 243900418 ps
CPU time 1.12 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:19 PM PDT 24
Peak memory 217296 kb
Host smart-42203b77-bde6-436c-9618-f3072c4243c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641730796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.641730796
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2783245945
Short name T201
Test name
Test status
Simulation time 203782059 ps
CPU time 0.91 seconds
Started Jun 30 05:05:07 PM PDT 24
Finished Jun 30 05:05:09 PM PDT 24
Peak memory 199804 kb
Host smart-62653539-107d-4c96-8c4c-4fdb543ea2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783245945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2783245945
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2247441261
Short name T432
Test name
Test status
Simulation time 693861878 ps
CPU time 3.67 seconds
Started Jun 30 05:05:07 PM PDT 24
Finished Jun 30 05:05:11 PM PDT 24
Peak memory 200232 kb
Host smart-b0c6fdb6-0576-4aa5-951c-1fc9d8fffcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247441261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2247441261
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.453691004
Short name T466
Test name
Test status
Simulation time 97774254 ps
CPU time 0.96 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:26 PM PDT 24
Peak memory 199896 kb
Host smart-81b685ab-3853-4b08-ad66-198fd11a95c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453691004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.453691004
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.899511961
Short name T94
Test name
Test status
Simulation time 226189686 ps
CPU time 1.55 seconds
Started Jun 30 05:05:14 PM PDT 24
Finished Jun 30 05:05:17 PM PDT 24
Peak memory 200112 kb
Host smart-3c19c2c7-4b5a-40eb-ba4c-7895c5b1f5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899511961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.899511961
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2623378215
Short name T399
Test name
Test status
Simulation time 1488037124 ps
CPU time 7.19 seconds
Started Jun 30 05:05:14 PM PDT 24
Finished Jun 30 05:05:22 PM PDT 24
Peak memory 200268 kb
Host smart-e0e89d42-0a22-480f-b30a-c02cf0d91dd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623378215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2623378215
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2550724742
Short name T203
Test name
Test status
Simulation time 265109552 ps
CPU time 1.91 seconds
Started Jun 30 05:05:17 PM PDT 24
Finished Jun 30 05:05:20 PM PDT 24
Peak memory 199960 kb
Host smart-3fdbedc3-0df0-4390-8a59-d93187ec6475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550724742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2550724742
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3071479822
Short name T283
Test name
Test status
Simulation time 211277365 ps
CPU time 1.46 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:19 PM PDT 24
Peak memory 200016 kb
Host smart-9375929e-63cb-44e5-87eb-2e2a02a5bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071479822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3071479822
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2513929420
Short name T170
Test name
Test status
Simulation time 73863047 ps
CPU time 0.77 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:18 PM PDT 24
Peak memory 199788 kb
Host smart-b14bb67d-186b-4834-9584-b8aa1bd3a047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513929420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2513929420
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3835875655
Short name T439
Test name
Test status
Simulation time 2371431212 ps
CPU time 8.46 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:25 PM PDT 24
Peak memory 221612 kb
Host smart-ee3da6ba-4161-46fc-a6c8-2e4534bdeb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835875655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3835875655
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.964643269
Short name T531
Test name
Test status
Simulation time 244147909 ps
CPU time 1.04 seconds
Started Jun 30 05:05:13 PM PDT 24
Finished Jun 30 05:05:14 PM PDT 24
Peak memory 217348 kb
Host smart-59703233-57a7-44db-b2ca-bbbc531f9418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964643269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.964643269
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.450232108
Short name T16
Test name
Test status
Simulation time 169357542 ps
CPU time 0.89 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:19 PM PDT 24
Peak memory 199824 kb
Host smart-6b2e0c54-b693-4c6a-83f8-cf51a48c1a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450232108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.450232108
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2854910495
Short name T402
Test name
Test status
Simulation time 793862627 ps
CPU time 4.4 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:22 PM PDT 24
Peak memory 200264 kb
Host smart-8544abd7-f4c8-447a-9c88-7b64ff9e0dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854910495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2854910495
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2438365275
Short name T393
Test name
Test status
Simulation time 112157953 ps
CPU time 1.08 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:17 PM PDT 24
Peak memory 200016 kb
Host smart-1bb10ad1-5b96-4fe2-a907-60cd689df903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438365275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2438365275
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1997004164
Short name T261
Test name
Test status
Simulation time 224995131 ps
CPU time 1.42 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:18 PM PDT 24
Peak memory 200108 kb
Host smart-ef1b87e4-d58a-47cd-908f-8065dc554f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997004164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1997004164
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.668964394
Short name T1
Test name
Test status
Simulation time 150570235 ps
CPU time 1.91 seconds
Started Jun 30 05:05:18 PM PDT 24
Finished Jun 30 05:05:20 PM PDT 24
Peak memory 199976 kb
Host smart-23c97b03-32e8-4ab0-882f-e4c13f4df7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668964394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.668964394
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1400597804
Short name T37
Test name
Test status
Simulation time 116828986 ps
CPU time 0.97 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:17 PM PDT 24
Peak memory 200000 kb
Host smart-9bcf08d9-5a0f-40db-9f98-5fc82af590ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400597804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1400597804
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2240570416
Short name T471
Test name
Test status
Simulation time 64573618 ps
CPU time 0.77 seconds
Started Jun 30 05:05:13 PM PDT 24
Finished Jun 30 05:05:14 PM PDT 24
Peak memory 199804 kb
Host smart-f2d442b1-352e-4fd1-b7fe-65c7cb5e2183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240570416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2240570416
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3012439622
Short name T53
Test name
Test status
Simulation time 1229710663 ps
CPU time 5.87 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:23 PM PDT 24
Peak memory 217356 kb
Host smart-e686dc18-c5a7-445f-92a2-0a6de80bff42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012439622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3012439622
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1336150271
Short name T524
Test name
Test status
Simulation time 245245936 ps
CPU time 1.02 seconds
Started Jun 30 05:05:22 PM PDT 24
Finished Jun 30 05:05:25 PM PDT 24
Peak memory 217192 kb
Host smart-b890f8c7-b028-4a26-8f11-be410c3a2df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336150271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1336150271
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1996134509
Short name T442
Test name
Test status
Simulation time 199148278 ps
CPU time 0.92 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:18 PM PDT 24
Peak memory 199828 kb
Host smart-ef687722-f8e0-4e6c-9039-e804f7b66441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996134509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1996134509
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2335187906
Short name T363
Test name
Test status
Simulation time 1230247668 ps
CPU time 5.18 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:21 PM PDT 24
Peak memory 200256 kb
Host smart-9f55a290-2ff4-4fc4-b594-415261c23f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335187906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2335187906
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.4278681499
Short name T521
Test name
Test status
Simulation time 148984266 ps
CPU time 1.1 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:18 PM PDT 24
Peak memory 199980 kb
Host smart-e639595a-ab82-4db1-97b4-c1710efce4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278681499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.4278681499
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3696262798
Short name T333
Test name
Test status
Simulation time 120947062 ps
CPU time 1.2 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:18 PM PDT 24
Peak memory 200204 kb
Host smart-6a7f2ddf-75d4-4ddc-953f-8fb55c1bb901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696262798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3696262798
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.4201890884
Short name T527
Test name
Test status
Simulation time 3375561778 ps
CPU time 12.27 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:30 PM PDT 24
Peak memory 200332 kb
Host smart-313dbfc6-31be-47e0-805b-aa215d8af5c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201890884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.4201890884
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2440317219
Short name T468
Test name
Test status
Simulation time 414204611 ps
CPU time 2.29 seconds
Started Jun 30 05:05:14 PM PDT 24
Finished Jun 30 05:05:18 PM PDT 24
Peak memory 208144 kb
Host smart-d805c229-085c-445d-8952-7b22ba493eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440317219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2440317219
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4153338236
Short name T269
Test name
Test status
Simulation time 146867732 ps
CPU time 1.15 seconds
Started Jun 30 05:05:13 PM PDT 24
Finished Jun 30 05:05:14 PM PDT 24
Peak memory 200024 kb
Host smart-31dfe661-baf9-4f57-8d19-05667b356990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153338236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4153338236
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.4181907073
Short name T395
Test name
Test status
Simulation time 68577896 ps
CPU time 0.74 seconds
Started Jun 30 05:04:33 PM PDT 24
Finished Jun 30 05:04:34 PM PDT 24
Peak memory 199808 kb
Host smart-d055a606-15a7-41b8-bca5-3f1685d7dd11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181907073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4181907073
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.679647124
Short name T461
Test name
Test status
Simulation time 1892636938 ps
CPU time 7.72 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:04:44 PM PDT 24
Peak memory 221452 kb
Host smart-0e6f9064-e452-449b-bb65-a329c62ef2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679647124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.679647124
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1119957343
Short name T350
Test name
Test status
Simulation time 243650872 ps
CPU time 1.05 seconds
Started Jun 30 05:04:34 PM PDT 24
Finished Jun 30 05:04:36 PM PDT 24
Peak memory 217360 kb
Host smart-77c3be47-644f-4e77-98b4-383361ef9db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119957343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1119957343
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1799621639
Short name T303
Test name
Test status
Simulation time 186415842 ps
CPU time 0.94 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:04:37 PM PDT 24
Peak memory 199756 kb
Host smart-73340cb5-ee5a-4008-be40-330033c21358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799621639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1799621639
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2762764428
Short name T156
Test name
Test status
Simulation time 1391033427 ps
CPU time 6.38 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:44 PM PDT 24
Peak memory 200256 kb
Host smart-3f749489-842b-4220-a736-6ae753684056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762764428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2762764428
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1190976227
Short name T361
Test name
Test status
Simulation time 155608411 ps
CPU time 1.12 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:38 PM PDT 24
Peak memory 200016 kb
Host smart-784d0f69-c53e-4c91-bf20-7c2c5d14c5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190976227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1190976227
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1233939760
Short name T277
Test name
Test status
Simulation time 193706338 ps
CPU time 1.29 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:38 PM PDT 24
Peak memory 200204 kb
Host smart-7b720af5-bd7b-4c62-abac-3ffb3ce8b274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233939760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1233939760
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.648154436
Short name T410
Test name
Test status
Simulation time 4796661146 ps
CPU time 22.22 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:59 PM PDT 24
Peak memory 208524 kb
Host smart-e3c62d9c-4459-449f-8e0a-82f78a21c783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648154436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.648154436
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.924244095
Short name T273
Test name
Test status
Simulation time 293571385 ps
CPU time 1.98 seconds
Started Jun 30 05:04:34 PM PDT 24
Finished Jun 30 05:04:36 PM PDT 24
Peak memory 208128 kb
Host smart-790f1f95-709a-4510-97c4-25369d69f9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924244095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.924244095
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1038724848
Short name T55
Test name
Test status
Simulation time 92023835 ps
CPU time 0.91 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:38 PM PDT 24
Peak memory 199964 kb
Host smart-d77d4740-cba0-440c-84df-b77adb7cf961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038724848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1038724848
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.4120283606
Short name T310
Test name
Test status
Simulation time 70189854 ps
CPU time 0.79 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:26 PM PDT 24
Peak memory 199804 kb
Host smart-3f139e2d-3245-4c88-bfe1-908e3b55420c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120283606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.4120283606
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2433917649
Short name T62
Test name
Test status
Simulation time 1226706052 ps
CPU time 5.46 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:30 PM PDT 24
Peak memory 221492 kb
Host smart-338d60a5-7c57-4e25-896e-65244d307da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433917649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2433917649
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3528867590
Short name T453
Test name
Test status
Simulation time 244321403 ps
CPU time 1.1 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:26 PM PDT 24
Peak memory 217364 kb
Host smart-e35f3182-fa93-4926-83c1-4c63b9e6e578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528867590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3528867590
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1547440732
Short name T339
Test name
Test status
Simulation time 87040538 ps
CPU time 0.74 seconds
Started Jun 30 05:05:22 PM PDT 24
Finished Jun 30 05:05:23 PM PDT 24
Peak memory 199628 kb
Host smart-cec286ec-4452-41fe-add0-847f573ac596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547440732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1547440732
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2277904592
Short name T112
Test name
Test status
Simulation time 997505195 ps
CPU time 4.79 seconds
Started Jun 30 05:05:22 PM PDT 24
Finished Jun 30 05:05:28 PM PDT 24
Peak memory 200084 kb
Host smart-0adb12cd-6f44-4741-b475-72af67418211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277904592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2277904592
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4077725381
Short name T161
Test name
Test status
Simulation time 184995550 ps
CPU time 1.23 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:18 PM PDT 24
Peak memory 200028 kb
Host smart-60814a5a-07ad-41e4-aa4c-aabaeed2dec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077725381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4077725381
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2870801384
Short name T525
Test name
Test status
Simulation time 200244752 ps
CPU time 1.38 seconds
Started Jun 30 05:05:15 PM PDT 24
Finished Jun 30 05:05:18 PM PDT 24
Peak memory 200180 kb
Host smart-f2f9af61-0640-49a7-b965-9c6320b4b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870801384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2870801384
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.906901078
Short name T515
Test name
Test status
Simulation time 15437530263 ps
CPU time 50.64 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:06:15 PM PDT 24
Peak memory 208516 kb
Host smart-9b2416a0-3187-4a59-b3cf-b403359025c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906901078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.906901078
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.805288264
Short name T187
Test name
Test status
Simulation time 142663474 ps
CPU time 1.88 seconds
Started Jun 30 05:05:16 PM PDT 24
Finished Jun 30 05:05:19 PM PDT 24
Peak memory 200032 kb
Host smart-3d9f6245-fee2-4ff1-b89c-b5200eb26edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805288264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.805288264
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1174289106
Short name T143
Test name
Test status
Simulation time 87120710 ps
CPU time 0.85 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:26 PM PDT 24
Peak memory 199788 kb
Host smart-baa32183-3570-4e4f-9ef3-e96a4627e63c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174289106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1174289106
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1570384164
Short name T327
Test name
Test status
Simulation time 1227382303 ps
CPU time 5.75 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:31 PM PDT 24
Peak memory 217340 kb
Host smart-3a40ffe9-bb13-470a-af76-3493f696bc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570384164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1570384164
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2606636716
Short name T166
Test name
Test status
Simulation time 248249076 ps
CPU time 1.07 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:25 PM PDT 24
Peak memory 217352 kb
Host smart-3e090e8b-dd12-46de-8d3e-2709aa93ddb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606636716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2606636716
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1424159030
Short name T379
Test name
Test status
Simulation time 154319175 ps
CPU time 0.84 seconds
Started Jun 30 05:05:22 PM PDT 24
Finished Jun 30 05:05:24 PM PDT 24
Peak memory 199800 kb
Host smart-57de21f1-80d6-4c21-b4bb-e402d3138a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424159030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1424159030
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.400482177
Short name T176
Test name
Test status
Simulation time 1551452361 ps
CPU time 6.2 seconds
Started Jun 30 05:05:22 PM PDT 24
Finished Jun 30 05:05:28 PM PDT 24
Peak memory 200288 kb
Host smart-255caa9b-68a5-40ab-b040-d47fcdd5fa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400482177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.400482177
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.4059660914
Short name T38
Test name
Test status
Simulation time 103083222 ps
CPU time 1.01 seconds
Started Jun 30 05:05:22 PM PDT 24
Finished Jun 30 05:05:25 PM PDT 24
Peak memory 199992 kb
Host smart-55f2a0c3-5c35-4965-a446-9ceb36fec9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059660914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.4059660914
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2662417292
Short name T420
Test name
Test status
Simulation time 113689457 ps
CPU time 1.22 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:26 PM PDT 24
Peak memory 200200 kb
Host smart-2cac42ef-a97b-4393-8909-9a9e74d4f584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662417292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2662417292
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.549220356
Short name T383
Test name
Test status
Simulation time 252651141 ps
CPU time 1.59 seconds
Started Jun 30 05:05:22 PM PDT 24
Finished Jun 30 05:05:25 PM PDT 24
Peak memory 199980 kb
Host smart-cc8dd03a-3dd4-4760-b65d-bc54839c0650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549220356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.549220356
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3967005378
Short name T426
Test name
Test status
Simulation time 135332215 ps
CPU time 1.74 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:26 PM PDT 24
Peak memory 200008 kb
Host smart-66c9f847-1c89-4074-a209-c412c5816028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967005378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3967005378
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.628612238
Short name T476
Test name
Test status
Simulation time 179773965 ps
CPU time 1.26 seconds
Started Jun 30 05:05:24 PM PDT 24
Finished Jun 30 05:05:27 PM PDT 24
Peak memory 200252 kb
Host smart-83b3b37b-c27a-4644-bafc-6160727c0087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628612238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.628612238
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3210490737
Short name T256
Test name
Test status
Simulation time 79575486 ps
CPU time 0.82 seconds
Started Jun 30 05:05:22 PM PDT 24
Finished Jun 30 05:05:24 PM PDT 24
Peak memory 199808 kb
Host smart-c9fa9060-9557-4dd4-9a0d-b34191a3ac5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210490737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3210490737
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.509082969
Short name T336
Test name
Test status
Simulation time 243947834 ps
CPU time 1.12 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:26 PM PDT 24
Peak memory 217348 kb
Host smart-99293a08-e523-45e6-9450-00b77d8d58d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509082969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.509082969
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3055849884
Short name T239
Test name
Test status
Simulation time 262240167 ps
CPU time 1 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:26 PM PDT 24
Peak memory 199820 kb
Host smart-c483582b-d841-4b5b-a375-d1b066fc2032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055849884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3055849884
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2140711850
Short name T40
Test name
Test status
Simulation time 1504709698 ps
CPU time 6.24 seconds
Started Jun 30 05:05:25 PM PDT 24
Finished Jun 30 05:05:32 PM PDT 24
Peak memory 200280 kb
Host smart-c2b20b98-be73-4cd3-a7b2-5bb92e7706f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140711850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2140711850
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.4093435917
Short name T501
Test name
Test status
Simulation time 159490586 ps
CPU time 1.26 seconds
Started Jun 30 05:05:25 PM PDT 24
Finished Jun 30 05:05:27 PM PDT 24
Peak memory 200028 kb
Host smart-4ad9a4e2-315f-41df-8595-85235676f6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093435917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.4093435917
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.403840117
Short name T240
Test name
Test status
Simulation time 245107516 ps
CPU time 1.41 seconds
Started Jun 30 05:05:25 PM PDT 24
Finished Jun 30 05:05:27 PM PDT 24
Peak memory 200192 kb
Host smart-573e2742-e91f-4732-bd97-5424c543a81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403840117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.403840117
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3713453062
Short name T477
Test name
Test status
Simulation time 11083404348 ps
CPU time 39.79 seconds
Started Jun 30 05:05:22 PM PDT 24
Finished Jun 30 05:06:02 PM PDT 24
Peak memory 208444 kb
Host smart-912828e7-154f-4383-88b0-389910a56709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713453062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3713453062
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.866198839
Short name T535
Test name
Test status
Simulation time 457913700 ps
CPU time 2.45 seconds
Started Jun 30 05:05:21 PM PDT 24
Finished Jun 30 05:05:24 PM PDT 24
Peak memory 199920 kb
Host smart-d9e492cb-0544-4ddc-ae42-a85b37f6eabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866198839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.866198839
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3264260820
Short name T326
Test name
Test status
Simulation time 65916155 ps
CPU time 0.78 seconds
Started Jun 30 05:05:22 PM PDT 24
Finished Jun 30 05:05:24 PM PDT 24
Peak memory 200016 kb
Host smart-e7cc9bc8-5321-4249-ba25-97b5409d61d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264260820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3264260820
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3781145574
Short name T313
Test name
Test status
Simulation time 68325748 ps
CPU time 0.76 seconds
Started Jun 30 05:05:29 PM PDT 24
Finished Jun 30 05:05:31 PM PDT 24
Peak memory 199808 kb
Host smart-6959ca40-95d4-4d11-a9b5-c2631393c4dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781145574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3781145574
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1016165023
Short name T29
Test name
Test status
Simulation time 1228489693 ps
CPU time 5.68 seconds
Started Jun 30 05:05:32 PM PDT 24
Finished Jun 30 05:05:38 PM PDT 24
Peak memory 217660 kb
Host smart-491f8166-840a-41c8-856c-f5b7e0842056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016165023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1016165023
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3884908275
Short name T235
Test name
Test status
Simulation time 244291051 ps
CPU time 1.18 seconds
Started Jun 30 05:05:32 PM PDT 24
Finished Jun 30 05:05:34 PM PDT 24
Peak memory 217328 kb
Host smart-61ab47e1-dd65-437d-939d-234b53871d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884908275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3884908275
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.848924577
Short name T19
Test name
Test status
Simulation time 205286318 ps
CPU time 0.91 seconds
Started Jun 30 05:05:21 PM PDT 24
Finished Jun 30 05:05:22 PM PDT 24
Peak memory 199720 kb
Host smart-067f5133-4a79-4818-9f4c-1cd59bc70fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848924577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.848924577
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.4117624282
Short name T85
Test name
Test status
Simulation time 1866717964 ps
CPU time 6.8 seconds
Started Jun 30 05:05:30 PM PDT 24
Finished Jun 30 05:05:37 PM PDT 24
Peak memory 200268 kb
Host smart-10d6db12-a271-4d40-8a0e-6ee90f066c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117624282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.4117624282
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2904344944
Short name T89
Test name
Test status
Simulation time 99105126 ps
CPU time 0.99 seconds
Started Jun 30 05:05:32 PM PDT 24
Finished Jun 30 05:05:34 PM PDT 24
Peak memory 200008 kb
Host smart-6f219241-6d80-4ec6-b93c-5b0a8d3fd9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904344944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2904344944
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3077477867
Short name T177
Test name
Test status
Simulation time 247867979 ps
CPU time 1.45 seconds
Started Jun 30 05:05:23 PM PDT 24
Finished Jun 30 05:05:26 PM PDT 24
Peak memory 200204 kb
Host smart-4715b6c7-d74f-4e44-9821-cb29b7869d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077477867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3077477867
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.815650011
Short name T254
Test name
Test status
Simulation time 3802862357 ps
CPU time 17.83 seconds
Started Jun 30 05:05:29 PM PDT 24
Finished Jun 30 05:05:47 PM PDT 24
Peak memory 200320 kb
Host smart-a52e8fdf-ea85-4f1c-8291-430262040092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815650011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.815650011
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2719876612
Short name T464
Test name
Test status
Simulation time 436862810 ps
CPU time 2.29 seconds
Started Jun 30 05:05:29 PM PDT 24
Finished Jun 30 05:05:32 PM PDT 24
Peak memory 200004 kb
Host smart-01ee546b-e16d-418a-89d0-dbb75814b061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719876612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2719876612
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3373441863
Short name T11
Test name
Test status
Simulation time 117565656 ps
CPU time 1.05 seconds
Started Jun 30 05:05:30 PM PDT 24
Finished Jun 30 05:05:32 PM PDT 24
Peak memory 200020 kb
Host smart-26b17e9b-1617-446b-a22a-96f7da908218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373441863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3373441863
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3317430579
Short name T348
Test name
Test status
Simulation time 80624695 ps
CPU time 0.83 seconds
Started Jun 30 05:05:31 PM PDT 24
Finished Jun 30 05:05:33 PM PDT 24
Peak memory 199792 kb
Host smart-3fec263c-c1e8-4537-9fa0-8f667024ebe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317430579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3317430579
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2571255964
Short name T61
Test name
Test status
Simulation time 2354054234 ps
CPU time 8.54 seconds
Started Jun 30 05:05:37 PM PDT 24
Finished Jun 30 05:05:46 PM PDT 24
Peak memory 217224 kb
Host smart-9cfd76ff-5064-4e07-8406-d33f11bc61f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571255964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2571255964
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3710683316
Short name T87
Test name
Test status
Simulation time 244077567 ps
CPU time 1.14 seconds
Started Jun 30 05:05:30 PM PDT 24
Finished Jun 30 05:05:32 PM PDT 24
Peak memory 217376 kb
Host smart-612f3b3d-d12b-4c74-86e0-838dbdb770d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710683316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3710683316
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.606399312
Short name T13
Test name
Test status
Simulation time 181000123 ps
CPU time 0.89 seconds
Started Jun 30 05:05:31 PM PDT 24
Finished Jun 30 05:05:32 PM PDT 24
Peak memory 200116 kb
Host smart-09761a76-a63a-4c1a-80b3-97e05a699871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606399312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.606399312
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.934825652
Short name T306
Test name
Test status
Simulation time 1519207475 ps
CPU time 6.46 seconds
Started Jun 30 05:05:30 PM PDT 24
Finished Jun 30 05:05:37 PM PDT 24
Peak memory 200624 kb
Host smart-fdde3132-4457-4696-bcaf-22b3b999b1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934825652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.934825652
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3909863130
Short name T279
Test name
Test status
Simulation time 143406282 ps
CPU time 1.12 seconds
Started Jun 30 05:05:29 PM PDT 24
Finished Jun 30 05:05:31 PM PDT 24
Peak memory 200004 kb
Host smart-54f224c8-accc-4300-b33a-419985da80b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909863130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3909863130
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1295394116
Short name T66
Test name
Test status
Simulation time 247231732 ps
CPU time 1.55 seconds
Started Jun 30 05:05:30 PM PDT 24
Finished Jun 30 05:05:32 PM PDT 24
Peak memory 200168 kb
Host smart-8ada756c-3d62-4e5b-a9e7-f71455c0fad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295394116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1295394116
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2839763935
Short name T437
Test name
Test status
Simulation time 4629780386 ps
CPU time 16.27 seconds
Started Jun 30 05:05:32 PM PDT 24
Finished Jun 30 05:05:49 PM PDT 24
Peak memory 210056 kb
Host smart-762bc3f1-6b78-432d-b47e-b72c1542be95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839763935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2839763935
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3035160362
Short name T334
Test name
Test status
Simulation time 333995864 ps
CPU time 2.39 seconds
Started Jun 30 05:05:30 PM PDT 24
Finished Jun 30 05:05:33 PM PDT 24
Peak memory 208200 kb
Host smart-55eef405-6779-4dee-b729-62bffcb055ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035160362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3035160362
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.163425510
Short name T202
Test name
Test status
Simulation time 180151678 ps
CPU time 1.24 seconds
Started Jun 30 05:05:33 PM PDT 24
Finished Jun 30 05:05:35 PM PDT 24
Peak memory 200004 kb
Host smart-9ae561fe-9251-4f3e-9127-42800c872337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163425510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.163425510
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2099023174
Short name T21
Test name
Test status
Simulation time 71078754 ps
CPU time 0.81 seconds
Started Jun 30 05:05:40 PM PDT 24
Finished Jun 30 05:05:42 PM PDT 24
Peak memory 199820 kb
Host smart-a2c9031a-d6b2-4f6e-9728-de67a10678dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099023174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2099023174
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.185794313
Short name T52
Test name
Test status
Simulation time 1223504758 ps
CPU time 5.64 seconds
Started Jun 30 05:05:28 PM PDT 24
Finished Jun 30 05:05:34 PM PDT 24
Peak memory 217384 kb
Host smart-0059832e-5c11-4447-a010-092e98b8d34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185794313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.185794313
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2989676231
Short name T267
Test name
Test status
Simulation time 243449657 ps
CPU time 1.08 seconds
Started Jun 30 05:05:39 PM PDT 24
Finished Jun 30 05:05:42 PM PDT 24
Peak memory 217356 kb
Host smart-25323f85-25b7-40f0-b552-17bb87be0d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989676231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2989676231
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3590899171
Short name T364
Test name
Test status
Simulation time 184831334 ps
CPU time 0.89 seconds
Started Jun 30 05:05:33 PM PDT 24
Finished Jun 30 05:05:34 PM PDT 24
Peak memory 199816 kb
Host smart-8f17a4d5-2f66-48d4-af06-701ba53c1b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590899171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3590899171
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.471193389
Short name T204
Test name
Test status
Simulation time 1776622101 ps
CPU time 7.03 seconds
Started Jun 30 05:05:31 PM PDT 24
Finished Jun 30 05:05:38 PM PDT 24
Peak memory 200268 kb
Host smart-19fa7e38-71a7-4cc1-b977-81df61efe454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471193389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.471193389
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1482404314
Short name T200
Test name
Test status
Simulation time 153500052 ps
CPU time 1.21 seconds
Started Jun 30 05:05:30 PM PDT 24
Finished Jun 30 05:05:32 PM PDT 24
Peak memory 200032 kb
Host smart-e66264b9-b6db-44dc-a5dd-af2575dcb404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482404314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1482404314
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1769726245
Short name T56
Test name
Test status
Simulation time 193997010 ps
CPU time 1.4 seconds
Started Jun 30 05:05:30 PM PDT 24
Finished Jun 30 05:05:32 PM PDT 24
Peak memory 200212 kb
Host smart-1bcc9b47-7ae2-4d66-ba44-a3c51c59872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769726245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1769726245
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1275844701
Short name T401
Test name
Test status
Simulation time 6848617488 ps
CPU time 22.5 seconds
Started Jun 30 05:05:40 PM PDT 24
Finished Jun 30 05:06:04 PM PDT 24
Peak memory 200324 kb
Host smart-7cb408cc-323f-4da7-96bd-a50a12a8e771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275844701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1275844701
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1511732611
Short name T353
Test name
Test status
Simulation time 138486454 ps
CPU time 1.81 seconds
Started Jun 30 05:05:32 PM PDT 24
Finished Jun 30 05:05:34 PM PDT 24
Peak memory 199984 kb
Host smart-bc238718-d8ce-451f-ad19-8cfe6957934b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511732611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1511732611
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.831600795
Short name T374
Test name
Test status
Simulation time 98491789 ps
CPU time 0.96 seconds
Started Jun 30 05:05:32 PM PDT 24
Finished Jun 30 05:05:34 PM PDT 24
Peak memory 200008 kb
Host smart-20f339aa-5212-41ce-9102-78ac1d099f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831600795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.831600795
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.4293715212
Short name T482
Test name
Test status
Simulation time 65499081 ps
CPU time 0.78 seconds
Started Jun 30 05:05:40 PM PDT 24
Finished Jun 30 05:05:42 PM PDT 24
Peak memory 199820 kb
Host smart-25733f98-f31d-4c00-8bdf-aa43e06e3b5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293715212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4293715212
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.922468873
Short name T30
Test name
Test status
Simulation time 1890001440 ps
CPU time 6.95 seconds
Started Jun 30 05:05:40 PM PDT 24
Finished Jun 30 05:05:48 PM PDT 24
Peak memory 221552 kb
Host smart-c3c64e1c-b24d-4b35-ab43-0b09a828dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922468873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.922468873
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.455686509
Short name T295
Test name
Test status
Simulation time 245326260 ps
CPU time 1.1 seconds
Started Jun 30 05:05:37 PM PDT 24
Finished Jun 30 05:05:39 PM PDT 24
Peak memory 217356 kb
Host smart-64eec919-21fa-49c7-932d-73d890287a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455686509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.455686509
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2293380189
Short name T511
Test name
Test status
Simulation time 123455942 ps
CPU time 0.78 seconds
Started Jun 30 05:05:39 PM PDT 24
Finished Jun 30 05:05:41 PM PDT 24
Peak memory 199732 kb
Host smart-e58636fe-079a-475e-bf9d-1ac00a61f277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293380189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2293380189
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3284685974
Short name T517
Test name
Test status
Simulation time 1072990147 ps
CPU time 5.44 seconds
Started Jun 30 05:05:38 PM PDT 24
Finished Jun 30 05:05:44 PM PDT 24
Peak memory 200268 kb
Host smart-33ef08c5-05ac-4454-b70c-24f5cff7a691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284685974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3284685974
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2493400790
Short name T329
Test name
Test status
Simulation time 176031402 ps
CPU time 1.19 seconds
Started Jun 30 05:05:42 PM PDT 24
Finished Jun 30 05:05:43 PM PDT 24
Peak memory 200016 kb
Host smart-dedaa9e5-51d0-4511-86d9-f7454be918c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493400790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2493400790
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.96844067
Short name T260
Test name
Test status
Simulation time 115189988 ps
CPU time 1.14 seconds
Started Jun 30 05:05:42 PM PDT 24
Finished Jun 30 05:05:43 PM PDT 24
Peak memory 200220 kb
Host smart-45e60ac6-799b-440a-b15f-4dfea3316c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96844067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.96844067
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2714353892
Short name T321
Test name
Test status
Simulation time 2009006144 ps
CPU time 7.54 seconds
Started Jun 30 05:05:39 PM PDT 24
Finished Jun 30 05:05:48 PM PDT 24
Peak memory 200268 kb
Host smart-f69ff70c-4938-4eef-87e1-0ddaa424f5e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714353892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2714353892
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3934681900
Short name T215
Test name
Test status
Simulation time 142328027 ps
CPU time 1.72 seconds
Started Jun 30 05:05:43 PM PDT 24
Finished Jun 30 05:05:46 PM PDT 24
Peak memory 200000 kb
Host smart-44d64fd6-4619-427b-9a79-c0a0a2189fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934681900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3934681900
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1884835570
Short name T185
Test name
Test status
Simulation time 165243604 ps
CPU time 1.2 seconds
Started Jun 30 05:05:39 PM PDT 24
Finished Jun 30 05:05:41 PM PDT 24
Peak memory 199960 kb
Host smart-ae32425d-ad1f-43f8-8d6f-48d561447051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884835570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1884835570
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1510491047
Short name T536
Test name
Test status
Simulation time 74695522 ps
CPU time 0.83 seconds
Started Jun 30 05:05:38 PM PDT 24
Finished Jun 30 05:05:40 PM PDT 24
Peak memory 199808 kb
Host smart-9ef3ef23-46d0-4de2-b581-bf7dbddc8d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510491047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1510491047
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2301946709
Short name T394
Test name
Test status
Simulation time 2361963002 ps
CPU time 8.26 seconds
Started Jun 30 05:05:38 PM PDT 24
Finished Jun 30 05:05:47 PM PDT 24
Peak memory 217792 kb
Host smart-46df9ea1-1d40-42d5-bae7-ff71efb740ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301946709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2301946709
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3425194408
Short name T23
Test name
Test status
Simulation time 244701112 ps
CPU time 1.05 seconds
Started Jun 30 05:05:37 PM PDT 24
Finished Jun 30 05:05:39 PM PDT 24
Peak memory 217392 kb
Host smart-ea17ef32-e09e-41e7-bcd8-8f3838baeabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425194408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3425194408
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.471251274
Short name T195
Test name
Test status
Simulation time 206573921 ps
CPU time 0.97 seconds
Started Jun 30 05:05:37 PM PDT 24
Finished Jun 30 05:05:40 PM PDT 24
Peak memory 199788 kb
Host smart-b6138631-77b3-4e2f-8826-4e0147df4cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471251274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.471251274
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.158233719
Short name T500
Test name
Test status
Simulation time 1780009281 ps
CPU time 6.82 seconds
Started Jun 30 05:05:39 PM PDT 24
Finished Jun 30 05:05:46 PM PDT 24
Peak memory 200240 kb
Host smart-5cc2e9ff-9799-40c6-95e5-045ff1ef96a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158233719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.158233719
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.564435252
Short name T265
Test name
Test status
Simulation time 102664229 ps
CPU time 1.01 seconds
Started Jun 30 05:05:37 PM PDT 24
Finished Jun 30 05:05:39 PM PDT 24
Peak memory 200000 kb
Host smart-3776303e-cd60-422e-9202-27308db21796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564435252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.564435252
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3441920817
Short name T522
Test name
Test status
Simulation time 256572110 ps
CPU time 1.42 seconds
Started Jun 30 05:05:42 PM PDT 24
Finished Jun 30 05:05:43 PM PDT 24
Peak memory 200200 kb
Host smart-a9a91014-19a6-4aa3-aaff-6b1acd1cb100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441920817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3441920817
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2418203788
Short name T168
Test name
Test status
Simulation time 8262512058 ps
CPU time 29.85 seconds
Started Jun 30 05:05:39 PM PDT 24
Finished Jun 30 05:06:10 PM PDT 24
Peak memory 200312 kb
Host smart-9152402b-2e2d-46a7-901d-9759345a5815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418203788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2418203788
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1005553471
Short name T465
Test name
Test status
Simulation time 243956410 ps
CPU time 1.86 seconds
Started Jun 30 05:05:38 PM PDT 24
Finished Jun 30 05:05:41 PM PDT 24
Peak memory 199984 kb
Host smart-f277e96d-a801-4a15-a394-4ea7b73dd73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005553471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1005553471
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.4164748205
Short name T158
Test name
Test status
Simulation time 206737527 ps
CPU time 1.28 seconds
Started Jun 30 05:05:39 PM PDT 24
Finished Jun 30 05:05:42 PM PDT 24
Peak memory 200020 kb
Host smart-fa9231e2-da9d-45f8-90bb-43a2ed353607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164748205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.4164748205
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3630028167
Short name T405
Test name
Test status
Simulation time 71358939 ps
CPU time 0.78 seconds
Started Jun 30 05:05:40 PM PDT 24
Finished Jun 30 05:05:42 PM PDT 24
Peak memory 199752 kb
Host smart-633bec57-5963-4cb3-8ece-e7e1d510e7e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630028167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3630028167
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3006000798
Short name T50
Test name
Test status
Simulation time 1227048749 ps
CPU time 5.46 seconds
Started Jun 30 05:05:40 PM PDT 24
Finished Jun 30 05:05:46 PM PDT 24
Peak memory 217624 kb
Host smart-f25aca0c-c999-4d83-bcd1-695ec1e61f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006000798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3006000798
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.739489860
Short name T307
Test name
Test status
Simulation time 244482007 ps
CPU time 1.06 seconds
Started Jun 30 05:05:38 PM PDT 24
Finished Jun 30 05:05:40 PM PDT 24
Peak memory 217376 kb
Host smart-07cba854-f694-472c-84e3-d84e4b0a4f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739489860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.739489860
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4171663242
Short name T14
Test name
Test status
Simulation time 178859630 ps
CPU time 0.87 seconds
Started Jun 30 05:05:38 PM PDT 24
Finished Jun 30 05:05:40 PM PDT 24
Peak memory 199828 kb
Host smart-a71e034b-b5fb-4303-856d-1bf13adb0e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171663242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4171663242
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1026612684
Short name T444
Test name
Test status
Simulation time 1532011107 ps
CPU time 5.91 seconds
Started Jun 30 05:05:40 PM PDT 24
Finished Jun 30 05:05:47 PM PDT 24
Peak memory 200212 kb
Host smart-4030761a-f61a-40b9-a985-1b65d2aa91cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026612684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1026612684
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.804064122
Short name T382
Test name
Test status
Simulation time 99579504 ps
CPU time 1.05 seconds
Started Jun 30 05:05:37 PM PDT 24
Finished Jun 30 05:05:39 PM PDT 24
Peak memory 200020 kb
Host smart-37188da3-f454-4f7b-98ad-41337fb872cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804064122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.804064122
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2829377258
Short name T264
Test name
Test status
Simulation time 249455846 ps
CPU time 1.45 seconds
Started Jun 30 05:05:38 PM PDT 24
Finished Jun 30 05:05:40 PM PDT 24
Peak memory 200204 kb
Host smart-6ddedf19-3d3f-4c40-9d61-c02bc023cfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829377258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2829377258
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.886647514
Short name T463
Test name
Test status
Simulation time 3635855191 ps
CPU time 12.88 seconds
Started Jun 30 05:05:40 PM PDT 24
Finished Jun 30 05:05:54 PM PDT 24
Peak memory 208476 kb
Host smart-5f0288bc-e590-4bdc-b401-2ce6e550ba5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886647514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.886647514
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1639241802
Short name T424
Test name
Test status
Simulation time 385700461 ps
CPU time 2.53 seconds
Started Jun 30 05:05:40 PM PDT 24
Finished Jun 30 05:05:44 PM PDT 24
Peak memory 200000 kb
Host smart-139b2723-8c4a-4396-b223-002e6deb95b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639241802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1639241802
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3145803097
Short name T245
Test name
Test status
Simulation time 136407971 ps
CPU time 1.14 seconds
Started Jun 30 05:05:38 PM PDT 24
Finished Jun 30 05:05:40 PM PDT 24
Peak memory 200016 kb
Host smart-abacfeb5-c31e-4551-9b35-9caf7ea46a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145803097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3145803097
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3148266927
Short name T147
Test name
Test status
Simulation time 64235007 ps
CPU time 0.74 seconds
Started Jun 30 05:05:43 PM PDT 24
Finished Jun 30 05:05:45 PM PDT 24
Peak memory 199800 kb
Host smart-bfa32461-0600-474f-8642-e3341ad6e987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148266927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3148266927
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1944037782
Short name T31
Test name
Test status
Simulation time 1229716561 ps
CPU time 5.67 seconds
Started Jun 30 05:05:37 PM PDT 24
Finished Jun 30 05:05:44 PM PDT 24
Peak memory 217668 kb
Host smart-9be44701-595a-4186-8bd3-c1325c9dd1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944037782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1944037782
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3612020764
Short name T373
Test name
Test status
Simulation time 244158095 ps
CPU time 1.14 seconds
Started Jun 30 05:05:47 PM PDT 24
Finished Jun 30 05:05:49 PM PDT 24
Peak memory 217280 kb
Host smart-77ba2468-0e9b-4f48-bbf4-30bf875ee1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612020764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3612020764
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2972724085
Short name T328
Test name
Test status
Simulation time 81541162 ps
CPU time 0.77 seconds
Started Jun 30 05:05:40 PM PDT 24
Finished Jun 30 05:05:42 PM PDT 24
Peak memory 199808 kb
Host smart-a4cdc163-691c-4fb0-bd8f-261fa38cf414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972724085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2972724085
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1775644063
Short name T180
Test name
Test status
Simulation time 729166604 ps
CPU time 3.58 seconds
Started Jun 30 05:05:43 PM PDT 24
Finished Jun 30 05:05:48 PM PDT 24
Peak memory 200260 kb
Host smart-055dc8ae-d281-47b3-967a-89be2a9c0a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775644063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1775644063
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3372812569
Short name T331
Test name
Test status
Simulation time 155953030 ps
CPU time 1.2 seconds
Started Jun 30 05:05:42 PM PDT 24
Finished Jun 30 05:05:43 PM PDT 24
Peak memory 200028 kb
Host smart-596fe817-be4a-44f8-bb25-a1202fa62825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372812569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3372812569
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2350490099
Short name T317
Test name
Test status
Simulation time 245328837 ps
CPU time 1.63 seconds
Started Jun 30 05:05:38 PM PDT 24
Finished Jun 30 05:05:41 PM PDT 24
Peak memory 200196 kb
Host smart-1b814a00-f6c7-4864-9185-d029eb5a7cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350490099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2350490099
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2792859690
Short name T159
Test name
Test status
Simulation time 1067412573 ps
CPU time 4.74 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:52 PM PDT 24
Peak memory 200204 kb
Host smart-5f5c3d99-8753-4e49-a1f9-22a81daabdbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792859690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2792859690
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3637671664
Short name T227
Test name
Test status
Simulation time 150207848 ps
CPU time 1.81 seconds
Started Jun 30 05:05:40 PM PDT 24
Finished Jun 30 05:05:43 PM PDT 24
Peak memory 200000 kb
Host smart-11f08dcc-fe32-40c7-98c8-793a9541c6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637671664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3637671664
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1156026881
Short name T233
Test name
Test status
Simulation time 175356707 ps
CPU time 1.23 seconds
Started Jun 30 05:05:39 PM PDT 24
Finished Jun 30 05:05:41 PM PDT 24
Peak memory 200012 kb
Host smart-d4e200be-1405-4d36-957b-12db4f1591be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156026881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1156026881
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3662371742
Short name T155
Test name
Test status
Simulation time 69272125 ps
CPU time 0.75 seconds
Started Jun 30 05:04:34 PM PDT 24
Finished Jun 30 05:04:35 PM PDT 24
Peak memory 199744 kb
Host smart-4a7b25a6-7c05-4dba-838c-9e4e9e56ee2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662371742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3662371742
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3000358912
Short name T370
Test name
Test status
Simulation time 2339433754 ps
CPU time 9.26 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:46 PM PDT 24
Peak memory 217804 kb
Host smart-6b37deec-2470-4fd2-a948-82b542a15d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000358912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3000358912
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2063868288
Short name T257
Test name
Test status
Simulation time 244327441 ps
CPU time 1.07 seconds
Started Jun 30 05:04:38 PM PDT 24
Finished Jun 30 05:04:39 PM PDT 24
Peak memory 217340 kb
Host smart-800e2739-22a0-49c2-a19d-fa5d500b2714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063868288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2063868288
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1179479635
Short name T315
Test name
Test status
Simulation time 134612715 ps
CPU time 0.88 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:38 PM PDT 24
Peak memory 199828 kb
Host smart-836a9526-8943-4e6e-9de4-1f9cc8664163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179479635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1179479635
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1179377545
Short name T324
Test name
Test status
Simulation time 1372207113 ps
CPU time 4.86 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:04:40 PM PDT 24
Peak memory 200268 kb
Host smart-c6e62b9e-b7c0-4849-9cb9-921e4f3a1c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179377545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1179377545
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.10955977
Short name T76
Test name
Test status
Simulation time 8443475913 ps
CPU time 14.78 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:04:51 PM PDT 24
Peak memory 217344 kb
Host smart-25c46f7e-bada-432b-844a-f71c7711ee63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10955977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.10955977
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3878053767
Short name T275
Test name
Test status
Simulation time 98040105 ps
CPU time 1 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:38 PM PDT 24
Peak memory 199996 kb
Host smart-8eb1dca1-f2ac-4a10-9854-d403752fdb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878053767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3878053767
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.765677946
Short name T218
Test name
Test status
Simulation time 111742185 ps
CPU time 1.21 seconds
Started Jun 30 05:04:37 PM PDT 24
Finished Jun 30 05:04:39 PM PDT 24
Peak memory 200224 kb
Host smart-f70006ef-e3ce-4f50-a961-ae419bcc67e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765677946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.765677946
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3210997370
Short name T372
Test name
Test status
Simulation time 1995468481 ps
CPU time 8.77 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:46 PM PDT 24
Peak memory 200272 kb
Host smart-8c100e6c-f96c-4b7e-90e4-a4a10bdf23b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210997370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3210997370
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3030336521
Short name T206
Test name
Test status
Simulation time 340251491 ps
CPU time 2.19 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:04:37 PM PDT 24
Peak memory 208144 kb
Host smart-bfc547f4-0196-480b-93b6-482226ecd0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030336521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3030336521
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.486236601
Short name T184
Test name
Test status
Simulation time 154075406 ps
CPU time 1.25 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:38 PM PDT 24
Peak memory 199924 kb
Host smart-1007deb8-c199-4aa0-995a-b1912ce92ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486236601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.486236601
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.4049185733
Short name T220
Test name
Test status
Simulation time 70107494 ps
CPU time 0.78 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:47 PM PDT 24
Peak memory 199784 kb
Host smart-8a98bfa5-b6e5-4fd2-a0b9-f48ecaee69a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049185733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.4049185733
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.705031862
Short name T252
Test name
Test status
Simulation time 2187247563 ps
CPU time 8.03 seconds
Started Jun 30 05:05:47 PM PDT 24
Finished Jun 30 05:05:57 PM PDT 24
Peak memory 217004 kb
Host smart-4cbc8a56-3fb4-45c1-9913-9d56fd9d3f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705031862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.705031862
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1096134368
Short name T478
Test name
Test status
Simulation time 243981722 ps
CPU time 1.07 seconds
Started Jun 30 05:05:44 PM PDT 24
Finished Jun 30 05:05:46 PM PDT 24
Peak memory 217336 kb
Host smart-c7217b03-c44c-49fb-bb9a-59d0e331fb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096134368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1096134368
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2620868259
Short name T223
Test name
Test status
Simulation time 97403148 ps
CPU time 0.8 seconds
Started Jun 30 05:05:46 PM PDT 24
Finished Jun 30 05:05:49 PM PDT 24
Peak memory 199796 kb
Host smart-f5b8584b-3ff9-4dab-a700-319471de344d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620868259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2620868259
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.145431672
Short name T199
Test name
Test status
Simulation time 1751876321 ps
CPU time 7.21 seconds
Started Jun 30 05:05:44 PM PDT 24
Finished Jun 30 05:05:52 PM PDT 24
Peak memory 200308 kb
Host smart-a146df6f-9817-4a7b-b970-a135adaebf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145431672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.145431672
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3802710783
Short name T293
Test name
Test status
Simulation time 101195369 ps
CPU time 1.12 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:47 PM PDT 24
Peak memory 199996 kb
Host smart-8f2779f7-65ed-4861-bc10-e4f4c1553a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802710783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3802710783
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.589807154
Short name T406
Test name
Test status
Simulation time 120664360 ps
CPU time 1.23 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:47 PM PDT 24
Peak memory 200248 kb
Host smart-8baf1694-f98e-4f45-8a4f-7d532c00a935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589807154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.589807154
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2931358987
Short name T451
Test name
Test status
Simulation time 11449456521 ps
CPU time 38.24 seconds
Started Jun 30 05:05:44 PM PDT 24
Finished Jun 30 05:06:23 PM PDT 24
Peak memory 208532 kb
Host smart-57b0f01a-e8f0-4b5d-b804-9c808dbd2416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931358987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2931358987
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.542041715
Short name T253
Test name
Test status
Simulation time 374204580 ps
CPU time 2.4 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:49 PM PDT 24
Peak memory 200324 kb
Host smart-ea6b3928-4b4e-4fa9-99a4-0ee9e9b9ddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542041715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.542041715
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2394938088
Short name T244
Test name
Test status
Simulation time 90743565 ps
CPU time 0.92 seconds
Started Jun 30 05:05:46 PM PDT 24
Finished Jun 30 05:05:49 PM PDT 24
Peak memory 199980 kb
Host smart-86a6e30c-67ae-4b8f-8807-06353d720779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394938088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2394938088
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.357672132
Short name T409
Test name
Test status
Simulation time 77241486 ps
CPU time 0.82 seconds
Started Jun 30 05:05:44 PM PDT 24
Finished Jun 30 05:05:45 PM PDT 24
Peak memory 199792 kb
Host smart-34ea19d5-d65c-4805-83a2-69b477a60a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357672132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.357672132
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3449465865
Short name T302
Test name
Test status
Simulation time 1223039022 ps
CPU time 5.72 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:52 PM PDT 24
Peak memory 221228 kb
Host smart-2e8d186c-52f0-440f-bfff-fcfb1d55363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449465865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3449465865
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2207227904
Short name T136
Test name
Test status
Simulation time 243655368 ps
CPU time 1.06 seconds
Started Jun 30 05:05:49 PM PDT 24
Finished Jun 30 05:05:51 PM PDT 24
Peak memory 217392 kb
Host smart-6be04290-e57a-4f5f-a2bf-9279426211d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207227904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2207227904
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3877035471
Short name T12
Test name
Test status
Simulation time 126899586 ps
CPU time 0.78 seconds
Started Jun 30 05:05:46 PM PDT 24
Finished Jun 30 05:05:48 PM PDT 24
Peak memory 199828 kb
Host smart-e0b2a3da-9c9a-47d5-8ff6-0209721c83c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877035471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3877035471
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2551609486
Short name T428
Test name
Test status
Simulation time 1340411989 ps
CPU time 5.22 seconds
Started Jun 30 05:05:47 PM PDT 24
Finished Jun 30 05:05:53 PM PDT 24
Peak memory 200260 kb
Host smart-edf4cd81-d363-47ad-9f31-2de048fdbf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551609486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2551609486
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.904913080
Short name T460
Test name
Test status
Simulation time 103284452 ps
CPU time 0.99 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:47 PM PDT 24
Peak memory 200012 kb
Host smart-869b320c-6d46-4f16-91ee-a59f487aa0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904913080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.904913080
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1871006641
Short name T150
Test name
Test status
Simulation time 121532408 ps
CPU time 1.18 seconds
Started Jun 30 05:05:47 PM PDT 24
Finished Jun 30 05:05:50 PM PDT 24
Peak memory 200204 kb
Host smart-f519fa06-22f2-4ae9-88ad-c44e17327af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871006641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1871006641
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1240834055
Short name T113
Test name
Test status
Simulation time 8657433698 ps
CPU time 38.74 seconds
Started Jun 30 05:05:47 PM PDT 24
Finished Jun 30 05:06:27 PM PDT 24
Peak memory 208532 kb
Host smart-6f1f0fa2-2f34-4dd5-933a-8b37459d6f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240834055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1240834055
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1849544622
Short name T472
Test name
Test status
Simulation time 265372549 ps
CPU time 1.93 seconds
Started Jun 30 05:05:47 PM PDT 24
Finished Jun 30 05:05:50 PM PDT 24
Peak memory 200020 kb
Host smart-bac817f9-92a5-485c-ad18-fd2da6e9908a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849544622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1849544622
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2870987004
Short name T278
Test name
Test status
Simulation time 250954489 ps
CPU time 1.42 seconds
Started Jun 30 05:05:48 PM PDT 24
Finished Jun 30 05:05:50 PM PDT 24
Peak memory 200132 kb
Host smart-34ca620d-cec9-4f0d-9903-c68f21b1f5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870987004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2870987004
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1422448286
Short name T140
Test name
Test status
Simulation time 67025568 ps
CPU time 0.83 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:47 PM PDT 24
Peak memory 199804 kb
Host smart-1d55bcdf-e6d8-4c68-b9f3-b7e09caa718a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422448286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1422448286
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.440795891
Short name T355
Test name
Test status
Simulation time 2355507604 ps
CPU time 8.25 seconds
Started Jun 30 05:05:47 PM PDT 24
Finished Jun 30 05:05:57 PM PDT 24
Peak memory 221616 kb
Host smart-27a7c353-47ea-4fe1-bfc7-fc7198709a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440795891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.440795891
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3380206793
Short name T221
Test name
Test status
Simulation time 244696655 ps
CPU time 1.02 seconds
Started Jun 30 05:05:46 PM PDT 24
Finished Jun 30 05:05:48 PM PDT 24
Peak memory 217372 kb
Host smart-7ae8c025-d9ef-4d50-bb5a-67a35dbcc478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380206793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3380206793
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1895641566
Short name T351
Test name
Test status
Simulation time 136189216 ps
CPU time 0.82 seconds
Started Jun 30 05:05:46 PM PDT 24
Finished Jun 30 05:05:49 PM PDT 24
Peak memory 199808 kb
Host smart-7e02f418-92ed-4eb0-a17e-11d49a66c204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895641566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1895641566
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.212361614
Short name T57
Test name
Test status
Simulation time 1957002993 ps
CPU time 7.58 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:55 PM PDT 24
Peak memory 200264 kb
Host smart-4ceebbd2-ad22-47f8-8005-a5aac1e7132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212361614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.212361614
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3147154757
Short name T243
Test name
Test status
Simulation time 157191759 ps
CPU time 1.1 seconds
Started Jun 30 05:05:49 PM PDT 24
Finished Jun 30 05:05:51 PM PDT 24
Peak memory 199992 kb
Host smart-e1822863-6d4b-4da1-bf40-48ab07030ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147154757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3147154757
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1131951797
Short name T84
Test name
Test status
Simulation time 119447119 ps
CPU time 1.17 seconds
Started Jun 30 05:05:48 PM PDT 24
Finished Jun 30 05:05:50 PM PDT 24
Peak memory 200248 kb
Host smart-06509979-a410-40f2-93b7-b9ee0564d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131951797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1131951797
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1441311033
Short name T352
Test name
Test status
Simulation time 4212987127 ps
CPU time 19.75 seconds
Started Jun 30 05:05:48 PM PDT 24
Finished Jun 30 05:06:09 PM PDT 24
Peak memory 200376 kb
Host smart-d063a788-78fe-46ab-95c7-ae7cf1f4fbab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441311033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1441311033
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3920579849
Short name T398
Test name
Test status
Simulation time 257988754 ps
CPU time 1.84 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:47 PM PDT 24
Peak memory 200016 kb
Host smart-49cb0508-01d6-4071-a4ab-b072f57a5c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920579849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3920579849
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.4240490625
Short name T174
Test name
Test status
Simulation time 244570059 ps
CPU time 1.36 seconds
Started Jun 30 05:05:49 PM PDT 24
Finished Jun 30 05:05:51 PM PDT 24
Peak memory 199996 kb
Host smart-1a154395-7055-4690-a050-8ffb819d738c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240490625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.4240490625
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2220102892
Short name T356
Test name
Test status
Simulation time 70951096 ps
CPU time 0.8 seconds
Started Jun 30 05:05:49 PM PDT 24
Finished Jun 30 05:05:50 PM PDT 24
Peak memory 199808 kb
Host smart-6f069409-8417-4fbb-98ee-c75e86602874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220102892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2220102892
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.674086535
Short name T480
Test name
Test status
Simulation time 1219251056 ps
CPU time 5.47 seconds
Started Jun 30 05:05:44 PM PDT 24
Finished Jun 30 05:05:50 PM PDT 24
Peak memory 221516 kb
Host smart-9a71c4be-ddab-4afb-953a-b05e2e963fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674086535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.674086535
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1719401185
Short name T59
Test name
Test status
Simulation time 246074075 ps
CPU time 1.08 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:47 PM PDT 24
Peak memory 217320 kb
Host smart-116cee82-9a9a-4557-867a-3dc2401da151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719401185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1719401185
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3226763560
Short name T454
Test name
Test status
Simulation time 216532001 ps
CPU time 0.94 seconds
Started Jun 30 05:05:44 PM PDT 24
Finished Jun 30 05:05:45 PM PDT 24
Peak memory 199812 kb
Host smart-d426a46b-6945-410d-bfe3-e165c52be4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226763560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3226763560
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3202395612
Short name T318
Test name
Test status
Simulation time 1462241176 ps
CPU time 6.25 seconds
Started Jun 30 05:05:48 PM PDT 24
Finished Jun 30 05:05:55 PM PDT 24
Peak memory 200172 kb
Host smart-ef10b120-7e21-414e-9867-6e99737171f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202395612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3202395612
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.625482461
Short name T196
Test name
Test status
Simulation time 141276339 ps
CPU time 1.07 seconds
Started Jun 30 05:05:49 PM PDT 24
Finished Jun 30 05:05:51 PM PDT 24
Peak memory 200020 kb
Host smart-184a16a4-06b0-4b31-a5f0-47b997736685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625482461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.625482461
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3126538495
Short name T148
Test name
Test status
Simulation time 116820896 ps
CPU time 1.19 seconds
Started Jun 30 05:05:46 PM PDT 24
Finished Jun 30 05:05:49 PM PDT 24
Peak memory 200192 kb
Host smart-d5acebc5-fa41-49ed-bca9-cfcd2646e2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126538495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3126538495
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3170976049
Short name T138
Test name
Test status
Simulation time 202828151 ps
CPU time 1.23 seconds
Started Jun 30 05:05:49 PM PDT 24
Finished Jun 30 05:05:51 PM PDT 24
Peak memory 199996 kb
Host smart-fb62ee5b-b801-41db-96e2-5590613679ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170976049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3170976049
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3623373879
Short name T506
Test name
Test status
Simulation time 119399754 ps
CPU time 1.5 seconds
Started Jun 30 05:05:45 PM PDT 24
Finished Jun 30 05:05:47 PM PDT 24
Peak memory 200064 kb
Host smart-fac70328-7df1-4f49-91c1-19685438db0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623373879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3623373879
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1675370457
Short name T35
Test name
Test status
Simulation time 100490232 ps
CPU time 0.86 seconds
Started Jun 30 05:05:46 PM PDT 24
Finished Jun 30 05:05:48 PM PDT 24
Peak memory 200012 kb
Host smart-26889449-4f14-40d8-9e72-e74518238d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675370457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1675370457
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1620329724
Short name T330
Test name
Test status
Simulation time 65981474 ps
CPU time 0.76 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:02 PM PDT 24
Peak memory 199712 kb
Host smart-b958bec9-1afc-4b8f-93da-b2e87ff71696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620329724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1620329724
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2765898371
Short name T378
Test name
Test status
Simulation time 2345415270 ps
CPU time 7.87 seconds
Started Jun 30 05:05:50 PM PDT 24
Finished Jun 30 05:05:59 PM PDT 24
Peak memory 221596 kb
Host smart-8d22d3bf-6f2e-44e8-93bb-6172668251fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765898371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2765898371
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3730762442
Short name T186
Test name
Test status
Simulation time 244148335 ps
CPU time 1.18 seconds
Started Jun 30 05:05:54 PM PDT 24
Finished Jun 30 05:05:55 PM PDT 24
Peak memory 217376 kb
Host smart-ff99a9f7-340a-418c-96cd-104043871ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730762442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3730762442
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2364924847
Short name T250
Test name
Test status
Simulation time 160443490 ps
CPU time 0.82 seconds
Started Jun 30 05:05:55 PM PDT 24
Finished Jun 30 05:05:57 PM PDT 24
Peak memory 199840 kb
Host smart-cbd1ada3-e045-48e6-8e62-ca87f1c4352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364924847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2364924847
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3511791834
Short name T107
Test name
Test status
Simulation time 1416871929 ps
CPU time 5.95 seconds
Started Jun 30 05:05:53 PM PDT 24
Finished Jun 30 05:06:00 PM PDT 24
Peak memory 200260 kb
Host smart-d8c8f5bc-6e11-48ce-b496-7c7c9b8b3462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511791834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3511791834
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1197572159
Short name T489
Test name
Test status
Simulation time 103036423 ps
CPU time 1.01 seconds
Started Jun 30 05:05:51 PM PDT 24
Finished Jun 30 05:05:52 PM PDT 24
Peak memory 200012 kb
Host smart-4fcaa89f-3353-4f60-b12d-ad3216b35df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197572159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1197572159
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2581279744
Short name T238
Test name
Test status
Simulation time 127072219 ps
CPU time 1.2 seconds
Started Jun 30 05:05:46 PM PDT 24
Finished Jun 30 05:05:49 PM PDT 24
Peak memory 200200 kb
Host smart-841b3505-9fde-42a3-8816-7077807b45ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581279744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2581279744
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3408948609
Short name T467
Test name
Test status
Simulation time 2249635629 ps
CPU time 10.25 seconds
Started Jun 30 05:05:56 PM PDT 24
Finished Jun 30 05:06:06 PM PDT 24
Peak memory 200388 kb
Host smart-819f577b-bd1e-4d54-9810-5ed9da44608b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408948609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3408948609
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1479985348
Short name T41
Test name
Test status
Simulation time 119414797 ps
CPU time 1.57 seconds
Started Jun 30 05:05:55 PM PDT 24
Finished Jun 30 05:05:57 PM PDT 24
Peak memory 199992 kb
Host smart-1153374a-72a5-4086-8fc0-b5b9c5293df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479985348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1479985348
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3825108624
Short name T479
Test name
Test status
Simulation time 103160889 ps
CPU time 0.85 seconds
Started Jun 30 05:05:53 PM PDT 24
Finished Jun 30 05:05:54 PM PDT 24
Peak memory 199968 kb
Host smart-ef411259-d571-402b-9e81-f8cc8fd1037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825108624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3825108624
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3848410273
Short name T246
Test name
Test status
Simulation time 84950089 ps
CPU time 0.8 seconds
Started Jun 30 05:05:54 PM PDT 24
Finished Jun 30 05:05:55 PM PDT 24
Peak memory 199788 kb
Host smart-b40c4f31-a54b-4d3b-972b-638bb7e13173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848410273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3848410273
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2314371646
Short name T490
Test name
Test status
Simulation time 1221878301 ps
CPU time 5.44 seconds
Started Jun 30 05:05:54 PM PDT 24
Finished Jun 30 05:06:00 PM PDT 24
Peak memory 221584 kb
Host smart-22baa950-955e-4470-bd03-f8cac7684078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314371646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2314371646
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3865066476
Short name T285
Test name
Test status
Simulation time 243818377 ps
CPU time 1.09 seconds
Started Jun 30 05:05:52 PM PDT 24
Finished Jun 30 05:05:54 PM PDT 24
Peak memory 217336 kb
Host smart-959ce9f6-0181-4048-b373-312b1023630c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865066476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3865066476
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.600522157
Short name T452
Test name
Test status
Simulation time 141202266 ps
CPU time 0.83 seconds
Started Jun 30 05:05:52 PM PDT 24
Finished Jun 30 05:05:53 PM PDT 24
Peak memory 199788 kb
Host smart-8609f81e-b5f0-49cb-88f9-17e1e78f7c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600522157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.600522157
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2217043158
Short name T263
Test name
Test status
Simulation time 898954392 ps
CPU time 4.62 seconds
Started Jun 30 05:05:52 PM PDT 24
Finished Jun 30 05:05:57 PM PDT 24
Peak memory 200264 kb
Host smart-75388e71-c60f-4b7d-b008-72b37fe8c808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217043158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2217043158
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3768770949
Short name T9
Test name
Test status
Simulation time 106120351 ps
CPU time 1.02 seconds
Started Jun 30 05:05:51 PM PDT 24
Finished Jun 30 05:05:53 PM PDT 24
Peak memory 199920 kb
Host smart-7208d952-d532-44e1-a9a5-244f208319c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768770949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3768770949
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3494506779
Short name T288
Test name
Test status
Simulation time 261491488 ps
CPU time 1.43 seconds
Started Jun 30 05:05:52 PM PDT 24
Finished Jun 30 05:05:54 PM PDT 24
Peak memory 200204 kb
Host smart-3da8be3e-841f-4742-86ea-cd43babd70b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494506779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3494506779
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.741151257
Short name T48
Test name
Test status
Simulation time 11918965826 ps
CPU time 42.76 seconds
Started Jun 30 05:05:51 PM PDT 24
Finished Jun 30 05:06:34 PM PDT 24
Peak memory 208516 kb
Host smart-633d9d04-904a-4857-842b-d2f4b2e1b729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741151257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.741151257
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.4078183685
Short name T422
Test name
Test status
Simulation time 124988568 ps
CPU time 1.58 seconds
Started Jun 30 05:05:54 PM PDT 24
Finished Jun 30 05:05:56 PM PDT 24
Peak memory 200032 kb
Host smart-cc0a3771-66cb-48ab-80e9-34a266723173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078183685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4078183685
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1817279428
Short name T205
Test name
Test status
Simulation time 124078428 ps
CPU time 1.12 seconds
Started Jun 30 05:05:54 PM PDT 24
Finished Jun 30 05:05:56 PM PDT 24
Peak memory 200000 kb
Host smart-31f2ca70-e815-4a16-8647-2d9bb8919ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817279428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1817279428
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2876193258
Short name T153
Test name
Test status
Simulation time 70355578 ps
CPU time 0.8 seconds
Started Jun 30 05:05:51 PM PDT 24
Finished Jun 30 05:05:52 PM PDT 24
Peak memory 199796 kb
Host smart-99bb0782-6f10-4a88-9d34-b77eeed55e82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876193258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2876193258
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1473312512
Short name T414
Test name
Test status
Simulation time 244831135 ps
CPU time 1.1 seconds
Started Jun 30 05:05:53 PM PDT 24
Finished Jun 30 05:05:55 PM PDT 24
Peak memory 217388 kb
Host smart-9523ba45-280c-4657-a76e-baac74a28dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473312512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1473312512
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1698116263
Short name T304
Test name
Test status
Simulation time 177992270 ps
CPU time 0.86 seconds
Started Jun 30 05:05:51 PM PDT 24
Finished Jun 30 05:05:53 PM PDT 24
Peak memory 199808 kb
Host smart-ce1ba906-7e37-406b-b25d-c30ae3e09cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698116263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1698116263
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2113809719
Short name T475
Test name
Test status
Simulation time 1770042427 ps
CPU time 6.8 seconds
Started Jun 30 05:05:51 PM PDT 24
Finished Jun 30 05:05:58 PM PDT 24
Peak memory 200276 kb
Host smart-4623d2f8-b6da-4dd3-b01e-6fdd14ca62e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113809719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2113809719
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3426633929
Short name T418
Test name
Test status
Simulation time 113607484 ps
CPU time 0.99 seconds
Started Jun 30 05:05:53 PM PDT 24
Finished Jun 30 05:05:54 PM PDT 24
Peak memory 200016 kb
Host smart-4349fe8f-c273-41f5-9fab-2ab4c062468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426633929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3426633929
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2318055967
Short name T540
Test name
Test status
Simulation time 191361961 ps
CPU time 1.38 seconds
Started Jun 30 05:05:50 PM PDT 24
Finished Jun 30 05:05:52 PM PDT 24
Peak memory 200188 kb
Host smart-34c2be99-15a6-45b4-9342-70d7035a051e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318055967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2318055967
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1593676832
Short name T210
Test name
Test status
Simulation time 2356250553 ps
CPU time 10.72 seconds
Started Jun 30 05:05:52 PM PDT 24
Finished Jun 30 05:06:04 PM PDT 24
Peak memory 208472 kb
Host smart-23607cdc-8cd4-45b8-88d6-b180538635de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593676832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1593676832
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1412947688
Short name T337
Test name
Test status
Simulation time 113113499 ps
CPU time 1.49 seconds
Started Jun 30 05:05:52 PM PDT 24
Finished Jun 30 05:05:54 PM PDT 24
Peak memory 199916 kb
Host smart-b41743a1-0559-44ea-afc9-6a64ca6e29d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412947688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1412947688
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2122021862
Short name T497
Test name
Test status
Simulation time 139818924 ps
CPU time 1.15 seconds
Started Jun 30 05:05:52 PM PDT 24
Finished Jun 30 05:05:53 PM PDT 24
Peak memory 200020 kb
Host smart-48ad71ab-dc75-4e51-9c18-3bd9f97619aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122021862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2122021862
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1072487133
Short name T508
Test name
Test status
Simulation time 63441087 ps
CPU time 0.74 seconds
Started Jun 30 05:05:57 PM PDT 24
Finished Jun 30 05:05:58 PM PDT 24
Peak memory 199780 kb
Host smart-17cd1a4e-b416-4593-ad9d-9377ae869516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072487133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1072487133
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1906368177
Short name T224
Test name
Test status
Simulation time 1900165769 ps
CPU time 7.54 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:08 PM PDT 24
Peak memory 217660 kb
Host smart-141bdb67-8b77-4c63-b6a5-e91acd2b6758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906368177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1906368177
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3913856693
Short name T534
Test name
Test status
Simulation time 244240067 ps
CPU time 1.11 seconds
Started Jun 30 05:05:59 PM PDT 24
Finished Jun 30 05:06:01 PM PDT 24
Peak memory 217276 kb
Host smart-3a098999-34d4-4748-8f93-1642d37ec4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913856693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3913856693
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3718231842
Short name T488
Test name
Test status
Simulation time 110862954 ps
CPU time 0.85 seconds
Started Jun 30 05:05:51 PM PDT 24
Finished Jun 30 05:05:53 PM PDT 24
Peak memory 199812 kb
Host smart-130c79fb-c303-4ff8-8f1f-7d5d75609070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718231842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3718231842
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1498987187
Short name T360
Test name
Test status
Simulation time 1442289422 ps
CPU time 5.96 seconds
Started Jun 30 05:06:04 PM PDT 24
Finished Jun 30 05:06:10 PM PDT 24
Peak memory 200208 kb
Host smart-ee76d144-606a-4ee9-a2bb-9ff5ad63e4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498987187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1498987187
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2349017568
Short name T249
Test name
Test status
Simulation time 105662257 ps
CPU time 1.02 seconds
Started Jun 30 05:06:02 PM PDT 24
Finished Jun 30 05:06:04 PM PDT 24
Peak memory 200008 kb
Host smart-917c9974-944a-4530-a3ca-d247d94af00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349017568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2349017568
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.115847315
Short name T362
Test name
Test status
Simulation time 200785644 ps
CPU time 1.45 seconds
Started Jun 30 05:05:51 PM PDT 24
Finished Jun 30 05:05:53 PM PDT 24
Peak memory 200192 kb
Host smart-6f4b8aa5-d0c0-46ca-83ad-fb0c5d70669b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115847315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.115847315
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2466182773
Short name T430
Test name
Test status
Simulation time 122153567 ps
CPU time 1.06 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:01 PM PDT 24
Peak memory 199988 kb
Host smart-71d19ac8-ef9b-497d-95a3-6f9d79c9a29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466182773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2466182773
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2618623679
Short name T320
Test name
Test status
Simulation time 79577956 ps
CPU time 0.82 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:02 PM PDT 24
Peak memory 199804 kb
Host smart-130c9a28-de99-499f-9c3a-03a6f8153a24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618623679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2618623679
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2910510059
Short name T32
Test name
Test status
Simulation time 1230004208 ps
CPU time 6.12 seconds
Started Jun 30 05:05:59 PM PDT 24
Finished Jun 30 05:06:06 PM PDT 24
Peak memory 221548 kb
Host smart-786cbe38-a427-4709-ae66-1c283eeba2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910510059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2910510059
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3719417105
Short name T415
Test name
Test status
Simulation time 243745779 ps
CPU time 1.1 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:02 PM PDT 24
Peak memory 217220 kb
Host smart-6324f6c8-d71f-400c-880a-2b1ee0adbeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719417105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3719417105
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3095091527
Short name T436
Test name
Test status
Simulation time 94073341 ps
CPU time 0.77 seconds
Started Jun 30 05:06:03 PM PDT 24
Finished Jun 30 05:06:05 PM PDT 24
Peak memory 199820 kb
Host smart-21ca6b8a-521a-43ce-90ed-0e79fa70dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095091527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3095091527
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2845682350
Short name T404
Test name
Test status
Simulation time 1540283847 ps
CPU time 5.86 seconds
Started Jun 30 05:05:56 PM PDT 24
Finished Jun 30 05:06:03 PM PDT 24
Peak memory 200260 kb
Host smart-2e513930-0bb7-4581-86c8-3835b16d0c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845682350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2845682350
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1590410529
Short name T344
Test name
Test status
Simulation time 98413410 ps
CPU time 1.05 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:02 PM PDT 24
Peak memory 199280 kb
Host smart-33e4f7e3-5a48-4c32-abc4-c9ab846177e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590410529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1590410529
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.4228854560
Short name T387
Test name
Test status
Simulation time 229862964 ps
CPU time 1.53 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:03 PM PDT 24
Peak memory 200188 kb
Host smart-c20d0ad5-15a3-4124-b9ce-5f32614e5208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228854560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.4228854560
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.287513651
Short name T440
Test name
Test status
Simulation time 9324939241 ps
CPU time 32.84 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:34 PM PDT 24
Peak memory 216616 kb
Host smart-15cfaef8-49a6-45bc-ad9a-a74f6090c032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287513651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.287513651
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2435466745
Short name T262
Test name
Test status
Simulation time 141864521 ps
CPU time 2.11 seconds
Started Jun 30 05:05:59 PM PDT 24
Finished Jun 30 05:06:02 PM PDT 24
Peak memory 200004 kb
Host smart-56391836-a0f7-4dbc-9eba-58b03993d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435466745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2435466745
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2050840793
Short name T46
Test name
Test status
Simulation time 76240901 ps
CPU time 0.83 seconds
Started Jun 30 05:05:57 PM PDT 24
Finished Jun 30 05:05:58 PM PDT 24
Peak memory 200012 kb
Host smart-772685e4-5d3f-468a-9718-7b40eff18f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050840793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2050840793
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1288311153
Short name T496
Test name
Test status
Simulation time 71489534 ps
CPU time 0.78 seconds
Started Jun 30 05:06:01 PM PDT 24
Finished Jun 30 05:06:03 PM PDT 24
Peak memory 199808 kb
Host smart-21ca63dd-f78e-469b-92a8-c76e9f63fb4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288311153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1288311153
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2298458748
Short name T281
Test name
Test status
Simulation time 1225406104 ps
CPU time 5.48 seconds
Started Jun 30 05:05:59 PM PDT 24
Finished Jun 30 05:06:05 PM PDT 24
Peak memory 217016 kb
Host smart-85b92a66-17ab-4346-9b34-e971a8154659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298458748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2298458748
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.29184083
Short name T214
Test name
Test status
Simulation time 244025321 ps
CPU time 1.13 seconds
Started Jun 30 05:06:04 PM PDT 24
Finished Jun 30 05:06:05 PM PDT 24
Peak memory 217312 kb
Host smart-ffb088aa-86f8-4b0f-a9df-9c935d3f2fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29184083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.29184083
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2643068577
Short name T8
Test name
Test status
Simulation time 178705118 ps
CPU time 0.84 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:01 PM PDT 24
Peak memory 199828 kb
Host smart-8edf8d8a-0ec0-4602-ad7d-7099af2bb421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643068577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2643068577
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2442994830
Short name T230
Test name
Test status
Simulation time 964955399 ps
CPU time 5.2 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:07 PM PDT 24
Peak memory 200300 kb
Host smart-a0672a64-4917-4e21-8395-a92d51ff9fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442994830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2442994830
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.223592211
Short name T449
Test name
Test status
Simulation time 114816570 ps
CPU time 1.02 seconds
Started Jun 30 05:05:57 PM PDT 24
Finished Jun 30 05:05:59 PM PDT 24
Peak memory 199980 kb
Host smart-faa49634-0844-469a-8763-1653c284a4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223592211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.223592211
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2995898239
Short name T292
Test name
Test status
Simulation time 107772965 ps
CPU time 1.22 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:02 PM PDT 24
Peak memory 200164 kb
Host smart-af054cbe-f201-4f2e-9bef-b4a5e14b5ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995898239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2995898239
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.334181643
Short name T216
Test name
Test status
Simulation time 1940830983 ps
CPU time 7.56 seconds
Started Jun 30 05:05:58 PM PDT 24
Finished Jun 30 05:06:06 PM PDT 24
Peak memory 200268 kb
Host smart-05ab1d77-a695-4ec0-b835-e4b659eca34a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334181643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.334181643
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.967998471
Short name T457
Test name
Test status
Simulation time 468668612 ps
CPU time 2.54 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:04 PM PDT 24
Peak memory 199992 kb
Host smart-30d8b676-685a-47e7-b323-c628ff417d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967998471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.967998471
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2246977688
Short name T443
Test name
Test status
Simulation time 61332649 ps
CPU time 0.8 seconds
Started Jun 30 05:06:02 PM PDT 24
Finished Jun 30 05:06:04 PM PDT 24
Peak memory 200032 kb
Host smart-6f2c6a3c-2f02-412c-85b9-ffc9a3c7b693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246977688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2246977688
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2254842703
Short name T236
Test name
Test status
Simulation time 91374214 ps
CPU time 0.81 seconds
Started Jun 30 05:04:34 PM PDT 24
Finished Jun 30 05:04:35 PM PDT 24
Peak memory 199716 kb
Host smart-c6fe8d8c-8d4a-458c-89d4-9d17eca85412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254842703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2254842703
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.75663390
Short name T403
Test name
Test status
Simulation time 1909554755 ps
CPU time 7.71 seconds
Started Jun 30 05:04:37 PM PDT 24
Finished Jun 30 05:04:45 PM PDT 24
Peak memory 217644 kb
Host smart-8238187b-2688-4855-9618-c7a4052e8c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75663390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.75663390
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2950475452
Short name T258
Test name
Test status
Simulation time 243945872 ps
CPU time 1.04 seconds
Started Jun 30 05:04:38 PM PDT 24
Finished Jun 30 05:04:39 PM PDT 24
Peak memory 217392 kb
Host smart-274b584d-d159-4ec8-af97-dedcf6f2789f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950475452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2950475452
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.230892152
Short name T182
Test name
Test status
Simulation time 171951153 ps
CPU time 0.89 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:04:36 PM PDT 24
Peak memory 199804 kb
Host smart-21a29e58-ad32-4108-becd-cc3e4cc73a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230892152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.230892152
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3420151805
Short name T231
Test name
Test status
Simulation time 1750590403 ps
CPU time 6.55 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:04:41 PM PDT 24
Peak memory 200148 kb
Host smart-980deea6-8260-4cd8-8d6a-8dee88291613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420151805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3420151805
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1212680929
Short name T80
Test name
Test status
Simulation time 16854328835 ps
CPU time 25.53 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:05:02 PM PDT 24
Peak memory 217132 kb
Host smart-f930d566-6a83-4d31-877c-f63f122cd77b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212680929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1212680929
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.439934214
Short name T4
Test name
Test status
Simulation time 204611825 ps
CPU time 1.41 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:04:39 PM PDT 24
Peak memory 200216 kb
Host smart-86faf891-c947-4fd8-89bb-71311291ee4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439934214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.439934214
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3856950859
Short name T208
Test name
Test status
Simulation time 8066926902 ps
CPU time 28.4 seconds
Started Jun 30 05:04:36 PM PDT 24
Finished Jun 30 05:05:05 PM PDT 24
Peak memory 200364 kb
Host smart-47f896a3-a4dc-4a96-ad1c-20656bb0dd38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856950859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3856950859
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2023469301
Short name T419
Test name
Test status
Simulation time 344653833 ps
CPU time 2.31 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:04:38 PM PDT 24
Peak memory 199988 kb
Host smart-50924ed7-5026-4953-a26a-a7eebb2f36c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023469301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2023469301
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.928795653
Short name T173
Test name
Test status
Simulation time 215705149 ps
CPU time 1.36 seconds
Started Jun 30 05:04:34 PM PDT 24
Finished Jun 30 05:04:36 PM PDT 24
Peak memory 200016 kb
Host smart-6727e514-323f-4f92-a80d-fc3539470a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928795653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.928795653
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.33064538
Short name T510
Test name
Test status
Simulation time 71325525 ps
CPU time 0.79 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:02 PM PDT 24
Peak memory 199076 kb
Host smart-4091e922-f6ae-436c-a50f-aff4c1d01ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33064538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.33064538
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2286780956
Short name T43
Test name
Test status
Simulation time 2358092545 ps
CPU time 9.47 seconds
Started Jun 30 05:05:57 PM PDT 24
Finished Jun 30 05:06:07 PM PDT 24
Peak memory 221560 kb
Host smart-175db110-4b21-4245-98f4-707484e2281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286780956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2286780956
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2470147227
Short name T335
Test name
Test status
Simulation time 244157812 ps
CPU time 1.1 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:02 PM PDT 24
Peak memory 217312 kb
Host smart-15d41f17-8105-4e8c-ae8a-7d8e6f94075d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470147227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2470147227
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.4153455076
Short name T316
Test name
Test status
Simulation time 111105104 ps
CPU time 0.84 seconds
Started Jun 30 05:06:01 PM PDT 24
Finished Jun 30 05:06:03 PM PDT 24
Peak memory 199800 kb
Host smart-5ef3d11d-1185-4724-9167-ea9dc929b191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153455076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.4153455076
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2163807971
Short name T450
Test name
Test status
Simulation time 1673052009 ps
CPU time 6.65 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:08 PM PDT 24
Peak memory 200244 kb
Host smart-622accba-5d29-48c6-9270-eba27febfc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163807971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2163807971
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.225361154
Short name T301
Test name
Test status
Simulation time 151662594 ps
CPU time 1.18 seconds
Started Jun 30 05:06:01 PM PDT 24
Finished Jun 30 05:06:03 PM PDT 24
Peak memory 199992 kb
Host smart-0a0042f9-accf-4baa-aa09-d4d871e74be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225361154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.225361154
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.955059330
Short name T528
Test name
Test status
Simulation time 251284389 ps
CPU time 1.44 seconds
Started Jun 30 05:05:58 PM PDT 24
Finished Jun 30 05:06:00 PM PDT 24
Peak memory 200156 kb
Host smart-b8afd53b-46b0-4dac-87e1-0420ef802692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955059330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.955059330
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3884860332
Short name T523
Test name
Test status
Simulation time 4560233840 ps
CPU time 17.72 seconds
Started Jun 30 05:06:01 PM PDT 24
Finished Jun 30 05:06:20 PM PDT 24
Peak memory 200340 kb
Host smart-f30e71ab-ac9f-40cd-aec9-0fb5c92a7f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884860332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3884860332
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2856647742
Short name T172
Test name
Test status
Simulation time 525322412 ps
CPU time 2.79 seconds
Started Jun 30 05:06:00 PM PDT 24
Finished Jun 30 05:06:04 PM PDT 24
Peak memory 199944 kb
Host smart-d5e7454b-c797-4824-8fe8-9671d8b9a227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856647742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2856647742
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.339775175
Short name T537
Test name
Test status
Simulation time 121371278 ps
CPU time 1.01 seconds
Started Jun 30 05:06:01 PM PDT 24
Finished Jun 30 05:06:03 PM PDT 24
Peak memory 200016 kb
Host smart-008f1c7a-8057-4c4b-9b0c-36c4702a9c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339775175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.339775175
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2258471137
Short name T160
Test name
Test status
Simulation time 74941249 ps
CPU time 0.86 seconds
Started Jun 30 05:06:05 PM PDT 24
Finished Jun 30 05:06:06 PM PDT 24
Peak memory 199800 kb
Host smart-5e568af1-4751-43a9-89eb-10d660beeacd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258471137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2258471137
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.807456545
Short name T341
Test name
Test status
Simulation time 2362336322 ps
CPU time 8.48 seconds
Started Jun 30 05:06:04 PM PDT 24
Finished Jun 30 05:06:13 PM PDT 24
Peak memory 217784 kb
Host smart-85b9f27f-2e2e-4d83-b373-e538b58a1e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807456545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.807456545
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.990260362
Short name T385
Test name
Test status
Simulation time 244538739 ps
CPU time 1.15 seconds
Started Jun 30 05:06:07 PM PDT 24
Finished Jun 30 05:06:09 PM PDT 24
Peak memory 217348 kb
Host smart-ec40a13c-484c-43d3-b897-23d16eb73bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990260362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.990260362
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2748668294
Short name T407
Test name
Test status
Simulation time 215740098 ps
CPU time 0.92 seconds
Started Jun 30 05:06:08 PM PDT 24
Finished Jun 30 05:06:09 PM PDT 24
Peak memory 199800 kb
Host smart-5999f91d-dab8-4190-9d62-054d67159939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748668294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2748668294
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.344100407
Short name T389
Test name
Test status
Simulation time 1736837257 ps
CPU time 7.1 seconds
Started Jun 30 05:06:06 PM PDT 24
Finished Jun 30 05:06:15 PM PDT 24
Peak memory 200248 kb
Host smart-f42b75f7-8b1e-4c0c-a521-a4791e50de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344100407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.344100407
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1393223916
Short name T294
Test name
Test status
Simulation time 179868246 ps
CPU time 1.18 seconds
Started Jun 30 05:06:06 PM PDT 24
Finished Jun 30 05:06:08 PM PDT 24
Peak memory 199980 kb
Host smart-88795e0a-7430-4471-9737-2d55a9c3a879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393223916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1393223916
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3065046469
Short name T67
Test name
Test status
Simulation time 115944154 ps
CPU time 1.23 seconds
Started Jun 30 05:06:01 PM PDT 24
Finished Jun 30 05:06:03 PM PDT 24
Peak memory 200212 kb
Host smart-cdd028b0-c3e5-4b48-a407-af1f48f2b3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065046469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3065046469
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.186962934
Short name T36
Test name
Test status
Simulation time 1838346990 ps
CPU time 6.9 seconds
Started Jun 30 05:06:08 PM PDT 24
Finished Jun 30 05:06:15 PM PDT 24
Peak memory 200240 kb
Host smart-092a293a-d5c7-42d1-9ec9-126d0d2ed8c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186962934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.186962934
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1855839428
Short name T376
Test name
Test status
Simulation time 306615291 ps
CPU time 2.07 seconds
Started Jun 30 05:06:08 PM PDT 24
Finished Jun 30 05:06:11 PM PDT 24
Peak memory 208228 kb
Host smart-0b306a9c-ebc3-4e97-9974-55b9cb2742c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855839428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1855839428
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1136752611
Short name T217
Test name
Test status
Simulation time 180624616 ps
CPU time 1.23 seconds
Started Jun 30 05:06:08 PM PDT 24
Finished Jun 30 05:06:11 PM PDT 24
Peak memory 199992 kb
Host smart-5687730c-6e8c-4643-8f58-8b3bda4b4a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136752611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1136752611
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2936626502
Short name T77
Test name
Test status
Simulation time 73147641 ps
CPU time 0.78 seconds
Started Jun 30 05:06:09 PM PDT 24
Finished Jun 30 05:06:11 PM PDT 24
Peak memory 199800 kb
Host smart-3f02dc2c-6b3c-49f0-b605-b0250d796710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936626502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2936626502
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1190585984
Short name T416
Test name
Test status
Simulation time 1892334671 ps
CPU time 7.47 seconds
Started Jun 30 05:06:16 PM PDT 24
Finished Jun 30 05:06:24 PM PDT 24
Peak memory 217660 kb
Host smart-24f81949-b41b-4317-a6ef-344b8e81ac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190585984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1190585984
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2486541240
Short name T190
Test name
Test status
Simulation time 244693789 ps
CPU time 1.08 seconds
Started Jun 30 05:06:09 PM PDT 24
Finished Jun 30 05:06:11 PM PDT 24
Peak memory 217368 kb
Host smart-d6853e93-f32e-46ae-ae8f-d7aea5e8d1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486541240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2486541240
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2382799524
Short name T503
Test name
Test status
Simulation time 91373018 ps
CPU time 0.74 seconds
Started Jun 30 05:06:04 PM PDT 24
Finished Jun 30 05:06:05 PM PDT 24
Peak memory 199824 kb
Host smart-1229aeaa-f5d7-4753-902b-49d82f1fea17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382799524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2382799524
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1422861780
Short name T165
Test name
Test status
Simulation time 1418839179 ps
CPU time 5.48 seconds
Started Jun 30 05:06:09 PM PDT 24
Finished Jun 30 05:06:16 PM PDT 24
Peak memory 200300 kb
Host smart-65d77956-7028-45a8-879d-ac073582aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422861780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1422861780
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1732415193
Short name T280
Test name
Test status
Simulation time 101315724 ps
CPU time 1.04 seconds
Started Jun 30 05:06:08 PM PDT 24
Finished Jun 30 05:06:11 PM PDT 24
Peak memory 200012 kb
Host smart-b9de978c-59fc-4a6c-b576-f1205cf918aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732415193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1732415193
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.801611920
Short name T388
Test name
Test status
Simulation time 117195332 ps
CPU time 1.19 seconds
Started Jun 30 05:06:07 PM PDT 24
Finished Jun 30 05:06:09 PM PDT 24
Peak memory 200200 kb
Host smart-9a76fcb2-86bd-44c0-81ac-624c7a2d4d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801611920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.801611920
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1443700613
Short name T342
Test name
Test status
Simulation time 203039166 ps
CPU time 1.31 seconds
Started Jun 30 05:06:08 PM PDT 24
Finished Jun 30 05:06:11 PM PDT 24
Peak memory 199792 kb
Host smart-7b91c779-771d-4ed4-a3e2-c18c4ce1ab98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443700613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1443700613
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.519024692
Short name T375
Test name
Test status
Simulation time 366946414 ps
CPU time 2.31 seconds
Started Jun 30 05:06:06 PM PDT 24
Finished Jun 30 05:06:08 PM PDT 24
Peak memory 200024 kb
Host smart-5576fbde-2293-4bc1-ba08-1c9d02306e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519024692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.519024692
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.488419396
Short name T169
Test name
Test status
Simulation time 173369710 ps
CPU time 1.17 seconds
Started Jun 30 05:06:06 PM PDT 24
Finished Jun 30 05:06:09 PM PDT 24
Peak memory 199996 kb
Host smart-5bea92a0-635a-4e28-b1f5-98575ada2b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488419396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.488419396
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.838260463
Short name T266
Test name
Test status
Simulation time 64814028 ps
CPU time 0.73 seconds
Started Jun 30 05:06:07 PM PDT 24
Finished Jun 30 05:06:09 PM PDT 24
Peak memory 199784 kb
Host smart-b4c7eafb-6b3a-48a5-9790-bb0c0764f636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838260463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.838260463
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3768366210
Short name T42
Test name
Test status
Simulation time 1231542802 ps
CPU time 6.2 seconds
Started Jun 30 05:06:07 PM PDT 24
Finished Jun 30 05:06:14 PM PDT 24
Peak memory 217576 kb
Host smart-9632e957-d4e8-4cac-b514-623715c1bd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768366210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3768366210
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2248100243
Short name T345
Test name
Test status
Simulation time 246165025 ps
CPU time 1.03 seconds
Started Jun 30 05:06:16 PM PDT 24
Finished Jun 30 05:06:17 PM PDT 24
Peak memory 217368 kb
Host smart-9c32f14c-d13f-40c4-bad5-8db04f25951d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248100243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2248100243
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.4075359993
Short name T297
Test name
Test status
Simulation time 108578843 ps
CPU time 0.85 seconds
Started Jun 30 05:06:17 PM PDT 24
Finished Jun 30 05:06:18 PM PDT 24
Peak memory 199820 kb
Host smart-5ad7b72f-ec5f-41ab-a7e2-83e40667f632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075359993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.4075359993
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.641895229
Short name T191
Test name
Test status
Simulation time 1405824672 ps
CPU time 5.61 seconds
Started Jun 30 05:06:06 PM PDT 24
Finished Jun 30 05:06:13 PM PDT 24
Peak memory 200256 kb
Host smart-7955d5c5-10ba-48e9-8b50-9ce3122e9ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641895229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.641895229
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3910270211
Short name T251
Test name
Test status
Simulation time 175035420 ps
CPU time 1.26 seconds
Started Jun 30 05:06:05 PM PDT 24
Finished Jun 30 05:06:07 PM PDT 24
Peak memory 200016 kb
Host smart-8898741f-cfdd-4246-bde3-1eb83a3dc03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910270211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3910270211
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.656134520
Short name T247
Test name
Test status
Simulation time 197440130 ps
CPU time 1.44 seconds
Started Jun 30 05:06:19 PM PDT 24
Finished Jun 30 05:06:20 PM PDT 24
Peak memory 200192 kb
Host smart-33dc9ee5-1db7-4e71-a326-58b1a0ce4642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656134520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.656134520
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.784133306
Short name T115
Test name
Test status
Simulation time 3285797240 ps
CPU time 12.27 seconds
Started Jun 30 05:06:07 PM PDT 24
Finished Jun 30 05:06:20 PM PDT 24
Peak memory 208572 kb
Host smart-15b3821b-7c59-442d-8ca1-fc0fc25df03b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784133306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.784133306
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1005848684
Short name T276
Test name
Test status
Simulation time 141619302 ps
CPU time 1.85 seconds
Started Jun 30 05:06:06 PM PDT 24
Finished Jun 30 05:06:09 PM PDT 24
Peak memory 200012 kb
Host smart-212c32a5-9a31-474d-a7e8-7e34e0a20484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005848684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1005848684
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.27970596
Short name T384
Test name
Test status
Simulation time 62397358 ps
CPU time 0.79 seconds
Started Jun 30 05:06:08 PM PDT 24
Finished Jun 30 05:06:11 PM PDT 24
Peak memory 200004 kb
Host smart-92560088-4111-4d44-a89f-a0ae538127aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27970596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.27970596
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2041121941
Short name T377
Test name
Test status
Simulation time 69493339 ps
CPU time 0.76 seconds
Started Jun 30 05:06:15 PM PDT 24
Finished Jun 30 05:06:17 PM PDT 24
Peak memory 199804 kb
Host smart-4844e254-198f-4121-bc01-c5f56953a07f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041121941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2041121941
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.901509340
Short name T34
Test name
Test status
Simulation time 1222409453 ps
CPU time 5.61 seconds
Started Jun 30 05:06:14 PM PDT 24
Finished Jun 30 05:06:21 PM PDT 24
Peak memory 217140 kb
Host smart-2d872592-a1ea-4704-bfc4-5b2ea3400c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901509340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.901509340
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3302926300
Short name T365
Test name
Test status
Simulation time 244106920 ps
CPU time 1.11 seconds
Started Jun 30 05:06:14 PM PDT 24
Finished Jun 30 05:06:16 PM PDT 24
Peak memory 217384 kb
Host smart-79eb0cf8-5ba2-4287-ad11-fc887ad9f5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302926300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3302926300
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.616578220
Short name T311
Test name
Test status
Simulation time 145947479 ps
CPU time 0.82 seconds
Started Jun 30 05:06:08 PM PDT 24
Finished Jun 30 05:06:11 PM PDT 24
Peak memory 199804 kb
Host smart-731400a4-1053-41ad-bdf4-90874c3e5ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616578220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.616578220
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3956739703
Short name T105
Test name
Test status
Simulation time 1349009086 ps
CPU time 5.21 seconds
Started Jun 30 05:06:05 PM PDT 24
Finished Jun 30 05:06:11 PM PDT 24
Peak memory 200244 kb
Host smart-7034a958-3537-45ff-b7f4-8a58bb0427cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956739703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3956739703
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1397923632
Short name T154
Test name
Test status
Simulation time 184120354 ps
CPU time 1.21 seconds
Started Jun 30 05:06:08 PM PDT 24
Finished Jun 30 05:06:11 PM PDT 24
Peak memory 200000 kb
Host smart-1a4af7a6-f13a-453c-b1b1-748f020ce10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397923632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1397923632
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.4221923621
Short name T332
Test name
Test status
Simulation time 200905400 ps
CPU time 1.41 seconds
Started Jun 30 05:06:06 PM PDT 24
Finished Jun 30 05:06:09 PM PDT 24
Peak memory 200200 kb
Host smart-e06ff71b-07cf-444a-9448-ebbe483bcf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221923621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.4221923621
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.576477997
Short name T282
Test name
Test status
Simulation time 7974006401 ps
CPU time 37.62 seconds
Started Jun 30 05:06:19 PM PDT 24
Finished Jun 30 05:06:57 PM PDT 24
Peak memory 208568 kb
Host smart-d5cb9d37-0896-4810-b500-c4ed57eec0c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576477997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.576477997
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3742522568
Short name T222
Test name
Test status
Simulation time 468121213 ps
CPU time 2.57 seconds
Started Jun 30 05:06:06 PM PDT 24
Finished Jun 30 05:06:10 PM PDT 24
Peak memory 199988 kb
Host smart-49fde530-5352-44d8-9ba5-8f35faed8d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742522568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3742522568
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.319440327
Short name T532
Test name
Test status
Simulation time 127540576 ps
CPU time 1.06 seconds
Started Jun 30 05:06:07 PM PDT 24
Finished Jun 30 05:06:09 PM PDT 24
Peak memory 199996 kb
Host smart-dd97d323-2311-447a-91a9-b0f742a8285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319440327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.319440327
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1087987920
Short name T192
Test name
Test status
Simulation time 95397372 ps
CPU time 0.85 seconds
Started Jun 30 05:06:14 PM PDT 24
Finished Jun 30 05:06:16 PM PDT 24
Peak memory 199808 kb
Host smart-e3a1a430-4bde-4aba-8768-83a0302e8ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087987920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1087987920
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3260992501
Short name T526
Test name
Test status
Simulation time 2153333953 ps
CPU time 7.59 seconds
Started Jun 30 05:06:14 PM PDT 24
Finished Jun 30 05:06:22 PM PDT 24
Peak memory 216848 kb
Host smart-55feb566-047f-4049-860f-198ec5826bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260992501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3260992501
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3291761631
Short name T441
Test name
Test status
Simulation time 243951169 ps
CPU time 1.17 seconds
Started Jun 30 05:06:14 PM PDT 24
Finished Jun 30 05:06:16 PM PDT 24
Peak memory 217372 kb
Host smart-44a803f7-71a6-4668-a406-741844b98490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291761631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3291761631
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1097370470
Short name T502
Test name
Test status
Simulation time 103541015 ps
CPU time 0.79 seconds
Started Jun 30 05:06:13 PM PDT 24
Finished Jun 30 05:06:15 PM PDT 24
Peak memory 199816 kb
Host smart-5d8b18c5-9a27-4b3a-9c33-5b61c1a525ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097370470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1097370470
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1113842579
Short name T319
Test name
Test status
Simulation time 1214580811 ps
CPU time 4.85 seconds
Started Jun 30 05:06:14 PM PDT 24
Finished Jun 30 05:06:20 PM PDT 24
Peak memory 200324 kb
Host smart-b1abb4ea-b85f-4c34-923e-1232dc0619f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113842579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1113842579
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.534366318
Short name T152
Test name
Test status
Simulation time 150288554 ps
CPU time 1.21 seconds
Started Jun 30 05:06:14 PM PDT 24
Finished Jun 30 05:06:16 PM PDT 24
Peak memory 200316 kb
Host smart-efd4ed62-8e18-482d-9bad-64518d1f929b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534366318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.534366318
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3330208722
Short name T167
Test name
Test status
Simulation time 260233396 ps
CPU time 1.57 seconds
Started Jun 30 05:06:13 PM PDT 24
Finished Jun 30 05:06:15 PM PDT 24
Peak memory 200204 kb
Host smart-6742d49f-ef18-4545-bfc3-a6359532fc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330208722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3330208722
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1598254384
Short name T181
Test name
Test status
Simulation time 6016751664 ps
CPU time 22.87 seconds
Started Jun 30 05:06:14 PM PDT 24
Finished Jun 30 05:06:38 PM PDT 24
Peak memory 200652 kb
Host smart-ae108bdf-8f48-4a45-ac03-675912609ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598254384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1598254384
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3311934118
Short name T397
Test name
Test status
Simulation time 365533874 ps
CPU time 2.3 seconds
Started Jun 30 05:06:13 PM PDT 24
Finished Jun 30 05:06:16 PM PDT 24
Peak memory 199932 kb
Host smart-a85a09a8-7e99-4c61-ad8f-729cd6c343a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311934118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3311934118
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2334684308
Short name T193
Test name
Test status
Simulation time 75664069 ps
CPU time 0.84 seconds
Started Jun 30 05:06:14 PM PDT 24
Finished Jun 30 05:06:16 PM PDT 24
Peak memory 199992 kb
Host smart-ea799cd8-2052-4f85-8aea-dbc7d5737ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334684308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2334684308
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2612473131
Short name T455
Test name
Test status
Simulation time 74165770 ps
CPU time 0.86 seconds
Started Jun 30 05:06:13 PM PDT 24
Finished Jun 30 05:06:15 PM PDT 24
Peak memory 199804 kb
Host smart-534351d1-4c2e-4798-8cb7-0fc8be6a4cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612473131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2612473131
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1477738111
Short name T44
Test name
Test status
Simulation time 1888289098 ps
CPU time 7.39 seconds
Started Jun 30 05:06:15 PM PDT 24
Finished Jun 30 05:06:23 PM PDT 24
Peak memory 217432 kb
Host smart-7792bd64-94a6-46ab-b8f2-414496b93b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477738111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1477738111
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3963854890
Short name T175
Test name
Test status
Simulation time 244358040 ps
CPU time 1.05 seconds
Started Jun 30 05:06:12 PM PDT 24
Finished Jun 30 05:06:14 PM PDT 24
Peak memory 217424 kb
Host smart-3b9787e8-c8d3-4de2-b849-d27e7f3bd986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963854890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3963854890
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1440494060
Short name T530
Test name
Test status
Simulation time 134992944 ps
CPU time 0.95 seconds
Started Jun 30 05:06:15 PM PDT 24
Finished Jun 30 05:06:17 PM PDT 24
Peak memory 199804 kb
Host smart-9d6ddad4-dfd9-49a3-a144-e662f651e90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440494060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1440494060
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3484586299
Short name T47
Test name
Test status
Simulation time 1531798169 ps
CPU time 6.75 seconds
Started Jun 30 05:06:15 PM PDT 24
Finished Jun 30 05:06:22 PM PDT 24
Peak memory 200248 kb
Host smart-dcde5c16-1826-4c89-bc62-3be065520dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484586299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3484586299
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2546374574
Short name T343
Test name
Test status
Simulation time 175778865 ps
CPU time 1.22 seconds
Started Jun 30 05:06:15 PM PDT 24
Finished Jun 30 05:06:17 PM PDT 24
Peak memory 200016 kb
Host smart-043da638-7b95-4329-bff1-b6eb44bc081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546374574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2546374574
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4199026676
Short name T386
Test name
Test status
Simulation time 124828710 ps
CPU time 1.21 seconds
Started Jun 30 05:06:14 PM PDT 24
Finished Jun 30 05:06:17 PM PDT 24
Peak memory 200188 kb
Host smart-e1abaa8c-4c23-4a0f-9f3a-c1d9c56dc893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199026676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4199026676
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3857255432
Short name T111
Test name
Test status
Simulation time 4218435937 ps
CPU time 14.38 seconds
Started Jun 30 05:06:14 PM PDT 24
Finished Jun 30 05:06:29 PM PDT 24
Peak memory 208528 kb
Host smart-e48f3af8-a6c4-4337-add9-569c3a5c7237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857255432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3857255432
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2542132812
Short name T145
Test name
Test status
Simulation time 380574596 ps
CPU time 2.34 seconds
Started Jun 30 05:06:15 PM PDT 24
Finished Jun 30 05:06:18 PM PDT 24
Peak memory 199996 kb
Host smart-72a2b435-5aea-4729-9bd8-7c0ebb875098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542132812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2542132812
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1009879
Short name T24
Test name
Test status
Simulation time 247079533 ps
CPU time 1.46 seconds
Started Jun 30 05:06:15 PM PDT 24
Finished Jun 30 05:06:17 PM PDT 24
Peak memory 199992 kb
Host smart-de4e25b6-c21c-485b-88a6-cbfd7003d401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1009879
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1179360015
Short name T284
Test name
Test status
Simulation time 70908899 ps
CPU time 0.78 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:06:22 PM PDT 24
Peak memory 199808 kb
Host smart-ada663dd-e810-472d-8773-1636a5f3a07a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179360015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1179360015
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2533018155
Short name T309
Test name
Test status
Simulation time 1897832584 ps
CPU time 7.11 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:06:28 PM PDT 24
Peak memory 217460 kb
Host smart-f5442bfa-98e3-4589-a5d6-014ea8ead6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533018155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2533018155
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4195585175
Short name T438
Test name
Test status
Simulation time 244232850 ps
CPU time 1.18 seconds
Started Jun 30 05:06:23 PM PDT 24
Finished Jun 30 05:06:25 PM PDT 24
Peak memory 217392 kb
Host smart-0d1eb353-9bbe-4784-8959-0df54058c4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195585175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4195585175
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.545718975
Short name T423
Test name
Test status
Simulation time 104865943 ps
CPU time 0.81 seconds
Started Jun 30 05:06:19 PM PDT 24
Finished Jun 30 05:06:20 PM PDT 24
Peak memory 199816 kb
Host smart-0e1e4eb4-6eee-4dcf-a461-11db63d23a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545718975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.545718975
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.928260221
Short name T499
Test name
Test status
Simulation time 1685133269 ps
CPU time 6.33 seconds
Started Jun 30 05:06:13 PM PDT 24
Finished Jun 30 05:06:20 PM PDT 24
Peak memory 200276 kb
Host smart-e818617f-b4c1-4f02-8649-c71a14b0f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928260221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.928260221
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2296347937
Short name T367
Test name
Test status
Simulation time 168447854 ps
CPU time 1.12 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:06:22 PM PDT 24
Peak memory 200012 kb
Host smart-451ca7e0-39de-4a6f-9f08-a733c8d4368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296347937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2296347937
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4252040018
Short name T290
Test name
Test status
Simulation time 195243339 ps
CPU time 1.44 seconds
Started Jun 30 05:06:19 PM PDT 24
Finished Jun 30 05:06:20 PM PDT 24
Peak memory 200196 kb
Host smart-367157a8-e1a8-41b5-b753-a2881993982d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252040018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4252040018
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1554248062
Short name T494
Test name
Test status
Simulation time 8856174980 ps
CPU time 34.51 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:06:55 PM PDT 24
Peak memory 208512 kb
Host smart-8d10968a-fa22-4e34-bcec-4ab9c572d056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554248062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1554248062
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1388376495
Short name T197
Test name
Test status
Simulation time 491695743 ps
CPU time 2.63 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:06:25 PM PDT 24
Peak memory 199972 kb
Host smart-c5b35c7d-f460-4f92-91d0-817f141cbb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388376495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1388376495
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.381443196
Short name T509
Test name
Test status
Simulation time 127620736 ps
CPU time 1.07 seconds
Started Jun 30 05:06:22 PM PDT 24
Finished Jun 30 05:06:25 PM PDT 24
Peak memory 200004 kb
Host smart-bbc73806-2ab2-448d-ac92-6b928ecec0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381443196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.381443196
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.715188430
Short name T81
Test name
Test status
Simulation time 65938394 ps
CPU time 0.72 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:06:21 PM PDT 24
Peak memory 199784 kb
Host smart-082f35fb-dab7-46b8-9a07-f5c6600d5f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715188430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.715188430
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.422479750
Short name T291
Test name
Test status
Simulation time 1900582140 ps
CPU time 8.02 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:06:30 PM PDT 24
Peak memory 217456 kb
Host smart-5e622b77-764c-4163-8242-ff28e4a4c759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422479750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.422479750
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1135754146
Short name T146
Test name
Test status
Simulation time 244606929 ps
CPU time 1.2 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:06:22 PM PDT 24
Peak memory 217312 kb
Host smart-746f9b25-8a2e-4d26-a099-a3ed643952c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135754146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1135754146
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3738752751
Short name T18
Test name
Test status
Simulation time 109742972 ps
CPU time 0.86 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:06:24 PM PDT 24
Peak memory 199788 kb
Host smart-bedbfa8e-86d0-4bf4-a150-4237e87cf4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738752751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3738752751
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.985010244
Short name T183
Test name
Test status
Simulation time 910532720 ps
CPU time 4.59 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:06:27 PM PDT 24
Peak memory 200264 kb
Host smart-b72634ca-f1ae-410e-a13d-0d563e0caf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985010244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.985010244
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.989300944
Short name T470
Test name
Test status
Simulation time 102155658 ps
CPU time 1 seconds
Started Jun 30 05:06:22 PM PDT 24
Finished Jun 30 05:06:24 PM PDT 24
Peak memory 199924 kb
Host smart-83c398f3-e97c-4bab-9088-4ed70769a69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989300944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.989300944
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.6984159
Short name T516
Test name
Test status
Simulation time 248523073 ps
CPU time 1.53 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:06:24 PM PDT 24
Peak memory 200228 kb
Host smart-4678790d-d164-486b-ad99-46d45d917ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6984159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.6984159
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2720319569
Short name T486
Test name
Test status
Simulation time 990254280 ps
CPU time 4.33 seconds
Started Jun 30 05:06:22 PM PDT 24
Finished Jun 30 05:06:27 PM PDT 24
Peak memory 200268 kb
Host smart-46bec879-1f92-44ae-ab2d-f87f656024ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720319569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2720319569
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1721871200
Short name T237
Test name
Test status
Simulation time 467817323 ps
CPU time 2.62 seconds
Started Jun 30 05:06:26 PM PDT 24
Finished Jun 30 05:06:30 PM PDT 24
Peak memory 200008 kb
Host smart-771ac7ad-d3b6-474e-bf72-15cbcc91d8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721871200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1721871200
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1518242796
Short name T312
Test name
Test status
Simulation time 85564926 ps
CPU time 0.85 seconds
Started Jun 30 05:06:24 PM PDT 24
Finished Jun 30 05:06:25 PM PDT 24
Peak memory 200032 kb
Host smart-40e7fecc-d083-4b55-a2eb-3ac90e546865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518242796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1518242796
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2656276470
Short name T212
Test name
Test status
Simulation time 67244315 ps
CPU time 0.79 seconds
Started Jun 30 05:06:22 PM PDT 24
Finished Jun 30 05:06:24 PM PDT 24
Peak memory 199788 kb
Host smart-0ca9d029-58f6-40d9-8d09-36281b3d5f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656276470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2656276470
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2852446223
Short name T28
Test name
Test status
Simulation time 1900344786 ps
CPU time 7.16 seconds
Started Jun 30 05:06:22 PM PDT 24
Finished Jun 30 05:06:30 PM PDT 24
Peak memory 217624 kb
Host smart-f81a3c62-7bfe-4716-b113-05402194ff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852446223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2852446223
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.988927098
Short name T492
Test name
Test status
Simulation time 244942294 ps
CPU time 1.15 seconds
Started Jun 30 05:06:24 PM PDT 24
Finished Jun 30 05:06:26 PM PDT 24
Peak memory 217368 kb
Host smart-9872429f-586e-400f-b380-1d366b1559fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988927098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.988927098
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.535270151
Short name T504
Test name
Test status
Simulation time 211485204 ps
CPU time 0.86 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:06:23 PM PDT 24
Peak memory 199812 kb
Host smart-4ef3b94e-f97f-44ed-899f-b8581554dedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535270151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.535270151
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3552067478
Short name T518
Test name
Test status
Simulation time 877704079 ps
CPU time 4.36 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:06:26 PM PDT 24
Peak memory 200252 kb
Host smart-9b64d32d-fd12-479e-92c1-6e329f7e8dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552067478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3552067478
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1508615048
Short name T498
Test name
Test status
Simulation time 152230619 ps
CPU time 1.14 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:06:22 PM PDT 24
Peak memory 200000 kb
Host smart-cb415951-aa27-430b-b4d8-53cc42023496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508615048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1508615048
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3994842854
Short name T519
Test name
Test status
Simulation time 191525307 ps
CPU time 1.36 seconds
Started Jun 30 05:06:25 PM PDT 24
Finished Jun 30 05:06:27 PM PDT 24
Peak memory 200200 kb
Host smart-251a3da3-c07a-4765-8b52-115198fcb290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994842854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3994842854
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1385425324
Short name T60
Test name
Test status
Simulation time 12679460973 ps
CPU time 46.91 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:07:09 PM PDT 24
Peak memory 208512 kb
Host smart-abb3c1d9-2d58-4d06-b799-ba9917ef2128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385425324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1385425324
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3745472411
Short name T287
Test name
Test status
Simulation time 141526910 ps
CPU time 1.79 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:06:24 PM PDT 24
Peak memory 200020 kb
Host smart-e0db15ec-8f95-43fb-9079-7e2d37deaee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745472411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3745472411
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.356595433
Short name T289
Test name
Test status
Simulation time 110367262 ps
CPU time 1.03 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:06:22 PM PDT 24
Peak memory 199992 kb
Host smart-9793aa50-cd74-48c4-9147-dd5cfe2149ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356595433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.356595433
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1464968585
Short name T255
Test name
Test status
Simulation time 65490404 ps
CPU time 0.76 seconds
Started Jun 30 05:04:48 PM PDT 24
Finished Jun 30 05:04:49 PM PDT 24
Peak memory 199752 kb
Host smart-34ce2001-4c2e-46a2-a751-6ca697a48e78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464968585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1464968585
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3240422697
Short name T354
Test name
Test status
Simulation time 1892089917 ps
CPU time 7.55 seconds
Started Jun 30 05:04:46 PM PDT 24
Finished Jun 30 05:04:54 PM PDT 24
Peak memory 217960 kb
Host smart-ecd7a692-8dfc-4c13-b5d1-3ab9ddccf92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240422697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3240422697
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3447397502
Short name T429
Test name
Test status
Simulation time 243915799 ps
CPU time 1.15 seconds
Started Jun 30 05:04:45 PM PDT 24
Finished Jun 30 05:04:47 PM PDT 24
Peak memory 217340 kb
Host smart-32b2f7b2-0f89-45dd-8c3f-cedaa1ce155a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447397502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3447397502
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.738905954
Short name T272
Test name
Test status
Simulation time 143124553 ps
CPU time 0.81 seconds
Started Jun 30 05:04:44 PM PDT 24
Finished Jun 30 05:04:46 PM PDT 24
Peak memory 199804 kb
Host smart-ac2b25b4-d7ef-43d1-985e-ec2415a1a093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738905954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.738905954
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2646288812
Short name T268
Test name
Test status
Simulation time 786167591 ps
CPU time 4.03 seconds
Started Jun 30 05:04:43 PM PDT 24
Finished Jun 30 05:04:47 PM PDT 24
Peak memory 200164 kb
Host smart-09a1ee67-1d7f-4dc3-b666-c1b21cda1ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646288812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2646288812
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1867538212
Short name T198
Test name
Test status
Simulation time 105203912 ps
CPU time 1.07 seconds
Started Jun 30 05:04:45 PM PDT 24
Finished Jun 30 05:04:47 PM PDT 24
Peak memory 200004 kb
Host smart-17c22f7c-98d9-4e15-a5fa-38fb9d0d2458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867538212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1867538212
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.359406144
Short name T95
Test name
Test status
Simulation time 112357663 ps
CPU time 1.16 seconds
Started Jun 30 05:04:35 PM PDT 24
Finished Jun 30 05:04:37 PM PDT 24
Peak memory 200236 kb
Host smart-c4243888-f3c9-4fac-8832-1474c01ad509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359406144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.359406144
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2187911304
Short name T469
Test name
Test status
Simulation time 10530658542 ps
CPU time 36.86 seconds
Started Jun 30 05:04:45 PM PDT 24
Finished Jun 30 05:05:23 PM PDT 24
Peak memory 208520 kb
Host smart-32b8fc7f-c8ac-42da-83ad-0a5942a01d81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187911304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2187911304
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.709574251
Short name T458
Test name
Test status
Simulation time 417983560 ps
CPU time 2.2 seconds
Started Jun 30 05:04:45 PM PDT 24
Finished Jun 30 05:04:48 PM PDT 24
Peak memory 208204 kb
Host smart-a118f74f-7ad2-4544-ab8c-75968ee8f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709574251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.709574251
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.36684049
Short name T427
Test name
Test status
Simulation time 97409015 ps
CPU time 0.93 seconds
Started Jun 30 05:04:44 PM PDT 24
Finished Jun 30 05:04:45 PM PDT 24
Peak memory 200008 kb
Host smart-33b34352-c4a0-42a3-9e37-a2b1fcacae44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36684049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.36684049
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.4265476380
Short name T349
Test name
Test status
Simulation time 83614892 ps
CPU time 0.8 seconds
Started Jun 30 05:04:48 PM PDT 24
Finished Jun 30 05:04:49 PM PDT 24
Peak memory 199752 kb
Host smart-0e9cb35e-d1b6-4c9f-bf9e-84c5362d3929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265476380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.4265476380
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3930350599
Short name T33
Test name
Test status
Simulation time 1211831090 ps
CPU time 6.4 seconds
Started Jun 30 05:04:46 PM PDT 24
Finished Jun 30 05:04:54 PM PDT 24
Peak memory 221600 kb
Host smart-0f0498cb-92f6-4b27-91f9-45611012ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930350599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3930350599
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1032409279
Short name T149
Test name
Test status
Simulation time 243738902 ps
CPU time 1.04 seconds
Started Jun 30 05:04:44 PM PDT 24
Finished Jun 30 05:04:45 PM PDT 24
Peak memory 217392 kb
Host smart-bdd8a12b-e044-4724-a704-d8fd2a2d470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032409279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1032409279
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.435245201
Short name T505
Test name
Test status
Simulation time 244827997 ps
CPU time 0.99 seconds
Started Jun 30 05:04:44 PM PDT 24
Finished Jun 30 05:04:45 PM PDT 24
Peak memory 199800 kb
Host smart-a741f417-cd56-4020-bdfe-3f67ccdbc3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435245201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.435245201
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1967036326
Short name T485
Test name
Test status
Simulation time 2027378916 ps
CPU time 7.31 seconds
Started Jun 30 05:04:45 PM PDT 24
Finished Jun 30 05:04:53 PM PDT 24
Peak memory 200300 kb
Host smart-8e3fa4f8-8c0e-4ed0-aec7-ba284c884556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967036326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1967036326
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3113584378
Short name T381
Test name
Test status
Simulation time 181870950 ps
CPU time 1.24 seconds
Started Jun 30 05:04:45 PM PDT 24
Finished Jun 30 05:04:47 PM PDT 24
Peak memory 199896 kb
Host smart-1d0cff93-bd76-4592-90a3-c44f30b51513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113584378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3113584378
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.56679562
Short name T135
Test name
Test status
Simulation time 265985023 ps
CPU time 1.48 seconds
Started Jun 30 05:04:44 PM PDT 24
Finished Jun 30 05:04:46 PM PDT 24
Peak memory 200228 kb
Host smart-a7a6f96f-6009-44eb-93eb-51a974960631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56679562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.56679562
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3804240507
Short name T433
Test name
Test status
Simulation time 2533510626 ps
CPU time 10.31 seconds
Started Jun 30 05:04:45 PM PDT 24
Finished Jun 30 05:04:57 PM PDT 24
Peak memory 216644 kb
Host smart-c3427390-103c-42c4-a9ae-97b848a32da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804240507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3804240507
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2897014778
Short name T259
Test name
Test status
Simulation time 159776236 ps
CPU time 2.04 seconds
Started Jun 30 05:04:45 PM PDT 24
Finished Jun 30 05:04:48 PM PDT 24
Peak memory 199988 kb
Host smart-fb79cd13-98f5-45b1-93a2-d311e4de4468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897014778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2897014778
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2077222539
Short name T207
Test name
Test status
Simulation time 276581866 ps
CPU time 1.61 seconds
Started Jun 30 05:04:45 PM PDT 24
Finished Jun 30 05:04:47 PM PDT 24
Peak memory 200012 kb
Host smart-8e086b8b-c3af-4b8f-8824-246e7452d1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077222539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2077222539
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.4171002299
Short name T347
Test name
Test status
Simulation time 74031324 ps
CPU time 0.76 seconds
Started Jun 30 05:04:57 PM PDT 24
Finished Jun 30 05:04:58 PM PDT 24
Peak memory 199712 kb
Host smart-8a8fb0cf-6719-4d19-95a7-00bac0228f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171002299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.4171002299
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3539100839
Short name T481
Test name
Test status
Simulation time 1922715076 ps
CPU time 8.15 seconds
Started Jun 30 05:04:54 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 217408 kb
Host smart-d0e6e42c-eeb9-4b6b-af74-38ee25198ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539100839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3539100839
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3123540521
Short name T412
Test name
Test status
Simulation time 243788042 ps
CPU time 1.18 seconds
Started Jun 30 05:04:54 PM PDT 24
Finished Jun 30 05:04:56 PM PDT 24
Peak memory 217348 kb
Host smart-c8eccd91-d2a6-487d-9c91-5a230f18a0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123540521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3123540521
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1201078434
Short name T15
Test name
Test status
Simulation time 105358778 ps
CPU time 0.78 seconds
Started Jun 30 05:04:46 PM PDT 24
Finished Jun 30 05:04:48 PM PDT 24
Peak memory 199780 kb
Host smart-f1b31b07-90ac-40ef-b55e-bb2f65bc1ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201078434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1201078434
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2070836779
Short name T116
Test name
Test status
Simulation time 959906027 ps
CPU time 4.62 seconds
Started Jun 30 05:04:46 PM PDT 24
Finished Jun 30 05:04:52 PM PDT 24
Peak memory 200280 kb
Host smart-cd2c4da3-983b-47d8-89e2-2314299d6f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070836779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2070836779
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.613182580
Short name T299
Test name
Test status
Simulation time 158404007 ps
CPU time 1.18 seconds
Started Jun 30 05:04:59 PM PDT 24
Finished Jun 30 05:05:00 PM PDT 24
Peak memory 200012 kb
Host smart-61081e02-94b9-43b8-9df2-fe1a37686996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613182580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.613182580
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4286450573
Short name T3
Test name
Test status
Simulation time 120906205 ps
CPU time 1.25 seconds
Started Jun 30 05:04:46 PM PDT 24
Finished Jun 30 05:04:48 PM PDT 24
Peak memory 200200 kb
Host smart-29c8be95-364a-4d54-9b40-f297f19488e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286450573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4286450573
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1293089621
Short name T462
Test name
Test status
Simulation time 7742675862 ps
CPU time 27.27 seconds
Started Jun 30 05:04:55 PM PDT 24
Finished Jun 30 05:05:23 PM PDT 24
Peak memory 208524 kb
Host smart-6a3bd701-4c9f-4143-94bb-914428a62dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293089621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1293089621
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.593847066
Short name T358
Test name
Test status
Simulation time 341190330 ps
CPU time 2.3 seconds
Started Jun 30 05:04:43 PM PDT 24
Finished Jun 30 05:04:45 PM PDT 24
Peak memory 199920 kb
Host smart-108cc885-66b2-4c6b-90cc-773bea1bf262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593847066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.593847066
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.660724059
Short name T459
Test name
Test status
Simulation time 157662526 ps
CPU time 1.11 seconds
Started Jun 30 05:04:45 PM PDT 24
Finished Jun 30 05:04:47 PM PDT 24
Peak memory 200024 kb
Host smart-dbb7f7fc-9574-4f21-8f47-385b3304344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660724059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.660724059
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2731161778
Short name T435
Test name
Test status
Simulation time 78324408 ps
CPU time 0.84 seconds
Started Jun 30 05:04:55 PM PDT 24
Finished Jun 30 05:04:57 PM PDT 24
Peak memory 199808 kb
Host smart-a1e141d0-703b-4d53-8eef-3a064880f8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731161778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2731161778
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2424368407
Short name T417
Test name
Test status
Simulation time 1218795248 ps
CPU time 6.2 seconds
Started Jun 30 05:04:57 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 217704 kb
Host smart-0164d073-33f3-423b-b60f-f8baa712debf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424368407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2424368407
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.831301061
Short name T151
Test name
Test status
Simulation time 244149959 ps
CPU time 1.07 seconds
Started Jun 30 05:04:56 PM PDT 24
Finished Jun 30 05:04:58 PM PDT 24
Peak memory 217356 kb
Host smart-7673de78-65e9-4aef-9421-89076fb18b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831301061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.831301061
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.228695841
Short name T271
Test name
Test status
Simulation time 168494115 ps
CPU time 0.84 seconds
Started Jun 30 05:04:58 PM PDT 24
Finished Jun 30 05:04:59 PM PDT 24
Peak memory 199732 kb
Host smart-f13a42d7-bb06-469a-85a5-bbf58ae95662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228695841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.228695841
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3802327234
Short name T325
Test name
Test status
Simulation time 1139664659 ps
CPU time 5.25 seconds
Started Jun 30 05:04:59 PM PDT 24
Finished Jun 30 05:05:04 PM PDT 24
Peak memory 200304 kb
Host smart-6577195d-adba-4882-bc7a-89e239d3771b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802327234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3802327234
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.206843857
Short name T144
Test name
Test status
Simulation time 152571301 ps
CPU time 1.15 seconds
Started Jun 30 05:04:54 PM PDT 24
Finished Jun 30 05:04:56 PM PDT 24
Peak memory 200016 kb
Host smart-b554e572-d6e6-4896-887a-2c3c6334d449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206843857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.206843857
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.738995703
Short name T93
Test name
Test status
Simulation time 111663528 ps
CPU time 1.17 seconds
Started Jun 30 05:04:55 PM PDT 24
Finished Jun 30 05:04:57 PM PDT 24
Peak memory 200216 kb
Host smart-f59f4b6b-db05-4c32-9a97-04f2165d4598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738995703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.738995703
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.4012560649
Short name T92
Test name
Test status
Simulation time 6022379070 ps
CPU time 23.99 seconds
Started Jun 30 05:04:54 PM PDT 24
Finished Jun 30 05:05:19 PM PDT 24
Peak memory 200292 kb
Host smart-ed2e3f3f-eceb-4434-95a0-d370a8a5f178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012560649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4012560649
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3344894204
Short name T82
Test name
Test status
Simulation time 143692238 ps
CPU time 1.69 seconds
Started Jun 30 05:04:56 PM PDT 24
Finished Jun 30 05:04:58 PM PDT 24
Peak memory 199992 kb
Host smart-305248be-689b-4d1a-a523-f775cbe7e0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344894204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3344894204
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2410248955
Short name T189
Test name
Test status
Simulation time 170358109 ps
CPU time 1.23 seconds
Started Jun 30 05:04:55 PM PDT 24
Finished Jun 30 05:04:57 PM PDT 24
Peak memory 199968 kb
Host smart-dc9a41c5-6765-4153-acb3-6aaa15fbd7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410248955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2410248955
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.327298753
Short name T228
Test name
Test status
Simulation time 78817401 ps
CPU time 0.8 seconds
Started Jun 30 05:04:58 PM PDT 24
Finished Jun 30 05:04:59 PM PDT 24
Peak memory 199748 kb
Host smart-e32ac4fe-f4ea-4ce1-8589-24d1bfd5ccb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327298753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.327298753
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.556804008
Short name T305
Test name
Test status
Simulation time 2370889244 ps
CPU time 8.06 seconds
Started Jun 30 05:04:55 PM PDT 24
Finished Jun 30 05:05:04 PM PDT 24
Peak memory 221620 kb
Host smart-524af533-1896-4e39-9671-76a27cbfe819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556804008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.556804008
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2410476316
Short name T391
Test name
Test status
Simulation time 244368251 ps
CPU time 1.05 seconds
Started Jun 30 05:04:54 PM PDT 24
Finished Jun 30 05:04:56 PM PDT 24
Peak memory 217352 kb
Host smart-9361984d-a59a-44bd-b4a7-7e67f9611acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410476316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2410476316
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1024444442
Short name T188
Test name
Test status
Simulation time 111956977 ps
CPU time 0.77 seconds
Started Jun 30 05:04:57 PM PDT 24
Finished Jun 30 05:04:58 PM PDT 24
Peak memory 199828 kb
Host smart-3649693c-14f3-4250-933b-59955fc1c81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024444442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1024444442
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.299248956
Short name T211
Test name
Test status
Simulation time 1738136412 ps
CPU time 6.35 seconds
Started Jun 30 05:04:58 PM PDT 24
Finished Jun 30 05:05:05 PM PDT 24
Peak memory 200192 kb
Host smart-7cc78749-2b6c-48f7-b211-ad44c28f8d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299248956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.299248956
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1046575316
Short name T49
Test name
Test status
Simulation time 151608783 ps
CPU time 1.12 seconds
Started Jun 30 05:04:54 PM PDT 24
Finished Jun 30 05:04:56 PM PDT 24
Peak memory 199916 kb
Host smart-c592377f-4869-47f2-8c9f-58bb127103cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046575316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1046575316
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3768900312
Short name T366
Test name
Test status
Simulation time 121328868 ps
CPU time 1.18 seconds
Started Jun 30 05:04:53 PM PDT 24
Finished Jun 30 05:04:55 PM PDT 24
Peak memory 200200 kb
Host smart-0613cf75-bd84-4208-a4c1-604ec5dbb2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768900312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3768900312
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3073925709
Short name T232
Test name
Test status
Simulation time 9627694885 ps
CPU time 39.42 seconds
Started Jun 30 05:04:59 PM PDT 24
Finished Jun 30 05:05:39 PM PDT 24
Peak memory 216672 kb
Host smart-7b1d2fb6-3d19-4f33-bde8-fa516d02910c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073925709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3073925709
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3554414304
Short name T474
Test name
Test status
Simulation time 361035768 ps
CPU time 2.06 seconds
Started Jun 30 05:04:54 PM PDT 24
Finished Jun 30 05:04:56 PM PDT 24
Peak memory 200004 kb
Host smart-8088c669-34e5-4d4e-98c8-7ce20fbcd318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554414304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3554414304
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.658147239
Short name T425
Test name
Test status
Simulation time 136739011 ps
CPU time 1.21 seconds
Started Jun 30 05:04:54 PM PDT 24
Finished Jun 30 05:04:56 PM PDT 24
Peak memory 199968 kb
Host smart-0e662212-4d1e-4a58-8b6a-9be74b35958c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658147239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.658147239
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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