Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8074

1

T1

9

T6

34

T7

38

auto[1]

11280

1

T1

1

T4

1

T6

38

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5970	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6526	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3028	1			T6	7		T7	10		T9	9
reset_info_cp[4]	3937	1			T6	15		T7	10		T9	11
reset_info_cp[8]	115	1			T11	1		T12	3		T36	1
reset_info_cp[16]	103	1			T1	1		T12	3		T36	1
reset_info_cp[32]	95	1			T8	1		T9	1		T11	1
reset_info_cp[64]	103	1			T12	3		T36	1		T38	1
reset_info_cp[128]	97	1			T7	1		T8	1		T9	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3059	1			T6	11		T7	14		T9	9
reset_info_cp[1]	auto[1]	2847	1			T6	13		T7	6		T9	8
reset_info_cp[2]	auto[0]	960	1			T6	1		T7	5		T9	6
reset_info_cp[2]	auto[1]	2068	1			T6	6		T7	5		T9	3
reset_info_cp[4]	auto[0]	1397	1			T6	8		T7	6		T9	5
reset_info_cp[4]	auto[1]	2540	1			T6	7		T7	4		T9	6
reset_info_cp[8]	auto[0]	45	1			T11	1		T36	1		T38	2
reset_info_cp[8]	auto[1]	70	1			T12	3		T24	1		T48	1
reset_info_cp[16]	auto[0]	37	1			T1	1		T12	1		T36	1
reset_info_cp[16]	auto[1]	66	1			T12	2		T48	1		T26	1
reset_info_cp[32]	auto[0]	33	1			T8	1		T9	1		T11	1
reset_info_cp[32]	auto[1]	62	1			T12	1		T25	2		T26	2
reset_info_cp[64]	auto[0]	44	1			T12	1		T36	1		T38	1
reset_info_cp[64]	auto[1]	59	1			T12	2		T24	1		T48	1
reset_info_cp[128]	auto[0]	39	1			T7	1		T8	1		T9	1
reset_info_cp[128]	auto[1]	58	1			T52	1		T23	1		T48	1