Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3072523617 Jul 01 10:41:53 AM PDT 24 Jul 01 10:42:01 AM PDT 24 1241708040 ps
T539 /workspace/coverage/default/15.rstmgr_smoke.105563163 Jul 01 10:42:10 AM PDT 24 Jul 01 10:42:15 AM PDT 24 235334009 ps
T540 /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.28881078 Jul 01 10:42:56 AM PDT 24 Jul 01 10:42:58 AM PDT 24 131623195 ps
T541 /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2984002811 Jul 01 10:43:01 AM PDT 24 Jul 01 10:43:06 AM PDT 24 160409888 ps
T542 /workspace/coverage/default/38.rstmgr_stress_all.2755534189 Jul 01 10:43:01 AM PDT 24 Jul 01 10:43:34 AM PDT 24 8920019204 ps
T58 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1904325873 Jul 01 10:39:09 AM PDT 24 Jul 01 10:39:15 AM PDT 24 897705828 ps
T59 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.273446809 Jul 01 10:39:04 AM PDT 24 Jul 01 10:39:09 AM PDT 24 222330645 ps
T60 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4276290248 Jul 01 10:39:07 AM PDT 24 Jul 01 10:39:11 AM PDT 24 224446427 ps
T61 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3782893839 Jul 01 10:39:20 AM PDT 24 Jul 01 10:39:23 AM PDT 24 229447011 ps
T97 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1609166824 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:56 AM PDT 24 108315123 ps
T62 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3033402174 Jul 01 10:39:12 AM PDT 24 Jul 01 10:39:15 AM PDT 24 283205169 ps
T124 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3302257198 Jul 01 10:38:49 AM PDT 24 Jul 01 10:38:58 AM PDT 24 1559336243 ps
T63 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1117801000 Jul 01 10:38:59 AM PDT 24 Jul 01 10:39:02 AM PDT 24 118406168 ps
T125 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.429532194 Jul 01 10:38:56 AM PDT 24 Jul 01 10:39:00 AM PDT 24 460449040 ps
T543 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1389255391 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:56 AM PDT 24 70535997 ps
T65 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.539038243 Jul 01 10:39:10 AM PDT 24 Jul 01 10:39:14 AM PDT 24 685002929 ps
T64 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1507369760 Jul 01 10:38:57 AM PDT 24 Jul 01 10:38:58 AM PDT 24 169832198 ps
T98 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.23422192 Jul 01 10:38:55 AM PDT 24 Jul 01 10:38:57 AM PDT 24 210280712 ps
T544 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4188700331 Jul 01 10:38:54 AM PDT 24 Jul 01 10:38:56 AM PDT 24 73950827 ps
T84 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4164479633 Jul 01 10:38:49 AM PDT 24 Jul 01 10:38:51 AM PDT 24 160278002 ps
T85 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2613210721 Jul 01 10:38:51 AM PDT 24 Jul 01 10:38:54 AM PDT 24 175989634 ps
T86 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1375827226 Jul 01 10:38:57 AM PDT 24 Jul 01 10:39:01 AM PDT 24 926458676 ps
T545 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1666237353 Jul 01 10:38:51 AM PDT 24 Jul 01 10:38:54 AM PDT 24 77571675 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.73002541 Jul 01 10:38:52 AM PDT 24 Jul 01 10:38:55 AM PDT 24 195283084 ps
T99 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.46320290 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:35 AM PDT 24 78159207 ps
T100 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4143131803 Jul 01 10:39:24 AM PDT 24 Jul 01 10:39:27 AM PDT 24 186736340 ps
T87 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3128825043 Jul 01 10:39:00 AM PDT 24 Jul 01 10:39:02 AM PDT 24 108080675 ps
T101 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2055631001 Jul 01 10:39:17 AM PDT 24 Jul 01 10:39:19 AM PDT 24 148148024 ps
T88 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2815418837 Jul 01 10:39:07 AM PDT 24 Jul 01 10:39:11 AM PDT 24 140326600 ps
T89 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.240364520 Jul 01 10:39:59 AM PDT 24 Jul 01 10:40:02 AM PDT 24 119202459 ps
T90 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2688521585 Jul 01 10:39:23 AM PDT 24 Jul 01 10:39:26 AM PDT 24 185416913 ps
T547 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1597062497 Jul 01 10:39:33 AM PDT 24 Jul 01 10:39:48 AM PDT 24 481873851 ps
T548 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3737774942 Jul 01 10:39:40 AM PDT 24 Jul 01 10:39:45 AM PDT 24 67366862 ps
T107 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.482166174 Jul 01 10:40:18 AM PDT 24 Jul 01 10:40:25 AM PDT 24 778237085 ps
T106 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2233027929 Jul 01 10:39:22 AM PDT 24 Jul 01 10:39:25 AM PDT 24 418622619 ps
T102 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1845680577 Jul 01 10:39:13 AM PDT 24 Jul 01 10:39:17 AM PDT 24 266745491 ps
T549 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2466767554 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:06 AM PDT 24 75109600 ps
T103 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.972003994 Jul 01 10:39:00 AM PDT 24 Jul 01 10:39:02 AM PDT 24 82536684 ps
T105 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1065635532 Jul 01 10:39:04 AM PDT 24 Jul 01 10:39:10 AM PDT 24 195191532 ps
T550 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3300578335 Jul 01 10:39:01 AM PDT 24 Jul 01 10:39:03 AM PDT 24 124982595 ps
T114 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3441433918 Jul 01 10:39:00 AM PDT 24 Jul 01 10:39:04 AM PDT 24 370485869 ps
T551 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2986283265 Jul 01 10:39:11 AM PDT 24 Jul 01 10:39:14 AM PDT 24 153951482 ps
T104 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.470945772 Jul 01 10:39:08 AM PDT 24 Jul 01 10:39:12 AM PDT 24 85689660 ps
T552 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3873034141 Jul 01 10:40:32 AM PDT 24 Jul 01 10:40:34 AM PDT 24 69818006 ps
T553 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2735975472 Jul 01 10:38:59 AM PDT 24 Jul 01 10:39:02 AM PDT 24 314067607 ps
T554 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2133095648 Jul 01 10:39:31 AM PDT 24 Jul 01 10:39:34 AM PDT 24 108990822 ps
T555 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2521387587 Jul 01 10:39:29 AM PDT 24 Jul 01 10:39:33 AM PDT 24 441776267 ps
T556 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.706968140 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:43 AM PDT 24 192995887 ps
T557 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1001982079 Jul 01 10:39:04 AM PDT 24 Jul 01 10:39:10 AM PDT 24 475198485 ps
T108 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2081321531 Jul 01 10:39:28 AM PDT 24 Jul 01 10:39:31 AM PDT 24 482406913 ps
T558 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1961521083 Jul 01 10:38:54 AM PDT 24 Jul 01 10:38:56 AM PDT 24 115574345 ps
T559 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1144613798 Jul 01 10:39:35 AM PDT 24 Jul 01 10:39:39 AM PDT 24 57949843 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1294293439 Jul 01 10:38:39 AM PDT 24 Jul 01 10:38:41 AM PDT 24 66984833 ps
T561 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3218005267 Jul 01 10:38:57 AM PDT 24 Jul 01 10:39:00 AM PDT 24 450539426 ps
T109 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3432727821 Jul 01 10:39:06 AM PDT 24 Jul 01 10:39:10 AM PDT 24 430527510 ps
T562 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1861749007 Jul 01 10:38:42 AM PDT 24 Jul 01 10:38:44 AM PDT 24 467614972 ps
T563 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3476900400 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:56 AM PDT 24 101025632 ps
T564 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1657035450 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:08 AM PDT 24 288734333 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.832205026 Jul 01 10:38:43 AM PDT 24 Jul 01 10:38:48 AM PDT 24 523331194 ps
T566 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1678067036 Jul 01 10:39:11 AM PDT 24 Jul 01 10:39:15 AM PDT 24 309075675 ps
T567 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2162813799 Jul 01 10:39:02 AM PDT 24 Jul 01 10:39:03 AM PDT 24 73195967 ps
T568 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4215201727 Jul 01 10:39:02 AM PDT 24 Jul 01 10:39:04 AM PDT 24 124068691 ps
T569 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1877840283 Jul 01 10:39:17 AM PDT 24 Jul 01 10:39:19 AM PDT 24 94234799 ps
T570 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2209836424 Jul 01 10:39:13 AM PDT 24 Jul 01 10:39:17 AM PDT 24 255993267 ps
T571 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3705511941 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:55 AM PDT 24 71606489 ps
T572 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3915429801 Jul 01 10:38:44 AM PDT 24 Jul 01 10:38:46 AM PDT 24 58153882 ps
T573 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2137615336 Jul 01 10:38:58 AM PDT 24 Jul 01 10:39:00 AM PDT 24 196368570 ps
T574 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3789122646 Jul 01 10:38:48 AM PDT 24 Jul 01 10:38:56 AM PDT 24 152697328 ps
T575 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1273245206 Jul 01 10:40:16 AM PDT 24 Jul 01 10:40:20 AM PDT 24 253917577 ps
T576 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3046931 Jul 01 10:39:23 AM PDT 24 Jul 01 10:39:26 AM PDT 24 323652919 ps
T91 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1103900062 Jul 01 10:39:14 AM PDT 24 Jul 01 10:39:17 AM PDT 24 97581062 ps
T577 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.156780560 Jul 01 10:39:08 AM PDT 24 Jul 01 10:39:13 AM PDT 24 263904391 ps
T578 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1810562296 Jul 01 10:40:19 AM PDT 24 Jul 01 10:40:24 AM PDT 24 152817499 ps
T579 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2311888232 Jul 01 10:39:12 AM PDT 24 Jul 01 10:39:23 AM PDT 24 1522123042 ps
T580 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1382359282 Jul 01 10:38:51 AM PDT 24 Jul 01 10:38:53 AM PDT 24 78985851 ps
T581 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1268978176 Jul 01 10:39:05 AM PDT 24 Jul 01 10:39:08 AM PDT 24 62828321 ps
T582 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.69197131 Jul 01 10:39:31 AM PDT 24 Jul 01 10:39:34 AM PDT 24 232903213 ps
T583 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2320279543 Jul 01 10:39:02 AM PDT 24 Jul 01 10:39:03 AM PDT 24 145534174 ps
T584 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.327010922 Jul 01 10:38:46 AM PDT 24 Jul 01 10:38:49 AM PDT 24 466483092 ps
T585 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3075258693 Jul 01 10:39:20 AM PDT 24 Jul 01 10:39:22 AM PDT 24 97369745 ps
T586 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.41472295 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:59 AM PDT 24 535653677 ps
T587 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2492733031 Jul 01 10:40:19 AM PDT 24 Jul 01 10:40:24 AM PDT 24 513750080 ps
T588 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3882007350 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:07 AM PDT 24 437084538 ps
T589 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.890990993 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:56 AM PDT 24 119955126 ps
T590 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2646563397 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:06 AM PDT 24 145704133 ps
T591 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2144606361 Jul 01 10:39:02 AM PDT 24 Jul 01 10:39:04 AM PDT 24 543871746 ps
T592 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2614328419 Jul 01 10:39:24 AM PDT 24 Jul 01 10:39:26 AM PDT 24 136273831 ps
T110 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.893407237 Jul 01 10:39:25 AM PDT 24 Jul 01 10:39:29 AM PDT 24 816747260 ps
T112 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.478430698 Jul 01 10:39:22 AM PDT 24 Jul 01 10:39:25 AM PDT 24 425991004 ps
T593 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2991016057 Jul 01 10:39:07 AM PDT 24 Jul 01 10:39:10 AM PDT 24 54867011 ps
T594 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.433057814 Jul 01 10:39:17 AM PDT 24 Jul 01 10:39:19 AM PDT 24 93363159 ps
T595 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1391332923 Jul 01 10:39:13 AM PDT 24 Jul 01 10:39:16 AM PDT 24 104494872 ps
T596 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3839310673 Jul 01 10:38:49 AM PDT 24 Jul 01 10:38:51 AM PDT 24 204288399 ps
T597 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3974550785 Jul 01 10:38:55 AM PDT 24 Jul 01 10:38:57 AM PDT 24 57580312 ps
T111 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3947469210 Jul 01 10:38:48 AM PDT 24 Jul 01 10:38:52 AM PDT 24 780821025 ps
T598 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4090675570 Jul 01 10:39:13 AM PDT 24 Jul 01 10:39:16 AM PDT 24 113950849 ps
T599 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3033638660 Jul 01 10:39:22 AM PDT 24 Jul 01 10:39:24 AM PDT 24 63775215 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1757267027 Jul 01 10:39:13 AM PDT 24 Jul 01 10:39:17 AM PDT 24 183357162 ps
T601 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1640577674 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:42 AM PDT 24 1557551796 ps
T602 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.493419060 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:55 AM PDT 24 66202927 ps
T603 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3112626699 Jul 01 10:38:58 AM PDT 24 Jul 01 10:39:00 AM PDT 24 191152535 ps
T604 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1062232338 Jul 01 10:39:17 AM PDT 24 Jul 01 10:39:21 AM PDT 24 221953863 ps
T605 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.405601323 Jul 01 10:38:59 AM PDT 24 Jul 01 10:39:02 AM PDT 24 195122294 ps
T606 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2047028803 Jul 01 10:39:11 AM PDT 24 Jul 01 10:39:16 AM PDT 24 523318050 ps
T607 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2121496055 Jul 01 10:39:09 AM PDT 24 Jul 01 10:39:14 AM PDT 24 354027639 ps
T608 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2444876296 Jul 01 10:39:07 AM PDT 24 Jul 01 10:39:16 AM PDT 24 476661684 ps
T113 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3946163956 Jul 01 10:39:12 AM PDT 24 Jul 01 10:39:18 AM PDT 24 928863731 ps
T609 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3646045469 Jul 01 10:39:09 AM PDT 24 Jul 01 10:39:12 AM PDT 24 105621876 ps
T610 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.722796730 Jul 01 10:39:06 AM PDT 24 Jul 01 10:39:09 AM PDT 24 188733464 ps
T611 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1646646514 Jul 01 10:38:50 AM PDT 24 Jul 01 10:38:54 AM PDT 24 466530326 ps
T612 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1670638913 Jul 01 10:38:56 AM PDT 24 Jul 01 10:38:59 AM PDT 24 494617807 ps
T613 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3977427329 Jul 01 10:40:18 AM PDT 24 Jul 01 10:40:23 AM PDT 24 98695875 ps
T614 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1211653757 Jul 01 10:39:11 AM PDT 24 Jul 01 10:39:14 AM PDT 24 205621419 ps
T615 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1660664277 Jul 01 10:39:59 AM PDT 24 Jul 01 10:40:02 AM PDT 24 137745494 ps
T92 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2650986456 Jul 01 10:39:06 AM PDT 24 Jul 01 10:39:10 AM PDT 24 112273635 ps
T616 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3640487816 Jul 01 10:39:27 AM PDT 24 Jul 01 10:39:31 AM PDT 24 918737245 ps
T617 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1346829429 Jul 01 10:38:48 AM PDT 24 Jul 01 10:38:50 AM PDT 24 63581549 ps
T618 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2645468821 Jul 01 10:39:06 AM PDT 24 Jul 01 10:39:09 AM PDT 24 92787662 ps
T619 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3642617523 Jul 01 10:38:58 AM PDT 24 Jul 01 10:39:00 AM PDT 24 57745843 ps
T620 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2288321631 Jul 01 10:39:33 AM PDT 24 Jul 01 10:39:37 AM PDT 24 164440263 ps

Test location /workspace/coverage/default/37.rstmgr_stress_all.2833497944
Short name T6
Test name
Test status
Simulation time 1295213264 ps
CPU time 6.82 seconds
Started Jul 01 10:42:45 AM PDT 24
Finished Jul 01 10:42:52 AM PDT 24
Peak memory 200292 kb
Host smart-08795a1d-843a-4e64-923f-5140657dc3b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833497944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2833497944
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3784687514
Short name T79
Test name
Test status
Simulation time 397569161 ps
CPU time 2.24 seconds
Started Jul 01 10:42:37 AM PDT 24
Finished Jul 01 10:42:41 AM PDT 24
Peak memory 200068 kb
Host smart-923077e5-5ccc-42a3-bb6e-0dd11de46364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784687514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3784687514
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1904325873
Short name T58
Test name
Test status
Simulation time 897705828 ps
CPU time 3.43 seconds
Started Jul 01 10:39:09 AM PDT 24
Finished Jul 01 10:39:15 AM PDT 24
Peak memory 200624 kb
Host smart-877736e8-cecb-4c64-b5ee-3417b294f104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904325873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1904325873
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2990985843
Short name T66
Test name
Test status
Simulation time 16961911265 ps
CPU time 24.27 seconds
Started Jul 01 10:42:11 AM PDT 24
Finished Jul 01 10:42:38 AM PDT 24
Peak memory 221172 kb
Host smart-ab313eff-9b1a-4a93-9c1e-cb90b08af2af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990985843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2990985843
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2258104760
Short name T24
Test name
Test status
Simulation time 1225209910 ps
CPU time 5.73 seconds
Started Jul 01 10:42:13 AM PDT 24
Finished Jul 01 10:42:22 AM PDT 24
Peak memory 217204 kb
Host smart-57e88817-25bc-4915-9e04-7ebdbb4e7d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258104760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2258104760
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3546120911
Short name T12
Test name
Test status
Simulation time 10400536964 ps
CPU time 34.93 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:42 AM PDT 24
Peak memory 200344 kb
Host smart-290de338-9826-43ba-8722-57dd61512688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546120911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3546120911
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1117801000
Short name T63
Test name
Test status
Simulation time 118406168 ps
CPU time 1.43 seconds
Started Jul 01 10:38:59 AM PDT 24
Finished Jul 01 10:39:02 AM PDT 24
Peak memory 208304 kb
Host smart-204a295a-f75e-450b-b18c-882b873e0c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117801000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1117801000
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.426089674
Short name T40
Test name
Test status
Simulation time 72748881 ps
CPU time 0.8 seconds
Started Jul 01 10:42:16 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 199732 kb
Host smart-fe17d678-4e32-43e2-bd8b-ed62521534f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426089674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.426089674
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.798910040
Short name T10
Test name
Test status
Simulation time 185455517 ps
CPU time 1.29 seconds
Started Jul 01 10:41:53 AM PDT 24
Finished Jul 01 10:41:56 AM PDT 24
Peak memory 199944 kb
Host smart-d8e3e25e-d88b-4a4c-a563-8b7225579a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798910040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.798910040
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2127108873
Short name T11
Test name
Test status
Simulation time 1926665434 ps
CPU time 7.35 seconds
Started Jul 01 10:42:13 AM PDT 24
Finished Jul 01 10:42:24 AM PDT 24
Peak memory 200196 kb
Host smart-6954ab49-70d3-42c3-a1ac-1a912d24de26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127108873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2127108873
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1777804651
Short name T23
Test name
Test status
Simulation time 1229125021 ps
CPU time 6.52 seconds
Started Jul 01 10:41:54 AM PDT 24
Finished Jul 01 10:42:03 AM PDT 24
Peak memory 217540 kb
Host smart-aa759ddf-8e40-4e31-a6db-22073b82449d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777804651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1777804651
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3033402174
Short name T62
Test name
Test status
Simulation time 283205169 ps
CPU time 1.99 seconds
Started Jul 01 10:39:12 AM PDT 24
Finished Jul 01 10:39:15 AM PDT 24
Peak memory 211548 kb
Host smart-8620c4db-f905-4707-8f59-a2a4077b66db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033402174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3033402174
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.52546461
Short name T137
Test name
Test status
Simulation time 83066858 ps
CPU time 0.86 seconds
Started Jul 01 10:41:30 AM PDT 24
Finished Jul 01 10:41:32 AM PDT 24
Peak memory 199976 kb
Host smart-64bab247-5356-4ffa-b914-c907192a0c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52546461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.52546461
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2055631001
Short name T101
Test name
Test status
Simulation time 148148024 ps
CPU time 1.09 seconds
Started Jul 01 10:39:17 AM PDT 24
Finished Jul 01 10:39:19 AM PDT 24
Peak memory 200060 kb
Host smart-0c8a3d30-7497-4e4d-afe7-18f68b2a99f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055631001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2055631001
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2424417297
Short name T14
Test name
Test status
Simulation time 185034257 ps
CPU time 0.91 seconds
Started Jul 01 10:41:45 AM PDT 24
Finished Jul 01 10:41:47 AM PDT 24
Peak memory 199752 kb
Host smart-59d9f716-23ac-449c-bcc7-51fca533a29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424417297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2424417297
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.941594591
Short name T153
Test name
Test status
Simulation time 2352999128 ps
CPU time 9.02 seconds
Started Jul 01 10:42:08 AM PDT 24
Finished Jul 01 10:42:19 AM PDT 24
Peak memory 217684 kb
Host smart-05a5e063-95c1-4d9a-91ce-a2135e5bff07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941594591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.941594591
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2187470743
Short name T5
Test name
Test status
Simulation time 244443057 ps
CPU time 1.09 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 217312 kb
Host smart-8a8c65b2-556c-48e3-b9cf-a7f1b2b61912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187470743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2187470743
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2081321531
Short name T108
Test name
Test status
Simulation time 482406913 ps
CPU time 2.07 seconds
Started Jul 01 10:39:28 AM PDT 24
Finished Jul 01 10:39:31 AM PDT 24
Peak memory 200304 kb
Host smart-2e6911fc-0c0c-4da5-a733-b8c3bf0e7207
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081321531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2081321531
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1375827226
Short name T86
Test name
Test status
Simulation time 926458676 ps
CPU time 3.38 seconds
Started Jul 01 10:38:57 AM PDT 24
Finished Jul 01 10:39:01 AM PDT 24
Peak memory 200252 kb
Host smart-ba0bb737-5fb8-4aba-95ff-4a2b56bd2bad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375827226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1375827226
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2233027929
Short name T106
Test name
Test status
Simulation time 418622619 ps
CPU time 1.76 seconds
Started Jul 01 10:39:22 AM PDT 24
Finished Jul 01 10:39:25 AM PDT 24
Peak memory 200280 kb
Host smart-47abfddc-8590-430c-a767-d9b54f37206b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233027929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2233027929
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.273446809
Short name T59
Test name
Test status
Simulation time 222330645 ps
CPU time 1.57 seconds
Started Jul 01 10:39:04 AM PDT 24
Finished Jul 01 10:39:09 AM PDT 24
Peak memory 200276 kb
Host smart-8ebb508b-613d-44f9-9baa-59313f5b10dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273446809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.273446809
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1640577674
Short name T601
Test name
Test status
Simulation time 1557551796 ps
CPU time 7.78 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:42 AM PDT 24
Peak memory 200200 kb
Host smart-07507926-2aff-49c8-af9c-964d69baf0ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640577674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
640577674
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2614328419
Short name T592
Test name
Test status
Simulation time 136273831 ps
CPU time 0.92 seconds
Started Jul 01 10:39:24 AM PDT 24
Finished Jul 01 10:39:26 AM PDT 24
Peak memory 200072 kb
Host smart-15ba0218-c45d-44e2-b8cb-81400d4f12ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614328419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
614328419
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3789122646
Short name T574
Test name
Test status
Simulation time 152697328 ps
CPU time 1.32 seconds
Started Jul 01 10:38:48 AM PDT 24
Finished Jul 01 10:38:56 AM PDT 24
Peak memory 211252 kb
Host smart-901adfa9-375a-4fc0-8f68-5a4a3ea456fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789122646 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3789122646
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1382359282
Short name T580
Test name
Test status
Simulation time 78985851 ps
CPU time 0.83 seconds
Started Jul 01 10:38:51 AM PDT 24
Finished Jul 01 10:38:53 AM PDT 24
Peak memory 200040 kb
Host smart-fa41956f-14c7-4dfe-b9aa-7fafb1d08c21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382359282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1382359282
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.433057814
Short name T594
Test name
Test status
Simulation time 93363159 ps
CPU time 1.07 seconds
Started Jul 01 10:39:17 AM PDT 24
Finished Jul 01 10:39:19 AM PDT 24
Peak memory 200124 kb
Host smart-6e4114c2-f90e-4236-981d-662c8b324ce2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433057814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.433057814
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.429532194
Short name T125
Test name
Test status
Simulation time 460449040 ps
CPU time 2.56 seconds
Started Jul 01 10:38:56 AM PDT 24
Finished Jul 01 10:39:00 AM PDT 24
Peak memory 200228 kb
Host smart-de43bff3-f2a8-468b-98d2-9314f50d64f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429532194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.429532194
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1597062497
Short name T547
Test name
Test status
Simulation time 481873851 ps
CPU time 5.52 seconds
Started Jul 01 10:39:33 AM PDT 24
Finished Jul 01 10:39:48 AM PDT 24
Peak memory 200264 kb
Host smart-b68786ae-e330-40a4-b904-43f28a2e7b73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597062497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
597062497
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.890990993
Short name T589
Test name
Test status
Simulation time 119955126 ps
CPU time 0.93 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:56 AM PDT 24
Peak memory 200020 kb
Host smart-28c36007-c46e-43e0-ac2c-b7befa1685fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890990993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.890990993
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2688521585
Short name T90
Test name
Test status
Simulation time 185416913 ps
CPU time 1.25 seconds
Started Jul 01 10:39:23 AM PDT 24
Finished Jul 01 10:39:26 AM PDT 24
Peak memory 208336 kb
Host smart-bf3948e7-7b2c-40fd-8e42-59feafd66f19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688521585 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2688521585
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1294293439
Short name T560
Test name
Test status
Simulation time 66984833 ps
CPU time 0.75 seconds
Started Jul 01 10:38:39 AM PDT 24
Finished Jul 01 10:38:41 AM PDT 24
Peak memory 200056 kb
Host smart-8a8b6ac1-0ed9-4b00-85ab-05d95e926abb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294293439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1294293439
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3476900400
Short name T563
Test name
Test status
Simulation time 101025632 ps
CPU time 1.15 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:56 AM PDT 24
Peak memory 200244 kb
Host smart-98f35bca-c4f0-4b4e-94ed-4b8121f2512c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476900400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3476900400
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1757267027
Short name T600
Test name
Test status
Simulation time 183357162 ps
CPU time 2.51 seconds
Started Jul 01 10:39:13 AM PDT 24
Finished Jul 01 10:39:17 AM PDT 24
Peak memory 208388 kb
Host smart-8ef81e46-d0b5-42d0-b449-5450bca8ac82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757267027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1757267027
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3640487816
Short name T616
Test name
Test status
Simulation time 918737245 ps
CPU time 3.07 seconds
Started Jul 01 10:39:27 AM PDT 24
Finished Jul 01 10:39:31 AM PDT 24
Peak memory 200288 kb
Host smart-58140fcd-bc14-4e3f-87cf-78f5f4b51708
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640487816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3640487816
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2815418837
Short name T88
Test name
Test status
Simulation time 140326600 ps
CPU time 1.22 seconds
Started Jul 01 10:39:07 AM PDT 24
Finished Jul 01 10:39:11 AM PDT 24
Peak memory 209396 kb
Host smart-7580219f-901b-4641-9174-247558ba9593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815418837 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2815418837
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3737774942
Short name T548
Test name
Test status
Simulation time 67366862 ps
CPU time 0.76 seconds
Started Jul 01 10:39:40 AM PDT 24
Finished Jul 01 10:39:45 AM PDT 24
Peak memory 200020 kb
Host smart-9ee3da2d-9a45-4eda-af62-285eda4c25f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737774942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3737774942
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1065635532
Short name T105
Test name
Test status
Simulation time 195191532 ps
CPU time 2.75 seconds
Started Jul 01 10:39:04 AM PDT 24
Finished Jul 01 10:39:10 AM PDT 24
Peak memory 208392 kb
Host smart-ad52b944-bcc2-492b-a94e-82af48b7856b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065635532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1065635532
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.722796730
Short name T610
Test name
Test status
Simulation time 188733464 ps
CPU time 1.34 seconds
Started Jul 01 10:39:06 AM PDT 24
Finished Jul 01 10:39:09 AM PDT 24
Peak memory 208360 kb
Host smart-12f07833-2a0d-4f1b-b3b0-b760509a553f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722796730 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.722796730
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.493419060
Short name T602
Test name
Test status
Simulation time 66202927 ps
CPU time 0.76 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:55 AM PDT 24
Peak memory 200048 kb
Host smart-62580d87-a5cf-4193-81c0-cde76643764d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493419060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.493419060
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1810562296
Short name T578
Test name
Test status
Simulation time 152817499 ps
CPU time 1.14 seconds
Started Jul 01 10:40:19 AM PDT 24
Finished Jul 01 10:40:24 AM PDT 24
Peak memory 200008 kb
Host smart-99610e32-bfc8-4df4-b567-1531a44820c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810562296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1810562296
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2047028803
Short name T606
Test name
Test status
Simulation time 523318050 ps
CPU time 3.82 seconds
Started Jul 01 10:39:11 AM PDT 24
Finished Jul 01 10:39:16 AM PDT 24
Peak memory 208432 kb
Host smart-2e6c9491-9b7f-44f2-bd66-938c29c905f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047028803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2047028803
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3128825043
Short name T87
Test name
Test status
Simulation time 108080675 ps
CPU time 1.19 seconds
Started Jul 01 10:39:00 AM PDT 24
Finished Jul 01 10:39:02 AM PDT 24
Peak memory 208272 kb
Host smart-3d851db3-61e4-4886-a3c5-73f3d272cd2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128825043 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3128825043
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3642617523
Short name T619
Test name
Test status
Simulation time 57745843 ps
CPU time 0.83 seconds
Started Jul 01 10:38:58 AM PDT 24
Finished Jul 01 10:39:00 AM PDT 24
Peak memory 200128 kb
Host smart-6d868f69-cd22-4108-8bca-ab6decdc1c27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642617523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3642617523
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.23422192
Short name T98
Test name
Test status
Simulation time 210280712 ps
CPU time 1.58 seconds
Started Jul 01 10:38:55 AM PDT 24
Finished Jul 01 10:38:57 AM PDT 24
Peak memory 200288 kb
Host smart-feb3af5c-b659-46ba-81fd-09b0eb818550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23422192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sam
e_csr_outstanding.23422192
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3946163956
Short name T113
Test name
Test status
Simulation time 928863731 ps
CPU time 3.41 seconds
Started Jul 01 10:39:12 AM PDT 24
Finished Jul 01 10:39:18 AM PDT 24
Peak memory 200224 kb
Host smart-d7c007be-1cf0-41c4-bf20-6772ba61d6b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946163956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3946163956
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3112626699
Short name T603
Test name
Test status
Simulation time 191152535 ps
CPU time 1.81 seconds
Started Jul 01 10:38:58 AM PDT 24
Finished Jul 01 10:39:00 AM PDT 24
Peak memory 208512 kb
Host smart-ac4b48ed-77c9-4183-9664-04e4ab0b5ae8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112626699 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3112626699
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3705511941
Short name T571
Test name
Test status
Simulation time 71606489 ps
CPU time 0.78 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:55 AM PDT 24
Peak memory 200052 kb
Host smart-8e596e64-47e9-485a-b680-70f093b9f985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705511941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3705511941
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.470945772
Short name T104
Test name
Test status
Simulation time 85689660 ps
CPU time 1.08 seconds
Started Jul 01 10:39:08 AM PDT 24
Finished Jul 01 10:39:12 AM PDT 24
Peak memory 200096 kb
Host smart-2698a4d2-d39c-4945-bd5c-a54f95575a2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470945772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.470945772
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3441433918
Short name T114
Test name
Test status
Simulation time 370485869 ps
CPU time 2.86 seconds
Started Jul 01 10:39:00 AM PDT 24
Finished Jul 01 10:39:04 AM PDT 24
Peak memory 208344 kb
Host smart-15c65446-d42e-4def-bf44-6baf7c444948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441433918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3441433918
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.478430698
Short name T112
Test name
Test status
Simulation time 425991004 ps
CPU time 1.84 seconds
Started Jul 01 10:39:22 AM PDT 24
Finished Jul 01 10:39:25 AM PDT 24
Peak memory 200244 kb
Host smart-9b6bd0fd-6656-4d77-9e41-3eb8b4f61356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478430698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.478430698
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4090675570
Short name T598
Test name
Test status
Simulation time 113950849 ps
CPU time 0.97 seconds
Started Jul 01 10:39:13 AM PDT 24
Finished Jul 01 10:39:16 AM PDT 24
Peak memory 200152 kb
Host smart-eeb94c7b-ac30-4ae9-8cdd-40b2e4334b4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090675570 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.4090675570
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3033638660
Short name T599
Test name
Test status
Simulation time 63775215 ps
CPU time 0.82 seconds
Started Jul 01 10:39:22 AM PDT 24
Finished Jul 01 10:39:24 AM PDT 24
Peak memory 200044 kb
Host smart-a24d50d5-b04a-4147-8958-bfdcd404ebde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033638660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3033638660
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3977427329
Short name T613
Test name
Test status
Simulation time 98695875 ps
CPU time 1.19 seconds
Started Jul 01 10:40:18 AM PDT 24
Finished Jul 01 10:40:23 AM PDT 24
Peak memory 200136 kb
Host smart-bd1b9ae6-5cac-4b2b-b9ea-34f7abc8bcd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977427329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3977427329
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2121496055
Short name T607
Test name
Test status
Simulation time 354027639 ps
CPU time 2.69 seconds
Started Jul 01 10:39:09 AM PDT 24
Finished Jul 01 10:39:14 AM PDT 24
Peak memory 208456 kb
Host smart-b09d5573-6fba-47f1-8876-67ca24d27ed0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121496055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2121496055
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2144606361
Short name T591
Test name
Test status
Simulation time 543871746 ps
CPU time 2 seconds
Started Jul 01 10:39:02 AM PDT 24
Finished Jul 01 10:39:04 AM PDT 24
Peak memory 200328 kb
Host smart-cde0da0f-b89e-4a16-a2a5-a6d6ff0c7d70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144606361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2144606361
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2613210721
Short name T85
Test name
Test status
Simulation time 175989634 ps
CPU time 1.71 seconds
Started Jul 01 10:38:51 AM PDT 24
Finished Jul 01 10:38:54 AM PDT 24
Peak memory 214324 kb
Host smart-f2dc83e6-bace-422d-a1b7-b82526bbded3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613210721 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2613210721
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3873034141
Short name T552
Test name
Test status
Simulation time 69818006 ps
CPU time 0.72 seconds
Started Jul 01 10:40:32 AM PDT 24
Finished Jul 01 10:40:34 AM PDT 24
Peak memory 199908 kb
Host smart-03bcc7b7-0010-4590-ad93-207c338c1784
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873034141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3873034141
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1273245206
Short name T575
Test name
Test status
Simulation time 253917577 ps
CPU time 1.45 seconds
Started Jul 01 10:40:16 AM PDT 24
Finished Jul 01 10:40:20 AM PDT 24
Peak memory 200200 kb
Host smart-c1bc5eb4-336e-4018-91c2-46b376ebe24d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273245206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1273245206
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1657035450
Short name T564
Test name
Test status
Simulation time 288734333 ps
CPU time 2.17 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:08 AM PDT 24
Peak memory 208464 kb
Host smart-aef798e1-0909-40a7-9190-654a39817897
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657035450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1657035450
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1660664277
Short name T615
Test name
Test status
Simulation time 137745494 ps
CPU time 1.13 seconds
Started Jul 01 10:39:59 AM PDT 24
Finished Jul 01 10:40:02 AM PDT 24
Peak memory 207988 kb
Host smart-1943e66d-575f-415f-a131-7bc70472490d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660664277 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1660664277
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2645468821
Short name T618
Test name
Test status
Simulation time 92787662 ps
CPU time 0.9 seconds
Started Jul 01 10:39:06 AM PDT 24
Finished Jul 01 10:39:09 AM PDT 24
Peak memory 200020 kb
Host smart-563f18cb-fc3d-4c58-be02-566baeb5f7fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645468821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2645468821
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.972003994
Short name T103
Test name
Test status
Simulation time 82536684 ps
CPU time 0.93 seconds
Started Jul 01 10:39:00 AM PDT 24
Finished Jul 01 10:39:02 AM PDT 24
Peak memory 200120 kb
Host smart-e03c4c3f-6c47-400c-a898-8f9c5f7eb760
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972003994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.972003994
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1678067036
Short name T566
Test name
Test status
Simulation time 309075675 ps
CPU time 2.45 seconds
Started Jul 01 10:39:11 AM PDT 24
Finished Jul 01 10:39:15 AM PDT 24
Peak memory 208396 kb
Host smart-5a511ac7-71d0-47db-8748-cb7234c0805a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678067036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1678067036
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.539038243
Short name T65
Test name
Test status
Simulation time 685002929 ps
CPU time 2.25 seconds
Started Jul 01 10:39:10 AM PDT 24
Finished Jul 01 10:39:14 AM PDT 24
Peak memory 200328 kb
Host smart-c43edaa4-b2f4-43ac-abb6-1c9b9f3c6c11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539038243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.539038243
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.240364520
Short name T89
Test name
Test status
Simulation time 119202459 ps
CPU time 1.17 seconds
Started Jul 01 10:39:59 AM PDT 24
Finished Jul 01 10:40:02 AM PDT 24
Peak memory 206696 kb
Host smart-ce9b0dcd-347b-4e88-a0ca-68cb2bf53fab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240364520 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.240364520
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1346829429
Short name T617
Test name
Test status
Simulation time 63581549 ps
CPU time 0.82 seconds
Started Jul 01 10:38:48 AM PDT 24
Finished Jul 01 10:38:50 AM PDT 24
Peak memory 199948 kb
Host smart-e5fca8be-ac64-4454-90e4-0484955b7561
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346829429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1346829429
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1211653757
Short name T614
Test name
Test status
Simulation time 205621419 ps
CPU time 1.6 seconds
Started Jul 01 10:39:11 AM PDT 24
Finished Jul 01 10:39:14 AM PDT 24
Peak memory 200356 kb
Host smart-2a60d050-e1c2-405a-bd5f-b90bf6aa6e8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211653757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1211653757
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2735975472
Short name T553
Test name
Test status
Simulation time 314067607 ps
CPU time 2.24 seconds
Started Jul 01 10:38:59 AM PDT 24
Finished Jul 01 10:39:02 AM PDT 24
Peak memory 208344 kb
Host smart-b9b73ec1-c4bc-4f52-8064-44e15688262a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735975472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2735975472
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.482166174
Short name T107
Test name
Test status
Simulation time 778237085 ps
CPU time 2.79 seconds
Started Jul 01 10:40:18 AM PDT 24
Finished Jul 01 10:40:25 AM PDT 24
Peak memory 200244 kb
Host smart-b5464f74-47a4-4b37-9b87-78376cfbacbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482166174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.482166174
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3300578335
Short name T550
Test name
Test status
Simulation time 124982595 ps
CPU time 0.99 seconds
Started Jul 01 10:39:01 AM PDT 24
Finished Jul 01 10:39:03 AM PDT 24
Peak memory 200180 kb
Host smart-4088748d-dc91-415f-8055-c47f06eae59c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300578335 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3300578335
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3974550785
Short name T597
Test name
Test status
Simulation time 57580312 ps
CPU time 0.8 seconds
Started Jul 01 10:38:55 AM PDT 24
Finished Jul 01 10:38:57 AM PDT 24
Peak memory 200040 kb
Host smart-89e769c4-5667-490a-b19e-a03a04b5d181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974550785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3974550785
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3075258693
Short name T585
Test name
Test status
Simulation time 97369745 ps
CPU time 1.36 seconds
Started Jul 01 10:39:20 AM PDT 24
Finished Jul 01 10:39:22 AM PDT 24
Peak memory 200252 kb
Host smart-c9ecf9dd-6a9a-4787-bf63-09b0d5610d31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075258693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3075258693
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1062232338
Short name T604
Test name
Test status
Simulation time 221953863 ps
CPU time 3.21 seconds
Started Jul 01 10:39:17 AM PDT 24
Finished Jul 01 10:39:21 AM PDT 24
Peak memory 208332 kb
Host smart-42f4b238-547c-4846-9379-e187b17fed5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062232338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1062232338
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2492733031
Short name T587
Test name
Test status
Simulation time 513750080 ps
CPU time 1.83 seconds
Started Jul 01 10:40:19 AM PDT 24
Finished Jul 01 10:40:24 AM PDT 24
Peak memory 200228 kb
Host smart-ba405f69-d442-4390-8fc9-54833175a18c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492733031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2492733031
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1507369760
Short name T64
Test name
Test status
Simulation time 169832198 ps
CPU time 1.15 seconds
Started Jul 01 10:38:57 AM PDT 24
Finished Jul 01 10:38:58 AM PDT 24
Peak memory 208336 kb
Host smart-4b4e2fd9-4ed3-4f43-b351-1a3f4b2f747f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507369760 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1507369760
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2991016057
Short name T593
Test name
Test status
Simulation time 54867011 ps
CPU time 0.75 seconds
Started Jul 01 10:39:07 AM PDT 24
Finished Jul 01 10:39:10 AM PDT 24
Peak memory 200036 kb
Host smart-703903c8-05e0-4d30-9bf5-6adaa6f136a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991016057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2991016057
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1845680577
Short name T102
Test name
Test status
Simulation time 266745491 ps
CPU time 1.55 seconds
Started Jul 01 10:39:13 AM PDT 24
Finished Jul 01 10:39:17 AM PDT 24
Peak memory 200212 kb
Host smart-646c0178-a51e-46a9-a813-b773a9633ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845680577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1845680577
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.405601323
Short name T605
Test name
Test status
Simulation time 195122294 ps
CPU time 1.54 seconds
Started Jul 01 10:38:59 AM PDT 24
Finished Jul 01 10:39:02 AM PDT 24
Peak memory 208424 kb
Host smart-2250783b-4532-4294-8828-3d7891e5d192
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405601323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.405601323
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.893407237
Short name T110
Test name
Test status
Simulation time 816747260 ps
CPU time 3 seconds
Started Jul 01 10:39:25 AM PDT 24
Finished Jul 01 10:39:29 AM PDT 24
Peak memory 200240 kb
Host smart-72e90696-dc5c-41d3-a629-167127aa5fe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893407237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.893407237
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1103900062
Short name T91
Test name
Test status
Simulation time 97581062 ps
CPU time 1.3 seconds
Started Jul 01 10:39:14 AM PDT 24
Finished Jul 01 10:39:17 AM PDT 24
Peak memory 200268 kb
Host smart-5f40395b-3665-4fcb-9fee-297c13ae6193
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103900062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
103900062
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3302257198
Short name T124
Test name
Test status
Simulation time 1559336243 ps
CPU time 7.97 seconds
Started Jul 01 10:38:49 AM PDT 24
Finished Jul 01 10:38:58 AM PDT 24
Peak memory 200264 kb
Host smart-c1d2148e-3ac8-4dde-a45b-66c29795b37e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302257198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
302257198
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1391332923
Short name T595
Test name
Test status
Simulation time 104494872 ps
CPU time 0.84 seconds
Started Jul 01 10:39:13 AM PDT 24
Finished Jul 01 10:39:16 AM PDT 24
Peak memory 200072 kb
Host smart-98f4fcd0-3fd6-4e9b-bb0f-2c5f1f69d691
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391332923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
391332923
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3839310673
Short name T596
Test name
Test status
Simulation time 204288399 ps
CPU time 1.31 seconds
Started Jul 01 10:38:49 AM PDT 24
Finished Jul 01 10:38:51 AM PDT 24
Peak memory 211056 kb
Host smart-1a16a079-5c6b-461a-8cac-f2edca6cb656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839310673 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3839310673
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1666237353
Short name T545
Test name
Test status
Simulation time 77571675 ps
CPU time 0.8 seconds
Started Jul 01 10:38:51 AM PDT 24
Finished Jul 01 10:38:54 AM PDT 24
Peak memory 200000 kb
Host smart-926149e4-b855-4153-87bd-9096de7f7619
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666237353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1666237353
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1609166824
Short name T97
Test name
Test status
Simulation time 108315123 ps
CPU time 1.24 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:56 AM PDT 24
Peak memory 200236 kb
Host smart-eb73d531-2a7e-4c2e-8b49-3ec8c46aa523
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609166824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1609166824
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2209836424
Short name T570
Test name
Test status
Simulation time 255993267 ps
CPU time 2.11 seconds
Started Jul 01 10:39:13 AM PDT 24
Finished Jul 01 10:39:17 AM PDT 24
Peak memory 208440 kb
Host smart-a2c143be-c665-473b-8443-4a8d0c159ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209836424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2209836424
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3947469210
Short name T111
Test name
Test status
Simulation time 780821025 ps
CPU time 3.14 seconds
Started Jul 01 10:38:48 AM PDT 24
Finished Jul 01 10:38:52 AM PDT 24
Peak memory 200264 kb
Host smart-a8dce2c8-2909-4226-acd8-2a9b04439e85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947469210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3947469210
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.73002541
Short name T546
Test name
Test status
Simulation time 195283084 ps
CPU time 1.51 seconds
Started Jul 01 10:38:52 AM PDT 24
Finished Jul 01 10:38:55 AM PDT 24
Peak memory 200192 kb
Host smart-e0526af8-540d-45dc-a521-51874907c4b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73002541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.73002541
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2444876296
Short name T608
Test name
Test status
Simulation time 476661684 ps
CPU time 5.76 seconds
Started Jul 01 10:39:07 AM PDT 24
Finished Jul 01 10:39:16 AM PDT 24
Peak memory 216532 kb
Host smart-eeafbe93-9fda-44e7-9b6c-c432e0dd4cfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444876296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
444876296
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3646045469
Short name T609
Test name
Test status
Simulation time 105621876 ps
CPU time 0.94 seconds
Started Jul 01 10:39:09 AM PDT 24
Finished Jul 01 10:39:12 AM PDT 24
Peak memory 200056 kb
Host smart-9f2fad89-18ea-4b76-89cb-75380060cab2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646045469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
646045469
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4215201727
Short name T568
Test name
Test status
Simulation time 124068691 ps
CPU time 1.38 seconds
Started Jul 01 10:39:02 AM PDT 24
Finished Jul 01 10:39:04 AM PDT 24
Peak memory 208308 kb
Host smart-8c2d2eaa-fa2e-40f3-bbcb-f81b36cf5315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215201727 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.4215201727
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3915429801
Short name T572
Test name
Test status
Simulation time 58153882 ps
CPU time 0.76 seconds
Started Jul 01 10:38:44 AM PDT 24
Finished Jul 01 10:38:46 AM PDT 24
Peak memory 199928 kb
Host smart-8b8ae86f-c649-4a8b-bc7d-c07101ae4683
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915429801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3915429801
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2646563397
Short name T590
Test name
Test status
Simulation time 145704133 ps
CPU time 1.17 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:06 AM PDT 24
Peak memory 200124 kb
Host smart-88e13d53-5e5b-4e69-8e4c-5155b237d4cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646563397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2646563397
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.832205026
Short name T565
Test name
Test status
Simulation time 523331194 ps
CPU time 3.61 seconds
Started Jul 01 10:38:43 AM PDT 24
Finished Jul 01 10:38:48 AM PDT 24
Peak memory 208360 kb
Host smart-5af0190c-0767-4297-9bb8-9a2b0a7ba3b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832205026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.832205026
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3432727821
Short name T109
Test name
Test status
Simulation time 430527510 ps
CPU time 1.74 seconds
Started Jul 01 10:39:06 AM PDT 24
Finished Jul 01 10:39:10 AM PDT 24
Peak memory 208448 kb
Host smart-261d9e61-3af7-4c9e-8478-a4d61cb322ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432727821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3432727821
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2650986456
Short name T92
Test name
Test status
Simulation time 112273635 ps
CPU time 1.34 seconds
Started Jul 01 10:39:06 AM PDT 24
Finished Jul 01 10:39:10 AM PDT 24
Peak memory 200180 kb
Host smart-a807a275-e56c-4d90-8682-6e7dddc9e612
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650986456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
650986456
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2311888232
Short name T579
Test name
Test status
Simulation time 1522123042 ps
CPU time 8.74 seconds
Started Jul 01 10:39:12 AM PDT 24
Finished Jul 01 10:39:23 AM PDT 24
Peak memory 200212 kb
Host smart-48ad2177-230b-4ba3-8e37-b9eda22b626c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311888232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
311888232
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2320279543
Short name T583
Test name
Test status
Simulation time 145534174 ps
CPU time 1.06 seconds
Started Jul 01 10:39:02 AM PDT 24
Finished Jul 01 10:39:03 AM PDT 24
Peak memory 200024 kb
Host smart-c72b07f2-be47-4363-8405-2d3681da871c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320279543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
320279543
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2986283265
Short name T551
Test name
Test status
Simulation time 153951482 ps
CPU time 1.33 seconds
Started Jul 01 10:39:11 AM PDT 24
Finished Jul 01 10:39:14 AM PDT 24
Peak memory 208276 kb
Host smart-ca2ad5c4-62d3-4f1a-af94-a9da60f17362
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986283265 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2986283265
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1144613798
Short name T559
Test name
Test status
Simulation time 57949843 ps
CPU time 0.75 seconds
Started Jul 01 10:39:35 AM PDT 24
Finished Jul 01 10:39:39 AM PDT 24
Peak memory 199980 kb
Host smart-9859474a-a8cb-4a18-8c58-70884ec84134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144613798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1144613798
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1961521083
Short name T558
Test name
Test status
Simulation time 115574345 ps
CPU time 1.16 seconds
Started Jul 01 10:38:54 AM PDT 24
Finished Jul 01 10:38:56 AM PDT 24
Peak memory 200188 kb
Host smart-43201769-a3a9-4958-a858-4601734d0023
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961521083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1961521083
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.156780560
Short name T577
Test name
Test status
Simulation time 263904391 ps
CPU time 2.01 seconds
Started Jul 01 10:39:08 AM PDT 24
Finished Jul 01 10:39:13 AM PDT 24
Peak memory 208400 kb
Host smart-c0e3da92-fc48-4136-a4dd-3eefaa6554ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156780560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.156780560
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1670638913
Short name T612
Test name
Test status
Simulation time 494617807 ps
CPU time 1.86 seconds
Started Jul 01 10:38:56 AM PDT 24
Finished Jul 01 10:38:59 AM PDT 24
Peak memory 200272 kb
Host smart-7952ccf6-d086-4a36-8de4-790a06c6aedf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670638913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1670638913
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.706968140
Short name T556
Test name
Test status
Simulation time 192995887 ps
CPU time 1.29 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:43 AM PDT 24
Peak memory 208384 kb
Host smart-62930746-3e01-4df9-9f64-73a415c84fd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706968140 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.706968140
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1268978176
Short name T581
Test name
Test status
Simulation time 62828321 ps
CPU time 0.76 seconds
Started Jul 01 10:39:05 AM PDT 24
Finished Jul 01 10:39:08 AM PDT 24
Peak memory 199904 kb
Host smart-2b1d1e06-582b-4741-addb-39293a65ffdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268978176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1268978176
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.46320290
Short name T99
Test name
Test status
Simulation time 78159207 ps
CPU time 0.99 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:35 AM PDT 24
Peak memory 200124 kb
Host smart-12e88e99-570e-4074-8e56-0f8fb94fa8d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46320290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same
_csr_outstanding.46320290
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2521387587
Short name T555
Test name
Test status
Simulation time 441776267 ps
CPU time 2.95 seconds
Started Jul 01 10:39:29 AM PDT 24
Finished Jul 01 10:39:33 AM PDT 24
Peak memory 211780 kb
Host smart-fee5e901-2448-4198-9a2b-96108aa8cb21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521387587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2521387587
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1861749007
Short name T562
Test name
Test status
Simulation time 467614972 ps
CPU time 1.93 seconds
Started Jul 01 10:38:42 AM PDT 24
Finished Jul 01 10:38:44 AM PDT 24
Peak memory 200156 kb
Host smart-95a0fc3b-2dcc-42a4-8767-17ae2e4f79a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861749007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1861749007
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2133095648
Short name T554
Test name
Test status
Simulation time 108990822 ps
CPU time 0.95 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:39:34 AM PDT 24
Peak memory 200176 kb
Host smart-1a3106ae-ece7-4f4b-97ca-958a6e281a23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133095648 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2133095648
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1389255391
Short name T543
Test name
Test status
Simulation time 70535997 ps
CPU time 0.8 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:56 AM PDT 24
Peak memory 200400 kb
Host smart-46eec75f-0dd3-489f-937b-d307e3259753
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389255391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1389255391
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4143131803
Short name T100
Test name
Test status
Simulation time 186736340 ps
CPU time 1.46 seconds
Started Jul 01 10:39:24 AM PDT 24
Finished Jul 01 10:39:27 AM PDT 24
Peak memory 200204 kb
Host smart-e7d63e2a-fa63-47ee-bc08-f6c02b0d3731
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143131803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.4143131803
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2137615336
Short name T573
Test name
Test status
Simulation time 196368570 ps
CPU time 1.64 seconds
Started Jul 01 10:38:58 AM PDT 24
Finished Jul 01 10:39:00 AM PDT 24
Peak memory 208356 kb
Host smart-315cd164-5eaf-4fa8-8091-2d530a80ac7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137615336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2137615336
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3882007350
Short name T588
Test name
Test status
Simulation time 437084538 ps
CPU time 1.93 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:07 AM PDT 24
Peak memory 200352 kb
Host smart-deae1549-5f70-4a9a-b387-9df47e155d23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882007350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3882007350
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2288321631
Short name T620
Test name
Test status
Simulation time 164440263 ps
CPU time 1.56 seconds
Started Jul 01 10:39:33 AM PDT 24
Finished Jul 01 10:39:37 AM PDT 24
Peak memory 208452 kb
Host smart-e89be4f4-5f0c-41ac-9f64-a16ed4cdbf74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288321631 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2288321631
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2466767554
Short name T549
Test name
Test status
Simulation time 75109600 ps
CPU time 0.86 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:06 AM PDT 24
Peak memory 200040 kb
Host smart-d0ae3823-e9aa-4959-b0ae-3acd7792768a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466767554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2466767554
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4276290248
Short name T60
Test name
Test status
Simulation time 224446427 ps
CPU time 1.39 seconds
Started Jul 01 10:39:07 AM PDT 24
Finished Jul 01 10:39:11 AM PDT 24
Peak memory 200204 kb
Host smart-639a72e7-aae0-409b-ad26-8fcac5cc153b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276290248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.4276290248
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3046931
Short name T576
Test name
Test status
Simulation time 323652919 ps
CPU time 2.25 seconds
Started Jul 01 10:39:23 AM PDT 24
Finished Jul 01 10:39:26 AM PDT 24
Peak memory 208440 kb
Host smart-d0dddf6b-6413-4e5d-b14b-89cadfc6238f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3046931
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3218005267
Short name T561
Test name
Test status
Simulation time 450539426 ps
CPU time 1.94 seconds
Started Jul 01 10:38:57 AM PDT 24
Finished Jul 01 10:39:00 AM PDT 24
Peak memory 200148 kb
Host smart-dbef8c75-a2a9-4004-8450-7a92ae05e468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218005267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3218005267
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4164479633
Short name T84
Test name
Test status
Simulation time 160278002 ps
CPU time 1.53 seconds
Started Jul 01 10:38:49 AM PDT 24
Finished Jul 01 10:38:51 AM PDT 24
Peak memory 208460 kb
Host smart-dee9fb7e-0ef1-4479-bcfe-193edc3b1190
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164479633 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.4164479633
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4188700331
Short name T544
Test name
Test status
Simulation time 73950827 ps
CPU time 0.86 seconds
Started Jul 01 10:38:54 AM PDT 24
Finished Jul 01 10:38:56 AM PDT 24
Peak memory 199976 kb
Host smart-7453161a-6f81-4871-bb3a-9ad0850501c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188700331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4188700331
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3782893839
Short name T61
Test name
Test status
Simulation time 229447011 ps
CPU time 1.53 seconds
Started Jul 01 10:39:20 AM PDT 24
Finished Jul 01 10:39:23 AM PDT 24
Peak memory 200288 kb
Host smart-41db06b8-05bf-4ec6-ad9c-8f6d48a3e751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782893839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3782893839
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.41472295
Short name T586
Test name
Test status
Simulation time 535653677 ps
CPU time 4.15 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:59 AM PDT 24
Peak memory 208392 kb
Host smart-522d79e9-9357-4e78-9fd5-202254b12240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41472295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.41472295
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1646646514
Short name T611
Test name
Test status
Simulation time 466530326 ps
CPU time 1.81 seconds
Started Jul 01 10:38:50 AM PDT 24
Finished Jul 01 10:38:54 AM PDT 24
Peak memory 200224 kb
Host smart-84eebff3-fe04-45d0-8f92-9c23b4f6031c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646646514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1646646514
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1877840283
Short name T569
Test name
Test status
Simulation time 94234799 ps
CPU time 0.95 seconds
Started Jul 01 10:39:17 AM PDT 24
Finished Jul 01 10:39:19 AM PDT 24
Peak memory 208364 kb
Host smart-efba02a5-e097-42a1-b06c-55e4ae9cf65f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877840283 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1877840283
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2162813799
Short name T567
Test name
Test status
Simulation time 73195967 ps
CPU time 0.82 seconds
Started Jul 01 10:39:02 AM PDT 24
Finished Jul 01 10:39:03 AM PDT 24
Peak memory 200012 kb
Host smart-cfc71214-89ed-4b07-8d68-5c10712d096e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162813799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2162813799
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.69197131
Short name T582
Test name
Test status
Simulation time 232903213 ps
CPU time 1.48 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:39:34 AM PDT 24
Peak memory 200260 kb
Host smart-b569ad44-af56-4d01-a678-e815d95d11c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69197131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same
_csr_outstanding.69197131
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1001982079
Short name T557
Test name
Test status
Simulation time 475198485 ps
CPU time 3.01 seconds
Started Jul 01 10:39:04 AM PDT 24
Finished Jul 01 10:39:10 AM PDT 24
Peak memory 208360 kb
Host smart-b7848051-1988-4a6f-9c99-9437a9937af9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001982079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1001982079
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.327010922
Short name T584
Test name
Test status
Simulation time 466483092 ps
CPU time 1.84 seconds
Started Jul 01 10:38:46 AM PDT 24
Finished Jul 01 10:38:49 AM PDT 24
Peak memory 200400 kb
Host smart-6ca7ea78-8353-4ec1-b71c-05acbc734a0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327010922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
327010922
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3712757059
Short name T166
Test name
Test status
Simulation time 69658273 ps
CPU time 0.78 seconds
Started Jul 01 10:41:32 AM PDT 24
Finished Jul 01 10:41:34 AM PDT 24
Peak memory 199728 kb
Host smart-76231a5f-6f9c-4b56-b874-845179152c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712757059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3712757059
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3072523617
Short name T538
Test name
Test status
Simulation time 1241708040 ps
CPU time 5.66 seconds
Started Jul 01 10:41:53 AM PDT 24
Finished Jul 01 10:42:01 AM PDT 24
Peak memory 217560 kb
Host smart-1dc1ac1c-505f-46a1-a27e-ae1fae680cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072523617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3072523617
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.214895758
Short name T295
Test name
Test status
Simulation time 243407307 ps
CPU time 1.14 seconds
Started Jul 01 10:41:30 AM PDT 24
Finished Jul 01 10:41:33 AM PDT 24
Peak memory 217312 kb
Host smart-0b29d4ce-89b6-44c3-a6c2-30d52101af6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214895758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.214895758
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.438080260
Short name T504
Test name
Test status
Simulation time 178077555 ps
CPU time 0.9 seconds
Started Jul 01 10:41:30 AM PDT 24
Finished Jul 01 10:41:33 AM PDT 24
Peak memory 199792 kb
Host smart-7df21ae0-fa76-43b0-b4fb-0c6bce58c2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438080260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.438080260
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2899634089
Short name T174
Test name
Test status
Simulation time 1141827338 ps
CPU time 5.49 seconds
Started Jul 01 10:41:32 AM PDT 24
Finished Jul 01 10:41:38 AM PDT 24
Peak memory 200260 kb
Host smart-1e4e1d97-9e7a-4330-8fed-8530c2a2be1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899634089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2899634089
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.445736942
Short name T67
Test name
Test status
Simulation time 8410387844 ps
CPU time 12.97 seconds
Started Jul 01 10:41:53 AM PDT 24
Finished Jul 01 10:42:08 AM PDT 24
Peak memory 217060 kb
Host smart-f4d31fb4-3b40-4acd-ae57-98e8821df766
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445736942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.445736942
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2954137573
Short name T482
Test name
Test status
Simulation time 107980869 ps
CPU time 1.01 seconds
Started Jul 01 10:41:45 AM PDT 24
Finished Jul 01 10:41:46 AM PDT 24
Peak memory 199900 kb
Host smart-ee14e55c-29e2-4c9d-8fbf-d34d712793c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954137573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2954137573
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1090705144
Short name T162
Test name
Test status
Simulation time 121110871 ps
CPU time 1.27 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:06 AM PDT 24
Peak memory 200204 kb
Host smart-a72fcf42-2553-4462-a625-3ca7090638cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090705144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1090705144
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3613730743
Short name T337
Test name
Test status
Simulation time 8129549494 ps
CPU time 32.93 seconds
Started Jul 01 10:41:34 AM PDT 24
Finished Jul 01 10:42:08 AM PDT 24
Peak memory 216944 kb
Host smart-881198be-cccd-4334-b1e5-1cebdeda9bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613730743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3613730743
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2959998471
Short name T371
Test name
Test status
Simulation time 290736761 ps
CPU time 2.08 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:07 AM PDT 24
Peak memory 208144 kb
Host smart-123c738c-0387-4464-8049-449a539206e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959998471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2959998471
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2098757148
Short name T273
Test name
Test status
Simulation time 157872376 ps
CPU time 1.31 seconds
Started Jul 01 10:41:33 AM PDT 24
Finished Jul 01 10:41:35 AM PDT 24
Peak memory 199924 kb
Host smart-dd5ff457-1a28-4733-9b28-5ba1133177f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098757148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2098757148
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4047119631
Short name T178
Test name
Test status
Simulation time 77774219 ps
CPU time 0.87 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:06 AM PDT 24
Peak memory 199732 kb
Host smart-1d6d85b2-99e2-42d2-b196-2d25b875b717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047119631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4047119631
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2834793295
Short name T323
Test name
Test status
Simulation time 1226128116 ps
CPU time 6.31 seconds
Started Jul 01 10:42:06 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 221460 kb
Host smart-a7055f3c-3c06-44d0-aea7-a024fa79f2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834793295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2834793295
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.4230394788
Short name T499
Test name
Test status
Simulation time 243995260 ps
CPU time 1.1 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:16 AM PDT 24
Peak memory 217376 kb
Host smart-aa9b5ec0-db56-4972-852a-3bc22f19994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230394788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.4230394788
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1611301046
Short name T37
Test name
Test status
Simulation time 954794216 ps
CPU time 4.79 seconds
Started Jul 01 10:41:52 AM PDT 24
Finished Jul 01 10:41:59 AM PDT 24
Peak memory 200216 kb
Host smart-c8fb9fa9-a87b-4384-aa76-070ae683a0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611301046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1611301046
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3227030605
Short name T70
Test name
Test status
Simulation time 10378779941 ps
CPU time 18.77 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:26 AM PDT 24
Peak memory 216872 kb
Host smart-20684441-49d0-4084-b715-d9f23c1f69fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227030605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3227030605
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1568733273
Short name T455
Test name
Test status
Simulation time 182077362 ps
CPU time 1.23 seconds
Started Jul 01 10:41:31 AM PDT 24
Finished Jul 01 10:41:34 AM PDT 24
Peak memory 199944 kb
Host smart-9596941e-0541-469d-ac51-fd4620404506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568733273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1568733273
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2850866156
Short name T292
Test name
Test status
Simulation time 114074261 ps
CPU time 1.2 seconds
Started Jul 01 10:41:33 AM PDT 24
Finished Jul 01 10:41:35 AM PDT 24
Peak memory 200148 kb
Host smart-647f799c-1b17-4ec6-bc90-ca21520b772e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850866156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2850866156
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3394671536
Short name T389
Test name
Test status
Simulation time 12914219930 ps
CPU time 42.58 seconds
Started Jul 01 10:41:40 AM PDT 24
Finished Jul 01 10:42:23 AM PDT 24
Peak memory 208516 kb
Host smart-72a9031b-878b-48f6-a343-98eca9226975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394671536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3394671536
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1514479696
Short name T46
Test name
Test status
Simulation time 122150917 ps
CPU time 1.45 seconds
Started Jul 01 10:41:29 AM PDT 24
Finished Jul 01 10:41:33 AM PDT 24
Peak memory 199940 kb
Host smart-12911b4f-0650-4da3-802b-446541c19bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514479696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1514479696
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1795632463
Short name T226
Test name
Test status
Simulation time 66455569 ps
CPU time 0.87 seconds
Started Jul 01 10:41:54 AM PDT 24
Finished Jul 01 10:41:57 AM PDT 24
Peak memory 199768 kb
Host smart-5d8babe8-53e0-4b25-bee0-1d52bec1a923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795632463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1795632463
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2355261832
Short name T500
Test name
Test status
Simulation time 245025346 ps
CPU time 1.11 seconds
Started Jul 01 10:41:53 AM PDT 24
Finished Jul 01 10:41:56 AM PDT 24
Peak memory 217296 kb
Host smart-b0a5b598-f8ef-4a24-964f-5f0d3f3c2742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355261832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2355261832
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2499827659
Short name T501
Test name
Test status
Simulation time 83313554 ps
CPU time 0.76 seconds
Started Jul 01 10:42:12 AM PDT 24
Finished Jul 01 10:42:16 AM PDT 24
Peak memory 199836 kb
Host smart-f20bfa62-040b-4bff-8a04-9c56b242acf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499827659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2499827659
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2020131149
Short name T308
Test name
Test status
Simulation time 1460044049 ps
CPU time 5.32 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:19 AM PDT 24
Peak memory 200112 kb
Host smart-7840cd2f-256a-4baa-85b8-a78b8c94044a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020131149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2020131149
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1086854568
Short name T200
Test name
Test status
Simulation time 169904522 ps
CPU time 1.29 seconds
Started Jul 01 10:41:49 AM PDT 24
Finished Jul 01 10:41:50 AM PDT 24
Peak memory 199924 kb
Host smart-b226cc94-f3b9-43a4-8d8d-d63264549482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086854568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1086854568
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.256407927
Short name T304
Test name
Test status
Simulation time 119948326 ps
CPU time 1.24 seconds
Started Jul 01 10:42:08 AM PDT 24
Finished Jul 01 10:42:12 AM PDT 24
Peak memory 200244 kb
Host smart-63eac469-7cf3-4ce9-b276-4b3bc7b5113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256407927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.256407927
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3338317125
Short name T93
Test name
Test status
Simulation time 5498941563 ps
CPU time 23.2 seconds
Started Jul 01 10:42:12 AM PDT 24
Finished Jul 01 10:42:38 AM PDT 24
Peak memory 208496 kb
Host smart-6bc31e79-ae62-4045-be41-18a976ddca78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338317125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3338317125
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1857176249
Short name T367
Test name
Test status
Simulation time 130105655 ps
CPU time 1.55 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:08 AM PDT 24
Peak memory 199940 kb
Host smart-a8b252da-68af-48fc-b7ff-9835b7fbb40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857176249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1857176249
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.736361131
Short name T220
Test name
Test status
Simulation time 68412395 ps
CPU time 0.74 seconds
Started Jul 01 10:42:11 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 199948 kb
Host smart-534ebeeb-32c1-4c78-825c-c147a281d6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736361131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.736361131
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2763880571
Short name T480
Test name
Test status
Simulation time 76651300 ps
CPU time 0.81 seconds
Started Jul 01 10:41:56 AM PDT 24
Finished Jul 01 10:41:59 AM PDT 24
Peak memory 199724 kb
Host smart-7e87c431-b935-49db-99d2-5f83296359ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763880571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2763880571
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1014313606
Short name T537
Test name
Test status
Simulation time 245030674 ps
CPU time 1.03 seconds
Started Jul 01 10:42:08 AM PDT 24
Finished Jul 01 10:42:17 AM PDT 24
Peak memory 217320 kb
Host smart-da448e8a-ffa5-4488-bf96-ce21959a8721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014313606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1014313606
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2733398444
Short name T294
Test name
Test status
Simulation time 100778676 ps
CPU time 0.79 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 199832 kb
Host smart-2290f6c8-3056-4278-9f7a-c9657a64b18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733398444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2733398444
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3424099939
Short name T123
Test name
Test status
Simulation time 1504826670 ps
CPU time 5.32 seconds
Started Jul 01 10:42:37 AM PDT 24
Finished Jul 01 10:42:44 AM PDT 24
Peak memory 200216 kb
Host smart-c7417fb5-57eb-46e6-bea5-b6700be1fe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424099939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3424099939
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3627245011
Short name T469
Test name
Test status
Simulation time 181912254 ps
CPU time 1.21 seconds
Started Jul 01 10:41:55 AM PDT 24
Finished Jul 01 10:41:59 AM PDT 24
Peak memory 199928 kb
Host smart-881cf27d-b3d7-458e-ba7c-7021531b3a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627245011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3627245011
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3458264603
Short name T246
Test name
Test status
Simulation time 264444491 ps
CPU time 1.54 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 200116 kb
Host smart-59492a62-c4bb-4caf-ab4d-1c446e1430ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458264603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3458264603
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3258525381
Short name T424
Test name
Test status
Simulation time 5385123203 ps
CPU time 20.64 seconds
Started Jul 01 10:41:56 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 208524 kb
Host smart-b251d213-3114-4fe0-b394-0e9a5e0c6e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258525381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3258525381
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1506548348
Short name T236
Test name
Test status
Simulation time 337000456 ps
CPU time 2.28 seconds
Started Jul 01 10:42:12 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 200116 kb
Host smart-914033c2-3190-49fd-87a5-9b9604e22af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506548348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1506548348
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.655099705
Short name T78
Test name
Test status
Simulation time 242778499 ps
CPU time 1.48 seconds
Started Jul 01 10:41:54 AM PDT 24
Finished Jul 01 10:41:57 AM PDT 24
Peak memory 200180 kb
Host smart-e3fa4a51-77e1-4bc0-bbeb-dca44773faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655099705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.655099705
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2487316029
Short name T534
Test name
Test status
Simulation time 70816376 ps
CPU time 0.75 seconds
Started Jul 01 10:41:54 AM PDT 24
Finished Jul 01 10:41:57 AM PDT 24
Peak memory 199788 kb
Host smart-57e96c6d-03f3-4e26-9bcf-772c5f6aea71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487316029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2487316029
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1926210677
Short name T223
Test name
Test status
Simulation time 1880127016 ps
CPU time 8.87 seconds
Started Jul 01 10:41:54 AM PDT 24
Finished Jul 01 10:42:05 AM PDT 24
Peak memory 216696 kb
Host smart-533069dc-a588-4115-b7e1-74eba0e6bfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926210677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1926210677
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2892473255
Short name T369
Test name
Test status
Simulation time 244329775 ps
CPU time 1.11 seconds
Started Jul 01 10:41:53 AM PDT 24
Finished Jul 01 10:41:56 AM PDT 24
Peak memory 217368 kb
Host smart-b42eca11-d879-43ad-94c8-167cd4d43c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892473255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2892473255
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3368598818
Short name T251
Test name
Test status
Simulation time 171064591 ps
CPU time 0.86 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 199852 kb
Host smart-98c44173-403d-4522-b3ff-2e1a2bcb379e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368598818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3368598818
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1086177925
Short name T394
Test name
Test status
Simulation time 1257542107 ps
CPU time 5.22 seconds
Started Jul 01 10:42:06 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 200216 kb
Host smart-2ff03685-be61-472e-8c9d-4b856378526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086177925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1086177925
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3002722236
Short name T290
Test name
Test status
Simulation time 200442770 ps
CPU time 1.38 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 200128 kb
Host smart-b25be438-5f34-4158-8f94-d126769986ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002722236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3002722236
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1034996591
Short name T118
Test name
Test status
Simulation time 9847692010 ps
CPU time 34.34 seconds
Started Jul 01 10:41:56 AM PDT 24
Finished Jul 01 10:42:33 AM PDT 24
Peak memory 210320 kb
Host smart-05d00ce5-8729-420f-97e1-7ddca81ee3b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034996591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1034996591
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.906991237
Short name T83
Test name
Test status
Simulation time 118733324 ps
CPU time 1.61 seconds
Started Jul 01 10:41:55 AM PDT 24
Finished Jul 01 10:41:59 AM PDT 24
Peak memory 199964 kb
Host smart-33d0f813-5890-407e-8d32-b4cb34cb22f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906991237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.906991237
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1689138876
Short name T289
Test name
Test status
Simulation time 272453657 ps
CPU time 1.45 seconds
Started Jul 01 10:41:55 AM PDT 24
Finished Jul 01 10:41:59 AM PDT 24
Peak memory 199960 kb
Host smart-6e8355c0-3607-455e-99f8-6c87436dd29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689138876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1689138876
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2923227719
Short name T134
Test name
Test status
Simulation time 90371971 ps
CPU time 0.87 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 199656 kb
Host smart-f4c5847b-81aa-48ec-b83e-81633e540f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923227719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2923227719
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1513659986
Short name T55
Test name
Test status
Simulation time 2356056161 ps
CPU time 7.91 seconds
Started Jul 01 10:42:33 AM PDT 24
Finished Jul 01 10:42:41 AM PDT 24
Peak memory 221560 kb
Host smart-1e103c3e-ea59-4ce6-b110-273e4f15f2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513659986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1513659986
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1450530093
Short name T511
Test name
Test status
Simulation time 164868639 ps
CPU time 0.91 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 199752 kb
Host smart-de91141e-f1b9-4fd6-a6ca-0c206f1ea58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450530093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1450530093
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2612881748
Short name T364
Test name
Test status
Simulation time 1457374665 ps
CPU time 5.86 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:19 AM PDT 24
Peak memory 200216 kb
Host smart-6b64315e-7071-46e2-8159-8b763ccf9a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612881748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2612881748
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.93552853
Short name T441
Test name
Test status
Simulation time 173245117 ps
CPU time 1.16 seconds
Started Jul 01 10:41:57 AM PDT 24
Finished Jul 01 10:42:00 AM PDT 24
Peak memory 200000 kb
Host smart-f1113fbe-917e-44e5-806b-bd7725882381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93552853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.93552853
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.17495106
Short name T315
Test name
Test status
Simulation time 111907965 ps
CPU time 1.16 seconds
Started Jul 01 10:41:53 AM PDT 24
Finished Jul 01 10:41:56 AM PDT 24
Peak memory 200144 kb
Host smart-05cf0e69-e0a5-45b1-b13e-46c958609404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17495106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.17495106
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3713386829
Short name T330
Test name
Test status
Simulation time 4103944906 ps
CPU time 15.16 seconds
Started Jul 01 10:41:58 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 208524 kb
Host smart-6254ceb1-817d-4f23-8a6b-a52b289d4bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713386829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3713386829
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1818629866
Short name T321
Test name
Test status
Simulation time 503123443 ps
CPU time 2.87 seconds
Started Jul 01 10:42:00 AM PDT 24
Finished Jul 01 10:42:04 AM PDT 24
Peak memory 199940 kb
Host smart-cdc54bc1-ca4c-47b8-b656-6996e67153f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818629866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1818629866
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3495952070
Short name T421
Test name
Test status
Simulation time 59499096 ps
CPU time 0.76 seconds
Started Jul 01 10:42:11 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 199884 kb
Host smart-23603b32-135b-4123-966c-57969c84186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495952070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3495952070
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.477839279
Short name T256
Test name
Test status
Simulation time 57782172 ps
CPU time 0.76 seconds
Started Jul 01 10:41:59 AM PDT 24
Finished Jul 01 10:42:01 AM PDT 24
Peak memory 199720 kb
Host smart-0a93ca10-8231-453b-9463-88eadc3a026f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477839279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.477839279
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1594092212
Short name T465
Test name
Test status
Simulation time 1893760981 ps
CPU time 7.22 seconds
Started Jul 01 10:41:58 AM PDT 24
Finished Jul 01 10:42:07 AM PDT 24
Peak memory 217636 kb
Host smart-80aaadaa-42cf-4768-a4ae-5eb00a973519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594092212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1594092212
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3287545608
Short name T489
Test name
Test status
Simulation time 246610866 ps
CPU time 1.09 seconds
Started Jul 01 10:41:59 AM PDT 24
Finished Jul 01 10:42:02 AM PDT 24
Peak memory 217284 kb
Host smart-879b010f-5bd0-4288-ac0d-b6e488978688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287545608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3287545608
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2300498082
Short name T392
Test name
Test status
Simulation time 109658727 ps
CPU time 0.8 seconds
Started Jul 01 10:41:57 AM PDT 24
Finished Jul 01 10:41:59 AM PDT 24
Peak memory 199752 kb
Host smart-91ad84e5-2d48-4c5f-ace6-37e16b101c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300498082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2300498082
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3571450384
Short name T401
Test name
Test status
Simulation time 844823702 ps
CPU time 4.32 seconds
Started Jul 01 10:41:59 AM PDT 24
Finished Jul 01 10:42:05 AM PDT 24
Peak memory 200240 kb
Host smart-7e36743c-22cb-47ca-aa30-6bba7c46edfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571450384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3571450384
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3215065920
Short name T483
Test name
Test status
Simulation time 111201978 ps
CPU time 1.1 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:12 AM PDT 24
Peak memory 200108 kb
Host smart-a4013383-bcd1-42b5-915c-840f3f4aeebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215065920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3215065920
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.251563097
Short name T463
Test name
Test status
Simulation time 197701955 ps
CPU time 1.37 seconds
Started Jul 01 10:41:57 AM PDT 24
Finished Jul 01 10:42:00 AM PDT 24
Peak memory 200164 kb
Host smart-90295d3f-d60b-4087-8fd4-f9d47b03f337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251563097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.251563097
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2472050784
Short name T326
Test name
Test status
Simulation time 4294144928 ps
CPU time 19.28 seconds
Started Jul 01 10:42:00 AM PDT 24
Finished Jul 01 10:42:20 AM PDT 24
Peak memory 200244 kb
Host smart-af0ae981-7383-4fc6-8ce1-f3f00ad4243b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472050784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2472050784
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.4025666435
Short name T488
Test name
Test status
Simulation time 307704387 ps
CPU time 2 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 199860 kb
Host smart-0e89462f-fced-4400-b388-57faa5182523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025666435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.4025666435
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3454892766
Short name T138
Test name
Test status
Simulation time 207322749 ps
CPU time 1.28 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 199948 kb
Host smart-4b0ab67d-8e16-43f4-be27-c9e350a57003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454892766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3454892766
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.153635509
Short name T442
Test name
Test status
Simulation time 69404757 ps
CPU time 0.76 seconds
Started Jul 01 10:42:03 AM PDT 24
Finished Jul 01 10:42:05 AM PDT 24
Peak memory 199672 kb
Host smart-d6af3144-33f7-4c66-9ec4-b533ee2c148f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153635509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.153635509
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.358761253
Short name T122
Test name
Test status
Simulation time 2355750703 ps
CPU time 8.6 seconds
Started Jul 01 10:42:13 AM PDT 24
Finished Jul 01 10:42:25 AM PDT 24
Peak memory 217564 kb
Host smart-d82eb361-b87e-4f9b-8a70-838ea645fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358761253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.358761253
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3149422814
Short name T160
Test name
Test status
Simulation time 243497826 ps
CPU time 1.18 seconds
Started Jul 01 10:41:59 AM PDT 24
Finished Jul 01 10:42:02 AM PDT 24
Peak memory 217320 kb
Host smart-230be3d1-b53a-41ae-89d6-15f14879c76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149422814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3149422814
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.868715949
Short name T451
Test name
Test status
Simulation time 164108253 ps
CPU time 0.85 seconds
Started Jul 01 10:41:57 AM PDT 24
Finished Jul 01 10:42:00 AM PDT 24
Peak memory 199812 kb
Host smart-b8f3bd39-893e-4952-b096-de057d2afbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868715949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.868715949
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.4221585208
Short name T281
Test name
Test status
Simulation time 1709169632 ps
CPU time 7.15 seconds
Started Jul 01 10:42:13 AM PDT 24
Finished Jul 01 10:42:23 AM PDT 24
Peak memory 200276 kb
Host smart-4ce90c04-19bc-4854-b46a-7c961d59565a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221585208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.4221585208
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3775951978
Short name T248
Test name
Test status
Simulation time 188623624 ps
CPU time 1.31 seconds
Started Jul 01 10:41:59 AM PDT 24
Finished Jul 01 10:42:02 AM PDT 24
Peak memory 199948 kb
Host smart-fe471deb-b6f3-400b-9949-cc64c2d3c35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775951978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3775951978
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.105563163
Short name T539
Test name
Test status
Simulation time 235334009 ps
CPU time 1.52 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 200132 kb
Host smart-d67492f5-29c6-438d-ac29-1b9290310f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105563163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.105563163
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3721308855
Short name T80
Test name
Test status
Simulation time 4544239339 ps
CPU time 21.61 seconds
Started Jul 01 10:42:14 AM PDT 24
Finished Jul 01 10:42:38 AM PDT 24
Peak memory 210320 kb
Host smart-670ea6a0-2cf4-4c76-8ac0-fc1a729c4fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721308855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3721308855
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2648558190
Short name T3
Test name
Test status
Simulation time 466274793 ps
CPU time 2.38 seconds
Started Jul 01 10:42:11 AM PDT 24
Finished Jul 01 10:42:17 AM PDT 24
Peak memory 199940 kb
Host smart-90670ced-eaea-4d5d-9029-f330bcee8869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648558190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2648558190
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1952157643
Short name T481
Test name
Test status
Simulation time 170023967 ps
CPU time 1.17 seconds
Started Jul 01 10:42:24 AM PDT 24
Finished Jul 01 10:42:25 AM PDT 24
Peak memory 200016 kb
Host smart-e27888d5-d54f-48e6-a661-69a786f86516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952157643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1952157643
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.717364182
Short name T516
Test name
Test status
Simulation time 63743388 ps
CPU time 0.79 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 199740 kb
Host smart-596087be-1184-43e5-a3eb-1c9137478b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717364182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.717364182
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2964016419
Short name T35
Test name
Test status
Simulation time 244289260 ps
CPU time 1.12 seconds
Started Jul 01 10:42:01 AM PDT 24
Finished Jul 01 10:42:03 AM PDT 24
Peak memory 217628 kb
Host smart-f3b58dbd-bf87-46b4-98a6-eb1be0d729a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964016419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2964016419
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3257860496
Short name T531
Test name
Test status
Simulation time 178823602 ps
CPU time 0.92 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:06 AM PDT 24
Peak memory 199656 kb
Host smart-508e4216-8780-4932-9a77-3bd4b705627f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257860496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3257860496
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4102826028
Short name T117
Test name
Test status
Simulation time 1496412007 ps
CPU time 5.93 seconds
Started Jul 01 10:42:17 AM PDT 24
Finished Jul 01 10:42:24 AM PDT 24
Peak memory 200280 kb
Host smart-684fdf7c-2fc6-4f42-a6e8-0ed5a1a50986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102826028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4102826028
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.257374562
Short name T288
Test name
Test status
Simulation time 168657948 ps
CPU time 1.18 seconds
Started Jul 01 10:42:14 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 200008 kb
Host smart-a1a9e2d2-aad0-49f3-8690-e237a2afc85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257374562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.257374562
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3436419201
Short name T459
Test name
Test status
Simulation time 113827049 ps
CPU time 1.19 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 200128 kb
Host smart-cbea6fe9-4f9b-49a2-9c3c-09265f45836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436419201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3436419201
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3632675054
Short name T487
Test name
Test status
Simulation time 10895614748 ps
CPU time 37.57 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:42 AM PDT 24
Peak memory 200392 kb
Host smart-9b361dec-7fb8-4096-bd08-1d355ea359e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632675054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3632675054
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1019535617
Short name T425
Test name
Test status
Simulation time 502530652 ps
CPU time 2.9 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:08 AM PDT 24
Peak memory 199916 kb
Host smart-80cce0be-adfe-42b7-a9ca-44abc10037f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019535617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1019535617
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2815499317
Short name T370
Test name
Test status
Simulation time 82370822 ps
CPU time 0.85 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 199872 kb
Host smart-ab0a2821-0a85-45b4-9972-cd027e881711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815499317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2815499317
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.944505199
Short name T190
Test name
Test status
Simulation time 79947730 ps
CPU time 0.85 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 199736 kb
Host smart-eb82566e-83ef-488a-882b-13e6d2e0f597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944505199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.944505199
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1748161042
Short name T390
Test name
Test status
Simulation time 1884544328 ps
CPU time 7.39 seconds
Started Jul 01 10:42:30 AM PDT 24
Finished Jul 01 10:42:38 AM PDT 24
Peak memory 217472 kb
Host smart-024aa6ca-feaa-49cf-9383-642d8e1e22aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748161042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1748161042
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.405115256
Short name T74
Test name
Test status
Simulation time 243623921 ps
CPU time 1.21 seconds
Started Jul 01 10:42:03 AM PDT 24
Finished Jul 01 10:42:05 AM PDT 24
Peak memory 217364 kb
Host smart-830bce9d-6b6a-4e98-b9d9-fc278cf021ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405115256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.405115256
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3820821012
Short name T355
Test name
Test status
Simulation time 229870503 ps
CPU time 1.09 seconds
Started Jul 01 10:42:03 AM PDT 24
Finished Jul 01 10:42:05 AM PDT 24
Peak memory 199816 kb
Host smart-f123e703-02f3-48e1-a82b-0cb154a196e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820821012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3820821012
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1533432374
Short name T303
Test name
Test status
Simulation time 858002766 ps
CPU time 4.47 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:09 AM PDT 24
Peak memory 200284 kb
Host smart-67df72dc-0de8-489f-8b65-25e5d16298bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533432374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1533432374
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.4002814733
Short name T126
Test name
Test status
Simulation time 146321755 ps
CPU time 1.14 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:07 AM PDT 24
Peak memory 199932 kb
Host smart-b45c9c21-6dbf-4acf-8c08-658a63f8ff90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002814733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.4002814733
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1304877159
Short name T344
Test name
Test status
Simulation time 128775258 ps
CPU time 1.29 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 200212 kb
Host smart-ece9e209-3de7-48a8-8c6a-d9e177bc8a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304877159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1304877159
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.114359976
Short name T464
Test name
Test status
Simulation time 590663144 ps
CPU time 2.67 seconds
Started Jul 01 10:42:11 AM PDT 24
Finished Jul 01 10:42:17 AM PDT 24
Peak memory 200112 kb
Host smart-a887fc71-6120-42c7-bb5d-eb672d7e8bf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114359976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.114359976
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4261680762
Short name T533
Test name
Test status
Simulation time 256148288 ps
CPU time 1.72 seconds
Started Jul 01 10:42:08 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 200024 kb
Host smart-7a90f30e-0113-491a-a62b-aa2096d4bb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261680762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4261680762
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2954326985
Short name T414
Test name
Test status
Simulation time 82991967 ps
CPU time 0.85 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:12 AM PDT 24
Peak memory 199952 kb
Host smart-443a97b5-86a8-466a-aac2-a80db597f831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954326985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2954326985
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1262711347
Short name T238
Test name
Test status
Simulation time 67454945 ps
CPU time 0.78 seconds
Started Jul 01 10:42:11 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 199764 kb
Host smart-e52699ee-ef8e-4969-8f6a-3dd082ff2607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262711347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1262711347
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1810575291
Short name T42
Test name
Test status
Simulation time 1879928953 ps
CPU time 7.5 seconds
Started Jul 01 10:42:38 AM PDT 24
Finished Jul 01 10:42:48 AM PDT 24
Peak memory 216728 kb
Host smart-40a6e5e2-bb31-44de-92bd-eaf13255dd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810575291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1810575291
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1541669944
Short name T217
Test name
Test status
Simulation time 243912229 ps
CPU time 1.1 seconds
Started Jul 01 10:42:31 AM PDT 24
Finished Jul 01 10:42:33 AM PDT 24
Peak memory 217320 kb
Host smart-37263c39-e383-41fb-8695-5148876f397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541669944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1541669944
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.951293439
Short name T402
Test name
Test status
Simulation time 185529214 ps
CPU time 0.87 seconds
Started Jul 01 10:42:13 AM PDT 24
Finished Jul 01 10:42:17 AM PDT 24
Peak memory 199812 kb
Host smart-a2dfe054-0b09-4841-9055-7224e798d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951293439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.951293439
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3230128732
Short name T361
Test name
Test status
Simulation time 944740673 ps
CPU time 4.48 seconds
Started Jul 01 10:42:06 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 200192 kb
Host smart-896a3aef-581c-4eba-a388-bced8b239fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230128732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3230128732
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.245717677
Short name T212
Test name
Test status
Simulation time 145411213 ps
CPU time 1.12 seconds
Started Jul 01 10:42:11 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 200032 kb
Host smart-56c2190c-2d9f-45e4-aeff-652753f7dbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245717677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.245717677
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3058299593
Short name T440
Test name
Test status
Simulation time 121900322 ps
CPU time 1.19 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 200060 kb
Host smart-8c387731-2c22-4b29-a9df-f0607d0bb0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058299593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3058299593
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.679305858
Short name T434
Test name
Test status
Simulation time 1621048355 ps
CPU time 7.13 seconds
Started Jul 01 10:42:38 AM PDT 24
Finished Jul 01 10:42:48 AM PDT 24
Peak memory 200260 kb
Host smart-89afd4f0-3066-4c5f-8353-f9b655cad19b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679305858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.679305858
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3121409064
Short name T171
Test name
Test status
Simulation time 288126261 ps
CPU time 1.95 seconds
Started Jul 01 10:42:16 AM PDT 24
Finished Jul 01 10:42:19 AM PDT 24
Peak memory 199944 kb
Host smart-9caa1280-e560-460d-a4d3-f936a36326c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121409064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3121409064
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1554756498
Short name T229
Test name
Test status
Simulation time 227535438 ps
CPU time 1.48 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:10 AM PDT 24
Peak memory 200020 kb
Host smart-514665c1-e01c-48ff-83af-c34878f8f8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554756498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1554756498
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1521234269
Short name T187
Test name
Test status
Simulation time 76411532 ps
CPU time 0.75 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:08 AM PDT 24
Peak memory 199796 kb
Host smart-611323a9-e4aa-4a5c-9177-b27786325d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521234269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1521234269
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1134256627
Short name T54
Test name
Test status
Simulation time 1231964698 ps
CPU time 5.38 seconds
Started Jul 01 10:42:08 AM PDT 24
Finished Jul 01 10:42:16 AM PDT 24
Peak memory 217436 kb
Host smart-0adaf0fb-a21f-4166-b3fb-5f56632c8bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134256627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1134256627
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4130365654
Short name T510
Test name
Test status
Simulation time 244989121 ps
CPU time 1.04 seconds
Started Jul 01 10:42:23 AM PDT 24
Finished Jul 01 10:42:25 AM PDT 24
Peak memory 217308 kb
Host smart-4a8bb8a6-b4cd-44c5-affb-75f9df240750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130365654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4130365654
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.648969159
Short name T348
Test name
Test status
Simulation time 93828705 ps
CPU time 0.82 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 199756 kb
Host smart-3cbef286-a92f-4bd3-b834-374401c6d0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648969159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.648969159
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1911041682
Short name T232
Test name
Test status
Simulation time 1108994552 ps
CPU time 5.24 seconds
Started Jul 01 10:42:27 AM PDT 24
Finished Jul 01 10:42:33 AM PDT 24
Peak memory 200224 kb
Host smart-66dd72cc-0255-450f-9106-810a5d24504e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911041682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1911041682
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1498808625
Short name T529
Test name
Test status
Simulation time 176153224 ps
CPU time 1.22 seconds
Started Jul 01 10:42:14 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 199940 kb
Host smart-40693348-dd50-47af-8e52-5108053e4787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498808625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1498808625
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1083358481
Short name T252
Test name
Test status
Simulation time 257775936 ps
CPU time 1.61 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 200188 kb
Host smart-e2005e9c-7ba8-4338-ba96-214cca263660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083358481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1083358481
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.485250092
Short name T297
Test name
Test status
Simulation time 8357798274 ps
CPU time 32.68 seconds
Started Jul 01 10:42:16 AM PDT 24
Finished Jul 01 10:42:55 AM PDT 24
Peak memory 200340 kb
Host smart-438bb5cb-877e-470e-b624-87ce1479c464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485250092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.485250092
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1056602590
Short name T36
Test name
Test status
Simulation time 165031561 ps
CPU time 1.15 seconds
Started Jul 01 10:42:12 AM PDT 24
Finished Jul 01 10:42:16 AM PDT 24
Peak memory 200044 kb
Host smart-b693be76-2800-4193-b81d-0e57ab5a329b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056602590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1056602590
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3238619030
Short name T156
Test name
Test status
Simulation time 53870081 ps
CPU time 0.75 seconds
Started Jul 01 10:41:36 AM PDT 24
Finished Jul 01 10:41:37 AM PDT 24
Peak memory 199632 kb
Host smart-666b1d3c-1d1b-4d93-95d0-73a61a1fc819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238619030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3238619030
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3799064567
Short name T453
Test name
Test status
Simulation time 1229879464 ps
CPU time 5.15 seconds
Started Jul 01 10:41:51 AM PDT 24
Finished Jul 01 10:41:58 AM PDT 24
Peak memory 217492 kb
Host smart-83eacce2-35f3-441a-8f64-1b6d3e01f95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799064567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3799064567
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1307939934
Short name T224
Test name
Test status
Simulation time 244399295 ps
CPU time 1.06 seconds
Started Jul 01 10:41:34 AM PDT 24
Finished Jul 01 10:41:36 AM PDT 24
Peak memory 217252 kb
Host smart-170fc7a5-a611-4b23-8b70-f729f6a2c379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307939934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1307939934
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3135074004
Short name T15
Test name
Test status
Simulation time 104242540 ps
CPU time 0.77 seconds
Started Jul 01 10:41:55 AM PDT 24
Finished Jul 01 10:41:58 AM PDT 24
Peak memory 199788 kb
Host smart-b9d03c50-9821-4cb3-acf8-40314ff07afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135074004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3135074004
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.196995663
Short name T76
Test name
Test status
Simulation time 1751000865 ps
CPU time 6.62 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:12 AM PDT 24
Peak memory 200204 kb
Host smart-9fd0d5dc-1fa5-46f2-a4a7-6ca76685b29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196995663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.196995663
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.965654626
Short name T69
Test name
Test status
Simulation time 16529782958 ps
CPU time 26.41 seconds
Started Jul 01 10:41:53 AM PDT 24
Finished Jul 01 10:42:22 AM PDT 24
Peak memory 217420 kb
Host smart-9624dd61-db6b-4b44-98ab-2eba70a95323
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965654626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.965654626
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.253572414
Short name T318
Test name
Test status
Simulation time 149822192 ps
CPU time 1.1 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:10 AM PDT 24
Peak memory 200004 kb
Host smart-54616eda-80a7-45fb-b4f3-9c0cfd3db221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253572414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.253572414
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1727970448
Short name T300
Test name
Test status
Simulation time 245774525 ps
CPU time 1.66 seconds
Started Jul 01 10:41:40 AM PDT 24
Finished Jul 01 10:41:43 AM PDT 24
Peak memory 200208 kb
Host smart-2c8544b1-0b4b-40be-a901-1281c9edccc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727970448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1727970448
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.470780225
Short name T491
Test name
Test status
Simulation time 2845963823 ps
CPU time 10.63 seconds
Started Jul 01 10:41:58 AM PDT 24
Finished Jul 01 10:42:10 AM PDT 24
Peak memory 200188 kb
Host smart-64fae5bc-7876-48cc-8bad-9b7911bb2c1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470780225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.470780225
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3896326369
Short name T351
Test name
Test status
Simulation time 345651947 ps
CPU time 2.25 seconds
Started Jul 01 10:41:35 AM PDT 24
Finished Jul 01 10:41:38 AM PDT 24
Peak memory 199940 kb
Host smart-33548869-896b-4c2d-8f9f-d4706ef6b2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896326369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3896326369
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1795966648
Short name T119
Test name
Test status
Simulation time 197606674 ps
CPU time 1.22 seconds
Started Jul 01 10:41:34 AM PDT 24
Finished Jul 01 10:41:36 AM PDT 24
Peak memory 199948 kb
Host smart-5c358920-2e56-4bdc-b471-d9a33f3359f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795966648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1795966648
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2878224693
Short name T416
Test name
Test status
Simulation time 81788570 ps
CPU time 0.84 seconds
Started Jul 01 10:42:11 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 199812 kb
Host smart-d5df1820-b32c-404b-833e-1e4fde55c0ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878224693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2878224693
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.358706088
Short name T27
Test name
Test status
Simulation time 1877177429 ps
CPU time 7.19 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:16 AM PDT 24
Peak memory 217556 kb
Host smart-ff681960-305c-4eb6-8164-5ba4f499dcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358706088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.358706088
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.954210388
Short name T194
Test name
Test status
Simulation time 244539239 ps
CPU time 1.06 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 217204 kb
Host smart-51ad6d8f-def6-4ed6-93bd-d280da15380a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954210388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.954210388
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.648044788
Short name T532
Test name
Test status
Simulation time 136525540 ps
CPU time 0.85 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:12 AM PDT 24
Peak memory 199756 kb
Host smart-981c146a-92d8-416f-9a3d-b979f36ed735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648044788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.648044788
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.270854445
Short name T259
Test name
Test status
Simulation time 1036586715 ps
CPU time 4.82 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 200212 kb
Host smart-41f4b5da-2ac9-4754-9bb9-df70fd84c9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270854445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.270854445
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.643817701
Short name T527
Test name
Test status
Simulation time 176234867 ps
CPU time 1.29 seconds
Started Jul 01 10:42:32 AM PDT 24
Finished Jul 01 10:42:34 AM PDT 24
Peak memory 200008 kb
Host smart-f4e2131e-16e6-425c-9f64-5c3c1d78b9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643817701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.643817701
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.554718968
Short name T196
Test name
Test status
Simulation time 115692422 ps
CPU time 1.13 seconds
Started Jul 01 10:42:14 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 200116 kb
Host smart-3799b2f9-e513-4feb-9fe4-327f7ee77aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554718968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.554718968
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.517460652
Short name T477
Test name
Test status
Simulation time 5722786222 ps
CPU time 21.14 seconds
Started Jul 01 10:42:13 AM PDT 24
Finished Jul 01 10:42:37 AM PDT 24
Peak memory 200284 kb
Host smart-19ef4151-681f-4edd-8bf3-3138b28afad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517460652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.517460652
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1653876173
Short name T50
Test name
Test status
Simulation time 449858070 ps
CPU time 2.54 seconds
Started Jul 01 10:42:24 AM PDT 24
Finished Jul 01 10:42:27 AM PDT 24
Peak memory 199940 kb
Host smart-ab7e5331-7326-4836-8144-144ddd167486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653876173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1653876173
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2911066161
Short name T161
Test name
Test status
Simulation time 100907669 ps
CPU time 0.96 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 199932 kb
Host smart-c8a6285d-53c2-44f4-93c4-3beed183da5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911066161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2911066161
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2003199958
Short name T340
Test name
Test status
Simulation time 64319449 ps
CPU time 0.76 seconds
Started Jul 01 10:42:14 AM PDT 24
Finished Jul 01 10:42:17 AM PDT 24
Peak memory 199728 kb
Host smart-c99df5f6-6c62-4a2a-bb00-83edd5287d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003199958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2003199958
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2102165122
Short name T473
Test name
Test status
Simulation time 1232460088 ps
CPU time 6.06 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 217428 kb
Host smart-56e08449-8e1d-4229-b2d6-9f4260a49ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102165122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2102165122
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1051987077
Short name T470
Test name
Test status
Simulation time 244940044 ps
CPU time 1.09 seconds
Started Jul 01 10:42:13 AM PDT 24
Finished Jul 01 10:42:17 AM PDT 24
Peak memory 217384 kb
Host smart-5bd67f08-ecb3-4717-9924-6980b0154811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051987077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1051987077
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3700008941
Short name T353
Test name
Test status
Simulation time 201534669 ps
CPU time 0.9 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 199732 kb
Host smart-99c110fe-1f90-43f0-a16b-31e1298d4eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700008941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3700008941
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1504218082
Short name T296
Test name
Test status
Simulation time 1326671845 ps
CPU time 5.13 seconds
Started Jul 01 10:42:28 AM PDT 24
Finished Jul 01 10:42:34 AM PDT 24
Peak memory 200296 kb
Host smart-5f09957a-e78d-43b9-a700-a91b9fbf5545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504218082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1504218082
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3162697857
Short name T132
Test name
Test status
Simulation time 108578385 ps
CPU time 1.01 seconds
Started Jul 01 10:42:33 AM PDT 24
Finished Jul 01 10:42:35 AM PDT 24
Peak memory 200008 kb
Host smart-4fdb9fd2-5bc5-4b13-a625-92c4a7575f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162697857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3162697857
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2532897118
Short name T461
Test name
Test status
Simulation time 251900366 ps
CPU time 1.52 seconds
Started Jul 01 10:42:37 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 200196 kb
Host smart-581ad02f-2a57-46a1-b75f-72163edb4b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532897118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2532897118
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1906764719
Short name T435
Test name
Test status
Simulation time 6410874831 ps
CPU time 23.55 seconds
Started Jul 01 10:42:15 AM PDT 24
Finished Jul 01 10:42:41 AM PDT 24
Peak memory 200352 kb
Host smart-e74fa1db-7b95-4b99-89cc-a3833354ea21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906764719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1906764719
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1927504243
Short name T241
Test name
Test status
Simulation time 388239357 ps
CPU time 2.18 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 199996 kb
Host smart-3301416d-9385-4174-9f68-807a9de62144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927504243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1927504243
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.858681657
Short name T415
Test name
Test status
Simulation time 98697774 ps
CPU time 0.9 seconds
Started Jul 01 10:42:11 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 200000 kb
Host smart-6a5ddc44-0488-4e67-b80d-cf875371f663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858681657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.858681657
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2710014401
Short name T173
Test name
Test status
Simulation time 56320379 ps
CPU time 0.75 seconds
Started Jul 01 10:42:15 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 199712 kb
Host smart-8e3991ee-6b47-4a09-9c63-ac7b522c7541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710014401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2710014401
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1630897544
Short name T45
Test name
Test status
Simulation time 1893794333 ps
CPU time 8 seconds
Started Jul 01 10:42:13 AM PDT 24
Finished Jul 01 10:42:24 AM PDT 24
Peak memory 221536 kb
Host smart-f330dbb7-2c89-4bb0-86d6-bca93fccd2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630897544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1630897544
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3577197764
Short name T188
Test name
Test status
Simulation time 244624961 ps
CPU time 1.16 seconds
Started Jul 01 10:42:51 AM PDT 24
Finished Jul 01 10:42:52 AM PDT 24
Peak memory 217376 kb
Host smart-a9b5d92a-7233-474a-9eda-47bb2cf654ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577197764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3577197764
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.400040733
Short name T382
Test name
Test status
Simulation time 171452271 ps
CPU time 0.85 seconds
Started Jul 01 10:42:20 AM PDT 24
Finished Jul 01 10:42:22 AM PDT 24
Peak memory 199680 kb
Host smart-30754248-c067-4a6e-9726-841ddea367d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400040733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.400040733
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1776124909
Short name T193
Test name
Test status
Simulation time 152482359 ps
CPU time 1.14 seconds
Started Jul 01 10:42:13 AM PDT 24
Finished Jul 01 10:42:17 AM PDT 24
Peak memory 199928 kb
Host smart-f1530a65-3f53-4368-aa85-5a0ee028dea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776124909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1776124909
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.4238850040
Short name T428
Test name
Test status
Simulation time 116282166 ps
CPU time 1.08 seconds
Started Jul 01 10:42:18 AM PDT 24
Finished Jul 01 10:42:20 AM PDT 24
Peak memory 200256 kb
Host smart-ccfe04aa-a09b-4ef3-a13a-3baaae577454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238850040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.4238850040
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2591525179
Short name T73
Test name
Test status
Simulation time 1277205405 ps
CPU time 6.13 seconds
Started Jul 01 10:42:27 AM PDT 24
Finished Jul 01 10:42:34 AM PDT 24
Peak memory 200120 kb
Host smart-045bfe21-0ae5-4878-82ce-07ffcd0cdb39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591525179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2591525179
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1637616083
Short name T298
Test name
Test status
Simulation time 146407356 ps
CPU time 1.86 seconds
Started Jul 01 10:42:11 AM PDT 24
Finished Jul 01 10:42:16 AM PDT 24
Peak memory 199992 kb
Host smart-54b9846c-47ad-4429-95a7-74d12aa2a812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637616083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1637616083
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3963464424
Short name T458
Test name
Test status
Simulation time 216457573 ps
CPU time 1.43 seconds
Started Jul 01 10:42:33 AM PDT 24
Finished Jul 01 10:42:35 AM PDT 24
Peak memory 199932 kb
Host smart-1c3b9e78-4451-4a03-82f1-707e0c16d4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963464424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3963464424
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2164922805
Short name T29
Test name
Test status
Simulation time 1225407613 ps
CPU time 5.83 seconds
Started Jul 01 10:42:43 AM PDT 24
Finished Jul 01 10:42:49 AM PDT 24
Peak memory 217212 kb
Host smart-deb79788-e12a-40f0-8654-01f22d59f1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164922805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2164922805
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2250548719
Short name T437
Test name
Test status
Simulation time 243488067 ps
CPU time 1.24 seconds
Started Jul 01 10:42:18 AM PDT 24
Finished Jul 01 10:42:21 AM PDT 24
Peak memory 217312 kb
Host smart-a23d2d30-5a64-498f-b484-1cc27d75f850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250548719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2250548719
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1798838439
Short name T521
Test name
Test status
Simulation time 164155068 ps
CPU time 0.89 seconds
Started Jul 01 10:42:34 AM PDT 24
Finished Jul 01 10:42:35 AM PDT 24
Peak memory 199812 kb
Host smart-2392ad91-dc4e-4332-8cde-6304df971a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798838439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1798838439
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.12993205
Short name T536
Test name
Test status
Simulation time 802169376 ps
CPU time 4.26 seconds
Started Jul 01 10:42:34 AM PDT 24
Finished Jul 01 10:42:39 AM PDT 24
Peak memory 200252 kb
Host smart-b575ff3f-91bc-4bca-a879-29da800c84bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12993205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.12993205
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3975767033
Short name T336
Test name
Test status
Simulation time 179233848 ps
CPU time 1.15 seconds
Started Jul 01 10:42:40 AM PDT 24
Finished Jul 01 10:42:43 AM PDT 24
Peak memory 200036 kb
Host smart-32eb60cd-b7a8-4c2c-992b-16242ae05e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975767033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3975767033
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1779232139
Short name T332
Test name
Test status
Simulation time 124580854 ps
CPU time 1.27 seconds
Started Jul 01 10:42:15 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 200180 kb
Host smart-5d0087e9-f331-475c-8b73-64faf3572985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779232139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1779232139
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2603236692
Short name T395
Test name
Test status
Simulation time 616240190 ps
CPU time 3.18 seconds
Started Jul 01 10:42:32 AM PDT 24
Finished Jul 01 10:42:43 AM PDT 24
Peak memory 208392 kb
Host smart-232bd29f-ba4c-4e42-bb0b-9418149a5f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603236692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2603236692
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3209258272
Short name T286
Test name
Test status
Simulation time 148318716 ps
CPU time 1.89 seconds
Started Jul 01 10:42:18 AM PDT 24
Finished Jul 01 10:42:21 AM PDT 24
Peak memory 199936 kb
Host smart-02f138bf-7112-4e7d-9e20-f414f3446be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209258272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3209258272
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1590447149
Short name T140
Test name
Test status
Simulation time 122406162 ps
CPU time 1.07 seconds
Started Jul 01 10:42:15 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 200000 kb
Host smart-e643cb87-b73c-4e54-9244-ad0e59fb6ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590447149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1590447149
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.760054272
Short name T47
Test name
Test status
Simulation time 60869898 ps
CPU time 0.72 seconds
Started Jul 01 10:42:15 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 199732 kb
Host smart-ab08346a-2159-4efc-8267-e452750490e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760054272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.760054272
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1810747339
Short name T365
Test name
Test status
Simulation time 2343017051 ps
CPU time 8.32 seconds
Started Jul 01 10:42:27 AM PDT 24
Finished Jul 01 10:42:36 AM PDT 24
Peak memory 217672 kb
Host smart-3d1641f3-6872-455d-859f-f09a04224773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810747339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1810747339
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1601704749
Short name T443
Test name
Test status
Simulation time 243815963 ps
CPU time 1.17 seconds
Started Jul 01 10:42:20 AM PDT 24
Finished Jul 01 10:42:22 AM PDT 24
Peak memory 217300 kb
Host smart-72dafdf7-e899-4ce4-acc5-e6d553e934a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601704749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1601704749
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.4202650859
Short name T386
Test name
Test status
Simulation time 136402669 ps
CPU time 0.84 seconds
Started Jul 01 10:42:20 AM PDT 24
Finished Jul 01 10:42:21 AM PDT 24
Peak memory 199832 kb
Host smart-9c05aa68-947b-49c9-906a-3a0392ac5886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202650859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.4202650859
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3355460130
Short name T277
Test name
Test status
Simulation time 1344907770 ps
CPU time 5.38 seconds
Started Jul 01 10:42:20 AM PDT 24
Finished Jul 01 10:42:26 AM PDT 24
Peak memory 200236 kb
Host smart-2744b306-8925-4f2e-a462-11ae78796ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355460130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3355460130
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1450048475
Short name T383
Test name
Test status
Simulation time 94367967 ps
CPU time 0.98 seconds
Started Jul 01 10:42:48 AM PDT 24
Finished Jul 01 10:42:50 AM PDT 24
Peak memory 199912 kb
Host smart-fe7a5485-06ad-4454-a273-68c1532ae91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450048475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1450048475
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.928127211
Short name T211
Test name
Test status
Simulation time 124955791 ps
CPU time 1.17 seconds
Started Jul 01 10:42:54 AM PDT 24
Finished Jul 01 10:42:56 AM PDT 24
Peak memory 200212 kb
Host smart-d41b1797-e3fb-4df8-9143-ca9875177fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928127211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.928127211
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2572643612
Short name T457
Test name
Test status
Simulation time 1513835267 ps
CPU time 6.84 seconds
Started Jul 01 10:42:46 AM PDT 24
Finished Jul 01 10:42:54 AM PDT 24
Peak memory 200160 kb
Host smart-8e56115e-3418-4c90-abb0-37ad2d0449ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572643612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2572643612
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.4233711968
Short name T319
Test name
Test status
Simulation time 152607926 ps
CPU time 1.9 seconds
Started Jul 01 10:42:51 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200020 kb
Host smart-8225e78a-079b-45f1-a170-88dbec357b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233711968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4233711968
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3248976138
Short name T4
Test name
Test status
Simulation time 60567138 ps
CPU time 0.73 seconds
Started Jul 01 10:42:38 AM PDT 24
Finished Jul 01 10:42:41 AM PDT 24
Peak memory 199912 kb
Host smart-896fe00a-9ace-4f7f-abc7-982b9400d72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248976138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3248976138
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.4238566106
Short name T141
Test name
Test status
Simulation time 73663308 ps
CPU time 0.79 seconds
Started Jul 01 10:42:41 AM PDT 24
Finished Jul 01 10:42:43 AM PDT 24
Peak memory 199656 kb
Host smart-c2166353-3d56-48c0-b01e-14bf2b007321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238566106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.4238566106
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.459895056
Short name T391
Test name
Test status
Simulation time 2375921294 ps
CPU time 8.85 seconds
Started Jul 01 10:42:29 AM PDT 24
Finished Jul 01 10:42:38 AM PDT 24
Peak memory 217596 kb
Host smart-10536aaf-6ebc-431a-ba47-c33a28d0b91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459895056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.459895056
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4257299019
Short name T253
Test name
Test status
Simulation time 244987731 ps
CPU time 1.14 seconds
Started Jul 01 10:42:25 AM PDT 24
Finished Jul 01 10:42:26 AM PDT 24
Peak memory 217380 kb
Host smart-b9dc25fb-998f-4a83-b24a-153cdeba37b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257299019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4257299019
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1891185165
Short name T13
Test name
Test status
Simulation time 240415163 ps
CPU time 0.95 seconds
Started Jul 01 10:42:31 AM PDT 24
Finished Jul 01 10:42:32 AM PDT 24
Peak memory 199732 kb
Host smart-a0768066-d2ca-408b-85f4-82f42d34de78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891185165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1891185165
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.814855477
Short name T506
Test name
Test status
Simulation time 1631786050 ps
CPU time 6.48 seconds
Started Jul 01 10:42:19 AM PDT 24
Finished Jul 01 10:42:26 AM PDT 24
Peak memory 200236 kb
Host smart-d389c52d-e494-4a05-83be-33a685e7de2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814855477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.814855477
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.123023501
Short name T375
Test name
Test status
Simulation time 180611876 ps
CPU time 1.23 seconds
Started Jul 01 10:42:26 AM PDT 24
Finished Jul 01 10:42:28 AM PDT 24
Peak memory 200032 kb
Host smart-87b2bef4-6e18-4e8b-96e8-d1d2447bac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123023501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.123023501
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3886080674
Short name T450
Test name
Test status
Simulation time 119828628 ps
CPU time 1.25 seconds
Started Jul 01 10:42:18 AM PDT 24
Finished Jul 01 10:42:21 AM PDT 24
Peak memory 200132 kb
Host smart-725255d8-8175-4ba6-8d5e-70a969ffb7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886080674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3886080674
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3458516584
Short name T522
Test name
Test status
Simulation time 2058432060 ps
CPU time 8.22 seconds
Started Jul 01 10:42:33 AM PDT 24
Finished Jul 01 10:42:48 AM PDT 24
Peak memory 200132 kb
Host smart-851c8e36-c619-4dee-a783-24f0cb40357c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458516584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3458516584
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.11023696
Short name T207
Test name
Test status
Simulation time 122564764 ps
CPU time 1.62 seconds
Started Jul 01 10:42:18 AM PDT 24
Finished Jul 01 10:42:20 AM PDT 24
Peak memory 200036 kb
Host smart-a18160ca-a277-4fd3-91df-4c716905855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11023696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.11023696
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.567150037
Short name T494
Test name
Test status
Simulation time 248357803 ps
CPU time 1.61 seconds
Started Jul 01 10:42:19 AM PDT 24
Finished Jul 01 10:42:21 AM PDT 24
Peak memory 200028 kb
Host smart-6dd1f441-2e39-4ec3-8e74-d14cf9774b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567150037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.567150037
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2314680450
Short name T34
Test name
Test status
Simulation time 72787246 ps
CPU time 0.82 seconds
Started Jul 01 10:42:24 AM PDT 24
Finished Jul 01 10:42:25 AM PDT 24
Peak memory 199772 kb
Host smart-95fa5389-7df0-4d53-9895-c12915d3b817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314680450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2314680450
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.568695952
Short name T388
Test name
Test status
Simulation time 1892125186 ps
CPU time 7.26 seconds
Started Jul 01 10:42:22 AM PDT 24
Finished Jul 01 10:42:29 AM PDT 24
Peak memory 217540 kb
Host smart-2fe5b07e-2315-4b07-a103-ed25a2e8935d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568695952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.568695952
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3504166788
Short name T216
Test name
Test status
Simulation time 244359902 ps
CPU time 1.12 seconds
Started Jul 01 10:42:46 AM PDT 24
Finished Jul 01 10:42:48 AM PDT 24
Peak memory 217396 kb
Host smart-05ee1298-4642-4a0d-aef5-b51f19225178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504166788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3504166788
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.4201450833
Short name T341
Test name
Test status
Simulation time 141705946 ps
CPU time 0.88 seconds
Started Jul 01 10:42:22 AM PDT 24
Finished Jul 01 10:42:23 AM PDT 24
Peak memory 199844 kb
Host smart-02c035fb-1c9c-4e53-b38e-afcbeab43051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201450833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.4201450833
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.240468181
Short name T262
Test name
Test status
Simulation time 1016997001 ps
CPU time 5.08 seconds
Started Jul 01 10:42:25 AM PDT 24
Finished Jul 01 10:42:31 AM PDT 24
Peak memory 200272 kb
Host smart-2bb6b68b-ae48-4a67-afd1-7fb510822820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240468181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.240468181
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.4078983742
Short name T245
Test name
Test status
Simulation time 102443141 ps
CPU time 1 seconds
Started Jul 01 10:42:25 AM PDT 24
Finished Jul 01 10:42:26 AM PDT 24
Peak memory 199868 kb
Host smart-954beaea-ba4a-4cbe-a403-d8e3c51635e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078983742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.4078983742
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1821801237
Short name T486
Test name
Test status
Simulation time 206038326 ps
CPU time 1.41 seconds
Started Jul 01 10:42:25 AM PDT 24
Finished Jul 01 10:42:27 AM PDT 24
Peak memory 200180 kb
Host smart-3f3d64cc-10ec-4e8d-800c-f2d7c631cddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821801237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1821801237
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.500153782
Short name T48
Test name
Test status
Simulation time 2114588030 ps
CPU time 10.22 seconds
Started Jul 01 10:42:42 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 208412 kb
Host smart-1ad12506-80c3-4f98-b132-a180ffd69c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500153782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.500153782
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2672955860
Short name T347
Test name
Test status
Simulation time 110236803 ps
CPU time 1.55 seconds
Started Jul 01 10:42:25 AM PDT 24
Finished Jul 01 10:42:27 AM PDT 24
Peak memory 199920 kb
Host smart-af3b3060-664e-4cb7-a770-09a0632f6ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672955860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2672955860
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2165816036
Short name T309
Test name
Test status
Simulation time 182775669 ps
CPU time 1.22 seconds
Started Jul 01 10:42:38 AM PDT 24
Finished Jul 01 10:42:42 AM PDT 24
Peak memory 200012 kb
Host smart-6314ec15-d5e1-4383-8730-e1df1880144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165816036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2165816036
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.934133748
Short name T380
Test name
Test status
Simulation time 68235738 ps
CPU time 0.76 seconds
Started Jul 01 10:42:47 AM PDT 24
Finished Jul 01 10:42:48 AM PDT 24
Peak memory 199736 kb
Host smart-53e70a28-3a4c-4e9d-a5b5-66d56f2cd421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934133748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.934133748
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.979772364
Short name T28
Test name
Test status
Simulation time 1891591145 ps
CPU time 7.63 seconds
Started Jul 01 10:42:28 AM PDT 24
Finished Jul 01 10:42:37 AM PDT 24
Peak memory 221556 kb
Host smart-089dd553-f503-40a9-ae7b-a91c7fb2cfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979772364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.979772364
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2839898996
Short name T376
Test name
Test status
Simulation time 244537306 ps
CPU time 1.03 seconds
Started Jul 01 10:42:29 AM PDT 24
Finished Jul 01 10:42:31 AM PDT 24
Peak memory 217364 kb
Host smart-a86eac9e-ddc4-4be4-8fe5-35f094cd2f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839898996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2839898996
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1609070825
Short name T359
Test name
Test status
Simulation time 175825159 ps
CPU time 0.82 seconds
Started Jul 01 10:42:45 AM PDT 24
Finished Jul 01 10:42:47 AM PDT 24
Peak memory 199716 kb
Host smart-f44e08a4-d1ac-43ff-b7dd-7c9b4a9287e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609070825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1609070825
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.558944207
Short name T268
Test name
Test status
Simulation time 1804049541 ps
CPU time 7.4 seconds
Started Jul 01 10:42:22 AM PDT 24
Finished Jul 01 10:42:30 AM PDT 24
Peak memory 200220 kb
Host smart-d1687eea-b3ce-4b2e-9576-13920d29b2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558944207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.558944207
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1159956563
Short name T439
Test name
Test status
Simulation time 101690330 ps
CPU time 1.03 seconds
Started Jul 01 10:42:27 AM PDT 24
Finished Jul 01 10:42:29 AM PDT 24
Peak memory 199944 kb
Host smart-58e76c39-5319-44df-bd70-7ebf6fc91424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159956563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1159956563
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.4024532871
Short name T357
Test name
Test status
Simulation time 128290368 ps
CPU time 1.27 seconds
Started Jul 01 10:42:53 AM PDT 24
Finished Jul 01 10:42:56 AM PDT 24
Peak memory 200352 kb
Host smart-3ba4c568-1986-46d8-b092-4fc174d75936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024532871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.4024532871
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.88225993
Short name T282
Test name
Test status
Simulation time 294404217 ps
CPU time 1.65 seconds
Started Jul 01 10:43:03 AM PDT 24
Finished Jul 01 10:43:09 AM PDT 24
Peak memory 200092 kb
Host smart-3f320625-0651-4ecb-8b38-9d5b6595ed61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88225993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.88225993
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3402480265
Short name T270
Test name
Test status
Simulation time 122526597 ps
CPU time 1.53 seconds
Started Jul 01 10:42:51 AM PDT 24
Finished Jul 01 10:42:54 AM PDT 24
Peak memory 200008 kb
Host smart-f8b04b4a-161e-45fd-a6c8-a5fdb9b64d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402480265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3402480265
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3051310636
Short name T338
Test name
Test status
Simulation time 84606122 ps
CPU time 0.83 seconds
Started Jul 01 10:42:22 AM PDT 24
Finished Jul 01 10:42:24 AM PDT 24
Peak memory 199944 kb
Host smart-2c914e96-5e85-4bdc-97a6-3f1a3597e255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051310636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3051310636
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3514713690
Short name T460
Test name
Test status
Simulation time 63236058 ps
CPU time 0.84 seconds
Started Jul 01 10:42:26 AM PDT 24
Finished Jul 01 10:42:27 AM PDT 24
Peak memory 199728 kb
Host smart-8e20f80a-1b8c-43d7-bfac-dfdd4251b810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514713690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3514713690
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2698544514
Short name T26
Test name
Test status
Simulation time 1213998911 ps
CPU time 5.64 seconds
Started Jul 01 10:42:49 AM PDT 24
Finished Jul 01 10:42:56 AM PDT 24
Peak memory 217624 kb
Host smart-896ad4cd-7c06-4405-a619-50143d89c6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698544514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2698544514
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1584399764
Short name T445
Test name
Test status
Simulation time 245125122 ps
CPU time 1.05 seconds
Started Jul 01 10:42:45 AM PDT 24
Finished Jul 01 10:42:47 AM PDT 24
Peak memory 217356 kb
Host smart-36d88028-b59d-474d-8099-549fb598ac20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584399764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1584399764
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3735263791
Short name T325
Test name
Test status
Simulation time 94902225 ps
CPU time 0.83 seconds
Started Jul 01 10:42:46 AM PDT 24
Finished Jul 01 10:42:48 AM PDT 24
Peak memory 199832 kb
Host smart-e446ab52-b812-47fc-9a34-13d6dde5f192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735263791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3735263791
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.210304983
Short name T280
Test name
Test status
Simulation time 1367917557 ps
CPU time 5.08 seconds
Started Jul 01 10:42:52 AM PDT 24
Finished Jul 01 10:42:58 AM PDT 24
Peak memory 200208 kb
Host smart-0388fe5c-74f1-4986-a646-e750f860cba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210304983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.210304983
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.799406221
Short name T260
Test name
Test status
Simulation time 148780588 ps
CPU time 1.11 seconds
Started Jul 01 10:42:42 AM PDT 24
Finished Jul 01 10:42:44 AM PDT 24
Peak memory 199912 kb
Host smart-e694009b-f5d1-412e-bf4b-1159d6ca233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799406221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.799406221
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3809766993
Short name T301
Test name
Test status
Simulation time 117870379 ps
CPU time 1.22 seconds
Started Jul 01 10:42:53 AM PDT 24
Finished Jul 01 10:42:55 AM PDT 24
Peak memory 200092 kb
Host smart-bf5a8ada-d1a3-49f8-8a42-45a14a72904b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809766993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3809766993
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.987853491
Short name T471
Test name
Test status
Simulation time 8323184829 ps
CPU time 31.67 seconds
Started Jul 01 10:42:59 AM PDT 24
Finished Jul 01 10:43:33 AM PDT 24
Peak memory 208476 kb
Host smart-53756a49-839b-472e-bd47-92eba59b8dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987853491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.987853491
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.430438363
Short name T210
Test name
Test status
Simulation time 319500323 ps
CPU time 2.15 seconds
Started Jul 01 10:42:30 AM PDT 24
Finished Jul 01 10:42:33 AM PDT 24
Peak memory 200004 kb
Host smart-3c678db0-9cbd-4524-a8b0-8e9ce0def0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430438363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.430438363
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3795325349
Short name T1
Test name
Test status
Simulation time 158527394 ps
CPU time 1.23 seconds
Started Jul 01 10:42:29 AM PDT 24
Finished Jul 01 10:42:31 AM PDT 24
Peak memory 200000 kb
Host smart-5744f112-4ad7-49e6-ad74-d5908895afc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795325349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3795325349
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.4242874428
Short name T314
Test name
Test status
Simulation time 61272823 ps
CPU time 0.72 seconds
Started Jul 01 10:42:59 AM PDT 24
Finished Jul 01 10:43:02 AM PDT 24
Peak memory 199780 kb
Host smart-1c8e2c06-d5cf-4618-8a39-2f09c5f1b4a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242874428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.4242874428
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.326306244
Short name T503
Test name
Test status
Simulation time 1228620816 ps
CPU time 5.62 seconds
Started Jul 01 10:42:29 AM PDT 24
Finished Jul 01 10:42:36 AM PDT 24
Peak memory 217620 kb
Host smart-d259f38c-cfae-4b08-9802-8703d0adefd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326306244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.326306244
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3265984294
Short name T33
Test name
Test status
Simulation time 243696294 ps
CPU time 1.16 seconds
Started Jul 01 10:42:28 AM PDT 24
Finished Jul 01 10:42:31 AM PDT 24
Peak memory 217392 kb
Host smart-117530a1-1ce2-4c48-b7c2-175dc7913f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265984294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3265984294
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.4118871401
Short name T418
Test name
Test status
Simulation time 103197400 ps
CPU time 0.77 seconds
Started Jul 01 10:42:46 AM PDT 24
Finished Jul 01 10:42:47 AM PDT 24
Peak memory 199716 kb
Host smart-55d77adc-6b55-443d-b6c8-8e5560c0c8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118871401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.4118871401
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2227811795
Short name T381
Test name
Test status
Simulation time 1598886027 ps
CPU time 6.34 seconds
Started Jul 01 10:42:58 AM PDT 24
Finished Jul 01 10:43:06 AM PDT 24
Peak memory 200160 kb
Host smart-b2c01c48-bb41-440d-8204-4a16922d06c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227811795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2227811795
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2574461864
Short name T408
Test name
Test status
Simulation time 176608697 ps
CPU time 1.24 seconds
Started Jul 01 10:42:30 AM PDT 24
Finished Jul 01 10:42:32 AM PDT 24
Peak memory 200020 kb
Host smart-a426e2ee-231b-4dc1-9698-74c3571fa38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574461864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2574461864
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1297069504
Short name T349
Test name
Test status
Simulation time 252290962 ps
CPU time 1.46 seconds
Started Jul 01 10:42:36 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 200132 kb
Host smart-b6771064-df91-498d-baf7-707e50759486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297069504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1297069504
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.554073498
Short name T316
Test name
Test status
Simulation time 8677970864 ps
CPU time 34.93 seconds
Started Jul 01 10:42:29 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 208520 kb
Host smart-684a973b-2722-4cce-a6fb-b0f32ce0167a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554073498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.554073498
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2748929197
Short name T143
Test name
Test status
Simulation time 397410459 ps
CPU time 2.53 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 199940 kb
Host smart-fcdad78f-10db-4d65-93a6-ddda7a00c87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748929197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2748929197
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2731140288
Short name T373
Test name
Test status
Simulation time 122696847 ps
CPU time 1.14 seconds
Started Jul 01 10:42:29 AM PDT 24
Finished Jul 01 10:42:31 AM PDT 24
Peak memory 199948 kb
Host smart-7d2035d9-985a-4d44-a795-511ec5d54c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731140288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2731140288
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1453110468
Short name T360
Test name
Test status
Simulation time 70738757 ps
CPU time 0.84 seconds
Started Jul 01 10:42:08 AM PDT 24
Finished Jul 01 10:42:11 AM PDT 24
Peak memory 200072 kb
Host smart-43a9a1a8-b26e-4bf9-96dc-de3adc5364ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453110468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1453110468
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2370264374
Short name T409
Test name
Test status
Simulation time 2358758997 ps
CPU time 9.33 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 217796 kb
Host smart-9dd2ef38-fa6d-47ca-a940-3d4114741335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370264374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2370264374
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2638838390
Short name T431
Test name
Test status
Simulation time 244164470 ps
CPU time 1.06 seconds
Started Jul 01 10:41:51 AM PDT 24
Finished Jul 01 10:41:53 AM PDT 24
Peak memory 217320 kb
Host smart-95033137-875a-4061-8db1-8c79c2a0b890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638838390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2638838390
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1858158877
Short name T419
Test name
Test status
Simulation time 170070168 ps
CPU time 0.86 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:10 AM PDT 24
Peak memory 199812 kb
Host smart-d23f1e61-dfcb-4833-afe4-698d31107cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858158877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1858158877
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3969276863
Short name T255
Test name
Test status
Simulation time 868533436 ps
CPU time 4.16 seconds
Started Jul 01 10:41:33 AM PDT 24
Finished Jul 01 10:41:38 AM PDT 24
Peak memory 200200 kb
Host smart-e16fb85d-434d-42c3-8340-8a7f0e1e7db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969276863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3969276863
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1712612830
Short name T68
Test name
Test status
Simulation time 16546755415 ps
CPU time 25.63 seconds
Started Jul 01 10:42:03 AM PDT 24
Finished Jul 01 10:42:30 AM PDT 24
Peak memory 216980 kb
Host smart-16a2668f-7b51-4596-8337-935f8b3eb8fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712612830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1712612830
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1072548059
Short name T235
Test name
Test status
Simulation time 103744761 ps
CPU time 0.94 seconds
Started Jul 01 10:41:58 AM PDT 24
Finished Jul 01 10:42:01 AM PDT 24
Peak memory 199896 kb
Host smart-62608a59-86f6-4592-9a62-b18aa981c8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072548059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1072548059
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.487657258
Short name T219
Test name
Test status
Simulation time 118743275 ps
CPU time 1.29 seconds
Started Jul 01 10:41:33 AM PDT 24
Finished Jul 01 10:41:35 AM PDT 24
Peak memory 200128 kb
Host smart-061fb50c-2d79-48d1-bf2e-75eb512ea42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487657258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.487657258
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1685062102
Short name T426
Test name
Test status
Simulation time 417694602 ps
CPU time 2.08 seconds
Started Jul 01 10:41:35 AM PDT 24
Finished Jul 01 10:41:38 AM PDT 24
Peak memory 200108 kb
Host smart-479eff4c-616c-4ba8-ac55-e93e24dd0422
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685062102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1685062102
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3577448442
Short name T462
Test name
Test status
Simulation time 383524620 ps
CPU time 2.26 seconds
Started Jul 01 10:42:06 AM PDT 24
Finished Jul 01 10:42:11 AM PDT 24
Peak memory 200032 kb
Host smart-ccbff3e3-0703-41d7-ac0d-dc3f66116107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577448442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3577448442
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.565622334
Short name T411
Test name
Test status
Simulation time 124164803 ps
CPU time 1.16 seconds
Started Jul 01 10:42:01 AM PDT 24
Finished Jul 01 10:42:03 AM PDT 24
Peak memory 199904 kb
Host smart-53d21733-84ea-409f-a07e-676543816b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565622334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.565622334
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1633722255
Short name T221
Test name
Test status
Simulation time 73244949 ps
CPU time 0.77 seconds
Started Jul 01 10:42:58 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 199812 kb
Host smart-b82f3b38-9325-4b90-84a4-8c09211ec917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633722255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1633722255
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2150222090
Short name T43
Test name
Test status
Simulation time 1886965204 ps
CPU time 6.97 seconds
Started Jul 01 10:42:35 AM PDT 24
Finished Jul 01 10:42:43 AM PDT 24
Peak memory 216704 kb
Host smart-0aadce60-59c2-464b-a220-fcebfedaf612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150222090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2150222090
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2922670138
Short name T157
Test name
Test status
Simulation time 244579758 ps
CPU time 1.04 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:04 AM PDT 24
Peak memory 217380 kb
Host smart-38c6142b-e74d-42c4-9a45-94a93e5211fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922670138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2922670138
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3732770921
Short name T420
Test name
Test status
Simulation time 116037539 ps
CPU time 0.82 seconds
Started Jul 01 10:42:31 AM PDT 24
Finished Jul 01 10:42:33 AM PDT 24
Peak memory 199816 kb
Host smart-d9feadc3-1b9e-492c-991c-0e66792799e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732770921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3732770921
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3558145551
Short name T145
Test name
Test status
Simulation time 968786153 ps
CPU time 4.96 seconds
Started Jul 01 10:42:31 AM PDT 24
Finished Jul 01 10:42:37 AM PDT 24
Peak memory 200196 kb
Host smart-8357ac5e-515b-401f-b613-23c7c977ff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558145551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3558145551
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.59854249
Short name T181
Test name
Test status
Simulation time 103273419 ps
CPU time 1.17 seconds
Started Jul 01 10:42:36 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 199996 kb
Host smart-4dee3a69-acba-4aa0-ba79-b99220c84b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59854249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.59854249
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3128993979
Short name T159
Test name
Test status
Simulation time 200945925 ps
CPU time 1.39 seconds
Started Jul 01 10:42:59 AM PDT 24
Finished Jul 01 10:43:02 AM PDT 24
Peak memory 200172 kb
Host smart-23192823-dda7-47df-8651-15cf6900878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128993979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3128993979
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2509785363
Short name T492
Test name
Test status
Simulation time 144742637 ps
CPU time 1.37 seconds
Started Jul 01 10:42:36 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 199932 kb
Host smart-84f4303c-6c24-4eeb-a83d-7baa7c74aece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509785363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2509785363
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2883995037
Short name T518
Test name
Test status
Simulation time 147523628 ps
CPU time 1.93 seconds
Started Jul 01 10:42:34 AM PDT 24
Finished Jul 01 10:42:37 AM PDT 24
Peak memory 199988 kb
Host smart-3f98850e-2e1f-4018-821a-86cab0256eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883995037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2883995037
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3821036011
Short name T8
Test name
Test status
Simulation time 239528711 ps
CPU time 1.31 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:42:59 AM PDT 24
Peak memory 199952 kb
Host smart-7fab08fd-2ca8-427d-b6ba-51dd70a1f11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821036011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3821036011
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1152396218
Short name T77
Test name
Test status
Simulation time 70855528 ps
CPU time 0.81 seconds
Started Jul 01 10:42:53 AM PDT 24
Finished Jul 01 10:42:55 AM PDT 24
Peak memory 199732 kb
Host smart-49bd1046-b37c-48cf-96c1-457d6ec3fca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152396218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1152396218
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3428656635
Short name T474
Test name
Test status
Simulation time 1232504380 ps
CPU time 5.63 seconds
Started Jul 01 10:42:50 AM PDT 24
Finished Jul 01 10:42:56 AM PDT 24
Peak memory 217568 kb
Host smart-d5235ec1-bef0-45f1-ba4c-4cde442d11c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428656635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3428656635
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2795126972
Short name T358
Test name
Test status
Simulation time 243742587 ps
CPU time 1.16 seconds
Started Jul 01 10:42:36 AM PDT 24
Finished Jul 01 10:42:39 AM PDT 24
Peak memory 217256 kb
Host smart-ae570436-0a42-4fd1-a56b-83428f9e99f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795126972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2795126972
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3086843552
Short name T525
Test name
Test status
Simulation time 77531289 ps
CPU time 0.76 seconds
Started Jul 01 10:42:35 AM PDT 24
Finished Jul 01 10:42:36 AM PDT 24
Peak memory 199740 kb
Host smart-169cfbcc-f84e-4a44-be83-9469019dd1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086843552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3086843552
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1565999878
Short name T7
Test name
Test status
Simulation time 1005737230 ps
CPU time 5.07 seconds
Started Jul 01 10:42:32 AM PDT 24
Finished Jul 01 10:42:38 AM PDT 24
Peak memory 200248 kb
Host smart-bbd368ef-d5e4-4ea0-a492-76e3b389b142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565999878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1565999878
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1634302050
Short name T505
Test name
Test status
Simulation time 178162201 ps
CPU time 1.24 seconds
Started Jul 01 10:42:35 AM PDT 24
Finished Jul 01 10:42:37 AM PDT 24
Peak memory 199996 kb
Host smart-191fadfa-24e7-4c24-b8f3-6716a8d4db2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634302050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1634302050
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2205244553
Short name T275
Test name
Test status
Simulation time 117406109 ps
CPU time 1.25 seconds
Started Jul 01 10:42:33 AM PDT 24
Finished Jul 01 10:42:34 AM PDT 24
Peak memory 200212 kb
Host smart-6bdd13d5-b264-46f9-a227-9ec0ae430b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205244553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2205244553
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1738225103
Short name T454
Test name
Test status
Simulation time 1807719317 ps
CPU time 8.61 seconds
Started Jul 01 10:42:31 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 208504 kb
Host smart-238d5a20-dac4-4dc8-8cf7-f147cfcfd9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738225103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1738225103
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3143893705
Short name T206
Test name
Test status
Simulation time 126034710 ps
CPU time 1.49 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 199980 kb
Host smart-e873dc8f-9d16-44a4-a9ae-c27bcece29d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143893705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3143893705
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.652215607
Short name T342
Test name
Test status
Simulation time 126741477 ps
CPU time 1.15 seconds
Started Jul 01 10:42:31 AM PDT 24
Finished Jul 01 10:42:33 AM PDT 24
Peak memory 200020 kb
Host smart-9335f1c2-71f7-40e1-9197-d47c1a3be851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652215607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.652215607
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.4289057568
Short name T53
Test name
Test status
Simulation time 74661233 ps
CPU time 0.86 seconds
Started Jul 01 10:42:36 AM PDT 24
Finished Jul 01 10:42:39 AM PDT 24
Peak memory 199724 kb
Host smart-15682451-a44b-45e1-a44a-960858b1f486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289057568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.4289057568
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3165533029
Short name T227
Test name
Test status
Simulation time 1219252149 ps
CPU time 6.17 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 217660 kb
Host smart-5312aeb7-c16c-4ade-99f0-eb5f9301e99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165533029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3165533029
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2786039633
Short name T182
Test name
Test status
Simulation time 243995713 ps
CPU time 1.1 seconds
Started Jul 01 10:42:35 AM PDT 24
Finished Jul 01 10:42:37 AM PDT 24
Peak memory 217368 kb
Host smart-74c3efa8-56be-4495-88a5-adcd65bb6520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786039633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2786039633
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3415044965
Short name T374
Test name
Test status
Simulation time 187489716 ps
CPU time 0.94 seconds
Started Jul 01 10:42:36 AM PDT 24
Finished Jul 01 10:42:39 AM PDT 24
Peak memory 199644 kb
Host smart-fb188a70-354d-4e6b-bf3c-1559a62b3787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415044965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3415044965
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3494471436
Short name T306
Test name
Test status
Simulation time 855780704 ps
CPU time 4.66 seconds
Started Jul 01 10:42:35 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 200276 kb
Host smart-2fe970a2-0d1b-4dd4-8502-0dee066ae18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494471436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3494471436
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.923470850
Short name T127
Test name
Test status
Simulation time 100199299 ps
CPU time 0.97 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:04 AM PDT 24
Peak memory 199984 kb
Host smart-af6359b0-e543-430b-af37-6299e60bd6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923470850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.923470850
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.421620966
Short name T452
Test name
Test status
Simulation time 193987831 ps
CPU time 1.33 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:06 AM PDT 24
Peak memory 200228 kb
Host smart-ad3847c9-b5d7-409f-8652-6f20898a0010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421620966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.421620966
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1691831496
Short name T94
Test name
Test status
Simulation time 11604335916 ps
CPU time 42.88 seconds
Started Jul 01 10:42:33 AM PDT 24
Finished Jul 01 10:43:17 AM PDT 24
Peak memory 200348 kb
Host smart-e631e49d-0e59-44fd-99dc-958049b8bb9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691831496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1691831496
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1922207228
Short name T192
Test name
Test status
Simulation time 133993446 ps
CPU time 1.66 seconds
Started Jul 01 10:42:36 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 208036 kb
Host smart-2bad57b1-6ed7-4db3-ba04-3dee1181d2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922207228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1922207228
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.709788477
Short name T324
Test name
Test status
Simulation time 74490302 ps
CPU time 0.82 seconds
Started Jul 01 10:42:37 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 200004 kb
Host smart-6e672b5a-9bf9-4f68-8a8c-b09c1473f1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709788477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.709788477
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1004049216
Short name T247
Test name
Test status
Simulation time 56241209 ps
CPU time 0.77 seconds
Started Jul 01 10:42:36 AM PDT 24
Finished Jul 01 10:42:39 AM PDT 24
Peak memory 199796 kb
Host smart-0cec6608-c31d-45ba-b01c-f552d3ac3b4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004049216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1004049216
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3966439835
Short name T327
Test name
Test status
Simulation time 2351998064 ps
CPU time 8.18 seconds
Started Jul 01 10:42:59 AM PDT 24
Finished Jul 01 10:43:09 AM PDT 24
Peak memory 217652 kb
Host smart-e6b10e06-ff83-42aa-b9d9-de050753c916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966439835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3966439835
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2446518665
Short name T148
Test name
Test status
Simulation time 250109233 ps
CPU time 1.1 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:42:59 AM PDT 24
Peak memory 217432 kb
Host smart-cbcb013f-6385-4aa4-9a12-f00c2d7b6eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446518665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2446518665
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3736970301
Short name T305
Test name
Test status
Simulation time 114605432 ps
CPU time 0.79 seconds
Started Jul 01 10:42:52 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 199692 kb
Host smart-ee4155c7-4f1e-4f34-9525-50ee5c19cf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736970301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3736970301
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1511055118
Short name T115
Test name
Test status
Simulation time 1831794949 ps
CPU time 6.73 seconds
Started Jul 01 10:42:34 AM PDT 24
Finished Jul 01 10:42:42 AM PDT 24
Peak memory 200220 kb
Host smart-ba783e76-4291-4ccd-98cf-1d63ccb93860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511055118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1511055118
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1746551472
Short name T519
Test name
Test status
Simulation time 162236105 ps
CPU time 1.25 seconds
Started Jul 01 10:42:35 AM PDT 24
Finished Jul 01 10:42:37 AM PDT 24
Peak memory 200028 kb
Host smart-3a13eab6-4800-4aea-a9a1-e2c869cd953f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746551472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1746551472
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3134783781
Short name T313
Test name
Test status
Simulation time 206453289 ps
CPU time 1.36 seconds
Started Jul 01 10:42:57 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 200200 kb
Host smart-edc79a2b-3f02-4256-87a4-8f513fab41fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134783781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3134783781
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.565501715
Short name T417
Test name
Test status
Simulation time 4750355653 ps
CPU time 16.58 seconds
Started Jul 01 10:42:36 AM PDT 24
Finished Jul 01 10:42:55 AM PDT 24
Peak memory 200316 kb
Host smart-6cecec8f-776d-41c0-a33d-40335fb32a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565501715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.565501715
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.4005644797
Short name T478
Test name
Test status
Simulation time 414065906 ps
CPU time 2.27 seconds
Started Jul 01 10:43:03 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 208232 kb
Host smart-feb517e5-9b69-4924-bafa-d3ceb4782b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005644797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.4005644797
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3515441820
Short name T164
Test name
Test status
Simulation time 109035771 ps
CPU time 0.98 seconds
Started Jul 01 10:42:52 AM PDT 24
Finished Jul 01 10:42:54 AM PDT 24
Peak memory 200008 kb
Host smart-6a1eaf4e-7bae-44e3-b800-f85c27abce3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515441820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3515441820
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2834523258
Short name T261
Test name
Test status
Simulation time 76485840 ps
CPU time 0.81 seconds
Started Jul 01 10:42:39 AM PDT 24
Finished Jul 01 10:42:42 AM PDT 24
Peak memory 199788 kb
Host smart-014d3bf1-3cfe-459c-b769-48c065575bfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834523258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2834523258
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3760559185
Short name T25
Test name
Test status
Simulation time 1895001660 ps
CPU time 7.06 seconds
Started Jul 01 10:42:38 AM PDT 24
Finished Jul 01 10:42:48 AM PDT 24
Peak memory 221460 kb
Host smart-385dda9a-6f4c-4a52-8e37-fd6608ad18af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760559185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3760559185
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.733521307
Short name T447
Test name
Test status
Simulation time 243983095 ps
CPU time 1.11 seconds
Started Jul 01 10:42:39 AM PDT 24
Finished Jul 01 10:42:42 AM PDT 24
Peak memory 217364 kb
Host smart-64ef688c-1491-4cd2-88fe-62a3cf92af05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733521307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.733521307
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1553344681
Short name T18
Test name
Test status
Simulation time 92984325 ps
CPU time 0.83 seconds
Started Jul 01 10:42:52 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 199756 kb
Host smart-a621b836-88d6-4e01-9a47-4b5842c250b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553344681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1553344681
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1605959921
Short name T476
Test name
Test status
Simulation time 1281667868 ps
CPU time 5.09 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 200272 kb
Host smart-aaf3c859-61c9-47f4-b03c-a7afed942090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605959921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1605959921
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.632590218
Short name T195
Test name
Test status
Simulation time 109075790 ps
CPU time 1.04 seconds
Started Jul 01 10:42:57 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 200032 kb
Host smart-4733b9bf-02d1-4bfd-b696-083715024f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632590218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.632590218
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2143833278
Short name T385
Test name
Test status
Simulation time 195904572 ps
CPU time 1.44 seconds
Started Jul 01 10:42:33 AM PDT 24
Finished Jul 01 10:42:35 AM PDT 24
Peak memory 200220 kb
Host smart-be280e0d-3db6-403f-8756-5e23c90b59bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143833278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2143833278
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1364135492
Short name T191
Test name
Test status
Simulation time 2029717691 ps
CPU time 9.78 seconds
Started Jul 01 10:42:37 AM PDT 24
Finished Jul 01 10:42:49 AM PDT 24
Peak memory 200532 kb
Host smart-a42d20a5-08e9-4cdc-adf2-210e7a6d7177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364135492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1364135492
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3161134484
Short name T520
Test name
Test status
Simulation time 145913952 ps
CPU time 1.86 seconds
Started Jul 01 10:42:38 AM PDT 24
Finished Jul 01 10:42:42 AM PDT 24
Peak memory 199992 kb
Host smart-315e3258-5c67-4208-b8af-e131b683d8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161134484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3161134484
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2322918728
Short name T169
Test name
Test status
Simulation time 58820530 ps
CPU time 0.73 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 199912 kb
Host smart-efe046d7-dc09-44ba-b598-bb3a41b482d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322918728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2322918728
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2297463382
Short name T168
Test name
Test status
Simulation time 63155188 ps
CPU time 0.75 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 199628 kb
Host smart-e3baca89-6ee3-4556-9ccf-4acf345b72cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297463382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2297463382
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3305102343
Short name T302
Test name
Test status
Simulation time 1231327750 ps
CPU time 5.8 seconds
Started Jul 01 10:43:03 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 217704 kb
Host smart-06fc1df7-7abf-44a2-94c0-39d7a79c0a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305102343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3305102343
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3809500706
Short name T269
Test name
Test status
Simulation time 244700128 ps
CPU time 1.04 seconds
Started Jul 01 10:42:44 AM PDT 24
Finished Jul 01 10:42:45 AM PDT 24
Peak memory 217328 kb
Host smart-b631090c-1a25-405d-ad0a-89858fa8e313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809500706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3809500706
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1062615399
Short name T293
Test name
Test status
Simulation time 87318091 ps
CPU time 0.77 seconds
Started Jul 01 10:42:39 AM PDT 24
Finished Jul 01 10:42:42 AM PDT 24
Peak memory 199792 kb
Host smart-e2b7c525-81ab-448a-8140-fdeb5f1d1852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062615399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1062615399
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3373166598
Short name T75
Test name
Test status
Simulation time 1631920501 ps
CPU time 5.86 seconds
Started Jul 01 10:42:55 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 200176 kb
Host smart-01967260-cc67-4436-8f25-37328a7021bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373166598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3373166598
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.18722
Short name T203
Test name
Test status
Simulation time 156576708 ps
CPU time 1.09 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 199992 kb
Host smart-989467e7-2d59-4f65-9809-8b1e3d04f554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.18722
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2514318536
Short name T523
Test name
Test status
Simulation time 249192933 ps
CPU time 1.54 seconds
Started Jul 01 10:42:59 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 200200 kb
Host smart-f3924682-a872-49e8-b671-3c3589f1463c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514318536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2514318536
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1701945661
Short name T467
Test name
Test status
Simulation time 9263220917 ps
CPU time 37.14 seconds
Started Jul 01 10:42:40 AM PDT 24
Finished Jul 01 10:43:19 AM PDT 24
Peak memory 200296 kb
Host smart-a926c3fc-628e-458f-9a0f-67cce5b19a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701945661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1701945661
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.510637671
Short name T490
Test name
Test status
Simulation time 148441913 ps
CPU time 1.9 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:04 AM PDT 24
Peak memory 199960 kb
Host smart-82b84eef-3b22-45f5-a0ab-d41629950571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510637671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.510637671
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2267509294
Short name T165
Test name
Test status
Simulation time 153207793 ps
CPU time 1.05 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:04 AM PDT 24
Peak memory 200032 kb
Host smart-30a1fdff-473d-4a5e-a8ea-8dd7325951d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267509294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2267509294
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1053495913
Short name T272
Test name
Test status
Simulation time 66989116 ps
CPU time 0.78 seconds
Started Jul 01 10:42:40 AM PDT 24
Finished Jul 01 10:42:43 AM PDT 24
Peak memory 199728 kb
Host smart-d09ddde8-e797-40a6-8417-76b6540e5280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053495913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1053495913
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3629613648
Short name T276
Test name
Test status
Simulation time 2361676070 ps
CPU time 8.59 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 217828 kb
Host smart-1dd2ccfd-c4b7-4b5d-a039-1805b2d3b1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629613648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3629613648
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2420960760
Short name T130
Test name
Test status
Simulation time 245329192 ps
CPU time 1.08 seconds
Started Jul 01 10:42:41 AM PDT 24
Finished Jul 01 10:42:43 AM PDT 24
Peak memory 217380 kb
Host smart-fe487a02-8643-4c21-b81d-1efe05dfe0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420960760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2420960760
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2599046328
Short name T21
Test name
Test status
Simulation time 108824038 ps
CPU time 0.77 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:04 AM PDT 24
Peak memory 199836 kb
Host smart-449dbcb1-2243-4d2c-92fb-ddd3d37610bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599046328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2599046328
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1767552782
Short name T205
Test name
Test status
Simulation time 1422003453 ps
CPU time 5.82 seconds
Started Jul 01 10:42:58 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 200244 kb
Host smart-23203d9f-fc6f-4c15-b093-985287ff0906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767552782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1767552782
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1917653455
Short name T466
Test name
Test status
Simulation time 116499757 ps
CPU time 1.04 seconds
Started Jul 01 10:42:39 AM PDT 24
Finished Jul 01 10:42:42 AM PDT 24
Peak memory 200012 kb
Host smart-b6a42a10-0dd9-4f0b-b68b-1cf1a6189b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917653455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1917653455
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.770406982
Short name T81
Test name
Test status
Simulation time 203235151 ps
CPU time 1.39 seconds
Started Jul 01 10:42:39 AM PDT 24
Finished Jul 01 10:42:43 AM PDT 24
Peak memory 200124 kb
Host smart-f84f532b-262a-4ec5-8cc7-c77a7b21da7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770406982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.770406982
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2663503295
Short name T283
Test name
Test status
Simulation time 6218828761 ps
CPU time 21.3 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:32 AM PDT 24
Peak memory 200212 kb
Host smart-0ce78799-1c7f-4f34-903a-9b8009e56d1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663503295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2663503295
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1807391599
Short name T372
Test name
Test status
Simulation time 136331927 ps
CPU time 1.83 seconds
Started Jul 01 10:42:39 AM PDT 24
Finished Jul 01 10:42:43 AM PDT 24
Peak memory 200016 kb
Host smart-c5cdd9e3-941e-41a3-a490-53e72168c391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807391599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1807391599
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2442191534
Short name T496
Test name
Test status
Simulation time 148948654 ps
CPU time 1.18 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 199980 kb
Host smart-e7c838b8-f5b0-4e29-992a-911777445839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442191534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2442191534
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.348048825
Short name T72
Test name
Test status
Simulation time 60401968 ps
CPU time 0.78 seconds
Started Jul 01 10:42:44 AM PDT 24
Finished Jul 01 10:42:46 AM PDT 24
Peak memory 199812 kb
Host smart-964a2573-5df7-4606-ba78-beb5bfcfc87f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348048825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.348048825
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3046913436
Short name T356
Test name
Test status
Simulation time 1895663234 ps
CPU time 6.61 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:16 AM PDT 24
Peak memory 216760 kb
Host smart-b38672fd-b9be-4b17-970e-c1ebc2dee2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046913436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3046913436
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1097890198
Short name T265
Test name
Test status
Simulation time 244368111 ps
CPU time 1.14 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 217380 kb
Host smart-8b04768f-9f16-46bf-8bf8-8e2f7fb09409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097890198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1097890198
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3353012204
Short name T422
Test name
Test status
Simulation time 203903784 ps
CPU time 0.94 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 199772 kb
Host smart-91d2b118-4161-446d-9bb4-5f97e9a94dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353012204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3353012204
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.895138425
Short name T436
Test name
Test status
Simulation time 1298447983 ps
CPU time 5.36 seconds
Started Jul 01 10:42:39 AM PDT 24
Finished Jul 01 10:42:46 AM PDT 24
Peak memory 200272 kb
Host smart-5a838cf5-d726-4be4-a5a9-a5d79d06ff27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895138425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.895138425
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3709534102
Short name T185
Test name
Test status
Simulation time 184532576 ps
CPU time 1.21 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 199324 kb
Host smart-4451127e-2bf1-4dea-831e-19cb0063346e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709534102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3709534102
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.859686184
Short name T180
Test name
Test status
Simulation time 252282318 ps
CPU time 1.42 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 200184 kb
Host smart-c9cba10e-8b3e-4ec4-8182-aab289d283ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859686184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.859686184
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2530668580
Short name T120
Test name
Test status
Simulation time 369498699 ps
CPU time 2.15 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 200184 kb
Host smart-66571529-cfb5-43e3-bead-d343446fe280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530668580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2530668580
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1250675196
Short name T399
Test name
Test status
Simulation time 168997168 ps
CPU time 1.22 seconds
Started Jul 01 10:42:38 AM PDT 24
Finished Jul 01 10:42:41 AM PDT 24
Peak memory 200020 kb
Host smart-25da14b3-c4ed-4b47-bfd3-6af7e31251ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250675196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1250675196
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.851941786
Short name T49
Test name
Test status
Simulation time 57948791 ps
CPU time 0.8 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 199764 kb
Host smart-9530321c-f6fe-414e-ba4f-0ce7ffa8eb47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851941786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.851941786
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1842668869
Short name T30
Test name
Test status
Simulation time 2350553951 ps
CPU time 9.61 seconds
Started Jul 01 10:42:44 AM PDT 24
Finished Jul 01 10:42:55 AM PDT 24
Peak memory 217808 kb
Host smart-03b2cf04-d77f-4d0f-a078-5650f61b31ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842668869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1842668869
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.412094110
Short name T154
Test name
Test status
Simulation time 245826683 ps
CPU time 1.05 seconds
Started Jul 01 10:42:46 AM PDT 24
Finished Jul 01 10:42:48 AM PDT 24
Peak memory 217368 kb
Host smart-aebd4850-1878-4611-86d1-62cd9969c666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412094110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.412094110
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3330493318
Short name T19
Test name
Test status
Simulation time 89779477 ps
CPU time 0.81 seconds
Started Jul 01 10:42:44 AM PDT 24
Finished Jul 01 10:42:45 AM PDT 24
Peak memory 199804 kb
Host smart-b133fbcf-2f7c-4b19-8305-b135334e85fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330493318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3330493318
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3172238048
Short name T189
Test name
Test status
Simulation time 1530994625 ps
CPU time 6.2 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:15 AM PDT 24
Peak memory 199496 kb
Host smart-005ffdcb-50cf-4439-826b-fee9ac801a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172238048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3172238048
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.267471286
Short name T222
Test name
Test status
Simulation time 161159778 ps
CPU time 1.18 seconds
Started Jul 01 10:43:41 AM PDT 24
Finished Jul 01 10:43:42 AM PDT 24
Peak memory 200044 kb
Host smart-19ca56b9-76ba-49c3-9469-214bd607c619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267471286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.267471286
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.224879822
Short name T493
Test name
Test status
Simulation time 113952993 ps
CPU time 1.15 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 200132 kb
Host smart-e22fc303-c5f1-4ae1-b855-d200650253fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224879822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.224879822
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2755534189
Short name T542
Test name
Test status
Simulation time 8920019204 ps
CPU time 30.21 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:34 AM PDT 24
Peak memory 209396 kb
Host smart-246b0549-a65b-4528-b397-19949f5322d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755534189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2755534189
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.261992752
Short name T230
Test name
Test status
Simulation time 134064847 ps
CPU time 1.59 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 208180 kb
Host smart-655e6ce4-85d4-4882-8e92-6ef3f5375ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261992752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.261992752
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3629034247
Short name T239
Test name
Test status
Simulation time 147155198 ps
CPU time 1.29 seconds
Started Jul 01 10:43:03 AM PDT 24
Finished Jul 01 10:43:09 AM PDT 24
Peak memory 199888 kb
Host smart-3e11dcaf-de0d-4952-b09f-20182174b23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629034247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3629034247
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.4276870569
Short name T432
Test name
Test status
Simulation time 82248939 ps
CPU time 0.84 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 199696 kb
Host smart-b7a2afee-3926-4153-837c-d3e2cc381b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276870569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.4276870569
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.885677936
Short name T31
Test name
Test status
Simulation time 1218462331 ps
CPU time 5.33 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:16 AM PDT 24
Peak memory 217264 kb
Host smart-3409742e-9182-4ee3-b45d-69008154d2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885677936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.885677936
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2356289775
Short name T266
Test name
Test status
Simulation time 243940421 ps
CPU time 1.13 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 217376 kb
Host smart-a62a5462-e497-4a13-bd92-59d446c32156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356289775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2356289775
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3025264710
Short name T310
Test name
Test status
Simulation time 101540156 ps
CPU time 0.82 seconds
Started Jul 01 10:42:45 AM PDT 24
Finished Jul 01 10:42:46 AM PDT 24
Peak memory 199804 kb
Host smart-7c6f30cc-f634-49da-9d7d-0a41fb8f14dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025264710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3025264710
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3385814146
Short name T9
Test name
Test status
Simulation time 877669613 ps
CPU time 4.43 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:15 AM PDT 24
Peak memory 200192 kb
Host smart-6f661767-509f-4606-b962-5f5a0b824620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385814146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3385814146
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3541746618
Short name T249
Test name
Test status
Simulation time 151446993 ps
CPU time 1.16 seconds
Started Jul 01 10:42:46 AM PDT 24
Finished Jul 01 10:42:47 AM PDT 24
Peak memory 199936 kb
Host smart-83e851c2-9d91-40a5-b9d8-2c9c757287d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541746618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3541746618
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2661799850
Short name T237
Test name
Test status
Simulation time 190291904 ps
CPU time 1.34 seconds
Started Jul 01 10:42:49 AM PDT 24
Finished Jul 01 10:42:51 AM PDT 24
Peak memory 200148 kb
Host smart-b4e43483-a72e-44fd-b3e4-10d5fd2d2b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661799850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2661799850
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1028196641
Short name T413
Test name
Test status
Simulation time 1983037097 ps
CPU time 7.22 seconds
Started Jul 01 10:42:43 AM PDT 24
Finished Jul 01 10:42:51 AM PDT 24
Peak memory 200260 kb
Host smart-b0ccf2d8-3322-436a-b9ec-70d61077f7e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028196641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1028196641
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1669873232
Short name T368
Test name
Test status
Simulation time 116827727 ps
CPU time 1.53 seconds
Started Jul 01 10:42:44 AM PDT 24
Finished Jul 01 10:42:46 AM PDT 24
Peak memory 200276 kb
Host smart-5c0ce598-0445-4a6f-931b-5d10cce8e592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669873232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1669873232
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4094387415
Short name T345
Test name
Test status
Simulation time 80813831 ps
CPU time 0.82 seconds
Started Jul 01 10:42:49 AM PDT 24
Finished Jul 01 10:42:51 AM PDT 24
Peak memory 199948 kb
Host smart-947871ed-af9f-42fe-9177-48984f2c4e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094387415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4094387415
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3250396880
Short name T271
Test name
Test status
Simulation time 88397696 ps
CPU time 0.84 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:07 AM PDT 24
Peak memory 199720 kb
Host smart-015a0e9a-d003-4758-9055-fe536f86ee63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250396880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3250396880
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1272469141
Short name T56
Test name
Test status
Simulation time 1884419120 ps
CPU time 7.11 seconds
Started Jul 01 10:41:54 AM PDT 24
Finished Jul 01 10:42:03 AM PDT 24
Peak memory 217160 kb
Host smart-d7028dc1-4946-455e-9ad0-10d17b8d011b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272469141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1272469141
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3055289231
Short name T263
Test name
Test status
Simulation time 244823170 ps
CPU time 1.19 seconds
Started Jul 01 10:42:06 AM PDT 24
Finished Jul 01 10:42:10 AM PDT 24
Peak memory 217288 kb
Host smart-e172f692-0bb3-46d7-9e60-7517dfae5dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055289231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3055289231
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3549211791
Short name T387
Test name
Test status
Simulation time 175533639 ps
CPU time 0.88 seconds
Started Jul 01 10:42:08 AM PDT 24
Finished Jul 01 10:42:12 AM PDT 24
Peak memory 199676 kb
Host smart-609b78f3-8c9a-4b8d-9aaf-2185a5a7c5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549211791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3549211791
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.999500862
Short name T449
Test name
Test status
Simulation time 1880720526 ps
CPU time 8.48 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 200188 kb
Host smart-751123b0-6807-4a12-b012-f362c3484de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999500862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.999500862
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.288015112
Short name T328
Test name
Test status
Simulation time 100158426 ps
CPU time 1.01 seconds
Started Jul 01 10:41:42 AM PDT 24
Finished Jul 01 10:41:44 AM PDT 24
Peak memory 200004 kb
Host smart-98f0ba1b-c268-47fc-bd00-9a2142edc52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288015112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.288015112
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2676231109
Short name T198
Test name
Test status
Simulation time 258614928 ps
CPU time 1.62 seconds
Started Jul 01 10:41:43 AM PDT 24
Finished Jul 01 10:41:45 AM PDT 24
Peak memory 200148 kb
Host smart-2a48f679-a2ac-4090-9ae3-35c19b380ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676231109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2676231109
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3287693974
Short name T116
Test name
Test status
Simulation time 4673201687 ps
CPU time 16.28 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:29 AM PDT 24
Peak memory 208380 kb
Host smart-84149187-f130-40d0-9b58-c5e6b954b331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287693974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3287693974
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.258172363
Short name T363
Test name
Test status
Simulation time 333029799 ps
CPU time 2.16 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:07 AM PDT 24
Peak memory 200016 kb
Host smart-cfc8a2ff-32c1-4e66-bcac-8477c885aca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258172363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.258172363
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1040515267
Short name T378
Test name
Test status
Simulation time 137617815 ps
CPU time 1.09 seconds
Started Jul 01 10:41:40 AM PDT 24
Finished Jul 01 10:41:42 AM PDT 24
Peak memory 200004 kb
Host smart-275f5b7a-08cc-447e-be59-192dc22d55f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040515267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1040515267
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1868865022
Short name T335
Test name
Test status
Simulation time 68415809 ps
CPU time 0.75 seconds
Started Jul 01 10:42:49 AM PDT 24
Finished Jul 01 10:42:51 AM PDT 24
Peak memory 199748 kb
Host smart-511652eb-16a6-4705-9da3-eb21b4b88165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868865022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1868865022
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2722847124
Short name T515
Test name
Test status
Simulation time 1230216108 ps
CPU time 5.59 seconds
Started Jul 01 10:42:48 AM PDT 24
Finished Jul 01 10:42:54 AM PDT 24
Peak memory 221468 kb
Host smart-79430dca-7b72-452f-a928-0f235cba2e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722847124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2722847124
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3857834494
Short name T214
Test name
Test status
Simulation time 244736991 ps
CPU time 1.07 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 217320 kb
Host smart-4a90994a-a3b8-4a8b-ba65-52a9957ade8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857834494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3857834494
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3150575405
Short name T2
Test name
Test status
Simulation time 152865089 ps
CPU time 0.87 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 199576 kb
Host smart-27caed82-e5fe-4250-bc7e-539c90d48c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150575405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3150575405
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3483668370
Short name T163
Test name
Test status
Simulation time 991253487 ps
CPU time 4.94 seconds
Started Jul 01 10:42:49 AM PDT 24
Finished Jul 01 10:42:55 AM PDT 24
Peak memory 200276 kb
Host smart-c7188642-912e-42b8-80c0-9a7a0912f211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483668370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3483668370
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.271353823
Short name T240
Test name
Test status
Simulation time 175451819 ps
CPU time 1.3 seconds
Started Jul 01 10:42:44 AM PDT 24
Finished Jul 01 10:42:47 AM PDT 24
Peak memory 200044 kb
Host smart-f4dd6b8c-73bb-4b23-82e7-079ac319eddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271353823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.271353823
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.928693732
Short name T312
Test name
Test status
Simulation time 251731665 ps
CPU time 1.43 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 200072 kb
Host smart-141e9cc5-635b-446f-9889-2ba60738845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928693732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.928693732
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.447075376
Short name T95
Test name
Test status
Simulation time 6277039644 ps
CPU time 21.66 seconds
Started Jul 01 10:43:03 AM PDT 24
Finished Jul 01 10:43:29 AM PDT 24
Peak memory 200208 kb
Host smart-dc75a6d8-62aa-4b67-8b3b-d146300cac87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447075376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.447075376
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1681613158
Short name T179
Test name
Test status
Simulation time 151606911 ps
CPU time 1.93 seconds
Started Jul 01 10:42:44 AM PDT 24
Finished Jul 01 10:42:47 AM PDT 24
Peak memory 199976 kb
Host smart-7fab5988-8f2b-4705-84fd-fc6144786931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681613158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1681613158
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1589177357
Short name T172
Test name
Test status
Simulation time 146074599 ps
CPU time 1.31 seconds
Started Jul 01 10:42:43 AM PDT 24
Finished Jul 01 10:42:45 AM PDT 24
Peak memory 200020 kb
Host smart-f3f7af4e-50c9-4d65-90eb-74d0f00edae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589177357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1589177357
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2748805864
Short name T183
Test name
Test status
Simulation time 62582959 ps
CPU time 0.76 seconds
Started Jul 01 10:42:47 AM PDT 24
Finished Jul 01 10:42:48 AM PDT 24
Peak memory 199800 kb
Host smart-a77b5342-8d7c-4a65-bb46-4de8617b8f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748805864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2748805864
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3090215007
Short name T398
Test name
Test status
Simulation time 1223255410 ps
CPU time 5.58 seconds
Started Jul 01 10:42:48 AM PDT 24
Finished Jul 01 10:42:54 AM PDT 24
Peak memory 217520 kb
Host smart-6433b0a4-32f8-4d34-ad37-dff16a0d2b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090215007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3090215007
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3933564385
Short name T456
Test name
Test status
Simulation time 243825615 ps
CPU time 1.14 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 217344 kb
Host smart-4bfeee94-854f-4afe-9911-485abf32803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933564385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3933564385
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.606913083
Short name T20
Test name
Test status
Simulation time 155119961 ps
CPU time 0.79 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 199644 kb
Host smart-7bf42a46-c131-4ad1-8780-93ff153ea89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606913083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.606913083
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1703789520
Short name T215
Test name
Test status
Simulation time 801614238 ps
CPU time 4.03 seconds
Started Jul 01 10:42:49 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200324 kb
Host smart-58da1bb5-5b72-4465-9c15-fb66e8a5bfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703789520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1703789520
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4276159738
Short name T502
Test name
Test status
Simulation time 141988842 ps
CPU time 1.12 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 199884 kb
Host smart-35eb1758-cbdd-4c91-bfe1-b1b73dc70e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276159738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4276159738
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1544053877
Short name T208
Test name
Test status
Simulation time 250122334 ps
CPU time 1.41 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 200084 kb
Host smart-88aec045-2b1e-42b0-8df6-37e608c087a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544053877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1544053877
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.4036162168
Short name T279
Test name
Test status
Simulation time 5774242750 ps
CPU time 25.08 seconds
Started Jul 01 10:43:34 AM PDT 24
Finished Jul 01 10:44:00 AM PDT 24
Peak memory 208500 kb
Host smart-80307aa2-fee7-4519-973f-5b4697f4991c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036162168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4036162168
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3301708652
Short name T218
Test name
Test status
Simulation time 108984161 ps
CPU time 1.41 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 199920 kb
Host smart-06a6b30f-e7d8-492f-86ff-aa8c48d58b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301708652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3301708652
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2984002811
Short name T541
Test name
Test status
Simulation time 160409888 ps
CPU time 1.31 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:06 AM PDT 24
Peak memory 200156 kb
Host smart-6d6458bf-fb57-4351-931e-832e0e91cdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984002811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2984002811
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.328760348
Short name T152
Test name
Test status
Simulation time 76954555 ps
CPU time 0.77 seconds
Started Jul 01 10:43:03 AM PDT 24
Finished Jul 01 10:43:08 AM PDT 24
Peak memory 199820 kb
Host smart-34687238-90de-4e40-b19c-ab9f706f3ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328760348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.328760348
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1637680805
Short name T32
Test name
Test status
Simulation time 1894704730 ps
CPU time 6.9 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 217672 kb
Host smart-936cd178-74f5-46ef-aeaf-ba7f11df6ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637680805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1637680805
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2283733761
Short name T331
Test name
Test status
Simulation time 243863934 ps
CPU time 1.11 seconds
Started Jul 01 10:42:54 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 217320 kb
Host smart-5f8a0806-e7ab-4fd8-a562-a39dcfabfc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283733761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2283733761
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2638787219
Short name T526
Test name
Test status
Simulation time 91872108 ps
CPU time 0.77 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 199844 kb
Host smart-eb7ffa0b-c5a4-42fc-a38f-ed6156b9f21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638787219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2638787219
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2028488571
Short name T52
Test name
Test status
Simulation time 2136251717 ps
CPU time 7.68 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:17 AM PDT 24
Peak memory 200108 kb
Host smart-316cffd8-fb37-405d-b9db-f83bfcf1a953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028488571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2028488571
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1180464497
Short name T379
Test name
Test status
Simulation time 148150028 ps
CPU time 1.21 seconds
Started Jul 01 10:42:51 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200016 kb
Host smart-7feb3b46-57ec-40f8-bf33-39e26d11445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180464497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1180464497
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1432266775
Short name T146
Test name
Test status
Simulation time 115957507 ps
CPU time 1.13 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 199460 kb
Host smart-f91ca47d-a4aa-41f7-8cdb-9e0157f50392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432266775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1432266775
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2891845175
Short name T285
Test name
Test status
Simulation time 9452319540 ps
CPU time 34.16 seconds
Started Jul 01 10:42:49 AM PDT 24
Finished Jul 01 10:43:24 AM PDT 24
Peak memory 208460 kb
Host smart-d77a95c6-2c71-4350-9d20-3e6dc200561f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891845175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2891845175
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2364185456
Short name T405
Test name
Test status
Simulation time 280121937 ps
CPU time 1.92 seconds
Started Jul 01 10:42:51 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200000 kb
Host smart-541bcc74-28f6-4734-ac76-39ae0b675cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364185456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2364185456
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.4281996629
Short name T234
Test name
Test status
Simulation time 192073811 ps
CPU time 1.26 seconds
Started Jul 01 10:42:52 AM PDT 24
Finished Jul 01 10:42:54 AM PDT 24
Peak memory 200040 kb
Host smart-9da5c598-ae11-4ddb-8c5a-8685d9dfa413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281996629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4281996629
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2871990837
Short name T170
Test name
Test status
Simulation time 53656383 ps
CPU time 0.72 seconds
Started Jul 01 10:42:51 AM PDT 24
Finished Jul 01 10:42:52 AM PDT 24
Peak memory 199776 kb
Host smart-530567b2-4a08-44dd-87cb-769f0ab70574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871990837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2871990837
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3235904661
Short name T498
Test name
Test status
Simulation time 2365255790 ps
CPU time 8.89 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:18 AM PDT 24
Peak memory 217852 kb
Host smart-0becc944-caa6-418f-8d7e-c259a5231956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235904661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3235904661
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3238568793
Short name T139
Test name
Test status
Simulation time 244366254 ps
CPU time 1.03 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:04 AM PDT 24
Peak memory 217404 kb
Host smart-a748c35f-9497-4dec-97fc-71dfec2dc734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238568793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3238568793
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3916810773
Short name T427
Test name
Test status
Simulation time 214735674 ps
CPU time 0.95 seconds
Started Jul 01 10:42:50 AM PDT 24
Finished Jul 01 10:42:51 AM PDT 24
Peak memory 199772 kb
Host smart-ca0a56cd-dba1-4a84-bc8d-7179ea5c4ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916810773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3916810773
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.4077319591
Short name T22
Test name
Test status
Simulation time 1841508462 ps
CPU time 6.61 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:15 AM PDT 24
Peak memory 200200 kb
Host smart-eca05e17-6b01-4efc-8ca3-17154c848b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077319591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.4077319591
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2033712549
Short name T322
Test name
Test status
Simulation time 106326884 ps
CPU time 1 seconds
Started Jul 01 10:42:49 AM PDT 24
Finished Jul 01 10:42:51 AM PDT 24
Peak memory 200036 kb
Host smart-ab364137-d4d1-4467-8daf-2c81a1043e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033712549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2033712549
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.763738413
Short name T129
Test name
Test status
Simulation time 126523034 ps
CPU time 1.21 seconds
Started Jul 01 10:42:55 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 200228 kb
Host smart-0687785f-6063-45a8-9e85-ba105b9360de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763738413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.763738413
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2515216115
Short name T412
Test name
Test status
Simulation time 8321808186 ps
CPU time 34.8 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:44 AM PDT 24
Peak memory 208228 kb
Host smart-0676e089-da16-4c1c-8a9a-73ced231ae1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515216115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2515216115
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.406866391
Short name T528
Test name
Test status
Simulation time 146541534 ps
CPU time 1.74 seconds
Started Jul 01 10:42:49 AM PDT 24
Finished Jul 01 10:42:51 AM PDT 24
Peak memory 208224 kb
Host smart-7b566b0c-6005-47f0-81b9-5e850297fae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406866391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.406866391
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.167426076
Short name T228
Test name
Test status
Simulation time 87870505 ps
CPU time 0.86 seconds
Started Jul 01 10:42:55 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 199936 kb
Host smart-66061321-de4f-4796-83d2-ca1b391ecdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167426076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.167426076
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3070346309
Short name T320
Test name
Test status
Simulation time 67494468 ps
CPU time 0.78 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 199716 kb
Host smart-da8ef1a9-af93-4812-b172-2ddaca9b9bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070346309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3070346309
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3173597950
Short name T274
Test name
Test status
Simulation time 1233202323 ps
CPU time 6.09 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:43:04 AM PDT 24
Peak memory 221560 kb
Host smart-e5e4860e-20b4-453f-9bf3-c092af9163c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173597950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3173597950
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.626965576
Short name T307
Test name
Test status
Simulation time 244329587 ps
CPU time 1.17 seconds
Started Jul 01 10:42:49 AM PDT 24
Finished Jul 01 10:42:51 AM PDT 24
Peak memory 217364 kb
Host smart-f2e1ef4b-a064-4f3b-9018-6aaa278d8a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626965576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.626965576
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2388528496
Short name T257
Test name
Test status
Simulation time 81273211 ps
CPU time 0.76 seconds
Started Jul 01 10:42:52 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 199832 kb
Host smart-80ea4f73-f878-43bf-93ff-3735069151eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388528496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2388528496
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1231446053
Short name T311
Test name
Test status
Simulation time 1546705883 ps
CPU time 6.54 seconds
Started Jul 01 10:42:57 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 200252 kb
Host smart-3d17c7fa-23e6-48dd-9b76-66fc21a2c2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231446053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1231446053
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.107694543
Short name T204
Test name
Test status
Simulation time 156065630 ps
CPU time 1.04 seconds
Started Jul 01 10:44:42 AM PDT 24
Finished Jul 01 10:44:44 AM PDT 24
Peak memory 199976 kb
Host smart-4ba5d434-0b34-4023-b2ae-fb2730d8f13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107694543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.107694543
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.660066674
Short name T131
Test name
Test status
Simulation time 112203395 ps
CPU time 1.19 seconds
Started Jul 01 10:44:02 AM PDT 24
Finished Jul 01 10:44:04 AM PDT 24
Peak memory 198784 kb
Host smart-1f0e9cb1-68b1-4aeb-afae-38daa4933e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660066674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.660066674
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1167159037
Short name T51
Test name
Test status
Simulation time 5552112146 ps
CPU time 23.08 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:29 AM PDT 24
Peak memory 200368 kb
Host smart-b152f2c8-16da-48c4-bb00-4ade83c8700d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167159037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1167159037
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4121218761
Short name T384
Test name
Test status
Simulation time 368535731 ps
CPU time 1.94 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 199756 kb
Host smart-fa3087c9-0160-45a4-a80f-c6907a395b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121218761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4121218761
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1059741765
Short name T343
Test name
Test status
Simulation time 81616366 ps
CPU time 0.82 seconds
Started Jul 01 10:43:07 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 199876 kb
Host smart-5dfc54d7-0fb2-45c2-9bb0-37eebcecc317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059741765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1059741765
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2746808362
Short name T291
Test name
Test status
Simulation time 71192601 ps
CPU time 0.82 seconds
Started Jul 01 10:43:17 AM PDT 24
Finished Jul 01 10:43:18 AM PDT 24
Peak memory 199824 kb
Host smart-aaa7b7e2-c798-4d27-b27d-fd1dbb043e82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746808362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2746808362
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1703225945
Short name T350
Test name
Test status
Simulation time 1892709905 ps
CPU time 7.52 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 217628 kb
Host smart-a13b0ac4-491a-446f-853c-2154442fb920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703225945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1703225945
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3394237453
Short name T366
Test name
Test status
Simulation time 243204839 ps
CPU time 1.15 seconds
Started Jul 01 10:43:03 AM PDT 24
Finished Jul 01 10:43:08 AM PDT 24
Peak memory 217408 kb
Host smart-277e12bf-2a55-464a-81c9-4efb746891cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394237453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3394237453
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.863888484
Short name T17
Test name
Test status
Simulation time 195829117 ps
CPU time 0.96 seconds
Started Jul 01 10:42:50 AM PDT 24
Finished Jul 01 10:42:52 AM PDT 24
Peak memory 199816 kb
Host smart-61a1ce63-169b-4248-ba5f-d5a4b09dbd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863888484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.863888484
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.566831205
Short name T184
Test name
Test status
Simulation time 1440076680 ps
CPU time 6.02 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 200212 kb
Host smart-66d67f01-6066-46c9-b7a0-a18b9af06b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566831205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.566831205
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3486737781
Short name T175
Test name
Test status
Simulation time 176165774 ps
CPU time 1.22 seconds
Started Jul 01 10:42:55 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 199948 kb
Host smart-d0ff0ae8-db2b-42e1-b2d1-2f22df95baed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486737781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3486737781
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2632136797
Short name T410
Test name
Test status
Simulation time 194623656 ps
CPU time 1.36 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:06 AM PDT 24
Peak memory 200016 kb
Host smart-5bc6910b-fb60-4271-9399-8d49e0347ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632136797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2632136797
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3762029483
Short name T517
Test name
Test status
Simulation time 16481795857 ps
CPU time 62.49 seconds
Started Jul 01 10:43:15 AM PDT 24
Finished Jul 01 10:44:18 AM PDT 24
Peak memory 200296 kb
Host smart-b7958fa8-8861-4394-babc-826b97e49849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762029483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3762029483
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1920625281
Short name T155
Test name
Test status
Simulation time 106443741 ps
CPU time 1.38 seconds
Started Jul 01 10:42:55 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 199716 kb
Host smart-e5b0a763-ce17-4a27-88b1-b5643a3882a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920625281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1920625281
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2457909399
Short name T250
Test name
Test status
Simulation time 191403564 ps
CPU time 1.21 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:42:58 AM PDT 24
Peak memory 199948 kb
Host smart-6a55abc5-a982-40fa-9988-4fb6c169668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457909399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2457909399
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.422724096
Short name T472
Test name
Test status
Simulation time 71613539 ps
CPU time 0.74 seconds
Started Jul 01 10:44:02 AM PDT 24
Finished Jul 01 10:44:04 AM PDT 24
Peak memory 198444 kb
Host smart-8ef1a3f2-2bd4-49cc-b131-fce5e5a6d4ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422724096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.422724096
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3037623341
Short name T225
Test name
Test status
Simulation time 1237909645 ps
CPU time 5.49 seconds
Started Jul 01 10:44:42 AM PDT 24
Finished Jul 01 10:44:48 AM PDT 24
Peak memory 221568 kb
Host smart-cda55815-cdcf-47d9-b9f2-403d811ab8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037623341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3037623341
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.108196439
Short name T400
Test name
Test status
Simulation time 244154187 ps
CPU time 1.13 seconds
Started Jul 01 10:42:50 AM PDT 24
Finished Jul 01 10:42:52 AM PDT 24
Peak memory 217364 kb
Host smart-2a889fee-3f72-470c-bd4b-dbe335f391b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108196439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.108196439
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.4241534374
Short name T535
Test name
Test status
Simulation time 223284148 ps
CPU time 0.94 seconds
Started Jul 01 10:42:55 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 199496 kb
Host smart-1d77838f-5d34-4f4e-ad4f-98ced47fd904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241534374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.4241534374
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.161283971
Short name T512
Test name
Test status
Simulation time 1653497884 ps
CPU time 6.21 seconds
Started Jul 01 10:43:13 AM PDT 24
Finished Jul 01 10:43:20 AM PDT 24
Peak memory 200136 kb
Host smart-d2ed22d3-943b-4bbd-a308-34325d6f0b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161283971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.161283971
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2291902428
Short name T142
Test name
Test status
Simulation time 166569559 ps
CPU time 1.23 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 200048 kb
Host smart-32b1c2b2-f2da-428c-b9dd-f707492ca9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291902428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2291902428
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4004336530
Short name T244
Test name
Test status
Simulation time 193041080 ps
CPU time 1.29 seconds
Started Jul 01 10:44:23 AM PDT 24
Finished Jul 01 10:44:25 AM PDT 24
Peak memory 200044 kb
Host smart-8f40a2c5-ca82-478f-8636-4514e9dc0bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004336530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4004336530
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1489572005
Short name T530
Test name
Test status
Simulation time 6268612922 ps
CPU time 27.78 seconds
Started Jul 01 10:42:57 AM PDT 24
Finished Jul 01 10:43:26 AM PDT 24
Peak memory 200316 kb
Host smart-a373f8cb-7f61-4a6b-a152-507f1a0f9dc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489572005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1489572005
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3510279273
Short name T484
Test name
Test status
Simulation time 142615644 ps
CPU time 1.76 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 199996 kb
Host smart-7be30410-33ad-4991-ac01-fbac77fdb200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510279273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3510279273
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3746833467
Short name T199
Test name
Test status
Simulation time 119539998 ps
CPU time 1.11 seconds
Started Jul 01 10:42:51 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200040 kb
Host smart-53643376-f4bd-4368-9b84-08056f9d8d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746833467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3746833467
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1640430651
Short name T468
Test name
Test status
Simulation time 69696071 ps
CPU time 0.73 seconds
Started Jul 01 10:44:46 AM PDT 24
Finished Jul 01 10:44:48 AM PDT 24
Peak memory 199752 kb
Host smart-b4e9e23f-beb7-4f67-bd71-677d47ab6d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640430651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1640430651
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2024474406
Short name T287
Test name
Test status
Simulation time 2175247740 ps
CPU time 9.06 seconds
Started Jul 01 10:43:28 AM PDT 24
Finished Jul 01 10:43:38 AM PDT 24
Peak memory 217776 kb
Host smart-b09973cf-ed40-4de2-8561-f6c48015e91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024474406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2024474406
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1193243277
Short name T39
Test name
Test status
Simulation time 243743562 ps
CPU time 1.03 seconds
Started Jul 01 10:44:35 AM PDT 24
Finished Jul 01 10:44:37 AM PDT 24
Peak memory 217260 kb
Host smart-295bb0c2-894c-4fee-b656-7766a4339a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193243277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1193243277
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3673870423
Short name T377
Test name
Test status
Simulation time 96189082 ps
CPU time 0.73 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 199640 kb
Host smart-339d0f7e-7ca0-4585-a79e-dc318146dc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673870423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3673870423
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.756333947
Short name T201
Test name
Test status
Simulation time 901255770 ps
CPU time 4.35 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:43:02 AM PDT 24
Peak memory 200264 kb
Host smart-64c7cc26-0e35-46b1-87b6-402e5ace3b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756333947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.756333947
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3600079187
Short name T254
Test name
Test status
Simulation time 112688669 ps
CPU time 1.04 seconds
Started Jul 01 10:43:03 AM PDT 24
Finished Jul 01 10:43:09 AM PDT 24
Peak memory 199952 kb
Host smart-a2fa269e-2af6-4d28-a7d0-b048a4d82d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600079187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3600079187
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3015259838
Short name T397
Test name
Test status
Simulation time 116688745 ps
CPU time 1.15 seconds
Started Jul 01 10:43:07 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 200208 kb
Host smart-6150cd0b-64ae-422d-923f-b8d35e99fef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015259838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3015259838
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3751348621
Short name T339
Test name
Test status
Simulation time 4306433600 ps
CPU time 17.89 seconds
Started Jul 01 10:44:02 AM PDT 24
Finished Jul 01 10:44:21 AM PDT 24
Peak memory 206916 kb
Host smart-3f98b772-8d18-4f3d-a9e9-46528e2f6db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751348621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3751348621
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2836424537
Short name T403
Test name
Test status
Simulation time 146106737 ps
CPU time 1.95 seconds
Started Jul 01 10:42:52 AM PDT 24
Finished Jul 01 10:42:54 AM PDT 24
Peak memory 200020 kb
Host smart-38ffa2af-c4bd-4f79-96c5-7355a020c92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836424537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2836424537
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.28881078
Short name T540
Test name
Test status
Simulation time 131623195 ps
CPU time 1.19 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:42:58 AM PDT 24
Peak memory 199924 kb
Host smart-abc0a810-8ab2-42b1-8de4-045092479458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28881078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.28881078
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2374387034
Short name T524
Test name
Test status
Simulation time 69448654 ps
CPU time 0.74 seconds
Started Jul 01 10:42:58 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 199672 kb
Host smart-2d3bef6a-73a3-46b6-9640-c92de4135a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374387034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2374387034
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.754070449
Short name T41
Test name
Test status
Simulation time 1231701078 ps
CPU time 6.62 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 221560 kb
Host smart-6abd08ee-5f27-437e-9391-fae81bdd2b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754070449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.754070449
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.247973436
Short name T243
Test name
Test status
Simulation time 244698477 ps
CPU time 1.09 seconds
Started Jul 01 10:42:57 AM PDT 24
Finished Jul 01 10:42:59 AM PDT 24
Peak memory 217388 kb
Host smart-4a527453-a07e-41a0-9ef6-e99712e1c3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247973436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.247973436
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2312886911
Short name T509
Test name
Test status
Simulation time 213122675 ps
CPU time 0.96 seconds
Started Jul 01 10:44:31 AM PDT 24
Finished Jul 01 10:44:32 AM PDT 24
Peak memory 199652 kb
Host smart-a971f370-8ee7-4774-bb07-f94fdd636bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312886911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2312886911
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3316240303
Short name T448
Test name
Test status
Simulation time 708863852 ps
CPU time 3.8 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 200224 kb
Host smart-373fbe30-c5a1-4b64-899b-f5ffc5255d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316240303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3316240303
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2839667926
Short name T352
Test name
Test status
Simulation time 156744512 ps
CPU time 1.22 seconds
Started Jul 01 10:43:24 AM PDT 24
Finished Jul 01 10:43:34 AM PDT 24
Peak memory 200040 kb
Host smart-6adc3e5b-9599-4606-b95d-9b5d89d953a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839667926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2839667926
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.373785130
Short name T150
Test name
Test status
Simulation time 117327922 ps
CPU time 1.22 seconds
Started Jul 01 10:42:51 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200168 kb
Host smart-fc5adfcb-2d9c-4e28-b9ba-3076c0492069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373785130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.373785130
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.4228390473
Short name T202
Test name
Test status
Simulation time 5122229571 ps
CPU time 18.56 seconds
Started Jul 01 10:43:32 AM PDT 24
Finished Jul 01 10:43:52 AM PDT 24
Peak memory 208540 kb
Host smart-75a1f38e-2262-4863-8cda-66a64141e62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228390473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.4228390473
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1927811094
Short name T121
Test name
Test status
Simulation time 542787781 ps
CPU time 2.94 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 199888 kb
Host smart-93f1bd93-7c3f-42ea-b785-9513a88bd4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927811094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1927811094
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.4114998671
Short name T404
Test name
Test status
Simulation time 234818241 ps
CPU time 1.39 seconds
Started Jul 01 10:42:55 AM PDT 24
Finished Jul 01 10:42:58 AM PDT 24
Peak memory 200016 kb
Host smart-17f2da1f-a30b-4239-8e1f-11758e181520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114998671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.4114998671
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2436261194
Short name T444
Test name
Test status
Simulation time 74942177 ps
CPU time 0.79 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 199732 kb
Host smart-45efb54f-71b2-4267-a25d-53034edf550b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436261194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2436261194
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1579464149
Short name T406
Test name
Test status
Simulation time 1231326535 ps
CPU time 5.65 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 217676 kb
Host smart-13cda696-34fd-4cfb-b470-198467d3d543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579464149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1579464149
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2851975489
Short name T242
Test name
Test status
Simulation time 243576991 ps
CPU time 1.08 seconds
Started Jul 01 10:42:57 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 217316 kb
Host smart-c491fbff-d074-4bbf-889a-43e1dc00b161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851975489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2851975489
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1612679188
Short name T362
Test name
Test status
Simulation time 138780766 ps
CPU time 0.85 seconds
Started Jul 01 10:43:27 AM PDT 24
Finished Jul 01 10:43:28 AM PDT 24
Peak memory 199984 kb
Host smart-a860a8bc-890d-405f-be10-7e4ab736494f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612679188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1612679188
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3647648543
Short name T329
Test name
Test status
Simulation time 1835013627 ps
CPU time 7.09 seconds
Started Jul 01 10:42:54 AM PDT 24
Finished Jul 01 10:43:02 AM PDT 24
Peak memory 200304 kb
Host smart-5d938c58-6d29-4b68-a493-9dfe6c87ee21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647648543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3647648543
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3686619067
Short name T71
Test name
Test status
Simulation time 98372367 ps
CPU time 1.05 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:06 AM PDT 24
Peak memory 199856 kb
Host smart-a195521d-c05c-41e3-b9fc-10676ef4a903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686619067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3686619067
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2348764062
Short name T231
Test name
Test status
Simulation time 111618044 ps
CPU time 1.24 seconds
Started Jul 01 10:43:07 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 200164 kb
Host smart-3338d7fb-72d6-408e-8a12-ec5936483196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348764062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2348764062
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.4223610047
Short name T147
Test name
Test status
Simulation time 2277849600 ps
CPU time 11.02 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:20 AM PDT 24
Peak memory 200404 kb
Host smart-34e19845-4ab9-4e57-ae99-14679e573954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223610047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.4223610047
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.181311191
Short name T495
Test name
Test status
Simulation time 281909104 ps
CPU time 2.07 seconds
Started Jul 01 10:42:54 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 199992 kb
Host smart-2a1bd84a-916d-42d9-975a-aa924e469b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181311191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.181311191
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1352169896
Short name T128
Test name
Test status
Simulation time 92647910 ps
CPU time 1 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:42:59 AM PDT 24
Peak memory 200000 kb
Host smart-a39d6458-34f7-49da-8720-4930518558ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352169896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1352169896
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3612303748
Short name T278
Test name
Test status
Simulation time 78160754 ps
CPU time 0.81 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:10 AM PDT 24
Peak memory 199732 kb
Host smart-cd32019c-bf2c-4190-b418-c311ca85154a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612303748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3612303748
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1602839008
Short name T57
Test name
Test status
Simulation time 2355972466 ps
CPU time 8.53 seconds
Started Jul 01 10:41:38 AM PDT 24
Finished Jul 01 10:41:47 AM PDT 24
Peak memory 221488 kb
Host smart-2c59d966-eca3-47ec-bfa3-0a8cd0bac798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602839008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1602839008
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1306719649
Short name T264
Test name
Test status
Simulation time 244207862 ps
CPU time 1.05 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:10 AM PDT 24
Peak memory 217388 kb
Host smart-5c969c00-7ce2-4e97-af5d-fa8d38cb32c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306719649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1306719649
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.21487998
Short name T429
Test name
Test status
Simulation time 112486964 ps
CPU time 0.88 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:06 AM PDT 24
Peak memory 199668 kb
Host smart-474e8c67-36c0-4991-bdf9-de60d5a7378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21487998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.21487998
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2821013943
Short name T96
Test name
Test status
Simulation time 821958999 ps
CPU time 4.33 seconds
Started Jul 01 10:41:37 AM PDT 24
Finished Jul 01 10:41:42 AM PDT 24
Peak memory 200212 kb
Host smart-55b1027f-c76f-48ce-96df-46db31c3c1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821013943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2821013943
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3166648301
Short name T136
Test name
Test status
Simulation time 95749249 ps
CPU time 1.04 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:08 AM PDT 24
Peak memory 199956 kb
Host smart-938bc3c9-2ae9-4a1c-8df9-54d4181f8901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166648301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3166648301
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3529689152
Short name T393
Test name
Test status
Simulation time 111992377 ps
CPU time 1.17 seconds
Started Jul 01 10:41:47 AM PDT 24
Finished Jul 01 10:41:49 AM PDT 24
Peak memory 200216 kb
Host smart-67491806-dd4c-469d-bd59-4576be7f634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529689152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3529689152
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3080375410
Short name T514
Test name
Test status
Simulation time 8027926382 ps
CPU time 29.33 seconds
Started Jul 01 10:41:43 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 208464 kb
Host smart-48f069aa-fe23-4c10-b64c-6103354eb5d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080375410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3080375410
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1061757106
Short name T149
Test name
Test status
Simulation time 311072092 ps
CPU time 2.06 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:08 AM PDT 24
Peak memory 208188 kb
Host smart-98daaefa-2ad8-40c8-911b-f2b61de2008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061757106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1061757106
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2579046502
Short name T396
Test name
Test status
Simulation time 200607026 ps
CPU time 1.4 seconds
Started Jul 01 10:41:41 AM PDT 24
Finished Jul 01 10:41:43 AM PDT 24
Peak memory 199944 kb
Host smart-0b62f482-d3df-4169-85ca-87818a8d625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579046502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2579046502
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.758771907
Short name T177
Test name
Test status
Simulation time 62731734 ps
CPU time 0.74 seconds
Started Jul 01 10:41:43 AM PDT 24
Finished Jul 01 10:41:44 AM PDT 24
Peak memory 199716 kb
Host smart-8ab180a5-249e-4393-9c80-24d41a866651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758771907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.758771907
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.454741891
Short name T433
Test name
Test status
Simulation time 1894550010 ps
CPU time 7.22 seconds
Started Jul 01 10:41:43 AM PDT 24
Finished Jul 01 10:41:51 AM PDT 24
Peak memory 221480 kb
Host smart-e10f626d-38b2-41f0-b476-c4dd761f29d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454741891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.454741891
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3130126705
Short name T144
Test name
Test status
Simulation time 244652637 ps
CPU time 1.05 seconds
Started Jul 01 10:41:44 AM PDT 24
Finished Jul 01 10:41:46 AM PDT 24
Peak memory 217300 kb
Host smart-1f628bc3-829b-406d-8a27-7da5539f7a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130126705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3130126705
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.4292747026
Short name T299
Test name
Test status
Simulation time 205787746 ps
CPU time 0.83 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:12 AM PDT 24
Peak memory 199680 kb
Host smart-a943eb5a-abc6-4080-8c52-528fb93ee415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292747026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.4292747026
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3842825730
Short name T317
Test name
Test status
Simulation time 1289116100 ps
CPU time 5.81 seconds
Started Jul 01 10:41:57 AM PDT 24
Finished Jul 01 10:42:05 AM PDT 24
Peak memory 200296 kb
Host smart-361a2295-065b-4b0c-9dc3-c39016c63f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842825730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3842825730
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2163179509
Short name T213
Test name
Test status
Simulation time 145488890 ps
CPU time 1.11 seconds
Started Jul 01 10:41:44 AM PDT 24
Finished Jul 01 10:41:46 AM PDT 24
Peak memory 199944 kb
Host smart-567a1319-7b89-444a-8ef4-2c8abca6efeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163179509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2163179509
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3386333976
Short name T82
Test name
Test status
Simulation time 125734925 ps
CPU time 1.21 seconds
Started Jul 01 10:41:55 AM PDT 24
Finished Jul 01 10:41:59 AM PDT 24
Peak memory 200104 kb
Host smart-a8f80289-f9f6-4a1e-8016-4b1208563c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386333976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3386333976
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1871420295
Short name T209
Test name
Test status
Simulation time 4866321876 ps
CPU time 21.94 seconds
Started Jul 01 10:41:42 AM PDT 24
Finished Jul 01 10:42:05 AM PDT 24
Peak memory 208552 kb
Host smart-99b0cc20-0784-4fb0-85a9-e16a14843a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871420295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1871420295
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4229694923
Short name T158
Test name
Test status
Simulation time 122579617 ps
CPU time 1.63 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:08 AM PDT 24
Peak memory 199944 kb
Host smart-69eb889f-e4ec-4274-a301-e9d56051e17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229694923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4229694923
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4084088034
Short name T38
Test name
Test status
Simulation time 167821334 ps
CPU time 1.41 seconds
Started Jul 01 10:41:40 AM PDT 24
Finished Jul 01 10:41:42 AM PDT 24
Peak memory 200152 kb
Host smart-81b3e1ed-a171-4b56-9f5e-44a789cd9700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084088034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4084088034
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2165654471
Short name T346
Test name
Test status
Simulation time 54113189 ps
CPU time 0.74 seconds
Started Jul 01 10:42:03 AM PDT 24
Finished Jul 01 10:42:05 AM PDT 24
Peak memory 199728 kb
Host smart-17289bcf-27b0-43b1-bb2b-b14a4ef4f679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165654471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2165654471
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.111292357
Short name T44
Test name
Test status
Simulation time 1891383712 ps
CPU time 7.64 seconds
Started Jul 01 10:42:12 AM PDT 24
Finished Jul 01 10:42:23 AM PDT 24
Peak memory 217636 kb
Host smart-e14b9636-1ad4-42d6-9709-7c723642ba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111292357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.111292357
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.806388316
Short name T438
Test name
Test status
Simulation time 244082031 ps
CPU time 1.04 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:42:07 AM PDT 24
Peak memory 217292 kb
Host smart-6aac2e31-66c2-4ecd-bae1-583553b0a5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806388316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.806388316
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1982110717
Short name T475
Test name
Test status
Simulation time 225622158 ps
CPU time 0.95 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:11 AM PDT 24
Peak memory 199676 kb
Host smart-107800f6-3502-4112-bfab-feb060f7e50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982110717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1982110717
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2527479050
Short name T267
Test name
Test status
Simulation time 916580357 ps
CPU time 4.68 seconds
Started Jul 01 10:41:45 AM PDT 24
Finished Jul 01 10:41:51 AM PDT 24
Peak memory 200164 kb
Host smart-e80a14c8-ebbf-4fd3-8b17-bcdd79110249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527479050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2527479050
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.455633009
Short name T151
Test name
Test status
Simulation time 167362550 ps
CPU time 1.22 seconds
Started Jul 01 10:42:17 AM PDT 24
Finished Jul 01 10:42:19 AM PDT 24
Peak memory 199948 kb
Host smart-69ac2324-12c8-4f38-be80-2d1162c1d43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455633009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.455633009
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2024120971
Short name T133
Test name
Test status
Simulation time 201741622 ps
CPU time 1.42 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:08 AM PDT 24
Peak memory 200152 kb
Host smart-6769c2d0-bc70-4abc-af01-28a495d729af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024120971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2024120971
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1690646158
Short name T485
Test name
Test status
Simulation time 139534451 ps
CPU time 1.82 seconds
Started Jul 01 10:42:06 AM PDT 24
Finished Jul 01 10:42:10 AM PDT 24
Peak memory 199940 kb
Host smart-5b08805b-3867-4303-bb30-ef0498524d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690646158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1690646158
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1065117234
Short name T508
Test name
Test status
Simulation time 117188829 ps
CPU time 1.14 seconds
Started Jul 01 10:42:01 AM PDT 24
Finished Jul 01 10:42:03 AM PDT 24
Peak memory 199948 kb
Host smart-e496e9da-0622-49ec-bd89-c0f17f45c8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065117234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1065117234
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1439391078
Short name T354
Test name
Test status
Simulation time 67165663 ps
CPU time 0.75 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 199728 kb
Host smart-caaebb83-6083-42bf-aee9-6ef625401bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439391078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1439391078
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.447750303
Short name T513
Test name
Test status
Simulation time 1216132542 ps
CPU time 5.79 seconds
Started Jul 01 10:41:48 AM PDT 24
Finished Jul 01 10:41:55 AM PDT 24
Peak memory 217528 kb
Host smart-5fadd324-2a8b-4a60-86b2-410064583d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447750303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.447750303
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2476820505
Short name T233
Test name
Test status
Simulation time 244108677 ps
CPU time 1.17 seconds
Started Jul 01 10:41:49 AM PDT 24
Finished Jul 01 10:41:51 AM PDT 24
Peak memory 217248 kb
Host smart-4070355d-ee87-4d6b-b2d0-9a3a5ec13b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476820505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2476820505
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2851419508
Short name T430
Test name
Test status
Simulation time 134412818 ps
CPU time 0.79 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:09 AM PDT 24
Peak memory 199836 kb
Host smart-a40db68b-4978-4916-8c79-1f30e7839020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851419508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2851419508
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3144820423
Short name T446
Test name
Test status
Simulation time 1620968126 ps
CPU time 6.05 seconds
Started Jul 01 10:41:45 AM PDT 24
Finished Jul 01 10:41:51 AM PDT 24
Peak memory 200312 kb
Host smart-c1546946-36e5-435e-b549-f12cb9687d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144820423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3144820423
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3166816261
Short name T407
Test name
Test status
Simulation time 151022277 ps
CPU time 1.04 seconds
Started Jul 01 10:42:12 AM PDT 24
Finished Jul 01 10:42:16 AM PDT 24
Peak memory 200032 kb
Host smart-f31d8a2e-304f-4b1d-aef4-23b4329ab62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166816261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3166816261
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1943409919
Short name T135
Test name
Test status
Simulation time 189540192 ps
CPU time 1.39 seconds
Started Jul 01 10:41:45 AM PDT 24
Finished Jul 01 10:41:47 AM PDT 24
Peak memory 200152 kb
Host smart-d94bb618-0a09-4a72-932c-02b0ac7e031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943409919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1943409919
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2058677588
Short name T507
Test name
Test status
Simulation time 3991232937 ps
CPU time 16.74 seconds
Started Jul 01 10:41:49 AM PDT 24
Finished Jul 01 10:42:06 AM PDT 24
Peak memory 208524 kb
Host smart-21702a7f-ad36-4f23-9fbb-3d73d76ff283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058677588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2058677588
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3786658411
Short name T423
Test name
Test status
Simulation time 110199880 ps
CPU time 1.5 seconds
Started Jul 01 10:41:48 AM PDT 24
Finished Jul 01 10:41:51 AM PDT 24
Peak memory 199916 kb
Host smart-cdd226d1-3a66-452a-8bfd-c9ca43f741d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786658411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3786658411
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1962934344
Short name T176
Test name
Test status
Simulation time 113359437 ps
CPU time 1.03 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 199932 kb
Host smart-02734ead-f6be-4ccf-bf84-cd84fd9c1ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962934344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1962934344
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1258995554
Short name T497
Test name
Test status
Simulation time 66567708 ps
CPU time 0.81 seconds
Started Jul 01 10:41:50 AM PDT 24
Finished Jul 01 10:41:52 AM PDT 24
Peak memory 199728 kb
Host smart-39698c3b-0198-4e49-9ec1-fc619bfb749e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258995554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1258995554
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.473074248
Short name T284
Test name
Test status
Simulation time 1221200363 ps
CPU time 6.28 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:16 AM PDT 24
Peak memory 216756 kb
Host smart-49909c97-4629-45fd-a93d-5f2464d3ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473074248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.473074248
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1484173246
Short name T334
Test name
Test status
Simulation time 244652692 ps
CPU time 1.03 seconds
Started Jul 01 10:41:50 AM PDT 24
Finished Jul 01 10:41:52 AM PDT 24
Peak memory 217364 kb
Host smart-e803a933-5583-4a67-976c-c32fc1c7c0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484173246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1484173246
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1103291498
Short name T16
Test name
Test status
Simulation time 90190348 ps
CPU time 0.79 seconds
Started Jul 01 10:41:50 AM PDT 24
Finished Jul 01 10:41:51 AM PDT 24
Peak memory 199756 kb
Host smart-b2d4213b-f6bd-4db8-9304-4e0023d52ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103291498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1103291498
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1672785079
Short name T333
Test name
Test status
Simulation time 2276715972 ps
CPU time 7.56 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:17 AM PDT 24
Peak memory 200264 kb
Host smart-40a7d977-f2b4-4b92-b448-ccbbad7b8059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672785079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1672785079
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.93504587
Short name T186
Test name
Test status
Simulation time 172868467 ps
CPU time 1.18 seconds
Started Jul 01 10:41:50 AM PDT 24
Finished Jul 01 10:41:52 AM PDT 24
Peak memory 199948 kb
Host smart-b60afe08-47de-4eef-9eb2-05687e96cc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93504587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.93504587
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1950414819
Short name T258
Test name
Test status
Simulation time 257113145 ps
CPU time 1.55 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:11 AM PDT 24
Peak memory 200148 kb
Host smart-9b977fd4-e2f3-408f-8979-ff1aa35dfe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950414819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1950414819
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3102082808
Short name T479
Test name
Test status
Simulation time 7560880440 ps
CPU time 26.82 seconds
Started Jul 01 10:41:48 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 208456 kb
Host smart-10d3b150-29de-46dd-924a-77fff538466e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102082808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3102082808
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.398920679
Short name T167
Test name
Test status
Simulation time 159072058 ps
CPU time 1.92 seconds
Started Jul 01 10:41:47 AM PDT 24
Finished Jul 01 10:41:50 AM PDT 24
Peak memory 199940 kb
Host smart-ddd57e4d-b46d-45d8-a985-7828cb71a570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398920679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.398920679
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3565809701
Short name T197
Test name
Test status
Simulation time 234945476 ps
CPU time 1.5 seconds
Started Jul 01 10:42:12 AM PDT 24
Finished Jul 01 10:42:17 AM PDT 24
Peak memory 200028 kb
Host smart-5a56fa55-6cde-4f89-a41c-8a8cac29106c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565809701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3565809701
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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