Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T536 /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.790209482 Jul 01 04:41:20 PM PDT 24 Jul 01 04:41:29 PM PDT 24 239375696 ps
T537 /workspace/coverage/default/10.rstmgr_por_stretcher.2312245463 Jul 01 04:41:10 PM PDT 24 Jul 01 04:41:14 PM PDT 24 90993460 ps
T538 /workspace/coverage/default/41.rstmgr_sw_rst.2288890729 Jul 01 04:42:06 PM PDT 24 Jul 01 04:42:12 PM PDT 24 144235331 ps
T539 /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3474258242 Jul 01 04:41:40 PM PDT 24 Jul 01 04:41:57 PM PDT 24 1902004600 ps
T540 /workspace/coverage/default/14.rstmgr_reset.3555688254 Jul 01 04:41:19 PM PDT 24 Jul 01 04:41:32 PM PDT 24 1643757438 ps
T58 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1354735865 Jul 01 04:28:03 PM PDT 24 Jul 01 04:28:15 PM PDT 24 472377313 ps
T59 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3972738711 Jul 01 04:27:57 PM PDT 24 Jul 01 04:28:04 PM PDT 24 123450147 ps
T60 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.394753549 Jul 01 04:28:12 PM PDT 24 Jul 01 04:28:22 PM PDT 24 123441424 ps
T63 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2291359658 Jul 01 04:27:58 PM PDT 24 Jul 01 04:28:08 PM PDT 24 287290108 ps
T61 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.134609306 Jul 01 04:28:05 PM PDT 24 Jul 01 04:28:16 PM PDT 24 88230269 ps
T62 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1049214679 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:12 PM PDT 24 69075850 ps
T64 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2149228956 Jul 01 04:28:11 PM PDT 24 Jul 01 04:28:22 PM PDT 24 262950810 ps
T70 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3734144229 Jul 01 04:27:47 PM PDT 24 Jul 01 04:27:56 PM PDT 24 191572825 ps
T82 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3128250624 Jul 01 04:28:18 PM PDT 24 Jul 01 04:28:26 PM PDT 24 171649892 ps
T104 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4022671791 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:13 PM PDT 24 207861279 ps
T83 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1685883713 Jul 01 04:28:04 PM PDT 24 Jul 01 04:28:17 PM PDT 24 770963116 ps
T128 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2238804430 Jul 01 04:28:13 PM PDT 24 Jul 01 04:28:21 PM PDT 24 88111997 ps
T84 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.901483174 Jul 01 04:27:56 PM PDT 24 Jul 01 04:28:04 PM PDT 24 153444024 ps
T88 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3342002089 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:11 PM PDT 24 787528221 ps
T85 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1287603583 Jul 01 04:28:03 PM PDT 24 Jul 01 04:28:14 PM PDT 24 243077966 ps
T105 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.340075784 Jul 01 04:28:20 PM PDT 24 Jul 01 04:28:27 PM PDT 24 151707769 ps
T106 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2002809125 Jul 01 04:28:04 PM PDT 24 Jul 01 04:28:14 PM PDT 24 58189916 ps
T86 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3570785732 Jul 01 04:28:28 PM PDT 24 Jul 01 04:28:34 PM PDT 24 115077597 ps
T87 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.373788617 Jul 01 04:28:15 PM PDT 24 Jul 01 04:28:24 PM PDT 24 526825538 ps
T89 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.150017339 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:11 PM PDT 24 477366402 ps
T541 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3775949489 Jul 01 04:28:06 PM PDT 24 Jul 01 04:28:20 PM PDT 24 799579925 ps
T107 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1879547932 Jul 01 04:28:12 PM PDT 24 Jul 01 04:28:21 PM PDT 24 68120622 ps
T90 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.374938636 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:12 PM PDT 24 276481704 ps
T91 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2839620839 Jul 01 04:28:24 PM PDT 24 Jul 01 04:28:31 PM PDT 24 136944451 ps
T108 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2333608173 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:12 PM PDT 24 57025303 ps
T109 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2170105754 Jul 01 04:28:03 PM PDT 24 Jul 01 04:28:14 PM PDT 24 152526663 ps
T110 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1446515474 Jul 01 04:28:20 PM PDT 24 Jul 01 04:28:26 PM PDT 24 72985742 ps
T542 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3247322670 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:05 PM PDT 24 494541599 ps
T543 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2562296884 Jul 01 04:28:04 PM PDT 24 Jul 01 04:28:15 PM PDT 24 105066654 ps
T544 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4102276214 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:18 PM PDT 24 72704120 ps
T545 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.515976456 Jul 01 04:28:37 PM PDT 24 Jul 01 04:28:44 PM PDT 24 69068287 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.757139462 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:10 PM PDT 24 84149501 ps
T547 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2756877217 Jul 01 04:28:27 PM PDT 24 Jul 01 04:28:33 PM PDT 24 88438776 ps
T548 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1981653036 Jul 01 04:28:15 PM PDT 24 Jul 01 04:28:23 PM PDT 24 86743477 ps
T111 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1766017975 Jul 01 04:28:09 PM PDT 24 Jul 01 04:28:22 PM PDT 24 933077934 ps
T549 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.311186993 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:12 PM PDT 24 130024007 ps
T550 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3858784219 Jul 01 04:27:53 PM PDT 24 Jul 01 04:28:00 PM PDT 24 142116121 ps
T551 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2740190635 Jul 01 04:28:11 PM PDT 24 Jul 01 04:28:21 PM PDT 24 177122042 ps
T118 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1035405947 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:13 PM PDT 24 307959497 ps
T552 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2414724633 Jul 01 04:27:59 PM PDT 24 Jul 01 04:28:16 PM PDT 24 2271594105 ps
T553 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.249360366 Jul 01 04:28:12 PM PDT 24 Jul 01 04:28:22 PM PDT 24 153488668 ps
T554 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1098107634 Jul 01 04:28:43 PM PDT 24 Jul 01 04:28:54 PM PDT 24 68066345 ps
T555 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3530198902 Jul 01 04:27:59 PM PDT 24 Jul 01 04:28:08 PM PDT 24 57165554 ps
T556 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3498283048 Jul 01 04:28:03 PM PDT 24 Jul 01 04:28:14 PM PDT 24 210867723 ps
T114 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1224331934 Jul 01 04:28:27 PM PDT 24 Jul 01 04:28:35 PM PDT 24 775986774 ps
T557 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2948886622 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:11 PM PDT 24 93273842 ps
T558 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.68348796 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:12 PM PDT 24 59856660 ps
T559 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4080870042 Jul 01 04:28:06 PM PDT 24 Jul 01 04:28:19 PM PDT 24 191273995 ps
T560 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3085384555 Jul 01 04:28:03 PM PDT 24 Jul 01 04:28:19 PM PDT 24 486571199 ps
T561 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3729282652 Jul 01 04:28:17 PM PDT 24 Jul 01 04:28:24 PM PDT 24 73696166 ps
T562 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1081594698 Jul 01 04:28:04 PM PDT 24 Jul 01 04:28:16 PM PDT 24 178439970 ps
T117 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.680465785 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:11 PM PDT 24 464834650 ps
T563 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.766947418 Jul 01 04:28:20 PM PDT 24 Jul 01 04:28:27 PM PDT 24 98994178 ps
T564 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.872121069 Jul 01 04:28:10 PM PDT 24 Jul 01 04:28:22 PM PDT 24 361403060 ps
T565 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2435978361 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:11 PM PDT 24 132490447 ps
T566 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2449515146 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:13 PM PDT 24 133819187 ps
T115 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3245924400 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:14 PM PDT 24 931880941 ps
T567 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.105091543 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:10 PM PDT 24 139662004 ps
T568 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3190232676 Jul 01 04:28:27 PM PDT 24 Jul 01 04:28:32 PM PDT 24 195531231 ps
T569 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4154654144 Jul 01 04:28:12 PM PDT 24 Jul 01 04:28:21 PM PDT 24 93818749 ps
T570 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.318948413 Jul 01 04:27:58 PM PDT 24 Jul 01 04:28:08 PM PDT 24 266984078 ps
T571 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1713281210 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:18 PM PDT 24 703026465 ps
T127 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1712935123 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:14 PM PDT 24 950411299 ps
T572 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.379545054 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:12 PM PDT 24 107823769 ps
T573 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2107498036 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:11 PM PDT 24 347828394 ps
T574 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3681704228 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:12 PM PDT 24 71570030 ps
T112 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.725443808 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:14 PM PDT 24 892201685 ps
T575 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.827301212 Jul 01 04:28:28 PM PDT 24 Jul 01 04:28:34 PM PDT 24 117646739 ps
T113 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1406740049 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:11 PM PDT 24 403857935 ps
T576 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.474064102 Jul 01 04:27:56 PM PDT 24 Jul 01 04:28:04 PM PDT 24 158365912 ps
T577 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1717828440 Jul 01 04:28:05 PM PDT 24 Jul 01 04:28:15 PM PDT 24 81912153 ps
T578 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2301373344 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:12 PM PDT 24 112495441 ps
T116 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1340702379 Jul 01 04:28:04 PM PDT 24 Jul 01 04:28:15 PM PDT 24 514906333 ps
T579 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1984889187 Jul 01 04:28:03 PM PDT 24 Jul 01 04:28:14 PM PDT 24 70580439 ps
T580 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1793084113 Jul 01 04:28:34 PM PDT 24 Jul 01 04:28:43 PM PDT 24 966743936 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3034530539 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:14 PM PDT 24 449250616 ps
T582 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2451670195 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:12 PM PDT 24 927875257 ps
T583 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.42853536 Jul 01 04:27:58 PM PDT 24 Jul 01 04:28:08 PM PDT 24 495126007 ps
T584 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.520320650 Jul 01 04:28:29 PM PDT 24 Jul 01 04:28:42 PM PDT 24 482319614 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4205423122 Jul 01 04:28:04 PM PDT 24 Jul 01 04:28:16 PM PDT 24 160398498 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.699630224 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:12 PM PDT 24 142689683 ps
T587 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2170112466 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:12 PM PDT 24 144954095 ps
T588 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3198033542 Jul 01 04:28:19 PM PDT 24 Jul 01 04:28:31 PM PDT 24 79784567 ps
T589 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3196203289 Jul 01 04:27:56 PM PDT 24 Jul 01 04:28:07 PM PDT 24 813618401 ps
T590 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.34637741 Jul 01 04:28:35 PM PDT 24 Jul 01 04:28:45 PM PDT 24 580583266 ps
T591 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2973066851 Jul 01 04:28:15 PM PDT 24 Jul 01 04:28:25 PM PDT 24 158247314 ps
T592 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2015698105 Jul 01 04:28:09 PM PDT 24 Jul 01 04:28:20 PM PDT 24 132740015 ps
T593 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3074556631 Jul 01 04:28:12 PM PDT 24 Jul 01 04:28:22 PM PDT 24 88040215 ps
T594 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.506782417 Jul 01 04:28:28 PM PDT 24 Jul 01 04:28:35 PM PDT 24 884366681 ps
T595 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.635578840 Jul 01 04:28:27 PM PDT 24 Jul 01 04:28:32 PM PDT 24 70915682 ps
T596 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1397419562 Jul 01 04:27:57 PM PDT 24 Jul 01 04:28:05 PM PDT 24 222993897 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3844311530 Jul 01 04:27:58 PM PDT 24 Jul 01 04:28:07 PM PDT 24 154497587 ps
T598 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.567872351 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:01 PM PDT 24 199440322 ps
T599 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1469256776 Jul 01 04:28:03 PM PDT 24 Jul 01 04:28:13 PM PDT 24 120369888 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2550606528 Jul 01 04:28:25 PM PDT 24 Jul 01 04:28:30 PM PDT 24 124913741 ps
T601 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2707458506 Jul 01 04:28:04 PM PDT 24 Jul 01 04:28:15 PM PDT 24 114745042 ps
T602 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3309948363 Jul 01 04:28:27 PM PDT 24 Jul 01 04:28:33 PM PDT 24 190647635 ps
T603 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3800308002 Jul 01 04:27:51 PM PDT 24 Jul 01 04:27:59 PM PDT 24 105446905 ps
T604 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2521783840 Jul 01 04:28:03 PM PDT 24 Jul 01 04:28:13 PM PDT 24 55449676 ps
T605 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2552634599 Jul 01 04:28:23 PM PDT 24 Jul 01 04:28:31 PM PDT 24 186704190 ps
T606 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4025755791 Jul 01 04:28:05 PM PDT 24 Jul 01 04:28:16 PM PDT 24 129622945 ps
T607 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.323863229 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:12 PM PDT 24 212531904 ps
T608 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2146063878 Jul 01 04:27:53 PM PDT 24 Jul 01 04:27:59 PM PDT 24 98533727 ps
T609 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2118899793 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:17 PM PDT 24 1545243439 ps
T610 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.492867045 Jul 01 04:28:18 PM PDT 24 Jul 01 04:28:25 PM PDT 24 223458006 ps
T611 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2032690392 Jul 01 04:28:19 PM PDT 24 Jul 01 04:28:25 PM PDT 24 92497134 ps
T612 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3033452194 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:11 PM PDT 24 146359423 ps
T613 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3681596400 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:12 PM PDT 24 113948453 ps
T614 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1129553352 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:13 PM PDT 24 125537391 ps
T615 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2415542706 Jul 01 04:28:05 PM PDT 24 Jul 01 04:28:16 PM PDT 24 82248801 ps
T616 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3489979773 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:12 PM PDT 24 128539173 ps
T617 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2549064429 Jul 01 04:28:31 PM PDT 24 Jul 01 04:28:37 PM PDT 24 131692268 ps
T618 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2406760487 Jul 01 04:28:07 PM PDT 24 Jul 01 04:28:21 PM PDT 24 451947670 ps
T619 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1908013540 Jul 01 04:28:27 PM PDT 24 Jul 01 04:28:33 PM PDT 24 176407761 ps
T620 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.659665392 Jul 01 04:28:15 PM PDT 24 Jul 01 04:28:25 PM PDT 24 919030508 ps

Test location /workspace/coverage/default/23.rstmgr_smoke.3964446637
Short name T8
Test name
Test status
Simulation time 116201830 ps
CPU time 1.14 seconds
Started Jul 01 04:41:29 PM PDT 24
Finished Jul 01 04:41:40 PM PDT 24
Peak memory 200220 kb
Host smart-5d776f49-4ab9-49f8-99ef-ba147b3f0843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964446637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3964446637
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1405566694
Short name T12
Test name
Test status
Simulation time 10975195932 ps
CPU time 37.6 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:43:17 PM PDT 24
Peak memory 208544 kb
Host smart-3a8d66c8-c616-4eaa-ae4c-fb34220ff888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405566694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1405566694
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1053673748
Short name T37
Test name
Test status
Simulation time 1870669362 ps
CPU time 6.91 seconds
Started Jul 01 04:41:58 PM PDT 24
Finished Jul 01 04:42:08 PM PDT 24
Peak memory 221628 kb
Host smart-04243d06-d39c-4c1e-8ac6-8764941750be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053673748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1053673748
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.394753549
Short name T60
Test name
Test status
Simulation time 123441424 ps
CPU time 1.28 seconds
Started Jul 01 04:28:12 PM PDT 24
Finished Jul 01 04:28:22 PM PDT 24
Peak memory 208320 kb
Host smart-3fe472c7-c4cd-460f-b9e5-32efe29b6984
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394753549 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.394753549
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3529132863
Short name T47
Test name
Test status
Simulation time 340989915 ps
CPU time 1.96 seconds
Started Jul 01 04:41:27 PM PDT 24
Finished Jul 01 04:41:38 PM PDT 24
Peak memory 200264 kb
Host smart-0eb928cf-ade5-4d83-9b43-80fa92faa543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529132863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3529132863
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.579257535
Short name T66
Test name
Test status
Simulation time 16619862312 ps
CPU time 24.45 seconds
Started Jul 01 04:40:55 PM PDT 24
Finished Jul 01 04:41:23 PM PDT 24
Peak memory 217068 kb
Host smart-0da5ba07-bf33-4317-bd5c-2b21b7c96438
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579257535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.579257535
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1685883713
Short name T83
Test name
Test status
Simulation time 770963116 ps
CPU time 2.9 seconds
Started Jul 01 04:28:04 PM PDT 24
Finished Jul 01 04:28:17 PM PDT 24
Peak memory 200252 kb
Host smart-67665880-71b6-4805-8f10-e3fe5875c83e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685883713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1685883713
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2797940396
Short name T2
Test name
Test status
Simulation time 84074522 ps
CPU time 0.82 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:25 PM PDT 24
Peak memory 199952 kb
Host smart-4be211fe-266b-4615-b19e-590a422efc6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797940396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2797940396
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2180869418
Short name T34
Test name
Test status
Simulation time 1880383351 ps
CPU time 7.48 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:07 PM PDT 24
Peak memory 217396 kb
Host smart-b5b5a748-42aa-4822-a498-9e6c17dd1955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180869418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2180869418
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1672643286
Short name T69
Test name
Test status
Simulation time 95373081 ps
CPU time 0.98 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:40:56 PM PDT 24
Peak memory 200108 kb
Host smart-7dbf109b-1f0d-49b0-bf2a-5c73bdcbff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672643286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1672643286
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1598685727
Short name T100
Test name
Test status
Simulation time 14014975891 ps
CPU time 49.35 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:42:39 PM PDT 24
Peak memory 208320 kb
Host smart-30a7a80b-1bc1-42e7-b103-83e46833bd8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598685727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1598685727
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3570785732
Short name T86
Test name
Test status
Simulation time 115077597 ps
CPU time 1.44 seconds
Started Jul 01 04:28:28 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 208352 kb
Host smart-7ff4af96-c304-45c4-b875-5330b05b2f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570785732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3570785732
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1004953310
Short name T175
Test name
Test status
Simulation time 296249327 ps
CPU time 1.51 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:28 PM PDT 24
Peak memory 200116 kb
Host smart-d745aff5-d724-432a-86a7-b76d0d349946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004953310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1004953310
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.725443808
Short name T112
Test name
Test status
Simulation time 892201685 ps
CPU time 3.46 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 200184 kb
Host smart-5eef3562-a9a3-47f5-809a-bef437b30d88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725443808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
725443808
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3298183342
Short name T53
Test name
Test status
Simulation time 2179715712 ps
CPU time 9.38 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:39 PM PDT 24
Peak memory 217544 kb
Host smart-d7848162-ac8b-419a-b613-000dee046dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298183342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3298183342
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2192387416
Short name T54
Test name
Test status
Simulation time 1220255331 ps
CPU time 6.01 seconds
Started Jul 01 04:42:23 PM PDT 24
Finished Jul 01 04:42:39 PM PDT 24
Peak memory 221672 kb
Host smart-00016fda-facb-4041-b2b7-46f2982c58bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192387416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2192387416
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1879547932
Short name T107
Test name
Test status
Simulation time 68120622 ps
CPU time 0.78 seconds
Started Jul 01 04:28:12 PM PDT 24
Finished Jul 01 04:28:21 PM PDT 24
Peak memory 199964 kb
Host smart-4b49a2ec-ef3f-49b8-9357-fa9f284da77c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879547932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1879547932
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1978792367
Short name T17
Test name
Test status
Simulation time 179824391 ps
CPU time 0.87 seconds
Started Jul 01 04:41:08 PM PDT 24
Finished Jul 01 04:41:11 PM PDT 24
Peak memory 199824 kb
Host smart-be4426a7-5af8-4063-bfd2-aec1edaa53bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978792367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1978792367
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1376913401
Short name T103
Test name
Test status
Simulation time 3452800289 ps
CPU time 15.49 seconds
Started Jul 01 04:41:24 PM PDT 24
Finished Jul 01 04:41:48 PM PDT 24
Peak memory 200348 kb
Host smart-7b63c6d8-528b-463b-bd0f-7b38f006041f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376913401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1376913401
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.680465785
Short name T117
Test name
Test status
Simulation time 464834650 ps
CPU time 1.92 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:11 PM PDT 24
Peak memory 200348 kb
Host smart-e12fc27e-95eb-43ea-9fea-6402859e2af4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680465785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
680465785
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.105091543
Short name T567
Test name
Test status
Simulation time 139662004 ps
CPU time 1.26 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:10 PM PDT 24
Peak memory 200368 kb
Host smart-2e31d843-93cb-4647-a87e-af5227702ab2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105091543 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.105091543
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3245924400
Short name T115
Test name
Test status
Simulation time 931880941 ps
CPU time 3.11 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 200272 kb
Host smart-b5db8ae0-206b-4b93-b7b6-d5688d3347da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245924400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3245924400
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2349596993
Short name T238
Test name
Test status
Simulation time 121108568 ps
CPU time 1.2 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:31 PM PDT 24
Peak memory 200196 kb
Host smart-9fd1037a-8238-4d08-93ff-5cb8cd788d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349596993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2349596993
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2107498036
Short name T573
Test name
Test status
Simulation time 347828394 ps
CPU time 2.47 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:11 PM PDT 24
Peak memory 200176 kb
Host smart-0f546cec-9577-46f5-9b3f-3b8895debdbb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107498036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
107498036
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2414724633
Short name T552
Test name
Test status
Simulation time 2271594105 ps
CPU time 9.36 seconds
Started Jul 01 04:27:59 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 200208 kb
Host smart-d2aa6563-74fa-4173-afe6-23fe80f0806d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414724633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
414724633
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2146063878
Short name T608
Test name
Test status
Simulation time 98533727 ps
CPU time 0.84 seconds
Started Jul 01 04:27:53 PM PDT 24
Finished Jul 01 04:27:59 PM PDT 24
Peak memory 199944 kb
Host smart-b7a46582-e8fb-41a1-bdfb-193b5ee667e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146063878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
146063878
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3734144229
Short name T70
Test name
Test status
Simulation time 191572825 ps
CPU time 1.19 seconds
Started Jul 01 04:27:47 PM PDT 24
Finished Jul 01 04:27:56 PM PDT 24
Peak memory 200072 kb
Host smart-65c60696-1feb-47d2-a691-77866686c86e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734144229 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3734144229
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3530198902
Short name T555
Test name
Test status
Simulation time 57165554 ps
CPU time 0.74 seconds
Started Jul 01 04:27:59 PM PDT 24
Finished Jul 01 04:28:08 PM PDT 24
Peak memory 200032 kb
Host smart-629956d4-fab1-453e-a9b5-c1624b56edbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530198902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3530198902
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3858784219
Short name T550
Test name
Test status
Simulation time 142116121 ps
CPU time 1.14 seconds
Started Jul 01 04:27:53 PM PDT 24
Finished Jul 01 04:28:00 PM PDT 24
Peak memory 200084 kb
Host smart-936340ff-f2d6-4976-aa00-b1e504fda25d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858784219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3858784219
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3800308002
Short name T603
Test name
Test status
Simulation time 105446905 ps
CPU time 1.54 seconds
Started Jul 01 04:27:51 PM PDT 24
Finished Jul 01 04:27:59 PM PDT 24
Peak memory 216492 kb
Host smart-c99f2aac-ecfd-4d34-bd55-fd67ab6c27ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800308002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3800308002
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4205423122
Short name T585
Test name
Test status
Simulation time 160398498 ps
CPU time 2.01 seconds
Started Jul 01 04:28:04 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 200200 kb
Host smart-a25316a8-4c8e-4827-8f3d-491a5dcade9e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205423122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.4
205423122
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3196203289
Short name T589
Test name
Test status
Simulation time 813618401 ps
CPU time 4.71 seconds
Started Jul 01 04:27:56 PM PDT 24
Finished Jul 01 04:28:07 PM PDT 24
Peak memory 200168 kb
Host smart-3c511c2b-4731-4b9a-b4e2-48b37d03d420
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196203289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
196203289
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2550606528
Short name T600
Test name
Test status
Simulation time 124913741 ps
CPU time 0.87 seconds
Started Jul 01 04:28:25 PM PDT 24
Finished Jul 01 04:28:30 PM PDT 24
Peak memory 200188 kb
Host smart-d0663452-a60b-4699-bc0c-a82cf7b39feb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550606528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
550606528
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3489979773
Short name T616
Test name
Test status
Simulation time 128539173 ps
CPU time 0.98 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 200156 kb
Host smart-9695ff25-08c4-4f41-abc9-34e58cd6c99c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489979773 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3489979773
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3033452194
Short name T612
Test name
Test status
Simulation time 146359423 ps
CPU time 1.11 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:11 PM PDT 24
Peak memory 200100 kb
Host smart-1a69c316-5cc4-4031-8110-fe129b1b791b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033452194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3033452194
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.318948413
Short name T570
Test name
Test status
Simulation time 266984078 ps
CPU time 2.03 seconds
Started Jul 01 04:27:58 PM PDT 24
Finished Jul 01 04:28:08 PM PDT 24
Peak memory 208332 kb
Host smart-8f541b8a-361b-4e11-82bc-b3f1e31f4fad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318948413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.318948413
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3342002089
Short name T88
Test name
Test status
Simulation time 787528221 ps
CPU time 2.66 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:11 PM PDT 24
Peak memory 200260 kb
Host smart-0cac526e-a442-41b7-8fde-74c8ffdf1bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342002089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3342002089
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1446515474
Short name T110
Test name
Test status
Simulation time 72985742 ps
CPU time 0.79 seconds
Started Jul 01 04:28:20 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 199916 kb
Host smart-cde0e1cb-4dea-486f-9a02-e13a46bb7221
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446515474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1446515474
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.766947418
Short name T563
Test name
Test status
Simulation time 98994178 ps
CPU time 1.25 seconds
Started Jul 01 04:28:20 PM PDT 24
Finished Jul 01 04:28:27 PM PDT 24
Peak memory 200244 kb
Host smart-83dcd534-9f2a-49b4-a65f-e9505c241528
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766947418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.766947418
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.34637741
Short name T590
Test name
Test status
Simulation time 580583266 ps
CPU time 3.48 seconds
Started Jul 01 04:28:35 PM PDT 24
Finished Jul 01 04:28:45 PM PDT 24
Peak memory 208380 kb
Host smart-a0737f67-f02d-4ba8-9a56-5fe3d556f15a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34637741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.34637741
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2740190635
Short name T551
Test name
Test status
Simulation time 177122042 ps
CPU time 1.27 seconds
Started Jul 01 04:28:11 PM PDT 24
Finished Jul 01 04:28:21 PM PDT 24
Peak memory 208356 kb
Host smart-95ebec92-76dd-4d71-beb5-074e7f721521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740190635 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2740190635
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3729282652
Short name T561
Test name
Test status
Simulation time 73696166 ps
CPU time 0.77 seconds
Started Jul 01 04:28:17 PM PDT 24
Finished Jul 01 04:28:24 PM PDT 24
Peak memory 200040 kb
Host smart-f87ca26d-e339-42ae-964f-c613fed0011b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729282652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3729282652
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2170112466
Short name T587
Test name
Test status
Simulation time 144954095 ps
CPU time 1.15 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 200400 kb
Host smart-6c5f46a1-e5ca-4536-b63c-8b8ccb538e05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170112466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2170112466
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2552634599
Short name T605
Test name
Test status
Simulation time 186704190 ps
CPU time 2.6 seconds
Started Jul 01 04:28:23 PM PDT 24
Finished Jul 01 04:28:31 PM PDT 24
Peak memory 208364 kb
Host smart-d5396f6f-7209-4ed7-a71d-d93a026343ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552634599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2552634599
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.659665392
Short name T620
Test name
Test status
Simulation time 919030508 ps
CPU time 2.95 seconds
Started Jul 01 04:28:15 PM PDT 24
Finished Jul 01 04:28:25 PM PDT 24
Peak memory 200284 kb
Host smart-58612f1c-60a2-4b00-a6d8-d04c74bb0a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659665392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.659665392
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2549064429
Short name T617
Test name
Test status
Simulation time 131692268 ps
CPU time 1.01 seconds
Started Jul 01 04:28:31 PM PDT 24
Finished Jul 01 04:28:37 PM PDT 24
Peak memory 200396 kb
Host smart-642ddc5b-2a2c-4fe4-bf3f-b3a45644b4bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549064429 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2549064429
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3074556631
Short name T593
Test name
Test status
Simulation time 88040215 ps
CPU time 0.87 seconds
Started Jul 01 04:28:12 PM PDT 24
Finished Jul 01 04:28:22 PM PDT 24
Peak memory 200040 kb
Host smart-0172e733-e9bd-448f-a67f-2c7e74ec10b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074556631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3074556631
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1984889187
Short name T579
Test name
Test status
Simulation time 70580439 ps
CPU time 0.88 seconds
Started Jul 01 04:28:03 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 200100 kb
Host smart-b8d28370-4839-4154-a45a-00ba0116b1d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984889187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1984889187
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3247322670
Short name T542
Test name
Test status
Simulation time 494541599 ps
CPU time 1.91 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:05 PM PDT 24
Peak memory 200448 kb
Host smart-f45c3ede-337e-4022-9c1e-a6e2315ca72f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247322670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3247322670
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4025755791
Short name T606
Test name
Test status
Simulation time 129622945 ps
CPU time 1.35 seconds
Started Jul 01 04:28:05 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 212752 kb
Host smart-c3eaac70-dc9d-4da7-a93b-368e099b8a3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025755791 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4025755791
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3198033542
Short name T588
Test name
Test status
Simulation time 79784567 ps
CPU time 0.84 seconds
Started Jul 01 04:28:19 PM PDT 24
Finished Jul 01 04:28:31 PM PDT 24
Peak memory 200148 kb
Host smart-29699539-5e47-4bca-bae0-abba97e85d80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198033542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3198033542
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.827301212
Short name T575
Test name
Test status
Simulation time 117646739 ps
CPU time 1.04 seconds
Started Jul 01 04:28:28 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 199984 kb
Host smart-b823ae82-df9c-4799-9843-17194a98f330
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827301212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.827301212
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2973066851
Short name T591
Test name
Test status
Simulation time 158247314 ps
CPU time 2.24 seconds
Started Jul 01 04:28:15 PM PDT 24
Finished Jul 01 04:28:25 PM PDT 24
Peak memory 208292 kb
Host smart-05879cb0-04cf-4527-8a1e-b6875ec8e97d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973066851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2973066851
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1354735865
Short name T58
Test name
Test status
Simulation time 472377313 ps
CPU time 2.04 seconds
Started Jul 01 04:28:03 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 200244 kb
Host smart-d7bd2964-5f31-484b-bb68-59fa6b77b506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354735865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1354735865
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2562296884
Short name T543
Test name
Test status
Simulation time 105066654 ps
CPU time 0.94 seconds
Started Jul 01 04:28:04 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 200124 kb
Host smart-649f63e0-2e1f-4549-bc8c-816dc8088efe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562296884 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2562296884
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2415542706
Short name T615
Test name
Test status
Simulation time 82248801 ps
CPU time 0.87 seconds
Started Jul 01 04:28:05 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 200044 kb
Host smart-8213ad00-3dff-4d30-9f66-66574f01f8a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415542706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2415542706
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.340075784
Short name T105
Test name
Test status
Simulation time 151707769 ps
CPU time 1.24 seconds
Started Jul 01 04:28:20 PM PDT 24
Finished Jul 01 04:28:27 PM PDT 24
Peak memory 200080 kb
Host smart-50b856e1-6f51-4837-979e-a207753480e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340075784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.340075784
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1287603583
Short name T85
Test name
Test status
Simulation time 243077966 ps
CPU time 2.03 seconds
Started Jul 01 04:28:03 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 208304 kb
Host smart-715805d7-9e54-41f7-a7d4-f3290ecea6ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287603583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1287603583
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1793084113
Short name T580
Test name
Test status
Simulation time 966743936 ps
CPU time 3.15 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:43 PM PDT 24
Peak memory 200364 kb
Host smart-8975195a-55ab-4680-9337-c612ebdf2820
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793084113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1793084113
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3190232676
Short name T568
Test name
Test status
Simulation time 195531231 ps
CPU time 1.29 seconds
Started Jul 01 04:28:27 PM PDT 24
Finished Jul 01 04:28:32 PM PDT 24
Peak memory 200176 kb
Host smart-feffc90f-321d-44ca-9a03-435fde6e05af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190232676 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3190232676
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2238804430
Short name T128
Test name
Test status
Simulation time 88111997 ps
CPU time 0.86 seconds
Started Jul 01 04:28:13 PM PDT 24
Finished Jul 01 04:28:21 PM PDT 24
Peak memory 199992 kb
Host smart-75d40a2e-9472-45e2-8efc-efd827a357a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238804430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2238804430
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2032690392
Short name T611
Test name
Test status
Simulation time 92497134 ps
CPU time 1.03 seconds
Started Jul 01 04:28:19 PM PDT 24
Finished Jul 01 04:28:25 PM PDT 24
Peak memory 200064 kb
Host smart-cb66038d-a94e-45ac-8132-dc585280e31b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032690392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2032690392
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2406760487
Short name T618
Test name
Test status
Simulation time 451947670 ps
CPU time 3.25 seconds
Started Jul 01 04:28:07 PM PDT 24
Finished Jul 01 04:28:21 PM PDT 24
Peak memory 200156 kb
Host smart-49076ad2-8926-447c-afe2-aa63677130e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406760487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2406760487
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1340702379
Short name T116
Test name
Test status
Simulation time 514906333 ps
CPU time 1.99 seconds
Started Jul 01 04:28:04 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 200256 kb
Host smart-24bc9834-6d87-49be-893c-e73d9d457fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340702379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1340702379
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4102276214
Short name T544
Test name
Test status
Simulation time 72704120 ps
CPU time 0.84 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:18 PM PDT 24
Peak memory 200308 kb
Host smart-94907249-9d2d-4d5e-801b-7861eb11d521
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102276214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.4102276214
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2756877217
Short name T547
Test name
Test status
Simulation time 88438776 ps
CPU time 0.99 seconds
Started Jul 01 04:28:27 PM PDT 24
Finished Jul 01 04:28:33 PM PDT 24
Peak memory 200064 kb
Host smart-9f2aeaf4-4d8c-4626-9f00-4f9971296764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756877217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2756877217
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3128250624
Short name T82
Test name
Test status
Simulation time 171649892 ps
CPU time 2.36 seconds
Started Jul 01 04:28:18 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 216528 kb
Host smart-5c1a6899-b753-4cdb-ba0b-e971112c4141
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128250624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3128250624
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1712935123
Short name T127
Test name
Test status
Simulation time 950411299 ps
CPU time 3.05 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 200240 kb
Host smart-4538d5a3-ca5e-40b0-a56f-004cfbad3c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712935123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1712935123
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2839620839
Short name T91
Test name
Test status
Simulation time 136944451 ps
CPU time 1.43 seconds
Started Jul 01 04:28:24 PM PDT 24
Finished Jul 01 04:28:31 PM PDT 24
Peak memory 208564 kb
Host smart-324ef538-ddea-49f0-a5a8-656f931c252d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839620839 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2839620839
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1098107634
Short name T554
Test name
Test status
Simulation time 68066345 ps
CPU time 0.8 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:54 PM PDT 24
Peak memory 199968 kb
Host smart-28c416c8-7edf-4076-a80b-d234e5d95ad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098107634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1098107634
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.492867045
Short name T610
Test name
Test status
Simulation time 223458006 ps
CPU time 1.46 seconds
Started Jul 01 04:28:18 PM PDT 24
Finished Jul 01 04:28:25 PM PDT 24
Peak memory 200200 kb
Host smart-7169104b-25ff-4f1a-bec7-a8076508dd52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492867045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.492867045
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.567872351
Short name T598
Test name
Test status
Simulation time 199440322 ps
CPU time 1.76 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:01 PM PDT 24
Peak memory 200384 kb
Host smart-0a8dddfd-4fbc-4650-bec8-6d0fea78e40f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567872351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.567872351
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1766017975
Short name T111
Test name
Test status
Simulation time 933077934 ps
CPU time 3.42 seconds
Started Jul 01 04:28:09 PM PDT 24
Finished Jul 01 04:28:22 PM PDT 24
Peak memory 200300 kb
Host smart-7d4dfe71-18dd-4607-9f44-87573c555027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766017975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1766017975
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.379545054
Short name T572
Test name
Test status
Simulation time 107823769 ps
CPU time 0.98 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 200368 kb
Host smart-efa38fe7-3f24-4085-aad8-7dc06fc67523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379545054 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.379545054
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1717828440
Short name T577
Test name
Test status
Simulation time 81912153 ps
CPU time 0.83 seconds
Started Jul 01 04:28:05 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 200148 kb
Host smart-51617abb-39ae-4fc0-951e-91f7b41d7c39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717828440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1717828440
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1981653036
Short name T548
Test name
Test status
Simulation time 86743477 ps
CPU time 0.95 seconds
Started Jul 01 04:28:15 PM PDT 24
Finished Jul 01 04:28:23 PM PDT 24
Peak memory 200084 kb
Host smart-43f5dd17-bbc8-4661-84fa-a5ccdb6a28fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981653036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1981653036
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2149228956
Short name T64
Test name
Test status
Simulation time 262950810 ps
CPU time 1.99 seconds
Started Jul 01 04:28:11 PM PDT 24
Finished Jul 01 04:28:22 PM PDT 24
Peak memory 208336 kb
Host smart-9f852043-cd28-4838-9492-facc3252fcca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149228956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2149228956
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.506782417
Short name T594
Test name
Test status
Simulation time 884366681 ps
CPU time 2.89 seconds
Started Jul 01 04:28:28 PM PDT 24
Finished Jul 01 04:28:35 PM PDT 24
Peak memory 200256 kb
Host smart-95286f5e-decf-4c9a-aa2e-8f06ce8d4b10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506782417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.506782417
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2707458506
Short name T601
Test name
Test status
Simulation time 114745042 ps
CPU time 1.21 seconds
Started Jul 01 04:28:04 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 208304 kb
Host smart-e14fa403-fe13-4ae0-aadb-52b32df61f3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707458506 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2707458506
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.515976456
Short name T545
Test name
Test status
Simulation time 69068287 ps
CPU time 0.9 seconds
Started Jul 01 04:28:37 PM PDT 24
Finished Jul 01 04:28:44 PM PDT 24
Peak memory 200264 kb
Host smart-cee7b145-cffd-4a13-8539-a6661b6806a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515976456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.515976456
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4080870042
Short name T559
Test name
Test status
Simulation time 191273995 ps
CPU time 1.45 seconds
Started Jul 01 04:28:06 PM PDT 24
Finished Jul 01 04:28:19 PM PDT 24
Peak memory 200192 kb
Host smart-7ee27c14-73f5-4c5c-91f0-3d2cc3a53cfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080870042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.4080870042
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3498283048
Short name T556
Test name
Test status
Simulation time 210867723 ps
CPU time 1.73 seconds
Started Jul 01 04:28:03 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 208588 kb
Host smart-8967da0e-1ff3-4c48-9753-74b571250e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498283048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3498283048
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.520320650
Short name T584
Test name
Test status
Simulation time 482319614 ps
CPU time 2.02 seconds
Started Jul 01 04:28:29 PM PDT 24
Finished Jul 01 04:28:42 PM PDT 24
Peak memory 200656 kb
Host smart-df01612b-c750-4bc8-8b59-5c2b6d4ae576
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520320650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.520320650
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.474064102
Short name T576
Test name
Test status
Simulation time 158365912 ps
CPU time 1.98 seconds
Started Jul 01 04:27:56 PM PDT 24
Finished Jul 01 04:28:04 PM PDT 24
Peak memory 200152 kb
Host smart-5cae826c-d84c-4346-9089-6bf3b94254ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474064102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.474064102
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3775949489
Short name T541
Test name
Test status
Simulation time 799579925 ps
CPU time 4.46 seconds
Started Jul 01 04:28:06 PM PDT 24
Finished Jul 01 04:28:20 PM PDT 24
Peak memory 200180 kb
Host smart-ece43c56-27be-4e45-aff0-4aa136980b06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775949489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
775949489
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2948886622
Short name T557
Test name
Test status
Simulation time 93273842 ps
CPU time 0.81 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:11 PM PDT 24
Peak memory 199980 kb
Host smart-2bdfa2b1-5441-4523-b571-9f1b266e14e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948886622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
948886622
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.311186993
Short name T549
Test name
Test status
Simulation time 130024007 ps
CPU time 1.37 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 208480 kb
Host smart-997e848e-9fe6-4e67-b72e-4d542dee0b25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311186993 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.311186993
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3681704228
Short name T574
Test name
Test status
Simulation time 71570030 ps
CPU time 0.87 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 200040 kb
Host smart-a90af2e0-6cc7-4538-b2aa-dc838ca8d9d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681704228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3681704228
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.134609306
Short name T61
Test name
Test status
Simulation time 88230269 ps
CPU time 1.01 seconds
Started Jul 01 04:28:05 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 200084 kb
Host smart-f359f62e-a8f6-4870-8d55-fd15d69b8efa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134609306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.134609306
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1035405947
Short name T118
Test name
Test status
Simulation time 307959497 ps
CPU time 2.29 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:13 PM PDT 24
Peak memory 200332 kb
Host smart-295e0aac-98b6-4218-8936-09d286d403c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035405947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1035405947
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.373788617
Short name T87
Test name
Test status
Simulation time 526825538 ps
CPU time 2.01 seconds
Started Jul 01 04:28:15 PM PDT 24
Finished Jul 01 04:28:24 PM PDT 24
Peak memory 200288 kb
Host smart-76115ee3-109f-4f5a-93f6-eac867d95924
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373788617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
373788617
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3844311530
Short name T597
Test name
Test status
Simulation time 154497587 ps
CPU time 2.03 seconds
Started Jul 01 04:27:58 PM PDT 24
Finished Jul 01 04:28:07 PM PDT 24
Peak memory 200352 kb
Host smart-ae34d06b-3550-4b8e-af12-6fd33134feb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844311530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
844311530
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2118899793
Short name T609
Test name
Test status
Simulation time 1545243439 ps
CPU time 7.75 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:17 PM PDT 24
Peak memory 200168 kb
Host smart-292cc2cf-7d82-435e-ba57-6835ab471bf8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118899793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
118899793
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.699630224
Short name T586
Test name
Test status
Simulation time 142689683 ps
CPU time 0.89 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 200024 kb
Host smart-886f3c9a-d70a-42c7-894c-80ded7f36c17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699630224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.699630224
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1469256776
Short name T599
Test name
Test status
Simulation time 120369888 ps
CPU time 0.93 seconds
Started Jul 01 04:28:03 PM PDT 24
Finished Jul 01 04:28:13 PM PDT 24
Peak memory 200048 kb
Host smart-fe9669dd-cc95-403b-997a-1cd9e86c74d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469256776 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1469256776
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2333608173
Short name T108
Test name
Test status
Simulation time 57025303 ps
CPU time 0.78 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 200040 kb
Host smart-68c0e81c-c346-4b06-8214-411db709ffa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333608173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2333608173
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.757139462
Short name T546
Test name
Test status
Simulation time 84149501 ps
CPU time 1.02 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:10 PM PDT 24
Peak memory 200080 kb
Host smart-b6b79534-0b3f-4f2c-9e08-b894e73f75c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757139462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.757139462
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2449515146
Short name T566
Test name
Test status
Simulation time 133819187 ps
CPU time 1.67 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:13 PM PDT 24
Peak memory 216316 kb
Host smart-90c4772e-20c1-4102-af27-8455902ceafa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449515146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2449515146
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1224331934
Short name T114
Test name
Test status
Simulation time 775986774 ps
CPU time 2.89 seconds
Started Jul 01 04:28:27 PM PDT 24
Finished Jul 01 04:28:35 PM PDT 24
Peak memory 200248 kb
Host smart-804f37b7-e452-4fdb-a203-4332601cd01d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224331934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1224331934
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2301373344
Short name T578
Test name
Test status
Simulation time 112495441 ps
CPU time 1.33 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 200240 kb
Host smart-3dc18eae-1636-413e-8523-5ed0d677a593
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301373344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
301373344
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3085384555
Short name T560
Test name
Test status
Simulation time 486571199 ps
CPU time 5.56 seconds
Started Jul 01 04:28:03 PM PDT 24
Finished Jul 01 04:28:19 PM PDT 24
Peak memory 200160 kb
Host smart-6c469c24-07a0-469a-83c1-81565b0a6f59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085384555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
085384555
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2015698105
Short name T592
Test name
Test status
Simulation time 132740015 ps
CPU time 0.97 seconds
Started Jul 01 04:28:09 PM PDT 24
Finished Jul 01 04:28:20 PM PDT 24
Peak memory 200284 kb
Host smart-7b00af72-5430-4e70-a64e-f6001c3b06b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015698105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
015698105
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1081594698
Short name T562
Test name
Test status
Simulation time 178439970 ps
CPU time 1.65 seconds
Started Jul 01 04:28:04 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 208588 kb
Host smart-2a473403-2221-492e-8a17-8bb8e9ccd4d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081594698 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1081594698
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1049214679
Short name T62
Test name
Test status
Simulation time 69075850 ps
CPU time 0.78 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 199996 kb
Host smart-4fab0090-7bbe-4be6-a38c-31ba912b6498
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049214679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1049214679
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4022671791
Short name T104
Test name
Test status
Simulation time 207861279 ps
CPU time 1.57 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:13 PM PDT 24
Peak memory 200180 kb
Host smart-2e243375-9e5a-4f75-9f17-b2090820628a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022671791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.4022671791
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.374938636
Short name T90
Test name
Test status
Simulation time 276481704 ps
CPU time 2.08 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 211832 kb
Host smart-3169c413-efa8-405d-84ef-a42e37b5ba94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374938636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.374938636
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1406740049
Short name T113
Test name
Test status
Simulation time 403857935 ps
CPU time 1.96 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:11 PM PDT 24
Peak memory 200740 kb
Host smart-152f25f6-b801-4936-8a78-9abf59ccf53c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406740049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1406740049
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3681596400
Short name T613
Test name
Test status
Simulation time 113948453 ps
CPU time 1.15 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 208540 kb
Host smart-8cf0f5ee-b3fb-46ff-9006-f06f84e82ce7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681596400 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3681596400
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2002809125
Short name T106
Test name
Test status
Simulation time 58189916 ps
CPU time 0.72 seconds
Started Jul 01 04:28:04 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 199968 kb
Host smart-4d208415-4181-4064-bc53-ac6fc7510435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002809125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2002809125
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.249360366
Short name T553
Test name
Test status
Simulation time 153488668 ps
CPU time 1.23 seconds
Started Jul 01 04:28:12 PM PDT 24
Finished Jul 01 04:28:22 PM PDT 24
Peak memory 199932 kb
Host smart-2a304435-9c23-48d9-b9e1-e7416d783673
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249360366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.249360366
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1713281210
Short name T571
Test name
Test status
Simulation time 703026465 ps
CPU time 4.57 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:18 PM PDT 24
Peak memory 208600 kb
Host smart-994a7105-1c8d-4921-8f56-730070e822a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713281210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1713281210
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1908013540
Short name T619
Test name
Test status
Simulation time 176407761 ps
CPU time 1.65 seconds
Started Jul 01 04:28:27 PM PDT 24
Finished Jul 01 04:28:33 PM PDT 24
Peak memory 208548 kb
Host smart-92a20736-6800-4985-ab32-301f41902bf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908013540 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1908013540
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.68348796
Short name T558
Test name
Test status
Simulation time 59856660 ps
CPU time 0.77 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 200100 kb
Host smart-8e071d09-a66f-44fe-b1e3-a4d859955f5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68348796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.68348796
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3972738711
Short name T59
Test name
Test status
Simulation time 123450147 ps
CPU time 1.07 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:28:04 PM PDT 24
Peak memory 200060 kb
Host smart-38b54ad2-4742-45cc-a80e-f3113f2744e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972738711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3972738711
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1397419562
Short name T596
Test name
Test status
Simulation time 222993897 ps
CPU time 1.7 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:28:05 PM PDT 24
Peak memory 208308 kb
Host smart-6d84b3af-82ce-42b4-ba88-6d51d066b0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397419562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1397419562
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2451670195
Short name T582
Test name
Test status
Simulation time 927875257 ps
CPU time 3.28 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 200524 kb
Host smart-41d2d3cb-942b-455e-9248-e2581fa69b8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451670195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2451670195
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.901483174
Short name T84
Test name
Test status
Simulation time 153444024 ps
CPU time 1.31 seconds
Started Jul 01 04:27:56 PM PDT 24
Finished Jul 01 04:28:04 PM PDT 24
Peak memory 200148 kb
Host smart-61adda9b-fd4f-40a4-aeb0-a78bdfbf1da7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901483174 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.901483174
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.635578840
Short name T595
Test name
Test status
Simulation time 70915682 ps
CPU time 0.83 seconds
Started Jul 01 04:28:27 PM PDT 24
Finished Jul 01 04:28:32 PM PDT 24
Peak memory 199984 kb
Host smart-0c428ecb-5723-4c7a-92d9-df46302a9aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635578840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.635578840
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.323863229
Short name T607
Test name
Test status
Simulation time 212531904 ps
CPU time 1.48 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 200244 kb
Host smart-b24d6666-fe0d-4e15-9b66-4fe0ab4ec083
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323863229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.323863229
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.872121069
Short name T564
Test name
Test status
Simulation time 361403060 ps
CPU time 2.71 seconds
Started Jul 01 04:28:10 PM PDT 24
Finished Jul 01 04:28:22 PM PDT 24
Peak memory 208332 kb
Host smart-549cbb93-517f-4d44-9edc-d863b2e1735e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872121069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.872121069
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.42853536
Short name T583
Test name
Test status
Simulation time 495126007 ps
CPU time 2.05 seconds
Started Jul 01 04:27:58 PM PDT 24
Finished Jul 01 04:28:08 PM PDT 24
Peak memory 200188 kb
Host smart-e0564715-6e48-42af-8b03-641624044479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42853536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.42853536
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2435978361
Short name T565
Test name
Test status
Simulation time 132490447 ps
CPU time 1.33 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:11 PM PDT 24
Peak memory 212372 kb
Host smart-58d57ad2-2845-46b4-8064-d28f3aa50eb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435978361 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2435978361
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4154654144
Short name T569
Test name
Test status
Simulation time 93818749 ps
CPU time 0.89 seconds
Started Jul 01 04:28:12 PM PDT 24
Finished Jul 01 04:28:21 PM PDT 24
Peak memory 200272 kb
Host smart-43e9de18-d5c5-4764-b4ee-ea97a57819e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154654144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4154654144
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3309948363
Short name T602
Test name
Test status
Simulation time 190647635 ps
CPU time 1.36 seconds
Started Jul 01 04:28:27 PM PDT 24
Finished Jul 01 04:28:33 PM PDT 24
Peak memory 200288 kb
Host smart-76d63d74-8dec-4bfa-bbf6-6ec02b6d0812
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309948363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3309948363
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2291359658
Short name T63
Test name
Test status
Simulation time 287290108 ps
CPU time 2.02 seconds
Started Jul 01 04:27:58 PM PDT 24
Finished Jul 01 04:28:08 PM PDT 24
Peak memory 216368 kb
Host smart-41a3097a-0ece-4db7-b4bf-a88e9fce2c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291359658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2291359658
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.150017339
Short name T89
Test name
Test status
Simulation time 477366402 ps
CPU time 2.05 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:11 PM PDT 24
Peak memory 200256 kb
Host smart-e5431ce2-1ae4-4968-975a-9f79654f874b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150017339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
150017339
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1129553352
Short name T614
Test name
Test status
Simulation time 125537391 ps
CPU time 1.21 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:13 PM PDT 24
Peak memory 208356 kb
Host smart-76be7b80-94ec-48c3-a011-d3bf7855da2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129553352 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1129553352
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2521783840
Short name T604
Test name
Test status
Simulation time 55449676 ps
CPU time 0.73 seconds
Started Jul 01 04:28:03 PM PDT 24
Finished Jul 01 04:28:13 PM PDT 24
Peak memory 200044 kb
Host smart-97d35a22-ee07-4920-b876-e35ef06e82f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521783840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2521783840
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2170105754
Short name T109
Test name
Test status
Simulation time 152526663 ps
CPU time 1.18 seconds
Started Jul 01 04:28:03 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 200100 kb
Host smart-5add8023-5398-48ab-8bbc-584b2d1382a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170105754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2170105754
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3034530539
Short name T581
Test name
Test status
Simulation time 449250616 ps
CPU time 2.8 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 216456 kb
Host smart-36e14496-9e0b-41ae-ba5b-e728bb02d21e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034530539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3034530539
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.685767031
Short name T144
Test name
Test status
Simulation time 64407630 ps
CPU time 0.74 seconds
Started Jul 01 04:40:47 PM PDT 24
Finished Jul 01 04:40:51 PM PDT 24
Peak memory 199808 kb
Host smart-b02737c3-b5e8-4cc2-bd1c-bde3c07685b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685767031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.685767031
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1811512420
Short name T43
Test name
Test status
Simulation time 1220922213 ps
CPU time 5.4 seconds
Started Jul 01 04:40:44 PM PDT 24
Finished Jul 01 04:40:52 PM PDT 24
Peak memory 221600 kb
Host smart-1df7f9da-6c72-4ce2-b902-47b28b04a246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811512420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1811512420
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2210106790
Short name T368
Test name
Test status
Simulation time 244037154 ps
CPU time 1.04 seconds
Started Jul 01 04:40:44 PM PDT 24
Finished Jul 01 04:40:47 PM PDT 24
Peak memory 217376 kb
Host smart-18d43f17-7ab7-4ff3-8b30-5beb5bacfe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210106790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2210106790
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3356416648
Short name T307
Test name
Test status
Simulation time 220827904 ps
CPU time 0.93 seconds
Started Jul 01 04:40:47 PM PDT 24
Finished Jul 01 04:40:50 PM PDT 24
Peak memory 199748 kb
Host smart-1b1207e3-cdd6-4e3d-b94b-d97073025a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356416648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3356416648
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.268753235
Short name T302
Test name
Test status
Simulation time 1034214720 ps
CPU time 4.96 seconds
Started Jul 01 04:40:54 PM PDT 24
Finished Jul 01 04:41:03 PM PDT 24
Peak memory 200200 kb
Host smart-f96c4b27-9c87-43d3-a12a-490c42951d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268753235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.268753235
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2173997902
Short name T185
Test name
Test status
Simulation time 192493819 ps
CPU time 1.36 seconds
Started Jul 01 04:40:45 PM PDT 24
Finished Jul 01 04:40:49 PM PDT 24
Peak memory 200112 kb
Host smart-c128be2d-8256-4586-ab3d-e87b6d37fc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173997902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2173997902
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2519030865
Short name T168
Test name
Test status
Simulation time 248286418 ps
CPU time 1.45 seconds
Started Jul 01 04:40:44 PM PDT 24
Finished Jul 01 04:40:47 PM PDT 24
Peak memory 200220 kb
Host smart-2aaa38e1-5ea4-4630-99bb-d85b32cd5be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519030865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2519030865
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2414155118
Short name T231
Test name
Test status
Simulation time 899213182 ps
CPU time 4.37 seconds
Started Jul 01 04:40:56 PM PDT 24
Finished Jul 01 04:41:04 PM PDT 24
Peak memory 200200 kb
Host smart-236eee6c-e3aa-4ad9-a61a-abbb576c4dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414155118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2414155118
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3967916121
Short name T362
Test name
Test status
Simulation time 303660384 ps
CPU time 1.88 seconds
Started Jul 01 04:40:46 PM PDT 24
Finished Jul 01 04:40:51 PM PDT 24
Peak memory 208124 kb
Host smart-28be22d6-ba1e-4144-8537-b835ad45985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967916121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3967916121
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.540607913
Short name T336
Test name
Test status
Simulation time 68696554 ps
CPU time 0.76 seconds
Started Jul 01 04:40:45 PM PDT 24
Finished Jul 01 04:40:48 PM PDT 24
Peak memory 200036 kb
Host smart-fe74e9c2-76c9-40d7-ab3c-866e979e5b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540607913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.540607913
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2223952694
Short name T184
Test name
Test status
Simulation time 77624512 ps
CPU time 0.79 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:40:56 PM PDT 24
Peak memory 199824 kb
Host smart-4229b322-ca6d-47c7-8d5f-31a2b38ec9f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223952694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2223952694
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.4138472214
Short name T254
Test name
Test status
Simulation time 1226323900 ps
CPU time 5.52 seconds
Started Jul 01 04:40:52 PM PDT 24
Finished Jul 01 04:41:00 PM PDT 24
Peak memory 221404 kb
Host smart-0ac22af0-4afb-4018-8456-4f737276c934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138472214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.4138472214
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3600746948
Short name T308
Test name
Test status
Simulation time 243994391 ps
CPU time 1.14 seconds
Started Jul 01 04:40:52 PM PDT 24
Finished Jul 01 04:40:55 PM PDT 24
Peak memory 217392 kb
Host smart-90a357da-f15c-4e97-9701-488779f827f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600746948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3600746948
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3314078030
Short name T77
Test name
Test status
Simulation time 201618942 ps
CPU time 0.85 seconds
Started Jul 01 04:40:45 PM PDT 24
Finished Jul 01 04:40:49 PM PDT 24
Peak memory 199844 kb
Host smart-5add57c1-3119-40f2-9886-505f42fffb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314078030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3314078030
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2300382315
Short name T268
Test name
Test status
Simulation time 769415690 ps
CPU time 3.91 seconds
Started Jul 01 04:40:45 PM PDT 24
Finished Jul 01 04:40:52 PM PDT 24
Peak memory 200328 kb
Host smart-7893b805-d244-429c-9eaf-16a5ab3c134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300382315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2300382315
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1060301014
Short name T67
Test name
Test status
Simulation time 16522836902 ps
CPU time 33.44 seconds
Started Jul 01 04:40:52 PM PDT 24
Finished Jul 01 04:41:27 PM PDT 24
Peak memory 218160 kb
Host smart-193e66f0-77cf-430b-95d3-1c0a0152d7ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060301014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1060301014
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1984945048
Short name T209
Test name
Test status
Simulation time 112607347 ps
CPU time 1.21 seconds
Started Jul 01 04:40:44 PM PDT 24
Finished Jul 01 04:40:47 PM PDT 24
Peak memory 200156 kb
Host smart-98f6d2db-2d37-428a-8e98-987692071fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984945048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1984945048
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2251892215
Short name T405
Test name
Test status
Simulation time 5453116132 ps
CPU time 19.91 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:41:15 PM PDT 24
Peak memory 209660 kb
Host smart-6094964e-15e5-4c15-a627-903be2af1859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251892215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2251892215
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3569663584
Short name T464
Test name
Test status
Simulation time 127689087 ps
CPU time 1.55 seconds
Started Jul 01 04:40:47 PM PDT 24
Finished Jul 01 04:40:51 PM PDT 24
Peak memory 200056 kb
Host smart-31f49cf8-b3ad-4c40-9f04-61eae2e34f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569663584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3569663584
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2411276559
Short name T482
Test name
Test status
Simulation time 134566666 ps
CPU time 1.03 seconds
Started Jul 01 04:40:54 PM PDT 24
Finished Jul 01 04:40:59 PM PDT 24
Peak memory 199928 kb
Host smart-a6b239b0-57bf-4c42-8467-f91a8c2ddc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411276559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2411276559
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2220428423
Short name T346
Test name
Test status
Simulation time 76785672 ps
CPU time 0.79 seconds
Started Jul 01 04:41:08 PM PDT 24
Finished Jul 01 04:41:11 PM PDT 24
Peak memory 199740 kb
Host smart-7f863800-b8b8-458e-ad76-4280708c7ade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220428423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2220428423
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3694563508
Short name T391
Test name
Test status
Simulation time 1222169321 ps
CPU time 5.89 seconds
Started Jul 01 04:41:13 PM PDT 24
Finished Jul 01 04:41:23 PM PDT 24
Peak memory 217392 kb
Host smart-bd69fbbe-9fe3-4b86-b1a2-62fe1afd71d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694563508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3694563508
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1246836183
Short name T493
Test name
Test status
Simulation time 243874016 ps
CPU time 1.13 seconds
Started Jul 01 04:41:11 PM PDT 24
Finished Jul 01 04:41:16 PM PDT 24
Peak memory 217392 kb
Host smart-c4bae02e-67b7-495f-9418-5182e2e32073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246836183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1246836183
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2312245463
Short name T537
Test name
Test status
Simulation time 90993460 ps
CPU time 0.78 seconds
Started Jul 01 04:41:10 PM PDT 24
Finished Jul 01 04:41:14 PM PDT 24
Peak memory 199892 kb
Host smart-9e298ccf-28d7-4b81-a902-874d2839359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312245463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2312245463
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1576229302
Short name T427
Test name
Test status
Simulation time 1430335646 ps
CPU time 5.81 seconds
Started Jul 01 04:41:09 PM PDT 24
Finished Jul 01 04:41:17 PM PDT 24
Peak memory 200284 kb
Host smart-2af0e031-0e38-4d65-9178-6b2f38d0927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576229302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1576229302
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1746477985
Short name T460
Test name
Test status
Simulation time 171411145 ps
CPU time 1.19 seconds
Started Jul 01 04:41:11 PM PDT 24
Finished Jul 01 04:41:15 PM PDT 24
Peak memory 200124 kb
Host smart-5aede428-122a-4414-be30-03bd37db67fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746477985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1746477985
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1467942488
Short name T251
Test name
Test status
Simulation time 120873684 ps
CPU time 1.25 seconds
Started Jul 01 04:41:09 PM PDT 24
Finished Jul 01 04:41:13 PM PDT 24
Peak memory 200264 kb
Host smart-dfe490b1-3ae2-4783-befc-ec2ba1a9fded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467942488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1467942488
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.976721925
Short name T265
Test name
Test status
Simulation time 4761615177 ps
CPU time 17.17 seconds
Started Jul 01 04:41:09 PM PDT 24
Finished Jul 01 04:41:28 PM PDT 24
Peak memory 200348 kb
Host smart-f67a9df1-9b74-463c-a1df-6509f7220ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976721925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.976721925
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3439583703
Short name T124
Test name
Test status
Simulation time 378830941 ps
CPU time 2.11 seconds
Started Jul 01 04:41:09 PM PDT 24
Finished Jul 01 04:41:14 PM PDT 24
Peak memory 200116 kb
Host smart-e253a931-a28e-44e6-a881-9f55859c19b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439583703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3439583703
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.197398067
Short name T500
Test name
Test status
Simulation time 80905516 ps
CPU time 0.82 seconds
Started Jul 01 04:41:11 PM PDT 24
Finished Jul 01 04:41:14 PM PDT 24
Peak memory 199952 kb
Host smart-5c4cbcb0-19b5-460d-9f8f-a43f28b9e866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197398067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.197398067
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2155275583
Short name T470
Test name
Test status
Simulation time 71319577 ps
CPU time 0.75 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:28 PM PDT 24
Peak memory 199824 kb
Host smart-12d3a0e0-2446-4b6b-b0f3-c5e6e9a604ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155275583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2155275583
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.826362148
Short name T506
Test name
Test status
Simulation time 1223701258 ps
CPU time 5.76 seconds
Started Jul 01 04:41:12 PM PDT 24
Finished Jul 01 04:41:22 PM PDT 24
Peak memory 216760 kb
Host smart-2d3c181f-80c6-4350-98f6-9f321dba1224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826362148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.826362148
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.466406773
Short name T174
Test name
Test status
Simulation time 243775123 ps
CPU time 1.12 seconds
Started Jul 01 04:41:10 PM PDT 24
Finished Jul 01 04:41:14 PM PDT 24
Peak memory 217392 kb
Host smart-338e97c1-4647-42ec-8b2a-f706e3d21105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466406773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.466406773
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1978628678
Short name T230
Test name
Test status
Simulation time 1685385086 ps
CPU time 6.22 seconds
Started Jul 01 04:41:16 PM PDT 24
Finished Jul 01 04:41:25 PM PDT 24
Peak memory 200284 kb
Host smart-9d9f2751-2aa2-4607-87df-a82b8f8f96fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978628678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1978628678
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.4075977423
Short name T133
Test name
Test status
Simulation time 175572228 ps
CPU time 1.19 seconds
Started Jul 01 04:41:16 PM PDT 24
Finished Jul 01 04:41:20 PM PDT 24
Peak memory 199776 kb
Host smart-cb1843be-4811-4692-a4fd-f4ee43d02bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075977423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.4075977423
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1832161166
Short name T165
Test name
Test status
Simulation time 122901012 ps
CPU time 1.17 seconds
Started Jul 01 04:41:09 PM PDT 24
Finished Jul 01 04:41:13 PM PDT 24
Peak memory 200092 kb
Host smart-8e4dc660-d2cd-4920-a5f2-fe23643206d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832161166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1832161166
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.494638405
Short name T498
Test name
Test status
Simulation time 3632390415 ps
CPU time 16.27 seconds
Started Jul 01 04:41:11 PM PDT 24
Finished Jul 01 04:41:31 PM PDT 24
Peak memory 200356 kb
Host smart-d9683e5b-c6de-4e9d-a092-c86ae74a6ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494638405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.494638405
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1101175273
Short name T441
Test name
Test status
Simulation time 373025209 ps
CPU time 2.18 seconds
Started Jul 01 04:41:10 PM PDT 24
Finished Jul 01 04:41:15 PM PDT 24
Peak memory 208224 kb
Host smart-b8c0e17f-c703-4dd3-87c6-d9eee59eec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101175273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1101175273
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3543248597
Short name T448
Test name
Test status
Simulation time 189699538 ps
CPU time 1.3 seconds
Started Jul 01 04:41:11 PM PDT 24
Finished Jul 01 04:41:16 PM PDT 24
Peak memory 199988 kb
Host smart-7e02c973-5f90-4baf-87cb-9746e34855a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543248597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3543248597
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2494087216
Short name T140
Test name
Test status
Simulation time 73157153 ps
CPU time 0.81 seconds
Started Jul 01 04:41:23 PM PDT 24
Finished Jul 01 04:41:32 PM PDT 24
Peak memory 199832 kb
Host smart-246c779e-27e9-49d2-affe-31689cfb7452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494087216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2494087216
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3503310725
Short name T295
Test name
Test status
Simulation time 1899165353 ps
CPU time 6.8 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:34 PM PDT 24
Peak memory 216604 kb
Host smart-79a0fab0-4d84-425c-87b5-6a8b1f664d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503310725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3503310725
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.790337538
Short name T157
Test name
Test status
Simulation time 243779026 ps
CPU time 1.05 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:30 PM PDT 24
Peak memory 217392 kb
Host smart-3928879a-a759-4357-9239-c1a226dfd689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790337538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.790337538
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3132337190
Short name T21
Test name
Test status
Simulation time 153074423 ps
CPU time 0.84 seconds
Started Jul 01 04:41:17 PM PDT 24
Finished Jul 01 04:41:20 PM PDT 24
Peak memory 200044 kb
Host smart-84a2a5e3-12bb-4c23-b94a-9e3447c1fb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132337190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3132337190
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3870795515
Short name T312
Test name
Test status
Simulation time 1663840609 ps
CPU time 6.17 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:32 PM PDT 24
Peak memory 200188 kb
Host smart-ee3d570b-6edf-4de7-bb73-22f5ea60fb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870795515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3870795515
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.4021098353
Short name T501
Test name
Test status
Simulation time 106984224 ps
CPU time 1 seconds
Started Jul 01 04:41:23 PM PDT 24
Finished Jul 01 04:41:32 PM PDT 24
Peak memory 200032 kb
Host smart-fecacf53-39f2-4aa2-a94b-4c74a5626184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021098353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.4021098353
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.165978721
Short name T523
Test name
Test status
Simulation time 122785142 ps
CPU time 1.14 seconds
Started Jul 01 04:41:17 PM PDT 24
Finished Jul 01 04:41:21 PM PDT 24
Peak memory 200216 kb
Host smart-420f0342-5d88-4a6c-ac1a-363a2c3eec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165978721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.165978721
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3799940634
Short name T259
Test name
Test status
Simulation time 8051964216 ps
CPU time 27.89 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:57 PM PDT 24
Peak memory 200440 kb
Host smart-e687f9b5-c715-48c7-a722-1a68802cc7fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799940634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3799940634
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1940226869
Short name T290
Test name
Test status
Simulation time 326954438 ps
CPU time 2.18 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:32 PM PDT 24
Peak memory 199928 kb
Host smart-932bd583-2a89-48dd-8ea3-d8ef3120ef6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940226869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1940226869
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.790209482
Short name T536
Test name
Test status
Simulation time 239375696 ps
CPU time 1.46 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:29 PM PDT 24
Peak memory 200260 kb
Host smart-4a76a1cd-d6ba-4d06-9925-109abc008c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790209482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.790209482
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.805527538
Short name T513
Test name
Test status
Simulation time 76775348 ps
CPU time 0.8 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:30 PM PDT 24
Peak memory 199724 kb
Host smart-79ecd302-6a58-4b53-930e-cd208655d0fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805527538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.805527538
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2401960715
Short name T41
Test name
Test status
Simulation time 1228371073 ps
CPU time 5.38 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:30 PM PDT 24
Peak memory 217760 kb
Host smart-81a2089c-edb1-4e0f-aaa3-d063c32bb842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401960715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2401960715
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.571971718
Short name T518
Test name
Test status
Simulation time 244564743 ps
CPU time 1.16 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:26 PM PDT 24
Peak memory 217452 kb
Host smart-ca153989-4ef6-4495-8de8-82fbd38b62f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571971718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.571971718
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.61247642
Short name T454
Test name
Test status
Simulation time 171368674 ps
CPU time 0.93 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:28 PM PDT 24
Peak memory 199844 kb
Host smart-5450b35e-4377-4051-9498-6645cd400ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61247642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.61247642
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2431532421
Short name T381
Test name
Test status
Simulation time 800571411 ps
CPU time 4.33 seconds
Started Jul 01 04:41:22 PM PDT 24
Finished Jul 01 04:41:34 PM PDT 24
Peak memory 200264 kb
Host smart-c2cfa5a3-f8dd-44ea-9752-f281f4823cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431532421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2431532421
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2277048674
Short name T535
Test name
Test status
Simulation time 180442559 ps
CPU time 1.19 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:24 PM PDT 24
Peak memory 200028 kb
Host smart-006397bd-93eb-4cfd-ac1a-b6f6b54d0a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277048674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2277048674
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.459527198
Short name T101
Test name
Test status
Simulation time 5001653358 ps
CPU time 20.55 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:43 PM PDT 24
Peak memory 200268 kb
Host smart-7c2a4777-66f8-4927-87e5-0e96bca7c7ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459527198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.459527198
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.446465427
Short name T286
Test name
Test status
Simulation time 136188879 ps
CPU time 1.72 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:30 PM PDT 24
Peak memory 200032 kb
Host smart-0d663739-db16-49d7-b266-74c38e90428d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446465427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.446465427
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.837632831
Short name T324
Test name
Test status
Simulation time 61246715 ps
CPU time 0.75 seconds
Started Jul 01 04:41:24 PM PDT 24
Finished Jul 01 04:41:33 PM PDT 24
Peak memory 199820 kb
Host smart-1806594d-0a70-414b-a547-f18570af7799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837632831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.837632831
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2675771002
Short name T272
Test name
Test status
Simulation time 245330048 ps
CPU time 1.06 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:28 PM PDT 24
Peak memory 217392 kb
Host smart-b6b94dd6-704d-459e-b629-61138d3cec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675771002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2675771002
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3101663724
Short name T434
Test name
Test status
Simulation time 210333162 ps
CPU time 0.89 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:30 PM PDT 24
Peak memory 199720 kb
Host smart-ef9cd3dd-412f-40d4-b156-2bfb01488169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101663724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3101663724
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3555688254
Short name T540
Test name
Test status
Simulation time 1643757438 ps
CPU time 7.04 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:32 PM PDT 24
Peak memory 200284 kb
Host smart-ef4778eb-3d43-4671-ace1-1d1689218c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555688254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3555688254
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3228013160
Short name T396
Test name
Test status
Simulation time 143287584 ps
CPU time 1.13 seconds
Started Jul 01 04:41:23 PM PDT 24
Finished Jul 01 04:41:33 PM PDT 24
Peak memory 200140 kb
Host smart-8cc02ba4-11c0-4798-8b23-a5bef88715fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228013160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3228013160
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3279176589
Short name T228
Test name
Test status
Simulation time 260038924 ps
CPU time 1.46 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:31 PM PDT 24
Peak memory 200208 kb
Host smart-e7b7d489-7bf0-4ace-9b36-07e7bfebae36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279176589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3279176589
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1501341464
Short name T338
Test name
Test status
Simulation time 3078549093 ps
CPU time 14.34 seconds
Started Jul 01 04:41:23 PM PDT 24
Finished Jul 01 04:41:46 PM PDT 24
Peak memory 208548 kb
Host smart-9810d120-823c-4561-ac31-901eaabba360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501341464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1501341464
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1392243586
Short name T530
Test name
Test status
Simulation time 385622363 ps
CPU time 2.27 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:27 PM PDT 24
Peak memory 208264 kb
Host smart-143fdb9a-8141-4702-948b-a2aa683a6eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392243586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1392243586
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2487560696
Short name T483
Test name
Test status
Simulation time 174025526 ps
CPU time 1.21 seconds
Started Jul 01 04:41:23 PM PDT 24
Finished Jul 01 04:41:33 PM PDT 24
Peak memory 200040 kb
Host smart-9311cf3c-95a1-45d8-a947-85de1d11ab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487560696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2487560696
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3093199317
Short name T30
Test name
Test status
Simulation time 1230758383 ps
CPU time 5.9 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:31 PM PDT 24
Peak memory 217368 kb
Host smart-0aaf9d38-217f-47f7-bd4c-b4b22a3301ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093199317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3093199317
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.539916805
Short name T517
Test name
Test status
Simulation time 244828931 ps
CPU time 1.12 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:31 PM PDT 24
Peak memory 217384 kb
Host smart-2f00403e-f8e2-484b-9c78-9bf2f5e3b44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539916805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.539916805
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.921416549
Short name T339
Test name
Test status
Simulation time 199493280 ps
CPU time 0.94 seconds
Started Jul 01 04:41:23 PM PDT 24
Finished Jul 01 04:41:32 PM PDT 24
Peak memory 199960 kb
Host smart-db67386e-8920-41a3-a87d-36fe4669bb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921416549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.921416549
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.323897694
Short name T458
Test name
Test status
Simulation time 1362543579 ps
CPU time 5.19 seconds
Started Jul 01 04:41:23 PM PDT 24
Finished Jul 01 04:41:36 PM PDT 24
Peak memory 200284 kb
Host smart-e022025f-a709-4ea2-a24c-95bf5c105cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323897694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.323897694
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1352789753
Short name T186
Test name
Test status
Simulation time 111039437 ps
CPU time 1.05 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:25 PM PDT 24
Peak memory 200028 kb
Host smart-fe1270e1-bc7a-4351-892e-1b202647cb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352789753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1352789753
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3375048811
Short name T269
Test name
Test status
Simulation time 121571160 ps
CPU time 1.21 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:24 PM PDT 24
Peak memory 200264 kb
Host smart-f643582e-3e99-46f3-bfa4-d2e93c0e5177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375048811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3375048811
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2205273585
Short name T121
Test name
Test status
Simulation time 10079371010 ps
CPU time 34.72 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:42:02 PM PDT 24
Peak memory 208544 kb
Host smart-7c27d9f0-f11f-411d-ba90-536d5616f07f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205273585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2205273585
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2535036173
Short name T297
Test name
Test status
Simulation time 154373368 ps
CPU time 2.02 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:27 PM PDT 24
Peak memory 200228 kb
Host smart-9daa4d48-ceb0-4e2d-b402-e75202282c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535036173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2535036173
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3391226823
Short name T276
Test name
Test status
Simulation time 79317881 ps
CPU time 0.83 seconds
Started Jul 01 04:41:24 PM PDT 24
Finished Jul 01 04:41:33 PM PDT 24
Peak memory 200036 kb
Host smart-ebd583f4-55db-46d2-8da0-1e72952095a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391226823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3391226823
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1069187915
Short name T48
Test name
Test status
Simulation time 75319697 ps
CPU time 0.84 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:30 PM PDT 24
Peak memory 199816 kb
Host smart-3df66463-31fe-4382-b29e-19f884ab7b5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069187915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1069187915
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1819931618
Short name T332
Test name
Test status
Simulation time 1887053444 ps
CPU time 6.72 seconds
Started Jul 01 04:41:22 PM PDT 24
Finished Jul 01 04:41:37 PM PDT 24
Peak memory 229628 kb
Host smart-7ceba4dc-3e13-4b57-9ab5-e63e1ce93996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819931618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1819931618
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.734026832
Short name T197
Test name
Test status
Simulation time 245824149 ps
CPU time 1.01 seconds
Started Jul 01 04:41:23 PM PDT 24
Finished Jul 01 04:41:32 PM PDT 24
Peak memory 217364 kb
Host smart-e52d877f-628f-4ff6-bc43-2e03ccd8ab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734026832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.734026832
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1558941235
Short name T412
Test name
Test status
Simulation time 90281883 ps
CPU time 0.79 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:25 PM PDT 24
Peak memory 199936 kb
Host smart-6f4b69f1-b235-4b45-b84e-9d04c5e94bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558941235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1558941235
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2752490245
Short name T275
Test name
Test status
Simulation time 1350747578 ps
CPU time 5.24 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:33 PM PDT 24
Peak memory 200336 kb
Host smart-cb90842c-c2eb-486c-80a6-8829f2fc6d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752490245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2752490245
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1968880978
Short name T383
Test name
Test status
Simulation time 98033373 ps
CPU time 0.98 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:28 PM PDT 24
Peak memory 200032 kb
Host smart-d02322bb-13d3-4122-9cfa-7f145401d0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968880978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1968880978
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4125071849
Short name T527
Test name
Test status
Simulation time 108446851 ps
CPU time 1.13 seconds
Started Jul 01 04:41:24 PM PDT 24
Finished Jul 01 04:41:34 PM PDT 24
Peak memory 200220 kb
Host smart-ecc03e28-3e70-41b3-ae4d-8570d9df2606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125071849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4125071849
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2573387290
Short name T471
Test name
Test status
Simulation time 2721768862 ps
CPU time 12.8 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:41 PM PDT 24
Peak memory 200340 kb
Host smart-f0fab4c3-e55b-4419-b558-be7fdd8c352e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573387290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2573387290
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1850814692
Short name T317
Test name
Test status
Simulation time 318860346 ps
CPU time 1.87 seconds
Started Jul 01 04:41:23 PM PDT 24
Finished Jul 01 04:41:33 PM PDT 24
Peak memory 200032 kb
Host smart-c3e2376e-359d-481d-91f1-d5721896998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850814692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1850814692
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2317664322
Short name T352
Test name
Test status
Simulation time 92040363 ps
CPU time 0.86 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:28 PM PDT 24
Peak memory 200036 kb
Host smart-bba18e1d-9a41-4fd7-9baa-81ff92adeada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317664322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2317664322
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1595188092
Short name T418
Test name
Test status
Simulation time 74987007 ps
CPU time 0.77 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:23 PM PDT 24
Peak memory 199744 kb
Host smart-650a552a-adfe-44f1-8642-c180be9473b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595188092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1595188092
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1508528997
Short name T525
Test name
Test status
Simulation time 1226341345 ps
CPU time 5.49 seconds
Started Jul 01 04:41:18 PM PDT 24
Finished Jul 01 04:41:27 PM PDT 24
Peak memory 217616 kb
Host smart-c2f7298c-86d2-49c4-ae94-0287e32b5da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508528997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1508528997
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.724732080
Short name T156
Test name
Test status
Simulation time 244078423 ps
CPU time 1.17 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:30 PM PDT 24
Peak memory 217400 kb
Host smart-f0c76d2a-8bd4-4f21-ad47-e48ec4ff5ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724732080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.724732080
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2532634102
Short name T24
Test name
Test status
Simulation time 117605582 ps
CPU time 0.79 seconds
Started Jul 01 04:41:21 PM PDT 24
Finished Jul 01 04:41:30 PM PDT 24
Peak memory 199720 kb
Host smart-a91fe4d0-ee28-49ec-8a72-991cecd2ab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532634102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2532634102
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.669685263
Short name T298
Test name
Test status
Simulation time 1650707617 ps
CPU time 7.17 seconds
Started Jul 01 04:41:24 PM PDT 24
Finished Jul 01 04:41:40 PM PDT 24
Peak memory 200284 kb
Host smart-1b36458a-6fa1-49fb-9345-0c6cb5415603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669685263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.669685263
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3273789366
Short name T303
Test name
Test status
Simulation time 157413659 ps
CPU time 1.1 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:26 PM PDT 24
Peak memory 200016 kb
Host smart-cbe52119-0ce6-4dbb-87d0-bebf84ac61e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273789366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3273789366
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2245190092
Short name T284
Test name
Test status
Simulation time 250401200 ps
CPU time 1.48 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:28 PM PDT 24
Peak memory 200212 kb
Host smart-ce302280-f411-4b9c-85e2-4a9c5bc2560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245190092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2245190092
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1211987609
Short name T402
Test name
Test status
Simulation time 404493039 ps
CPU time 2.32 seconds
Started Jul 01 04:41:19 PM PDT 24
Finished Jul 01 04:41:27 PM PDT 24
Peak memory 199928 kb
Host smart-85a38341-6811-4120-b3ea-ab3f2c800ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211987609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1211987609
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4014888258
Short name T466
Test name
Test status
Simulation time 215942051 ps
CPU time 1.3 seconds
Started Jul 01 04:41:23 PM PDT 24
Finished Jul 01 04:41:33 PM PDT 24
Peak memory 200140 kb
Host smart-648428fc-fa02-4cc6-bfee-ea946dcbb22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014888258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4014888258
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3544623272
Short name T274
Test name
Test status
Simulation time 67036005 ps
CPU time 0.78 seconds
Started Jul 01 04:41:26 PM PDT 24
Finished Jul 01 04:41:36 PM PDT 24
Peak memory 199924 kb
Host smart-653de563-e4c2-48c3-b1c8-180f7190fb08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544623272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3544623272
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3017372902
Short name T313
Test name
Test status
Simulation time 1888796620 ps
CPU time 7 seconds
Started Jul 01 04:41:29 PM PDT 24
Finished Jul 01 04:41:46 PM PDT 24
Peak memory 217656 kb
Host smart-227a8d2b-2dc2-4f20-bc02-1aea1358eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017372902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3017372902
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.454129355
Short name T349
Test name
Test status
Simulation time 243704079 ps
CPU time 1.14 seconds
Started Jul 01 04:41:29 PM PDT 24
Finished Jul 01 04:41:40 PM PDT 24
Peak memory 217380 kb
Host smart-c4a64681-c2bb-44bd-8fc4-4e76be690f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454129355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.454129355
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3427474394
Short name T438
Test name
Test status
Simulation time 192867928 ps
CPU time 0.86 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:28 PM PDT 24
Peak memory 199844 kb
Host smart-7c36a884-388a-4d9b-88d6-7c583d58fe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427474394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3427474394
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3051882496
Short name T122
Test name
Test status
Simulation time 2041705801 ps
CPU time 7.18 seconds
Started Jul 01 04:41:20 PM PDT 24
Finished Jul 01 04:41:34 PM PDT 24
Peak memory 200240 kb
Host smart-dc5f3159-83ac-427e-91a1-8ad00c01f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051882496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3051882496
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3772198063
Short name T239
Test name
Test status
Simulation time 95415072 ps
CPU time 1.05 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:38 PM PDT 24
Peak memory 200100 kb
Host smart-204e8d31-b52f-4946-bd93-43f3382e6712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772198063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3772198063
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.174163779
Short name T299
Test name
Test status
Simulation time 113364638 ps
CPU time 1.19 seconds
Started Jul 01 04:41:22 PM PDT 24
Finished Jul 01 04:41:32 PM PDT 24
Peak memory 200264 kb
Host smart-851d2165-94f8-40f1-a487-129e2a120c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174163779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.174163779
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3811433672
Short name T376
Test name
Test status
Simulation time 4882411725 ps
CPU time 18.05 seconds
Started Jul 01 04:41:27 PM PDT 24
Finished Jul 01 04:41:54 PM PDT 24
Peak memory 200352 kb
Host smart-da410ad0-944f-4653-a7bc-ac20ad423fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811433672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3811433672
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.468405234
Short name T397
Test name
Test status
Simulation time 519943209 ps
CPU time 2.87 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:40 PM PDT 24
Peak memory 200028 kb
Host smart-d1c4e4de-8821-46a8-950b-411b83641a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468405234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.468405234
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2277914658
Short name T181
Test name
Test status
Simulation time 141119903 ps
CPU time 1.08 seconds
Started Jul 01 04:41:24 PM PDT 24
Finished Jul 01 04:41:34 PM PDT 24
Peak memory 200036 kb
Host smart-8b838ef4-e81c-4fb1-90bc-761d30332af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277914658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2277914658
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1864663071
Short name T271
Test name
Test status
Simulation time 74653489 ps
CPU time 0.76 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:38 PM PDT 24
Peak memory 199824 kb
Host smart-cbde27c7-ce26-4cbf-81fa-9ff2381c529c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864663071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1864663071
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2247135362
Short name T7
Test name
Test status
Simulation time 1220586777 ps
CPU time 5.54 seconds
Started Jul 01 04:41:27 PM PDT 24
Finished Jul 01 04:41:41 PM PDT 24
Peak memory 217608 kb
Host smart-157bf6fd-46f6-4282-83a8-46b7b15a61c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247135362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2247135362
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3619815878
Short name T6
Test name
Test status
Simulation time 244623351 ps
CPU time 1.11 seconds
Started Jul 01 04:41:25 PM PDT 24
Finished Jul 01 04:41:35 PM PDT 24
Peak memory 217396 kb
Host smart-0e19b079-28fb-43ed-ae93-e7fa6a565bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619815878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3619815878
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.211123868
Short name T19
Test name
Test status
Simulation time 83027171 ps
CPU time 0.71 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:38 PM PDT 24
Peak memory 199848 kb
Host smart-901b0421-3f86-4a8e-a75d-230a6c9c6c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211123868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.211123868
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2048989419
Short name T257
Test name
Test status
Simulation time 1401210046 ps
CPU time 5.86 seconds
Started Jul 01 04:41:29 PM PDT 24
Finished Jul 01 04:41:44 PM PDT 24
Peak memory 200184 kb
Host smart-d08f3f00-fd18-4c8e-8a8b-abccb41d183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048989419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2048989419
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.928572460
Short name T173
Test name
Test status
Simulation time 100105706 ps
CPU time 0.97 seconds
Started Jul 01 04:41:26 PM PDT 24
Finished Jul 01 04:41:36 PM PDT 24
Peak memory 199988 kb
Host smart-017bfc7b-7a52-41c1-a5de-f02ed75e4949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928572460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.928572460
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3452523796
Short name T139
Test name
Test status
Simulation time 117747781 ps
CPU time 1.18 seconds
Started Jul 01 04:41:29 PM PDT 24
Finished Jul 01 04:41:39 PM PDT 24
Peak memory 200220 kb
Host smart-4e6743e2-61fe-4cbb-bc48-c4981365dc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452523796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3452523796
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1403936542
Short name T213
Test name
Test status
Simulation time 5964193707 ps
CPU time 19.58 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:57 PM PDT 24
Peak memory 200392 kb
Host smart-31295771-4f87-457e-9f6a-6f42aa96c0bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403936542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1403936542
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4048171136
Short name T420
Test name
Test status
Simulation time 206748931 ps
CPU time 1.41 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:38 PM PDT 24
Peak memory 200252 kb
Host smart-c0a7c7a7-0e4e-4b82-9f32-8af13a99aff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048171136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4048171136
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3526200769
Short name T147
Test name
Test status
Simulation time 79996661 ps
CPU time 0.8 seconds
Started Jul 01 04:40:54 PM PDT 24
Finished Jul 01 04:40:58 PM PDT 24
Peak memory 199776 kb
Host smart-b1915a48-70b1-43b2-873e-89e01f9f4ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526200769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3526200769
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3077928302
Short name T316
Test name
Test status
Simulation time 1215868219 ps
CPU time 5.8 seconds
Started Jul 01 04:40:56 PM PDT 24
Finished Jul 01 04:41:05 PM PDT 24
Peak memory 216736 kb
Host smart-a28017b2-68fc-4113-8aff-390cb7cc1b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077928302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3077928302
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.77230834
Short name T180
Test name
Test status
Simulation time 243900196 ps
CPU time 1.12 seconds
Started Jul 01 04:40:51 PM PDT 24
Finished Jul 01 04:40:55 PM PDT 24
Peak memory 217396 kb
Host smart-736ab93d-1932-4368-8328-648d1475f75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77230834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.77230834
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3708478529
Short name T503
Test name
Test status
Simulation time 121870959 ps
CPU time 0.86 seconds
Started Jul 01 04:40:52 PM PDT 24
Finished Jul 01 04:40:55 PM PDT 24
Peak memory 199844 kb
Host smart-64577981-3f9d-473c-bd64-2005febeb098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708478529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3708478529
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2806249360
Short name T414
Test name
Test status
Simulation time 1681678716 ps
CPU time 6.74 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:41:04 PM PDT 24
Peak memory 200532 kb
Host smart-707d49f6-b845-4444-82a1-34ffe245b4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806249360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2806249360
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3069726838
Short name T72
Test name
Test status
Simulation time 8468723038 ps
CPU time 12.61 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:41:09 PM PDT 24
Peak memory 217056 kb
Host smart-5ee92bc0-f913-4985-aff6-f6e9cb02cbdc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069726838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3069726838
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3946600278
Short name T304
Test name
Test status
Simulation time 104029162 ps
CPU time 1.07 seconds
Started Jul 01 04:40:54 PM PDT 24
Finished Jul 01 04:40:59 PM PDT 24
Peak memory 200032 kb
Host smart-a078bc8e-4b1f-4180-bc34-ab4272308e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946600278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3946600278
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3520925663
Short name T342
Test name
Test status
Simulation time 205035690 ps
CPU time 1.38 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:40:58 PM PDT 24
Peak memory 200220 kb
Host smart-6cb9f1a6-dc67-40cb-846c-146ad5f2b1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520925663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3520925663
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2856851923
Short name T235
Test name
Test status
Simulation time 6013418025 ps
CPU time 25.81 seconds
Started Jul 01 04:40:54 PM PDT 24
Finished Jul 01 04:41:23 PM PDT 24
Peak memory 208496 kb
Host smart-5f2a663e-0e8b-4705-a645-14053453601f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856851923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2856851923
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.522361896
Short name T455
Test name
Test status
Simulation time 393997365 ps
CPU time 2.41 seconds
Started Jul 01 04:40:54 PM PDT 24
Finished Jul 01 04:41:00 PM PDT 24
Peak memory 200092 kb
Host smart-86c57bc2-c2b4-4369-b839-352b870f60a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522361896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.522361896
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1659340502
Short name T1
Test name
Test status
Simulation time 107938731 ps
CPU time 1.02 seconds
Started Jul 01 04:40:52 PM PDT 24
Finished Jul 01 04:40:56 PM PDT 24
Peak memory 200028 kb
Host smart-1d306737-b9ca-4a27-a3c4-42bd999df654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659340502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1659340502
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2398765275
Short name T512
Test name
Test status
Simulation time 92326908 ps
CPU time 0.81 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:42 PM PDT 24
Peak memory 199712 kb
Host smart-427a44c3-114b-403a-857f-19ed4d302d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398765275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2398765275
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3274939112
Short name T40
Test name
Test status
Simulation time 1882594540 ps
CPU time 6.72 seconds
Started Jul 01 04:41:31 PM PDT 24
Finished Jul 01 04:41:47 PM PDT 24
Peak memory 216792 kb
Host smart-979ee3f4-8022-4946-9146-134b849c7d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274939112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3274939112
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1590775393
Short name T439
Test name
Test status
Simulation time 243958770 ps
CPU time 1.05 seconds
Started Jul 01 04:41:31 PM PDT 24
Finished Jul 01 04:41:41 PM PDT 24
Peak memory 217392 kb
Host smart-a7aedae6-30f8-473b-8c53-8baa2c83af3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590775393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1590775393
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1336109616
Short name T386
Test name
Test status
Simulation time 206539412 ps
CPU time 1.04 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:39 PM PDT 24
Peak memory 199952 kb
Host smart-dbc46e87-46ef-475a-93fc-dc281c0a7ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336109616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1336109616
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1212928185
Short name T347
Test name
Test status
Simulation time 1032948894 ps
CPU time 5.09 seconds
Started Jul 01 04:41:29 PM PDT 24
Finished Jul 01 04:41:44 PM PDT 24
Peak memory 200360 kb
Host smart-23017074-b95d-4c3b-9e28-90209ac0f4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212928185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1212928185
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.371170342
Short name T241
Test name
Test status
Simulation time 108147123 ps
CPU time 1.01 seconds
Started Jul 01 04:41:31 PM PDT 24
Finished Jul 01 04:41:41 PM PDT 24
Peak memory 199884 kb
Host smart-7aebb064-b99b-4a71-9758-76e98f8b8f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371170342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.371170342
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.453203340
Short name T222
Test name
Test status
Simulation time 110998055 ps
CPU time 1.22 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:42 PM PDT 24
Peak memory 200220 kb
Host smart-304ab09c-053e-4860-9fe3-658ec4f4cd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453203340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.453203340
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.998913392
Short name T11
Test name
Test status
Simulation time 5441359508 ps
CPU time 18.61 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:59 PM PDT 24
Peak memory 209672 kb
Host smart-9fdfd7c4-e262-4890-b751-5d4cb3e79e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998913392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.998913392
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2897911140
Short name T219
Test name
Test status
Simulation time 155700125 ps
CPU time 1.86 seconds
Started Jul 01 04:41:29 PM PDT 24
Finished Jul 01 04:41:40 PM PDT 24
Peak memory 200024 kb
Host smart-b079042c-57ff-42d3-a3f1-c8aa8b9b6c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897911140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2897911140
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1378782719
Short name T415
Test name
Test status
Simulation time 224569076 ps
CPU time 1.33 seconds
Started Jul 01 04:41:27 PM PDT 24
Finished Jul 01 04:41:37 PM PDT 24
Peak memory 200040 kb
Host smart-8be780ce-a4cc-475d-aef8-70ff81d90c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378782719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1378782719
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1682264955
Short name T490
Test name
Test status
Simulation time 95288462 ps
CPU time 0.84 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:38 PM PDT 24
Peak memory 199804 kb
Host smart-e30c0448-9fc1-44c5-a8ca-ae6e7eab7e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682264955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1682264955
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3379258896
Short name T29
Test name
Test status
Simulation time 2365041093 ps
CPU time 8.7 seconds
Started Jul 01 04:41:29 PM PDT 24
Finished Jul 01 04:41:47 PM PDT 24
Peak memory 221552 kb
Host smart-aa51393a-b598-4d69-a68b-c8048daeca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379258896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3379258896
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.639165406
Short name T182
Test name
Test status
Simulation time 243332806 ps
CPU time 1.11 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:39 PM PDT 24
Peak memory 217376 kb
Host smart-1f243796-d18f-4239-8aec-77ac98f6c655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639165406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.639165406
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3167193480
Short name T22
Test name
Test status
Simulation time 205441416 ps
CPU time 0.9 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:39 PM PDT 24
Peak memory 199844 kb
Host smart-7d9c752d-be27-42fe-8f13-6d0c744b2fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167193480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3167193480
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2400182134
Short name T94
Test name
Test status
Simulation time 912129634 ps
CPU time 4.38 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:41 PM PDT 24
Peak memory 200336 kb
Host smart-33cf314f-1bfb-4ec6-adee-c171041fcf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400182134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2400182134
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2715445082
Short name T478
Test name
Test status
Simulation time 153538737 ps
CPU time 1.11 seconds
Started Jul 01 04:41:29 PM PDT 24
Finished Jul 01 04:41:40 PM PDT 24
Peak memory 200032 kb
Host smart-32e53836-6e63-4f57-8f75-051cb035e2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715445082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2715445082
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3146968396
Short name T220
Test name
Test status
Simulation time 204198742 ps
CPU time 1.38 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:42 PM PDT 24
Peak memory 200208 kb
Host smart-ccfe535e-2521-4538-880c-ce5f6e1537bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146968396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3146968396
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.955490294
Short name T364
Test name
Test status
Simulation time 10352495278 ps
CPU time 33.09 seconds
Started Jul 01 04:41:30 PM PDT 24
Finished Jul 01 04:42:12 PM PDT 24
Peak memory 200256 kb
Host smart-eb8652ed-95fa-4134-aed6-eacb75e6fc3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955490294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.955490294
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3130650991
Short name T457
Test name
Test status
Simulation time 147121756 ps
CPU time 1.78 seconds
Started Jul 01 04:41:30 PM PDT 24
Finished Jul 01 04:41:41 PM PDT 24
Peak memory 200100 kb
Host smart-5065828b-7fc2-4c7f-aae5-f90010b4a4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130650991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3130650991
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2449880697
Short name T26
Test name
Test status
Simulation time 69120146 ps
CPU time 0.76 seconds
Started Jul 01 04:41:27 PM PDT 24
Finished Jul 01 04:41:37 PM PDT 24
Peak memory 200040 kb
Host smart-cde5d7df-c992-40a1-84b1-8a601e911409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449880697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2449880697
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3505607092
Short name T379
Test name
Test status
Simulation time 74453428 ps
CPU time 0.77 seconds
Started Jul 01 04:41:35 PM PDT 24
Finished Jul 01 04:41:45 PM PDT 24
Peak memory 199928 kb
Host smart-d8d213ce-c2b3-4a6b-be19-af9bd298a512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505607092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3505607092
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3137785847
Short name T125
Test name
Test status
Simulation time 1220712134 ps
CPU time 5.78 seconds
Started Jul 01 04:41:36 PM PDT 24
Finished Jul 01 04:41:51 PM PDT 24
Peak memory 217476 kb
Host smart-61b08ad7-3e28-4db8-973d-91d968314862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137785847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3137785847
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3951360632
Short name T334
Test name
Test status
Simulation time 244206987 ps
CPU time 1.09 seconds
Started Jul 01 04:41:33 PM PDT 24
Finished Jul 01 04:41:42 PM PDT 24
Peak memory 217276 kb
Host smart-0a0059f6-90b9-4aa0-9c4a-a387f72802e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951360632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3951360632
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3487721295
Short name T25
Test name
Test status
Simulation time 158120337 ps
CPU time 0.85 seconds
Started Jul 01 04:41:30 PM PDT 24
Finished Jul 01 04:41:40 PM PDT 24
Peak memory 199836 kb
Host smart-6c291426-596e-482d-ab1a-b4ab74c1e715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487721295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3487721295
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2103304626
Short name T497
Test name
Test status
Simulation time 1445425183 ps
CPU time 6.09 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:44 PM PDT 24
Peak memory 200204 kb
Host smart-44d5d1c7-14c9-47d3-99f6-7c8e0621cb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103304626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2103304626
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1997761182
Short name T46
Test name
Test status
Simulation time 100535940 ps
CPU time 1.01 seconds
Started Jul 01 04:41:35 PM PDT 24
Finished Jul 01 04:41:45 PM PDT 24
Peak memory 200124 kb
Host smart-fca7be23-bd1c-4381-92c8-48b76edd4315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997761182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1997761182
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1958622060
Short name T278
Test name
Test status
Simulation time 252123078 ps
CPU time 1.52 seconds
Started Jul 01 04:41:33 PM PDT 24
Finished Jul 01 04:41:43 PM PDT 24
Peak memory 200168 kb
Host smart-97fd741d-42a2-4b2d-98f0-0cc9d6ea73bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958622060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1958622060
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1602516202
Short name T445
Test name
Test status
Simulation time 10942668466 ps
CPU time 39.04 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:42:28 PM PDT 24
Peak memory 200268 kb
Host smart-ed538e18-5e68-4f87-9e3c-f1b888170047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602516202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1602516202
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2790904130
Short name T467
Test name
Test status
Simulation time 404532833 ps
CPU time 2.4 seconds
Started Jul 01 04:41:31 PM PDT 24
Finished Jul 01 04:41:43 PM PDT 24
Peak memory 208168 kb
Host smart-e1234227-0da9-4564-93ea-caf6541058cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790904130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2790904130
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1964410816
Short name T199
Test name
Test status
Simulation time 154734469 ps
CPU time 1.31 seconds
Started Jul 01 04:41:33 PM PDT 24
Finished Jul 01 04:41:43 PM PDT 24
Peak memory 200232 kb
Host smart-af94bc0f-dda4-4d67-87cf-b71535460f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964410816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1964410816
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.818921050
Short name T516
Test name
Test status
Simulation time 73954179 ps
CPU time 0.77 seconds
Started Jul 01 04:41:36 PM PDT 24
Finished Jul 01 04:41:47 PM PDT 24
Peak memory 199796 kb
Host smart-06989d54-1d8d-4cf5-8def-87931ae3d4b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818921050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.818921050
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1927943919
Short name T519
Test name
Test status
Simulation time 1218213688 ps
CPU time 5.86 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:47 PM PDT 24
Peak memory 217608 kb
Host smart-55fc2488-3226-4272-908e-824f2be3b4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927943919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1927943919
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2164374105
Short name T201
Test name
Test status
Simulation time 244941845 ps
CPU time 1.1 seconds
Started Jul 01 04:41:30 PM PDT 24
Finished Jul 01 04:41:41 PM PDT 24
Peak memory 217504 kb
Host smart-1d44d7e3-b43c-4f2f-a3dc-869423040c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164374105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2164374105
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2895806799
Short name T240
Test name
Test status
Simulation time 152356180 ps
CPU time 0.89 seconds
Started Jul 01 04:41:28 PM PDT 24
Finished Jul 01 04:41:38 PM PDT 24
Peak memory 199844 kb
Host smart-8e145eb3-7de2-4256-afff-7f0aa9fcc92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895806799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2895806799
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.809611469
Short name T413
Test name
Test status
Simulation time 1884424615 ps
CPU time 7.58 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:57 PM PDT 24
Peak memory 200152 kb
Host smart-c0344aae-de73-44db-b6b7-1ff0aa51cefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809611469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.809611469
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2937744586
Short name T367
Test name
Test status
Simulation time 111480996 ps
CPU time 1 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:42 PM PDT 24
Peak memory 200032 kb
Host smart-cf456879-cdfd-4de3-91bd-b0aca5c850f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937744586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2937744586
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3542811725
Short name T499
Test name
Test status
Simulation time 418706726 ps
CPU time 2.24 seconds
Started Jul 01 04:41:35 PM PDT 24
Finished Jul 01 04:41:47 PM PDT 24
Peak memory 208344 kb
Host smart-7adc4974-d6e0-4ae5-9478-d2b7fe13f04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542811725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3542811725
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1488387510
Short name T253
Test name
Test status
Simulation time 184152104 ps
CPU time 1.23 seconds
Started Jul 01 04:41:35 PM PDT 24
Finished Jul 01 04:41:46 PM PDT 24
Peak memory 200128 kb
Host smart-7aa2e291-3c48-4e53-874a-935f35299935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488387510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1488387510
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3981149001
Short name T225
Test name
Test status
Simulation time 63951276 ps
CPU time 0.78 seconds
Started Jul 01 04:41:34 PM PDT 24
Finished Jul 01 04:41:44 PM PDT 24
Peak memory 199712 kb
Host smart-d2c0b745-dfdc-4e4a-a827-a1b1cb5cb59c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981149001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3981149001
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.4135847698
Short name T325
Test name
Test status
Simulation time 2171246925 ps
CPU time 8.23 seconds
Started Jul 01 04:41:39 PM PDT 24
Finished Jul 01 04:41:56 PM PDT 24
Peak memory 217636 kb
Host smart-3d449303-d014-4097-a82b-53aeab7a5840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135847698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.4135847698
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3958608659
Short name T198
Test name
Test status
Simulation time 244065126 ps
CPU time 1.06 seconds
Started Jul 01 04:41:34 PM PDT 24
Finished Jul 01 04:41:44 PM PDT 24
Peak memory 217328 kb
Host smart-cc2d89f3-7547-45c2-b5b0-12d7e0607a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958608659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3958608659
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3353923334
Short name T531
Test name
Test status
Simulation time 141159414 ps
CPU time 0.83 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:42 PM PDT 24
Peak memory 199832 kb
Host smart-53b73997-4fe4-4c38-a8f0-1a49f8669a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353923334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3353923334
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.734547579
Short name T507
Test name
Test status
Simulation time 1696386344 ps
CPU time 6.61 seconds
Started Jul 01 04:41:37 PM PDT 24
Finished Jul 01 04:41:53 PM PDT 24
Peak memory 200232 kb
Host smart-81a582ec-1e2c-45ce-821c-0307188af381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734547579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.734547579
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3921160162
Short name T183
Test name
Test status
Simulation time 175903308 ps
CPU time 1.17 seconds
Started Jul 01 04:41:38 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 200028 kb
Host smart-773dad65-ba94-4b93-8a9b-bb575e141bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921160162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3921160162
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1402528451
Short name T78
Test name
Test status
Simulation time 200782880 ps
CPU time 1.32 seconds
Started Jul 01 04:41:40 PM PDT 24
Finished Jul 01 04:41:50 PM PDT 24
Peak memory 200140 kb
Host smart-f50fa508-6d80-4442-a667-d140cdb8bdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402528451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1402528451
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3216629044
Short name T485
Test name
Test status
Simulation time 3029254485 ps
CPU time 13.15 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:54 PM PDT 24
Peak memory 200428 kb
Host smart-24465c49-3517-4797-87f0-fe5eba763627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216629044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3216629044
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2114487259
Short name T243
Test name
Test status
Simulation time 416655408 ps
CPU time 2.59 seconds
Started Jul 01 04:41:31 PM PDT 24
Finished Jul 01 04:41:43 PM PDT 24
Peak memory 208220 kb
Host smart-2f234a03-2ead-47db-bb74-cb833ad78eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114487259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2114487259
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3744084310
Short name T356
Test name
Test status
Simulation time 75984827 ps
CPU time 0.81 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:42 PM PDT 24
Peak memory 200036 kb
Host smart-1b6c891b-7e6e-4b0b-b082-cc35c4b9234b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744084310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3744084310
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3747121079
Short name T242
Test name
Test status
Simulation time 59915284 ps
CPU time 0.69 seconds
Started Jul 01 04:41:40 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 199744 kb
Host smart-d065ed07-d0a8-4170-87a8-1cc1588970e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747121079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3747121079
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2339255892
Short name T27
Test name
Test status
Simulation time 2356624576 ps
CPU time 8.1 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 221632 kb
Host smart-fa4c5a33-9768-4220-b69b-0da4cd275fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339255892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2339255892
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3205355983
Short name T452
Test name
Test status
Simulation time 244996819 ps
CPU time 1.04 seconds
Started Jul 01 04:41:34 PM PDT 24
Finished Jul 01 04:41:44 PM PDT 24
Peak memory 217368 kb
Host smart-3e9fe8fc-8195-4c64-9698-0e88a7c18418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205355983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3205355983
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2225972055
Short name T495
Test name
Test status
Simulation time 172457260 ps
CPU time 0.84 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:50 PM PDT 24
Peak memory 199672 kb
Host smart-92dcea1e-4637-453f-8bb4-4013db1f2c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225972055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2225972055
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1687129692
Short name T443
Test name
Test status
Simulation time 1441547287 ps
CPU time 5.52 seconds
Started Jul 01 04:41:35 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 200140 kb
Host smart-f64d1a00-346c-4aec-a179-9e60946ebcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687129692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1687129692
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1248557054
Short name T450
Test name
Test status
Simulation time 104815689 ps
CPU time 0.98 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:51 PM PDT 24
Peak memory 199948 kb
Host smart-888b7caf-8d2c-495f-ba7f-311354cc4835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248557054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1248557054
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2224518237
Short name T521
Test name
Test status
Simulation time 116904415 ps
CPU time 1.14 seconds
Started Jul 01 04:41:31 PM PDT 24
Finished Jul 01 04:41:42 PM PDT 24
Peak memory 200260 kb
Host smart-f52eb837-229c-403f-a739-bf54f0fedfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224518237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2224518237
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3526645928
Short name T435
Test name
Test status
Simulation time 266786498 ps
CPU time 2.01 seconds
Started Jul 01 04:41:38 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 200260 kb
Host smart-142ce8f7-2379-4770-b558-25e1a3c72045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526645928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3526645928
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.947626750
Short name T487
Test name
Test status
Simulation time 378446208 ps
CPU time 1.95 seconds
Started Jul 01 04:41:33 PM PDT 24
Finished Jul 01 04:41:43 PM PDT 24
Peak memory 200024 kb
Host smart-39583a3b-a8ab-404f-8784-b027061f9b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947626750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.947626750
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1909866979
Short name T355
Test name
Test status
Simulation time 129278069 ps
CPU time 1.24 seconds
Started Jul 01 04:41:33 PM PDT 24
Finished Jul 01 04:41:43 PM PDT 24
Peak memory 200036 kb
Host smart-565435c5-b789-4d92-917e-2ae4d16c2fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909866979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1909866979
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1766234391
Short name T130
Test name
Test status
Simulation time 72984293 ps
CPU time 0.8 seconds
Started Jul 01 04:41:37 PM PDT 24
Finished Jul 01 04:41:47 PM PDT 24
Peak memory 199780 kb
Host smart-8caf6429-b2c1-42d9-8148-f4dc755d178a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766234391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1766234391
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.603554955
Short name T494
Test name
Test status
Simulation time 2352805079 ps
CPU time 8.8 seconds
Started Jul 01 04:41:36 PM PDT 24
Finished Jul 01 04:41:54 PM PDT 24
Peak memory 217660 kb
Host smart-44632d9c-413c-4b3f-87f1-a21ed3e7579b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603554955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.603554955
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.656561433
Short name T328
Test name
Test status
Simulation time 243440760 ps
CPU time 1.16 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:42 PM PDT 24
Peak memory 217424 kb
Host smart-939f2f94-6256-45dc-9406-260808c1df42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656561433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.656561433
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3462538860
Short name T343
Test name
Test status
Simulation time 166490064 ps
CPU time 0.92 seconds
Started Jul 01 04:41:31 PM PDT 24
Finished Jul 01 04:41:41 PM PDT 24
Peak memory 199952 kb
Host smart-6f059d73-4ff2-4722-8bda-000eeef0b6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462538860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3462538860
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3887487050
Short name T330
Test name
Test status
Simulation time 914292724 ps
CPU time 4.42 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:45 PM PDT 24
Peak memory 200284 kb
Host smart-ab25a9d7-66e5-47a4-aad1-64c4450a1567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887487050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3887487050
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1110662986
Short name T155
Test name
Test status
Simulation time 100492468 ps
CPU time 0.97 seconds
Started Jul 01 04:41:37 PM PDT 24
Finished Jul 01 04:41:47 PM PDT 24
Peak memory 199988 kb
Host smart-7c2bae9b-eb50-49f0-ae11-e32002fe6612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110662986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1110662986
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1780042030
Short name T326
Test name
Test status
Simulation time 190195754 ps
CPU time 1.27 seconds
Started Jul 01 04:41:40 PM PDT 24
Finished Jul 01 04:41:50 PM PDT 24
Peak memory 200136 kb
Host smart-faa952d9-8278-4986-8d34-08c92abe8327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780042030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1780042030
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3186776394
Short name T468
Test name
Test status
Simulation time 9235220223 ps
CPU time 28.99 seconds
Started Jul 01 04:41:36 PM PDT 24
Finished Jul 01 04:42:14 PM PDT 24
Peak memory 200208 kb
Host smart-1dd58ee1-dc72-410d-93c4-06b3ec3472b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186776394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3186776394
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3097830239
Short name T306
Test name
Test status
Simulation time 115856808 ps
CPU time 1.51 seconds
Started Jul 01 04:41:33 PM PDT 24
Finished Jul 01 04:41:43 PM PDT 24
Peak memory 200020 kb
Host smart-15ca62c5-87c4-4bfa-b3f2-1cd840efb019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097830239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3097830239
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.4234144286
Short name T153
Test name
Test status
Simulation time 64365844 ps
CPU time 0.72 seconds
Started Jul 01 04:41:35 PM PDT 24
Finished Jul 01 04:41:45 PM PDT 24
Peak memory 199892 kb
Host smart-637d6fd1-f3e7-4646-b718-18a76d31f8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234144286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.4234144286
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1060633417
Short name T377
Test name
Test status
Simulation time 86153569 ps
CPU time 0.8 seconds
Started Jul 01 04:41:40 PM PDT 24
Finished Jul 01 04:41:50 PM PDT 24
Peak memory 199832 kb
Host smart-ac4f0869-16a4-466a-b530-686659be7ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060633417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1060633417
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3708321099
Short name T38
Test name
Test status
Simulation time 1888009534 ps
CPU time 6.9 seconds
Started Jul 01 04:41:39 PM PDT 24
Finished Jul 01 04:41:55 PM PDT 24
Peak memory 217612 kb
Host smart-d95ad89d-7095-41bf-be6a-40a487e7199b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708321099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3708321099
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2776544990
Short name T132
Test name
Test status
Simulation time 245859156 ps
CPU time 1.11 seconds
Started Jul 01 04:41:39 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 217616 kb
Host smart-da604c5f-ecad-4b3a-8c22-18c2e9da7484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776544990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2776544990
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2307567179
Short name T5
Test name
Test status
Simulation time 198649508 ps
CPU time 0.92 seconds
Started Jul 01 04:41:39 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 199852 kb
Host smart-14aec555-c202-4c49-b947-402b41414b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307567179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2307567179
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.4008203676
Short name T300
Test name
Test status
Simulation time 1948294638 ps
CPU time 6.76 seconds
Started Jul 01 04:41:32 PM PDT 24
Finished Jul 01 04:41:48 PM PDT 24
Peak memory 200312 kb
Host smart-de2233af-c131-467d-9968-503770d12f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008203676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.4008203676
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1192848744
Short name T509
Test name
Test status
Simulation time 163066504 ps
CPU time 1.19 seconds
Started Jul 01 04:41:38 PM PDT 24
Finished Jul 01 04:41:48 PM PDT 24
Peak memory 200040 kb
Host smart-555c5ee0-3063-497d-9115-cc8ef7642e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192848744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1192848744
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2996139318
Short name T223
Test name
Test status
Simulation time 114987329 ps
CPU time 1.16 seconds
Started Jul 01 04:41:37 PM PDT 24
Finished Jul 01 04:41:48 PM PDT 24
Peak memory 200192 kb
Host smart-cdb6cf27-260f-444f-80f1-e8c7f2a57e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996139318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2996139318
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.114275468
Short name T216
Test name
Test status
Simulation time 5990455715 ps
CPU time 20.29 seconds
Started Jul 01 04:41:40 PM PDT 24
Finished Jul 01 04:42:09 PM PDT 24
Peak memory 208584 kb
Host smart-f55bb49d-9f69-456f-bb15-e5c2314bb587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114275468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.114275468
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1660156190
Short name T442
Test name
Test status
Simulation time 132243890 ps
CPU time 1.65 seconds
Started Jul 01 04:41:38 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 200020 kb
Host smart-78651ab5-629b-48c2-b83a-c59f7cd694c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660156190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1660156190
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2504352553
Short name T333
Test name
Test status
Simulation time 178406956 ps
CPU time 1.22 seconds
Started Jul 01 04:41:38 PM PDT 24
Finished Jul 01 04:41:48 PM PDT 24
Peak memory 200036 kb
Host smart-13a55b93-e7aa-4257-9a60-795625b714e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504352553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2504352553
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1235037235
Short name T195
Test name
Test status
Simulation time 74445274 ps
CPU time 0.78 seconds
Started Jul 01 04:41:44 PM PDT 24
Finished Jul 01 04:41:52 PM PDT 24
Peak memory 199832 kb
Host smart-a54e0326-a0bc-4887-b9ff-d55cbdf6ae2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235037235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1235037235
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2719463601
Short name T353
Test name
Test status
Simulation time 1876245213 ps
CPU time 7.05 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:57 PM PDT 24
Peak memory 221536 kb
Host smart-1baa6095-2852-4891-a0e6-8564fe0d30e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719463601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2719463601
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1870508103
Short name T358
Test name
Test status
Simulation time 244082460 ps
CPU time 1.08 seconds
Started Jul 01 04:41:42 PM PDT 24
Finished Jul 01 04:41:52 PM PDT 24
Peak memory 217400 kb
Host smart-365c0a77-89ba-42ea-81ae-01daf9e4dd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870508103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1870508103
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2625349053
Short name T417
Test name
Test status
Simulation time 180149701 ps
CPU time 0.86 seconds
Started Jul 01 04:41:39 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 199764 kb
Host smart-a059adec-e296-4c52-953b-f5c51248b573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625349053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2625349053
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3374414682
Short name T430
Test name
Test status
Simulation time 946918799 ps
CPU time 4.57 seconds
Started Jul 01 04:41:43 PM PDT 24
Finished Jul 01 04:41:55 PM PDT 24
Peak memory 200336 kb
Host smart-eaf99e6a-0db1-4d12-a462-009329199812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374414682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3374414682
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1112416554
Short name T138
Test name
Test status
Simulation time 108037553 ps
CPU time 1.1 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:51 PM PDT 24
Peak memory 200028 kb
Host smart-df92fda2-d393-446b-b495-06273e9a0c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112416554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1112416554
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3677595708
Short name T171
Test name
Test status
Simulation time 116485252 ps
CPU time 1.24 seconds
Started Jul 01 04:41:39 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 200216 kb
Host smart-619c4a2d-7d8f-4d34-a832-ea49c3be67cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677595708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3677595708
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3454570922
Short name T250
Test name
Test status
Simulation time 2750803248 ps
CPU time 13.31 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:42:03 PM PDT 24
Peak memory 200348 kb
Host smart-a9a05aa5-931e-41fa-8cfe-3cfd97115143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454570922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3454570922
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.773613583
Short name T372
Test name
Test status
Simulation time 394277640 ps
CPU time 2.12 seconds
Started Jul 01 04:41:47 PM PDT 24
Finished Jul 01 04:41:55 PM PDT 24
Peak memory 200028 kb
Host smart-4938677d-de09-4b99-aba7-5ca80f31f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773613583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.773613583
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1067310038
Short name T224
Test name
Test status
Simulation time 180398424 ps
CPU time 1.27 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:51 PM PDT 24
Peak memory 200240 kb
Host smart-927e72fa-c328-4c84-a7a7-c1b1907f5155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067310038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1067310038
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.476544434
Short name T187
Test name
Test status
Simulation time 71280321 ps
CPU time 0.78 seconds
Started Jul 01 04:41:49 PM PDT 24
Finished Jul 01 04:41:55 PM PDT 24
Peak memory 199832 kb
Host smart-17964146-d249-434f-b327-809f8ffabbf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476544434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.476544434
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.582130366
Short name T32
Test name
Test status
Simulation time 1895173915 ps
CPU time 7.21 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:57 PM PDT 24
Peak memory 221632 kb
Host smart-16a09f40-18b4-4e1b-a746-1431e29dba93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582130366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.582130366
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3853170450
Short name T161
Test name
Test status
Simulation time 243458156 ps
CPU time 1.15 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:51 PM PDT 24
Peak memory 217344 kb
Host smart-3dd4f864-a916-4e70-b6a3-2654e2f91335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853170450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3853170450
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2958005530
Short name T20
Test name
Test status
Simulation time 71496899 ps
CPU time 0.76 seconds
Started Jul 01 04:41:45 PM PDT 24
Finished Jul 01 04:41:52 PM PDT 24
Peak memory 199852 kb
Host smart-4697b379-db93-42ae-aa7d-472f7d05282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958005530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2958005530
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2822257307
Short name T472
Test name
Test status
Simulation time 1058112784 ps
CPU time 5.26 seconds
Started Jul 01 04:41:39 PM PDT 24
Finished Jul 01 04:41:53 PM PDT 24
Peak memory 200232 kb
Host smart-5846b0ea-b562-4ac1-8a7f-559b2a30a4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822257307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2822257307
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3905980787
Short name T234
Test name
Test status
Simulation time 137650541 ps
CPU time 1.06 seconds
Started Jul 01 04:41:44 PM PDT 24
Finished Jul 01 04:41:53 PM PDT 24
Peak memory 200004 kb
Host smart-537d4ef0-92b0-4dca-bde7-a2da84ef610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905980787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3905980787
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.185972586
Short name T135
Test name
Test status
Simulation time 204904133 ps
CPU time 1.41 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:51 PM PDT 24
Peak memory 200244 kb
Host smart-b0bb0101-1a80-4fa9-83a1-834e6753f4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185972586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.185972586
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1498949583
Short name T261
Test name
Test status
Simulation time 9813478084 ps
CPU time 42.15 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:42:32 PM PDT 24
Peak memory 208612 kb
Host smart-d72126ea-c923-43fb-88e5-bda3b1513682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498949583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1498949583
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1402429309
Short name T232
Test name
Test status
Simulation time 381789609 ps
CPU time 2.42 seconds
Started Jul 01 04:41:42 PM PDT 24
Finished Jul 01 04:41:53 PM PDT 24
Peak memory 200036 kb
Host smart-a4cae37b-228f-4df2-935c-c007cfa90d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402429309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1402429309
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.627487753
Short name T260
Test name
Test status
Simulation time 167152625 ps
CPU time 1.28 seconds
Started Jul 01 04:41:44 PM PDT 24
Finished Jul 01 04:41:53 PM PDT 24
Peak memory 200208 kb
Host smart-88b80be7-82d1-41be-8f73-930d8a90eb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627487753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.627487753
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.488527445
Short name T508
Test name
Test status
Simulation time 73032709 ps
CPU time 0.77 seconds
Started Jul 01 04:40:51 PM PDT 24
Finished Jul 01 04:40:53 PM PDT 24
Peak memory 199820 kb
Host smart-3ed28d20-98cf-4f05-bb8a-4fe768eee089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488527445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.488527445
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1812236657
Short name T373
Test name
Test status
Simulation time 2172841740 ps
CPU time 7.83 seconds
Started Jul 01 04:40:52 PM PDT 24
Finished Jul 01 04:41:03 PM PDT 24
Peak memory 217420 kb
Host smart-4b4d8930-9c53-43b2-96be-0a2fb471127c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812236657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1812236657
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3048661728
Short name T282
Test name
Test status
Simulation time 245157173 ps
CPU time 1.11 seconds
Started Jul 01 04:40:52 PM PDT 24
Finished Jul 01 04:40:56 PM PDT 24
Peak memory 217308 kb
Host smart-c3875202-d70c-4bda-beb5-b7d094cdafb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048661728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3048661728
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3488334896
Short name T341
Test name
Test status
Simulation time 158067662 ps
CPU time 0.82 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:40:57 PM PDT 24
Peak memory 199760 kb
Host smart-7675d145-c5a0-4d9b-b3b0-2e10c958a723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488334896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3488334896
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1195159415
Short name T120
Test name
Test status
Simulation time 1849629321 ps
CPU time 7 seconds
Started Jul 01 04:40:52 PM PDT 24
Finished Jul 01 04:41:02 PM PDT 24
Peak memory 200284 kb
Host smart-ab09778c-a7cc-4325-a026-395ef9857353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195159415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1195159415
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2346308541
Short name T71
Test name
Test status
Simulation time 16804990754 ps
CPU time 24.5 seconds
Started Jul 01 04:40:56 PM PDT 24
Finished Jul 01 04:41:24 PM PDT 24
Peak memory 221600 kb
Host smart-7f8de242-34e7-4728-abc4-226a93916230
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346308541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2346308541
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1495236920
Short name T398
Test name
Test status
Simulation time 103747127 ps
CPU time 1.08 seconds
Started Jul 01 04:40:56 PM PDT 24
Finished Jul 01 04:41:00 PM PDT 24
Peak memory 200032 kb
Host smart-59d59593-af92-4d44-9c69-c1384a7e22bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495236920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1495236920
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3392497848
Short name T301
Test name
Test status
Simulation time 114654080 ps
CPU time 1.23 seconds
Started Jul 01 04:40:56 PM PDT 24
Finished Jul 01 04:41:00 PM PDT 24
Peak memory 200220 kb
Host smart-466f0ba3-7bff-41c5-8a0f-a7dd84ff60d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392497848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3392497848
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1515251549
Short name T371
Test name
Test status
Simulation time 1458538267 ps
CPU time 6.75 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:41:03 PM PDT 24
Peak memory 208488 kb
Host smart-8c4cdacd-c34e-40f4-92c5-362f700e390f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515251549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1515251549
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.719655767
Short name T433
Test name
Test status
Simulation time 138106230 ps
CPU time 1.7 seconds
Started Jul 01 04:40:56 PM PDT 24
Finished Jul 01 04:41:01 PM PDT 24
Peak memory 199944 kb
Host smart-9c902e9d-d626-4c08-b334-fb4ab638cef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719655767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.719655767
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3917496170
Short name T152
Test name
Test status
Simulation time 79450262 ps
CPU time 0.84 seconds
Started Jul 01 04:40:51 PM PDT 24
Finished Jul 01 04:40:54 PM PDT 24
Peak memory 199908 kb
Host smart-579353f7-0c8d-4174-bf1e-74516bd2bb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917496170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3917496170
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.612066581
Short name T350
Test name
Test status
Simulation time 66856953 ps
CPU time 0.8 seconds
Started Jul 01 04:41:44 PM PDT 24
Finished Jul 01 04:41:52 PM PDT 24
Peak memory 199828 kb
Host smart-f11f5283-cf93-42ef-b1e0-116a3564ecf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612066581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.612066581
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1785668510
Short name T511
Test name
Test status
Simulation time 1903498714 ps
CPU time 7.19 seconds
Started Jul 01 04:41:44 PM PDT 24
Finished Jul 01 04:41:59 PM PDT 24
Peak memory 217652 kb
Host smart-554e27f3-e454-429d-be84-740b6c78ada4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785668510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1785668510
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.101300981
Short name T15
Test name
Test status
Simulation time 244334234 ps
CPU time 1.12 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:51 PM PDT 24
Peak memory 217356 kb
Host smart-4fb91625-1583-44b2-8bb9-61e2e558894a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101300981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.101300981
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.4014606730
Short name T331
Test name
Test status
Simulation time 197990925 ps
CPU time 0.91 seconds
Started Jul 01 04:41:43 PM PDT 24
Finished Jul 01 04:41:52 PM PDT 24
Peak memory 199936 kb
Host smart-38f78c12-3ab5-4700-a235-d4113e34d6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014606730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.4014606730
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2925963428
Short name T49
Test name
Test status
Simulation time 1199493419 ps
CPU time 4.67 seconds
Started Jul 01 04:41:39 PM PDT 24
Finished Jul 01 04:41:53 PM PDT 24
Peak memory 200212 kb
Host smart-22d97879-c4c8-4a5c-b165-c03bb9996ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925963428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2925963428
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.160296394
Short name T202
Test name
Test status
Simulation time 142453371 ps
CPU time 1.12 seconds
Started Jul 01 04:41:42 PM PDT 24
Finished Jul 01 04:41:51 PM PDT 24
Peak memory 200084 kb
Host smart-92520776-6f6c-44ad-b933-e8a69d7494cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160296394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.160296394
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1256770469
Short name T229
Test name
Test status
Simulation time 119816903 ps
CPU time 1.21 seconds
Started Jul 01 04:41:44 PM PDT 24
Finished Jul 01 04:41:53 PM PDT 24
Peak memory 200228 kb
Host smart-cb6332c5-be7b-4822-bd43-f68f43908463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256770469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1256770469
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3172027564
Short name T215
Test name
Test status
Simulation time 5806784728 ps
CPU time 22.1 seconds
Started Jul 01 04:41:40 PM PDT 24
Finished Jul 01 04:42:11 PM PDT 24
Peak memory 210308 kb
Host smart-2c9872f4-261d-4806-ad37-d5072bf8ef4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172027564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3172027564
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.716397743
Short name T81
Test name
Test status
Simulation time 148446641 ps
CPU time 1.76 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:52 PM PDT 24
Peak memory 200076 kb
Host smart-3d64d6f4-db86-49bc-9fd6-d8d72385989d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716397743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.716397743
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2719960319
Short name T428
Test name
Test status
Simulation time 137944555 ps
CPU time 1.25 seconds
Started Jul 01 04:41:40 PM PDT 24
Finished Jul 01 04:41:50 PM PDT 24
Peak memory 200256 kb
Host smart-a3d00ea3-d955-4771-87e1-18904e17dd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719960319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2719960319
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2117739717
Short name T221
Test name
Test status
Simulation time 63070311 ps
CPU time 0.79 seconds
Started Jul 01 04:41:48 PM PDT 24
Finished Jul 01 04:41:54 PM PDT 24
Peak memory 199832 kb
Host smart-ad427bd1-5c6c-42c0-9236-15ea7efd9778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117739717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2117739717
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3474258242
Short name T539
Test name
Test status
Simulation time 1902004600 ps
CPU time 7.82 seconds
Started Jul 01 04:41:40 PM PDT 24
Finished Jul 01 04:41:57 PM PDT 24
Peak memory 217620 kb
Host smart-1e0b9291-7a47-4fcd-a0eb-bdcde49fe660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474258242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3474258242
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.89209355
Short name T447
Test name
Test status
Simulation time 243939599 ps
CPU time 1.18 seconds
Started Jul 01 04:41:40 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 217400 kb
Host smart-c189af9c-92b7-4639-875a-a4f906264148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89209355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.89209355
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1181002457
Short name T375
Test name
Test status
Simulation time 211788138 ps
CPU time 1.06 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:51 PM PDT 24
Peak memory 199844 kb
Host smart-b6c9c662-65b1-46e4-bb49-cd3979b1a553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181002457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1181002457
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.4108517709
Short name T363
Test name
Test status
Simulation time 1633210581 ps
CPU time 6.22 seconds
Started Jul 01 04:41:41 PM PDT 24
Finished Jul 01 04:41:56 PM PDT 24
Peak memory 200344 kb
Host smart-5abee1ca-191f-4146-bfd4-7fb21953a47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108517709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.4108517709
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3481858617
Short name T52
Test name
Test status
Simulation time 176492225 ps
CPU time 1.21 seconds
Started Jul 01 04:41:40 PM PDT 24
Finished Jul 01 04:41:50 PM PDT 24
Peak memory 200108 kb
Host smart-c932184f-9da1-4f58-821c-adbfcb12ef8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481858617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3481858617
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.94743234
Short name T4
Test name
Test status
Simulation time 206406011 ps
CPU time 1.42 seconds
Started Jul 01 04:41:39 PM PDT 24
Finished Jul 01 04:41:49 PM PDT 24
Peak memory 200308 kb
Host smart-e0aef09a-7054-4611-ad82-b4d96b6ddd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94743234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.94743234
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3190709494
Short name T119
Test name
Test status
Simulation time 6390325696 ps
CPU time 21.81 seconds
Started Jul 01 04:41:40 PM PDT 24
Finished Jul 01 04:42:10 PM PDT 24
Peak memory 208552 kb
Host smart-e5d7363a-8616-44db-97b8-cbe7bba658e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190709494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3190709494
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.524168272
Short name T320
Test name
Test status
Simulation time 401996888 ps
CPU time 2.13 seconds
Started Jul 01 04:41:42 PM PDT 24
Finished Jul 01 04:41:52 PM PDT 24
Peak memory 200032 kb
Host smart-802bc059-105c-47c1-9978-109ea52da7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524168272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.524168272
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2469576649
Short name T162
Test name
Test status
Simulation time 168320176 ps
CPU time 1.19 seconds
Started Jul 01 04:41:44 PM PDT 24
Finished Jul 01 04:41:53 PM PDT 24
Peak memory 200036 kb
Host smart-573497ca-bed1-4ef5-9a02-1cff89fac347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469576649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2469576649
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1635655781
Short name T285
Test name
Test status
Simulation time 88737360 ps
CPU time 0.86 seconds
Started Jul 01 04:41:49 PM PDT 24
Finished Jul 01 04:41:55 PM PDT 24
Peak memory 199800 kb
Host smart-32195409-984e-4c5a-aec0-770710faba54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635655781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1635655781
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3431041778
Short name T496
Test name
Test status
Simulation time 243446410 ps
CPU time 1.06 seconds
Started Jul 01 04:41:53 PM PDT 24
Finished Jul 01 04:41:57 PM PDT 24
Peak memory 217392 kb
Host smart-ded5480d-e898-4b7d-a574-b780298f43b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431041778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3431041778
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2825178981
Short name T18
Test name
Test status
Simulation time 126654858 ps
CPU time 0.78 seconds
Started Jul 01 04:41:50 PM PDT 24
Finished Jul 01 04:41:55 PM PDT 24
Peak memory 199844 kb
Host smart-12539049-96eb-433d-acaf-df62e0972f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825178981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2825178981
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.934579407
Short name T99
Test name
Test status
Simulation time 850490876 ps
CPU time 4.81 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:05 PM PDT 24
Peak memory 200284 kb
Host smart-725a960b-36d4-494c-9774-3822b4f6d350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934579407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.934579407
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2880173136
Short name T57
Test name
Test status
Simulation time 113818619 ps
CPU time 1.04 seconds
Started Jul 01 04:41:49 PM PDT 24
Finished Jul 01 04:41:55 PM PDT 24
Peak memory 198936 kb
Host smart-f0e940fc-5d78-4c4e-9f3b-27aa13a9f172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880173136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2880173136
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2325068628
Short name T393
Test name
Test status
Simulation time 204039081 ps
CPU time 1.38 seconds
Started Jul 01 04:41:51 PM PDT 24
Finished Jul 01 04:41:56 PM PDT 24
Peak memory 200316 kb
Host smart-3e5da16b-a44c-4d4f-b210-d7d92868a1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325068628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2325068628
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2271300210
Short name T449
Test name
Test status
Simulation time 1485123999 ps
CPU time 6.1 seconds
Started Jul 01 04:41:49 PM PDT 24
Finished Jul 01 04:42:00 PM PDT 24
Peak memory 200284 kb
Host smart-aebcbb3d-9383-4565-9a1e-bbc0d356847d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271300210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2271300210
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1242141634
Short name T248
Test name
Test status
Simulation time 156449553 ps
CPU time 1.82 seconds
Started Jul 01 04:41:50 PM PDT 24
Finished Jul 01 04:41:56 PM PDT 24
Peak memory 200088 kb
Host smart-226e4d2f-7344-463b-8b63-3b00ca7047b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242141634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1242141634
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2984272842
Short name T524
Test name
Test status
Simulation time 94150022 ps
CPU time 0.89 seconds
Started Jul 01 04:41:56 PM PDT 24
Finished Jul 01 04:42:00 PM PDT 24
Peak memory 200036 kb
Host smart-35122d6f-36e7-4c17-8890-3a19775dd0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984272842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2984272842
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1019965287
Short name T176
Test name
Test status
Simulation time 55492682 ps
CPU time 0.68 seconds
Started Jul 01 04:41:55 PM PDT 24
Finished Jul 01 04:41:58 PM PDT 24
Peak memory 199824 kb
Host smart-cf4a87bb-fae3-407e-8089-46ef30ef9ff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019965287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1019965287
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3270836420
Short name T408
Test name
Test status
Simulation time 1232415651 ps
CPU time 6.22 seconds
Started Jul 01 04:41:50 PM PDT 24
Finished Jul 01 04:42:01 PM PDT 24
Peak memory 217372 kb
Host smart-6af38eea-39dc-4c4e-b277-6fec794193ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270836420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3270836420
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.4149498394
Short name T309
Test name
Test status
Simulation time 244858460 ps
CPU time 1.05 seconds
Started Jul 01 04:41:50 PM PDT 24
Finished Jul 01 04:41:56 PM PDT 24
Peak memory 217388 kb
Host smart-85b05d50-df02-446a-ab7c-75a1166e47cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149498394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.4149498394
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.228511420
Short name T361
Test name
Test status
Simulation time 109570048 ps
CPU time 0.78 seconds
Started Jul 01 04:41:51 PM PDT 24
Finished Jul 01 04:41:56 PM PDT 24
Peak memory 199944 kb
Host smart-4fbaa2f0-4708-4eba-8318-c04c176368ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228511420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.228511420
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3388853342
Short name T345
Test name
Test status
Simulation time 1898386230 ps
CPU time 6.41 seconds
Started Jul 01 04:41:50 PM PDT 24
Finished Jul 01 04:42:01 PM PDT 24
Peak memory 200152 kb
Host smart-c3d708dc-b2a7-414c-ad86-40992441bbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388853342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3388853342
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.324720585
Short name T410
Test name
Test status
Simulation time 153906316 ps
CPU time 1.1 seconds
Started Jul 01 04:41:49 PM PDT 24
Finished Jul 01 04:41:55 PM PDT 24
Peak memory 200152 kb
Host smart-729e4163-215f-498a-81eb-fa826c88505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324720585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.324720585
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.124197123
Short name T311
Test name
Test status
Simulation time 204695493 ps
CPU time 1.44 seconds
Started Jul 01 04:41:49 PM PDT 24
Finished Jul 01 04:41:55 PM PDT 24
Peak memory 199296 kb
Host smart-12682b36-ba4d-458d-bec6-db82769ccd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124197123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.124197123
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2208381326
Short name T97
Test name
Test status
Simulation time 7354085672 ps
CPU time 28.18 seconds
Started Jul 01 04:41:50 PM PDT 24
Finished Jul 01 04:42:23 PM PDT 24
Peak memory 200392 kb
Host smart-df50afbb-bd1c-4674-92dd-54dc8390404a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208381326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2208381326
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1229862192
Short name T473
Test name
Test status
Simulation time 118314366 ps
CPU time 1.57 seconds
Started Jul 01 04:41:47 PM PDT 24
Finished Jul 01 04:41:55 PM PDT 24
Peak memory 200032 kb
Host smart-ceb67264-4b3e-485c-b1d4-3bdd443054de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229862192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1229862192
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1448731758
Short name T384
Test name
Test status
Simulation time 228819755 ps
CPU time 1.39 seconds
Started Jul 01 04:41:51 PM PDT 24
Finished Jul 01 04:41:57 PM PDT 24
Peak memory 200232 kb
Host smart-422a8e3b-16a9-4f4b-9b38-2c59ed9f0e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448731758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1448731758
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1573469518
Short name T76
Test name
Test status
Simulation time 70747849 ps
CPU time 0.76 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:01 PM PDT 24
Peak memory 199884 kb
Host smart-f26c76ce-6156-4d43-9195-5139770f2813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573469518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1573469518
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1401365392
Short name T55
Test name
Test status
Simulation time 1876122943 ps
CPU time 7.36 seconds
Started Jul 01 04:41:59 PM PDT 24
Finished Jul 01 04:42:09 PM PDT 24
Peak memory 221376 kb
Host smart-cbb97e61-2197-4e4a-b4e9-804511d7abf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401365392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1401365392
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2357852168
Short name T491
Test name
Test status
Simulation time 243992732 ps
CPU time 1.14 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:01 PM PDT 24
Peak memory 217340 kb
Host smart-6ee69f89-5313-4234-8dd7-c3a02bc963a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357852168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2357852168
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.4031111961
Short name T337
Test name
Test status
Simulation time 128624335 ps
CPU time 0.81 seconds
Started Jul 01 04:41:49 PM PDT 24
Finished Jul 01 04:41:55 PM PDT 24
Peak memory 199844 kb
Host smart-d8e03ce7-23fa-4d0d-bfbf-af30afe56d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031111961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.4031111961
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1920824187
Short name T318
Test name
Test status
Simulation time 1481465220 ps
CPU time 6.23 seconds
Started Jul 01 04:41:58 PM PDT 24
Finished Jul 01 04:42:07 PM PDT 24
Peak memory 200260 kb
Host smart-9ab34aea-49c7-49b6-b044-51b16b06c18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920824187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1920824187
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1461426435
Short name T143
Test name
Test status
Simulation time 100290931 ps
CPU time 1.03 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:01 PM PDT 24
Peak memory 200028 kb
Host smart-14163fad-4214-4624-a666-2f667b3f9610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461426435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1461426435
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.421791241
Short name T354
Test name
Test status
Simulation time 194860821 ps
CPU time 1.43 seconds
Started Jul 01 04:41:50 PM PDT 24
Finished Jul 01 04:41:56 PM PDT 24
Peak memory 200316 kb
Host smart-583cc414-632b-4cec-a599-1d0a05f59012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421791241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.421791241
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2520077097
Short name T80
Test name
Test status
Simulation time 6467418470 ps
CPU time 23.94 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:23 PM PDT 24
Peak memory 208576 kb
Host smart-ae7ed7f2-8f49-4a79-9682-b3c1ae7f59a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520077097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2520077097
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.420262155
Short name T392
Test name
Test status
Simulation time 274327445 ps
CPU time 1.76 seconds
Started Jul 01 04:42:03 PM PDT 24
Finished Jul 01 04:42:06 PM PDT 24
Peak memory 200024 kb
Host smart-ab365d59-24c1-46ac-8aa4-d7ba2653b067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420262155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.420262155
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2813219578
Short name T142
Test name
Test status
Simulation time 102985918 ps
CPU time 0.97 seconds
Started Jul 01 04:41:56 PM PDT 24
Finished Jul 01 04:42:00 PM PDT 24
Peak memory 200112 kb
Host smart-500d9564-4238-42d1-9daf-f0a49280a583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813219578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2813219578
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3461654466
Short name T36
Test name
Test status
Simulation time 55902951 ps
CPU time 0.69 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:11 PM PDT 24
Peak memory 199740 kb
Host smart-53e17bd2-13fb-48d9-92a2-0d643c7c80fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461654466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3461654466
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1299830658
Short name T510
Test name
Test status
Simulation time 2168761028 ps
CPU time 8.12 seconds
Started Jul 01 04:41:56 PM PDT 24
Finished Jul 01 04:42:08 PM PDT 24
Peak memory 217744 kb
Host smart-6c7dd01c-18c2-4f57-a104-7e8326381493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299830658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1299830658
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4032042049
Short name T237
Test name
Test status
Simulation time 244375732 ps
CPU time 1.14 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:11 PM PDT 24
Peak memory 217308 kb
Host smart-3d4ff598-63af-44cb-849e-698ac92d1fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032042049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4032042049
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.4127955209
Short name T211
Test name
Test status
Simulation time 170700452 ps
CPU time 0.87 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:11 PM PDT 24
Peak memory 199744 kb
Host smart-0dc0e33a-de9a-4073-9c0b-bf27a73a6166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127955209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.4127955209
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.4035168296
Short name T92
Test name
Test status
Simulation time 1713046900 ps
CPU time 6.5 seconds
Started Jul 01 04:41:58 PM PDT 24
Finished Jul 01 04:42:08 PM PDT 24
Peak memory 200288 kb
Host smart-59086338-08af-4b74-a701-8b3465dde47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035168296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.4035168296
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4292039840
Short name T404
Test name
Test status
Simulation time 104323599 ps
CPU time 1.04 seconds
Started Jul 01 04:41:56 PM PDT 24
Finished Jul 01 04:42:00 PM PDT 24
Peak memory 200124 kb
Host smart-a8892307-095c-4a0c-ac44-91464fefff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292039840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4292039840
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2932793426
Short name T255
Test name
Test status
Simulation time 111022309 ps
CPU time 1.19 seconds
Started Jul 01 04:41:56 PM PDT 24
Finished Jul 01 04:42:00 PM PDT 24
Peak memory 200308 kb
Host smart-70e72357-42d6-4007-86c6-ad224f40dba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932793426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2932793426
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2755453601
Short name T407
Test name
Test status
Simulation time 6873956776 ps
CPU time 29.45 seconds
Started Jul 01 04:41:56 PM PDT 24
Finished Jul 01 04:42:28 PM PDT 24
Peak memory 208548 kb
Host smart-2b9953bd-3861-4d89-8b6a-49238294a18a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755453601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2755453601
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1794321791
Short name T422
Test name
Test status
Simulation time 325205479 ps
CPU time 1.89 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:01 PM PDT 24
Peak memory 200072 kb
Host smart-8b8e8a9f-b558-4616-93ed-48a50cc30a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794321791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1794321791
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.711006673
Short name T488
Test name
Test status
Simulation time 117199512 ps
CPU time 0.97 seconds
Started Jul 01 04:41:56 PM PDT 24
Finished Jul 01 04:41:59 PM PDT 24
Peak memory 199936 kb
Host smart-73db52cd-9fa6-47cb-a035-8660e64e211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711006673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.711006673
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.451990898
Short name T154
Test name
Test status
Simulation time 87784508 ps
CPU time 0.82 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:12 PM PDT 24
Peak memory 199796 kb
Host smart-6ca42690-f589-4a06-9ca0-10708b40fceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451990898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.451990898
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2875688551
Short name T39
Test name
Test status
Simulation time 1226325222 ps
CPU time 5.69 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:06 PM PDT 24
Peak memory 217724 kb
Host smart-3b1108e3-2191-4a92-aa20-9f8e72489cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875688551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2875688551
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1509017717
Short name T163
Test name
Test status
Simulation time 244958746 ps
CPU time 1.15 seconds
Started Jul 01 04:41:58 PM PDT 24
Finished Jul 01 04:42:02 PM PDT 24
Peak memory 217392 kb
Host smart-a5e24b97-dde8-43fe-980c-3937d06ecfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509017717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1509017717
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.382056311
Short name T315
Test name
Test status
Simulation time 181248567 ps
CPU time 0.87 seconds
Started Jul 01 04:42:03 PM PDT 24
Finished Jul 01 04:42:05 PM PDT 24
Peak memory 199840 kb
Host smart-c46ed060-2b92-4527-b226-6d5a21ca139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382056311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.382056311
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2233677289
Short name T73
Test name
Test status
Simulation time 1457218304 ps
CPU time 5.51 seconds
Started Jul 01 04:41:59 PM PDT 24
Finished Jul 01 04:42:07 PM PDT 24
Peak memory 200296 kb
Host smart-6e0e32c4-a71a-4e93-a141-2335959fdaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233677289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2233677289
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3393317969
Short name T75
Test name
Test status
Simulation time 109702946 ps
CPU time 1 seconds
Started Jul 01 04:42:03 PM PDT 24
Finished Jul 01 04:42:06 PM PDT 24
Peak memory 200028 kb
Host smart-30a5b288-4f01-4270-a241-4fae06a5dc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393317969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3393317969
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.4243453011
Short name T359
Test name
Test status
Simulation time 113992510 ps
CPU time 1.16 seconds
Started Jul 01 04:41:56 PM PDT 24
Finished Jul 01 04:41:59 PM PDT 24
Peak memory 200344 kb
Host smart-7c604730-633d-4ff2-bb98-bafe37e93db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243453011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.4243453011
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.630774350
Short name T514
Test name
Test status
Simulation time 4191901939 ps
CPU time 16.05 seconds
Started Jul 01 04:41:56 PM PDT 24
Finished Jul 01 04:42:15 PM PDT 24
Peak memory 200356 kb
Host smart-1d097dd0-8410-4e0d-ac1f-52739937f1d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630774350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.630774350
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1827087129
Short name T188
Test name
Test status
Simulation time 315538173 ps
CPU time 1.91 seconds
Started Jul 01 04:41:58 PM PDT 24
Finished Jul 01 04:42:03 PM PDT 24
Peak memory 200028 kb
Host smart-841f55d0-e3ec-4197-a34e-a7ae06a163f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827087129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1827087129
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2936869477
Short name T167
Test name
Test status
Simulation time 89286612 ps
CPU time 0.87 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:01 PM PDT 24
Peak memory 200012 kb
Host smart-f789c5f8-c280-4870-94b6-6116f85c43f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936869477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2936869477
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2096081537
Short name T505
Test name
Test status
Simulation time 71571041 ps
CPU time 0.75 seconds
Started Jul 01 04:41:55 PM PDT 24
Finished Jul 01 04:41:58 PM PDT 24
Peak memory 199824 kb
Host smart-e7a6c9b5-45d9-4548-a679-e8cc009e4160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096081537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2096081537
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1675112298
Short name T160
Test name
Test status
Simulation time 244650418 ps
CPU time 1.2 seconds
Started Jul 01 04:41:58 PM PDT 24
Finished Jul 01 04:42:02 PM PDT 24
Peak memory 217444 kb
Host smart-fe5b3aa7-6d9b-440d-b6fc-b5e87514df65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675112298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1675112298
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1488923736
Short name T289
Test name
Test status
Simulation time 118564312 ps
CPU time 0.76 seconds
Started Jul 01 04:42:03 PM PDT 24
Finished Jul 01 04:42:05 PM PDT 24
Peak memory 199844 kb
Host smart-bff637c7-bdb8-492b-af4e-88c408c3a671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488923736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1488923736
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1802741919
Short name T170
Test name
Test status
Simulation time 1060156660 ps
CPU time 4.64 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:05 PM PDT 24
Peak memory 200424 kb
Host smart-c6320bef-038d-405b-b52b-a6ad263cf5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802741919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1802741919
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1946387526
Short name T351
Test name
Test status
Simulation time 99693235 ps
CPU time 0.96 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:13 PM PDT 24
Peak memory 200004 kb
Host smart-f690f03c-24e7-4487-9524-22e22511a6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946387526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1946387526
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.727691547
Short name T207
Test name
Test status
Simulation time 129358946 ps
CPU time 1.22 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:01 PM PDT 24
Peak memory 200232 kb
Host smart-061e16d6-a785-4100-a329-95891aff3ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727691547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.727691547
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2816770345
Short name T247
Test name
Test status
Simulation time 4826950461 ps
CPU time 20.67 seconds
Started Jul 01 04:41:59 PM PDT 24
Finished Jul 01 04:42:22 PM PDT 24
Peak memory 210208 kb
Host smart-d834e7ed-231a-4685-a8a5-543fb6512e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816770345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2816770345
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1551849347
Short name T409
Test name
Test status
Simulation time 122113364 ps
CPU time 1.62 seconds
Started Jul 01 04:41:57 PM PDT 24
Finished Jul 01 04:42:02 PM PDT 24
Peak memory 200016 kb
Host smart-d9af251c-5c71-443f-9089-d03a37197e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551849347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1551849347
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3766322347
Short name T159
Test name
Test status
Simulation time 89282425 ps
CPU time 0.86 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:12 PM PDT 24
Peak memory 200012 kb
Host smart-88451b85-55bc-4666-aae5-b43eba412927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766322347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3766322347
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2124596519
Short name T365
Test name
Test status
Simulation time 73325074 ps
CPU time 0.78 seconds
Started Jul 01 04:42:08 PM PDT 24
Finished Jul 01 04:42:14 PM PDT 24
Peak memory 199828 kb
Host smart-d30d5f5f-b297-4ba3-b876-7a54a1eada98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124596519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2124596519
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1638523598
Short name T390
Test name
Test status
Simulation time 1892965525 ps
CPU time 8.24 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:19 PM PDT 24
Peak memory 217788 kb
Host smart-62481c91-7845-4806-a7c5-4d3b775e4957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638523598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1638523598
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.4062428859
Short name T264
Test name
Test status
Simulation time 244278937 ps
CPU time 1.1 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:12 PM PDT 24
Peak memory 217312 kb
Host smart-20ae5abd-d93d-4535-9ee2-c54593c71b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062428859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.4062428859
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1709450360
Short name T200
Test name
Test status
Simulation time 125706118 ps
CPU time 0.9 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:13 PM PDT 24
Peak memory 199844 kb
Host smart-ce19a22a-159d-4ba7-97f4-9f2082b604a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709450360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1709450360
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2569767653
Short name T102
Test name
Test status
Simulation time 837036567 ps
CPU time 4.34 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:15 PM PDT 24
Peak memory 200284 kb
Host smart-67c93563-ef82-4bc1-8d8b-3f07a6d354a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569767653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2569767653
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.80525361
Short name T137
Test name
Test status
Simulation time 104148627 ps
CPU time 1.08 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:13 PM PDT 24
Peak memory 199940 kb
Host smart-71fb9e88-0c12-46b2-acad-11468b03f112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80525361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.80525361
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.693179492
Short name T453
Test name
Test status
Simulation time 114705047 ps
CPU time 1.22 seconds
Started Jul 01 04:41:56 PM PDT 24
Finished Jul 01 04:41:59 PM PDT 24
Peak memory 200208 kb
Host smart-c13306d2-3fe3-4c83-9e23-5ab6bab9abaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693179492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.693179492
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.764688671
Short name T166
Test name
Test status
Simulation time 5637694225 ps
CPU time 21.05 seconds
Started Jul 01 04:42:09 PM PDT 24
Finished Jul 01 04:42:34 PM PDT 24
Peak memory 200360 kb
Host smart-d9077bf8-5732-401c-b935-0782f608d340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764688671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.764688671
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3802685837
Short name T244
Test name
Test status
Simulation time 513071548 ps
CPU time 2.73 seconds
Started Jul 01 04:42:05 PM PDT 24
Finished Jul 01 04:42:11 PM PDT 24
Peak memory 200036 kb
Host smart-004ca401-5f83-489d-beff-92e9f7238671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802685837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3802685837
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3421199828
Short name T296
Test name
Test status
Simulation time 107107790 ps
CPU time 1 seconds
Started Jul 01 04:42:08 PM PDT 24
Finished Jul 01 04:42:14 PM PDT 24
Peak memory 200012 kb
Host smart-b12550f0-0346-471a-8ff5-cce92b3600c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421199828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3421199828
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.148348934
Short name T436
Test name
Test status
Simulation time 64327210 ps
CPU time 0.78 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:13 PM PDT 24
Peak memory 199808 kb
Host smart-11cf474b-0148-43db-92dc-3d8be1e510ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148348934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.148348934
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3679793542
Short name T45
Test name
Test status
Simulation time 1220833084 ps
CPU time 5.61 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:16 PM PDT 24
Peak memory 217624 kb
Host smart-0fdbeaad-ba1f-4256-b5d8-593867ec2af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679793542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3679793542
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2249768438
Short name T323
Test name
Test status
Simulation time 243834380 ps
CPU time 1.16 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:12 PM PDT 24
Peak memory 217632 kb
Host smart-f7af5174-de69-489e-ab44-9589348faebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249768438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2249768438
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2017708283
Short name T378
Test name
Test status
Simulation time 98700825 ps
CPU time 0.78 seconds
Started Jul 01 04:42:05 PM PDT 24
Finished Jul 01 04:42:08 PM PDT 24
Peak memory 199748 kb
Host smart-6447c98b-7742-4ae2-91ff-1211dd903b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017708283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2017708283
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.100914703
Short name T528
Test name
Test status
Simulation time 1880596443 ps
CPU time 7.06 seconds
Started Jul 01 04:42:09 PM PDT 24
Finished Jul 01 04:42:20 PM PDT 24
Peak memory 200284 kb
Host smart-17630721-4228-4e7d-9221-6291ae01375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100914703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.100914703
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3004800137
Short name T208
Test name
Test status
Simulation time 146946523 ps
CPU time 1.14 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:11 PM PDT 24
Peak memory 200092 kb
Host smart-f030dd72-bc4f-4933-bc47-b76232e793fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004800137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3004800137
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3448695558
Short name T399
Test name
Test status
Simulation time 116324547 ps
CPU time 1.19 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:14 PM PDT 24
Peak memory 200220 kb
Host smart-935c4276-1c7a-4755-afc9-708ed9dbafa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448695558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3448695558
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1602339615
Short name T456
Test name
Test status
Simulation time 2725842758 ps
CPU time 11.41 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:24 PM PDT 24
Peak memory 208592 kb
Host smart-2fbea1b9-a50f-4808-a83e-6c8db15090f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602339615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1602339615
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1746556883
Short name T463
Test name
Test status
Simulation time 264415597 ps
CPU time 1.89 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:13 PM PDT 24
Peak memory 200260 kb
Host smart-bb8a604b-0d9b-4e34-8444-98c456788ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746556883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1746556883
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3107602581
Short name T68
Test name
Test status
Simulation time 245826665 ps
CPU time 1.35 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:13 PM PDT 24
Peak memory 200040 kb
Host smart-a23c8cf5-15e0-416c-8f14-9dd17e971959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107602581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3107602581
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.441923398
Short name T329
Test name
Test status
Simulation time 78065473 ps
CPU time 0.81 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:40:57 PM PDT 24
Peak memory 199804 kb
Host smart-ed646e60-9846-4ded-a587-4791b2f801d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441923398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.441923398
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.799230958
Short name T35
Test name
Test status
Simulation time 1901872887 ps
CPU time 6.46 seconds
Started Jul 01 04:40:52 PM PDT 24
Finished Jul 01 04:41:00 PM PDT 24
Peak memory 221572 kb
Host smart-f66440eb-9d67-41ca-80b9-3ec69c767f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799230958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.799230958
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2293841266
Short name T534
Test name
Test status
Simulation time 245447935 ps
CPU time 1.03 seconds
Started Jul 01 04:40:54 PM PDT 24
Finished Jul 01 04:40:59 PM PDT 24
Peak memory 217392 kb
Host smart-82bdc90a-14f6-4175-a3f7-8f5c72d8a76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293841266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2293841266
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3354231043
Short name T348
Test name
Test status
Simulation time 131063665 ps
CPU time 0.84 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:40:58 PM PDT 24
Peak memory 199844 kb
Host smart-5d3077d2-05e9-48f9-bd77-2a25cb20ce49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354231043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3354231043
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.982972953
Short name T431
Test name
Test status
Simulation time 1446967451 ps
CPU time 6.03 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:41:03 PM PDT 24
Peak memory 200220 kb
Host smart-43c72010-b283-40c3-8525-8efb99fa8afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982972953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.982972953
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3072191833
Short name T65
Test name
Test status
Simulation time 16593906406 ps
CPU time 24.44 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:41:21 PM PDT 24
Peak memory 217124 kb
Host smart-f437d480-d45d-4cdc-a4d7-6193d2fe6b1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072191833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3072191833
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2143023397
Short name T245
Test name
Test status
Simulation time 145230379 ps
CPU time 1.12 seconds
Started Jul 01 04:40:54 PM PDT 24
Finished Jul 01 04:40:58 PM PDT 24
Peak memory 200096 kb
Host smart-d06476f0-c132-4dfa-8a8b-5425bbd0e984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143023397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2143023397
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1288271858
Short name T283
Test name
Test status
Simulation time 249582937 ps
CPU time 1.56 seconds
Started Jul 01 04:40:52 PM PDT 24
Finished Jul 01 04:40:56 PM PDT 24
Peak memory 200220 kb
Host smart-07da5cd0-49a3-47f0-af23-fed49ce6d011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288271858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1288271858
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3861506786
Short name T369
Test name
Test status
Simulation time 2694388885 ps
CPU time 10.25 seconds
Started Jul 01 04:40:54 PM PDT 24
Finished Jul 01 04:41:08 PM PDT 24
Peak memory 200260 kb
Host smart-4a6848b0-e653-433e-b73a-c280de45a04f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861506786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3861506786
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3640271187
Short name T226
Test name
Test status
Simulation time 463487566 ps
CPU time 2.46 seconds
Started Jul 01 04:40:51 PM PDT 24
Finished Jul 01 04:40:56 PM PDT 24
Peak memory 200068 kb
Host smart-f110ec8e-b5b0-4059-ac0e-ba6a53c8893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640271187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3640271187
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1305708010
Short name T129
Test name
Test status
Simulation time 171363886 ps
CPU time 1.27 seconds
Started Jul 01 04:40:54 PM PDT 24
Finished Jul 01 04:40:59 PM PDT 24
Peak memory 200180 kb
Host smart-48a839ba-d3c1-4bac-bd9b-855a03b05f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305708010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1305708010
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.518640359
Short name T481
Test name
Test status
Simulation time 62740793 ps
CPU time 0.79 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:12 PM PDT 24
Peak memory 199820 kb
Host smart-8691e89e-191a-4261-9b29-2c48ad6be9c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518640359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.518640359
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1502983318
Short name T31
Test name
Test status
Simulation time 1220917263 ps
CPU time 5.36 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:16 PM PDT 24
Peak memory 221632 kb
Host smart-4b7e6ec9-2736-445d-b136-36ffd366051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502983318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1502983318
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3172732747
Short name T440
Test name
Test status
Simulation time 244616946 ps
CPU time 1.11 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:13 PM PDT 24
Peak memory 217588 kb
Host smart-74c1885a-471b-4dd9-9ad0-df97a90bd830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172732747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3172732747
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3654589343
Short name T522
Test name
Test status
Simulation time 98574126 ps
CPU time 0.8 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:12 PM PDT 24
Peak memory 199848 kb
Host smart-22fb47bb-97b8-45ae-94ff-5f7af89f2ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654589343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3654589343
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2411069399
Short name T146
Test name
Test status
Simulation time 1367330503 ps
CPU time 5.62 seconds
Started Jul 01 04:42:05 PM PDT 24
Finished Jul 01 04:42:14 PM PDT 24
Peak memory 200268 kb
Host smart-f153a670-32c0-4d1c-b4ee-eebc4144deb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411069399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2411069399
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1920877427
Short name T14
Test name
Test status
Simulation time 171867319 ps
CPU time 1.17 seconds
Started Jul 01 04:42:08 PM PDT 24
Finished Jul 01 04:42:14 PM PDT 24
Peak memory 199980 kb
Host smart-102542c2-a80e-46d0-9b0e-e72ef549e2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920877427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1920877427
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.238224996
Short name T150
Test name
Test status
Simulation time 244287025 ps
CPU time 1.46 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:14 PM PDT 24
Peak memory 200216 kb
Host smart-2c41a250-fade-49da-bcf7-a736cf22cd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238224996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.238224996
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2689887499
Short name T394
Test name
Test status
Simulation time 8465048154 ps
CPU time 37.38 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:50 PM PDT 24
Peak memory 208592 kb
Host smart-4c18c3ec-c928-438f-bef4-c04cc0f18014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689887499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2689887499
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1642126530
Short name T432
Test name
Test status
Simulation time 309914617 ps
CPU time 2.05 seconds
Started Jul 01 04:42:09 PM PDT 24
Finished Jul 01 04:42:15 PM PDT 24
Peak memory 208220 kb
Host smart-010f7c49-407e-4c53-b761-e9c705b6eb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642126530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1642126530
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3081629247
Short name T319
Test name
Test status
Simulation time 242249527 ps
CPU time 1.4 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:12 PM PDT 24
Peak memory 200160 kb
Host smart-7446c9df-3ddc-42a4-ab84-52e53930bb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081629247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3081629247
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2508831018
Short name T360
Test name
Test status
Simulation time 63444000 ps
CPU time 0.78 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:11 PM PDT 24
Peak memory 199824 kb
Host smart-a568a741-9e10-4bf2-8af5-531f63a89b9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508831018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2508831018
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.813414971
Short name T28
Test name
Test status
Simulation time 1894302308 ps
CPU time 6.73 seconds
Started Jul 01 04:42:08 PM PDT 24
Finished Jul 01 04:42:20 PM PDT 24
Peak memory 217640 kb
Host smart-08cfd04f-220a-4855-9414-c239cd154dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813414971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.813414971
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3145189525
Short name T194
Test name
Test status
Simulation time 243741136 ps
CPU time 1.19 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:13 PM PDT 24
Peak memory 217604 kb
Host smart-e1ad1a66-fd90-44bb-b7b7-55fd5fc4b70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145189525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3145189525
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.505444176
Short name T321
Test name
Test status
Simulation time 205531571 ps
CPU time 0.97 seconds
Started Jul 01 04:42:05 PM PDT 24
Finished Jul 01 04:42:09 PM PDT 24
Peak memory 199944 kb
Host smart-458a6976-e090-466a-b3f4-9b35214ed9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505444176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.505444176
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2768552539
Short name T204
Test name
Test status
Simulation time 1040238245 ps
CPU time 4.81 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:15 PM PDT 24
Peak memory 200284 kb
Host smart-b62d21fc-f545-44cd-94c3-ad8cf6b51b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768552539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2768552539
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3241711155
Short name T267
Test name
Test status
Simulation time 95818782 ps
CPU time 1.01 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:13 PM PDT 24
Peak memory 200016 kb
Host smart-f4fd57df-4b33-4b34-b013-6171ddc324b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241711155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3241711155
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2014858459
Short name T461
Test name
Test status
Simulation time 118165730 ps
CPU time 1.2 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:12 PM PDT 24
Peak memory 200264 kb
Host smart-e608d008-a287-4221-b211-9ce4d6e354c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014858459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2014858459
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1936865112
Short name T13
Test name
Test status
Simulation time 1179590852 ps
CPU time 5.62 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:18 PM PDT 24
Peak memory 200264 kb
Host smart-4e7af9f9-6ae8-454a-ae5c-cd94f05e37e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936865112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1936865112
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2288890729
Short name T538
Test name
Test status
Simulation time 144235331 ps
CPU time 1.99 seconds
Started Jul 01 04:42:06 PM PDT 24
Finished Jul 01 04:42:12 PM PDT 24
Peak memory 200260 kb
Host smart-743c5933-af64-43f7-bdbd-ad3895c7bacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288890729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2288890729
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3258057013
Short name T9
Test name
Test status
Simulation time 171564856 ps
CPU time 1.33 seconds
Started Jul 01 04:42:07 PM PDT 24
Finished Jul 01 04:42:13 PM PDT 24
Peak memory 200316 kb
Host smart-b4441b44-abbd-4456-a0b1-45c84bc31654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258057013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3258057013
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.833832983
Short name T366
Test name
Test status
Simulation time 67271662 ps
CPU time 0.76 seconds
Started Jul 01 04:42:15 PM PDT 24
Finished Jul 01 04:42:18 PM PDT 24
Peak memory 199944 kb
Host smart-de680514-2306-4819-8c85-91caf68bea94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833832983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.833832983
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.406399640
Short name T246
Test name
Test status
Simulation time 2346309338 ps
CPU time 9.65 seconds
Started Jul 01 04:42:18 PM PDT 24
Finished Jul 01 04:42:33 PM PDT 24
Peak memory 217768 kb
Host smart-6cd7c36e-5222-4f1d-a329-58c6e257b2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406399640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.406399640
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3194609029
Short name T217
Test name
Test status
Simulation time 245739523 ps
CPU time 1.09 seconds
Started Jul 01 04:42:15 PM PDT 24
Finished Jul 01 04:42:20 PM PDT 24
Peak memory 217396 kb
Host smart-2716d386-35d3-44d7-990b-0817dc001b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194609029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3194609029
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2851621819
Short name T374
Test name
Test status
Simulation time 112907541 ps
CPU time 0.82 seconds
Started Jul 01 04:42:08 PM PDT 24
Finished Jul 01 04:42:14 PM PDT 24
Peak memory 199856 kb
Host smart-868b7a8f-edb0-4810-9f4f-5b8c07c1c948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851621819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2851621819
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3860759342
Short name T277
Test name
Test status
Simulation time 819296530 ps
CPU time 4.17 seconds
Started Jul 01 04:42:15 PM PDT 24
Finished Jul 01 04:42:23 PM PDT 24
Peak memory 200328 kb
Host smart-b9272769-522b-485d-afb6-ed00f33c5cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860759342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3860759342
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3711175954
Short name T196
Test name
Test status
Simulation time 182358544 ps
CPU time 1.24 seconds
Started Jul 01 04:42:14 PM PDT 24
Finished Jul 01 04:42:18 PM PDT 24
Peak memory 200232 kb
Host smart-495f912b-d98c-421f-9b73-f581f695a6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711175954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3711175954
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3584187116
Short name T227
Test name
Test status
Simulation time 190531779 ps
CPU time 1.38 seconds
Started Jul 01 04:42:04 PM PDT 24
Finished Jul 01 04:42:08 PM PDT 24
Peak memory 200164 kb
Host smart-8a9c9447-8338-4d31-8f9f-57309e0a58c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584187116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3584187116
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3854938580
Short name T281
Test name
Test status
Simulation time 2622600689 ps
CPU time 11.26 seconds
Started Jul 01 04:42:17 PM PDT 24
Finished Jul 01 04:42:34 PM PDT 24
Peak memory 208544 kb
Host smart-fd4492e1-03b6-4e9a-966c-5f86caddfbfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854938580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3854938580
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2096873922
Short name T50
Test name
Test status
Simulation time 121610164 ps
CPU time 1.58 seconds
Started Jul 01 04:42:15 PM PDT 24
Finished Jul 01 04:42:20 PM PDT 24
Peak memory 200024 kb
Host smart-6947ddbf-68cf-4142-9b6d-30fef81c8541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096873922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2096873922
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1931933440
Short name T164
Test name
Test status
Simulation time 113116768 ps
CPU time 1.08 seconds
Started Jul 01 04:42:19 PM PDT 24
Finished Jul 01 04:42:27 PM PDT 24
Peak memory 200044 kb
Host smart-46ff26b6-b732-4527-b5e9-87d04ce0c8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931933440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1931933440
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.230202855
Short name T280
Test name
Test status
Simulation time 96024379 ps
CPU time 0.82 seconds
Started Jul 01 04:42:14 PM PDT 24
Finished Jul 01 04:42:18 PM PDT 24
Peak memory 199928 kb
Host smart-0d220bdc-a0bc-4823-a4eb-78e4f5d428ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230202855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.230202855
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2598050102
Short name T214
Test name
Test status
Simulation time 2180589048 ps
CPU time 7.98 seconds
Started Jul 01 04:42:15 PM PDT 24
Finished Jul 01 04:42:26 PM PDT 24
Peak memory 221432 kb
Host smart-5fe43fb8-a5a6-4063-9edf-2705bbf78a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598050102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2598050102
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1606778720
Short name T273
Test name
Test status
Simulation time 244482433 ps
CPU time 1.07 seconds
Started Jul 01 04:42:14 PM PDT 24
Finished Jul 01 04:42:18 PM PDT 24
Peak memory 217396 kb
Host smart-b53f7245-a8c2-4206-a2cb-8a8ac731b01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606778720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1606778720
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1512960237
Short name T416
Test name
Test status
Simulation time 120787405 ps
CPU time 0.83 seconds
Started Jul 01 04:42:18 PM PDT 24
Finished Jul 01 04:42:24 PM PDT 24
Peak memory 199844 kb
Host smart-c225b043-a56a-4cf2-8ff7-d6c2ddefc493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512960237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1512960237
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3287072590
Short name T327
Test name
Test status
Simulation time 780076356 ps
CPU time 3.9 seconds
Started Jul 01 04:42:17 PM PDT 24
Finished Jul 01 04:42:27 PM PDT 24
Peak memory 200284 kb
Host smart-2930c72e-85b4-4795-9d10-cd84b9053a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287072590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3287072590
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.636461241
Short name T205
Test name
Test status
Simulation time 148986832 ps
CPU time 1.17 seconds
Started Jul 01 04:42:15 PM PDT 24
Finished Jul 01 04:42:19 PM PDT 24
Peak memory 200044 kb
Host smart-08530899-0f0c-4419-b527-51678e7a97b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636461241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.636461241
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3891366285
Short name T145
Test name
Test status
Simulation time 129577066 ps
CPU time 1.16 seconds
Started Jul 01 04:42:16 PM PDT 24
Finished Jul 01 04:42:21 PM PDT 24
Peak memory 200224 kb
Host smart-d12bb58f-530c-4146-b377-c18f659c1fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891366285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3891366285
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.300859828
Short name T293
Test name
Test status
Simulation time 176237187 ps
CPU time 1.45 seconds
Started Jul 01 04:42:14 PM PDT 24
Finished Jul 01 04:42:17 PM PDT 24
Peak memory 200164 kb
Host smart-4e41f876-ac08-4c10-aa02-0c2b3b15743f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300859828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.300859828
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1101565508
Short name T310
Test name
Test status
Simulation time 365944426 ps
CPU time 2.48 seconds
Started Jul 01 04:42:18 PM PDT 24
Finished Jul 01 04:42:26 PM PDT 24
Peak memory 199928 kb
Host smart-a6d6d7e0-a2f6-4d98-986f-d488edb2a54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101565508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1101565508
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3528715943
Short name T192
Test name
Test status
Simulation time 243912981 ps
CPU time 1.47 seconds
Started Jul 01 04:42:18 PM PDT 24
Finished Jul 01 04:42:26 PM PDT 24
Peak memory 200040 kb
Host smart-39d7dab7-4c5a-4ff8-bd08-9eee859b520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528715943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3528715943
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.268058564
Short name T533
Test name
Test status
Simulation time 100531324 ps
CPU time 0.89 seconds
Started Jul 01 04:42:14 PM PDT 24
Finished Jul 01 04:42:18 PM PDT 24
Peak memory 199820 kb
Host smart-7e392c9e-2de4-4b4a-b60d-75a705fd4d01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268058564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.268058564
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.692458526
Short name T252
Test name
Test status
Simulation time 2167886299 ps
CPU time 7.67 seconds
Started Jul 01 04:42:18 PM PDT 24
Finished Jul 01 04:42:32 PM PDT 24
Peak memory 217412 kb
Host smart-f883f723-da6a-4b87-a9c3-5066f53afbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692458526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.692458526
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.687394505
Short name T210
Test name
Test status
Simulation time 245367957 ps
CPU time 1.07 seconds
Started Jul 01 04:42:19 PM PDT 24
Finished Jul 01 04:42:27 PM PDT 24
Peak memory 217396 kb
Host smart-7bd458f1-07dd-4fd6-b8dc-4d7fd11c52b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687394505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.687394505
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3934890585
Short name T486
Test name
Test status
Simulation time 196285403 ps
CPU time 0.95 seconds
Started Jul 01 04:42:19 PM PDT 24
Finished Jul 01 04:42:27 PM PDT 24
Peak memory 199848 kb
Host smart-e0c4fecb-8a4c-428d-91ad-aed55a6ad6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934890585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3934890585
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1697592557
Short name T403
Test name
Test status
Simulation time 1612172097 ps
CPU time 5.56 seconds
Started Jul 01 04:42:16 PM PDT 24
Finished Jul 01 04:42:25 PM PDT 24
Peak memory 200272 kb
Host smart-04c17f38-9ea8-4b3a-9b20-f6441068bdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697592557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1697592557
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.659447543
Short name T477
Test name
Test status
Simulation time 173359675 ps
CPU time 1.13 seconds
Started Jul 01 04:42:16 PM PDT 24
Finished Jul 01 04:42:22 PM PDT 24
Peak memory 200048 kb
Host smart-c7ce0c2d-3dcf-40a9-86e4-5e94bd02deb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659447543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.659447543
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2232002073
Short name T123
Test name
Test status
Simulation time 248790200 ps
CPU time 1.51 seconds
Started Jul 01 04:42:18 PM PDT 24
Finished Jul 01 04:42:25 PM PDT 24
Peak memory 200348 kb
Host smart-f1543022-4c87-4b27-8cc6-0d6ef53898c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232002073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2232002073
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1800246522
Short name T98
Test name
Test status
Simulation time 1544134733 ps
CPU time 7.42 seconds
Started Jul 01 04:42:19 PM PDT 24
Finished Jul 01 04:42:33 PM PDT 24
Peak memory 200300 kb
Host smart-b620bb88-b1c7-4e9b-b6a9-2e482cddd232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800246522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1800246522
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1589405159
Short name T258
Test name
Test status
Simulation time 490904947 ps
CPU time 2.78 seconds
Started Jul 01 04:42:19 PM PDT 24
Finished Jul 01 04:42:29 PM PDT 24
Peak memory 200000 kb
Host smart-c1b7d937-f4d8-4949-88dc-a4f23188d0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589405159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1589405159
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.59840347
Short name T340
Test name
Test status
Simulation time 107290929 ps
CPU time 1.01 seconds
Started Jul 01 04:42:18 PM PDT 24
Finished Jul 01 04:42:25 PM PDT 24
Peak memory 200156 kb
Host smart-5260f03d-000a-45f6-851b-5b94c983f5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59840347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.59840347
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3526827374
Short name T151
Test name
Test status
Simulation time 71191069 ps
CPU time 0.78 seconds
Started Jul 01 04:42:19 PM PDT 24
Finished Jul 01 04:42:26 PM PDT 24
Peak memory 199832 kb
Host smart-50bbe447-8112-4dc3-9ad0-f1bc1578ef1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526827374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3526827374
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2194848872
Short name T314
Test name
Test status
Simulation time 2177174539 ps
CPU time 7.68 seconds
Started Jul 01 04:42:14 PM PDT 24
Finished Jul 01 04:42:25 PM PDT 24
Peak memory 217012 kb
Host smart-641042a0-0f7f-4f91-9496-94cd0827d1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194848872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2194848872
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1356316596
Short name T423
Test name
Test status
Simulation time 244196823 ps
CPU time 1.14 seconds
Started Jul 01 04:42:17 PM PDT 24
Finished Jul 01 04:42:24 PM PDT 24
Peak memory 217384 kb
Host smart-5dff1ec8-782a-46ba-a6d3-10126e0752a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356316596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1356316596
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.417979558
Short name T344
Test name
Test status
Simulation time 160040725 ps
CPU time 0.81 seconds
Started Jul 01 04:42:16 PM PDT 24
Finished Jul 01 04:42:22 PM PDT 24
Peak memory 199852 kb
Host smart-47487bdb-172d-434c-9575-01eca6220c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417979558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.417979558
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2824944154
Short name T446
Test name
Test status
Simulation time 837239420 ps
CPU time 4.31 seconds
Started Jul 01 04:42:19 PM PDT 24
Finished Jul 01 04:42:28 PM PDT 24
Peak memory 200260 kb
Host smart-d3eccea0-09b6-40b1-805c-afc254c167ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824944154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2824944154
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1963324675
Short name T256
Test name
Test status
Simulation time 172203605 ps
CPU time 1.18 seconds
Started Jul 01 04:42:17 PM PDT 24
Finished Jul 01 04:42:24 PM PDT 24
Peak memory 200140 kb
Host smart-ed63ce6b-0308-48b9-b2ab-7cd2cb977949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963324675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1963324675
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4012433590
Short name T400
Test name
Test status
Simulation time 122400495 ps
CPU time 1.18 seconds
Started Jul 01 04:42:17 PM PDT 24
Finished Jul 01 04:42:24 PM PDT 24
Peak memory 200264 kb
Host smart-f983fc72-6672-45c3-a9f7-3aae4b34d3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012433590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4012433590
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3570394512
Short name T51
Test name
Test status
Simulation time 9376520843 ps
CPU time 30.47 seconds
Started Jul 01 04:42:19 PM PDT 24
Finished Jul 01 04:42:55 PM PDT 24
Peak memory 208552 kb
Host smart-f3945b24-fc2c-4465-84d4-e1a60f25d229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570394512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3570394512
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2919075208
Short name T419
Test name
Test status
Simulation time 120497406 ps
CPU time 1.52 seconds
Started Jul 01 04:42:18 PM PDT 24
Finished Jul 01 04:42:25 PM PDT 24
Peak memory 200024 kb
Host smart-60ddda48-900d-45f0-ac1c-97206cba211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919075208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2919075208
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2307468210
Short name T191
Test name
Test status
Simulation time 195621918 ps
CPU time 1.19 seconds
Started Jul 01 04:42:15 PM PDT 24
Finished Jul 01 04:42:19 PM PDT 24
Peak memory 199940 kb
Host smart-92278356-02a6-46d9-9eaf-631bfff05d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307468210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2307468210
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1365514956
Short name T169
Test name
Test status
Simulation time 77655323 ps
CPU time 0.84 seconds
Started Jul 01 04:42:14 PM PDT 24
Finished Jul 01 04:42:18 PM PDT 24
Peak memory 199836 kb
Host smart-ccac39e0-cfce-46d9-8199-11cd446401f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365514956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1365514956
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.220964787
Short name T126
Test name
Test status
Simulation time 1901539630 ps
CPU time 7.15 seconds
Started Jul 01 04:42:18 PM PDT 24
Finished Jul 01 04:42:30 PM PDT 24
Peak memory 221520 kb
Host smart-b6e07d5d-952f-4251-9763-d21aa7d5608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220964787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.220964787
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.77661985
Short name T424
Test name
Test status
Simulation time 243773508 ps
CPU time 1.1 seconds
Started Jul 01 04:42:16 PM PDT 24
Finished Jul 01 04:42:21 PM PDT 24
Peak memory 217392 kb
Host smart-a1347350-0165-4a9e-bcbd-dda55bd6f417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77661985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.77661985
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2808534889
Short name T266
Test name
Test status
Simulation time 98370931 ps
CPU time 0.72 seconds
Started Jul 01 04:42:18 PM PDT 24
Finished Jul 01 04:42:24 PM PDT 24
Peak memory 199848 kb
Host smart-78a24e18-797d-40ab-958b-1377d884fc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808534889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2808534889
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2612424524
Short name T96
Test name
Test status
Simulation time 970238112 ps
CPU time 4.77 seconds
Started Jul 01 04:42:15 PM PDT 24
Finished Jul 01 04:42:24 PM PDT 24
Peak memory 200260 kb
Host smart-fa523dea-6dc2-4c7f-8d5d-2e13faeda846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612424524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2612424524
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.782854770
Short name T270
Test name
Test status
Simulation time 174120184 ps
CPU time 1.2 seconds
Started Jul 01 04:42:19 PM PDT 24
Finished Jul 01 04:42:26 PM PDT 24
Peak memory 200044 kb
Host smart-70adc60b-ae41-4aa0-95ec-8b39471bf87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782854770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.782854770
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.870745845
Short name T178
Test name
Test status
Simulation time 121319704 ps
CPU time 1.26 seconds
Started Jul 01 04:42:17 PM PDT 24
Finished Jul 01 04:42:23 PM PDT 24
Peak memory 200232 kb
Host smart-f186ab08-8bfd-48f3-accd-7954171e0f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870745845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.870745845
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2138837959
Short name T421
Test name
Test status
Simulation time 6664302381 ps
CPU time 28.9 seconds
Started Jul 01 04:42:17 PM PDT 24
Finished Jul 01 04:42:50 PM PDT 24
Peak memory 216512 kb
Host smart-ad873e1c-083f-4d20-a05e-e87cafd03eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138837959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2138837959
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.541940537
Short name T10
Test name
Test status
Simulation time 431860817 ps
CPU time 2.43 seconds
Started Jul 01 04:42:16 PM PDT 24
Finished Jul 01 04:42:23 PM PDT 24
Peak memory 208500 kb
Host smart-158045e0-6d72-431e-83ce-a7ae972c24ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541940537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.541940537
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1607574084
Short name T444
Test name
Test status
Simulation time 147199192 ps
CPU time 1.22 seconds
Started Jul 01 04:42:19 PM PDT 24
Finished Jul 01 04:42:27 PM PDT 24
Peak memory 200244 kb
Host smart-1e0ee71e-9afa-43e5-bf1a-cd6ac588e1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607574084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1607574084
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.515348878
Short name T177
Test name
Test status
Simulation time 65105255 ps
CPU time 0.81 seconds
Started Jul 01 04:42:23 PM PDT 24
Finished Jul 01 04:42:35 PM PDT 24
Peak memory 199724 kb
Host smart-d374bdb5-9c15-4b7a-83bf-c03f0468722c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515348878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.515348878
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3209706607
Short name T526
Test name
Test status
Simulation time 2350208715 ps
CPU time 7.88 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 04:42:50 PM PDT 24
Peak memory 221684 kb
Host smart-a750a752-b2b1-466a-9244-d1bbcd20e034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209706607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3209706607
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3634936773
Short name T16
Test name
Test status
Simulation time 244454196 ps
CPU time 1.07 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:42:38 PM PDT 24
Peak memory 217384 kb
Host smart-f22bf43b-db45-4bad-846e-af8c13f7b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634936773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3634936773
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3399965731
Short name T437
Test name
Test status
Simulation time 136606914 ps
CPU time 0.79 seconds
Started Jul 01 04:42:17 PM PDT 24
Finished Jul 01 04:42:24 PM PDT 24
Peak memory 199812 kb
Host smart-23adb913-2856-46d1-9294-658d37bddd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399965731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3399965731
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.700897569
Short name T411
Test name
Test status
Simulation time 733462499 ps
CPU time 4.03 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:42:41 PM PDT 24
Peak memory 200284 kb
Host smart-f8324b5b-7f5a-45a0-82a9-002c80308224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700897569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.700897569
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.191801485
Short name T179
Test name
Test status
Simulation time 139110622 ps
CPU time 1.22 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:42:38 PM PDT 24
Peak memory 200036 kb
Host smart-0eb10fbd-e2f9-4629-88ae-c54368285d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191801485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.191801485
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3062600288
Short name T479
Test name
Test status
Simulation time 198951736 ps
CPU time 1.39 seconds
Started Jul 01 04:42:17 PM PDT 24
Finished Jul 01 04:42:24 PM PDT 24
Peak memory 200164 kb
Host smart-96d7b849-178a-4786-afba-bd73676671da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062600288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3062600288
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.593000817
Short name T492
Test name
Test status
Simulation time 121485618 ps
CPU time 1.46 seconds
Started Jul 01 04:42:22 PM PDT 24
Finished Jul 01 04:42:32 PM PDT 24
Peak memory 200072 kb
Host smart-db2658d8-9dd9-4e2d-b961-931c403f6f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593000817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.593000817
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3290487473
Short name T529
Test name
Test status
Simulation time 175064218 ps
CPU time 1.23 seconds
Started Jul 01 04:42:24 PM PDT 24
Finished Jul 01 04:42:37 PM PDT 24
Peak memory 200036 kb
Host smart-48531744-bf07-4824-9082-6ede923408c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290487473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3290487473
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3164766294
Short name T263
Test name
Test status
Simulation time 77124629 ps
CPU time 0.77 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 04:42:41 PM PDT 24
Peak memory 199824 kb
Host smart-95681e00-9336-4a7d-a5b6-e601bd9ae585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164766294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3164766294
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2549893443
Short name T33
Test name
Test status
Simulation time 1894091992 ps
CPU time 6.87 seconds
Started Jul 01 04:42:28 PM PDT 24
Finished Jul 01 04:42:53 PM PDT 24
Peak memory 216956 kb
Host smart-d3dc9c1f-035a-49f3-bba9-681e6420a2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549893443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2549893443
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.19106702
Short name T203
Test name
Test status
Simulation time 244773372 ps
CPU time 1.06 seconds
Started Jul 01 04:42:23 PM PDT 24
Finished Jul 01 04:42:32 PM PDT 24
Peak memory 217400 kb
Host smart-9beea5b5-72d3-4474-8719-fa60a881d0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19106702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.19106702
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3445082951
Short name T380
Test name
Test status
Simulation time 201860478 ps
CPU time 0.89 seconds
Started Jul 01 04:42:23 PM PDT 24
Finished Jul 01 04:42:32 PM PDT 24
Peak memory 199960 kb
Host smart-e8744f29-dcc4-4261-8897-8b3a231e9831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445082951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3445082951
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2923600616
Short name T287
Test name
Test status
Simulation time 2193252743 ps
CPU time 7.56 seconds
Started Jul 01 04:42:23 PM PDT 24
Finished Jul 01 04:42:39 PM PDT 24
Peak memory 200312 kb
Host smart-e0481c4c-1396-4e34-9253-65921dad5eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923600616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2923600616
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.327103907
Short name T291
Test name
Test status
Simulation time 109582706 ps
CPU time 1.01 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:42:38 PM PDT 24
Peak memory 200036 kb
Host smart-dba7c611-7178-465c-a73c-1a077c85fb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327103907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.327103907
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.749758454
Short name T189
Test name
Test status
Simulation time 221870232 ps
CPU time 1.47 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:42:41 PM PDT 24
Peak memory 200308 kb
Host smart-7da618d8-f599-4817-9e71-abbc83ff518a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749758454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.749758454
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1470769977
Short name T95
Test name
Test status
Simulation time 8636053436 ps
CPU time 29.08 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 04:43:09 PM PDT 24
Peak memory 200476 kb
Host smart-6a5850be-0980-43e9-8705-8b61975245b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470769977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1470769977
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2562068017
Short name T401
Test name
Test status
Simulation time 359858517 ps
CPU time 2.41 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:42:40 PM PDT 24
Peak memory 200028 kb
Host smart-f0303c7b-7a7b-4bc1-9d5c-9d557a6e8348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562068017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2562068017
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.530566855
Short name T387
Test name
Test status
Simulation time 94064602 ps
CPU time 0.86 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 04:42:41 PM PDT 24
Peak memory 200140 kb
Host smart-ff3d0130-10af-4c37-9f90-d95c2b6a1202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530566855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.530566855
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1052810411
Short name T172
Test name
Test status
Simulation time 73829853 ps
CPU time 0.81 seconds
Started Jul 01 04:42:23 PM PDT 24
Finished Jul 01 04:42:32 PM PDT 24
Peak memory 199836 kb
Host smart-fe6c9b0a-ccfe-43f2-bebc-3afb30313e99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052810411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1052810411
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.703215029
Short name T131
Test name
Test status
Simulation time 244458272 ps
CPU time 1.04 seconds
Started Jul 01 04:42:24 PM PDT 24
Finished Jul 01 04:42:36 PM PDT 24
Peak memory 217396 kb
Host smart-1b441c49-3c27-4914-8ed6-399af0a1ca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703215029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.703215029
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2019367454
Short name T23
Test name
Test status
Simulation time 168164853 ps
CPU time 0.92 seconds
Started Jul 01 04:42:23 PM PDT 24
Finished Jul 01 04:42:32 PM PDT 24
Peak memory 199820 kb
Host smart-37a20b29-095e-40e6-a12b-f3a5c977b99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019367454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2019367454
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.378067262
Short name T93
Test name
Test status
Simulation time 1224215276 ps
CPU time 4.54 seconds
Started Jul 01 04:42:24 PM PDT 24
Finished Jul 01 04:42:39 PM PDT 24
Peak memory 200328 kb
Host smart-b70cedb4-0c4e-4146-8705-21a25e3d4856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378067262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.378067262
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3934832820
Short name T451
Test name
Test status
Simulation time 100941013 ps
CPU time 0.95 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:42:38 PM PDT 24
Peak memory 200020 kb
Host smart-7f6fc2ed-d9e8-4396-91b6-3bc479f6f334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934832820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3934832820
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.4226820167
Short name T480
Test name
Test status
Simulation time 198032854 ps
CPU time 1.32 seconds
Started Jul 01 04:42:22 PM PDT 24
Finished Jul 01 04:42:32 PM PDT 24
Peak memory 200220 kb
Host smart-e7b7a479-da32-4d1d-b567-7cb0b26492fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226820167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.4226820167
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3054644825
Short name T425
Test name
Test status
Simulation time 2588050530 ps
CPU time 8.94 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 04:42:51 PM PDT 24
Peak memory 208544 kb
Host smart-3804b1d8-41bc-4743-a50f-a43b29c7bce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054644825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3054644825
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.631687885
Short name T3
Test name
Test status
Simulation time 133858489 ps
CPU time 1.67 seconds
Started Jul 01 04:42:24 PM PDT 24
Finished Jul 01 04:42:37 PM PDT 24
Peak memory 200028 kb
Host smart-ec6a84c9-d4d6-4ea4-8944-ea2edc764b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631687885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.631687885
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3166632012
Short name T426
Test name
Test status
Simulation time 151784500 ps
CPU time 1.23 seconds
Started Jul 01 04:42:23 PM PDT 24
Finished Jul 01 04:42:35 PM PDT 24
Peak memory 200296 kb
Host smart-ac097e82-13cb-4e0b-bfd9-a8477b53cd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166632012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3166632012
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1827249343
Short name T335
Test name
Test status
Simulation time 67080753 ps
CPU time 0.78 seconds
Started Jul 01 04:41:03 PM PDT 24
Finished Jul 01 04:41:05 PM PDT 24
Peak memory 199804 kb
Host smart-5682f65a-4e6c-4d07-acff-042fe4d546a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827249343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1827249343
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2633431454
Short name T44
Test name
Test status
Simulation time 2183586350 ps
CPU time 7.99 seconds
Started Jul 01 04:41:01 PM PDT 24
Finished Jul 01 04:41:12 PM PDT 24
Peak memory 217812 kb
Host smart-cce6d288-90a4-48c6-8c71-cd6574433dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633431454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2633431454
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3674184773
Short name T212
Test name
Test status
Simulation time 248981966 ps
CPU time 1.11 seconds
Started Jul 01 04:41:01 PM PDT 24
Finished Jul 01 04:41:05 PM PDT 24
Peak memory 217404 kb
Host smart-4b5b6ce6-1b2c-4227-abd5-bee2330ac936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674184773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3674184773
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3285313127
Short name T532
Test name
Test status
Simulation time 105147916 ps
CPU time 0.8 seconds
Started Jul 01 04:40:52 PM PDT 24
Finished Jul 01 04:40:56 PM PDT 24
Peak memory 199832 kb
Host smart-93003f24-aeb5-4232-8cec-a73c876bf141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285313127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3285313127
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1230761611
Short name T158
Test name
Test status
Simulation time 1382961516 ps
CPU time 5.45 seconds
Started Jul 01 04:40:54 PM PDT 24
Finished Jul 01 04:41:03 PM PDT 24
Peak memory 200200 kb
Host smart-d8af010e-4d25-4c01-9330-bed7e7feeb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230761611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1230761611
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2282753650
Short name T395
Test name
Test status
Simulation time 163363225 ps
CPU time 1.17 seconds
Started Jul 01 04:41:01 PM PDT 24
Finished Jul 01 04:41:04 PM PDT 24
Peak memory 200080 kb
Host smart-72cc824d-e6cc-49d4-a06a-fe4fc82b1662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282753650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2282753650
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3119306976
Short name T56
Test name
Test status
Simulation time 248040047 ps
CPU time 1.46 seconds
Started Jul 01 04:40:53 PM PDT 24
Finished Jul 01 04:40:58 PM PDT 24
Peak memory 200132 kb
Host smart-d3d5dcbe-60d3-432a-8b49-e1f534a80dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119306976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3119306976
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.51376884
Short name T502
Test name
Test status
Simulation time 6884505472 ps
CPU time 29.25 seconds
Started Jul 01 04:41:01 PM PDT 24
Finished Jul 01 04:41:32 PM PDT 24
Peak memory 208488 kb
Host smart-565a9ab6-eda5-4bad-889c-d6ce719417e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51376884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.51376884
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2048654736
Short name T79
Test name
Test status
Simulation time 358819713 ps
CPU time 2.13 seconds
Started Jul 01 04:41:00 PM PDT 24
Finished Jul 01 04:41:04 PM PDT 24
Peak memory 200032 kb
Host smart-6c651d9c-046b-456e-b5ca-a7cc67462100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048654736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2048654736
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2687541472
Short name T262
Test name
Test status
Simulation time 105068195 ps
CPU time 1.05 seconds
Started Jul 01 04:40:58 PM PDT 24
Finished Jul 01 04:41:01 PM PDT 24
Peak memory 200032 kb
Host smart-c9e4572a-298f-4300-bd84-5d4d3c9e68da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687541472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2687541472
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2854675147
Short name T190
Test name
Test status
Simulation time 65994576 ps
CPU time 0.81 seconds
Started Jul 01 04:40:59 PM PDT 24
Finished Jul 01 04:41:02 PM PDT 24
Peak memory 199820 kb
Host smart-1f4b9df0-21ab-466f-8de7-5509548c4416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854675147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2854675147
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3482162770
Short name T475
Test name
Test status
Simulation time 2173796444 ps
CPU time 8.29 seconds
Started Jul 01 04:41:01 PM PDT 24
Finished Jul 01 04:41:11 PM PDT 24
Peak memory 217816 kb
Host smart-e435eed5-c509-4caa-9521-47259c3a8042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482162770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3482162770
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3741208893
Short name T148
Test name
Test status
Simulation time 244241850 ps
CPU time 1.07 seconds
Started Jul 01 04:41:01 PM PDT 24
Finished Jul 01 04:41:04 PM PDT 24
Peak memory 217440 kb
Host smart-c3ab213c-6dda-4dcf-8145-e76f0247ad01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741208893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3741208893
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.4046190540
Short name T206
Test name
Test status
Simulation time 211190460 ps
CPU time 0.95 seconds
Started Jul 01 04:41:00 PM PDT 24
Finished Jul 01 04:41:03 PM PDT 24
Peak memory 199920 kb
Host smart-6c531893-22f3-42b0-be45-01943e054009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046190540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.4046190540
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3852481496
Short name T236
Test name
Test status
Simulation time 1631296295 ps
CPU time 6.13 seconds
Started Jul 01 04:41:02 PM PDT 24
Finished Jul 01 04:41:10 PM PDT 24
Peak memory 200348 kb
Host smart-23b099fb-124c-42af-8651-1976f63244b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852481496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3852481496
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3222561904
Short name T288
Test name
Test status
Simulation time 136821283 ps
CPU time 1.13 seconds
Started Jul 01 04:40:59 PM PDT 24
Finished Jul 01 04:41:02 PM PDT 24
Peak memory 199936 kb
Host smart-97e3eb73-bd21-4421-820c-0c8760f31557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222561904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3222561904
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2757832332
Short name T134
Test name
Test status
Simulation time 112489855 ps
CPU time 1.26 seconds
Started Jul 01 04:40:59 PM PDT 24
Finished Jul 01 04:41:02 PM PDT 24
Peak memory 200184 kb
Host smart-fc59b33f-e770-4312-a69f-193c26d96d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757832332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2757832332
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3568572175
Short name T388
Test name
Test status
Simulation time 1746963267 ps
CPU time 6.66 seconds
Started Jul 01 04:41:01 PM PDT 24
Finished Jul 01 04:41:10 PM PDT 24
Peak memory 200260 kb
Host smart-2d145776-feec-46d4-8d23-bc02ccb585ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568572175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3568572175
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3016344993
Short name T292
Test name
Test status
Simulation time 371584731 ps
CPU time 2.17 seconds
Started Jul 01 04:41:01 PM PDT 24
Finished Jul 01 04:41:05 PM PDT 24
Peak memory 200024 kb
Host smart-5c2a27c3-36de-4f36-9edb-958a9f4a7035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016344993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3016344993
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3935280733
Short name T520
Test name
Test status
Simulation time 62280320 ps
CPU time 0.81 seconds
Started Jul 01 04:41:00 PM PDT 24
Finished Jul 01 04:41:03 PM PDT 24
Peak memory 200028 kb
Host smart-13f1510a-eaab-49d8-8ed1-f934faae9863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935280733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3935280733
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.283756061
Short name T141
Test name
Test status
Simulation time 60995848 ps
CPU time 0.89 seconds
Started Jul 01 04:41:12 PM PDT 24
Finished Jul 01 04:41:16 PM PDT 24
Peak memory 199820 kb
Host smart-3093ee5f-d0fc-4dc1-99c6-edccda7e1631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283756061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.283756061
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1408698072
Short name T42
Test name
Test status
Simulation time 1904205455 ps
CPU time 6.79 seconds
Started Jul 01 04:40:58 PM PDT 24
Finished Jul 01 04:41:07 PM PDT 24
Peak memory 221632 kb
Host smart-ca553ef8-a676-4fcd-b81a-67eebfa9be86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408698072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1408698072
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.68576881
Short name T489
Test name
Test status
Simulation time 245823446 ps
CPU time 1.04 seconds
Started Jul 01 04:41:10 PM PDT 24
Finished Jul 01 04:41:14 PM PDT 24
Peak memory 217316 kb
Host smart-8d5737c2-39e6-49b3-8e66-9d461e03a625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68576881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.68576881
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1346502805
Short name T218
Test name
Test status
Simulation time 172992693 ps
CPU time 0.88 seconds
Started Jul 01 04:40:58 PM PDT 24
Finished Jul 01 04:41:01 PM PDT 24
Peak memory 199844 kb
Host smart-ab42572e-479f-419b-b879-bf7c48bc01bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346502805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1346502805
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2413706913
Short name T294
Test name
Test status
Simulation time 1966040024 ps
CPU time 7.07 seconds
Started Jul 01 04:40:59 PM PDT 24
Finished Jul 01 04:41:08 PM PDT 24
Peak memory 200292 kb
Host smart-649114c0-9869-41a4-8bfb-339a64138719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413706913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2413706913
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2950586157
Short name T322
Test name
Test status
Simulation time 179033153 ps
CPU time 1.25 seconds
Started Jul 01 04:40:57 PM PDT 24
Finished Jul 01 04:41:01 PM PDT 24
Peak memory 200040 kb
Host smart-6e4a524e-1187-44a1-81f2-14fbe646aa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950586157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2950586157
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2081960700
Short name T474
Test name
Test status
Simulation time 244788173 ps
CPU time 1.6 seconds
Started Jul 01 04:41:00 PM PDT 24
Finished Jul 01 04:41:04 PM PDT 24
Peak memory 200356 kb
Host smart-ab348a0e-ea29-4973-ae90-6d230f5e38ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081960700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2081960700
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.373661693
Short name T476
Test name
Test status
Simulation time 10511188891 ps
CPU time 35.42 seconds
Started Jul 01 04:41:09 PM PDT 24
Finished Jul 01 04:41:47 PM PDT 24
Peak memory 200488 kb
Host smart-c0f5aac8-2c14-4ee3-8eb0-43d4c627f240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373661693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.373661693
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3666813527
Short name T484
Test name
Test status
Simulation time 135784976 ps
CPU time 1.81 seconds
Started Jul 01 04:41:03 PM PDT 24
Finished Jul 01 04:41:06 PM PDT 24
Peak memory 200000 kb
Host smart-200ec934-2c2e-448e-85e9-caea090a6c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666813527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3666813527
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2362923286
Short name T504
Test name
Test status
Simulation time 127868999 ps
CPU time 1 seconds
Started Jul 01 04:41:02 PM PDT 24
Finished Jul 01 04:41:05 PM PDT 24
Peak memory 200028 kb
Host smart-9f5df57a-af1a-4526-80a1-6652e3a1574e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362923286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2362923286
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1472614258
Short name T382
Test name
Test status
Simulation time 75740462 ps
CPU time 0.8 seconds
Started Jul 01 04:41:08 PM PDT 24
Finished Jul 01 04:41:11 PM PDT 24
Peak memory 199824 kb
Host smart-a4d8c65a-5c51-4f1d-b5d9-ad2c0eb33cde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472614258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1472614258
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3275205459
Short name T370
Test name
Test status
Simulation time 1222382546 ps
CPU time 5.77 seconds
Started Jul 01 04:41:09 PM PDT 24
Finished Jul 01 04:41:18 PM PDT 24
Peak memory 217724 kb
Host smart-9bb74c17-4e55-4c36-aea0-189ffa038574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275205459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3275205459
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3552860138
Short name T389
Test name
Test status
Simulation time 244458864 ps
CPU time 1.1 seconds
Started Jul 01 04:41:09 PM PDT 24
Finished Jul 01 04:41:13 PM PDT 24
Peak memory 217468 kb
Host smart-72772931-1893-4a83-8586-a813887336eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552860138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3552860138
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1719063494
Short name T249
Test name
Test status
Simulation time 138532241 ps
CPU time 0.81 seconds
Started Jul 01 04:41:10 PM PDT 24
Finished Jul 01 04:41:13 PM PDT 24
Peak memory 199908 kb
Host smart-d960bd27-dfaf-4cc1-b5fe-10ba21477545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719063494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1719063494
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2440421362
Short name T469
Test name
Test status
Simulation time 1527839570 ps
CPU time 5.97 seconds
Started Jul 01 04:41:16 PM PDT 24
Finished Jul 01 04:41:25 PM PDT 24
Peak memory 200284 kb
Host smart-2a207e54-a310-45d2-97e9-b61f4b7e0334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440421362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2440421362
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1363806993
Short name T462
Test name
Test status
Simulation time 136702734 ps
CPU time 1.16 seconds
Started Jul 01 04:41:11 PM PDT 24
Finished Jul 01 04:41:16 PM PDT 24
Peak memory 200032 kb
Host smart-f03e46e7-6e29-40f4-8494-839c8463c600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363806993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1363806993
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.587572925
Short name T149
Test name
Test status
Simulation time 198775337 ps
CPU time 1.53 seconds
Started Jul 01 04:41:11 PM PDT 24
Finished Jul 01 04:41:16 PM PDT 24
Peak memory 200156 kb
Host smart-4e04503d-df24-4226-b006-96f1ffb1b9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587572925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.587572925
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2425351771
Short name T465
Test name
Test status
Simulation time 2467433293 ps
CPU time 11.62 seconds
Started Jul 01 04:41:10 PM PDT 24
Finished Jul 01 04:41:25 PM PDT 24
Peak memory 216448 kb
Host smart-4c2dfc46-e694-42bc-9891-eb433cf8ecc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425351771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2425351771
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.417732083
Short name T305
Test name
Test status
Simulation time 500578560 ps
CPU time 2.74 seconds
Started Jul 01 04:41:09 PM PDT 24
Finished Jul 01 04:41:14 PM PDT 24
Peak memory 199944 kb
Host smart-277dc8f9-f3ad-4af1-aef8-c9ec281e3728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417732083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.417732083
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3121712391
Short name T515
Test name
Test status
Simulation time 140415314 ps
CPU time 1.11 seconds
Started Jul 01 04:41:10 PM PDT 24
Finished Jul 01 04:41:14 PM PDT 24
Peak memory 200016 kb
Host smart-8c91710d-5e33-4ac9-8be8-f0a137387c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121712391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3121712391
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.4191036904
Short name T385
Test name
Test status
Simulation time 79448673 ps
CPU time 0.8 seconds
Started Jul 01 04:41:09 PM PDT 24
Finished Jul 01 04:41:12 PM PDT 24
Peak memory 199828 kb
Host smart-47a26d3d-05d9-47e7-8af1-0d6ca1e796dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191036904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.4191036904
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.279931323
Short name T74
Test name
Test status
Simulation time 1239823610 ps
CPU time 5.42 seconds
Started Jul 01 04:41:14 PM PDT 24
Finished Jul 01 04:41:23 PM PDT 24
Peak memory 217540 kb
Host smart-a200399d-7973-4570-bc72-f931944e2896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279931323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.279931323
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.652926175
Short name T429
Test name
Test status
Simulation time 244368418 ps
CPU time 1.05 seconds
Started Jul 01 04:41:14 PM PDT 24
Finished Jul 01 04:41:19 PM PDT 24
Peak memory 217396 kb
Host smart-d41485fe-c18a-426e-bf1f-7994264022e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652926175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.652926175
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3423946942
Short name T193
Test name
Test status
Simulation time 224444534 ps
CPU time 0.97 seconds
Started Jul 01 04:41:09 PM PDT 24
Finished Jul 01 04:41:12 PM PDT 24
Peak memory 199952 kb
Host smart-4fbb0832-c9f7-4dac-a10b-8fbf8090ff8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423946942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3423946942
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1479401111
Short name T233
Test name
Test status
Simulation time 1356800751 ps
CPU time 6.21 seconds
Started Jul 01 04:41:13 PM PDT 24
Finished Jul 01 04:41:23 PM PDT 24
Peak memory 200424 kb
Host smart-71ddc6f4-7acc-4d48-9165-9027cd9f0434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479401111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1479401111
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2983946014
Short name T406
Test name
Test status
Simulation time 114998865 ps
CPU time 1.13 seconds
Started Jul 01 04:41:12 PM PDT 24
Finished Jul 01 04:41:17 PM PDT 24
Peak memory 200120 kb
Host smart-c62707a2-d6af-498b-9f96-bc1ed9916456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983946014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2983946014
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1289825222
Short name T459
Test name
Test status
Simulation time 121939971 ps
CPU time 1.26 seconds
Started Jul 01 04:41:11 PM PDT 24
Finished Jul 01 04:41:15 PM PDT 24
Peak memory 200464 kb
Host smart-982eca88-269f-4cd6-99ab-956df681b86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289825222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1289825222
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3640555610
Short name T136
Test name
Test status
Simulation time 114079767 ps
CPU time 0.98 seconds
Started Jul 01 04:41:16 PM PDT 24
Finished Jul 01 04:41:20 PM PDT 24
Peak memory 199484 kb
Host smart-20fc5d1b-c2d9-4730-9869-b3f48cc3e220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640555610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3640555610
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.941786781
Short name T357
Test name
Test status
Simulation time 339081220 ps
CPU time 2.23 seconds
Started Jul 01 04:41:10 PM PDT 24
Finished Jul 01 04:41:15 PM PDT 24
Peak memory 208128 kb
Host smart-d8e13e0b-ee80-4eb5-8a9c-e51d2b493ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941786781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.941786781
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3301651224
Short name T279
Test name
Test status
Simulation time 264690750 ps
CPU time 1.52 seconds
Started Jul 01 04:41:10 PM PDT 24
Finished Jul 01 04:41:14 PM PDT 24
Peak memory 200008 kb
Host smart-ca82f40e-2bfc-4fd5-a020-c2518b26ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301651224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3301651224
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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