Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7551

1

T3

26

T4

39

T5

28

auto[1]

10478

1

T3

28

T4

28

T5

21

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5573	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6048	1			T1	1		T2	1		T3	27
reset_info_cp[2]	2752	1			T3	9		T4	8		T5	7
reset_info_cp[4]	3720	1			T3	7		T4	19		T5	9
reset_info_cp[8]	113	1			T3	1		T5	1		T7	1
reset_info_cp[16]	107	1			T7	2		T10	1		T94	1
reset_info_cp[32]	107	1			T4	2		T5	1		T7	2
reset_info_cp[64]	114	1			T4	1		T5	1		T36	1
reset_info_cp[128]	115	1			T16	1		T149	1		T158	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2937	1			T3	12		T4	10		T5	10
reset_info_cp[1]	auto[1]	2491	1			T3	14		T4	9		T5	8
reset_info_cp[2]	auto[0]	819	1			T3	5		T4	4		T5	4
reset_info_cp[2]	auto[1]	1933	1			T3	4		T4	4		T5	3
reset_info_cp[4]	auto[0]	1313	1			T3	3		T4	9		T5	5
reset_info_cp[4]	auto[1]	2407	1			T3	4		T4	10		T5	4
reset_info_cp[8]	auto[0]	43	1			T3	1		T7	1		T28	1
reset_info_cp[8]	auto[1]	70	1			T5	1		T149	1		T161	1
reset_info_cp[16]	auto[0]	44	1			T7	1		T27	2		T96	1
reset_info_cp[16]	auto[1]	63	1			T7	1		T10	1		T94	1
reset_info_cp[32]	auto[0]	44	1			T4	1		T5	1		T149	1
reset_info_cp[32]	auto[1]	63	1			T4	1		T7	2		T35	1
reset_info_cp[64]	auto[0]	46	1			T4	1		T159	1		T162	2
reset_info_cp[64]	auto[1]	68	1			T5	1		T36	1		T143	1
reset_info_cp[128]	auto[0]	49	1			T149	1		T60	1		T63	4
reset_info_cp[128]	auto[1]	66	1			T16	1		T158	1		T54	1