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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T542 /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2807213454 Jul 02 08:00:59 AM PDT 24 Jul 02 08:01:20 AM PDT 24 244701365 ps
T543 /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2485348926 Jul 02 08:01:28 AM PDT 24 Jul 02 08:01:48 AM PDT 24 101285219 ps
T544 /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.856135987 Jul 02 08:01:11 AM PDT 24 Jul 02 08:01:30 AM PDT 24 244996961 ps
T545 /workspace/coverage/default/2.rstmgr_por_stretcher.86432491 Jul 02 08:00:25 AM PDT 24 Jul 02 08:00:42 AM PDT 24 195274273 ps
T546 /workspace/coverage/default/32.rstmgr_smoke.1009914680 Jul 02 08:00:58 AM PDT 24 Jul 02 08:01:19 AM PDT 24 189193360 ps
T68 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2818855513 Jul 02 08:00:15 AM PDT 24 Jul 02 08:00:27 AM PDT 24 164608942 ps
T69 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1962291954 Jul 02 08:00:18 AM PDT 24 Jul 02 08:00:32 AM PDT 24 163201549 ps
T70 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4294811919 Jul 02 07:59:50 AM PDT 24 Jul 02 08:00:02 AM PDT 24 443983648 ps
T71 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.732366280 Jul 02 08:00:22 AM PDT 24 Jul 02 08:00:38 AM PDT 24 793488951 ps
T72 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3477508113 Jul 02 08:00:06 AM PDT 24 Jul 02 08:00:19 AM PDT 24 422899180 ps
T73 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3370495535 Jul 02 08:01:17 AM PDT 24 Jul 02 08:01:38 AM PDT 24 182994842 ps
T74 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2397704245 Jul 02 08:00:20 AM PDT 24 Jul 02 08:00:35 AM PDT 24 113747241 ps
T102 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3649852514 Jul 02 08:00:24 AM PDT 24 Jul 02 08:00:40 AM PDT 24 129779311 ps
T547 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3553816030 Jul 02 08:00:10 AM PDT 24 Jul 02 08:00:22 AM PDT 24 106524635 ps
T103 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1323657560 Jul 02 08:00:14 AM PDT 24 Jul 02 08:00:27 AM PDT 24 201824661 ps
T119 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1831464785 Jul 02 08:00:19 AM PDT 24 Jul 02 08:00:34 AM PDT 24 224148734 ps
T104 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1698139207 Jul 02 07:59:59 AM PDT 24 Jul 02 08:00:10 AM PDT 24 192821896 ps
T105 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2980961025 Jul 02 08:00:22 AM PDT 24 Jul 02 08:00:38 AM PDT 24 152775933 ps
T107 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3556980850 Jul 02 08:00:26 AM PDT 24 Jul 02 08:00:44 AM PDT 24 489277143 ps
T120 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3769630542 Jul 02 08:00:18 AM PDT 24 Jul 02 08:00:32 AM PDT 24 222069938 ps
T106 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2821696098 Jul 02 08:00:27 AM PDT 24 Jul 02 08:00:44 AM PDT 24 171316128 ps
T75 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.114853142 Jul 02 08:00:00 AM PDT 24 Jul 02 08:00:14 AM PDT 24 150608289 ps
T138 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2156464215 Jul 02 08:00:09 AM PDT 24 Jul 02 08:00:22 AM PDT 24 777445286 ps
T121 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3805061994 Jul 02 08:00:12 AM PDT 24 Jul 02 08:00:25 AM PDT 24 205070763 ps
T128 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3384852918 Jul 02 08:00:23 AM PDT 24 Jul 02 08:00:40 AM PDT 24 294822864 ps
T141 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1058297810 Jul 02 08:00:11 AM PDT 24 Jul 02 08:00:25 AM PDT 24 911702641 ps
T548 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.273065428 Jul 02 07:59:59 AM PDT 24 Jul 02 08:00:10 AM PDT 24 91117612 ps
T129 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.671613744 Jul 02 08:00:14 AM PDT 24 Jul 02 08:00:29 AM PDT 24 592150535 ps
T131 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1201246811 Jul 02 08:00:28 AM PDT 24 Jul 02 08:00:46 AM PDT 24 256067506 ps
T130 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3198859908 Jul 02 08:00:36 AM PDT 24 Jul 02 08:00:55 AM PDT 24 109315249 ps
T549 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1556294658 Jul 02 08:01:01 AM PDT 24 Jul 02 08:01:22 AM PDT 24 140780397 ps
T133 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1517028593 Jul 02 08:00:15 AM PDT 24 Jul 02 08:00:29 AM PDT 24 444835506 ps
T550 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2564841234 Jul 02 08:00:05 AM PDT 24 Jul 02 08:00:17 AM PDT 24 113359023 ps
T122 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.903844465 Jul 02 08:00:22 AM PDT 24 Jul 02 08:00:38 AM PDT 24 223316486 ps
T156 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.265451342 Jul 02 08:00:25 AM PDT 24 Jul 02 08:00:43 AM PDT 24 500575799 ps
T134 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.218441609 Jul 02 08:00:11 AM PDT 24 Jul 02 08:00:24 AM PDT 24 455748205 ps
T551 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2575324567 Jul 02 08:00:10 AM PDT 24 Jul 02 08:00:22 AM PDT 24 71412581 ps
T552 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3387801758 Jul 02 08:00:54 AM PDT 24 Jul 02 08:01:20 AM PDT 24 491032511 ps
T123 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1091428845 Jul 02 08:00:14 AM PDT 24 Jul 02 08:00:26 AM PDT 24 87991891 ps
T553 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3627118345 Jul 02 08:00:09 AM PDT 24 Jul 02 08:00:21 AM PDT 24 118365510 ps
T137 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1449757796 Jul 02 08:00:12 AM PDT 24 Jul 02 08:00:25 AM PDT 24 473358972 ps
T124 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1733167108 Jul 02 08:00:29 AM PDT 24 Jul 02 08:00:47 AM PDT 24 191523845 ps
T157 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3455596506 Jul 02 07:59:58 AM PDT 24 Jul 02 08:00:11 AM PDT 24 891249415 ps
T554 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1268130198 Jul 02 07:59:53 AM PDT 24 Jul 02 08:00:03 AM PDT 24 75194126 ps
T555 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1681346407 Jul 02 08:00:08 AM PDT 24 Jul 02 08:00:20 AM PDT 24 66980674 ps
T132 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4228081664 Jul 02 08:00:01 AM PDT 24 Jul 02 08:00:14 AM PDT 24 194326147 ps
T135 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3502158060 Jul 02 07:59:53 AM PDT 24 Jul 02 08:00:04 AM PDT 24 424701460 ps
T142 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.85106014 Jul 02 08:00:30 AM PDT 24 Jul 02 08:00:48 AM PDT 24 167986746 ps
T556 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2512069686 Jul 02 08:00:23 AM PDT 24 Jul 02 08:00:41 AM PDT 24 816486008 ps
T125 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1265807308 Jul 02 08:00:23 AM PDT 24 Jul 02 08:00:40 AM PDT 24 236196338 ps
T557 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3549740414 Jul 02 08:00:16 AM PDT 24 Jul 02 08:00:30 AM PDT 24 111022242 ps
T558 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3334940145 Jul 02 08:00:24 AM PDT 24 Jul 02 08:00:41 AM PDT 24 508577722 ps
T126 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2737656279 Jul 02 08:00:21 AM PDT 24 Jul 02 08:00:36 AM PDT 24 79480023 ps
T127 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3364964172 Jul 02 08:00:13 AM PDT 24 Jul 02 08:00:25 AM PDT 24 66867817 ps
T559 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3838778328 Jul 02 08:00:19 AM PDT 24 Jul 02 08:00:35 AM PDT 24 198695629 ps
T140 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.195386965 Jul 02 08:00:11 AM PDT 24 Jul 02 08:00:24 AM PDT 24 411866208 ps
T560 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.172246621 Jul 02 08:00:26 AM PDT 24 Jul 02 08:00:43 AM PDT 24 104110283 ps
T561 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3646939455 Jul 02 08:00:24 AM PDT 24 Jul 02 08:00:41 AM PDT 24 463127828 ps
T562 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2565401238 Jul 02 08:00:10 AM PDT 24 Jul 02 08:00:22 AM PDT 24 69367707 ps
T563 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2282950315 Jul 02 08:00:11 AM PDT 24 Jul 02 08:00:23 AM PDT 24 128068578 ps
T139 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1579816984 Jul 02 08:00:18 AM PDT 24 Jul 02 08:00:33 AM PDT 24 496040276 ps
T564 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1481162350 Jul 02 08:00:26 AM PDT 24 Jul 02 08:00:42 AM PDT 24 139496151 ps
T565 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3750739931 Jul 02 08:00:27 AM PDT 24 Jul 02 08:00:44 AM PDT 24 77649623 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.4225846834 Jul 02 08:00:00 AM PDT 24 Jul 02 08:00:16 AM PDT 24 487905013 ps
T567 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1720246871 Jul 02 08:00:07 AM PDT 24 Jul 02 08:00:22 AM PDT 24 868987182 ps
T568 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4158560744 Jul 02 08:00:09 AM PDT 24 Jul 02 08:00:21 AM PDT 24 68951290 ps
T569 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.621852396 Jul 02 07:59:58 AM PDT 24 Jul 02 08:00:10 AM PDT 24 234490345 ps
T570 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.297615554 Jul 02 08:00:14 AM PDT 24 Jul 02 08:00:28 AM PDT 24 166744847 ps
T571 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3177455529 Jul 02 08:00:12 AM PDT 24 Jul 02 08:00:26 AM PDT 24 276080361 ps
T572 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2604320570 Jul 02 08:00:23 AM PDT 24 Jul 02 08:00:41 AM PDT 24 187663025 ps
T573 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2380251525 Jul 02 08:00:20 AM PDT 24 Jul 02 08:00:37 AM PDT 24 174190675 ps
T574 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4016677760 Jul 02 08:00:28 AM PDT 24 Jul 02 08:00:46 AM PDT 24 127111471 ps
T108 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3524933382 Jul 02 08:00:22 AM PDT 24 Jul 02 08:00:37 AM PDT 24 84580794 ps
T575 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1931070854 Jul 02 08:01:19 AM PDT 24 Jul 02 08:01:40 AM PDT 24 493458684 ps
T576 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.512977615 Jul 02 08:01:08 AM PDT 24 Jul 02 08:01:29 AM PDT 24 363775835 ps
T577 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3803884380 Jul 02 08:00:02 AM PDT 24 Jul 02 08:00:15 AM PDT 24 154902366 ps
T578 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.345808369 Jul 02 08:00:06 AM PDT 24 Jul 02 08:00:19 AM PDT 24 200122186 ps
T579 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2854492102 Jul 02 08:00:01 AM PDT 24 Jul 02 08:00:17 AM PDT 24 797242774 ps
T580 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1857980487 Jul 02 08:00:21 AM PDT 24 Jul 02 08:00:36 AM PDT 24 236736991 ps
T581 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2752318821 Jul 02 08:00:22 AM PDT 24 Jul 02 08:00:37 AM PDT 24 200738890 ps
T582 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4119560826 Jul 02 08:00:09 AM PDT 24 Jul 02 08:00:22 AM PDT 24 109946027 ps
T583 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1697764531 Jul 02 08:00:13 AM PDT 24 Jul 02 08:00:25 AM PDT 24 83402198 ps
T584 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1028505775 Jul 02 08:00:19 AM PDT 24 Jul 02 08:00:34 AM PDT 24 188234166 ps
T585 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1595064771 Jul 02 08:00:00 AM PDT 24 Jul 02 08:00:11 AM PDT 24 121330985 ps
T586 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.468919236 Jul 02 08:00:26 AM PDT 24 Jul 02 08:00:43 AM PDT 24 116855205 ps
T587 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1440603681 Jul 02 08:00:10 AM PDT 24 Jul 02 08:00:23 AM PDT 24 125861306 ps
T588 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2213895418 Jul 02 08:00:16 AM PDT 24 Jul 02 08:00:28 AM PDT 24 72734865 ps
T589 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4004411693 Jul 02 08:00:06 AM PDT 24 Jul 02 08:00:18 AM PDT 24 140581022 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3436155356 Jul 02 08:00:05 AM PDT 24 Jul 02 08:00:20 AM PDT 24 803492557 ps
T591 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2934490812 Jul 02 08:00:14 AM PDT 24 Jul 02 08:00:28 AM PDT 24 799987629 ps
T592 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1968220738 Jul 02 07:59:57 AM PDT 24 Jul 02 08:00:08 AM PDT 24 107448086 ps
T593 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.776023715 Jul 02 08:00:24 AM PDT 24 Jul 02 08:00:40 AM PDT 24 98692710 ps
T594 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1524187050 Jul 02 08:00:16 AM PDT 24 Jul 02 08:00:29 AM PDT 24 112650089 ps
T595 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2822993829 Jul 02 08:00:10 AM PDT 24 Jul 02 08:00:22 AM PDT 24 71943285 ps
T596 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3296179801 Jul 02 08:00:21 AM PDT 24 Jul 02 08:00:37 AM PDT 24 107235662 ps
T597 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1486026886 Jul 02 08:00:25 AM PDT 24 Jul 02 08:00:41 AM PDT 24 98165605 ps
T598 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4086215547 Jul 02 08:00:13 AM PDT 24 Jul 02 08:00:25 AM PDT 24 151990529 ps
T599 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2178271556 Jul 02 08:00:19 AM PDT 24 Jul 02 08:00:33 AM PDT 24 78737180 ps
T600 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1521355687 Jul 02 08:00:20 AM PDT 24 Jul 02 08:00:40 AM PDT 24 139664841 ps
T601 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4196810938 Jul 02 08:00:24 AM PDT 24 Jul 02 08:00:40 AM PDT 24 59574471 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1120175956 Jul 02 08:00:22 AM PDT 24 Jul 02 08:00:38 AM PDT 24 426201540 ps
T603 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3544037923 Jul 02 08:00:13 AM PDT 24 Jul 02 08:00:27 AM PDT 24 313783164 ps
T604 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.116127852 Jul 02 08:00:07 AM PDT 24 Jul 02 08:00:20 AM PDT 24 324109987 ps
T605 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3293348920 Jul 02 08:00:14 AM PDT 24 Jul 02 08:00:27 AM PDT 24 113490312 ps
T606 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4170067170 Jul 02 08:00:18 AM PDT 24 Jul 02 08:00:33 AM PDT 24 245356750 ps
T607 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2958522376 Jul 02 08:00:20 AM PDT 24 Jul 02 08:00:35 AM PDT 24 142291319 ps
T608 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3281209738 Jul 02 08:00:23 AM PDT 24 Jul 02 08:00:40 AM PDT 24 121322167 ps
T609 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1858256666 Jul 02 08:01:12 AM PDT 24 Jul 02 08:01:32 AM PDT 24 62120136 ps
T610 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3758153255 Jul 02 08:00:15 AM PDT 24 Jul 02 08:00:27 AM PDT 24 81404455 ps
T611 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.943006426 Jul 02 08:00:18 AM PDT 24 Jul 02 08:00:34 AM PDT 24 896335385 ps
T612 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3555424665 Jul 02 08:00:31 AM PDT 24 Jul 02 08:00:49 AM PDT 24 104730552 ps
T613 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3712451467 Jul 02 08:00:05 AM PDT 24 Jul 02 08:00:16 AM PDT 24 63567322 ps
T614 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2804125510 Jul 02 08:00:17 AM PDT 24 Jul 02 08:00:30 AM PDT 24 115413744 ps
T615 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3765860391 Jul 02 08:01:09 AM PDT 24 Jul 02 08:01:29 AM PDT 24 67788089 ps
T616 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4143330068 Jul 02 08:00:11 AM PDT 24 Jul 02 08:00:23 AM PDT 24 87366614 ps
T617 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1759758609 Jul 02 08:00:05 AM PDT 24 Jul 02 08:00:17 AM PDT 24 218624582 ps
T618 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2803300608 Jul 02 08:00:10 AM PDT 24 Jul 02 08:00:31 AM PDT 24 2291713642 ps
T619 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.734257255 Jul 02 08:00:21 AM PDT 24 Jul 02 08:00:39 AM PDT 24 661489270 ps
T136 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3247497394 Jul 02 08:00:26 AM PDT 24 Jul 02 08:00:44 AM PDT 24 883737601 ps
T620 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2282149182 Jul 02 08:00:28 AM PDT 24 Jul 02 08:00:47 AM PDT 24 411282317 ps

Test location /workspace/coverage/default/17.rstmgr_stress_all.1075376121
Short name T7
Test name
Test status
Simulation time 5689613343 ps
CPU time 20.32 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:27 AM PDT 24
Peak memory 208668 kb
Host smart-04fe0b91-273b-49e9-a8d6-5f9b35b0ab97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075376121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1075376121
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.39499967
Short name T11
Test name
Test status
Simulation time 423579576 ps
CPU time 2.31 seconds
Started Jul 02 08:00:13 AM PDT 24
Finished Jul 02 08:00:26 AM PDT 24
Peak memory 208332 kb
Host smart-d158e6aa-d97c-4022-a20c-d1a147f8f88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39499967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.39499967
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.732366280
Short name T71
Test name
Test status
Simulation time 793488951 ps
CPU time 2.69 seconds
Started Jul 02 08:00:22 AM PDT 24
Finished Jul 02 08:00:38 AM PDT 24
Peak memory 200556 kb
Host smart-5245a4fc-3181-4e4c-9045-8e3797fc2e6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732366280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.732366280
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.989113355
Short name T81
Test name
Test status
Simulation time 8320476549 ps
CPU time 13.44 seconds
Started Jul 02 08:00:34 AM PDT 24
Finished Jul 02 08:01:04 AM PDT 24
Peak memory 217288 kb
Host smart-0c3417e7-fe27-4cb0-b065-00672e8cddcd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989113355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.989113355
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.518187699
Short name T36
Test name
Test status
Simulation time 1235043712 ps
CPU time 5.18 seconds
Started Jul 02 08:00:52 AM PDT 24
Finished Jul 02 08:01:18 AM PDT 24
Peak memory 217436 kb
Host smart-841547fe-c920-4e93-8b5d-a71bcfa6c228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518187699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.518187699
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.114853142
Short name T75
Test name
Test status
Simulation time 150608289 ps
CPU time 2.27 seconds
Started Jul 02 08:00:00 AM PDT 24
Finished Jul 02 08:00:14 AM PDT 24
Peak memory 208604 kb
Host smart-0628ae57-1ec5-4120-899d-b559a039aa88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114853142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.114853142
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2741633182
Short name T79
Test name
Test status
Simulation time 72871220 ps
CPU time 0.74 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:39 AM PDT 24
Peak memory 199952 kb
Host smart-3e0928f2-623a-4746-8d45-670e80d40dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741633182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2741633182
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_reset.4222745067
Short name T60
Test name
Test status
Simulation time 1860049536 ps
CPU time 7.41 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:07 AM PDT 24
Peak memory 200484 kb
Host smart-172386d3-2a22-4c7b-8eb8-97cb2b9260c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222745067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4222745067
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2309059107
Short name T161
Test name
Test status
Simulation time 105118170 ps
CPU time 1.01 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 200084 kb
Host smart-7ca93a31-b225-4d2c-9968-5e9d7b994e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309059107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2309059107
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3837870796
Short name T159
Test name
Test status
Simulation time 131564098 ps
CPU time 1.06 seconds
Started Jul 02 08:00:53 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 200104 kb
Host smart-01392b1e-fa6b-44e6-8f40-e0febe2aaf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837870796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3837870796
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2578800569
Short name T54
Test name
Test status
Simulation time 1226790762 ps
CPU time 5.56 seconds
Started Jul 02 08:00:29 AM PDT 24
Finished Jul 02 08:00:52 AM PDT 24
Peak memory 216884 kb
Host smart-87ce4be5-002a-4b1d-be1d-cee3c35db5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578800569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2578800569
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.297615554
Short name T570
Test name
Test status
Simulation time 166744847 ps
CPU time 2.58 seconds
Started Jul 02 08:00:14 AM PDT 24
Finished Jul 02 08:00:28 AM PDT 24
Peak memory 200308 kb
Host smart-ce8723c1-da3a-4651-a2b7-ee05d719374e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297615554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.297615554
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1058297810
Short name T141
Test name
Test status
Simulation time 911702641 ps
CPU time 3.52 seconds
Started Jul 02 08:00:11 AM PDT 24
Finished Jul 02 08:00:25 AM PDT 24
Peak memory 200296 kb
Host smart-afcc5a1a-44f6-4d76-b22d-6112b9810d06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058297810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1058297810
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3940315145
Short name T100
Test name
Test status
Simulation time 6100575853 ps
CPU time 27.7 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:02:02 AM PDT 24
Peak memory 208716 kb
Host smart-74b5c94a-92ae-4c4e-93ca-86757baf04eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940315145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3940315145
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2795901550
Short name T50
Test name
Test status
Simulation time 1233287033 ps
CPU time 5.91 seconds
Started Jul 02 08:00:57 AM PDT 24
Finished Jul 02 08:01:23 AM PDT 24
Peak memory 216856 kb
Host smart-94fbde9e-d46b-442f-8f33-fcb6cbd5397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795901550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2795901550
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.85106014
Short name T142
Test name
Test status
Simulation time 167986746 ps
CPU time 2.34 seconds
Started Jul 02 08:00:30 AM PDT 24
Finished Jul 02 08:00:48 AM PDT 24
Peak memory 216596 kb
Host smart-4eeb2b2a-999f-46f9-a573-47283484dba1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85106014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.85106014
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3502158060
Short name T135
Test name
Test status
Simulation time 424701460 ps
CPU time 1.76 seconds
Started Jul 02 07:59:53 AM PDT 24
Finished Jul 02 08:00:04 AM PDT 24
Peak memory 200464 kb
Host smart-19c6b738-4357-446b-abd1-d3b1c7c367eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502158060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3502158060
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2737656279
Short name T126
Test name
Test status
Simulation time 79480023 ps
CPU time 0.96 seconds
Started Jul 02 08:00:21 AM PDT 24
Finished Jul 02 08:00:36 AM PDT 24
Peak memory 200296 kb
Host smart-3c905d82-6fbe-48c2-b5ee-5606f642d00f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737656279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2737656279
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.4111002981
Short name T21
Test name
Test status
Simulation time 85581965 ps
CPU time 0.73 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:39 AM PDT 24
Peak memory 199844 kb
Host smart-c2cc6b09-e141-4c97-bbda-a5ad9abe2a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111002981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4111002981
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2084967353
Short name T220
Test name
Test status
Simulation time 244407747 ps
CPU time 1.06 seconds
Started Jul 02 08:00:29 AM PDT 24
Finished Jul 02 08:00:47 AM PDT 24
Peak memory 217488 kb
Host smart-94f9c05e-21aa-444a-a443-1da5febcc811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084967353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2084967353
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1449757796
Short name T137
Test name
Test status
Simulation time 473358972 ps
CPU time 1.83 seconds
Started Jul 02 08:00:12 AM PDT 24
Finished Jul 02 08:00:25 AM PDT 24
Peak memory 200480 kb
Host smart-a4e75bb3-6657-46bb-b538-fb3fdd16177e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449757796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1449757796
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.195386965
Short name T140
Test name
Test status
Simulation time 411866208 ps
CPU time 1.67 seconds
Started Jul 02 08:00:11 AM PDT 24
Finished Jul 02 08:00:24 AM PDT 24
Peak memory 200508 kb
Host smart-791f3bbd-6436-4455-8394-01828e89ad77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195386965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
195386965
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4294811919
Short name T70
Test name
Test status
Simulation time 443983648 ps
CPU time 2.57 seconds
Started Jul 02 07:59:50 AM PDT 24
Finished Jul 02 08:00:02 AM PDT 24
Peak memory 200480 kb
Host smart-e5fd3048-1e34-45b7-864c-1c9b99e70d77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294811919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
294811919
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2803300608
Short name T618
Test name
Test status
Simulation time 2291713642 ps
CPU time 9.9 seconds
Started Jul 02 08:00:10 AM PDT 24
Finished Jul 02 08:00:31 AM PDT 24
Peak memory 200496 kb
Host smart-56251046-73cd-4e56-985d-b0f05e321c54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803300608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
803300608
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2282950315
Short name T563
Test name
Test status
Simulation time 128068578 ps
CPU time 0.96 seconds
Started Jul 02 08:00:11 AM PDT 24
Finished Jul 02 08:00:23 AM PDT 24
Peak memory 200316 kb
Host smart-19b33ac7-3461-4adc-a99a-aa9093bf0db1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282950315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
282950315
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.345808369
Short name T578
Test name
Test status
Simulation time 200122186 ps
CPU time 1.39 seconds
Started Jul 02 08:00:06 AM PDT 24
Finished Jul 02 08:00:19 AM PDT 24
Peak memory 208512 kb
Host smart-8986abf6-0901-47da-97b6-80023dda4c23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345808369 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.345808369
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3765860391
Short name T615
Test name
Test status
Simulation time 67788089 ps
CPU time 0.72 seconds
Started Jul 02 08:01:09 AM PDT 24
Finished Jul 02 08:01:29 AM PDT 24
Peak memory 199940 kb
Host smart-926698c4-0a0c-45e4-b5b3-be96eb9fb562
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765860391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3765860391
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1595064771
Short name T585
Test name
Test status
Simulation time 121330985 ps
CPU time 1.26 seconds
Started Jul 02 08:00:00 AM PDT 24
Finished Jul 02 08:00:11 AM PDT 24
Peak memory 200496 kb
Host smart-9fae124a-a521-4212-9696-6f7ce0f74eab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595064771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1595064771
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1931070854
Short name T575
Test name
Test status
Simulation time 493458684 ps
CPU time 1.94 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 200276 kb
Host smart-cc04024b-70ed-4971-94b8-7a614a08b28d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931070854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1931070854
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3838778328
Short name T559
Test name
Test status
Simulation time 198695629 ps
CPU time 1.63 seconds
Started Jul 02 08:00:19 AM PDT 24
Finished Jul 02 08:00:35 AM PDT 24
Peak memory 200280 kb
Host smart-1b1c9050-8eea-4002-89db-33a45998ecaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838778328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
838778328
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2854492102
Short name T579
Test name
Test status
Simulation time 797242774 ps
CPU time 4.39 seconds
Started Jul 02 08:00:01 AM PDT 24
Finished Jul 02 08:00:17 AM PDT 24
Peak memory 200628 kb
Host smart-1656895c-c017-4792-ba95-92cec114c67c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854492102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
854492102
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.273065428
Short name T548
Test name
Test status
Simulation time 91117612 ps
CPU time 0.81 seconds
Started Jul 02 07:59:59 AM PDT 24
Finished Jul 02 08:00:10 AM PDT 24
Peak memory 200172 kb
Host smart-1a8fbb4b-48c6-432c-9651-3d02bfcf34c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273065428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.273065428
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3370495535
Short name T73
Test name
Test status
Simulation time 182994842 ps
CPU time 1.33 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:38 AM PDT 24
Peak memory 208380 kb
Host smart-e98614e7-8e2e-4ec9-856a-d18ed1baba7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370495535 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3370495535
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2822993829
Short name T595
Test name
Test status
Simulation time 71943285 ps
CPU time 0.86 seconds
Started Jul 02 08:00:10 AM PDT 24
Finished Jul 02 08:00:22 AM PDT 24
Peak memory 200272 kb
Host smart-0ad46282-6920-4369-b199-b64861c53da3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822993829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2822993829
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3549740414
Short name T557
Test name
Test status
Simulation time 111022242 ps
CPU time 1.53 seconds
Started Jul 02 08:00:16 AM PDT 24
Finished Jul 02 08:00:30 AM PDT 24
Peak memory 216664 kb
Host smart-6605e1d5-8650-40c4-87fd-95a3a194800f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549740414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3549740414
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1720246871
Short name T567
Test name
Test status
Simulation time 868987182 ps
CPU time 3.45 seconds
Started Jul 02 08:00:07 AM PDT 24
Finished Jul 02 08:00:22 AM PDT 24
Peak memory 200464 kb
Host smart-320e4c60-4cd6-4820-9f8f-721d5b32beb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720246871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1720246871
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1028505775
Short name T584
Test name
Test status
Simulation time 188234166 ps
CPU time 1.13 seconds
Started Jul 02 08:00:19 AM PDT 24
Finished Jul 02 08:00:34 AM PDT 24
Peak memory 200328 kb
Host smart-76033383-0f1e-4150-bda2-06ffca5d6ac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028505775 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1028505775
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4196810938
Short name T601
Test name
Test status
Simulation time 59574471 ps
CPU time 0.79 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:40 AM PDT 24
Peak memory 200492 kb
Host smart-1013c09a-26c2-47b8-a2cf-6a37e5915234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196810938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4196810938
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3769630542
Short name T120
Test name
Test status
Simulation time 222069938 ps
CPU time 1.46 seconds
Started Jul 02 08:00:18 AM PDT 24
Finished Jul 02 08:00:32 AM PDT 24
Peak memory 200532 kb
Host smart-a213f784-faad-479f-b122-2ca0cfc4f2b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769630542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3769630542
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.265451342
Short name T156
Test name
Test status
Simulation time 500575799 ps
CPU time 1.85 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:43 AM PDT 24
Peak memory 200456 kb
Host smart-e63275a7-e43a-4341-9da3-c0140eae6f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265451342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.265451342
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2980961025
Short name T105
Test name
Test status
Simulation time 152775933 ps
CPU time 1.24 seconds
Started Jul 02 08:00:22 AM PDT 24
Finished Jul 02 08:00:38 AM PDT 24
Peak memory 211992 kb
Host smart-dcda816b-e388-4ba8-ae7d-2bc0fbce5603
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980961025 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2980961025
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1858256666
Short name T609
Test name
Test status
Simulation time 62120136 ps
CPU time 0.73 seconds
Started Jul 02 08:01:12 AM PDT 24
Finished Jul 02 08:01:32 AM PDT 24
Peak memory 199860 kb
Host smart-febca860-8a50-468d-9358-a03182365862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858256666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1858256666
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4086215547
Short name T598
Test name
Test status
Simulation time 151990529 ps
CPU time 1.13 seconds
Started Jul 02 08:00:13 AM PDT 24
Finished Jul 02 08:00:25 AM PDT 24
Peak memory 200316 kb
Host smart-3fcbc072-bc9f-4b92-93b6-d6fee98c8adb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086215547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.4086215547
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1759758609
Short name T617
Test name
Test status
Simulation time 218624582 ps
CPU time 1.62 seconds
Started Jul 02 08:00:05 AM PDT 24
Finished Jul 02 08:00:17 AM PDT 24
Peak memory 216748 kb
Host smart-0b78be4e-bbb0-44db-b1f0-fe39c688cccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759758609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1759758609
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.218441609
Short name T134
Test name
Test status
Simulation time 455748205 ps
CPU time 1.81 seconds
Started Jul 02 08:00:11 AM PDT 24
Finished Jul 02 08:00:24 AM PDT 24
Peak memory 200360 kb
Host smart-1c309726-b3eb-4e7e-9a75-535336ac0eca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218441609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.218441609
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2821696098
Short name T106
Test name
Test status
Simulation time 171316128 ps
CPU time 1.14 seconds
Started Jul 02 08:00:27 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 200440 kb
Host smart-e2410267-e5df-49ab-9303-5eca7ae0ced0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821696098 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2821696098
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3712451467
Short name T613
Test name
Test status
Simulation time 63567322 ps
CPU time 0.79 seconds
Started Jul 02 08:00:05 AM PDT 24
Finished Jul 02 08:00:16 AM PDT 24
Peak memory 200104 kb
Host smart-cc470bef-00b2-4eaa-8468-9a37dace29f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712451467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3712451467
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.172246621
Short name T560
Test name
Test status
Simulation time 104110283 ps
CPU time 1.3 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:43 AM PDT 24
Peak memory 200512 kb
Host smart-a06a5367-495a-44e4-84c8-06e15e56d804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172246621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.172246621
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.468919236
Short name T586
Test name
Test status
Simulation time 116855205 ps
CPU time 1.51 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:43 AM PDT 24
Peak memory 211416 kb
Host smart-018a0574-aebf-402f-87e4-0d40fcacb7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468919236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.468919236
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3627118345
Short name T553
Test name
Test status
Simulation time 118365510 ps
CPU time 0.99 seconds
Started Jul 02 08:00:09 AM PDT 24
Finished Jul 02 08:00:21 AM PDT 24
Peak memory 200264 kb
Host smart-c3c62385-257d-4ff2-b47a-ffb381f8c516
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627118345 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3627118345
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2575324567
Short name T551
Test name
Test status
Simulation time 71412581 ps
CPU time 0.83 seconds
Started Jul 02 08:00:10 AM PDT 24
Finished Jul 02 08:00:22 AM PDT 24
Peak memory 200232 kb
Host smart-9695fe64-249d-4b50-9d3f-f91c48f00561
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575324567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2575324567
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2958522376
Short name T607
Test name
Test status
Simulation time 142291319 ps
CPU time 1.08 seconds
Started Jul 02 08:00:20 AM PDT 24
Finished Jul 02 08:00:35 AM PDT 24
Peak memory 200212 kb
Host smart-0518b687-20cb-4924-9d17-5d05df6507d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958522376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2958522376
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3544037923
Short name T603
Test name
Test status
Simulation time 313783164 ps
CPU time 2.33 seconds
Started Jul 02 08:00:13 AM PDT 24
Finished Jul 02 08:00:27 AM PDT 24
Peak memory 208540 kb
Host smart-0a5dfd82-a6a8-4e45-8ba5-2b5c02bfed5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544037923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3544037923
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1481162350
Short name T564
Test name
Test status
Simulation time 139496151 ps
CPU time 1.06 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 209648 kb
Host smart-388c64bb-93c0-4eab-ae31-af57772453a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481162350 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1481162350
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3524933382
Short name T108
Test name
Test status
Simulation time 84580794 ps
CPU time 0.84 seconds
Started Jul 02 08:00:22 AM PDT 24
Finished Jul 02 08:00:37 AM PDT 24
Peak memory 200172 kb
Host smart-3b4cabb0-b2f3-47a5-8516-5a126aa115e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524933382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3524933382
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1733167108
Short name T124
Test name
Test status
Simulation time 191523845 ps
CPU time 1.35 seconds
Started Jul 02 08:00:29 AM PDT 24
Finished Jul 02 08:00:47 AM PDT 24
Peak memory 200404 kb
Host smart-d7831793-6a3a-457c-93ec-5ba9f3f5b365
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733167108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1733167108
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1524187050
Short name T594
Test name
Test status
Simulation time 112650089 ps
CPU time 1.56 seconds
Started Jul 02 08:00:16 AM PDT 24
Finished Jul 02 08:00:29 AM PDT 24
Peak memory 208628 kb
Host smart-be6c7278-058e-4b90-bab4-314cacff054c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524187050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1524187050
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3334940145
Short name T558
Test name
Test status
Simulation time 508577722 ps
CPU time 1.91 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 200364 kb
Host smart-284520ea-0698-4301-8264-f9a88d411d23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334940145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3334940145
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.776023715
Short name T593
Test name
Test status
Simulation time 98692710 ps
CPU time 1.01 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:40 AM PDT 24
Peak memory 208520 kb
Host smart-500f5be6-9112-44ee-a6a2-cfc8ee6d84d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776023715 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.776023715
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3758153255
Short name T610
Test name
Test status
Simulation time 81404455 ps
CPU time 0.85 seconds
Started Jul 02 08:00:15 AM PDT 24
Finished Jul 02 08:00:27 AM PDT 24
Peak memory 200236 kb
Host smart-475d6723-961d-4453-9d09-311cbb265929
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758153255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3758153255
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3177455529
Short name T571
Test name
Test status
Simulation time 276080361 ps
CPU time 1.78 seconds
Started Jul 02 08:00:12 AM PDT 24
Finished Jul 02 08:00:26 AM PDT 24
Peak memory 200372 kb
Host smart-d8e4217d-6a16-456f-bebd-8ce364db90bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177455529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3177455529
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3384852918
Short name T128
Test name
Test status
Simulation time 294822864 ps
CPU time 2.18 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:40 AM PDT 24
Peak memory 208636 kb
Host smart-b4fd1099-30a9-4c77-a19b-74cdad8ea2d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384852918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3384852918
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3281209738
Short name T608
Test name
Test status
Simulation time 121322167 ps
CPU time 1.32 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:40 AM PDT 24
Peak memory 208456 kb
Host smart-8bd45d52-2d46-456e-ae15-164c592dd2a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281209738 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3281209738
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3364964172
Short name T127
Test name
Test status
Simulation time 66867817 ps
CPU time 0.78 seconds
Started Jul 02 08:00:13 AM PDT 24
Finished Jul 02 08:00:25 AM PDT 24
Peak memory 200252 kb
Host smart-38d58a10-d5e2-42ac-a729-cb8bd111d852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364964172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3364964172
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1962291954
Short name T69
Test name
Test status
Simulation time 163201549 ps
CPU time 1.1 seconds
Started Jul 02 08:00:18 AM PDT 24
Finished Jul 02 08:00:32 AM PDT 24
Peak memory 200344 kb
Host smart-4c9a7a1b-089e-4241-9765-e24d37eb81e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962291954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1962291954
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2282149182
Short name T620
Test name
Test status
Simulation time 411282317 ps
CPU time 3.06 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:00:47 AM PDT 24
Peak memory 200304 kb
Host smart-57a4bc47-6cfa-4d37-a7af-73c6bc28b192
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282149182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2282149182
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2512069686
Short name T556
Test name
Test status
Simulation time 816486008 ps
CPU time 2.75 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 200528 kb
Host smart-f481bf0d-1fe7-485a-a933-a0c3d9744f1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512069686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2512069686
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3649852514
Short name T102
Test name
Test status
Simulation time 129779311 ps
CPU time 0.98 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:40 AM PDT 24
Peak memory 200288 kb
Host smart-163b4741-6bba-4e48-b1e9-10d63014fa11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649852514 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3649852514
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1697764531
Short name T583
Test name
Test status
Simulation time 83402198 ps
CPU time 0.84 seconds
Started Jul 02 08:00:13 AM PDT 24
Finished Jul 02 08:00:25 AM PDT 24
Peak memory 200300 kb
Host smart-2579e73b-b40b-40f1-b41f-529b8136a679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697764531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1697764531
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.903844465
Short name T122
Test name
Test status
Simulation time 223316486 ps
CPU time 1.55 seconds
Started Jul 02 08:00:22 AM PDT 24
Finished Jul 02 08:00:38 AM PDT 24
Peak memory 200460 kb
Host smart-6a77231b-0f4d-4537-ba41-f0a985fc7a09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903844465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.903844465
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.734257255
Short name T619
Test name
Test status
Simulation time 661489270 ps
CPU time 4.05 seconds
Started Jul 02 08:00:21 AM PDT 24
Finished Jul 02 08:00:39 AM PDT 24
Peak memory 216568 kb
Host smart-b9a438b6-e2a4-4142-996e-4bc227e45b29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734257255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.734257255
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3247497394
Short name T136
Test name
Test status
Simulation time 883737601 ps
CPU time 3.02 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 200556 kb
Host smart-fa106268-f8e5-4c01-973e-7670328d20c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247497394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3247497394
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1323657560
Short name T103
Test name
Test status
Simulation time 201824661 ps
CPU time 1.25 seconds
Started Jul 02 08:00:14 AM PDT 24
Finished Jul 02 08:00:27 AM PDT 24
Peak memory 208620 kb
Host smart-0c51db3b-6a93-4364-9dbe-a1f55118072f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323657560 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1323657560
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2213895418
Short name T588
Test name
Test status
Simulation time 72734865 ps
CPU time 0.9 seconds
Started Jul 02 08:00:16 AM PDT 24
Finished Jul 02 08:00:28 AM PDT 24
Peak memory 200204 kb
Host smart-77d99415-dcaa-4070-a6cf-0fa084b45b87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213895418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2213895418
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1857980487
Short name T580
Test name
Test status
Simulation time 236736991 ps
CPU time 1.56 seconds
Started Jul 02 08:00:21 AM PDT 24
Finished Jul 02 08:00:36 AM PDT 24
Peak memory 200468 kb
Host smart-8af4a4af-f413-4ddd-a766-5e5ca186e985
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857980487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1857980487
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2604320570
Short name T572
Test name
Test status
Simulation time 187663025 ps
CPU time 2.51 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 208524 kb
Host smart-50808331-f511-400d-97a6-570e5a1e7e83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604320570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2604320570
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3556980850
Short name T107
Test name
Test status
Simulation time 489277143 ps
CPU time 2.04 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 200420 kb
Host smart-06d77b99-1ab7-476a-bbf8-49c39589edd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556980850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3556980850
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3198859908
Short name T130
Test name
Test status
Simulation time 109315249 ps
CPU time 1.31 seconds
Started Jul 02 08:00:36 AM PDT 24
Finished Jul 02 08:00:55 AM PDT 24
Peak memory 212656 kb
Host smart-a4d09fe8-d691-4d9c-be12-bbb943f9d55d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198859908 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3198859908
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1486026886
Short name T597
Test name
Test status
Simulation time 98165605 ps
CPU time 0.86 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 200252 kb
Host smart-d8da5d7c-4e86-4f03-a60b-539e04691b1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486026886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1486026886
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1265807308
Short name T125
Test name
Test status
Simulation time 236196338 ps
CPU time 1.6 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:40 AM PDT 24
Peak memory 200536 kb
Host smart-fd294746-c2f8-4967-a33c-e9528e0b375f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265807308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1265807308
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3293348920
Short name T605
Test name
Test status
Simulation time 113490312 ps
CPU time 1.48 seconds
Started Jul 02 08:00:14 AM PDT 24
Finished Jul 02 08:00:27 AM PDT 24
Peak memory 208616 kb
Host smart-8493217d-4912-4c41-b0aa-35ccd1b5b46f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293348920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3293348920
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3646939455
Short name T561
Test name
Test status
Simulation time 463127828 ps
CPU time 1.81 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 200636 kb
Host smart-2c751b2c-efde-4e90-b38d-e6b87c49a9df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646939455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3646939455
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2564841234
Short name T550
Test name
Test status
Simulation time 113359023 ps
CPU time 1.31 seconds
Started Jul 02 08:00:05 AM PDT 24
Finished Jul 02 08:00:17 AM PDT 24
Peak memory 200472 kb
Host smart-36093c45-4939-4bdc-bece-27b2251bf411
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564841234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
564841234
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.4225846834
Short name T566
Test name
Test status
Simulation time 487905013 ps
CPU time 5.59 seconds
Started Jul 02 08:00:00 AM PDT 24
Finished Jul 02 08:00:16 AM PDT 24
Peak memory 200332 kb
Host smart-ef0847ab-9495-481d-82e0-0b71e857265e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225846834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.4
225846834
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1556294658
Short name T549
Test name
Test status
Simulation time 140780397 ps
CPU time 0.93 seconds
Started Jul 02 08:01:01 AM PDT 24
Finished Jul 02 08:01:22 AM PDT 24
Peak memory 199808 kb
Host smart-3ff05c6b-b44f-4b6e-87c9-91eaeb639cd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556294658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
556294658
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2397704245
Short name T74
Test name
Test status
Simulation time 113747241 ps
CPU time 1.22 seconds
Started Jul 02 08:00:20 AM PDT 24
Finished Jul 02 08:00:35 AM PDT 24
Peak memory 208444 kb
Host smart-624ca80c-f630-4375-ae1e-88eaaac2d3a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397704245 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2397704245
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3750739931
Short name T565
Test name
Test status
Simulation time 77649623 ps
CPU time 0.83 seconds
Started Jul 02 08:00:27 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 200264 kb
Host smart-d8cf3dcd-3c41-4dff-9cb6-88dd8f44a50a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750739931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3750739931
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1440603681
Short name T587
Test name
Test status
Simulation time 125861306 ps
CPU time 1.15 seconds
Started Jul 02 08:00:10 AM PDT 24
Finished Jul 02 08:00:23 AM PDT 24
Peak memory 200336 kb
Host smart-db15998f-5d33-4464-bc63-9805b742749c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440603681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1440603681
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2156464215
Short name T138
Test name
Test status
Simulation time 777445286 ps
CPU time 3.1 seconds
Started Jul 02 08:00:09 AM PDT 24
Finished Jul 02 08:00:22 AM PDT 24
Peak memory 200536 kb
Host smart-d8f3b1b5-7bef-43a3-ac3b-391ffd7166d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156464215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2156464215
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.512977615
Short name T576
Test name
Test status
Simulation time 363775835 ps
CPU time 2.15 seconds
Started Jul 02 08:01:08 AM PDT 24
Finished Jul 02 08:01:29 AM PDT 24
Peak memory 200104 kb
Host smart-2a62bb1f-89e9-4c9c-947d-3e01d41d5e9e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512977615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.512977615
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3387801758
Short name T552
Test name
Test status
Simulation time 491032511 ps
CPU time 5.56 seconds
Started Jul 02 08:00:54 AM PDT 24
Finished Jul 02 08:01:20 AM PDT 24
Peak memory 199412 kb
Host smart-07991af8-be5b-4f71-8a4e-c98eba3d0128
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387801758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
387801758
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4016677760
Short name T574
Test name
Test status
Simulation time 127111471 ps
CPU time 0.96 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:00:46 AM PDT 24
Peak memory 200180 kb
Host smart-70aac832-6391-43af-a37d-bc3f4a997311
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016677760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4
016677760
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3296179801
Short name T596
Test name
Test status
Simulation time 107235662 ps
CPU time 0.95 seconds
Started Jul 02 08:00:21 AM PDT 24
Finished Jul 02 08:00:37 AM PDT 24
Peak memory 200208 kb
Host smart-e95c8b5f-2138-46ac-b8e0-600a126787e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296179801 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3296179801
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1091428845
Short name T123
Test name
Test status
Simulation time 87991891 ps
CPU time 0.89 seconds
Started Jul 02 08:00:14 AM PDT 24
Finished Jul 02 08:00:26 AM PDT 24
Peak memory 200192 kb
Host smart-f35905e4-ff04-4ce2-b5fb-fb453b219398
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091428845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1091428845
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2752318821
Short name T581
Test name
Test status
Simulation time 200738890 ps
CPU time 1.59 seconds
Started Jul 02 08:00:22 AM PDT 24
Finished Jul 02 08:00:37 AM PDT 24
Peak memory 200348 kb
Host smart-17e6ef0c-cd69-4d93-9163-83d89cce6da4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752318821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2752318821
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2380251525
Short name T573
Test name
Test status
Simulation time 174190675 ps
CPU time 2.47 seconds
Started Jul 02 08:00:20 AM PDT 24
Finished Jul 02 08:00:37 AM PDT 24
Peak memory 211900 kb
Host smart-95a661c2-f7b5-4469-9714-d36ab321c18c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380251525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2380251525
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2934490812
Short name T591
Test name
Test status
Simulation time 799987629 ps
CPU time 2.72 seconds
Started Jul 02 08:00:14 AM PDT 24
Finished Jul 02 08:00:28 AM PDT 24
Peak memory 200520 kb
Host smart-389167af-15de-4bb1-b2bd-28f99811747d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934490812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2934490812
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1120175956
Short name T602
Test name
Test status
Simulation time 426201540 ps
CPU time 2.48 seconds
Started Jul 02 08:00:22 AM PDT 24
Finished Jul 02 08:00:38 AM PDT 24
Peak memory 200364 kb
Host smart-aec26177-989a-456b-8ca4-da22cbe956cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120175956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
120175956
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3436155356
Short name T590
Test name
Test status
Simulation time 803492557 ps
CPU time 4.3 seconds
Started Jul 02 08:00:05 AM PDT 24
Finished Jul 02 08:00:20 AM PDT 24
Peak memory 200332 kb
Host smart-949d7611-2ecd-40e7-95ba-0ee3e51f134b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436155356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
436155356
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3553816030
Short name T547
Test name
Test status
Simulation time 106524635 ps
CPU time 0.88 seconds
Started Jul 02 08:00:10 AM PDT 24
Finished Jul 02 08:00:22 AM PDT 24
Peak memory 200240 kb
Host smart-5980894c-7b59-4673-9e35-6e0a5cb4c72a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553816030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
553816030
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1968220738
Short name T592
Test name
Test status
Simulation time 107448086 ps
CPU time 0.95 seconds
Started Jul 02 07:59:57 AM PDT 24
Finished Jul 02 08:00:08 AM PDT 24
Peak memory 200312 kb
Host smart-c9732474-7468-4b07-b5c0-ac9bca2dfcc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968220738 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1968220738
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2178271556
Short name T599
Test name
Test status
Simulation time 78737180 ps
CPU time 0.79 seconds
Started Jul 02 08:00:19 AM PDT 24
Finished Jul 02 08:00:33 AM PDT 24
Peak memory 200196 kb
Host smart-61ae3891-0a42-454a-8671-b0f07fb42697
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178271556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2178271556
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1831464785
Short name T119
Test name
Test status
Simulation time 224148734 ps
CPU time 1.45 seconds
Started Jul 02 08:00:19 AM PDT 24
Finished Jul 02 08:00:34 AM PDT 24
Peak memory 200488 kb
Host smart-9aafe9df-97a6-4f46-8f78-a06f329f8c24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831464785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1831464785
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.671613744
Short name T129
Test name
Test status
Simulation time 592150535 ps
CPU time 3.81 seconds
Started Jul 02 08:00:14 AM PDT 24
Finished Jul 02 08:00:29 AM PDT 24
Peak memory 208628 kb
Host smart-f6e8c52e-92b8-4f1f-a817-6f2aee4cec13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671613744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.671613744
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.943006426
Short name T611
Test name
Test status
Simulation time 896335385 ps
CPU time 2.94 seconds
Started Jul 02 08:00:18 AM PDT 24
Finished Jul 02 08:00:34 AM PDT 24
Peak memory 200572 kb
Host smart-08e678bf-7ea0-474c-8e08-7e4956460884
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943006426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
943006426
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1698139207
Short name T104
Test name
Test status
Simulation time 192821896 ps
CPU time 1.25 seconds
Started Jul 02 07:59:59 AM PDT 24
Finished Jul 02 08:00:10 AM PDT 24
Peak memory 208576 kb
Host smart-715a5708-e6c4-43f5-b5b5-8f7afb271e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698139207 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1698139207
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1681346407
Short name T555
Test name
Test status
Simulation time 66980674 ps
CPU time 0.82 seconds
Started Jul 02 08:00:08 AM PDT 24
Finished Jul 02 08:00:20 AM PDT 24
Peak memory 200276 kb
Host smart-746487b8-24dc-4851-8416-3cacdae3eee0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681346407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1681346407
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4170067170
Short name T606
Test name
Test status
Simulation time 245356750 ps
CPU time 1.55 seconds
Started Jul 02 08:00:18 AM PDT 24
Finished Jul 02 08:00:33 AM PDT 24
Peak memory 208608 kb
Host smart-83039319-7647-471c-879b-976c06c24fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170067170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4170067170
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1517028593
Short name T133
Test name
Test status
Simulation time 444835506 ps
CPU time 3.18 seconds
Started Jul 02 08:00:15 AM PDT 24
Finished Jul 02 08:00:29 AM PDT 24
Peak memory 208516 kb
Host smart-16c297eb-9e30-4926-a178-707967c167bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517028593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1517028593
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2804125510
Short name T614
Test name
Test status
Simulation time 115413744 ps
CPU time 1.28 seconds
Started Jul 02 08:00:17 AM PDT 24
Finished Jul 02 08:00:30 AM PDT 24
Peak memory 208596 kb
Host smart-648ef467-c058-4715-8112-e1ce9f351f4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804125510 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2804125510
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1268130198
Short name T554
Test name
Test status
Simulation time 75194126 ps
CPU time 0.79 seconds
Started Jul 02 07:59:53 AM PDT 24
Finished Jul 02 08:00:03 AM PDT 24
Peak memory 200212 kb
Host smart-45031e76-4152-4423-9d61-3e61658ab26a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268130198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1268130198
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3555424665
Short name T612
Test name
Test status
Simulation time 104730552 ps
CPU time 1.28 seconds
Started Jul 02 08:00:31 AM PDT 24
Finished Jul 02 08:00:49 AM PDT 24
Peak memory 200460 kb
Host smart-d5ebb41c-fac1-4f3b-98b2-b404886b4b73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555424665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3555424665
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3803884380
Short name T577
Test name
Test status
Simulation time 154902366 ps
CPU time 2.11 seconds
Started Jul 02 08:00:02 AM PDT 24
Finished Jul 02 08:00:15 AM PDT 24
Peak memory 208600 kb
Host smart-df65cb33-3095-44c0-9d1f-f212a0a51522
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803884380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3803884380
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3455596506
Short name T157
Test name
Test status
Simulation time 891249415 ps
CPU time 3.59 seconds
Started Jul 02 07:59:58 AM PDT 24
Finished Jul 02 08:00:11 AM PDT 24
Peak memory 200524 kb
Host smart-e83a1eaf-ae9c-45e1-8768-89877c99f9ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455596506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3455596506
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4119560826
Short name T582
Test name
Test status
Simulation time 109946027 ps
CPU time 1.13 seconds
Started Jul 02 08:00:09 AM PDT 24
Finished Jul 02 08:00:22 AM PDT 24
Peak memory 208620 kb
Host smart-0936d220-864f-4ecb-9dda-1e37299c4733
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119560826 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.4119560826
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2565401238
Short name T562
Test name
Test status
Simulation time 69367707 ps
CPU time 0.77 seconds
Started Jul 02 08:00:10 AM PDT 24
Finished Jul 02 08:00:22 AM PDT 24
Peak memory 200216 kb
Host smart-88fa729b-f403-423c-8a6a-1656310e4404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565401238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2565401238
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3805061994
Short name T121
Test name
Test status
Simulation time 205070763 ps
CPU time 1.44 seconds
Started Jul 02 08:00:12 AM PDT 24
Finished Jul 02 08:00:25 AM PDT 24
Peak memory 200384 kb
Host smart-26e75b91-3257-420c-a917-e5ab9442d7d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805061994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3805061994
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4228081664
Short name T132
Test name
Test status
Simulation time 194326147 ps
CPU time 2.93 seconds
Started Jul 02 08:00:01 AM PDT 24
Finished Jul 02 08:00:14 AM PDT 24
Peak memory 216720 kb
Host smart-473bd8a4-e94f-437a-aac2-9441093b83dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228081664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.4228081664
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3477508113
Short name T72
Test name
Test status
Simulation time 422899180 ps
CPU time 1.64 seconds
Started Jul 02 08:00:06 AM PDT 24
Finished Jul 02 08:00:19 AM PDT 24
Peak memory 200540 kb
Host smart-6a4c1d3c-0a88-4a7f-aac3-9b67d9a03c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477508113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3477508113
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.621852396
Short name T569
Test name
Test status
Simulation time 234490345 ps
CPU time 1.54 seconds
Started Jul 02 07:59:58 AM PDT 24
Finished Jul 02 08:00:10 AM PDT 24
Peak memory 216704 kb
Host smart-0236c897-7cc1-4ee0-bbe1-cf373a43860f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621852396 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.621852396
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4143330068
Short name T616
Test name
Test status
Simulation time 87366614 ps
CPU time 0.87 seconds
Started Jul 02 08:00:11 AM PDT 24
Finished Jul 02 08:00:23 AM PDT 24
Peak memory 200168 kb
Host smart-146ed9f2-3184-4dcd-965f-abee0980c222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143330068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4143330068
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4004411693
Short name T589
Test name
Test status
Simulation time 140581022 ps
CPU time 1.18 seconds
Started Jul 02 08:00:06 AM PDT 24
Finished Jul 02 08:00:18 AM PDT 24
Peak memory 200212 kb
Host smart-2d66eb0b-dcee-429a-8d91-bbd54023f4d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004411693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.4004411693
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.116127852
Short name T604
Test name
Test status
Simulation time 324109987 ps
CPU time 2.48 seconds
Started Jul 02 08:00:07 AM PDT 24
Finished Jul 02 08:00:20 AM PDT 24
Peak memory 208616 kb
Host smart-d9f4ab03-194c-40a4-a4cd-630124bec4c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116127852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.116127852
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2818855513
Short name T68
Test name
Test status
Simulation time 164608942 ps
CPU time 1.13 seconds
Started Jul 02 08:00:15 AM PDT 24
Finished Jul 02 08:00:27 AM PDT 24
Peak memory 200356 kb
Host smart-cf97163e-dac9-404c-a115-9773b93068f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818855513 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2818855513
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4158560744
Short name T568
Test name
Test status
Simulation time 68951290 ps
CPU time 0.77 seconds
Started Jul 02 08:00:09 AM PDT 24
Finished Jul 02 08:00:21 AM PDT 24
Peak memory 200220 kb
Host smart-51a8672d-ff3a-4219-97ac-90a96867fb7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158560744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.4158560744
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1521355687
Short name T600
Test name
Test status
Simulation time 139664841 ps
CPU time 1.11 seconds
Started Jul 02 08:00:20 AM PDT 24
Finished Jul 02 08:00:40 AM PDT 24
Peak memory 200364 kb
Host smart-09bf2899-65ed-4dc4-9187-04e78973f968
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521355687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1521355687
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1201246811
Short name T131
Test name
Test status
Simulation time 256067506 ps
CPU time 1.93 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:00:46 AM PDT 24
Peak memory 208608 kb
Host smart-6e90c8df-6e04-4c13-8e54-575fe23bfad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201246811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1201246811
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1579816984
Short name T139
Test name
Test status
Simulation time 496040276 ps
CPU time 1.88 seconds
Started Jul 02 08:00:18 AM PDT 24
Finished Jul 02 08:00:33 AM PDT 24
Peak memory 200528 kb
Host smart-3d4557b3-0e83-4adb-b67b-39e905613986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579816984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1579816984
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1644487700
Short name T430
Test name
Test status
Simulation time 67372335 ps
CPU time 0.77 seconds
Started Jul 02 08:00:22 AM PDT 24
Finished Jul 02 08:00:38 AM PDT 24
Peak memory 199904 kb
Host smart-f1bbe180-1c6c-4617-9341-93ea26298f3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644487700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1644487700
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.513259219
Short name T52
Test name
Test status
Simulation time 2366461433 ps
CPU time 8.43 seconds
Started Jul 02 08:00:19 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 217712 kb
Host smart-9b57ae1b-cc2c-4ed4-93a9-0745a8633a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513259219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.513259219
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3215002716
Short name T477
Test name
Test status
Simulation time 243869491 ps
CPU time 1.14 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 217444 kb
Host smart-bf901f11-1d76-44ad-9128-850d369b3a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215002716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3215002716
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.871415369
Short name T325
Test name
Test status
Simulation time 1774045807 ps
CPU time 6.09 seconds
Started Jul 02 08:00:10 AM PDT 24
Finished Jul 02 08:00:27 AM PDT 24
Peak memory 200412 kb
Host smart-ac4cea29-8682-47b4-96fc-cd64a6deedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871415369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.871415369
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3446996513
Short name T406
Test name
Test status
Simulation time 145522359 ps
CPU time 1.08 seconds
Started Jul 02 08:00:16 AM PDT 24
Finished Jul 02 08:00:28 AM PDT 24
Peak memory 200128 kb
Host smart-5761d22a-dc02-494f-af23-df5491875f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446996513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3446996513
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3651876425
Short name T459
Test name
Test status
Simulation time 223743516 ps
CPU time 1.33 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:43 AM PDT 24
Peak memory 200312 kb
Host smart-3458e099-7b0d-4122-8f3d-627e1b37591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651876425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3651876425
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3474188820
Short name T413
Test name
Test status
Simulation time 884916153 ps
CPU time 4.1 seconds
Started Jul 02 08:00:21 AM PDT 24
Finished Jul 02 08:00:39 AM PDT 24
Peak memory 200380 kb
Host smart-21c09393-a912-4028-b706-10cc2c235c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474188820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3474188820
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.416633254
Short name T479
Test name
Test status
Simulation time 128279095 ps
CPU time 1.48 seconds
Started Jul 02 08:00:19 AM PDT 24
Finished Jul 02 08:00:34 AM PDT 24
Peak memory 200032 kb
Host smart-de619b6c-5fe4-4008-bf2a-f295d52a9b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416633254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.416633254
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2312432747
Short name T383
Test name
Test status
Simulation time 157623655 ps
CPU time 1.24 seconds
Started Jul 02 08:00:09 AM PDT 24
Finished Jul 02 08:00:22 AM PDT 24
Peak memory 200332 kb
Host smart-0cbe4f0a-8aa1-4e74-96f6-4824a15b98fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312432747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2312432747
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3682473196
Short name T330
Test name
Test status
Simulation time 60316245 ps
CPU time 0.74 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:39 AM PDT 24
Peak memory 199840 kb
Host smart-a015b26d-3914-471c-80d7-9f5fe40eca80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682473196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3682473196
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3982224051
Short name T46
Test name
Test status
Simulation time 1231008635 ps
CPU time 5.76 seconds
Started Jul 02 08:00:12 AM PDT 24
Finished Jul 02 08:00:29 AM PDT 24
Peak memory 216888 kb
Host smart-b8489454-f0ce-4754-bf48-55db3b95e33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982224051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3982224051
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.247823547
Short name T416
Test name
Test status
Simulation time 243613885 ps
CPU time 1.07 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:40 AM PDT 24
Peak memory 217520 kb
Host smart-9bd3fb77-cf41-4763-8ba5-aa92e709c15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247823547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.247823547
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2905081540
Short name T243
Test name
Test status
Simulation time 197999151 ps
CPU time 0.94 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:39 AM PDT 24
Peak memory 199968 kb
Host smart-b88598c9-428a-425d-a36c-8ed381b96b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905081540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2905081540
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.289059362
Short name T362
Test name
Test status
Simulation time 1736713199 ps
CPU time 6.39 seconds
Started Jul 02 08:00:20 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 200472 kb
Host smart-2d15b62f-4ba0-4b10-802b-7ef47558ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289059362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.289059362
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2174327589
Short name T76
Test name
Test status
Simulation time 8305064141 ps
CPU time 16.18 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:57 AM PDT 24
Peak memory 217636 kb
Host smart-06f5904c-8510-4dd4-b75d-533cc893e3bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174327589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2174327589
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.543978403
Short name T514
Test name
Test status
Simulation time 188748328 ps
CPU time 1.2 seconds
Started Jul 02 08:00:43 AM PDT 24
Finished Jul 02 08:01:02 AM PDT 24
Peak memory 200120 kb
Host smart-2827dc9f-dbd9-42aa-840b-83ff3ea9a75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543978403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.543978403
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2859684996
Short name T283
Test name
Test status
Simulation time 196441688 ps
CPU time 1.33 seconds
Started Jul 02 08:00:18 AM PDT 24
Finished Jul 02 08:00:33 AM PDT 24
Peak memory 200264 kb
Host smart-4366f876-b40a-4207-b9db-8661cf710611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859684996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2859684996
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.256471088
Short name T84
Test name
Test status
Simulation time 5306114443 ps
CPU time 23.93 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:01:07 AM PDT 24
Peak memory 208668 kb
Host smart-01f7d2b7-8371-4de8-aab3-a7c61df2cc08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256471088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.256471088
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2494700874
Short name T291
Test name
Test status
Simulation time 259607310 ps
CPU time 1.48 seconds
Started Jul 02 08:00:08 AM PDT 24
Finished Jul 02 08:00:21 AM PDT 24
Peak memory 200176 kb
Host smart-23c9fca8-6d89-4092-8805-1cdfb35ff72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494700874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2494700874
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.938477880
Short name T407
Test name
Test status
Simulation time 72199377 ps
CPU time 0.79 seconds
Started Jul 02 08:00:22 AM PDT 24
Finished Jul 02 08:00:38 AM PDT 24
Peak memory 199960 kb
Host smart-96b7cbb3-15a8-4f59-af8b-277188e60e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938477880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.938477880
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3814068570
Short name T349
Test name
Test status
Simulation time 1223255717 ps
CPU time 5.2 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:05 AM PDT 24
Peak memory 217764 kb
Host smart-cfc58705-d5cc-441e-96cd-6579087a328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814068570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3814068570
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1360651124
Short name T225
Test name
Test status
Simulation time 159495346 ps
CPU time 0.82 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 199924 kb
Host smart-cfd5360f-cee3-475a-b37d-2c07dd6467ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360651124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1360651124
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3694591891
Short name T429
Test name
Test status
Simulation time 1465126848 ps
CPU time 5.62 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 200348 kb
Host smart-ece976fc-ba94-40c7-b658-dbe2032904a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694591891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3694591891
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2650750484
Short name T398
Test name
Test status
Simulation time 145954679 ps
CPU time 1.07 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 200116 kb
Host smart-22979de1-72fe-4ca9-93de-a247657474cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650750484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2650750484
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1129480796
Short name T538
Test name
Test status
Simulation time 247444212 ps
CPU time 1.49 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:00:46 AM PDT 24
Peak memory 200272 kb
Host smart-a80412e5-75e9-493b-ac24-1e520f751637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129480796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1129480796
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2412728023
Short name T433
Test name
Test status
Simulation time 5448158228 ps
CPU time 24.64 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:01:09 AM PDT 24
Peak memory 208684 kb
Host smart-4e312fc3-95ab-43b6-b3ec-dbda65b511c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412728023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2412728023
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.418302557
Short name T239
Test name
Test status
Simulation time 115444991 ps
CPU time 1.35 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 200128 kb
Host smart-fdfb3670-55d6-4fbb-ae24-d4037a1857d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418302557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.418302557
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3968961305
Short name T286
Test name
Test status
Simulation time 113874805 ps
CPU time 1.11 seconds
Started Jul 02 08:00:50 AM PDT 24
Finished Jul 02 08:01:11 AM PDT 24
Peak memory 200132 kb
Host smart-d7c608be-bac3-4119-913f-70a1ae082b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968961305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3968961305
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.4237731729
Short name T408
Test name
Test status
Simulation time 1225256763 ps
CPU time 5.87 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:47 AM PDT 24
Peak memory 217752 kb
Host smart-d0a53711-8fc1-400a-b22c-35972261c898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237731729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.4237731729
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.120106565
Short name T299
Test name
Test status
Simulation time 247165641 ps
CPU time 1.06 seconds
Started Jul 02 08:00:29 AM PDT 24
Finished Jul 02 08:00:52 AM PDT 24
Peak memory 217524 kb
Host smart-645f9e87-cfa0-42cb-b0cb-dd45c3778552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120106565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.120106565
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1120722281
Short name T432
Test name
Test status
Simulation time 133573660 ps
CPU time 0.86 seconds
Started Jul 02 08:00:34 AM PDT 24
Finished Jul 02 08:00:53 AM PDT 24
Peak memory 199888 kb
Host smart-c1ca8c9d-8159-4b28-9c03-2e3ce81f76d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120722281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1120722281
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.307997651
Short name T468
Test name
Test status
Simulation time 862377424 ps
CPU time 4.34 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:10 AM PDT 24
Peak memory 200276 kb
Host smart-fa21eef6-0898-449e-b52c-9ed695c5d2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307997651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.307997651
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.992541535
Short name T334
Test name
Test status
Simulation time 102233766 ps
CPU time 0.96 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:40 AM PDT 24
Peak memory 200156 kb
Host smart-1672444c-3334-4454-a7cf-bdebfd86c6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992541535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.992541535
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2652790334
Short name T444
Test name
Test status
Simulation time 246116651 ps
CPU time 1.52 seconds
Started Jul 02 08:00:48 AM PDT 24
Finished Jul 02 08:01:10 AM PDT 24
Peak memory 200328 kb
Host smart-29afd392-a163-41c4-ad97-3483b440341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652790334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2652790334
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2700831085
Short name T483
Test name
Test status
Simulation time 6399001111 ps
CPU time 27.37 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:01:06 AM PDT 24
Peak memory 208568 kb
Host smart-4953b945-666b-41ee-9a2a-67987bee28c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700831085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2700831085
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3170438934
Short name T95
Test name
Test status
Simulation time 374031866 ps
CPU time 2.06 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 200124 kb
Host smart-383e2046-1e7f-46dc-9190-ff862267fab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170438934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3170438934
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.287705526
Short name T271
Test name
Test status
Simulation time 99242745 ps
CPU time 0.97 seconds
Started Jul 02 08:00:31 AM PDT 24
Finished Jul 02 08:00:48 AM PDT 24
Peak memory 200116 kb
Host smart-2ac71007-a89a-4702-be7f-50cf72e4915f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287705526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.287705526
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2891581950
Short name T171
Test name
Test status
Simulation time 65412020 ps
CPU time 0.75 seconds
Started Jul 02 08:00:32 AM PDT 24
Finished Jul 02 08:00:49 AM PDT 24
Peak memory 199936 kb
Host smart-3edfe8a7-32bb-4f3a-8759-7d8dbec24bce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891581950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2891581950
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3818326180
Short name T29
Test name
Test status
Simulation time 244195328 ps
CPU time 0.99 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:49 AM PDT 24
Peak memory 217528 kb
Host smart-9981fa70-0b52-4950-b4b8-f4bd57891b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818326180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3818326180
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.602800570
Short name T254
Test name
Test status
Simulation time 221123982 ps
CPU time 0.88 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 199888 kb
Host smart-38051aa5-1d9b-474a-ba31-bbf8b3a152ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602800570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.602800570
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1180427766
Short name T144
Test name
Test status
Simulation time 2144389738 ps
CPU time 7.27 seconds
Started Jul 02 08:00:50 AM PDT 24
Finished Jul 02 08:01:17 AM PDT 24
Peak memory 200380 kb
Host smart-6f585e14-8def-4dbd-87a9-f7f096f60fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180427766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1180427766
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2559957620
Short name T192
Test name
Test status
Simulation time 114730090 ps
CPU time 1.01 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 200144 kb
Host smart-88b373e5-7dfb-45c1-8868-b4c963dd4f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559957620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2559957620
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1618157173
Short name T268
Test name
Test status
Simulation time 200577302 ps
CPU time 1.42 seconds
Started Jul 02 08:00:32 AM PDT 24
Finished Jul 02 08:00:49 AM PDT 24
Peak memory 200344 kb
Host smart-e863e8ec-3bba-4aae-a9bd-1ae64a538847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618157173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1618157173
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.849508766
Short name T529
Test name
Test status
Simulation time 3580567144 ps
CPU time 12.56 seconds
Started Jul 02 08:00:31 AM PDT 24
Finished Jul 02 08:01:00 AM PDT 24
Peak memory 200456 kb
Host smart-9b490d3a-13d8-4fb8-95c2-331d09118184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849508766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.849508766
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3397046762
Short name T417
Test name
Test status
Simulation time 117653750 ps
CPU time 1.51 seconds
Started Jul 02 08:00:43 AM PDT 24
Finished Jul 02 08:01:03 AM PDT 24
Peak memory 200156 kb
Host smart-33281042-d81b-4aa8-b2d8-c66710a42cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397046762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3397046762
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.323382354
Short name T509
Test name
Test status
Simulation time 122411170 ps
CPU time 1.09 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:43 AM PDT 24
Peak memory 200056 kb
Host smart-364a49db-b08e-49f3-b7ff-4317b0fc032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323382354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.323382354
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1474954763
Short name T259
Test name
Test status
Simulation time 78035340 ps
CPU time 0.78 seconds
Started Jul 02 08:00:39 AM PDT 24
Finished Jul 02 08:00:58 AM PDT 24
Peak memory 199936 kb
Host smart-0b5071e5-6069-4147-89cb-cba165a322ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474954763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1474954763
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3579077503
Short name T35
Test name
Test status
Simulation time 2366718690 ps
CPU time 8.71 seconds
Started Jul 02 08:00:45 AM PDT 24
Finished Jul 02 08:01:14 AM PDT 24
Peak memory 217740 kb
Host smart-9a45fae1-7701-4553-a338-ec61909c2fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579077503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3579077503
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3640976614
Short name T304
Test name
Test status
Simulation time 244532161 ps
CPU time 1.1 seconds
Started Jul 02 08:00:43 AM PDT 24
Finished Jul 02 08:01:03 AM PDT 24
Peak memory 217364 kb
Host smart-6c9c4b9a-e02f-4d5b-9d41-be6e2bce50be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640976614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3640976614
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2889595927
Short name T415
Test name
Test status
Simulation time 175660569 ps
CPU time 0.89 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:00:50 AM PDT 24
Peak memory 199956 kb
Host smart-398e9016-157d-47f2-b604-ba7b59ff81ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889595927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2889595927
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3113716256
Short name T502
Test name
Test status
Simulation time 1666427780 ps
CPU time 5.66 seconds
Started Jul 02 08:00:33 AM PDT 24
Finished Jul 02 08:00:55 AM PDT 24
Peak memory 200336 kb
Host smart-77433d63-dfe0-4e1c-8b1e-6c8ae5f85027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113716256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3113716256
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1268723475
Short name T352
Test name
Test status
Simulation time 148494042 ps
CPU time 1.11 seconds
Started Jul 02 08:00:44 AM PDT 24
Finished Jul 02 08:01:04 AM PDT 24
Peak memory 200128 kb
Host smart-c96d0bd1-ef62-44f3-80b1-29e0b979a0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268723475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1268723475
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.202089933
Short name T30
Test name
Test status
Simulation time 193280852 ps
CPU time 1.32 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 200364 kb
Host smart-045e38ae-0f55-41c8-aaf4-b00a828a9993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202089933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.202089933
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3986286419
Short name T116
Test name
Test status
Simulation time 3538728717 ps
CPU time 13.13 seconds
Started Jul 02 08:00:39 AM PDT 24
Finished Jul 02 08:01:09 AM PDT 24
Peak memory 208660 kb
Host smart-a7280342-bfd4-49a6-9546-e1996a6994ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986286419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3986286419
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.309317575
Short name T356
Test name
Test status
Simulation time 265162718 ps
CPU time 1.9 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:07 AM PDT 24
Peak memory 200040 kb
Host smart-369c627c-e71d-4783-b141-f73e6f136cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309317575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.309317575
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3839002210
Short name T418
Test name
Test status
Simulation time 125819495 ps
CPU time 0.96 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 200172 kb
Host smart-1bad5cf7-4ac3-46d2-bb1d-ed0a04550c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839002210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3839002210
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.91452992
Short name T405
Test name
Test status
Simulation time 67940284 ps
CPU time 0.79 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:00:45 AM PDT 24
Peak memory 199956 kb
Host smart-7ade3054-b145-4887-a30c-0f959eeff261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91452992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.91452992
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1552726079
Short name T167
Test name
Test status
Simulation time 244371210 ps
CPU time 1.08 seconds
Started Jul 02 08:00:33 AM PDT 24
Finished Jul 02 08:00:51 AM PDT 24
Peak memory 217496 kb
Host smart-1b3de923-25d8-49fd-b706-1c869ef3bf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552726079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1552726079
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2009875014
Short name T248
Test name
Test status
Simulation time 184701838 ps
CPU time 0.85 seconds
Started Jul 02 08:01:07 AM PDT 24
Finished Jul 02 08:01:26 AM PDT 24
Peak memory 199924 kb
Host smart-1530d91f-3e75-4ae8-853d-7e2d8d28daaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009875014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2009875014
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.4114192099
Short name T230
Test name
Test status
Simulation time 1351126827 ps
CPU time 5 seconds
Started Jul 02 08:00:40 AM PDT 24
Finished Jul 02 08:01:04 AM PDT 24
Peak memory 200392 kb
Host smart-8d7d6c4f-5bf2-47dd-8d55-c9ed7249b734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114192099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4114192099
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.622267431
Short name T202
Test name
Test status
Simulation time 151789410 ps
CPU time 1.09 seconds
Started Jul 02 08:00:53 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 200120 kb
Host smart-e3d7d05f-8ff6-4b3c-aa7c-e0e00aa2a089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622267431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.622267431
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2488305696
Short name T489
Test name
Test status
Simulation time 118070547 ps
CPU time 1.17 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 200264 kb
Host smart-492261a7-eede-485e-a315-211d9777a540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488305696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2488305696
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2471252167
Short name T63
Test name
Test status
Simulation time 5753329453 ps
CPU time 26.26 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:01:11 AM PDT 24
Peak memory 200424 kb
Host smart-da5a2861-53ae-4d16-a406-c11b34b0168d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471252167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2471252167
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.707662165
Short name T382
Test name
Test status
Simulation time 539242969 ps
CPU time 2.74 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:00:47 AM PDT 24
Peak memory 200068 kb
Host smart-fc3e18b7-3006-442d-be77-67ba7c25d9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707662165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.707662165
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.57061008
Short name T200
Test name
Test status
Simulation time 102361683 ps
CPU time 0.93 seconds
Started Jul 02 08:00:42 AM PDT 24
Finished Jul 02 08:01:02 AM PDT 24
Peak memory 200068 kb
Host smart-7c31b65d-5c70-4473-a7c8-a3593d548f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57061008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.57061008
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2866565980
Short name T441
Test name
Test status
Simulation time 67532466 ps
CPU time 0.77 seconds
Started Jul 02 08:00:42 AM PDT 24
Finished Jul 02 08:01:02 AM PDT 24
Peak memory 199952 kb
Host smart-605b11e3-a313-4f37-bae7-0a611f0a9522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866565980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2866565980
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.699452892
Short name T506
Test name
Test status
Simulation time 2359212325 ps
CPU time 8.96 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 217876 kb
Host smart-83f2a3fe-0599-4d24-bee4-d544b584df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699452892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.699452892
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3079317994
Short name T470
Test name
Test status
Simulation time 244831078 ps
CPU time 1.03 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:06 AM PDT 24
Peak memory 217404 kb
Host smart-e2fe8e31-e4ab-47f5-a224-129526bcff72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079317994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3079317994
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1991363861
Short name T490
Test name
Test status
Simulation time 101206225 ps
CPU time 0.78 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 199924 kb
Host smart-cd7bc1f9-b70a-4b76-929f-cfedd95591be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991363861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1991363861
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3921099572
Short name T175
Test name
Test status
Simulation time 1363906891 ps
CPU time 5.47 seconds
Started Jul 02 08:00:52 AM PDT 24
Finished Jul 02 08:01:17 AM PDT 24
Peak memory 200392 kb
Host smart-e698e0de-788b-4080-a04b-f161d51f9e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921099572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3921099572
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.469461824
Short name T453
Test name
Test status
Simulation time 172318171 ps
CPU time 1.17 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 200152 kb
Host smart-6dbba74f-d749-4995-92e8-c5a181523c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469461824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.469461824
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.970631827
Short name T339
Test name
Test status
Simulation time 118522455 ps
CPU time 1.24 seconds
Started Jul 02 08:00:48 AM PDT 24
Finished Jul 02 08:01:09 AM PDT 24
Peak memory 200336 kb
Host smart-f6b6ed83-913e-4968-a11f-d5f75714f4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970631827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.970631827
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.262191484
Short name T358
Test name
Test status
Simulation time 6333283459 ps
CPU time 20.51 seconds
Started Jul 02 08:01:01 AM PDT 24
Finished Jul 02 08:01:41 AM PDT 24
Peak memory 208640 kb
Host smart-c82a5db4-4597-44bb-93b0-e28990188437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262191484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.262191484
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3929858274
Short name T216
Test name
Test status
Simulation time 153357707 ps
CPU time 1.98 seconds
Started Jul 02 08:00:34 AM PDT 24
Finished Jul 02 08:00:53 AM PDT 24
Peak memory 200072 kb
Host smart-8d5c7649-1d41-4642-890b-f21e1ec2cbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929858274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3929858274
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2385456643
Short name T368
Test name
Test status
Simulation time 136025525 ps
CPU time 1.18 seconds
Started Jul 02 08:00:36 AM PDT 24
Finished Jul 02 08:00:55 AM PDT 24
Peak memory 200156 kb
Host smart-0dd234fa-d365-4f68-8569-4a7947daa4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385456643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2385456643
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2487448432
Short name T87
Test name
Test status
Simulation time 69858298 ps
CPU time 0.83 seconds
Started Jul 02 08:00:45 AM PDT 24
Finished Jul 02 08:01:06 AM PDT 24
Peak memory 199948 kb
Host smart-baa4968c-28d2-41ea-94b3-d55c091f6b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487448432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2487448432
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.22796889
Short name T236
Test name
Test status
Simulation time 243873133 ps
CPU time 1.12 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:00:46 AM PDT 24
Peak memory 217512 kb
Host smart-65b58ba0-1e24-4a3c-a06b-0fbfc5b15b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22796889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.22796889
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2431025519
Short name T516
Test name
Test status
Simulation time 246027774 ps
CPU time 0.94 seconds
Started Jul 02 08:00:34 AM PDT 24
Finished Jul 02 08:00:54 AM PDT 24
Peak memory 199948 kb
Host smart-66cc1450-44f8-4cdd-81bd-936cb03e03d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431025519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2431025519
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.976932647
Short name T89
Test name
Test status
Simulation time 874282418 ps
CPU time 4.02 seconds
Started Jul 02 08:00:40 AM PDT 24
Finished Jul 02 08:01:02 AM PDT 24
Peak memory 200300 kb
Host smart-394f18d3-f44c-45b2-9b86-e15ee101daf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976932647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.976932647
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.192103465
Short name T376
Test name
Test status
Simulation time 175527013 ps
CPU time 1.18 seconds
Started Jul 02 08:01:02 AM PDT 24
Finished Jul 02 08:01:22 AM PDT 24
Peak memory 200132 kb
Host smart-57da13be-cf07-4930-a988-41986dd8709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192103465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.192103465
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.971031541
Short name T250
Test name
Test status
Simulation time 125954667 ps
CPU time 1.13 seconds
Started Jul 02 08:00:58 AM PDT 24
Finished Jul 02 08:01:19 AM PDT 24
Peak memory 200368 kb
Host smart-2164aa8e-c0df-40e3-9c05-b0547c1e8197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971031541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.971031541
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.514677065
Short name T97
Test name
Test status
Simulation time 2539930729 ps
CPU time 12.5 seconds
Started Jul 02 08:00:54 AM PDT 24
Finished Jul 02 08:01:27 AM PDT 24
Peak memory 208596 kb
Host smart-d79a64e0-668d-406a-b723-4988e792c8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514677065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.514677065
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2319968925
Short name T213
Test name
Test status
Simulation time 120614603 ps
CPU time 1.42 seconds
Started Jul 02 08:00:51 AM PDT 24
Finished Jul 02 08:01:13 AM PDT 24
Peak memory 199948 kb
Host smart-0650f3fb-26bb-499e-b5b1-d1b06a970c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319968925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2319968925
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.27568118
Short name T469
Test name
Test status
Simulation time 124749192 ps
CPU time 0.97 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:00:45 AM PDT 24
Peak memory 200040 kb
Host smart-76b866ea-4ef0-42a2-a06b-3681010495f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27568118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.27568118
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3694096909
Short name T517
Test name
Test status
Simulation time 67947046 ps
CPU time 0.72 seconds
Started Jul 02 08:00:38 AM PDT 24
Finished Jul 02 08:00:56 AM PDT 24
Peak memory 199924 kb
Host smart-4bf84775-6b4d-4be2-aa92-c7a5565d5f08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694096909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3694096909
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.4240284559
Short name T38
Test name
Test status
Simulation time 1235037452 ps
CPU time 5.39 seconds
Started Jul 02 08:00:59 AM PDT 24
Finished Jul 02 08:01:23 AM PDT 24
Peak memory 221808 kb
Host smart-1ebba96f-9138-46cb-a367-9a007f2a552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240284559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.4240284559
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1882429187
Short name T366
Test name
Test status
Simulation time 244317532 ps
CPU time 1.1 seconds
Started Jul 02 08:00:59 AM PDT 24
Finished Jul 02 08:01:19 AM PDT 24
Peak memory 217496 kb
Host smart-9e5b33cb-d77a-4fee-afc0-0e23e81b5cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882429187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1882429187
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1650998561
Short name T474
Test name
Test status
Simulation time 159410851 ps
CPU time 0.81 seconds
Started Jul 02 08:00:55 AM PDT 24
Finished Jul 02 08:01:16 AM PDT 24
Peak memory 199864 kb
Host smart-a51c734c-7a85-4008-a94a-10e0f23ad752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650998561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1650998561
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.221276428
Short name T360
Test name
Test status
Simulation time 917547166 ps
CPU time 4.51 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:04 AM PDT 24
Peak memory 200392 kb
Host smart-4c58cb9c-b835-449b-8e07-3b3fa34507b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221276428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.221276428
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3186774270
Short name T359
Test name
Test status
Simulation time 175499014 ps
CPU time 1.12 seconds
Started Jul 02 08:00:39 AM PDT 24
Finished Jul 02 08:00:59 AM PDT 24
Peak memory 200148 kb
Host smart-7e3839ae-7e74-48fa-979a-10bb85d01010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186774270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3186774270
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2319351828
Short name T464
Test name
Test status
Simulation time 113860213 ps
CPU time 1.13 seconds
Started Jul 02 08:00:29 AM PDT 24
Finished Jul 02 08:00:47 AM PDT 24
Peak memory 200352 kb
Host smart-467ef538-df6d-4cb6-90f8-0c5861397e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319351828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2319351828
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3239346517
Short name T357
Test name
Test status
Simulation time 139832674 ps
CPU time 1.77 seconds
Started Jul 02 08:00:49 AM PDT 24
Finished Jul 02 08:01:11 AM PDT 24
Peak memory 200148 kb
Host smart-8504d708-d052-4195-8f06-8b76eba1b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239346517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3239346517
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2590319104
Short name T494
Test name
Test status
Simulation time 136279780 ps
CPU time 1.14 seconds
Started Jul 02 08:00:40 AM PDT 24
Finished Jul 02 08:00:59 AM PDT 24
Peak memory 200068 kb
Host smart-37a15817-d743-4dd8-9be1-f7705b24a0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590319104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2590319104
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.217682282
Short name T80
Test name
Test status
Simulation time 90444893 ps
CPU time 0.81 seconds
Started Jul 02 08:01:06 AM PDT 24
Finished Jul 02 08:01:26 AM PDT 24
Peak memory 199932 kb
Host smart-86825f20-6623-422c-839a-90a285a9493c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217682282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.217682282
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2773877846
Short name T37
Test name
Test status
Simulation time 1248542527 ps
CPU time 5.31 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:11 AM PDT 24
Peak memory 217604 kb
Host smart-b992d299-4d89-4691-a357-f496a6bb2bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773877846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2773877846
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3243650250
Short name T177
Test name
Test status
Simulation time 244445132 ps
CPU time 1.08 seconds
Started Jul 02 08:00:56 AM PDT 24
Finished Jul 02 08:01:18 AM PDT 24
Peak memory 217416 kb
Host smart-74239295-3aa5-493b-aba8-3c967372628a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243650250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3243650250
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3572878845
Short name T355
Test name
Test status
Simulation time 141490687 ps
CPU time 0.87 seconds
Started Jul 02 08:00:36 AM PDT 24
Finished Jul 02 08:00:54 AM PDT 24
Peak memory 199964 kb
Host smart-5d6f50bc-81bb-4d0b-b335-7bf0cca8cd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572878845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3572878845
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3399075196
Short name T66
Test name
Test status
Simulation time 1008699447 ps
CPU time 5.06 seconds
Started Jul 02 08:00:44 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 200328 kb
Host smart-6fe806e6-0b6c-48a7-9cf8-8e52779a2cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399075196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3399075196
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1483497941
Short name T240
Test name
Test status
Simulation time 177356968 ps
CPU time 1.22 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 200128 kb
Host smart-67ab3fc2-1a13-4d58-a043-9688d6a3b56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483497941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1483497941
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.614492716
Short name T174
Test name
Test status
Simulation time 198914969 ps
CPU time 1.37 seconds
Started Jul 02 08:00:54 AM PDT 24
Finished Jul 02 08:01:16 AM PDT 24
Peak memory 200272 kb
Host smart-2490df0c-6e1a-4fb0-ad6a-0edea78379c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614492716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.614492716
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2831163073
Short name T508
Test name
Test status
Simulation time 369585378 ps
CPU time 2 seconds
Started Jul 02 08:00:51 AM PDT 24
Finished Jul 02 08:01:13 AM PDT 24
Peak memory 200384 kb
Host smart-7bcb9bd4-5b70-4822-a54a-0248d7d92dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831163073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2831163073
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.71288472
Short name T331
Test name
Test status
Simulation time 361453307 ps
CPU time 2.01 seconds
Started Jul 02 08:00:56 AM PDT 24
Finished Jul 02 08:01:18 AM PDT 24
Peak memory 200072 kb
Host smart-66b8d64e-5739-4b02-8bd9-e1d73c03f922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71288472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.71288472
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2644478739
Short name T317
Test name
Test status
Simulation time 94529787 ps
CPU time 0.98 seconds
Started Jul 02 08:00:42 AM PDT 24
Finished Jul 02 08:01:02 AM PDT 24
Peak memory 200144 kb
Host smart-fe9b71d4-06cd-41b8-ad9b-cc8f06e244a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644478739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2644478739
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1965474008
Short name T410
Test name
Test status
Simulation time 68609317 ps
CPU time 0.77 seconds
Started Jul 02 08:00:37 AM PDT 24
Finished Jul 02 08:00:56 AM PDT 24
Peak memory 199864 kb
Host smart-11175e1c-7972-4728-ab26-1b4a32bce831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965474008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1965474008
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2830104393
Short name T53
Test name
Test status
Simulation time 1904295383 ps
CPU time 6.61 seconds
Started Jul 02 08:01:38 AM PDT 24
Finished Jul 02 08:02:03 AM PDT 24
Peak memory 221580 kb
Host smart-217940bb-72ed-4441-8f57-f05c6c4a89a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830104393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2830104393
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3219930942
Short name T373
Test name
Test status
Simulation time 243242892 ps
CPU time 1.09 seconds
Started Jul 02 08:00:34 AM PDT 24
Finished Jul 02 08:00:52 AM PDT 24
Peak memory 217504 kb
Host smart-e0c6181a-5825-4660-a988-98dca27650d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219930942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3219930942
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2153964218
Short name T337
Test name
Test status
Simulation time 144814954 ps
CPU time 0.81 seconds
Started Jul 02 08:00:27 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 199948 kb
Host smart-a998774e-a1f1-4864-b606-5cab4dfc7b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153964218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2153964218
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2912254521
Short name T491
Test name
Test status
Simulation time 1523534646 ps
CPU time 5.54 seconds
Started Jul 02 08:00:57 AM PDT 24
Finished Jul 02 08:01:23 AM PDT 24
Peak memory 200420 kb
Host smart-c3702f25-2132-4038-8783-bd0a29d0525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912254521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2912254521
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2485348926
Short name T543
Test name
Test status
Simulation time 101285219 ps
CPU time 0.97 seconds
Started Jul 02 08:01:28 AM PDT 24
Finished Jul 02 08:01:48 AM PDT 24
Peak memory 198820 kb
Host smart-ea95ccc0-4573-4c82-a039-d92158484cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485348926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2485348926
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1863033715
Short name T446
Test name
Test status
Simulation time 119107859 ps
CPU time 1.18 seconds
Started Jul 02 08:00:52 AM PDT 24
Finished Jul 02 08:01:13 AM PDT 24
Peak memory 200284 kb
Host smart-158663fb-39a9-4315-9609-be17eaacdf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863033715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1863033715
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1257735613
Short name T85
Test name
Test status
Simulation time 8002459833 ps
CPU time 30 seconds
Started Jul 02 08:00:53 AM PDT 24
Finished Jul 02 08:01:44 AM PDT 24
Peak memory 208656 kb
Host smart-b0c247d6-a087-4cd7-9cf3-c566e1ac3066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257735613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1257735613
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2908336082
Short name T215
Test name
Test status
Simulation time 459318890 ps
CPU time 2.42 seconds
Started Jul 02 08:00:40 AM PDT 24
Finished Jul 02 08:01:00 AM PDT 24
Peak memory 200100 kb
Host smart-0239afe8-2a47-44cc-a1bd-baac5eb2d327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908336082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2908336082
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.825211462
Short name T275
Test name
Test status
Simulation time 65664023 ps
CPU time 0.76 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:00 AM PDT 24
Peak memory 200168 kb
Host smart-ce91cb79-d4d5-4165-a6af-73b64e759c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825211462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.825211462
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.299623200
Short name T485
Test name
Test status
Simulation time 78068290 ps
CPU time 0.86 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:39 AM PDT 24
Peak memory 199868 kb
Host smart-462a7f6b-f0c5-4a64-a8a1-371116851df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299623200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.299623200
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2079233040
Short name T457
Test name
Test status
Simulation time 1255795103 ps
CPU time 5.21 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:43 AM PDT 24
Peak memory 217548 kb
Host smart-b6d0e3b3-7b51-4d80-a337-c7faafc9e9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079233040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2079233040
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2623482001
Short name T278
Test name
Test status
Simulation time 244952609 ps
CPU time 1.13 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 217512 kb
Host smart-1a7e937d-a1f8-4549-8ccb-5fc0679491bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623482001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2623482001
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.86432491
Short name T545
Test name
Test status
Simulation time 195274273 ps
CPU time 0.92 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 199944 kb
Host smart-451acc3f-4eb9-4520-80d9-69bd30c51014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86432491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.86432491
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2145137444
Short name T472
Test name
Test status
Simulation time 1411207080 ps
CPU time 5.57 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:11 AM PDT 24
Peak memory 200404 kb
Host smart-863169f6-4857-499d-80e1-96c7a242b1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145137444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2145137444
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.106198309
Short name T77
Test name
Test status
Simulation time 16779257248 ps
CPU time 23.98 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:01:03 AM PDT 24
Peak memory 218192 kb
Host smart-94e5747d-dcb3-4356-b351-3500d2fe6aea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106198309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.106198309
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2316477039
Short name T266
Test name
Test status
Simulation time 176413649 ps
CPU time 1.15 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 200316 kb
Host smart-cb4de2b3-f12a-48cd-b25f-0607ec8592e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316477039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2316477039
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1627652338
Short name T305
Test name
Test status
Simulation time 191205552 ps
CPU time 1.31 seconds
Started Jul 02 08:00:12 AM PDT 24
Finished Jul 02 08:00:24 AM PDT 24
Peak memory 200352 kb
Host smart-6d66df89-1e70-4156-9490-b9be4f44a17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627652338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1627652338
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.4019500886
Short name T512
Test name
Test status
Simulation time 230833388 ps
CPU time 1.58 seconds
Started Jul 02 08:00:36 AM PDT 24
Finished Jul 02 08:00:55 AM PDT 24
Peak memory 200400 kb
Host smart-f24e1256-5c78-4104-a45f-a797faa51917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019500886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.4019500886
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.746821749
Short name T229
Test name
Test status
Simulation time 303793071 ps
CPU time 2.08 seconds
Started Jul 02 08:00:36 AM PDT 24
Finished Jul 02 08:00:56 AM PDT 24
Peak memory 208308 kb
Host smart-c0c478e2-399e-4218-a785-c340c0715a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746821749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.746821749
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3913611950
Short name T465
Test name
Test status
Simulation time 153332149 ps
CPU time 1.17 seconds
Started Jul 02 08:00:21 AM PDT 24
Finished Jul 02 08:00:36 AM PDT 24
Peak memory 200172 kb
Host smart-efb27ed2-7481-4f8a-8718-c901f4021061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913611950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3913611950
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.487567634
Short name T169
Test name
Test status
Simulation time 74782961 ps
CPU time 0.75 seconds
Started Jul 02 08:00:34 AM PDT 24
Finished Jul 02 08:00:53 AM PDT 24
Peak memory 199924 kb
Host smart-11cef67c-da6a-4d09-9e29-c309ff046f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487567634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.487567634
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.568593651
Short name T372
Test name
Test status
Simulation time 1898704171 ps
CPU time 6.7 seconds
Started Jul 02 08:01:33 AM PDT 24
Finished Jul 02 08:01:58 AM PDT 24
Peak memory 217556 kb
Host smart-db408938-46e2-4b77-aca2-4ddd7d4842fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568593651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.568593651
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1928509705
Short name T513
Test name
Test status
Simulation time 244069428 ps
CPU time 1.05 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 217492 kb
Host smart-1bda761b-5345-41d5-9c90-244c0c93441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928509705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1928509705
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1724077106
Short name T363
Test name
Test status
Simulation time 202856572 ps
CPU time 0.93 seconds
Started Jul 02 08:00:45 AM PDT 24
Finished Jul 02 08:01:06 AM PDT 24
Peak memory 199940 kb
Host smart-5250f290-1f09-4575-8926-58a4141fe4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724077106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1724077106
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2506032694
Short name T176
Test name
Test status
Simulation time 1372203700 ps
CPU time 5.27 seconds
Started Jul 02 08:00:40 AM PDT 24
Finished Jul 02 08:01:03 AM PDT 24
Peak memory 200392 kb
Host smart-e9e96b98-0b86-47be-83f3-316ebaa0c4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506032694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2506032694
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1818925167
Short name T348
Test name
Test status
Simulation time 144538354 ps
CPU time 1.12 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 200120 kb
Host smart-68dea8c7-38e6-4b75-be11-0e934a46759f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818925167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1818925167
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2786306719
Short name T371
Test name
Test status
Simulation time 125700014 ps
CPU time 1.15 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 200324 kb
Host smart-95bbbd28-aea5-4a4c-8021-d4ba300acb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786306719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2786306719
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3554377514
Short name T148
Test name
Test status
Simulation time 1977376101 ps
CPU time 6.8 seconds
Started Jul 02 08:00:42 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 200392 kb
Host smart-03b37fcb-3db7-4fb5-9d0e-bf0da8416bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554377514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3554377514
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2664520996
Short name T437
Test name
Test status
Simulation time 553499325 ps
CPU time 2.73 seconds
Started Jul 02 08:01:41 AM PDT 24
Finished Jul 02 08:02:01 AM PDT 24
Peak memory 200000 kb
Host smart-c6a213f6-acb2-4b0b-857e-04008a51ffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664520996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2664520996
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3185522921
Short name T251
Test name
Test status
Simulation time 94658462 ps
CPU time 0.86 seconds
Started Jul 02 08:00:58 AM PDT 24
Finished Jul 02 08:01:19 AM PDT 24
Peak memory 200156 kb
Host smart-5e2a6ca4-3f6f-4227-9315-f6d41b13181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185522921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3185522921
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.830533012
Short name T388
Test name
Test status
Simulation time 73994824 ps
CPU time 0.79 seconds
Started Jul 02 08:00:58 AM PDT 24
Finished Jul 02 08:01:18 AM PDT 24
Peak memory 199868 kb
Host smart-75fa96c2-d8e4-48d3-af91-d424b12a9b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830533012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.830533012
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2093800494
Short name T401
Test name
Test status
Simulation time 1889876100 ps
CPU time 7.42 seconds
Started Jul 02 08:01:42 AM PDT 24
Finished Jul 02 08:02:06 AM PDT 24
Peak memory 221576 kb
Host smart-d16c2699-6637-47e2-95a5-ed50a472ec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093800494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2093800494
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2241623086
Short name T8
Test name
Test status
Simulation time 245192368 ps
CPU time 1.11 seconds
Started Jul 02 08:01:43 AM PDT 24
Finished Jul 02 08:02:01 AM PDT 24
Peak memory 217040 kb
Host smart-a6bcb674-b091-4d81-979d-2ec7b417d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241623086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2241623086
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.188027222
Short name T456
Test name
Test status
Simulation time 188875116 ps
CPU time 0.84 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:01:56 AM PDT 24
Peak memory 199796 kb
Host smart-b3c1ff4e-5bba-42ec-9943-98de2ae90998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188027222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.188027222
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2350686388
Short name T170
Test name
Test status
Simulation time 1393084020 ps
CPU time 4.87 seconds
Started Jul 02 08:01:28 AM PDT 24
Finished Jul 02 08:01:52 AM PDT 24
Peak memory 199048 kb
Host smart-55214e22-748c-43e0-85c2-471fc7c2aedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350686388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2350686388
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3048782925
Short name T511
Test name
Test status
Simulation time 178583084 ps
CPU time 1.11 seconds
Started Jul 02 08:01:44 AM PDT 24
Finished Jul 02 08:02:02 AM PDT 24
Peak memory 199992 kb
Host smart-f9b7bf76-3b19-4acc-a7fa-89974f5f4f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048782925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3048782925
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2599636162
Short name T262
Test name
Test status
Simulation time 254151578 ps
CPU time 1.42 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:01:56 AM PDT 24
Peak memory 200180 kb
Host smart-3e2ae572-dd56-478e-b384-ca766cfa2e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599636162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2599636162
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.594174314
Short name T207
Test name
Test status
Simulation time 323657020 ps
CPU time 1.87 seconds
Started Jul 02 08:00:27 AM PDT 24
Finished Jul 02 08:00:46 AM PDT 24
Peak memory 200112 kb
Host smart-c80e7740-3bad-4dcc-8596-b860ad0c27f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594174314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.594174314
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3242357046
Short name T455
Test name
Test status
Simulation time 331481864 ps
CPU time 2.29 seconds
Started Jul 02 08:00:53 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 208324 kb
Host smart-cb26fb7c-42a6-4781-b4fe-1611ec5adf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242357046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3242357046
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3580918588
Short name T323
Test name
Test status
Simulation time 142651442 ps
CPU time 1.04 seconds
Started Jul 02 08:00:30 AM PDT 24
Finished Jul 02 08:00:47 AM PDT 24
Peak memory 200144 kb
Host smart-f112e9c5-f528-4161-be92-837c7a8fbc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580918588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3580918588
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1239382125
Short name T253
Test name
Test status
Simulation time 69074845 ps
CPU time 0.78 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 199908 kb
Host smart-8bef49ff-e68e-4802-8b60-096738122a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239382125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1239382125
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.4223854598
Short name T44
Test name
Test status
Simulation time 1238492426 ps
CPU time 5.42 seconds
Started Jul 02 08:00:30 AM PDT 24
Finished Jul 02 08:00:52 AM PDT 24
Peak memory 217796 kb
Host smart-bdcf0b2f-e8e7-4cdd-a45b-a3e5930a24df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223854598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.4223854598
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.919083215
Short name T31
Test name
Test status
Simulation time 243982072 ps
CPU time 1.01 seconds
Started Jul 02 08:01:54 AM PDT 24
Finished Jul 02 08:02:10 AM PDT 24
Peak memory 217348 kb
Host smart-57b75b60-3d3e-4691-a1fd-9692058344b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919083215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.919083215
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2492702104
Short name T18
Test name
Test status
Simulation time 160276216 ps
CPU time 0.88 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:00 AM PDT 24
Peak memory 199864 kb
Host smart-1d2ec42a-c62e-4fbe-9ee2-5a3e83ba858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492702104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2492702104
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3713674078
Short name T486
Test name
Test status
Simulation time 1961002975 ps
CPU time 6.75 seconds
Started Jul 02 08:00:45 AM PDT 24
Finished Jul 02 08:01:12 AM PDT 24
Peak memory 200404 kb
Host smart-ad48287a-12e4-4b61-85a7-78aac6f1e631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713674078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3713674078
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1421710504
Short name T166
Test name
Test status
Simulation time 109905127 ps
CPU time 0.96 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:01:55 AM PDT 24
Peak memory 200000 kb
Host smart-e0403ce4-9952-49ea-9344-c9ec9c38182a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421710504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1421710504
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.500266641
Short name T65
Test name
Test status
Simulation time 185821581 ps
CPU time 1.36 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 200316 kb
Host smart-4f56eb32-ba61-425d-b00c-8d34e832e942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500266641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.500266641
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1526877765
Short name T519
Test name
Test status
Simulation time 8073429208 ps
CPU time 30.61 seconds
Started Jul 02 08:00:27 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 208440 kb
Host smart-9a0081a9-3e49-4ee3-b2d7-9548e7eabf5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526877765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1526877765
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1870050026
Short name T460
Test name
Test status
Simulation time 378324780 ps
CPU time 2.42 seconds
Started Jul 02 08:01:38 AM PDT 24
Finished Jul 02 08:01:58 AM PDT 24
Peak memory 200000 kb
Host smart-661f81cd-585a-4ab1-8d5b-dc8ccd546dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870050026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1870050026
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3143891838
Short name T541
Test name
Test status
Simulation time 71999007 ps
CPU time 0.71 seconds
Started Jul 02 08:01:41 AM PDT 24
Finished Jul 02 08:01:59 AM PDT 24
Peak memory 199632 kb
Host smart-2e0419ea-3fd8-4a28-8137-c232b6daf2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143891838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3143891838
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3071335272
Short name T238
Test name
Test status
Simulation time 69239836 ps
CPU time 0.75 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:07 AM PDT 24
Peak memory 199840 kb
Host smart-25d4841b-bf3b-4b84-8004-6840aac9c745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071335272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3071335272
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3744112845
Short name T399
Test name
Test status
Simulation time 1228081738 ps
CPU time 5.36 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:12 AM PDT 24
Peak memory 221784 kb
Host smart-35de09b5-e817-43a9-a729-7cd4b2d0df5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744112845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3744112845
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.352853792
Short name T185
Test name
Test status
Simulation time 245624216 ps
CPU time 1.02 seconds
Started Jul 02 08:01:02 AM PDT 24
Finished Jul 02 08:01:22 AM PDT 24
Peak memory 217520 kb
Host smart-f4552993-8edc-47bf-8e73-1cb801c87ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352853792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.352853792
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2077225343
Short name T26
Test name
Test status
Simulation time 128286647 ps
CPU time 0.77 seconds
Started Jul 02 08:00:52 AM PDT 24
Finished Jul 02 08:01:13 AM PDT 24
Peak memory 199820 kb
Host smart-1e3dcc4d-42fe-465d-8ce8-d0b5de1cba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077225343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2077225343
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3664622279
Short name T285
Test name
Test status
Simulation time 1405539799 ps
CPU time 5.48 seconds
Started Jul 02 08:00:52 AM PDT 24
Finished Jul 02 08:01:18 AM PDT 24
Peak memory 200604 kb
Host smart-dc121251-21a2-4e1e-982f-56c477c10469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664622279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3664622279
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.211224336
Short name T58
Test name
Test status
Simulation time 98819093 ps
CPU time 0.99 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 200008 kb
Host smart-54a65055-397f-4c5f-b8e5-6d6fec701f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211224336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.211224336
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2191206571
Short name T537
Test name
Test status
Simulation time 116207009 ps
CPU time 1.16 seconds
Started Jul 02 08:00:54 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 200288 kb
Host smart-be88de5a-04dd-4d41-be68-e9092b7be142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191206571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2191206571
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.811338009
Short name T400
Test name
Test status
Simulation time 1876828486 ps
CPU time 8.21 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 208604 kb
Host smart-49023e48-cc92-4b6b-b697-d417af2fc677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811338009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.811338009
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3889135794
Short name T151
Test name
Test status
Simulation time 405991490 ps
CPU time 2.41 seconds
Started Jul 02 08:00:43 AM PDT 24
Finished Jul 02 08:01:04 AM PDT 24
Peak memory 200172 kb
Host smart-e19236e3-dfa5-458d-8d6e-effb345e7e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889135794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3889135794
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3954321996
Short name T28
Test name
Test status
Simulation time 102821068 ps
CPU time 0.96 seconds
Started Jul 02 08:00:54 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 200160 kb
Host smart-f093b5e2-b1d4-4d0a-9d43-31ad7dce3dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954321996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3954321996
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.37541899
Short name T423
Test name
Test status
Simulation time 97404394 ps
CPU time 0.91 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 199916 kb
Host smart-31eb7934-5be9-49c9-a36e-da1669d0f4d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37541899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.37541899
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1960801561
Short name T528
Test name
Test status
Simulation time 1222787708 ps
CPU time 5.93 seconds
Started Jul 02 08:00:45 AM PDT 24
Finished Jul 02 08:01:11 AM PDT 24
Peak memory 221732 kb
Host smart-5f879753-ad5f-481e-b135-c177df7cac15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960801561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1960801561
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3176260105
Short name T237
Test name
Test status
Simulation time 246120429 ps
CPU time 1.01 seconds
Started Jul 02 08:00:50 AM PDT 24
Finished Jul 02 08:01:11 AM PDT 24
Peak memory 217532 kb
Host smart-97be8240-d08b-4ba2-a962-cc83bb07c586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176260105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3176260105
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.4009059489
Short name T439
Test name
Test status
Simulation time 86410098 ps
CPU time 0.79 seconds
Started Jul 02 08:00:42 AM PDT 24
Finished Jul 02 08:01:02 AM PDT 24
Peak memory 199968 kb
Host smart-7b40925a-20f4-4d08-925b-3515a596b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009059489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.4009059489
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2737697510
Short name T208
Test name
Test status
Simulation time 1510635668 ps
CPU time 5.45 seconds
Started Jul 02 08:00:35 AM PDT 24
Finished Jul 02 08:00:58 AM PDT 24
Peak memory 200320 kb
Host smart-3c8bc021-e63b-4aff-81a3-8bf53a61a258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737697510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2737697510
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3735942219
Short name T158
Test name
Test status
Simulation time 102940722 ps
CPU time 1 seconds
Started Jul 02 08:00:42 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 200060 kb
Host smart-a37543ad-e4bb-4932-b996-64a99318622d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735942219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3735942219
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1698652343
Short name T320
Test name
Test status
Simulation time 114898394 ps
CPU time 1.15 seconds
Started Jul 02 08:01:01 AM PDT 24
Finished Jul 02 08:01:22 AM PDT 24
Peak memory 200316 kb
Host smart-d64b0046-5209-446c-899a-c1e3b768b586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698652343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1698652343
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3288731272
Short name T13
Test name
Test status
Simulation time 1579626278 ps
CPU time 6.08 seconds
Started Jul 02 08:00:55 AM PDT 24
Finished Jul 02 08:01:20 AM PDT 24
Peak memory 200420 kb
Host smart-623b84e4-7b5f-4235-8e90-cf773cb1f6d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288731272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3288731272
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2999425043
Short name T385
Test name
Test status
Simulation time 395328626 ps
CPU time 2.12 seconds
Started Jul 02 08:00:44 AM PDT 24
Finished Jul 02 08:01:05 AM PDT 24
Peak memory 200136 kb
Host smart-7d88662e-429e-49a3-a29c-c875814cdccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999425043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2999425043
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3972596266
Short name T27
Test name
Test status
Simulation time 182241802 ps
CPU time 1.19 seconds
Started Jul 02 08:00:54 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 200080 kb
Host smart-df30db11-281e-4412-82b1-329f1eb797cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972596266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3972596266
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3555663196
Short name T467
Test name
Test status
Simulation time 78207525 ps
CPU time 0.81 seconds
Started Jul 02 08:00:54 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 199952 kb
Host smart-cc820be6-bc57-4b65-9f00-41ab22117926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555663196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3555663196
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3703063785
Short name T49
Test name
Test status
Simulation time 1222919876 ps
CPU time 5.32 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:12 AM PDT 24
Peak memory 216896 kb
Host smart-64601277-deef-4d80-b8b9-0a682fe6083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703063785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3703063785
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1995666155
Short name T1
Test name
Test status
Simulation time 249360618 ps
CPU time 1.02 seconds
Started Jul 02 08:00:54 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 217528 kb
Host smart-54782236-125a-4dcb-a11a-50936f487f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995666155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1995666155
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2458489139
Short name T365
Test name
Test status
Simulation time 215663652 ps
CPU time 0.88 seconds
Started Jul 02 08:00:40 AM PDT 24
Finished Jul 02 08:00:59 AM PDT 24
Peak memory 199864 kb
Host smart-767838e6-b54c-4014-bb4f-ec987dfd92f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458489139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2458489139
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.846521695
Short name T112
Test name
Test status
Simulation time 834614854 ps
CPU time 4.16 seconds
Started Jul 02 08:00:49 AM PDT 24
Finished Jul 02 08:01:14 AM PDT 24
Peak memory 200408 kb
Host smart-effbe452-8b55-428a-b4b6-2e7a0f0eb16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846521695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.846521695
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.4213034646
Short name T32
Test name
Test status
Simulation time 149368695 ps
CPU time 1.19 seconds
Started Jul 02 08:00:43 AM PDT 24
Finished Jul 02 08:01:03 AM PDT 24
Peak memory 200072 kb
Host smart-cac5a712-8415-4ff4-8768-5cf0411e3b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213034646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.4213034646
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2444498549
Short name T454
Test name
Test status
Simulation time 192166086 ps
CPU time 1.32 seconds
Started Jul 02 08:01:10 AM PDT 24
Finished Jul 02 08:01:31 AM PDT 24
Peak memory 200324 kb
Host smart-50c2daf6-bc2b-48f5-bdc8-d5d3a9e528a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444498549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2444498549
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.4292300005
Short name T419
Test name
Test status
Simulation time 622628461 ps
CPU time 2.8 seconds
Started Jul 02 08:01:00 AM PDT 24
Finished Jul 02 08:01:22 AM PDT 24
Peak memory 200352 kb
Host smart-d98f072a-ab4c-4169-a477-f35db6769c5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292300005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.4292300005
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3232507498
Short name T297
Test name
Test status
Simulation time 344487250 ps
CPU time 2.15 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 200188 kb
Host smart-58ec2ea7-b147-4319-93c6-16745cda11b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232507498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3232507498
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3068227452
Short name T198
Test name
Test status
Simulation time 185457725 ps
CPU time 1.24 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 200076 kb
Host smart-312892b1-9ee5-4607-b6f2-318c05c935e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068227452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3068227452
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2589443154
Short name T2
Test name
Test status
Simulation time 69533248 ps
CPU time 0.76 seconds
Started Jul 02 08:01:10 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 199860 kb
Host smart-796ea7d0-a09d-4701-af17-d95803cf65b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589443154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2589443154
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1775512958
Short name T56
Test name
Test status
Simulation time 1223745846 ps
CPU time 5.94 seconds
Started Jul 02 08:00:44 AM PDT 24
Finished Jul 02 08:01:09 AM PDT 24
Peak memory 217728 kb
Host smart-d6f6ece2-e9d4-4cff-8205-e84e51dd25a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775512958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1775512958
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3005206167
Short name T282
Test name
Test status
Simulation time 245649375 ps
CPU time 1.03 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 217532 kb
Host smart-075b82cb-9e6e-4eee-8211-86bfa9ad4635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005206167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3005206167
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1531981545
Short name T434
Test name
Test status
Simulation time 147576087 ps
CPU time 0.87 seconds
Started Jul 02 08:00:49 AM PDT 24
Finished Jul 02 08:01:09 AM PDT 24
Peak memory 199976 kb
Host smart-0995ec99-9921-48cf-aec6-1590b365e153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531981545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1531981545
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.608476897
Short name T193
Test name
Test status
Simulation time 695704537 ps
CPU time 3.67 seconds
Started Jul 02 08:00:40 AM PDT 24
Finished Jul 02 08:01:03 AM PDT 24
Peak memory 200384 kb
Host smart-90e8ba9d-cc92-42d7-89e7-95e3d3180ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608476897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.608476897
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.4054514913
Short name T327
Test name
Test status
Simulation time 98249001 ps
CPU time 1.02 seconds
Started Jul 02 08:00:52 AM PDT 24
Finished Jul 02 08:01:12 AM PDT 24
Peak memory 200144 kb
Host smart-31001bac-f0e4-4182-b2ea-c707c500ca7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054514913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.4054514913
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3391603486
Short name T61
Test name
Test status
Simulation time 121735745 ps
CPU time 1.15 seconds
Started Jul 02 08:01:04 AM PDT 24
Finished Jul 02 08:01:24 AM PDT 24
Peak memory 200340 kb
Host smart-f079b2b9-13ad-41d1-bb4b-7e766adc3aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391603486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3391603486
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3814910764
Short name T160
Test name
Test status
Simulation time 4978579259 ps
CPU time 17.22 seconds
Started Jul 02 08:01:04 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 200452 kb
Host smart-95d3de70-1800-4f91-807c-cfce65346add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814910764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3814910764
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2569955596
Short name T309
Test name
Test status
Simulation time 144910110 ps
CPU time 1.91 seconds
Started Jul 02 08:01:09 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 200124 kb
Host smart-9abe0b8a-9b95-453a-b744-dbcba92e0583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569955596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2569955596
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2718900742
Short name T6
Test name
Test status
Simulation time 90202592 ps
CPU time 0.89 seconds
Started Jul 02 08:00:48 AM PDT 24
Finished Jul 02 08:01:09 AM PDT 24
Peak memory 200172 kb
Host smart-52eabf98-cce3-4d35-8b2b-54d32e8e6b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718900742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2718900742
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2760768487
Short name T205
Test name
Test status
Simulation time 68771966 ps
CPU time 0.75 seconds
Started Jul 02 08:00:58 AM PDT 24
Finished Jul 02 08:01:18 AM PDT 24
Peak memory 199944 kb
Host smart-1e7ebf58-f73d-4fa2-9510-0720d52c2d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760768487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2760768487
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3309069823
Short name T277
Test name
Test status
Simulation time 1215757213 ps
CPU time 5.71 seconds
Started Jul 02 08:00:51 AM PDT 24
Finished Jul 02 08:01:17 AM PDT 24
Peak memory 217820 kb
Host smart-61653267-f40e-44db-beb1-22a39a761688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309069823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3309069823
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2188972495
Short name T387
Test name
Test status
Simulation time 244109994 ps
CPU time 1.05 seconds
Started Jul 02 08:00:55 AM PDT 24
Finished Jul 02 08:01:16 AM PDT 24
Peak memory 217500 kb
Host smart-a6c3ba81-5ed6-40ba-9ccf-b3af1a033d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188972495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2188972495
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2886215404
Short name T25
Test name
Test status
Simulation time 102318505 ps
CPU time 0.74 seconds
Started Jul 02 08:00:55 AM PDT 24
Finished Jul 02 08:01:16 AM PDT 24
Peak memory 199976 kb
Host smart-cb174c1e-d6df-48f4-9c8e-4144c3d32121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886215404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2886215404
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1712722452
Short name T313
Test name
Test status
Simulation time 831953128 ps
CPU time 3.91 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:11 AM PDT 24
Peak memory 200416 kb
Host smart-db4ea49a-7fab-4d30-9587-2fa960ee933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712722452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1712722452
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1776682252
Short name T191
Test name
Test status
Simulation time 173567727 ps
CPU time 1.2 seconds
Started Jul 02 08:00:59 AM PDT 24
Finished Jul 02 08:01:20 AM PDT 24
Peak memory 200160 kb
Host smart-20f21f6c-6373-4481-bdf5-0533183a2bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776682252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1776682252
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1058507117
Short name T403
Test name
Test status
Simulation time 189615673 ps
CPU time 1.38 seconds
Started Jul 02 08:00:57 AM PDT 24
Finished Jul 02 08:01:18 AM PDT 24
Peak memory 200340 kb
Host smart-d840ad84-471f-4e9c-9791-e1d894aa5cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058507117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1058507117
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.265074375
Short name T504
Test name
Test status
Simulation time 6062541687 ps
CPU time 20.78 seconds
Started Jul 02 08:00:48 AM PDT 24
Finished Jul 02 08:01:29 AM PDT 24
Peak memory 200444 kb
Host smart-62d85c4e-ccac-44e9-9c57-718fbdeaccf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265074375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.265074375
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1600287150
Short name T353
Test name
Test status
Simulation time 146235350 ps
CPU time 1.81 seconds
Started Jul 02 08:00:50 AM PDT 24
Finished Jul 02 08:01:12 AM PDT 24
Peak memory 200132 kb
Host smart-cf5033ea-92b8-4b43-8468-b934890c72a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600287150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1600287150
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1662658712
Short name T497
Test name
Test status
Simulation time 201610684 ps
CPU time 1.25 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 200156 kb
Host smart-405a7621-d402-41fc-a453-43324a4b8d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662658712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1662658712
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1549020088
Short name T184
Test name
Test status
Simulation time 57147385 ps
CPU time 0.7 seconds
Started Jul 02 08:00:56 AM PDT 24
Finished Jul 02 08:01:17 AM PDT 24
Peak memory 199932 kb
Host smart-86388044-7df1-4c82-b21f-9c0de369d87e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549020088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1549020088
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.189767465
Short name T51
Test name
Test status
Simulation time 1216199631 ps
CPU time 5.66 seconds
Started Jul 02 08:01:02 AM PDT 24
Finished Jul 02 08:01:27 AM PDT 24
Peak memory 221744 kb
Host smart-19812074-0a9a-4b71-b82a-62a8dd85f213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189767465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.189767465
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1951716586
Short name T264
Test name
Test status
Simulation time 244204695 ps
CPU time 1.19 seconds
Started Jul 02 08:00:52 AM PDT 24
Finished Jul 02 08:01:13 AM PDT 24
Peak memory 217420 kb
Host smart-316f7671-a5f2-4b41-ae53-20d68823e381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951716586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1951716586
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1784133410
Short name T380
Test name
Test status
Simulation time 94528868 ps
CPU time 0.73 seconds
Started Jul 02 08:00:54 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 199892 kb
Host smart-301bcb78-9f13-45f3-bde6-1c8bc291bc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784133410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1784133410
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1912578290
Short name T496
Test name
Test status
Simulation time 1597870639 ps
CPU time 5.5 seconds
Started Jul 02 08:00:44 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 200384 kb
Host smart-3ebf1b25-23e9-4ee3-8dca-6dc58582c64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912578290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1912578290
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3241383277
Short name T164
Test name
Test status
Simulation time 103574501 ps
CPU time 1.01 seconds
Started Jul 02 08:01:01 AM PDT 24
Finished Jul 02 08:01:21 AM PDT 24
Peak memory 200316 kb
Host smart-ab444608-ed1b-4232-9439-de7aa356fde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241383277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3241383277
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.4076608378
Short name T535
Test name
Test status
Simulation time 205120408 ps
CPU time 1.43 seconds
Started Jul 02 08:00:55 AM PDT 24
Finished Jul 02 08:01:17 AM PDT 24
Peak memory 200328 kb
Host smart-1b70528b-d301-4acd-b000-ee0a744eeb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076608378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.4076608378
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1560503654
Short name T288
Test name
Test status
Simulation time 8057425638 ps
CPU time 28.38 seconds
Started Jul 02 08:00:45 AM PDT 24
Finished Jul 02 08:01:33 AM PDT 24
Peak memory 200444 kb
Host smart-6f619ca5-a1a8-4d57-802f-3196e7b8b0a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560503654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1560503654
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3834027503
Short name T232
Test name
Test status
Simulation time 124570530 ps
CPU time 1.55 seconds
Started Jul 02 08:00:51 AM PDT 24
Finished Jul 02 08:01:13 AM PDT 24
Peak memory 208376 kb
Host smart-563f453a-07da-4268-91c3-d0cf475f14ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834027503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3834027503
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.355382537
Short name T414
Test name
Test status
Simulation time 112855238 ps
CPU time 0.86 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 199836 kb
Host smart-6c38d5a0-1258-4334-a030-d776fe805c35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355382537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.355382537
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2295235248
Short name T45
Test name
Test status
Simulation time 1898580446 ps
CPU time 7.44 seconds
Started Jul 02 08:01:08 AM PDT 24
Finished Jul 02 08:01:34 AM PDT 24
Peak memory 217768 kb
Host smart-c608f967-d46f-4a99-8df9-c56215b91f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295235248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2295235248
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2807213454
Short name T542
Test name
Test status
Simulation time 244701365 ps
CPU time 1.03 seconds
Started Jul 02 08:00:59 AM PDT 24
Finished Jul 02 08:01:20 AM PDT 24
Peak memory 217524 kb
Host smart-96001204-03ca-4d8f-a605-5ce979bba99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807213454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2807213454
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3887847578
Short name T484
Test name
Test status
Simulation time 151787696 ps
CPU time 0.89 seconds
Started Jul 02 08:01:02 AM PDT 24
Finished Jul 02 08:01:22 AM PDT 24
Peak memory 199960 kb
Host smart-acf32cab-15d0-4ddc-9bc4-daf22c983a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887847578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3887847578
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.563945686
Short name T367
Test name
Test status
Simulation time 2015376075 ps
CPU time 6.84 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:06 AM PDT 24
Peak memory 200628 kb
Host smart-1dd3a519-7bf3-4a25-958d-26c20a5013dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563945686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.563945686
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1568596037
Short name T187
Test name
Test status
Simulation time 142786771 ps
CPU time 1.1 seconds
Started Jul 02 08:01:08 AM PDT 24
Finished Jul 02 08:01:29 AM PDT 24
Peak memory 200144 kb
Host smart-652d85b7-a544-4b2b-a8f1-cca5e6d18ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568596037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1568596037
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.4022906474
Short name T374
Test name
Test status
Simulation time 116652327 ps
CPU time 1.15 seconds
Started Jul 02 08:00:53 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 200384 kb
Host smart-b53a5afc-9aee-4efc-9701-4a48cf177a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022906474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.4022906474
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3471934643
Short name T495
Test name
Test status
Simulation time 4968656706 ps
CPU time 18.29 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:25 AM PDT 24
Peak memory 208660 kb
Host smart-fb5e4774-af3e-4c0a-ae50-dfcee0c3b5ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471934643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3471934643
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.853696384
Short name T324
Test name
Test status
Simulation time 142689015 ps
CPU time 1.79 seconds
Started Jul 02 08:00:58 AM PDT 24
Finished Jul 02 08:01:20 AM PDT 24
Peak memory 200132 kb
Host smart-1ca0abf9-092d-4326-92af-4023176b24a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853696384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.853696384
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.484704999
Short name T189
Test name
Test status
Simulation time 150321589 ps
CPU time 1.15 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 200140 kb
Host smart-e8781083-9e68-46d9-93db-a207df25e63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484704999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.484704999
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.755039556
Short name T218
Test name
Test status
Simulation time 74564563 ps
CPU time 0.8 seconds
Started Jul 02 08:00:20 AM PDT 24
Finished Jul 02 08:00:36 AM PDT 24
Peak memory 199844 kb
Host smart-cc427132-399c-4ff1-b682-cc0279f30d2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755039556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.755039556
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2340741161
Short name T425
Test name
Test status
Simulation time 1891667436 ps
CPU time 7.29 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:48 AM PDT 24
Peak memory 217644 kb
Host smart-27fb604b-6c5a-47c8-ae78-430a2b7b10e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340741161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2340741161
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1889019208
Short name T296
Test name
Test status
Simulation time 245023701 ps
CPU time 1.13 seconds
Started Jul 02 08:00:13 AM PDT 24
Finished Jul 02 08:00:25 AM PDT 24
Peak memory 217444 kb
Host smart-56260ca0-7010-4f32-af33-fdb9f2e33c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889019208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1889019208
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3030040325
Short name T518
Test name
Test status
Simulation time 144538159 ps
CPU time 0.79 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:40 AM PDT 24
Peak memory 199892 kb
Host smart-442097fc-81fd-40f8-8449-eece1b8605e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030040325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3030040325
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1440786710
Short name T113
Test name
Test status
Simulation time 989654164 ps
CPU time 5.02 seconds
Started Jul 02 08:00:06 AM PDT 24
Finished Jul 02 08:00:22 AM PDT 24
Peak memory 200452 kb
Host smart-8b7eac2c-a0e3-454d-8d5b-3cf9ba2fe0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440786710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1440786710
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2735155971
Short name T82
Test name
Test status
Simulation time 8295812077 ps
CPU time 16.16 seconds
Started Jul 02 08:00:31 AM PDT 24
Finished Jul 02 08:01:04 AM PDT 24
Peak memory 217256 kb
Host smart-e7d224a6-c59c-4d86-8661-010cfdffeb5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735155971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2735155971
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3185669785
Short name T422
Test name
Test status
Simulation time 154654319 ps
CPU time 1.1 seconds
Started Jul 02 08:00:21 AM PDT 24
Finished Jul 02 08:00:37 AM PDT 24
Peak memory 200168 kb
Host smart-e4f9fa54-035d-4e00-b220-022ae94965ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185669785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3185669785
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1512074543
Short name T463
Test name
Test status
Simulation time 198903792 ps
CPU time 1.33 seconds
Started Jul 02 08:00:38 AM PDT 24
Finished Jul 02 08:00:56 AM PDT 24
Peak memory 200264 kb
Host smart-0640594f-7f3c-460e-a497-155d7dc679c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512074543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1512074543
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1032361598
Short name T249
Test name
Test status
Simulation time 3965942097 ps
CPU time 17.83 seconds
Started Jul 02 08:00:19 AM PDT 24
Finished Jul 02 08:00:52 AM PDT 24
Peak memory 210504 kb
Host smart-c7c0fdea-315f-4891-b297-506575615d72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032361598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1032361598
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2846038046
Short name T14
Test name
Test status
Simulation time 332291691 ps
CPU time 2.08 seconds
Started Jul 02 08:00:27 AM PDT 24
Finished Jul 02 08:00:45 AM PDT 24
Peak memory 208360 kb
Host smart-842dfcf7-851a-42e2-a838-9a16f29ba9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846038046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2846038046
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2362696288
Short name T211
Test name
Test status
Simulation time 57362127 ps
CPU time 0.73 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 199968 kb
Host smart-8ca8ebf1-8c74-43f3-9bf1-26b88a1d3b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362696288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2362696288
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1037506061
Short name T515
Test name
Test status
Simulation time 87412908 ps
CPU time 0.89 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 199936 kb
Host smart-75a65350-3f68-4dfe-a48a-4af55a5160fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037506061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1037506061
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2857914613
Short name T344
Test name
Test status
Simulation time 1229160819 ps
CPU time 5.28 seconds
Started Jul 02 08:00:56 AM PDT 24
Finished Jul 02 08:01:21 AM PDT 24
Peak memory 216804 kb
Host smart-4ca1090a-1592-44f0-9ff0-2344ac6d1a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857914613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2857914613
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.115589709
Short name T34
Test name
Test status
Simulation time 244493858 ps
CPU time 1.03 seconds
Started Jul 02 08:00:52 AM PDT 24
Finished Jul 02 08:01:13 AM PDT 24
Peak memory 217492 kb
Host smart-aafe162a-3e99-4b1a-8082-0254104dc076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115589709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.115589709
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3776819408
Short name T23
Test name
Test status
Simulation time 138027517 ps
CPU time 0.81 seconds
Started Jul 02 08:00:55 AM PDT 24
Finished Jul 02 08:01:16 AM PDT 24
Peak memory 199872 kb
Host smart-3944efd6-b135-4072-a1ca-ac018bc99881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776819408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3776819408
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2440811126
Short name T3
Test name
Test status
Simulation time 1675387030 ps
CPU time 6.19 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:13 AM PDT 24
Peak memory 200460 kb
Host smart-c8fe56f0-da10-4fc2-8414-9f37f2655efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440811126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2440811126
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3499952884
Short name T533
Test name
Test status
Simulation time 189609099 ps
CPU time 1.24 seconds
Started Jul 02 08:01:02 AM PDT 24
Finished Jul 02 08:01:22 AM PDT 24
Peak memory 200068 kb
Host smart-a8857dd4-e96f-44cb-b51e-c8b8ecbd773d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499952884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3499952884
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1639936545
Short name T12
Test name
Test status
Simulation time 119122315 ps
CPU time 1.22 seconds
Started Jul 02 08:01:00 AM PDT 24
Finished Jul 02 08:01:21 AM PDT 24
Peak memory 200308 kb
Host smart-b972a227-d493-4b03-a0b8-75dd23066bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639936545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1639936545
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1844066447
Short name T117
Test name
Test status
Simulation time 1196923261 ps
CPU time 5.92 seconds
Started Jul 02 08:01:06 AM PDT 24
Finished Jul 02 08:01:31 AM PDT 24
Peak memory 209612 kb
Host smart-f386abf3-ce3d-447d-a825-590ee4b39194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844066447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1844066447
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.478788214
Short name T281
Test name
Test status
Simulation time 326123770 ps
CPU time 1.89 seconds
Started Jul 02 08:00:59 AM PDT 24
Finished Jul 02 08:01:21 AM PDT 24
Peak memory 200160 kb
Host smart-8cba7100-cb36-4a37-b822-c87ab3fb4679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478788214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.478788214
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3546764627
Short name T149
Test name
Test status
Simulation time 98749084 ps
CPU time 0.87 seconds
Started Jul 02 08:01:00 AM PDT 24
Finished Jul 02 08:01:20 AM PDT 24
Peak memory 200128 kb
Host smart-2f7672ae-b0f5-4ac0-867c-c1282fd4f56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546764627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3546764627
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1925945127
Short name T59
Test name
Test status
Simulation time 91815923 ps
CPU time 0.89 seconds
Started Jul 02 08:00:50 AM PDT 24
Finished Jul 02 08:01:11 AM PDT 24
Peak memory 199964 kb
Host smart-a284148e-52fc-434a-9ea0-773dff2209ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925945127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1925945127
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2370234895
Short name T427
Test name
Test status
Simulation time 1227923982 ps
CPU time 5.22 seconds
Started Jul 02 08:01:11 AM PDT 24
Finished Jul 02 08:01:35 AM PDT 24
Peak memory 221760 kb
Host smart-b8822e75-af64-40ee-93f6-fad10184b46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370234895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2370234895
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1238486330
Short name T392
Test name
Test status
Simulation time 244330875 ps
CPU time 1.15 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 217532 kb
Host smart-a42a7778-bdeb-4662-b8c9-30026ae44ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238486330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1238486330
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.613606268
Short name T19
Test name
Test status
Simulation time 201248896 ps
CPU time 0.93 seconds
Started Jul 02 08:00:52 AM PDT 24
Finished Jul 02 08:01:13 AM PDT 24
Peak memory 199932 kb
Host smart-f3b77a55-9e02-4fce-9757-ecfe59f3342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613606268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.613606268
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1111921635
Short name T525
Test name
Test status
Simulation time 1693178883 ps
CPU time 6 seconds
Started Jul 02 08:00:46 AM PDT 24
Finished Jul 02 08:01:11 AM PDT 24
Peak memory 200316 kb
Host smart-c847d3c9-c8c7-4058-ae1d-b91528609eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111921635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1111921635
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3454133728
Short name T165
Test name
Test status
Simulation time 137107494 ps
CPU time 1.22 seconds
Started Jul 02 08:00:54 AM PDT 24
Finished Jul 02 08:01:15 AM PDT 24
Peak memory 200088 kb
Host smart-a7427791-98c0-4d80-8985-24e784cadccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454133728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3454133728
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1331062778
Short name T370
Test name
Test status
Simulation time 121992925 ps
CPU time 1.22 seconds
Started Jul 02 08:00:52 AM PDT 24
Finished Jul 02 08:01:13 AM PDT 24
Peak memory 200308 kb
Host smart-fe4bcd82-49d8-41f6-a3fd-49f18831572e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331062778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1331062778
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.132101938
Short name T500
Test name
Test status
Simulation time 950713628 ps
CPU time 4.57 seconds
Started Jul 02 08:00:59 AM PDT 24
Finished Jul 02 08:01:23 AM PDT 24
Peak memory 200396 kb
Host smart-f294e512-536e-441a-954f-8e7d85d57e73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132101938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.132101938
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.613224124
Short name T329
Test name
Test status
Simulation time 127942556 ps
CPU time 1.68 seconds
Started Jul 02 08:00:53 AM PDT 24
Finished Jul 02 08:01:14 AM PDT 24
Peak memory 208392 kb
Host smart-43af91f5-7c69-4130-aac9-4f599a652182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613224124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.613224124
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1257944376
Short name T201
Test name
Test status
Simulation time 71495392 ps
CPU time 0.79 seconds
Started Jul 02 08:01:04 AM PDT 24
Finished Jul 02 08:01:24 AM PDT 24
Peak memory 200152 kb
Host smart-d1783b70-d88c-48f3-9647-92967541f77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257944376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1257944376
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1152151633
Short name T263
Test name
Test status
Simulation time 74984478 ps
CPU time 0.8 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:01:34 AM PDT 24
Peak memory 199952 kb
Host smart-b8683b31-f2bb-4ef3-91f2-520375cc3fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152151633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1152151633
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2679919197
Short name T539
Test name
Test status
Simulation time 2355517543 ps
CPU time 8.67 seconds
Started Jul 02 08:01:12 AM PDT 24
Finished Jul 02 08:01:39 AM PDT 24
Peak memory 217956 kb
Host smart-234d812b-b374-4a66-8cdc-84a92a2378e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679919197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2679919197
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2064860993
Short name T478
Test name
Test status
Simulation time 245068874 ps
CPU time 1.04 seconds
Started Jul 02 08:01:07 AM PDT 24
Finished Jul 02 08:01:31 AM PDT 24
Peak memory 217440 kb
Host smart-582dfb88-ff1f-4766-a1eb-03ad1843a04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064860993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2064860993
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2299288662
Short name T245
Test name
Test status
Simulation time 184492169 ps
CPU time 0.87 seconds
Started Jul 02 08:01:02 AM PDT 24
Finished Jul 02 08:01:22 AM PDT 24
Peak memory 199956 kb
Host smart-f4b7c177-0fc8-4666-a229-243f98613956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299288662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2299288662
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.86556882
Short name T290
Test name
Test status
Simulation time 1895839407 ps
CPU time 8.04 seconds
Started Jul 02 08:00:57 AM PDT 24
Finished Jul 02 08:01:25 AM PDT 24
Peak memory 200432 kb
Host smart-07c82a1a-7ee0-4555-a6c0-3e7428b07920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86556882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.86556882
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1834592026
Short name T186
Test name
Test status
Simulation time 169899349 ps
CPU time 1.12 seconds
Started Jul 02 08:01:01 AM PDT 24
Finished Jul 02 08:01:21 AM PDT 24
Peak memory 200164 kb
Host smart-a6d95a64-8df7-4a1e-897e-ef67f2c692f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834592026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1834592026
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1009914680
Short name T546
Test name
Test status
Simulation time 189193360 ps
CPU time 1.34 seconds
Started Jul 02 08:00:58 AM PDT 24
Finished Jul 02 08:01:19 AM PDT 24
Peak memory 200308 kb
Host smart-d9ac4c6e-f0ac-4f3a-895d-8feb39303b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009914680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1009914680
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.411602651
Short name T476
Test name
Test status
Simulation time 1767303813 ps
CPU time 7.26 seconds
Started Jul 02 08:00:51 AM PDT 24
Finished Jul 02 08:01:19 AM PDT 24
Peak memory 200240 kb
Host smart-6785bd57-271c-4a7e-8108-2dd43431ef90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411602651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.411602651
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4162723479
Short name T203
Test name
Test status
Simulation time 116648674 ps
CPU time 1.42 seconds
Started Jul 02 08:01:08 AM PDT 24
Finished Jul 02 08:01:28 AM PDT 24
Peak memory 200144 kb
Host smart-ee1f8087-f347-435a-9415-36855f1a56c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162723479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4162723479
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2711878603
Short name T311
Test name
Test status
Simulation time 234821055 ps
CPU time 1.39 seconds
Started Jul 02 08:01:07 AM PDT 24
Finished Jul 02 08:01:28 AM PDT 24
Peak memory 200144 kb
Host smart-37878908-fadd-4d4d-bfe3-c6ed708d78b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711878603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2711878603
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1669502549
Short name T109
Test name
Test status
Simulation time 76653010 ps
CPU time 0.79 seconds
Started Jul 02 08:01:10 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 199916 kb
Host smart-20f2070d-da68-45fe-b302-f32ec879ca41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669502549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1669502549
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1362465372
Short name T279
Test name
Test status
Simulation time 1897634608 ps
CPU time 6.93 seconds
Started Jul 02 08:01:16 AM PDT 24
Finished Jul 02 08:01:41 AM PDT 24
Peak memory 217664 kb
Host smart-7d795574-f4e0-42bc-afeb-808ab1f5c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362465372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1362465372
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.856135987
Short name T544
Test name
Test status
Simulation time 244996961 ps
CPU time 1.03 seconds
Started Jul 02 08:01:11 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 217548 kb
Host smart-b8a22126-6bfc-422b-a9b4-8b6fd9f07815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856135987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.856135987
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1593517687
Short name T258
Test name
Test status
Simulation time 212651213 ps
CPU time 0.89 seconds
Started Jul 02 08:01:07 AM PDT 24
Finished Jul 02 08:01:27 AM PDT 24
Peak memory 199924 kb
Host smart-8c86eafa-e091-437d-8ada-4e58876b0899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593517687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1593517687
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.595913770
Short name T4
Test name
Test status
Simulation time 1589835133 ps
CPU time 6.07 seconds
Started Jul 02 08:01:00 AM PDT 24
Finished Jul 02 08:01:26 AM PDT 24
Peak memory 200448 kb
Host smart-1a94916c-7191-40dd-96ee-331367ad2a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595913770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.595913770
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2437389041
Short name T449
Test name
Test status
Simulation time 176247436 ps
CPU time 1.25 seconds
Started Jul 02 08:01:09 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 200168 kb
Host smart-134fa643-254b-4ff5-93b3-c2679be8ddff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437389041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2437389041
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.4001133208
Short name T172
Test name
Test status
Simulation time 202273552 ps
CPU time 1.44 seconds
Started Jul 02 08:01:08 AM PDT 24
Finished Jul 02 08:01:29 AM PDT 24
Peak memory 200260 kb
Host smart-49527967-ce52-49e9-8266-c359b754462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001133208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.4001133208
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3663684835
Short name T475
Test name
Test status
Simulation time 13042973588 ps
CPU time 45.64 seconds
Started Jul 02 08:00:48 AM PDT 24
Finished Jul 02 08:01:54 AM PDT 24
Peak memory 208664 kb
Host smart-06068842-7046-4f06-9529-ef368bf51a8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663684835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3663684835
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1235132800
Short name T302
Test name
Test status
Simulation time 433707214 ps
CPU time 2.25 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:35 AM PDT 24
Peak memory 208320 kb
Host smart-5b5af26a-ce87-4d1f-999f-f66e3969e754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235132800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1235132800
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1936773185
Short name T110
Test name
Test status
Simulation time 91484621 ps
CPU time 0.9 seconds
Started Jul 02 08:01:12 AM PDT 24
Finished Jul 02 08:01:31 AM PDT 24
Peak memory 200156 kb
Host smart-31fd6246-0b38-462b-951b-d23ae3d971a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936773185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1936773185
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.97401388
Short name T190
Test name
Test status
Simulation time 70606023 ps
CPU time 0.83 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:37 AM PDT 24
Peak memory 200168 kb
Host smart-7a340b6e-d8ea-45b0-8274-db7f40d98c5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97401388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.97401388
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1498076345
Short name T452
Test name
Test status
Simulation time 1902179388 ps
CPU time 7.59 seconds
Started Jul 02 08:00:43 AM PDT 24
Finished Jul 02 08:01:09 AM PDT 24
Peak memory 217464 kb
Host smart-9a24529c-7b47-44fd-8852-40264ee19a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498076345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1498076345
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3254646638
Short name T221
Test name
Test status
Simulation time 244568725 ps
CPU time 1.05 seconds
Started Jul 02 08:01:09 AM PDT 24
Finished Jul 02 08:01:29 AM PDT 24
Peak memory 217520 kb
Host smart-dae0008f-41b9-4633-bb3b-c06221c513b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254646638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3254646638
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1406349330
Short name T505
Test name
Test status
Simulation time 245166461 ps
CPU time 1.02 seconds
Started Jul 02 08:01:00 AM PDT 24
Finished Jul 02 08:01:21 AM PDT 24
Peak memory 199892 kb
Host smart-cb927b0d-bdc6-472a-9080-831ecc0367df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406349330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1406349330
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1801076889
Short name T526
Test name
Test status
Simulation time 1538296588 ps
CPU time 6.09 seconds
Started Jul 02 08:00:57 AM PDT 24
Finished Jul 02 08:01:23 AM PDT 24
Peak memory 200444 kb
Host smart-5f45f3f8-00c9-4d91-8d89-c524bd88d5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801076889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1801076889
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1517572626
Short name T196
Test name
Test status
Simulation time 179998209 ps
CPU time 1.16 seconds
Started Jul 02 08:01:01 AM PDT 24
Finished Jul 02 08:01:21 AM PDT 24
Peak memory 200116 kb
Host smart-79fef05d-0576-401b-b6f8-05e558db588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517572626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1517572626
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1442131829
Short name T351
Test name
Test status
Simulation time 223869329 ps
CPU time 1.55 seconds
Started Jul 02 08:01:10 AM PDT 24
Finished Jul 02 08:01:31 AM PDT 24
Peak memory 200332 kb
Host smart-7ed55dce-9d0b-4bb7-a386-17fd15b6315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442131829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1442131829
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3384605829
Short name T115
Test name
Test status
Simulation time 5175063031 ps
CPU time 21.95 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:58 AM PDT 24
Peak memory 208712 kb
Host smart-47c05d95-2771-4ce3-86d4-cc69ac08f372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384605829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3384605829
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1458296926
Short name T379
Test name
Test status
Simulation time 471788401 ps
CPU time 2.63 seconds
Started Jul 02 08:00:51 AM PDT 24
Finished Jul 02 08:01:14 AM PDT 24
Peak memory 200160 kb
Host smart-ff066ffd-109e-4cf5-b0ad-a656c79a258e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458296926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1458296926
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3998578953
Short name T381
Test name
Test status
Simulation time 252407464 ps
CPU time 1.37 seconds
Started Jul 02 08:01:05 AM PDT 24
Finished Jul 02 08:01:26 AM PDT 24
Peak memory 200172 kb
Host smart-2a828683-93dc-442a-b442-9a30d641910b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998578953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3998578953
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1628138855
Short name T181
Test name
Test status
Simulation time 61605301 ps
CPU time 0.73 seconds
Started Jul 02 08:01:00 AM PDT 24
Finished Jul 02 08:01:20 AM PDT 24
Peak memory 199868 kb
Host smart-71025a63-bfde-4d6f-85d5-4cf1144d4340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628138855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1628138855
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1932399833
Short name T48
Test name
Test status
Simulation time 1232996069 ps
CPU time 5.26 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:01:39 AM PDT 24
Peak memory 221736 kb
Host smart-b0947e25-0afc-441c-9355-b9bba93a6b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932399833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1932399833
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2052587849
Short name T92
Test name
Test status
Simulation time 244777981 ps
CPU time 1.06 seconds
Started Jul 02 08:00:58 AM PDT 24
Finished Jul 02 08:01:19 AM PDT 24
Peak memory 217432 kb
Host smart-6e0a3dae-800d-4796-a9c3-35bd3b8e1a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052587849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2052587849
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2530061727
Short name T307
Test name
Test status
Simulation time 175781220 ps
CPU time 0.84 seconds
Started Jul 02 08:01:04 AM PDT 24
Finished Jul 02 08:01:24 AM PDT 24
Peak memory 199960 kb
Host smart-4b010907-88fc-4659-83a7-a869f9e8aee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530061727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2530061727
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3323097267
Short name T118
Test name
Test status
Simulation time 2124052992 ps
CPU time 8.49 seconds
Started Jul 02 08:01:13 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 200420 kb
Host smart-fbf761e4-eda9-41a4-ba80-70699b8102a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323097267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3323097267
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1703741296
Short name T482
Test name
Test status
Simulation time 110081684 ps
CPU time 1.03 seconds
Started Jul 02 08:01:02 AM PDT 24
Finished Jul 02 08:01:22 AM PDT 24
Peak memory 200128 kb
Host smart-330b1d02-940f-440e-805a-cf9f1c594f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703741296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1703741296
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2765508419
Short name T150
Test name
Test status
Simulation time 231708995 ps
CPU time 1.41 seconds
Started Jul 02 08:01:09 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 200316 kb
Host smart-d8e80ae8-88b1-4a0f-94d1-ea31e9d3ca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765508419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2765508419
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3233990155
Short name T306
Test name
Test status
Simulation time 2743335440 ps
CPU time 12.89 seconds
Started Jul 02 08:01:12 AM PDT 24
Finished Jul 02 08:01:43 AM PDT 24
Peak memory 208472 kb
Host smart-a67e0d2e-2df6-4307-bea1-bdade80fb31c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233990155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3233990155
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1846339644
Short name T527
Test name
Test status
Simulation time 469952767 ps
CPU time 2.59 seconds
Started Jul 02 08:01:07 AM PDT 24
Finished Jul 02 08:01:29 AM PDT 24
Peak memory 200160 kb
Host smart-9d62b72a-2ee8-4b07-be4b-3d5ba6626902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846339644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1846339644
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2638384243
Short name T212
Test name
Test status
Simulation time 221206285 ps
CPU time 1.39 seconds
Started Jul 02 08:01:03 AM PDT 24
Finished Jul 02 08:01:24 AM PDT 24
Peak memory 200172 kb
Host smart-90cbe6c3-f7f7-46c1-aed4-7aaccbd8385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638384243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2638384243
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1591550426
Short name T227
Test name
Test status
Simulation time 65997636 ps
CPU time 0.76 seconds
Started Jul 02 08:01:01 AM PDT 24
Finished Jul 02 08:01:21 AM PDT 24
Peak memory 199932 kb
Host smart-60f8f0f5-0712-44ce-a9a0-632849998e8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591550426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1591550426
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.954930025
Short name T536
Test name
Test status
Simulation time 1896258478 ps
CPU time 6.84 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 217548 kb
Host smart-5c9d6252-9630-4a97-a96b-d3726a9e7274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954930025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.954930025
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2112645643
Short name T289
Test name
Test status
Simulation time 244371317 ps
CPU time 1.02 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:34 AM PDT 24
Peak memory 217476 kb
Host smart-83059858-1aa3-4823-86fc-2d8f115c98ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112645643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2112645643
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.755410160
Short name T22
Test name
Test status
Simulation time 139448904 ps
CPU time 0.88 seconds
Started Jul 02 08:01:13 AM PDT 24
Finished Jul 02 08:01:33 AM PDT 24
Peak memory 199888 kb
Host smart-d5caedd6-f281-4a60-a853-2fbf13cd88c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755410160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.755410160
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.206656068
Short name T328
Test name
Test status
Simulation time 1926503974 ps
CPU time 6.71 seconds
Started Jul 02 08:01:03 AM PDT 24
Finished Jul 02 08:01:29 AM PDT 24
Peak memory 200308 kb
Host smart-8f2a6916-a734-4812-90af-2464cc4ed4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206656068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.206656068
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4178308220
Short name T402
Test name
Test status
Simulation time 174443524 ps
CPU time 1.23 seconds
Started Jul 02 08:01:09 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 200124 kb
Host smart-49296251-d880-4019-a38a-3836e7d276b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178308220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4178308220
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3844454162
Short name T435
Test name
Test status
Simulation time 231741833 ps
CPU time 1.39 seconds
Started Jul 02 08:01:06 AM PDT 24
Finished Jul 02 08:01:26 AM PDT 24
Peak memory 200308 kb
Host smart-fc2ddb41-7a30-4929-8320-7bf7c17be182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844454162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3844454162
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.778943166
Short name T94
Test name
Test status
Simulation time 376066195 ps
CPU time 1.72 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:01:36 AM PDT 24
Peak memory 200332 kb
Host smart-7bc27622-4313-4571-8c0f-2d7643989e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778943166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.778943166
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.555161164
Short name T316
Test name
Test status
Simulation time 350703797 ps
CPU time 2.19 seconds
Started Jul 02 08:01:01 AM PDT 24
Finished Jul 02 08:01:22 AM PDT 24
Peak memory 200156 kb
Host smart-6c6c7dfc-0882-4777-bf48-a3f42930315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555161164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.555161164
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3738042523
Short name T173
Test name
Test status
Simulation time 163480517 ps
CPU time 1.19 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:35 AM PDT 24
Peak memory 200152 kb
Host smart-57df887e-3beb-4a70-bb17-803a7a936a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738042523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3738042523
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3532837347
Short name T294
Test name
Test status
Simulation time 67575453 ps
CPU time 0.74 seconds
Started Jul 02 08:01:11 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 199936 kb
Host smart-0d39dc86-5064-46fe-b401-5e03defdba04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532837347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3532837347
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.610707504
Short name T47
Test name
Test status
Simulation time 2162423333 ps
CPU time 7.55 seconds
Started Jul 02 08:01:12 AM PDT 24
Finished Jul 02 08:01:38 AM PDT 24
Peak memory 221456 kb
Host smart-3b82c52f-1b1b-4289-a91c-21c83387dd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610707504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.610707504
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2959526967
Short name T9
Test name
Test status
Simulation time 243774489 ps
CPU time 1.18 seconds
Started Jul 02 08:00:56 AM PDT 24
Finished Jul 02 08:01:17 AM PDT 24
Peak memory 217504 kb
Host smart-57fd126e-5567-4089-9381-a00263e14870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959526967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2959526967
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3369889100
Short name T247
Test name
Test status
Simulation time 133106298 ps
CPU time 0.8 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:33 AM PDT 24
Peak memory 199928 kb
Host smart-196ba1df-8ede-413e-9995-0c6ba588f4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369889100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3369889100
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1023412202
Short name T343
Test name
Test status
Simulation time 1725745761 ps
CPU time 6.62 seconds
Started Jul 02 08:01:16 AM PDT 24
Finished Jul 02 08:01:41 AM PDT 24
Peak memory 200384 kb
Host smart-5046111f-34a0-49db-a888-de25545bd6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023412202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1023412202
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3265630773
Short name T321
Test name
Test status
Simulation time 109984031 ps
CPU time 1.09 seconds
Started Jul 02 08:01:06 AM PDT 24
Finished Jul 02 08:01:26 AM PDT 24
Peak memory 200112 kb
Host smart-8656b934-55cf-4506-b80a-0339dbf9cd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265630773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3265630773
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.62643851
Short name T312
Test name
Test status
Simulation time 121117447 ps
CPU time 1.22 seconds
Started Jul 02 08:01:20 AM PDT 24
Finished Jul 02 08:01:41 AM PDT 24
Peak memory 200332 kb
Host smart-33297755-6b43-4646-8f7d-2925a511c75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62643851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.62643851
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.510618643
Short name T396
Test name
Test status
Simulation time 3991347443 ps
CPU time 15.7 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:54 AM PDT 24
Peak memory 208660 kb
Host smart-dd206753-2531-45d7-8a62-5e63eb828dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510618643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.510618643
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.461628609
Short name T154
Test name
Test status
Simulation time 335658112 ps
CPU time 1.99 seconds
Started Jul 02 08:00:58 AM PDT 24
Finished Jul 02 08:01:20 AM PDT 24
Peak memory 200128 kb
Host smart-1c8e94a6-c796-4ad6-a785-d15996f57762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461628609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.461628609
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2089971683
Short name T436
Test name
Test status
Simulation time 86745624 ps
CPU time 0.81 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:34 AM PDT 24
Peak memory 200136 kb
Host smart-2c3d5f12-528d-42f5-ae76-10bd69dc140a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089971683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2089971683
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.906930385
Short name T219
Test name
Test status
Simulation time 85189464 ps
CPU time 0.85 seconds
Started Jul 02 08:01:06 AM PDT 24
Finished Jul 02 08:01:26 AM PDT 24
Peak memory 199956 kb
Host smart-01400c9a-da9a-41e1-9b4d-af82229a6341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906930385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.906930385
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.218572078
Short name T461
Test name
Test status
Simulation time 1221132363 ps
CPU time 5.41 seconds
Started Jul 02 08:01:10 AM PDT 24
Finished Jul 02 08:01:35 AM PDT 24
Peak memory 217724 kb
Host smart-57a13250-42ca-4567-baa9-fc7c86326ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218572078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.218572078
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.436983147
Short name T347
Test name
Test status
Simulation time 247192751 ps
CPU time 1.02 seconds
Started Jul 02 08:00:57 AM PDT 24
Finished Jul 02 08:01:18 AM PDT 24
Peak memory 217556 kb
Host smart-b21d06fd-bdf7-45e7-9e95-1604995c3c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436983147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.436983147
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.658235721
Short name T295
Test name
Test status
Simulation time 135982338 ps
CPU time 0.8 seconds
Started Jul 02 08:01:06 AM PDT 24
Finished Jul 02 08:01:26 AM PDT 24
Peak memory 199940 kb
Host smart-8db26d7f-d63c-46e4-be35-c5950fe22970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658235721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.658235721
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3199981494
Short name T146
Test name
Test status
Simulation time 1941804872 ps
CPU time 7.18 seconds
Started Jul 02 08:01:04 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 200444 kb
Host smart-a420f0e0-9ffc-4e0e-ba5a-151da2408e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199981494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3199981494
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3302782113
Short name T244
Test name
Test status
Simulation time 140771931 ps
CPU time 1.08 seconds
Started Jul 02 08:01:13 AM PDT 24
Finished Jul 02 08:01:33 AM PDT 24
Peak memory 200148 kb
Host smart-81b9917a-e84e-4b1f-9703-0bee04edabce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302782113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3302782113
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1486903990
Short name T471
Test name
Test status
Simulation time 115486942 ps
CPU time 1.13 seconds
Started Jul 02 08:01:16 AM PDT 24
Finished Jul 02 08:01:36 AM PDT 24
Peak memory 200348 kb
Host smart-7afefe4d-38d5-45be-ba0d-84ee987b4c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486903990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1486903990
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2837025744
Short name T260
Test name
Test status
Simulation time 7234047796 ps
CPU time 24.81 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:58 AM PDT 24
Peak memory 208740 kb
Host smart-42d9c342-9f1d-40e4-9bc3-803572acc5a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837025744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2837025744
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1996759695
Short name T210
Test name
Test status
Simulation time 138813575 ps
CPU time 1.78 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:45 AM PDT 24
Peak memory 200376 kb
Host smart-3e210b01-c762-480a-8cff-473386416705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996759695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1996759695
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1091747695
Short name T252
Test name
Test status
Simulation time 215206756 ps
CPU time 1.34 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:01:36 AM PDT 24
Peak memory 200152 kb
Host smart-c6ce5226-34b4-4bba-be96-f5e50b9fe4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091747695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1091747695
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3795659849
Short name T182
Test name
Test status
Simulation time 69897781 ps
CPU time 0.82 seconds
Started Jul 02 08:01:01 AM PDT 24
Finished Jul 02 08:01:20 AM PDT 24
Peak memory 199948 kb
Host smart-09df6f5f-4afc-443f-874b-022384e765ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795659849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3795659849
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1606839674
Short name T375
Test name
Test status
Simulation time 2366172406 ps
CPU time 7.94 seconds
Started Jul 02 08:01:08 AM PDT 24
Finished Jul 02 08:01:35 AM PDT 24
Peak memory 217232 kb
Host smart-59e7d5e6-bc48-43d5-96bf-44be257e0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606839674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1606839674
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3000037728
Short name T178
Test name
Test status
Simulation time 244202211 ps
CPU time 1.02 seconds
Started Jul 02 08:01:16 AM PDT 24
Finished Jul 02 08:01:35 AM PDT 24
Peak memory 217524 kb
Host smart-98a9257c-7a1e-413d-98f3-6ad6a38cd6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000037728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3000037728
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.266237724
Short name T466
Test name
Test status
Simulation time 103523935 ps
CPU time 0.73 seconds
Started Jul 02 08:01:11 AM PDT 24
Finished Jul 02 08:01:31 AM PDT 24
Peak memory 199884 kb
Host smart-702fc681-13b3-4107-8dd1-b71ab386f92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266237724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.266237724
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2257981719
Short name T5
Test name
Test status
Simulation time 1308588493 ps
CPU time 5.31 seconds
Started Jul 02 08:01:10 AM PDT 24
Finished Jul 02 08:01:35 AM PDT 24
Peak memory 200384 kb
Host smart-fb6284f6-eb24-4543-b1d5-bc5c8ffd0b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257981719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2257981719
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.693881828
Short name T206
Test name
Test status
Simulation time 175856047 ps
CPU time 1.15 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:37 AM PDT 24
Peak memory 200140 kb
Host smart-f99908cf-0bd8-41b8-b086-17c1984ad45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693881828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.693881828
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1496385986
Short name T531
Test name
Test status
Simulation time 117734807 ps
CPU time 1.19 seconds
Started Jul 02 08:01:04 AM PDT 24
Finished Jul 02 08:01:24 AM PDT 24
Peak memory 200312 kb
Host smart-a069529b-b3ab-41c8-a206-3f286be4dfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496385986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1496385986
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1332423101
Short name T333
Test name
Test status
Simulation time 1096201404 ps
CPU time 5.71 seconds
Started Jul 02 08:01:07 AM PDT 24
Finished Jul 02 08:01:32 AM PDT 24
Peak memory 200376 kb
Host smart-1200b15a-bed1-43ee-8804-0e918c023de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332423101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1332423101
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3819266015
Short name T204
Test name
Test status
Simulation time 131707129 ps
CPU time 1.58 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:38 AM PDT 24
Peak memory 208304 kb
Host smart-75a86635-0f56-41d0-ac4a-b83b09a61b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819266015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3819266015
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3105109520
Short name T224
Test name
Test status
Simulation time 172648375 ps
CPU time 1.3 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:37 AM PDT 24
Peak memory 200344 kb
Host smart-0a85cdd3-034f-4bcf-bc69-deafe48df66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105109520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3105109520
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.647974877
Short name T369
Test name
Test status
Simulation time 75746299 ps
CPU time 0.79 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 199952 kb
Host smart-fc87c763-34a5-4dcf-a494-c0b749ca5a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647974877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.647974877
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2552593079
Short name T41
Test name
Test status
Simulation time 2339841415 ps
CPU time 8.5 seconds
Started Jul 02 08:00:40 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 217940 kb
Host smart-3b992687-fbc4-4bb0-b5e1-189bb991cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552593079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2552593079
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.43988359
Short name T534
Test name
Test status
Simulation time 243364641 ps
CPU time 1.08 seconds
Started Jul 02 08:00:22 AM PDT 24
Finished Jul 02 08:00:38 AM PDT 24
Peak memory 217472 kb
Host smart-9f634809-2578-44e1-8ca0-c13bddd3e24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43988359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.43988359
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2985232188
Short name T438
Test name
Test status
Simulation time 172083477 ps
CPU time 0.82 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 199952 kb
Host smart-084ce49f-c2e4-43f8-8d37-8c712ecfaabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985232188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2985232188
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.4023975782
Short name T397
Test name
Test status
Simulation time 699459924 ps
CPU time 3.67 seconds
Started Jul 02 08:00:33 AM PDT 24
Finished Jul 02 08:00:53 AM PDT 24
Peak memory 200308 kb
Host smart-b7f19b6d-38ce-4d7a-b2f6-6149d6bea857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023975782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4023975782
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.837394609
Short name T78
Test name
Test status
Simulation time 8298516940 ps
CPU time 15.59 seconds
Started Jul 02 08:00:27 AM PDT 24
Finished Jul 02 08:00:59 AM PDT 24
Peak memory 217672 kb
Host smart-7bce199a-8664-42a9-a259-fbf48da7fe53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837394609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.837394609
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1609203886
Short name T303
Test name
Test status
Simulation time 93706145 ps
CPU time 0.99 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:00:45 AM PDT 24
Peak memory 200280 kb
Host smart-6ac814f3-cacb-40e8-b479-8780b59e821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609203886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1609203886
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1798769781
Short name T319
Test name
Test status
Simulation time 121406733 ps
CPU time 1.16 seconds
Started Jul 02 08:00:17 AM PDT 24
Finished Jul 02 08:00:32 AM PDT 24
Peak memory 200244 kb
Host smart-f54c48d9-79c9-4729-af4b-bcc6761f05d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798769781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1798769781
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2251902285
Short name T421
Test name
Test status
Simulation time 7236671024 ps
CPU time 25.63 seconds
Started Jul 02 08:00:27 AM PDT 24
Finished Jul 02 08:01:09 AM PDT 24
Peak memory 200276 kb
Host smart-00eca656-9742-4a8e-a85b-e94eb666021a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251902285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2251902285
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1011775254
Short name T152
Test name
Test status
Simulation time 373040655 ps
CPU time 2.14 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 208272 kb
Host smart-9506847d-8dd4-44bd-97c0-8971e708b715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011775254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1011775254
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3400113001
Short name T195
Test name
Test status
Simulation time 88286058 ps
CPU time 0.89 seconds
Started Jul 02 08:00:21 AM PDT 24
Finished Jul 02 08:00:37 AM PDT 24
Peak memory 200056 kb
Host smart-406c60ee-c65b-4e76-9313-931fe0d3ca75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400113001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3400113001
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2165927901
Short name T234
Test name
Test status
Simulation time 71822915 ps
CPU time 0.83 seconds
Started Jul 02 08:01:01 AM PDT 24
Finished Jul 02 08:01:21 AM PDT 24
Peak memory 199916 kb
Host smart-5319b473-d7ef-45a3-b889-afd1641d442a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165927901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2165927901
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.645585576
Short name T43
Test name
Test status
Simulation time 2367637777 ps
CPU time 8.31 seconds
Started Jul 02 08:01:13 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 217812 kb
Host smart-80161200-90c8-4ea7-82ec-d01744cdac80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645585576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.645585576
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1173281077
Short name T284
Test name
Test status
Simulation time 244695766 ps
CPU time 1.09 seconds
Started Jul 02 08:01:11 AM PDT 24
Finished Jul 02 08:01:31 AM PDT 24
Peak memory 217524 kb
Host smart-b91606c3-d836-44aa-ba59-26dae7ad0c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173281077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1173281077
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1456333678
Short name T24
Test name
Test status
Simulation time 111415460 ps
CPU time 0.81 seconds
Started Jul 02 08:01:12 AM PDT 24
Finished Jul 02 08:01:31 AM PDT 24
Peak memory 199960 kb
Host smart-4caf94bc-bf7b-4556-bd97-75d4ea7da801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456333678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1456333678
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1030225157
Short name T114
Test name
Test status
Simulation time 1775467122 ps
CPU time 7.24 seconds
Started Jul 02 08:01:22 AM PDT 24
Finished Jul 02 08:01:49 AM PDT 24
Peak memory 200300 kb
Host smart-bda78147-cd59-43cd-bb0c-33e2b033afac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030225157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1030225157
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2303342439
Short name T209
Test name
Test status
Simulation time 111034962 ps
CPU time 1.01 seconds
Started Jul 02 08:01:08 AM PDT 24
Finished Jul 02 08:01:29 AM PDT 24
Peak memory 200140 kb
Host smart-83e2ccf7-aa3a-4609-9a13-4e64e26f7f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303342439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2303342439
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.59327226
Short name T194
Test name
Test status
Simulation time 207576642 ps
CPU time 1.34 seconds
Started Jul 02 08:01:04 AM PDT 24
Finished Jul 02 08:01:24 AM PDT 24
Peak memory 200328 kb
Host smart-a585c066-34a4-44d7-a91b-074633c72e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59327226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.59327226
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.915332887
Short name T179
Test name
Test status
Simulation time 4196818050 ps
CPU time 15.47 seconds
Started Jul 02 08:01:09 AM PDT 24
Finished Jul 02 08:01:44 AM PDT 24
Peak memory 200460 kb
Host smart-7778074d-f541-4ea1-abe6-30195f8f89a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915332887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.915332887
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3283779794
Short name T336
Test name
Test status
Simulation time 488499490 ps
CPU time 2.55 seconds
Started Jul 02 08:01:08 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 200120 kb
Host smart-70842214-803e-4387-a711-e810c0965945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283779794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3283779794
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2594924351
Short name T393
Test name
Test status
Simulation time 191907155 ps
CPU time 1.26 seconds
Started Jul 02 08:01:07 AM PDT 24
Finished Jul 02 08:01:28 AM PDT 24
Peak memory 200132 kb
Host smart-d79e445a-cb4a-4e5b-ad55-aa7e0d5e8a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594924351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2594924351
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2043159442
Short name T342
Test name
Test status
Simulation time 80404620 ps
CPU time 0.81 seconds
Started Jul 02 08:01:03 AM PDT 24
Finished Jul 02 08:01:24 AM PDT 24
Peak memory 199924 kb
Host smart-9ebbe95d-fa28-489d-9458-2fa9ef4ba7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043159442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2043159442
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.348660755
Short name T42
Test name
Test status
Simulation time 1220585011 ps
CPU time 5.33 seconds
Started Jul 02 08:01:12 AM PDT 24
Finished Jul 02 08:01:36 AM PDT 24
Peak memory 217512 kb
Host smart-c390360d-5e3b-49d3-b486-0d52d9697423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348660755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.348660755
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1676892159
Short name T498
Test name
Test status
Simulation time 243862335 ps
CPU time 1.09 seconds
Started Jul 02 08:01:20 AM PDT 24
Finished Jul 02 08:01:41 AM PDT 24
Peak memory 217476 kb
Host smart-abb4520c-273e-40ed-ad77-8ab79e097a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676892159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1676892159
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.18948162
Short name T274
Test name
Test status
Simulation time 188074462 ps
CPU time 0.86 seconds
Started Jul 02 08:01:10 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 199896 kb
Host smart-8db72b09-dc10-44e4-bc5d-dd41b828d2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18948162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.18948162
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2475028704
Short name T15
Test name
Test status
Simulation time 969665662 ps
CPU time 4.52 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:01:44 AM PDT 24
Peak memory 200416 kb
Host smart-fcd0741f-3556-4eda-9a7e-d7f48b2ede64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475028704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2475028704
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1149012155
Short name T420
Test name
Test status
Simulation time 173115260 ps
CPU time 1.2 seconds
Started Jul 02 08:01:20 AM PDT 24
Finished Jul 02 08:01:41 AM PDT 24
Peak memory 200164 kb
Host smart-804162d0-e7de-45b4-99bf-6d688790032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149012155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1149012155
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2057593554
Short name T99
Test name
Test status
Simulation time 115366609 ps
CPU time 1.16 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 200392 kb
Host smart-0423e30c-d757-4c72-a8ed-82e126d073b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057593554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2057593554
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2461455367
Short name T448
Test name
Test status
Simulation time 8783930850 ps
CPU time 31.64 seconds
Started Jul 02 08:01:12 AM PDT 24
Finished Jul 02 08:02:03 AM PDT 24
Peak memory 200456 kb
Host smart-e3052752-6558-4e45-864c-0fc4acbe3967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461455367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2461455367
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2257537734
Short name T318
Test name
Test status
Simulation time 461251146 ps
CPU time 2.48 seconds
Started Jul 02 08:01:05 AM PDT 24
Finished Jul 02 08:01:27 AM PDT 24
Peak memory 200204 kb
Host smart-cc300a94-04cd-4967-b123-41efc224653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257537734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2257537734
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2188866700
Short name T16
Test name
Test status
Simulation time 89526320 ps
CPU time 0.86 seconds
Started Jul 02 08:01:12 AM PDT 24
Finished Jul 02 08:01:31 AM PDT 24
Peak memory 200120 kb
Host smart-42157b14-e670-4152-a59b-7e26ed749c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188866700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2188866700
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3060664316
Short name T395
Test name
Test status
Simulation time 83118348 ps
CPU time 0.79 seconds
Started Jul 02 08:01:11 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 199924 kb
Host smart-e6f7c9f1-9ea6-4db0-9d33-265f5f78ca64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060664316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3060664316
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2974266737
Short name T350
Test name
Test status
Simulation time 1211169746 ps
CPU time 6.14 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:38 AM PDT 24
Peak memory 217648 kb
Host smart-69fdc4bb-ec9f-43f8-8b32-d237a58fba4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974266737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2974266737
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2739954198
Short name T242
Test name
Test status
Simulation time 245279915 ps
CPU time 1.05 seconds
Started Jul 02 08:01:31 AM PDT 24
Finished Jul 02 08:01:51 AM PDT 24
Peak memory 217516 kb
Host smart-ef5e2935-4d7c-4ada-b6a8-a99a71de4fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739954198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2739954198
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3397570830
Short name T326
Test name
Test status
Simulation time 96323845 ps
CPU time 0.79 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:37 AM PDT 24
Peak memory 199972 kb
Host smart-d10db7a9-6873-4f0c-aac4-5d53199f255f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397570830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3397570830
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.289687353
Short name T223
Test name
Test status
Simulation time 1004196699 ps
CPU time 4.55 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:37 AM PDT 24
Peak memory 200428 kb
Host smart-b0849769-c9cd-44cd-98fc-f43f2db2cd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289687353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.289687353
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.813130037
Short name T522
Test name
Test status
Simulation time 95065901 ps
CPU time 0.97 seconds
Started Jul 02 08:01:20 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 200152 kb
Host smart-8f010d33-e4ef-40bf-a3fe-4dd1c9aa6db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813130037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.813130037
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2638671656
Short name T322
Test name
Test status
Simulation time 119205316 ps
CPU time 1.16 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:39 AM PDT 24
Peak memory 200308 kb
Host smart-244e0599-1e2e-489c-90ee-5acf6d8e158e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638671656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2638671656
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1164813441
Short name T292
Test name
Test status
Simulation time 4576063924 ps
CPU time 16.03 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:53 AM PDT 24
Peak memory 208632 kb
Host smart-122eb0d3-b4ff-47c0-b4c2-e785ad08c972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164813441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1164813441
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.518876503
Short name T272
Test name
Test status
Simulation time 305702103 ps
CPU time 1.86 seconds
Started Jul 02 08:01:00 AM PDT 24
Finished Jul 02 08:01:21 AM PDT 24
Peak memory 208240 kb
Host smart-20f9e453-fef1-4737-9cd3-10da6c8b8e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518876503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.518876503
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.146422925
Short name T257
Test name
Test status
Simulation time 137480836 ps
CPU time 0.99 seconds
Started Jul 02 08:01:13 AM PDT 24
Finished Jul 02 08:01:33 AM PDT 24
Peak memory 200088 kb
Host smart-72d7d2f1-3e72-4a96-9b9e-b8941ee513d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146422925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.146422925
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.626887126
Short name T314
Test name
Test status
Simulation time 73077206 ps
CPU time 0.78 seconds
Started Jul 02 08:01:21 AM PDT 24
Finished Jul 02 08:01:42 AM PDT 24
Peak memory 199876 kb
Host smart-1b427a4c-3090-4fe8-86ad-d161b6c5b58a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626887126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.626887126
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3310953118
Short name T493
Test name
Test status
Simulation time 1220169559 ps
CPU time 5.4 seconds
Started Jul 02 08:01:25 AM PDT 24
Finished Jul 02 08:01:50 AM PDT 24
Peak memory 217760 kb
Host smart-c2078cc5-65d4-4b11-b885-0a0255920770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310953118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3310953118
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2924811795
Short name T412
Test name
Test status
Simulation time 245039402 ps
CPU time 1.02 seconds
Started Jul 02 08:01:16 AM PDT 24
Finished Jul 02 08:01:36 AM PDT 24
Peak memory 217476 kb
Host smart-700a968a-aeb0-429f-804d-a0434526624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924811795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2924811795
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1338571689
Short name T91
Test name
Test status
Simulation time 178705964 ps
CPU time 0.91 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:01:35 AM PDT 24
Peak memory 199888 kb
Host smart-3b3b6b1b-e3a1-4227-8740-cb4a8a50780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338571689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1338571689
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3454603368
Short name T524
Test name
Test status
Simulation time 792320791 ps
CPU time 4.02 seconds
Started Jul 02 08:01:06 AM PDT 24
Finished Jul 02 08:01:29 AM PDT 24
Peak memory 200448 kb
Host smart-a95c7330-f58c-4a1a-bb2b-9fb83417a439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454603368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3454603368
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1692753028
Short name T255
Test name
Test status
Simulation time 96831531 ps
CPU time 0.99 seconds
Started Jul 02 08:01:12 AM PDT 24
Finished Jul 02 08:01:33 AM PDT 24
Peak memory 200164 kb
Host smart-d698f664-cbaf-44c7-9d7f-d74ba1d95a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692753028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1692753028
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.175645980
Short name T276
Test name
Test status
Simulation time 214528569 ps
CPU time 1.51 seconds
Started Jul 02 08:01:16 AM PDT 24
Finished Jul 02 08:01:36 AM PDT 24
Peak memory 200360 kb
Host smart-81e2f825-6ad5-4a8f-9195-218cee0e09ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175645980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.175645980
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.227997057
Short name T145
Test name
Test status
Simulation time 3947898073 ps
CPU time 13.23 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:49 AM PDT 24
Peak memory 216832 kb
Host smart-d05a7ceb-16ff-420d-ab0a-9321f933c7f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227997057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.227997057
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3022455718
Short name T180
Test name
Test status
Simulation time 146743429 ps
CPU time 1.76 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:01:36 AM PDT 24
Peak memory 200132 kb
Host smart-f637ee49-3377-4f00-bf6d-68c789db88ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022455718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3022455718
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3909955707
Short name T338
Test name
Test status
Simulation time 115781357 ps
CPU time 0.99 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:34 AM PDT 24
Peak memory 200152 kb
Host smart-e4a4947e-baae-4241-b0dd-b5dfb299771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909955707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3909955707
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1323816562
Short name T411
Test name
Test status
Simulation time 61534332 ps
CPU time 0.74 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:39 AM PDT 24
Peak memory 199900 kb
Host smart-39073f83-607f-4c90-a741-0749f0e2c964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323816562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1323816562
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3719127985
Short name T426
Test name
Test status
Simulation time 1234991382 ps
CPU time 5.42 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:38 AM PDT 24
Peak memory 217760 kb
Host smart-8f9e5df2-1564-4797-b9b7-7e2666484c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719127985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3719127985
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.4038420769
Short name T332
Test name
Test status
Simulation time 243858224 ps
CPU time 1.16 seconds
Started Jul 02 08:01:04 AM PDT 24
Finished Jul 02 08:01:24 AM PDT 24
Peak memory 217484 kb
Host smart-e1cd4ee3-41d9-4746-8290-e6b3fdede67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038420769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.4038420769
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3508915038
Short name T428
Test name
Test status
Simulation time 183786800 ps
CPU time 0.88 seconds
Started Jul 02 08:01:03 AM PDT 24
Finished Jul 02 08:01:24 AM PDT 24
Peak memory 199892 kb
Host smart-80155af8-e0af-4938-a0ff-42a9f5160bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508915038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3508915038
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.64327731
Short name T391
Test name
Test status
Simulation time 1254707065 ps
CPU time 5.4 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:38 AM PDT 24
Peak memory 200472 kb
Host smart-e024ff4a-ec72-4442-bdb2-50592083ba58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64327731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.64327731
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3955567188
Short name T269
Test name
Test status
Simulation time 166746461 ps
CPU time 1.2 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:39 AM PDT 24
Peak memory 200164 kb
Host smart-2ee61f7d-3186-4d12-a14f-542b7a13cb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955567188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3955567188
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1305281462
Short name T86
Test name
Test status
Simulation time 244693779 ps
CPU time 1.42 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:37 AM PDT 24
Peak memory 200304 kb
Host smart-b01db958-c2d8-4795-8b6e-b31095674f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305281462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1305281462
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1834775347
Short name T481
Test name
Test status
Simulation time 15849331416 ps
CPU time 52.07 seconds
Started Jul 02 08:01:11 AM PDT 24
Finished Jul 02 08:02:23 AM PDT 24
Peak memory 216708 kb
Host smart-984bfcb9-6e82-4c8b-be91-daab5b32c3e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834775347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1834775347
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1324383647
Short name T233
Test name
Test status
Simulation time 403033046 ps
CPU time 2.32 seconds
Started Jul 02 08:01:14 AM PDT 24
Finished Jul 02 08:01:35 AM PDT 24
Peak memory 200196 kb
Host smart-2731b2bd-bad4-4d9a-b079-bc3d552a92f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324383647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1324383647
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2961042149
Short name T83
Test name
Test status
Simulation time 175607494 ps
CPU time 1.13 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:38 AM PDT 24
Peak memory 200120 kb
Host smart-43893366-8987-4861-96d4-e6078a57adb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961042149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2961042149
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3192378572
Short name T540
Test name
Test status
Simulation time 63489254 ps
CPU time 0.73 seconds
Started Jul 02 08:01:27 AM PDT 24
Finished Jul 02 08:01:46 AM PDT 24
Peak memory 199952 kb
Host smart-a8ad489b-6590-45fe-b98c-36d7c0e00201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192378572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3192378572
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.343869147
Short name T155
Test name
Test status
Simulation time 1879759215 ps
CPU time 6.73 seconds
Started Jul 02 08:01:12 AM PDT 24
Finished Jul 02 08:01:37 AM PDT 24
Peak memory 217784 kb
Host smart-fc414ec2-bdc6-417d-a720-38970a71ae55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343869147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.343869147
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.555021108
Short name T222
Test name
Test status
Simulation time 243994280 ps
CPU time 1.06 seconds
Started Jul 02 08:01:10 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 217508 kb
Host smart-ab3c8334-728a-446f-b084-c1cd1b22355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555021108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.555021108
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2570917534
Short name T364
Test name
Test status
Simulation time 91494517 ps
CPU time 0.79 seconds
Started Jul 02 08:01:10 AM PDT 24
Finished Jul 02 08:01:30 AM PDT 24
Peak memory 199924 kb
Host smart-644a6a40-9715-4750-89ee-572d26f7f699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570917534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2570917534
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.668064022
Short name T111
Test name
Test status
Simulation time 730504444 ps
CPU time 3.78 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:41 AM PDT 24
Peak memory 200432 kb
Host smart-86898401-8f26-4a43-8134-feeb7cbfa12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668064022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.668064022
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.505528625
Short name T183
Test name
Test status
Simulation time 174830155 ps
CPU time 1.13 seconds
Started Jul 02 08:01:02 AM PDT 24
Finished Jul 02 08:01:22 AM PDT 24
Peak memory 200076 kb
Host smart-ca7219fa-1bbc-4beb-8c3d-d5b6673104e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505528625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.505528625
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.720592337
Short name T199
Test name
Test status
Simulation time 109034424 ps
CPU time 1.15 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:39 AM PDT 24
Peak memory 200412 kb
Host smart-d5ef2be8-1570-4f6f-a450-00a3490dd7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720592337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.720592337
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.323128834
Short name T424
Test name
Test status
Simulation time 11275744785 ps
CPU time 35.62 seconds
Started Jul 02 08:01:21 AM PDT 24
Finished Jul 02 08:02:17 AM PDT 24
Peak memory 208640 kb
Host smart-6048820b-1302-479e-89d4-78240cd6d9f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323128834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.323128834
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.73132253
Short name T293
Test name
Test status
Simulation time 130485777 ps
CPU time 1.7 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:01:35 AM PDT 24
Peak memory 200156 kb
Host smart-a81d311e-5034-4fd4-88b3-09744b079424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73132253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.73132253
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1904536674
Short name T90
Test name
Test status
Simulation time 150122570 ps
CPU time 1.08 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:39 AM PDT 24
Peak memory 200120 kb
Host smart-da7a79dd-f65c-4288-b93f-00c05d5ff54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904536674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1904536674
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3412920486
Short name T168
Test name
Test status
Simulation time 86495167 ps
CPU time 0.85 seconds
Started Jul 02 08:01:34 AM PDT 24
Finished Jul 02 08:01:52 AM PDT 24
Peak memory 200164 kb
Host smart-b56969a4-80d6-49c5-9623-67aafa2a38da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412920486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3412920486
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2904362602
Short name T88
Test name
Test status
Simulation time 1218880029 ps
CPU time 5.52 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:01:39 AM PDT 24
Peak memory 216812 kb
Host smart-1ce98959-5c51-426f-a61c-5796172122fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904362602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2904362602
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3909053480
Short name T503
Test name
Test status
Simulation time 244747166 ps
CPU time 1.09 seconds
Started Jul 02 08:01:28 AM PDT 24
Finished Jul 02 08:01:48 AM PDT 24
Peak memory 217480 kb
Host smart-10de55ee-64ab-45a7-ba09-e2da6d4a24a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909053480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3909053480
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2670462496
Short name T462
Test name
Test status
Simulation time 117874053 ps
CPU time 0.77 seconds
Started Jul 02 08:01:20 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 199976 kb
Host smart-cbd942d7-f01f-40bc-a059-edcebf618f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670462496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2670462496
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2574531425
Short name T270
Test name
Test status
Simulation time 750246511 ps
CPU time 3.56 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:42 AM PDT 24
Peak memory 200384 kb
Host smart-41975a14-5b0c-419c-bb1d-1664a6cbbc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574531425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2574531425
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2917115527
Short name T390
Test name
Test status
Simulation time 142749225 ps
CPU time 1.17 seconds
Started Jul 02 08:01:23 AM PDT 24
Finished Jul 02 08:01:44 AM PDT 24
Peak memory 200140 kb
Host smart-2f934e93-f545-4716-b52d-a931faaf65b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917115527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2917115527
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.297310524
Short name T153
Test name
Test status
Simulation time 224356342 ps
CPU time 1.45 seconds
Started Jul 02 08:01:27 AM PDT 24
Finished Jul 02 08:01:47 AM PDT 24
Peak memory 200360 kb
Host smart-cbbf4abd-cb91-452f-b613-1cf235449e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297310524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.297310524
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3445964367
Short name T214
Test name
Test status
Simulation time 875129679 ps
CPU time 3.8 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:42 AM PDT 24
Peak memory 200364 kb
Host smart-a4ebac3c-cc04-4049-90d7-7c7283c56131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445964367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3445964367
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1814509764
Short name T101
Test name
Test status
Simulation time 271949766 ps
CPU time 1.76 seconds
Started Jul 02 08:01:20 AM PDT 24
Finished Jul 02 08:01:41 AM PDT 24
Peak memory 200156 kb
Host smart-107e941f-eb54-4c47-9041-583e990066de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814509764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1814509764
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3191848976
Short name T96
Test name
Test status
Simulation time 73205000 ps
CPU time 0.79 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:38 AM PDT 24
Peak memory 200336 kb
Host smart-a5b60575-ef1b-48b0-bb47-e9c9eb2b295c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191848976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3191848976
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.992717868
Short name T499
Test name
Test status
Simulation time 58402175 ps
CPU time 0.71 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:37 AM PDT 24
Peak memory 199888 kb
Host smart-82aa399e-c9bf-4e8c-aab6-fec10a178aab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992717868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.992717868
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1476195215
Short name T404
Test name
Test status
Simulation time 2368716535 ps
CPU time 8.44 seconds
Started Jul 02 08:01:22 AM PDT 24
Finished Jul 02 08:01:50 AM PDT 24
Peak memory 221792 kb
Host smart-ee30d057-efca-4065-93ed-deed7a2e00ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476195215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1476195215
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1809953543
Short name T378
Test name
Test status
Simulation time 244917695 ps
CPU time 1.02 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:37 AM PDT 24
Peak memory 217576 kb
Host smart-40e405c3-1a14-4a82-89e5-89d56115448d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809953543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1809953543
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1338480204
Short name T280
Test name
Test status
Simulation time 102692621 ps
CPU time 0.75 seconds
Started Jul 02 08:01:28 AM PDT 24
Finished Jul 02 08:01:47 AM PDT 24
Peak memory 199888 kb
Host smart-aef275de-0635-4744-939d-6cc12f9f711a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338480204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1338480204
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2969055649
Short name T265
Test name
Test status
Simulation time 1455535593 ps
CPU time 5.36 seconds
Started Jul 02 08:01:16 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 200420 kb
Host smart-85c273b4-8ee9-4264-9afb-d10a2d2ea094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969055649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2969055649
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1934468807
Short name T93
Test name
Test status
Simulation time 109041571 ps
CPU time 1.02 seconds
Started Jul 02 08:01:24 AM PDT 24
Finished Jul 02 08:01:44 AM PDT 24
Peak memory 200112 kb
Host smart-8ce9ee2f-a5ab-4873-a58e-fc13351e14dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934468807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1934468807
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.343032928
Short name T98
Test name
Test status
Simulation time 266537271 ps
CPU time 1.44 seconds
Started Jul 02 08:01:20 AM PDT 24
Finished Jul 02 08:01:41 AM PDT 24
Peak memory 200324 kb
Host smart-2b26b3df-fd82-4a33-bbd5-d0d9262d3321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343032928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.343032928
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2624866651
Short name T67
Test name
Test status
Simulation time 291283890 ps
CPU time 1.85 seconds
Started Jul 02 08:01:28 AM PDT 24
Finished Jul 02 08:01:49 AM PDT 24
Peak memory 200128 kb
Host smart-eac7a2d3-1216-4ed2-963c-8392ed20766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624866651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2624866651
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2640606007
Short name T197
Test name
Test status
Simulation time 65902309 ps
CPU time 0.79 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:01:54 AM PDT 24
Peak memory 200144 kb
Host smart-16c26537-6b55-457a-95d7-0643d818bfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640606007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2640606007
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2366516317
Short name T386
Test name
Test status
Simulation time 62956806 ps
CPU time 0.79 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 199944 kb
Host smart-264207d1-78f8-47e2-9439-ac5b3e3f064b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366516317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2366516317
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.126773390
Short name T384
Test name
Test status
Simulation time 1904011747 ps
CPU time 6.93 seconds
Started Jul 02 08:01:21 AM PDT 24
Finished Jul 02 08:01:49 AM PDT 24
Peak memory 217808 kb
Host smart-cec64d54-53bb-4302-bf63-325d30d7e315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126773390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.126773390
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3175811265
Short name T447
Test name
Test status
Simulation time 244705016 ps
CPU time 1.14 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:39 AM PDT 24
Peak memory 217544 kb
Host smart-8d0621ce-7933-48ea-a462-52aba13039e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175811265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3175811265
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1471253426
Short name T451
Test name
Test status
Simulation time 102488886 ps
CPU time 0.79 seconds
Started Jul 02 08:01:23 AM PDT 24
Finished Jul 02 08:01:44 AM PDT 24
Peak memory 199972 kb
Host smart-d95171c1-0cfd-4f15-8eef-7a8378afcfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471253426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1471253426
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2969063192
Short name T389
Test name
Test status
Simulation time 1045749786 ps
CPU time 5.08 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:43 AM PDT 24
Peak memory 200316 kb
Host smart-1f95b3b9-9399-4754-ae6d-add635829209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969063192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2969063192
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2702125179
Short name T231
Test name
Test status
Simulation time 154486962 ps
CPU time 1.19 seconds
Started Jul 02 08:01:16 AM PDT 24
Finished Jul 02 08:01:36 AM PDT 24
Peak memory 200164 kb
Host smart-59489baf-9e93-46cd-8370-047d5dce6ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702125179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2702125179
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.4085444697
Short name T217
Test name
Test status
Simulation time 109955960 ps
CPU time 1.21 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:01:35 AM PDT 24
Peak memory 200328 kb
Host smart-8381bb7f-b061-4466-88c5-1feee77939c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085444697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.4085444697
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1258492475
Short name T287
Test name
Test status
Simulation time 7058081147 ps
CPU time 32.89 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:02:09 AM PDT 24
Peak memory 208652 kb
Host smart-4f6a988e-6d35-4402-807b-d02a94d05a42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258492475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1258492475
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2728639364
Short name T450
Test name
Test status
Simulation time 304825466 ps
CPU time 1.99 seconds
Started Jul 02 08:01:28 AM PDT 24
Finished Jul 02 08:01:49 AM PDT 24
Peak memory 208540 kb
Host smart-3cb55446-e7bc-4218-a8e2-4f5ac41842f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728639364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2728639364
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.898361271
Short name T300
Test name
Test status
Simulation time 159314987 ps
CPU time 1.15 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:39 AM PDT 24
Peak memory 200368 kb
Host smart-bde84089-df48-418c-a470-dfef2cd5ca8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898361271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.898361271
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.852934318
Short name T64
Test name
Test status
Simulation time 71620357 ps
CPU time 0.83 seconds
Started Jul 02 08:01:21 AM PDT 24
Finished Jul 02 08:01:42 AM PDT 24
Peak memory 199916 kb
Host smart-57f576e5-8a99-4070-8b6f-d8c96aa96609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852934318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.852934318
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1347234031
Short name T55
Test name
Test status
Simulation time 2182470519 ps
CPU time 7.9 seconds
Started Jul 02 08:01:22 AM PDT 24
Finished Jul 02 08:01:50 AM PDT 24
Peak memory 217608 kb
Host smart-5e519aeb-9838-4a7d-9801-f371d34b4a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347234031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1347234031
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3442759574
Short name T163
Test name
Test status
Simulation time 244653564 ps
CPU time 1.03 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:38 AM PDT 24
Peak memory 217524 kb
Host smart-e5d94604-617d-4eb9-9064-bb7d1b3b777f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442759574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3442759574
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2125730337
Short name T301
Test name
Test status
Simulation time 132525241 ps
CPU time 0.81 seconds
Started Jul 02 08:01:30 AM PDT 24
Finished Jul 02 08:01:49 AM PDT 24
Peak memory 200172 kb
Host smart-26477b79-b6d0-4d89-8434-b1d874aa54f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125730337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2125730337
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.54686187
Short name T147
Test name
Test status
Simulation time 1909413065 ps
CPU time 6.67 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:00 AM PDT 24
Peak memory 200444 kb
Host smart-c5a1c88c-22ba-4736-932a-7a0ffc14fcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54686187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.54686187
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.177125582
Short name T340
Test name
Test status
Simulation time 101873221 ps
CPU time 0.98 seconds
Started Jul 02 08:01:26 AM PDT 24
Finished Jul 02 08:01:47 AM PDT 24
Peak memory 200172 kb
Host smart-0562b4f7-4f5d-492f-8c35-157aca21fd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177125582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.177125582
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.225517030
Short name T394
Test name
Test status
Simulation time 119355525 ps
CPU time 1.13 seconds
Started Jul 02 08:01:26 AM PDT 24
Finished Jul 02 08:01:47 AM PDT 24
Peak memory 200344 kb
Host smart-22c2a836-b9f5-4638-a53e-10b633beee3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225517030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.225517030
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.862128978
Short name T261
Test name
Test status
Simulation time 6447379341 ps
CPU time 28.35 seconds
Started Jul 02 08:01:21 AM PDT 24
Finished Jul 02 08:02:10 AM PDT 24
Peak memory 200484 kb
Host smart-658fe3e5-36ab-4ec0-9b06-7a19cb6b63b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862128978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.862128978
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3174864764
Short name T431
Test name
Test status
Simulation time 133526384 ps
CPU time 1.67 seconds
Started Jul 02 08:01:36 AM PDT 24
Finished Jul 02 08:01:56 AM PDT 24
Peak memory 208272 kb
Host smart-a7ab5b82-70d4-4ab6-900b-8c9b2832e71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174864764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3174864764
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2338747299
Short name T162
Test name
Test status
Simulation time 186365321 ps
CPU time 1.34 seconds
Started Jul 02 08:01:28 AM PDT 24
Finished Jul 02 08:01:48 AM PDT 24
Peak memory 200388 kb
Host smart-bcdd2016-47ca-4dc2-bb29-bbd45892cc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338747299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2338747299
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.148365184
Short name T440
Test name
Test status
Simulation time 79864935 ps
CPU time 0.74 seconds
Started Jul 02 08:00:21 AM PDT 24
Finished Jul 02 08:00:36 AM PDT 24
Peak memory 199900 kb
Host smart-82ef7326-4b18-42e7-abc4-f78863d865d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148365184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.148365184
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3236838358
Short name T40
Test name
Test status
Simulation time 2180557826 ps
CPU time 7.97 seconds
Started Jul 02 08:00:17 AM PDT 24
Finished Jul 02 08:00:37 AM PDT 24
Peak memory 221656 kb
Host smart-0a042c2b-f2eb-42d9-adad-14800ee0aae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236838358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3236838358
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2205995101
Short name T443
Test name
Test status
Simulation time 244528811 ps
CPU time 1.07 seconds
Started Jul 02 08:00:27 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 217324 kb
Host smart-360e2ca6-3b41-45d7-bb8c-1c62721fccd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205995101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2205995101
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2353052097
Short name T335
Test name
Test status
Simulation time 144618460 ps
CPU time 0.84 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 199716 kb
Host smart-6013c5a5-6aaf-4e5a-9fd9-c1e92d10b37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353052097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2353052097
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.777064640
Short name T473
Test name
Test status
Simulation time 866588232 ps
CPU time 4.02 seconds
Started Jul 02 08:00:18 AM PDT 24
Finished Jul 02 08:00:35 AM PDT 24
Peak memory 200400 kb
Host smart-89ad9720-7bc5-4bd4-97ff-7b8a11a6222a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777064640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.777064640
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3385579606
Short name T530
Test name
Test status
Simulation time 170445155 ps
CPU time 1.14 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 199996 kb
Host smart-106c8ea9-da1d-4b9a-bff1-ec0be2fb6ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385579606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3385579606
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3515993489
Short name T341
Test name
Test status
Simulation time 258580333 ps
CPU time 1.46 seconds
Started Jul 02 08:00:21 AM PDT 24
Finished Jul 02 08:00:37 AM PDT 24
Peak memory 200320 kb
Host smart-49e93131-d6ec-440f-9c21-429daf92d6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515993489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3515993489
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.470593630
Short name T33
Test name
Test status
Simulation time 1720333798 ps
CPU time 6.9 seconds
Started Jul 02 08:00:28 AM PDT 24
Finished Jul 02 08:00:51 AM PDT 24
Peak memory 200616 kb
Host smart-1cbfde8f-8d80-46df-a87a-af0dc4d2190a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470593630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.470593630
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3481848676
Short name T488
Test name
Test status
Simulation time 383957927 ps
CPU time 2.2 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 208100 kb
Host smart-09512af5-5ba9-4fb7-8397-f6219086e47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481848676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3481848676
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2105459606
Short name T228
Test name
Test status
Simulation time 141289085 ps
CPU time 1.12 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 200148 kb
Host smart-af0353b2-cc76-4277-9f6b-7943dda38831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105459606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2105459606
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2408609044
Short name T480
Test name
Test status
Simulation time 64580462 ps
CPU time 0.79 seconds
Started Jul 02 08:00:42 AM PDT 24
Finished Jul 02 08:01:02 AM PDT 24
Peak memory 199940 kb
Host smart-beed5575-963a-4215-ad35-0ee808e1766b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408609044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2408609044
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2578579497
Short name T39
Test name
Test status
Simulation time 1925470939 ps
CPU time 7.03 seconds
Started Jul 02 08:00:36 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 217564 kb
Host smart-106ca29d-434a-473d-a942-6da3cfade739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578579497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2578579497
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.4198735591
Short name T532
Test name
Test status
Simulation time 249038600 ps
CPU time 1.05 seconds
Started Jul 02 08:00:22 AM PDT 24
Finished Jul 02 08:00:38 AM PDT 24
Peak memory 217420 kb
Host smart-20b1dcee-fdba-4a7d-9d85-ac186f93234b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198735591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.4198735591
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1410251636
Short name T346
Test name
Test status
Simulation time 122313666 ps
CPU time 0.81 seconds
Started Jul 02 08:00:20 AM PDT 24
Finished Jul 02 08:00:36 AM PDT 24
Peak memory 199804 kb
Host smart-34c48ac2-e8d8-4774-add7-2bc76f6d8354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410251636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1410251636
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1331635829
Short name T10
Test name
Test status
Simulation time 148997950 ps
CPU time 1.08 seconds
Started Jul 02 08:00:32 AM PDT 24
Finished Jul 02 08:00:51 AM PDT 24
Peak memory 200364 kb
Host smart-38331167-6cde-41f2-8694-910df50e3f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331635829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1331635829
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.261318353
Short name T458
Test name
Test status
Simulation time 255788111 ps
CPU time 1.49 seconds
Started Jul 02 08:00:16 AM PDT 24
Finished Jul 02 08:00:30 AM PDT 24
Peak memory 200256 kb
Host smart-d3b216f4-869a-46f8-bc1d-eabec7071ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261318353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.261318353
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.564631137
Short name T510
Test name
Test status
Simulation time 2650086810 ps
CPU time 9.8 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:49 AM PDT 24
Peak memory 200436 kb
Host smart-2dbb02db-0baf-4015-85fe-c239667890b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564631137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.564631137
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4068104153
Short name T273
Test name
Test status
Simulation time 248940351 ps
CPU time 1.69 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:43 AM PDT 24
Peak memory 199956 kb
Host smart-64f1fd71-e4a7-4411-853d-8f8aca869694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068104153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4068104153
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1060559397
Short name T226
Test name
Test status
Simulation time 65040442 ps
CPU time 0.78 seconds
Started Jul 02 08:00:17 AM PDT 24
Finished Jul 02 08:00:31 AM PDT 24
Peak memory 200172 kb
Host smart-cb24ef0b-c242-4ac6-8915-6ac4afc0ddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060559397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1060559397
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.153712468
Short name T523
Test name
Test status
Simulation time 77203736 ps
CPU time 0.82 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:00 AM PDT 24
Peak memory 199924 kb
Host smart-229522cd-c02a-421d-b04d-3fac584c2800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153712468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.153712468
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2686279165
Short name T361
Test name
Test status
Simulation time 2344724822 ps
CPU time 8.04 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:49 AM PDT 24
Peak memory 221764 kb
Host smart-d2e38500-02d4-4d51-ab18-e7d9fce95496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686279165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2686279165
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3251653110
Short name T521
Test name
Test status
Simulation time 244491131 ps
CPU time 1.07 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 217352 kb
Host smart-b29a8e75-7c15-4d04-894d-a85883dca19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251653110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3251653110
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3831307745
Short name T20
Test name
Test status
Simulation time 143399329 ps
CPU time 0.78 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 199960 kb
Host smart-572b7bd4-a6c5-45fd-8670-88d93bdda742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831307745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3831307745
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1819446264
Short name T445
Test name
Test status
Simulation time 2201712951 ps
CPU time 7.77 seconds
Started Jul 02 08:00:33 AM PDT 24
Finished Jul 02 08:00:57 AM PDT 24
Peak memory 200484 kb
Host smart-63ad542a-e03e-4bbc-8e1e-da7d0bb4e46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819446264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1819446264
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1420669070
Short name T235
Test name
Test status
Simulation time 146902876 ps
CPU time 1.09 seconds
Started Jul 02 08:00:38 AM PDT 24
Finished Jul 02 08:00:56 AM PDT 24
Peak memory 200168 kb
Host smart-cbd15db6-ba80-4596-8ded-14e16ed857a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420669070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1420669070
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1978370884
Short name T246
Test name
Test status
Simulation time 237287866 ps
CPU time 1.48 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:42 AM PDT 24
Peak memory 200288 kb
Host smart-4a6cbede-ee4e-476d-9c89-774801a73daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978370884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1978370884
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.591531120
Short name T315
Test name
Test status
Simulation time 1119417673 ps
CPU time 5.53 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:45 AM PDT 24
Peak memory 200324 kb
Host smart-2f53b328-3771-4346-8ab6-cab215ed2509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591531120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.591531120
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.264333719
Short name T354
Test name
Test status
Simulation time 342623811 ps
CPU time 2.12 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:45 AM PDT 24
Peak memory 200164 kb
Host smart-68d61c18-0a67-4550-bf07-3c6e78b8eabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264333719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.264333719
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1102384633
Short name T409
Test name
Test status
Simulation time 149410598 ps
CPU time 0.99 seconds
Started Jul 02 08:00:25 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 200152 kb
Host smart-efd8138a-7dfd-4b58-9ece-e677d7675efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102384633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1102384633
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1025063591
Short name T256
Test name
Test status
Simulation time 78359977 ps
CPU time 0.86 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 199744 kb
Host smart-9215437f-501a-4af8-8396-82a9ee7c7cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025063591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1025063591
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.354221872
Short name T442
Test name
Test status
Simulation time 2360014270 ps
CPU time 7.95 seconds
Started Jul 02 08:00:30 AM PDT 24
Finished Jul 02 08:00:54 AM PDT 24
Peak memory 217796 kb
Host smart-9a040fa8-e80e-46e7-95cd-a6c148bad8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354221872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.354221872
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3328055231
Short name T241
Test name
Test status
Simulation time 244958130 ps
CPU time 1.04 seconds
Started Jul 02 08:00:45 AM PDT 24
Finished Jul 02 08:01:06 AM PDT 24
Peak memory 217500 kb
Host smart-2c8737fe-1cbc-48ca-b554-7db2e6342899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328055231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3328055231
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.324356960
Short name T17
Test name
Test status
Simulation time 161581863 ps
CPU time 0.86 seconds
Started Jul 02 08:00:41 AM PDT 24
Finished Jul 02 08:01:00 AM PDT 24
Peak memory 199868 kb
Host smart-1206ba14-5800-4e0c-be3b-b7826f0bea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324356960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.324356960
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.562497132
Short name T308
Test name
Test status
Simulation time 973824141 ps
CPU time 4.77 seconds
Started Jul 02 08:00:40 AM PDT 24
Finished Jul 02 08:01:04 AM PDT 24
Peak memory 200348 kb
Host smart-635ec626-e449-418e-8e8b-4d66c0d5d3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562497132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.562497132
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.596509567
Short name T501
Test name
Test status
Simulation time 129366508 ps
CPU time 1.31 seconds
Started Jul 02 08:00:23 AM PDT 24
Finished Jul 02 08:00:39 AM PDT 24
Peak memory 200352 kb
Host smart-b31e8159-7cb4-48b9-8ae0-8b445e92954a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596509567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.596509567
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.882892925
Short name T143
Test name
Test status
Simulation time 5230323756 ps
CPU time 18.39 seconds
Started Jul 02 08:00:33 AM PDT 24
Finished Jul 02 08:01:08 AM PDT 24
Peak memory 208632 kb
Host smart-a58bd76c-321d-4302-98d1-0722d18b59a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882892925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.882892925
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2131461808
Short name T310
Test name
Test status
Simulation time 127538636 ps
CPU time 1.62 seconds
Started Jul 02 08:00:47 AM PDT 24
Finished Jul 02 08:01:09 AM PDT 24
Peak memory 200108 kb
Host smart-ea18df18-dad7-41de-8888-33a827c59616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131461808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2131461808
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1813834144
Short name T267
Test name
Test status
Simulation time 286073554 ps
CPU time 1.58 seconds
Started Jul 02 08:00:35 AM PDT 24
Finished Jul 02 08:00:54 AM PDT 24
Peak memory 200352 kb
Host smart-62128e61-2367-4f11-9040-701044108fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813834144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1813834144
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.846598198
Short name T377
Test name
Test status
Simulation time 68655631 ps
CPU time 0.76 seconds
Started Jul 02 08:00:39 AM PDT 24
Finished Jul 02 08:00:57 AM PDT 24
Peak memory 199944 kb
Host smart-88e738c1-f1f0-444b-b83d-a31f5e159563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846598198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.846598198
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1820975228
Short name T57
Test name
Test status
Simulation time 1231124675 ps
CPU time 5.95 seconds
Started Jul 02 08:00:30 AM PDT 24
Finished Jul 02 08:00:53 AM PDT 24
Peak memory 221676 kb
Host smart-4d420552-efde-471b-8a3b-46fe40c04fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820975228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1820975228
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3212407814
Short name T298
Test name
Test status
Simulation time 244370669 ps
CPU time 1.05 seconds
Started Jul 02 08:00:21 AM PDT 24
Finished Jul 02 08:00:37 AM PDT 24
Peak memory 217492 kb
Host smart-6c880e3e-8519-4bc1-a56b-5c33a0aa8271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212407814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3212407814
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2275345748
Short name T507
Test name
Test status
Simulation time 125871929 ps
CPU time 0.76 seconds
Started Jul 02 08:00:40 AM PDT 24
Finished Jul 02 08:00:59 AM PDT 24
Peak memory 199944 kb
Host smart-6179a411-9ebf-40dd-b541-5ab4c22bd0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275345748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2275345748
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.4084481678
Short name T62
Test name
Test status
Simulation time 1368790459 ps
CPU time 5.34 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:44 AM PDT 24
Peak memory 200436 kb
Host smart-53bc2a24-d8ee-45eb-9af3-473e10261261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084481678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.4084481678
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1007339599
Short name T492
Test name
Test status
Simulation time 99649436 ps
CPU time 0.97 seconds
Started Jul 02 08:00:33 AM PDT 24
Finished Jul 02 08:00:51 AM PDT 24
Peak memory 200072 kb
Host smart-79a18b4e-c818-46b2-a248-700b19555f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007339599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1007339599
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4076983912
Short name T487
Test name
Test status
Simulation time 226986817 ps
CPU time 1.53 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:40 AM PDT 24
Peak memory 200328 kb
Host smart-c828401e-92b6-4252-b363-e60edd52d8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076983912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4076983912
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.487437204
Short name T188
Test name
Test status
Simulation time 5520698548 ps
CPU time 21.01 seconds
Started Jul 02 08:00:38 AM PDT 24
Finished Jul 02 08:01:17 AM PDT 24
Peak memory 200476 kb
Host smart-d1ff9515-1b15-428f-86e6-60357f5e3ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487437204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.487437204
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2669190875
Short name T345
Test name
Test status
Simulation time 364193470 ps
CPU time 2.02 seconds
Started Jul 02 08:00:26 AM PDT 24
Finished Jul 02 08:00:45 AM PDT 24
Peak memory 200156 kb
Host smart-da1cfcc7-cca8-4cbb-8d50-c20f0e7fc714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669190875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2669190875
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3037143366
Short name T520
Test name
Test status
Simulation time 165400825 ps
CPU time 1.13 seconds
Started Jul 02 08:00:24 AM PDT 24
Finished Jul 02 08:00:41 AM PDT 24
Peak memory 200088 kb
Host smart-e1ad42a1-99dc-495f-9280-0a0dae41d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037143366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3037143366
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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