Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7879

1

T1

15

T2

37

T5

3

auto[1]

10964

1

T1

1

T2

24

T5

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5807	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6389	1			T1	1		T2	14		T3	1
reset_info_cp[2]	2968	1			T2	11		T6	1		T7	49
reset_info_cp[4]	3778	1			T2	17		T6	1		T7	39
reset_info_cp[8]	89	1			T5	1		T7	2		T9	1
reset_info_cp[16]	118	1			T1	2		T7	1		T11	1
reset_info_cp[32]	111	1			T7	1		T23	2		T24	1
reset_info_cp[64]	93	1			T2	3		T7	2		T9	1
reset_info_cp[128]	110	1			T2	1		T7	1		T9	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3028	1			T2	6		T7	35		T9	20
reset_info_cp[1]	auto[1]	2741	1			T2	7		T6	1		T7	42
reset_info_cp[2]	auto[0]	936	1			T2	8		T7	27		T11	6
reset_info_cp[2]	auto[1]	2032	1			T2	3		T6	1		T7	22
reset_info_cp[4]	auto[0]	1349	1			T2	12		T7	17		T11	3
reset_info_cp[4]	auto[1]	2429	1			T2	5		T6	1		T7	22
reset_info_cp[8]	auto[0]	33	1			T7	1		T85	1		T135	1
reset_info_cp[8]	auto[1]	56	1			T5	1		T7	1		T9	1
reset_info_cp[16]	auto[0]	50	1			T1	2		T7	1		T23	2
reset_info_cp[16]	auto[1]	68	1			T11	1		T85	1		T26	1
reset_info_cp[32]	auto[0]	35	1			T23	1		T134	1		T129	1
reset_info_cp[32]	auto[1]	76	1			T7	1		T23	1		T24	1
reset_info_cp[64]	auto[0]	35	1			T2	2		T98	1		T83	1
reset_info_cp[64]	auto[1]	58	1			T2	1		T7	2		T9	1
reset_info_cp[128]	auto[0]	40	1			T83	1		T85	1		T53	2
reset_info_cp[128]	auto[1]	70	1			T2	1		T7	1		T9	1