Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T535 /workspace/coverage/default/16.rstmgr_smoke.2537233249 Jul 03 04:27:28 PM PDT 24 Jul 03 04:27:30 PM PDT 24 121238134 ps
T536 /workspace/coverage/default/39.rstmgr_sw_rst.922878746 Jul 03 04:28:02 PM PDT 24 Jul 03 04:28:08 PM PDT 24 452460546 ps
T537 /workspace/coverage/default/20.rstmgr_por_stretcher.1458262646 Jul 03 04:27:50 PM PDT 24 Jul 03 04:27:52 PM PDT 24 193772996 ps
T538 /workspace/coverage/default/15.rstmgr_smoke.1029646509 Jul 03 04:27:11 PM PDT 24 Jul 03 04:27:15 PM PDT 24 123205697 ps
T539 /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3883292889 Jul 03 04:28:00 PM PDT 24 Jul 03 04:28:02 PM PDT 24 90822308 ps
T60 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1960052375 Jul 03 04:27:22 PM PDT 24 Jul 03 04:27:23 PM PDT 24 119234521 ps
T61 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.404770902 Jul 03 04:26:53 PM PDT 24 Jul 03 04:26:55 PM PDT 24 261027469 ps
T62 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1257724839 Jul 03 04:27:08 PM PDT 24 Jul 03 04:27:11 PM PDT 24 128861290 ps
T109 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2233126841 Jul 03 04:27:07 PM PDT 24 Jul 03 04:27:09 PM PDT 24 73577578 ps
T540 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1748064594 Jul 03 04:26:53 PM PDT 24 Jul 03 04:26:55 PM PDT 24 107457971 ps
T110 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1077289433 Jul 03 04:27:07 PM PDT 24 Jul 03 04:27:11 PM PDT 24 279657755 ps
T111 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4292187979 Jul 03 04:27:08 PM PDT 24 Jul 03 04:27:12 PM PDT 24 133564528 ps
T112 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3203455669 Jul 03 04:27:06 PM PDT 24 Jul 03 04:27:08 PM PDT 24 129113818 ps
T65 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.692776657 Jul 03 04:26:48 PM PDT 24 Jul 03 04:26:56 PM PDT 24 787115948 ps
T113 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2376816881 Jul 03 04:27:13 PM PDT 24 Jul 03 04:27:15 PM PDT 24 144820530 ps
T66 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1596963040 Jul 03 04:27:06 PM PDT 24 Jul 03 04:27:11 PM PDT 24 422368519 ps
T114 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1481109342 Jul 03 04:26:52 PM PDT 24 Jul 03 04:26:54 PM PDT 24 70272547 ps
T132 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2984441160 Jul 03 04:27:23 PM PDT 24 Jul 03 04:27:24 PM PDT 24 76360296 ps
T68 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3545009000 Jul 03 04:27:10 PM PDT 24 Jul 03 04:27:14 PM PDT 24 774913506 ps
T67 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.944930392 Jul 03 04:27:04 PM PDT 24 Jul 03 04:27:07 PM PDT 24 363065632 ps
T115 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4281947475 Jul 03 04:27:02 PM PDT 24 Jul 03 04:27:04 PM PDT 24 228281089 ps
T541 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1489140372 Jul 03 04:26:54 PM PDT 24 Jul 03 04:26:57 PM PDT 24 351580817 ps
T90 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2385141490 Jul 03 04:26:49 PM PDT 24 Jul 03 04:26:51 PM PDT 24 170995048 ps
T91 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3968009701 Jul 03 04:27:05 PM PDT 24 Jul 03 04:27:09 PM PDT 24 773580807 ps
T92 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1764909909 Jul 03 04:27:26 PM PDT 24 Jul 03 04:27:27 PM PDT 24 129197972 ps
T542 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.65901192 Jul 03 04:27:19 PM PDT 24 Jul 03 04:27:26 PM PDT 24 484079985 ps
T93 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3588474705 Jul 03 04:28:39 PM PDT 24 Jul 03 04:28:43 PM PDT 24 770541419 ps
T94 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2793416830 Jul 03 04:27:07 PM PDT 24 Jul 03 04:27:09 PM PDT 24 116655690 ps
T117 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.909662353 Jul 03 04:26:55 PM PDT 24 Jul 03 04:27:03 PM PDT 24 475691993 ps
T97 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3872089976 Jul 03 04:27:06 PM PDT 24 Jul 03 04:27:09 PM PDT 24 420661708 ps
T116 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3311280951 Jul 03 04:27:15 PM PDT 24 Jul 03 04:27:16 PM PDT 24 64981247 ps
T122 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2088436403 Jul 03 04:26:52 PM PDT 24 Jul 03 04:26:55 PM PDT 24 502621690 ps
T95 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2320090159 Jul 03 04:26:59 PM PDT 24 Jul 03 04:27:01 PM PDT 24 161939118 ps
T543 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3680852383 Jul 03 04:27:01 PM PDT 24 Jul 03 04:27:03 PM PDT 24 56412143 ps
T96 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.398932942 Jul 03 04:27:02 PM PDT 24 Jul 03 04:27:04 PM PDT 24 169365833 ps
T124 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3849931757 Jul 03 04:27:01 PM PDT 24 Jul 03 04:27:03 PM PDT 24 115327023 ps
T544 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3720372721 Jul 03 04:27:07 PM PDT 24 Jul 03 04:27:09 PM PDT 24 86826389 ps
T118 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1931568139 Jul 03 04:27:06 PM PDT 24 Jul 03 04:27:09 PM PDT 24 176532980 ps
T545 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.460263751 Jul 03 04:27:04 PM PDT 24 Jul 03 04:27:07 PM PDT 24 126161704 ps
T546 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.602636787 Jul 03 04:28:39 PM PDT 24 Jul 03 04:28:41 PM PDT 24 182400752 ps
T121 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4130329456 Jul 03 04:27:10 PM PDT 24 Jul 03 04:27:16 PM PDT 24 1165837815 ps
T123 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1415448223 Jul 03 04:27:00 PM PDT 24 Jul 03 04:27:02 PM PDT 24 468578055 ps
T547 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3316052576 Jul 03 04:27:07 PM PDT 24 Jul 03 04:27:10 PM PDT 24 71452969 ps
T548 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1184604546 Jul 03 04:27:30 PM PDT 24 Jul 03 04:27:32 PM PDT 24 141196525 ps
T549 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1018339453 Jul 03 04:27:48 PM PDT 24 Jul 03 04:27:50 PM PDT 24 185734386 ps
T550 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1718507124 Jul 03 04:27:03 PM PDT 24 Jul 03 04:27:05 PM PDT 24 183480879 ps
T551 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2096327939 Jul 03 04:27:32 PM PDT 24 Jul 03 04:27:34 PM PDT 24 245949448 ps
T552 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.706406840 Jul 03 04:27:05 PM PDT 24 Jul 03 04:27:06 PM PDT 24 75483824 ps
T553 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3151074837 Jul 03 04:27:12 PM PDT 24 Jul 03 04:27:17 PM PDT 24 400616118 ps
T554 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1161943889 Jul 03 04:27:02 PM PDT 24 Jul 03 04:27:08 PM PDT 24 1170997820 ps
T555 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3503639640 Jul 03 04:27:03 PM PDT 24 Jul 03 04:27:06 PM PDT 24 188365233 ps
T556 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2254129232 Jul 03 04:27:07 PM PDT 24 Jul 03 04:27:10 PM PDT 24 182161639 ps
T557 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3904067334 Jul 03 04:28:43 PM PDT 24 Jul 03 04:28:44 PM PDT 24 67231713 ps
T558 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.916503937 Jul 03 04:27:35 PM PDT 24 Jul 03 04:27:37 PM PDT 24 84206766 ps
T130 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4116402629 Jul 03 04:27:05 PM PDT 24 Jul 03 04:27:08 PM PDT 24 808617618 ps
T131 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2667562853 Jul 03 04:27:18 PM PDT 24 Jul 03 04:27:21 PM PDT 24 513874714 ps
T559 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1617148469 Jul 03 04:27:35 PM PDT 24 Jul 03 04:27:36 PM PDT 24 61989496 ps
T560 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.570278249 Jul 03 04:27:06 PM PDT 24 Jul 03 04:27:08 PM PDT 24 82826290 ps
T561 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.973110009 Jul 03 04:27:04 PM PDT 24 Jul 03 04:27:07 PM PDT 24 421916364 ps
T562 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2692201305 Jul 03 04:26:52 PM PDT 24 Jul 03 04:26:53 PM PDT 24 112023854 ps
T563 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1941071684 Jul 03 04:27:46 PM PDT 24 Jul 03 04:27:47 PM PDT 24 70652318 ps
T564 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.853821587 Jul 03 04:27:01 PM PDT 24 Jul 03 04:27:03 PM PDT 24 119524144 ps
T565 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2662307584 Jul 03 04:27:00 PM PDT 24 Jul 03 04:27:02 PM PDT 24 120115518 ps
T566 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1654499623 Jul 03 04:27:04 PM PDT 24 Jul 03 04:27:07 PM PDT 24 890666703 ps
T567 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.111689023 Jul 03 04:27:11 PM PDT 24 Jul 03 04:27:14 PM PDT 24 209159893 ps
T568 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1062994916 Jul 03 04:27:06 PM PDT 24 Jul 03 04:27:09 PM PDT 24 92079673 ps
T569 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.621288368 Jul 03 04:27:07 PM PDT 24 Jul 03 04:27:14 PM PDT 24 2292516218 ps
T570 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3344021792 Jul 03 04:27:08 PM PDT 24 Jul 03 04:27:13 PM PDT 24 595333706 ps
T571 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4010093244 Jul 03 04:27:11 PM PDT 24 Jul 03 04:27:16 PM PDT 24 189157659 ps
T572 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1452158279 Jul 03 04:26:56 PM PDT 24 Jul 03 04:26:57 PM PDT 24 70108694 ps
T573 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.581338069 Jul 03 04:27:06 PM PDT 24 Jul 03 04:27:09 PM PDT 24 88154517 ps
T574 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3645842366 Jul 03 04:26:52 PM PDT 24 Jul 03 04:27:01 PM PDT 24 1549710797 ps
T575 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3441484337 Jul 03 04:27:11 PM PDT 24 Jul 03 04:27:14 PM PDT 24 64194900 ps
T120 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1785198529 Jul 03 04:27:06 PM PDT 24 Jul 03 04:27:10 PM PDT 24 908951896 ps
T576 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3823662928 Jul 03 04:27:22 PM PDT 24 Jul 03 04:27:24 PM PDT 24 184201529 ps
T577 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1133060409 Jul 03 04:27:00 PM PDT 24 Jul 03 04:27:03 PM PDT 24 336442086 ps
T578 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.4168294008 Jul 03 04:26:53 PM PDT 24 Jul 03 04:26:56 PM PDT 24 252790413 ps
T579 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.726889212 Jul 03 04:26:58 PM PDT 24 Jul 03 04:27:01 PM PDT 24 462582283 ps
T580 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2525422056 Jul 03 04:27:06 PM PDT 24 Jul 03 04:27:09 PM PDT 24 127659595 ps
T581 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3489002108 Jul 03 04:27:09 PM PDT 24 Jul 03 04:27:13 PM PDT 24 388690923 ps
T582 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2074117658 Jul 03 04:27:10 PM PDT 24 Jul 03 04:27:13 PM PDT 24 146037377 ps
T583 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2104166320 Jul 03 04:27:12 PM PDT 24 Jul 03 04:27:15 PM PDT 24 124149268 ps
T584 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3881089698 Jul 03 04:27:07 PM PDT 24 Jul 03 04:27:10 PM PDT 24 213577986 ps
T585 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4101696512 Jul 03 04:27:08 PM PDT 24 Jul 03 04:27:11 PM PDT 24 211528952 ps
T119 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.45068917 Jul 03 04:27:07 PM PDT 24 Jul 03 04:27:11 PM PDT 24 793750608 ps
T586 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3333979857 Jul 03 04:27:35 PM PDT 24 Jul 03 04:27:37 PM PDT 24 247040160 ps
T587 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.769696798 Jul 03 04:27:31 PM PDT 24 Jul 03 04:27:33 PM PDT 24 75035893 ps
T588 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4157218001 Jul 03 04:27:33 PM PDT 24 Jul 03 04:27:35 PM PDT 24 460442361 ps
T589 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.282807975 Jul 03 04:27:00 PM PDT 24 Jul 03 04:27:04 PM PDT 24 801662156 ps
T590 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4159786918 Jul 03 04:27:01 PM PDT 24 Jul 03 04:27:03 PM PDT 24 145906542 ps
T591 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.402970541 Jul 03 04:27:02 PM PDT 24 Jul 03 04:27:04 PM PDT 24 87106299 ps
T592 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3569917614 Jul 03 04:27:24 PM PDT 24 Jul 03 04:27:26 PM PDT 24 124982231 ps
T593 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3262073654 Jul 03 04:27:00 PM PDT 24 Jul 03 04:27:01 PM PDT 24 143361479 ps
T594 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1733031151 Jul 03 04:27:20 PM PDT 24 Jul 03 04:27:21 PM PDT 24 116117750 ps
T595 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1289994092 Jul 03 04:27:17 PM PDT 24 Jul 03 04:27:19 PM PDT 24 216319554 ps
T596 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.127828180 Jul 03 04:27:23 PM PDT 24 Jul 03 04:27:26 PM PDT 24 190237557 ps
T597 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1564104577 Jul 03 04:27:35 PM PDT 24 Jul 03 04:27:36 PM PDT 24 89324673 ps
T598 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.593706851 Jul 03 04:27:03 PM PDT 24 Jul 03 04:27:04 PM PDT 24 123080050 ps
T599 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1437584960 Jul 03 04:27:11 PM PDT 24 Jul 03 04:27:16 PM PDT 24 447275410 ps
T600 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2348277371 Jul 03 04:26:55 PM PDT 24 Jul 03 04:26:56 PM PDT 24 111731441 ps
T601 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3358699711 Jul 03 04:27:19 PM PDT 24 Jul 03 04:27:21 PM PDT 24 466325183 ps
T602 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3426664841 Jul 03 04:27:11 PM PDT 24 Jul 03 04:27:14 PM PDT 24 64616202 ps
T603 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.974707841 Jul 03 04:27:09 PM PDT 24 Jul 03 04:27:12 PM PDT 24 106731455 ps
T604 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1410660834 Jul 03 04:27:06 PM PDT 24 Jul 03 04:27:08 PM PDT 24 69371122 ps
T605 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3786364010 Jul 03 04:27:00 PM PDT 24 Jul 03 04:27:03 PM PDT 24 359448251 ps
T606 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3026507748 Jul 03 04:27:17 PM PDT 24 Jul 03 04:27:23 PM PDT 24 94657075 ps
T607 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3269162398 Jul 03 04:26:54 PM PDT 24 Jul 03 04:26:55 PM PDT 24 140582498 ps
T608 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3459806804 Jul 03 04:28:39 PM PDT 24 Jul 03 04:28:42 PM PDT 24 499448138 ps
T609 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2794153786 Jul 03 04:27:03 PM PDT 24 Jul 03 04:27:05 PM PDT 24 73748195 ps
T610 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2865949776 Jul 03 04:27:14 PM PDT 24 Jul 03 04:27:16 PM PDT 24 181235517 ps
T611 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3164437170 Jul 03 04:27:11 PM PDT 24 Jul 03 04:27:15 PM PDT 24 154566003 ps
T612 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.102279321 Jul 03 04:27:02 PM PDT 24 Jul 03 04:27:06 PM PDT 24 878701299 ps
T613 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2128670280 Jul 03 04:26:49 PM PDT 24 Jul 03 04:26:57 PM PDT 24 1539128286 ps
T614 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.574388396 Jul 03 04:27:02 PM PDT 24 Jul 03 04:27:06 PM PDT 24 503580921 ps
T615 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.710540651 Jul 03 04:27:11 PM PDT 24 Jul 03 04:27:15 PM PDT 24 114320573 ps
T616 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2167446382 Jul 03 04:27:05 PM PDT 24 Jul 03 04:27:09 PM PDT 24 556823564 ps
T617 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3275836348 Jul 03 04:26:52 PM PDT 24 Jul 03 04:26:54 PM PDT 24 128291079 ps
T618 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3146074170 Jul 03 04:27:07 PM PDT 24 Jul 03 04:27:10 PM PDT 24 204568861 ps
T619 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3104431067 Jul 03 04:27:01 PM PDT 24 Jul 03 04:27:03 PM PDT 24 85025700 ps
T620 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1289364579 Jul 03 04:26:55 PM PDT 24 Jul 03 04:26:56 PM PDT 24 131653469 ps

Test location /workspace/coverage/default/4.rstmgr_stress_all.2179110857
Short name T7
Test name
Test status
Simulation time 6497614929 ps
CPU time 24.61 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:33 PM PDT 24
Peak memory 200364 kb
Host smart-69413fbd-5602-4e74-95bb-a44514ac817a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179110857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2179110857
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3869650619
Short name T12
Test name
Test status
Simulation time 470533167 ps
CPU time 2.49 seconds
Started Jul 03 04:28:06 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 200152 kb
Host smart-d006e8ec-9c68-42a0-be67-f20bf62d4b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869650619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3869650619
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1960052375
Short name T60
Test name
Test status
Simulation time 119234521 ps
CPU time 1.22 seconds
Started Jul 03 04:27:22 PM PDT 24
Finished Jul 03 04:27:23 PM PDT 24
Peak memory 208552 kb
Host smart-b6205110-8e69-457c-8efc-363d3878394d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960052375 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1960052375
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1191541294
Short name T69
Test name
Test status
Simulation time 16786964983 ps
CPU time 23.75 seconds
Started Jul 03 04:27:24 PM PDT 24
Finished Jul 03 04:27:48 PM PDT 24
Peak memory 218132 kb
Host smart-7814605f-816a-4cd1-af82-ebe9b8e04125
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191541294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1191541294
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2034245381
Short name T24
Test name
Test status
Simulation time 1224660214 ps
CPU time 5.63 seconds
Started Jul 03 04:28:05 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 217544 kb
Host smart-29bb992c-1d62-4d4f-aa9d-652decd41271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034245381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2034245381
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4130329456
Short name T121
Test name
Test status
Simulation time 1165837815 ps
CPU time 3.59 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 200280 kb
Host smart-78604d02-e6af-46c9-b27f-9c88bc90c222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130329456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.4130329456
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.341049984
Short name T72
Test name
Test status
Simulation time 68486853 ps
CPU time 0.76 seconds
Started Jul 03 04:27:17 PM PDT 24
Finished Jul 03 04:27:18 PM PDT 24
Peak memory 199860 kb
Host smart-1d3428f0-3fac-407c-8664-278b534138af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341049984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.341049984
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.944930392
Short name T67
Test name
Test status
Simulation time 363065632 ps
CPU time 2.56 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:07 PM PDT 24
Peak memory 208368 kb
Host smart-86f2df15-bec0-4cd2-a43b-7de0424744e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944930392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.944930392
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1426391336
Short name T55
Test name
Test status
Simulation time 3846651389 ps
CPU time 17.79 seconds
Started Jul 03 04:27:47 PM PDT 24
Finished Jul 03 04:28:06 PM PDT 24
Peak memory 200400 kb
Host smart-0f8b53a6-b712-499c-98cb-11ddeb404be1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426391336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1426391336
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2557325056
Short name T161
Test name
Test status
Simulation time 105951742 ps
CPU time 1.04 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 199928 kb
Host smart-ed6232e0-9e11-457e-aab6-3db267c44511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557325056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2557325056
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1356322968
Short name T127
Test name
Test status
Simulation time 5591858240 ps
CPU time 18.46 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:33 PM PDT 24
Peak memory 200372 kb
Host smart-30a67176-ba5a-40f2-a71c-8b78ef22ad15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356322968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1356322968
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1489521858
Short name T27
Test name
Test status
Simulation time 1233365397 ps
CPU time 5.51 seconds
Started Jul 03 04:27:16 PM PDT 24
Finished Jul 03 04:27:22 PM PDT 24
Peak memory 221688 kb
Host smart-9ebd1431-7f4d-4936-a698-acac997d289b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489521858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1489521858
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2309435297
Short name T134
Test name
Test status
Simulation time 119361078 ps
CPU time 0.99 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 200060 kb
Host smart-f7893010-a36c-494b-87a5-9552e5bcd952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309435297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2309435297
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3968009701
Short name T91
Test name
Test status
Simulation time 773580807 ps
CPU time 2.89 seconds
Started Jul 03 04:27:05 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 200248 kb
Host smart-1d909925-2712-42f5-af97-613f631aed98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968009701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3968009701
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.595888635
Short name T25
Test name
Test status
Simulation time 1877670143 ps
CPU time 6.57 seconds
Started Jul 03 04:28:03 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 217696 kb
Host smart-5700a8ef-7f6e-4ee8-afbd-6548272edf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595888635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.595888635
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4010093244
Short name T571
Test name
Test status
Simulation time 189157659 ps
CPU time 2.74 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 216568 kb
Host smart-c3195efc-5577-4ee7-80f3-15ef8bad6f71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010093244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4010093244
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.404770902
Short name T61
Test name
Test status
Simulation time 261027469 ps
CPU time 1.6 seconds
Started Jul 03 04:26:53 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 200348 kb
Host smart-b7729ed4-47b0-40af-ad32-91437ee3f73b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404770902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.404770902
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3575965534
Short name T16
Test name
Test status
Simulation time 140647837 ps
CPU time 0.78 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:13 PM PDT 24
Peak memory 199796 kb
Host smart-844ca8df-701c-4e75-a269-2ca86d66a658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575965534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3575965534
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3830918503
Short name T150
Test name
Test status
Simulation time 243610708 ps
CPU time 1.14 seconds
Started Jul 03 04:27:31 PM PDT 24
Finished Jul 03 04:27:32 PM PDT 24
Peak memory 217368 kb
Host smart-720154f7-d0b5-4b0c-b286-815700572873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830918503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3830918503
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.692776657
Short name T65
Test name
Test status
Simulation time 787115948 ps
CPU time 3.11 seconds
Started Jul 03 04:26:48 PM PDT 24
Finished Jul 03 04:26:56 PM PDT 24
Peak memory 200540 kb
Host smart-5c7319a3-6448-4ea8-afa7-1ae5739f32a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692776657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
692776657
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3459806804
Short name T608
Test name
Test status
Simulation time 499448138 ps
CPU time 1.83 seconds
Started Jul 03 04:28:39 PM PDT 24
Finished Jul 03 04:28:42 PM PDT 24
Peak memory 200268 kb
Host smart-bb5ca1a7-4d04-41db-8984-7f4759d14cee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459806804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3459806804
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4101696512
Short name T585
Test name
Test status
Simulation time 211528952 ps
CPU time 1.53 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:11 PM PDT 24
Peak memory 200172 kb
Host smart-08b99dea-f9a6-4a46-b76c-31e4f2569896
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101696512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
101696512
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1161943889
Short name T554
Test name
Test status
Simulation time 1170997820 ps
CPU time 5.12 seconds
Started Jul 03 04:27:02 PM PDT 24
Finished Jul 03 04:27:08 PM PDT 24
Peak memory 200308 kb
Host smart-a304aae7-3a4e-461b-b763-001468361d44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161943889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
161943889
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3269162398
Short name T607
Test name
Test status
Simulation time 140582498 ps
CPU time 0.92 seconds
Started Jul 03 04:26:54 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 200208 kb
Host smart-aee0be6f-6c3f-4fdb-9151-0fecc8221f95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269162398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
269162398
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3104431067
Short name T619
Test name
Test status
Simulation time 85025700 ps
CPU time 0.89 seconds
Started Jul 03 04:27:01 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 200192 kb
Host smart-b95864e2-45ab-43e7-bdd4-d98300c027fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104431067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3104431067
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3881089698
Short name T584
Test name
Test status
Simulation time 213577986 ps
CPU time 1.38 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 200292 kb
Host smart-55081349-b55f-4a26-919a-f8d2cf414e32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881089698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3881089698
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.726889212
Short name T579
Test name
Test status
Simulation time 462582283 ps
CPU time 2.88 seconds
Started Jul 03 04:26:58 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 200264 kb
Host smart-de8db4a0-9aaf-4ff6-8b35-2e8c76110087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726889212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.726889212
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1437584960
Short name T599
Test name
Test status
Simulation time 447275410 ps
CPU time 2.87 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 200264 kb
Host smart-1ba1eb8d-55e9-421b-813e-bfececb4ea8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437584960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
437584960
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2128670280
Short name T613
Test name
Test status
Simulation time 1539128286 ps
CPU time 7.67 seconds
Started Jul 03 04:26:49 PM PDT 24
Finished Jul 03 04:26:57 PM PDT 24
Peak memory 200232 kb
Host smart-5ac62bdd-bc41-467e-8cb9-b4d54930b10c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128670280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
128670280
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2074117658
Short name T582
Test name
Test status
Simulation time 146037377 ps
CPU time 0.97 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:13 PM PDT 24
Peak memory 200184 kb
Host smart-a85f64b1-bd76-44fe-b964-0a282e7e6e39
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074117658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
074117658
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2104166320
Short name T583
Test name
Test status
Simulation time 124149268 ps
CPU time 0.94 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 200224 kb
Host smart-a7d437c8-d2ac-43d8-86f5-c4515c70a0d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104166320 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2104166320
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1452158279
Short name T572
Test name
Test status
Simulation time 70108694 ps
CPU time 0.78 seconds
Started Jul 03 04:26:56 PM PDT 24
Finished Jul 03 04:26:57 PM PDT 24
Peak memory 200152 kb
Host smart-fb4811d2-81fb-407b-8157-bfa2e059383b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452158279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1452158279
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1133060409
Short name T577
Test name
Test status
Simulation time 336442086 ps
CPU time 2.37 seconds
Started Jul 03 04:27:00 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 211264 kb
Host smart-d1838ce2-5acb-4a10-9d4c-b04b8c2445d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133060409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1133060409
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.593706851
Short name T598
Test name
Test status
Simulation time 123080050 ps
CPU time 1.01 seconds
Started Jul 03 04:27:03 PM PDT 24
Finished Jul 03 04:27:04 PM PDT 24
Peak memory 200120 kb
Host smart-b5dced3b-4b64-4715-86d7-6575e4403995
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593706851 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.593706851
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1410660834
Short name T604
Test name
Test status
Simulation time 69371122 ps
CPU time 0.79 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:08 PM PDT 24
Peak memory 199988 kb
Host smart-f8024118-8ec8-4a51-824e-6ace451b49c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410660834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1410660834
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1018339453
Short name T549
Test name
Test status
Simulation time 185734386 ps
CPU time 1.41 seconds
Started Jul 03 04:27:48 PM PDT 24
Finished Jul 03 04:27:50 PM PDT 24
Peak memory 200252 kb
Host smart-55756e0b-3d0d-435b-a4f4-f2dac0963668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018339453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1018339453
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3164437170
Short name T611
Test name
Test status
Simulation time 154566003 ps
CPU time 2.04 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 216532 kb
Host smart-40c0f40d-b5d6-4d2b-92ff-21329929297a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164437170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3164437170
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1785198529
Short name T120
Test name
Test status
Simulation time 908951896 ps
CPU time 2.85 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 200388 kb
Host smart-2a8e5a0e-c6e2-4e26-8604-ab0161f07830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785198529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1785198529
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.111689023
Short name T567
Test name
Test status
Simulation time 209159893 ps
CPU time 1.26 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 208448 kb
Host smart-fcc7bd8c-c617-489c-bb40-1932baf93ec0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111689023 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.111689023
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3311280951
Short name T116
Test name
Test status
Simulation time 64981247 ps
CPU time 0.8 seconds
Started Jul 03 04:27:15 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 200164 kb
Host smart-3fe5b14d-23f5-4b0d-acc8-f689c0e276b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311280951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3311280951
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1184604546
Short name T548
Test name
Test status
Simulation time 141196525 ps
CPU time 1.11 seconds
Started Jul 03 04:27:30 PM PDT 24
Finished Jul 03 04:27:32 PM PDT 24
Peak memory 200576 kb
Host smart-afd78e98-bb45-45a9-91bb-856caeafa4f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184604546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1184604546
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2096327939
Short name T551
Test name
Test status
Simulation time 245949448 ps
CPU time 1.77 seconds
Started Jul 03 04:27:32 PM PDT 24
Finished Jul 03 04:27:34 PM PDT 24
Peak memory 208476 kb
Host smart-022f5f82-eb05-45d1-9a0f-fc29fc4f4589
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096327939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2096327939
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3872089976
Short name T97
Test name
Test status
Simulation time 420661708 ps
CPU time 1.77 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 200476 kb
Host smart-a0ace0ee-b985-4d6f-ba19-f23ae03edd27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872089976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3872089976
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.398932942
Short name T96
Test name
Test status
Simulation time 169365833 ps
CPU time 1.63 seconds
Started Jul 03 04:27:02 PM PDT 24
Finished Jul 03 04:27:04 PM PDT 24
Peak memory 208652 kb
Host smart-3856baf0-6828-4393-8123-3ff293603b5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398932942 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.398932942
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.570278249
Short name T560
Test name
Test status
Simulation time 82826290 ps
CPU time 0.86 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:08 PM PDT 24
Peak memory 200108 kb
Host smart-9cdf37ca-9cdd-4cde-a3ee-85cd3771605e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570278249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.570278249
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4292187979
Short name T111
Test name
Test status
Simulation time 133564528 ps
CPU time 1.04 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:12 PM PDT 24
Peak memory 199668 kb
Host smart-88f2e75a-b425-4276-8640-0b9477e17544
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292187979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4292187979
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.460263751
Short name T545
Test name
Test status
Simulation time 126161704 ps
CPU time 1.9 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:07 PM PDT 24
Peak memory 208464 kb
Host smart-d3a59a1c-ce03-407d-b3c7-021cbe3f2a1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460263751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.460263751
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.45068917
Short name T119
Test name
Test status
Simulation time 793750608 ps
CPU time 2.87 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:11 PM PDT 24
Peak memory 200416 kb
Host smart-23a9508d-bf8b-4b95-b9d3-9b74ff1b11bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45068917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.45068917
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1564104577
Short name T597
Test name
Test status
Simulation time 89324673 ps
CPU time 0.87 seconds
Started Jul 03 04:27:35 PM PDT 24
Finished Jul 03 04:27:36 PM PDT 24
Peak memory 200240 kb
Host smart-4d244461-b035-40e5-b711-5fa9d1c03d09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564104577 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1564104577
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.769696798
Short name T587
Test name
Test status
Simulation time 75035893 ps
CPU time 0.83 seconds
Started Jul 03 04:27:31 PM PDT 24
Finished Jul 03 04:27:33 PM PDT 24
Peak memory 200092 kb
Host smart-55a06488-9396-4cd4-864a-7f961ed14692
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769696798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.769696798
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3316052576
Short name T547
Test name
Test status
Simulation time 71452969 ps
CPU time 0.92 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 200148 kb
Host smart-55c59814-59d5-411c-ba5f-f606e3c7ad39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316052576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3316052576
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3503639640
Short name T555
Test name
Test status
Simulation time 188365233 ps
CPU time 2.4 seconds
Started Jul 03 04:27:03 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 208392 kb
Host smart-c04d98b7-ba32-4b83-b12a-606e00028f02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503639640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3503639640
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.102279321
Short name T612
Test name
Test status
Simulation time 878701299 ps
CPU time 2.98 seconds
Started Jul 03 04:27:02 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 200248 kb
Host smart-ee32783d-4859-4f6a-abc7-2a35512cb26a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102279321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.102279321
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2793416830
Short name T94
Test name
Test status
Simulation time 116655690 ps
CPU time 1.02 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 208556 kb
Host smart-c6ccc5e9-a578-4685-8075-d88e62d6580a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793416830 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2793416830
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1941071684
Short name T563
Test name
Test status
Simulation time 70652318 ps
CPU time 0.77 seconds
Started Jul 03 04:27:46 PM PDT 24
Finished Jul 03 04:27:47 PM PDT 24
Peak memory 200152 kb
Host smart-8bdc58c3-b5c6-4471-98e8-7988d8bdecfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941071684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1941071684
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3823662928
Short name T576
Test name
Test status
Simulation time 184201529 ps
CPU time 1.44 seconds
Started Jul 03 04:27:22 PM PDT 24
Finished Jul 03 04:27:24 PM PDT 24
Peak memory 200424 kb
Host smart-27591802-8fdb-4cd7-a996-9dd26e72700b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823662928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3823662928
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2662307584
Short name T565
Test name
Test status
Simulation time 120115518 ps
CPU time 0.97 seconds
Started Jul 03 04:27:00 PM PDT 24
Finished Jul 03 04:27:02 PM PDT 24
Peak memory 200360 kb
Host smart-b38c04bd-97a1-4953-8a50-496143b2ef1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662307584 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2662307584
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1617148469
Short name T559
Test name
Test status
Simulation time 61989496 ps
CPU time 0.78 seconds
Started Jul 03 04:27:35 PM PDT 24
Finished Jul 03 04:27:36 PM PDT 24
Peak memory 200224 kb
Host smart-24418a40-97af-4104-8cbb-f87003a5dd80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617148469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1617148469
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4281947475
Short name T115
Test name
Test status
Simulation time 228281089 ps
CPU time 1.53 seconds
Started Jul 03 04:27:02 PM PDT 24
Finished Jul 03 04:27:04 PM PDT 24
Peak memory 200460 kb
Host smart-3a9d910f-3d17-47c3-9375-342b49a19d9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281947475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.4281947475
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3146074170
Short name T618
Test name
Test status
Simulation time 204568861 ps
CPU time 1.72 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 208496 kb
Host smart-31762e4d-3530-4e42-82d6-ab33afa4ad20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146074170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3146074170
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1415448223
Short name T123
Test name
Test status
Simulation time 468578055 ps
CPU time 1.83 seconds
Started Jul 03 04:27:00 PM PDT 24
Finished Jul 03 04:27:02 PM PDT 24
Peak memory 200400 kb
Host smart-e38bf211-f287-49e5-a318-420be0bb2a96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415448223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1415448223
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.974707841
Short name T603
Test name
Test status
Simulation time 106731455 ps
CPU time 1.11 seconds
Started Jul 03 04:27:09 PM PDT 24
Finished Jul 03 04:27:12 PM PDT 24
Peak memory 208540 kb
Host smart-9952f2ef-6d3f-4d7f-bdc6-738a9a0270ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974707841 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.974707841
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2984441160
Short name T132
Test name
Test status
Simulation time 76360296 ps
CPU time 0.84 seconds
Started Jul 03 04:27:23 PM PDT 24
Finished Jul 03 04:27:24 PM PDT 24
Peak memory 200048 kb
Host smart-eef8b80d-e4d9-4710-bbf2-1cf118f6aeef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984441160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2984441160
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1077289433
Short name T110
Test name
Test status
Simulation time 279657755 ps
CPU time 1.78 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:11 PM PDT 24
Peak memory 200312 kb
Host smart-323a8c45-6ea5-4ab9-a7f9-099fa66f1e90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077289433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1077289433
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1062994916
Short name T568
Test name
Test status
Simulation time 92079673 ps
CPU time 1.37 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 208412 kb
Host smart-8f15c6ce-39bd-4401-8f6d-bf06169668fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062994916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1062994916
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1654499623
Short name T566
Test name
Test status
Simulation time 890666703 ps
CPU time 2.92 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:07 PM PDT 24
Peak memory 200440 kb
Host smart-930421e7-96a7-48b3-b157-7277c0299082
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654499623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1654499623
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.602636787
Short name T546
Test name
Test status
Simulation time 182400752 ps
CPU time 1.17 seconds
Started Jul 03 04:28:39 PM PDT 24
Finished Jul 03 04:28:41 PM PDT 24
Peak memory 209532 kb
Host smart-05934c89-55ef-4023-aec5-662eda0842b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602636787 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.602636787
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.402970541
Short name T591
Test name
Test status
Simulation time 87106299 ps
CPU time 0.9 seconds
Started Jul 03 04:27:02 PM PDT 24
Finished Jul 03 04:27:04 PM PDT 24
Peak memory 200100 kb
Host smart-398c776c-d2c6-4ef2-833e-85a3ef32f11c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402970541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.402970541
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2376816881
Short name T113
Test name
Test status
Simulation time 144820530 ps
CPU time 1.15 seconds
Started Jul 03 04:27:13 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 200252 kb
Host smart-1a238d5e-fc4e-4be6-b1d0-f6d9b592c394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376816881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2376816881
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.127828180
Short name T596
Test name
Test status
Simulation time 190237557 ps
CPU time 2.6 seconds
Started Jul 03 04:27:23 PM PDT 24
Finished Jul 03 04:27:26 PM PDT 24
Peak memory 208480 kb
Host smart-762fb612-7916-4eea-bba1-91d9b2281873
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127828180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.127828180
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3588474705
Short name T93
Test name
Test status
Simulation time 770541419 ps
CPU time 2.95 seconds
Started Jul 03 04:28:39 PM PDT 24
Finished Jul 03 04:28:43 PM PDT 24
Peak memory 200260 kb
Host smart-3f1ae459-8a51-4afe-abc6-6c4f70ef7637
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588474705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3588474705
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2254129232
Short name T556
Test name
Test status
Simulation time 182161639 ps
CPU time 1.54 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 213076 kb
Host smart-f964fda5-a5b7-4804-9869-2ff0f84cf6bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254129232 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2254129232
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3441484337
Short name T575
Test name
Test status
Simulation time 64194900 ps
CPU time 0.78 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 200072 kb
Host smart-ed521c05-f820-4296-906a-e6f598fec27e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441484337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3441484337
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3333979857
Short name T586
Test name
Test status
Simulation time 247040160 ps
CPU time 1.49 seconds
Started Jul 03 04:27:35 PM PDT 24
Finished Jul 03 04:27:37 PM PDT 24
Peak memory 200252 kb
Host smart-7465721c-c1aa-4872-ad3c-405349126232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333979857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3333979857
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2667562853
Short name T131
Test name
Test status
Simulation time 513874714 ps
CPU time 1.99 seconds
Started Jul 03 04:27:18 PM PDT 24
Finished Jul 03 04:27:21 PM PDT 24
Peak memory 200248 kb
Host smart-b65028cb-0779-4a48-94e2-3c919308ed4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667562853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2667562853
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1289994092
Short name T595
Test name
Test status
Simulation time 216319554 ps
CPU time 1.31 seconds
Started Jul 03 04:27:17 PM PDT 24
Finished Jul 03 04:27:19 PM PDT 24
Peak memory 208500 kb
Host smart-faac8f5c-55f3-429b-abae-e9375f34f4e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289994092 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1289994092
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2233126841
Short name T109
Test name
Test status
Simulation time 73577578 ps
CPU time 0.77 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 200068 kb
Host smart-db9c8cad-def7-4faa-aa08-1dc8a5e4bc31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233126841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2233126841
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1733031151
Short name T594
Test name
Test status
Simulation time 116117750 ps
CPU time 1.04 seconds
Started Jul 03 04:27:20 PM PDT 24
Finished Jul 03 04:27:21 PM PDT 24
Peak memory 200228 kb
Host smart-b93753e9-22cb-4b1d-826c-d16299c5f2ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733031151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1733031151
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3344021792
Short name T570
Test name
Test status
Simulation time 595333706 ps
CPU time 3.4 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:13 PM PDT 24
Peak memory 208520 kb
Host smart-1d750a36-25df-403b-8c43-e1048dc1e8d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344021792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3344021792
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3358699711
Short name T601
Test name
Test status
Simulation time 466325183 ps
CPU time 2.04 seconds
Started Jul 03 04:27:19 PM PDT 24
Finished Jul 03 04:27:21 PM PDT 24
Peak memory 200412 kb
Host smart-b5dfd220-e799-43be-9f58-f8fa886d9af9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358699711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3358699711
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1489140372
Short name T541
Test name
Test status
Simulation time 351580817 ps
CPU time 2.4 seconds
Started Jul 03 04:26:54 PM PDT 24
Finished Jul 03 04:26:57 PM PDT 24
Peak memory 208564 kb
Host smart-9a2d7396-e416-418b-b85e-6bbae7d03939
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489140372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
489140372
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.282807975
Short name T589
Test name
Test status
Simulation time 801662156 ps
CPU time 4.37 seconds
Started Jul 03 04:27:00 PM PDT 24
Finished Jul 03 04:27:04 PM PDT 24
Peak memory 200184 kb
Host smart-360e9bc7-c12d-4bac-a4cf-bda8d0efbc80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282807975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.282807975
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4159786918
Short name T590
Test name
Test status
Simulation time 145906542 ps
CPU time 0.91 seconds
Started Jul 03 04:27:01 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 200232 kb
Host smart-29d58a9f-1b16-4b17-b699-8fa69500bea8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159786918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.4
159786918
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3262073654
Short name T593
Test name
Test status
Simulation time 143361479 ps
CPU time 1.08 seconds
Started Jul 03 04:27:00 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 208612 kb
Host smart-ec133bcb-91ae-4f9e-aa9f-7944c8aff5cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262073654 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3262073654
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1481109342
Short name T114
Test name
Test status
Simulation time 70272547 ps
CPU time 0.77 seconds
Started Jul 03 04:26:52 PM PDT 24
Finished Jul 03 04:26:54 PM PDT 24
Peak memory 200068 kb
Host smart-4a47528d-ba07-49f3-ad0b-a309c297673b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481109342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1481109342
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3026507748
Short name T606
Test name
Test status
Simulation time 94657075 ps
CPU time 1.13 seconds
Started Jul 03 04:27:17 PM PDT 24
Finished Jul 03 04:27:23 PM PDT 24
Peak memory 200320 kb
Host smart-89e35632-402a-4305-9ce8-5ca928fe1636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026507748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3026507748
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.4168294008
Short name T578
Test name
Test status
Simulation time 252790413 ps
CPU time 1.75 seconds
Started Jul 03 04:26:53 PM PDT 24
Finished Jul 03 04:26:56 PM PDT 24
Peak memory 208496 kb
Host smart-1f20268e-43c8-445b-9734-03c9a9e079fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168294008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.4168294008
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4116402629
Short name T130
Test name
Test status
Simulation time 808617618 ps
CPU time 2.79 seconds
Started Jul 03 04:27:05 PM PDT 24
Finished Jul 03 04:27:08 PM PDT 24
Peak memory 200448 kb
Host smart-37634816-74da-4247-b8d6-4412bfc928cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116402629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.4116402629
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1748064594
Short name T540
Test name
Test status
Simulation time 107457971 ps
CPU time 1.34 seconds
Started Jul 03 04:26:53 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 200180 kb
Host smart-93bd252c-7a8f-45aa-bc62-c33ca4192307
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748064594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
748064594
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.65901192
Short name T542
Test name
Test status
Simulation time 484079985 ps
CPU time 5.88 seconds
Started Jul 03 04:27:19 PM PDT 24
Finished Jul 03 04:27:26 PM PDT 24
Peak memory 200384 kb
Host smart-40c88961-c8b4-4ae8-8a3c-a9c68434dcde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65901192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.65901192
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1289364579
Short name T620
Test name
Test status
Simulation time 131653469 ps
CPU time 0.93 seconds
Started Jul 03 04:26:55 PM PDT 24
Finished Jul 03 04:26:56 PM PDT 24
Peak memory 200012 kb
Host smart-cf162f02-8558-4372-952e-21bd9b5b1eb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289364579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
289364579
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2320090159
Short name T95
Test name
Test status
Simulation time 161939118 ps
CPU time 1.34 seconds
Started Jul 03 04:26:59 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 208524 kb
Host smart-963a50e6-94b7-432a-a533-4db6cbb2ac1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320090159 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2320090159
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3426664841
Short name T602
Test name
Test status
Simulation time 64616202 ps
CPU time 0.79 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 200188 kb
Host smart-12b1deca-371a-4fda-b032-75aff83825f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426664841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3426664841
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2525422056
Short name T580
Test name
Test status
Simulation time 127659595 ps
CPU time 1.26 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 200316 kb
Host smart-b596ebdc-9e0b-4852-8272-957378b21937
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525422056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2525422056
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1931568139
Short name T118
Test name
Test status
Simulation time 176532980 ps
CPU time 2.51 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 208496 kb
Host smart-5dfc4cf5-c546-49bd-a0db-f6eda6816988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931568139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1931568139
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2088436403
Short name T122
Test name
Test status
Simulation time 502621690 ps
CPU time 2.01 seconds
Started Jul 03 04:26:52 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 200336 kb
Host smart-02065973-720f-4eb7-a8ee-07dca3bcf9ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088436403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2088436403
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3786364010
Short name T605
Test name
Test status
Simulation time 359448251 ps
CPU time 2.32 seconds
Started Jul 03 04:27:00 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 200256 kb
Host smart-bfff3244-76b9-4fb8-b596-9454daad2c61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786364010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
786364010
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3645842366
Short name T574
Test name
Test status
Simulation time 1549710797 ps
CPU time 8.14 seconds
Started Jul 03 04:26:52 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 200156 kb
Host smart-a83cb578-2f94-4596-8447-a03a9ed26cc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645842366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
645842366
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.853821587
Short name T564
Test name
Test status
Simulation time 119524144 ps
CPU time 0.88 seconds
Started Jul 03 04:27:01 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 199944 kb
Host smart-a401715a-0fdd-4c1b-8825-5b70bb048229
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853821587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.853821587
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2385141490
Short name T90
Test name
Test status
Simulation time 170995048 ps
CPU time 1.48 seconds
Started Jul 03 04:26:49 PM PDT 24
Finished Jul 03 04:26:51 PM PDT 24
Peak memory 208660 kb
Host smart-0caaba42-5d49-4d98-923a-b056c7ba67fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385141490 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2385141490
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3904067334
Short name T557
Test name
Test status
Simulation time 67231713 ps
CPU time 0.82 seconds
Started Jul 03 04:28:43 PM PDT 24
Finished Jul 03 04:28:44 PM PDT 24
Peak memory 200048 kb
Host smart-6ad22ba6-b05c-4f88-8a6c-3a9da6fb2eff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904067334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3904067334
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3203455669
Short name T112
Test name
Test status
Simulation time 129113818 ps
CPU time 1.1 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:08 PM PDT 24
Peak memory 200236 kb
Host smart-9e8e1ee4-d1a9-4509-af98-8ef1182f8e88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203455669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3203455669
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3489002108
Short name T581
Test name
Test status
Simulation time 388690923 ps
CPU time 2.72 seconds
Started Jul 03 04:27:09 PM PDT 24
Finished Jul 03 04:27:13 PM PDT 24
Peak memory 216604 kb
Host smart-4ba55be0-6cc8-41b7-b7c2-8eb54a2a565b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489002108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3489002108
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.909662353
Short name T117
Test name
Test status
Simulation time 475691993 ps
CPU time 1.87 seconds
Started Jul 03 04:26:55 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 200268 kb
Host smart-9370d2e7-25f2-49a4-9038-3c111afab3f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909662353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
909662353
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2692201305
Short name T562
Test name
Test status
Simulation time 112023854 ps
CPU time 0.91 seconds
Started Jul 03 04:26:52 PM PDT 24
Finished Jul 03 04:26:53 PM PDT 24
Peak memory 200332 kb
Host smart-4b79cec1-4e8e-4139-ba28-7da058ec44b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692201305 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2692201305
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.581338069
Short name T573
Test name
Test status
Simulation time 88154517 ps
CPU time 0.87 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 200192 kb
Host smart-9e72f272-b743-497e-a754-71bd22be295b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581338069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.581338069
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2348277371
Short name T600
Test name
Test status
Simulation time 111731441 ps
CPU time 1.01 seconds
Started Jul 03 04:26:55 PM PDT 24
Finished Jul 03 04:26:56 PM PDT 24
Peak memory 200224 kb
Host smart-33918178-7ebf-4edf-ba58-e97ccd7742ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348277371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2348277371
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2167446382
Short name T616
Test name
Test status
Simulation time 556823564 ps
CPU time 3.41 seconds
Started Jul 03 04:27:05 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 208404 kb
Host smart-ea5b2dbd-cd93-4335-a7ff-ee1877e585c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167446382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2167446382
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.621288368
Short name T569
Test name
Test status
Simulation time 2292516218 ps
CPU time 5.26 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 200456 kb
Host smart-a2d32c89-cf91-49b8-a7ff-e9dd48a97df4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621288368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
621288368
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1718507124
Short name T550
Test name
Test status
Simulation time 183480879 ps
CPU time 1.19 seconds
Started Jul 03 04:27:03 PM PDT 24
Finished Jul 03 04:27:05 PM PDT 24
Peak memory 208444 kb
Host smart-de0a7b9f-e9cd-42ad-ae91-94e2b022d544
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718507124 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1718507124
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.916503937
Short name T558
Test name
Test status
Simulation time 84206766 ps
CPU time 0.84 seconds
Started Jul 03 04:27:35 PM PDT 24
Finished Jul 03 04:27:37 PM PDT 24
Peak memory 200212 kb
Host smart-efba1279-2bdc-4592-9c50-534ac601b94c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916503937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.916503937
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1257724839
Short name T62
Test name
Test status
Simulation time 128861290 ps
CPU time 1.42 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:11 PM PDT 24
Peak memory 200368 kb
Host smart-638b1d83-5097-4db6-9c48-2bb8576a4430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257724839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1257724839
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1596963040
Short name T66
Test name
Test status
Simulation time 422368519 ps
CPU time 3.05 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:11 PM PDT 24
Peak memory 208496 kb
Host smart-3cb019c1-9a9d-4daf-be84-0c1d2cae46f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596963040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1596963040
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.973110009
Short name T561
Test name
Test status
Simulation time 421916364 ps
CPU time 1.81 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:07 PM PDT 24
Peak memory 200424 kb
Host smart-fd2c3109-bbb3-477c-888e-700dbc2f47e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973110009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
973110009
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2865949776
Short name T610
Test name
Test status
Simulation time 181235517 ps
CPU time 1.14 seconds
Started Jul 03 04:27:14 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 200176 kb
Host smart-59275874-926b-4035-aa0c-42ddc526f31a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865949776 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2865949776
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3680852383
Short name T543
Test name
Test status
Simulation time 56412143 ps
CPU time 0.73 seconds
Started Jul 03 04:27:01 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 200096 kb
Host smart-4fc3a8da-265e-4466-ba81-0d82d966ad03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680852383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3680852383
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3275836348
Short name T617
Test name
Test status
Simulation time 128291079 ps
CPU time 1.23 seconds
Started Jul 03 04:26:52 PM PDT 24
Finished Jul 03 04:26:54 PM PDT 24
Peak memory 200180 kb
Host smart-aaf979d9-f0af-4689-82fb-5a6e97b78d77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275836348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3275836348
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3151074837
Short name T553
Test name
Test status
Simulation time 400616118 ps
CPU time 2.93 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:17 PM PDT 24
Peak memory 208564 kb
Host smart-e1786684-cf85-4eb6-8008-ed9a8e662fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151074837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3151074837
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3545009000
Short name T68
Test name
Test status
Simulation time 774913506 ps
CPU time 2.86 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 200240 kb
Host smart-2c11467c-8292-401a-a683-97e93d67af05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545009000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3545009000
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1764909909
Short name T92
Test name
Test status
Simulation time 129197972 ps
CPU time 1.06 seconds
Started Jul 03 04:27:26 PM PDT 24
Finished Jul 03 04:27:27 PM PDT 24
Peak memory 200728 kb
Host smart-05bd3f6f-b317-4c66-b300-ec12ed458253
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764909909 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1764909909
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2794153786
Short name T609
Test name
Test status
Simulation time 73748195 ps
CPU time 0.82 seconds
Started Jul 03 04:27:03 PM PDT 24
Finished Jul 03 04:27:05 PM PDT 24
Peak memory 199996 kb
Host smart-5dd90d64-c304-42d3-ac55-966ea41edab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794153786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2794153786
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.710540651
Short name T615
Test name
Test status
Simulation time 114320573 ps
CPU time 1.25 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 200352 kb
Host smart-1cb064f9-03ba-4132-88d0-4953adc3d845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710540651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.710540651
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3849931757
Short name T124
Test name
Test status
Simulation time 115327023 ps
CPU time 1.58 seconds
Started Jul 03 04:27:01 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 208604 kb
Host smart-5e4f81cb-deeb-4468-9269-581f663dae30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849931757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3849931757
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4157218001
Short name T588
Test name
Test status
Simulation time 460442361 ps
CPU time 1.93 seconds
Started Jul 03 04:27:33 PM PDT 24
Finished Jul 03 04:27:35 PM PDT 24
Peak memory 200344 kb
Host smart-be184e52-ece7-4aaf-8698-0b121767cb78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157218001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.4157218001
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3569917614
Short name T592
Test name
Test status
Simulation time 124982231 ps
CPU time 0.9 seconds
Started Jul 03 04:27:24 PM PDT 24
Finished Jul 03 04:27:26 PM PDT 24
Peak memory 200180 kb
Host smart-35c6c697-003d-4c5f-b6c1-884090f871e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569917614 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3569917614
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.706406840
Short name T552
Test name
Test status
Simulation time 75483824 ps
CPU time 0.87 seconds
Started Jul 03 04:27:05 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 200216 kb
Host smart-a5607e59-f9c9-4148-afe5-cc0b7b1c9226
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706406840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.706406840
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3720372721
Short name T544
Test name
Test status
Simulation time 86826389 ps
CPU time 0.98 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 200168 kb
Host smart-00232534-453a-447a-ba09-b4a0f99e5583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720372721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3720372721
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.574388396
Short name T614
Test name
Test status
Simulation time 503580921 ps
CPU time 3.34 seconds
Started Jul 03 04:27:02 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 208604 kb
Host smart-e452d8c8-51e4-4857-aa19-8295b870052f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574388396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.574388396
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3609530785
Short name T298
Test name
Test status
Simulation time 72149478 ps
CPU time 0.77 seconds
Started Jul 03 04:27:17 PM PDT 24
Finished Jul 03 04:27:18 PM PDT 24
Peak memory 199740 kb
Host smart-de36bd11-2b19-4c4f-96e0-85c4c8dc2c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609530785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3609530785
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.182994310
Short name T368
Test name
Test status
Simulation time 1892536814 ps
CPU time 6.91 seconds
Started Jul 03 04:27:14 PM PDT 24
Finished Jul 03 04:27:22 PM PDT 24
Peak memory 221584 kb
Host smart-365593fb-b2d8-48f6-8408-d18efbc294c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182994310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.182994310
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2100025906
Short name T466
Test name
Test status
Simulation time 244488608 ps
CPU time 1.01 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 217480 kb
Host smart-2983729b-5a68-415f-bb93-c385112551e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100025906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2100025906
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.853031085
Short name T255
Test name
Test status
Simulation time 211732445 ps
CPU time 0.88 seconds
Started Jul 03 04:27:14 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 199848 kb
Host smart-6730a603-f285-4dfe-bebb-52b9d68e7588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853031085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.853031085
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2310805038
Short name T102
Test name
Test status
Simulation time 967918893 ps
CPU time 4.59 seconds
Started Jul 03 04:27:31 PM PDT 24
Finished Jul 03 04:27:35 PM PDT 24
Peak memory 200684 kb
Host smart-cdbbf037-1074-4d86-bf47-354646b48fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310805038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2310805038
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2334740228
Short name T181
Test name
Test status
Simulation time 101577310 ps
CPU time 0.98 seconds
Started Jul 03 04:27:22 PM PDT 24
Finished Jul 03 04:27:23 PM PDT 24
Peak memory 200012 kb
Host smart-1fb03a23-5a6c-45b8-8455-5c63cbc75505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334740228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2334740228
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1035245149
Short name T265
Test name
Test status
Simulation time 256360453 ps
CPU time 1.38 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 200248 kb
Host smart-b9f6a5d7-b1a9-4bdc-836c-092f496f801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035245149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1035245149
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3513401166
Short name T210
Test name
Test status
Simulation time 5646370922 ps
CPU time 19.92 seconds
Started Jul 03 04:27:00 PM PDT 24
Finished Jul 03 04:27:21 PM PDT 24
Peak memory 208480 kb
Host smart-a62f2357-fcd8-4ee5-b203-410450fcf23b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513401166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3513401166
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.4285440387
Short name T128
Test name
Test status
Simulation time 411824513 ps
CPU time 2.32 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:07 PM PDT 24
Peak memory 208264 kb
Host smart-d7228588-263b-413e-82ca-90ca859cdfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285440387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.4285440387
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1906934490
Short name T84
Test name
Test status
Simulation time 151237893 ps
CPU time 1.09 seconds
Started Jul 03 04:27:21 PM PDT 24
Finished Jul 03 04:27:23 PM PDT 24
Peak memory 200016 kb
Host smart-419f589d-e393-4ede-bfb6-00f40ccab271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906934490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1906934490
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1667305690
Short name T356
Test name
Test status
Simulation time 71166134 ps
CPU time 0.74 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:13 PM PDT 24
Peak memory 199848 kb
Host smart-b74591ee-e817-4c7e-a1f6-6b9e327bc98e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667305690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1667305690
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2394068353
Short name T29
Test name
Test status
Simulation time 1230043373 ps
CPU time 5.35 seconds
Started Jul 03 04:27:33 PM PDT 24
Finished Jul 03 04:27:38 PM PDT 24
Peak memory 217736 kb
Host smart-f0913234-c1da-4993-bacd-2956b21b8521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394068353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2394068353
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3244862227
Short name T414
Test name
Test status
Simulation time 246279020 ps
CPU time 1.06 seconds
Started Jul 03 04:27:18 PM PDT 24
Finished Jul 03 04:27:20 PM PDT 24
Peak memory 217360 kb
Host smart-12bee142-6d9a-424d-9dd7-ae7bd23a0572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244862227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3244862227
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2839595776
Short name T491
Test name
Test status
Simulation time 151824015 ps
CPU time 0.85 seconds
Started Jul 03 04:27:25 PM PDT 24
Finished Jul 03 04:27:26 PM PDT 24
Peak memory 199824 kb
Host smart-95000d31-2ddb-4568-ad63-2c47a279af5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839595776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2839595776
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3204832553
Short name T427
Test name
Test status
Simulation time 1867177234 ps
CPU time 6.57 seconds
Started Jul 03 04:27:19 PM PDT 24
Finished Jul 03 04:27:26 PM PDT 24
Peak memory 200360 kb
Host smart-42d0d362-cf85-4a9a-a862-0696e9ec5d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204832553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3204832553
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.895478646
Short name T70
Test name
Test status
Simulation time 8473561521 ps
CPU time 12.3 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:24 PM PDT 24
Peak memory 217096 kb
Host smart-d12967ef-83bb-434f-a72e-ac2a6aa366b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895478646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.895478646
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.88936077
Short name T293
Test name
Test status
Simulation time 123358210 ps
CPU time 1.1 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:08 PM PDT 24
Peak memory 200296 kb
Host smart-607f5981-5bbd-4dbe-94d5-2236bdfee22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88936077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.88936077
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1376026856
Short name T352
Test name
Test status
Simulation time 5213571645 ps
CPU time 21.48 seconds
Started Jul 03 04:27:01 PM PDT 24
Finished Jul 03 04:27:23 PM PDT 24
Peak memory 210344 kb
Host smart-548b2afa-cae9-4b9c-bc5f-33553399dbc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376026856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1376026856
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3563865371
Short name T437
Test name
Test status
Simulation time 121074222 ps
CPU time 1.5 seconds
Started Jul 03 04:27:18 PM PDT 24
Finished Jul 03 04:27:20 PM PDT 24
Peak memory 199984 kb
Host smart-9d5e12ef-7e38-4459-b19b-62d802f408c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563865371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3563865371
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1633418071
Short name T201
Test name
Test status
Simulation time 88486747 ps
CPU time 0.95 seconds
Started Jul 03 04:27:36 PM PDT 24
Finished Jul 03 04:27:37 PM PDT 24
Peak memory 200080 kb
Host smart-a644fd01-6e20-4cc4-8639-8dbf305d4290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633418071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1633418071
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2998490000
Short name T461
Test name
Test status
Simulation time 1242707067 ps
CPU time 5.53 seconds
Started Jul 03 04:27:21 PM PDT 24
Finished Jul 03 04:27:27 PM PDT 24
Peak memory 221644 kb
Host smart-880eb22f-b04e-4db8-94d2-527819ef1c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998490000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2998490000
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1065210953
Short name T305
Test name
Test status
Simulation time 243916972 ps
CPU time 1.11 seconds
Started Jul 03 04:27:28 PM PDT 24
Finished Jul 03 04:27:29 PM PDT 24
Peak memory 217400 kb
Host smart-951f083c-9b27-400c-bfe9-764f2003119e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065210953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1065210953
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.212911695
Short name T476
Test name
Test status
Simulation time 208374148 ps
CPU time 0.84 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:17 PM PDT 24
Peak memory 199808 kb
Host smart-63fa2c18-6632-4e9d-b468-a45fce5311d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212911695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.212911695
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2584729281
Short name T106
Test name
Test status
Simulation time 1749882692 ps
CPU time 6.95 seconds
Started Jul 03 04:27:25 PM PDT 24
Finished Jul 03 04:27:32 PM PDT 24
Peak memory 200296 kb
Host smart-4b3bd15e-bac9-49e4-be88-634dc36bd46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584729281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2584729281
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4274058858
Short name T439
Test name
Test status
Simulation time 98162716 ps
CPU time 0.97 seconds
Started Jul 03 04:27:43 PM PDT 24
Finished Jul 03 04:27:45 PM PDT 24
Peak memory 199992 kb
Host smart-4c4a2c64-3720-418d-913d-abfcd236c986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274058858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4274058858
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2335925698
Short name T219
Test name
Test status
Simulation time 120321782 ps
CPU time 1.16 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:13 PM PDT 24
Peak memory 200272 kb
Host smart-8df24937-7eb7-4f40-880e-9c2257657e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335925698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2335925698
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2458257150
Short name T243
Test name
Test status
Simulation time 1632130617 ps
CPU time 7.54 seconds
Started Jul 03 04:27:14 PM PDT 24
Finished Jul 03 04:27:23 PM PDT 24
Peak memory 200316 kb
Host smart-751a2e87-ee87-426e-9f03-572f1d061c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458257150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2458257150
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.777106519
Short name T241
Test name
Test status
Simulation time 483539781 ps
CPU time 2.33 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 199704 kb
Host smart-532b554e-d340-4393-b573-a015a6a8afb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777106519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.777106519
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.576526121
Short name T441
Test name
Test status
Simulation time 212121084 ps
CPU time 1.26 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 199964 kb
Host smart-f06e0c23-5556-4296-8af2-76b9a9fa0780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576526121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.576526121
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.112130014
Short name T275
Test name
Test status
Simulation time 71030152 ps
CPU time 0.8 seconds
Started Jul 03 04:27:36 PM PDT 24
Finished Jul 03 04:27:37 PM PDT 24
Peak memory 199896 kb
Host smart-acc96190-dd15-4b7d-a3fe-03b3f69b9f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112130014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.112130014
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2812421835
Short name T50
Test name
Test status
Simulation time 1218672552 ps
CPU time 5.45 seconds
Started Jul 03 04:27:31 PM PDT 24
Finished Jul 03 04:27:37 PM PDT 24
Peak memory 217780 kb
Host smart-bedcc4a9-d207-4f34-99f2-1d68e8fede6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812421835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2812421835
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.4185513424
Short name T39
Test name
Test status
Simulation time 247207732 ps
CPU time 1.03 seconds
Started Jul 03 04:27:17 PM PDT 24
Finished Jul 03 04:27:23 PM PDT 24
Peak memory 217396 kb
Host smart-193ed79a-f3b1-42c9-9cbc-ef16d9facc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185513424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.4185513424
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2874099265
Short name T75
Test name
Test status
Simulation time 187192601 ps
CPU time 0.88 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 199744 kb
Host smart-c64cbd7b-4b73-47bd-9403-ec1078c9789d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874099265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2874099265
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.888171616
Short name T330
Test name
Test status
Simulation time 803586500 ps
CPU time 3.76 seconds
Started Jul 03 04:27:14 PM PDT 24
Finished Jul 03 04:27:19 PM PDT 24
Peak memory 200276 kb
Host smart-a3f7bda1-6a01-4a65-a514-0183d87f478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888171616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.888171616
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3510884539
Short name T463
Test name
Test status
Simulation time 177653383 ps
CPU time 1.17 seconds
Started Jul 03 04:27:44 PM PDT 24
Finished Jul 03 04:27:45 PM PDT 24
Peak memory 200064 kb
Host smart-30d8d9a5-36ec-4b59-91f5-e94d49ee6206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510884539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3510884539
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2030149033
Short name T413
Test name
Test status
Simulation time 123872638 ps
CPU time 1.31 seconds
Started Jul 03 04:28:20 PM PDT 24
Finished Jul 03 04:28:24 PM PDT 24
Peak memory 199196 kb
Host smart-b1204cf8-c0ee-4c16-9aea-bbf71a60f3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030149033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2030149033
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2427624348
Short name T341
Test name
Test status
Simulation time 8629310687 ps
CPU time 27.2 seconds
Started Jul 03 04:27:14 PM PDT 24
Finished Jul 03 04:27:42 PM PDT 24
Peak memory 200368 kb
Host smart-17ce3acf-ba6e-4e4d-b558-7fe93d5cbce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427624348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2427624348
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.985201214
Short name T165
Test name
Test status
Simulation time 328027749 ps
CPU time 2.03 seconds
Started Jul 03 04:27:47 PM PDT 24
Finished Jul 03 04:27:50 PM PDT 24
Peak memory 208176 kb
Host smart-3245b8f6-6a97-4c8c-a4e8-210d39404519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985201214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.985201214
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3529796680
Short name T286
Test name
Test status
Simulation time 89868805 ps
CPU time 0.82 seconds
Started Jul 03 04:27:30 PM PDT 24
Finished Jul 03 04:27:31 PM PDT 24
Peak memory 200080 kb
Host smart-c0ab8b5f-b3fa-4882-be43-2806577c5230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529796680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3529796680
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1945805403
Short name T372
Test name
Test status
Simulation time 57696000 ps
CPU time 0.73 seconds
Started Jul 03 04:28:56 PM PDT 24
Finished Jul 03 04:28:57 PM PDT 24
Peak memory 199736 kb
Host smart-88bb8b21-b63e-4ee0-83a5-43f26cd0a458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945805403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1945805403
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.4058412752
Short name T33
Test name
Test status
Simulation time 2159973650 ps
CPU time 7.97 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:19 PM PDT 24
Peak memory 217552 kb
Host smart-d9201fbb-90f8-4990-8a71-a04a4fa4272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058412752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.4058412752
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.683602856
Short name T502
Test name
Test status
Simulation time 271612423 ps
CPU time 1.07 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 217368 kb
Host smart-8086077d-613a-4b66-9fed-6342b09f38f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683602856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.683602856
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2723436218
Short name T209
Test name
Test status
Simulation time 146948867 ps
CPU time 0.83 seconds
Started Jul 03 04:28:53 PM PDT 24
Finished Jul 03 04:28:54 PM PDT 24
Peak memory 199812 kb
Host smart-34080fe4-2b58-432c-a379-da120a206706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723436218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2723436218
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.604347082
Short name T472
Test name
Test status
Simulation time 1589159638 ps
CPU time 5.33 seconds
Started Jul 03 04:28:39 PM PDT 24
Finished Jul 03 04:28:55 PM PDT 24
Peak memory 200136 kb
Host smart-a0cdb23a-0151-4df3-9381-c7fd11fbd5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604347082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.604347082
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3187627113
Short name T361
Test name
Test status
Simulation time 148531497 ps
CPU time 1.16 seconds
Started Jul 03 04:27:36 PM PDT 24
Finished Jul 03 04:27:38 PM PDT 24
Peak memory 200036 kb
Host smart-7c9992d2-c721-4385-868c-1ec004ca72e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187627113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3187627113
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2667931816
Short name T334
Test name
Test status
Simulation time 197954166 ps
CPU time 1.34 seconds
Started Jul 03 04:27:34 PM PDT 24
Finished Jul 03 04:27:36 PM PDT 24
Peak memory 200272 kb
Host smart-e14bd36e-30a7-4447-8362-f08c8f06de54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667931816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2667931816
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2849638535
Short name T450
Test name
Test status
Simulation time 282035362 ps
CPU time 2.04 seconds
Started Jul 03 04:27:13 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 208396 kb
Host smart-8d5fdaf1-8fee-47c6-832f-d3196eca5c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849638535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2849638535
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3695021025
Short name T486
Test name
Test status
Simulation time 323368314 ps
CPU time 2.07 seconds
Started Jul 03 04:27:18 PM PDT 24
Finished Jul 03 04:27:21 PM PDT 24
Peak memory 199988 kb
Host smart-5d6d5e3b-9606-4a21-bc37-a1dc6f1d71dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695021025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3695021025
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3472915539
Short name T494
Test name
Test status
Simulation time 79731750 ps
CPU time 0.75 seconds
Started Jul 03 04:28:44 PM PDT 24
Finished Jul 03 04:28:45 PM PDT 24
Peak memory 199928 kb
Host smart-86820017-f9ff-46c5-ab95-6d8d3744f446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472915539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3472915539
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3028506408
Short name T294
Test name
Test status
Simulation time 60039014 ps
CPU time 0.72 seconds
Started Jul 03 04:27:32 PM PDT 24
Finished Jul 03 04:27:33 PM PDT 24
Peak memory 199812 kb
Host smart-0f98f2a1-5b0a-4f35-b689-ee6a80392b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028506408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3028506408
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2294117886
Short name T332
Test name
Test status
Simulation time 1230829080 ps
CPU time 5.28 seconds
Started Jul 03 04:27:36 PM PDT 24
Finished Jul 03 04:27:42 PM PDT 24
Peak memory 217660 kb
Host smart-b71a3be2-0d27-49b1-add4-d686f260d550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294117886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2294117886
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1206017900
Short name T403
Test name
Test status
Simulation time 88863574 ps
CPU time 0.7 seconds
Started Jul 03 04:27:20 PM PDT 24
Finished Jul 03 04:27:21 PM PDT 24
Peak memory 199840 kb
Host smart-b044dea6-c94b-4931-9447-7fca308f1f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206017900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1206017900
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1835875933
Short name T101
Test name
Test status
Simulation time 2178457556 ps
CPU time 8.43 seconds
Started Jul 03 04:27:18 PM PDT 24
Finished Jul 03 04:27:27 PM PDT 24
Peak memory 200280 kb
Host smart-d0b5179e-de36-4bc4-8ca4-6f1b65d13fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835875933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1835875933
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2592616063
Short name T252
Test name
Test status
Simulation time 149078567 ps
CPU time 1.11 seconds
Started Jul 03 04:28:52 PM PDT 24
Finished Jul 03 04:28:54 PM PDT 24
Peak memory 200012 kb
Host smart-351f4ccb-3c47-4062-9f4d-3839914bfcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592616063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2592616063
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1535772972
Short name T170
Test name
Test status
Simulation time 114161507 ps
CPU time 1.07 seconds
Started Jul 03 04:27:16 PM PDT 24
Finished Jul 03 04:27:17 PM PDT 24
Peak memory 200224 kb
Host smart-352caad3-73d4-4f83-b8d6-24e1d648b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535772972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1535772972
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1716402907
Short name T406
Test name
Test status
Simulation time 125622584 ps
CPU time 1.45 seconds
Started Jul 03 04:27:13 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 208260 kb
Host smart-b4f9079f-d5c0-4521-a3e9-149b5f80ad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716402907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1716402907
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1998602711
Short name T169
Test name
Test status
Simulation time 193407896 ps
CPU time 1.2 seconds
Started Jul 03 04:28:39 PM PDT 24
Finished Jul 03 04:28:41 PM PDT 24
Peak memory 199908 kb
Host smart-4a0b8060-33d5-46e8-b380-a4b6c4c6c4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998602711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1998602711
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2365360391
Short name T140
Test name
Test status
Simulation time 99494972 ps
CPU time 0.91 seconds
Started Jul 03 04:27:13 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 199752 kb
Host smart-39b14209-51eb-4909-8f1e-989627b47e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365360391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2365360391
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.4006735872
Short name T76
Test name
Test status
Simulation time 1229202544 ps
CPU time 5.67 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 217800 kb
Host smart-770de905-b0f5-446a-ad5a-dae1a684a0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006735872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.4006735872
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3722189075
Short name T380
Test name
Test status
Simulation time 244777112 ps
CPU time 1.11 seconds
Started Jul 03 04:28:51 PM PDT 24
Finished Jul 03 04:28:53 PM PDT 24
Peak memory 217328 kb
Host smart-0b13c9fd-f340-4555-a3b0-c950a728d078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722189075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3722189075
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2800226653
Short name T191
Test name
Test status
Simulation time 1397840698 ps
CPU time 5.89 seconds
Started Jul 03 04:27:35 PM PDT 24
Finished Jul 03 04:27:42 PM PDT 24
Peak memory 200296 kb
Host smart-8cb279b4-50bc-4c23-b7b0-72f488db988d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800226653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2800226653
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2583148210
Short name T417
Test name
Test status
Simulation time 174915416 ps
CPU time 1.17 seconds
Started Jul 03 04:27:35 PM PDT 24
Finished Jul 03 04:27:37 PM PDT 24
Peak memory 200032 kb
Host smart-7d85a1d2-bdc3-443c-af98-ed0c6f5812bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583148210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2583148210
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2912250027
Short name T411
Test name
Test status
Simulation time 113240397 ps
CPU time 1.21 seconds
Started Jul 03 04:27:24 PM PDT 24
Finished Jul 03 04:27:25 PM PDT 24
Peak memory 200276 kb
Host smart-d09f8d34-68d9-4f8c-a555-d793e2826b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912250027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2912250027
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2182456613
Short name T188
Test name
Test status
Simulation time 1305459454 ps
CPU time 5.7 seconds
Started Jul 03 04:28:49 PM PDT 24
Finished Jul 03 04:28:55 PM PDT 24
Peak memory 200196 kb
Host smart-00c0f47d-2d96-4231-80a4-8a8c3cca6966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182456613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2182456613
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2753419338
Short name T446
Test name
Test status
Simulation time 253994764 ps
CPU time 1.83 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:11 PM PDT 24
Peak memory 199552 kb
Host smart-40a9313d-1125-4192-95b9-abe9cb10292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753419338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2753419338
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.814475091
Short name T300
Test name
Test status
Simulation time 75949227 ps
CPU time 0.8 seconds
Started Jul 03 04:28:52 PM PDT 24
Finished Jul 03 04:28:53 PM PDT 24
Peak memory 199952 kb
Host smart-babdc468-594b-41c8-8c01-02bfa472dec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814475091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.814475091
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2590105311
Short name T349
Test name
Test status
Simulation time 72860810 ps
CPU time 0.77 seconds
Started Jul 03 04:27:13 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 199796 kb
Host smart-782569a4-4a04-4656-851c-8b93aa8ba47b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590105311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2590105311
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1513108920
Short name T354
Test name
Test status
Simulation time 245656199 ps
CPU time 1 seconds
Started Jul 03 04:27:24 PM PDT 24
Finished Jul 03 04:27:26 PM PDT 24
Peak memory 217740 kb
Host smart-b65b9da5-d306-4d43-8f58-dcb30e5775b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513108920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1513108920
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1561487655
Short name T192
Test name
Test status
Simulation time 150197438 ps
CPU time 0.81 seconds
Started Jul 03 04:27:18 PM PDT 24
Finished Jul 03 04:27:20 PM PDT 24
Peak memory 199796 kb
Host smart-cbd7afdd-d8b2-4a30-bbf5-7a9cc7a22eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561487655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1561487655
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.414513657
Short name T468
Test name
Test status
Simulation time 924126877 ps
CPU time 4.21 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:17 PM PDT 24
Peak memory 200344 kb
Host smart-6dabfab4-9108-49de-be7d-936184c8bf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414513657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.414513657
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3016982267
Short name T8
Test name
Test status
Simulation time 97032920 ps
CPU time 0.94 seconds
Started Jul 03 04:27:21 PM PDT 24
Finished Jul 03 04:27:22 PM PDT 24
Peak memory 199992 kb
Host smart-f691c815-e76f-449d-8809-bb95f48c4c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016982267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3016982267
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1029646509
Short name T538
Test name
Test status
Simulation time 123205697 ps
CPU time 1.14 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 200176 kb
Host smart-d1e5e30f-0690-4358-9b28-2f9c88b5bc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029646509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1029646509
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3080045296
Short name T374
Test name
Test status
Simulation time 9000854564 ps
CPU time 32.31 seconds
Started Jul 03 04:27:38 PM PDT 24
Finished Jul 03 04:28:10 PM PDT 24
Peak memory 200380 kb
Host smart-039872a5-7eda-4a86-aab1-baf0d5ec127b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080045296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3080045296
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.320809188
Short name T207
Test name
Test status
Simulation time 129908617 ps
CPU time 1.66 seconds
Started Jul 03 04:27:24 PM PDT 24
Finished Jul 03 04:27:27 PM PDT 24
Peak memory 208328 kb
Host smart-462f188e-c20b-409e-a365-7a3d16574c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320809188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.320809188
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3362168177
Short name T271
Test name
Test status
Simulation time 113941333 ps
CPU time 1.01 seconds
Started Jul 03 04:27:27 PM PDT 24
Finished Jul 03 04:27:29 PM PDT 24
Peak memory 200040 kb
Host smart-7c13238b-827c-44b6-be34-80be88dc7a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362168177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3362168177
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3665553221
Short name T348
Test name
Test status
Simulation time 80482461 ps
CPU time 0.82 seconds
Started Jul 03 04:27:33 PM PDT 24
Finished Jul 03 04:27:34 PM PDT 24
Peak memory 199896 kb
Host smart-46e47462-13e2-41b9-b273-7f079a9a980e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665553221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3665553221
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1905762827
Short name T529
Test name
Test status
Simulation time 1229214724 ps
CPU time 5.35 seconds
Started Jul 03 04:27:16 PM PDT 24
Finished Jul 03 04:27:22 PM PDT 24
Peak memory 217072 kb
Host smart-bf4869e0-af3f-446b-8612-23b94da3aa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905762827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1905762827
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.798642265
Short name T142
Test name
Test status
Simulation time 245407578 ps
CPU time 1.07 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 217416 kb
Host smart-9c88a14f-c685-4737-baa3-c77159c90520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798642265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.798642265
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1544976637
Short name T220
Test name
Test status
Simulation time 149398942 ps
CPU time 0.81 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 199580 kb
Host smart-f2ceaefd-20f1-4c9a-bca6-b2a1585d4342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544976637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1544976637
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1004048200
Short name T38
Test name
Test status
Simulation time 1025406363 ps
CPU time 4.53 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:18 PM PDT 24
Peak memory 200156 kb
Host smart-1d07cb8c-b01a-4959-b01f-b32773c22eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004048200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1004048200
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.4254605458
Short name T481
Test name
Test status
Simulation time 100749760 ps
CPU time 0.93 seconds
Started Jul 03 04:27:32 PM PDT 24
Finished Jul 03 04:27:33 PM PDT 24
Peak memory 200076 kb
Host smart-cf0387a0-100d-4868-b06c-caacb18859e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254605458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.4254605458
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2537233249
Short name T535
Test name
Test status
Simulation time 121238134 ps
CPU time 1.12 seconds
Started Jul 03 04:27:28 PM PDT 24
Finished Jul 03 04:27:30 PM PDT 24
Peak memory 200576 kb
Host smart-517cbb3b-57d2-49a5-9f01-ff62c08943d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537233249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2537233249
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.191998255
Short name T493
Test name
Test status
Simulation time 9498866291 ps
CPU time 33.7 seconds
Started Jul 03 04:27:24 PM PDT 24
Finished Jul 03 04:27:58 PM PDT 24
Peak memory 200264 kb
Host smart-01393f35-52a0-4462-bf4d-93eebae6410c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191998255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.191998255
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.4005753241
Short name T178
Test name
Test status
Simulation time 145414360 ps
CPU time 1.74 seconds
Started Jul 03 04:27:36 PM PDT 24
Finished Jul 03 04:27:39 PM PDT 24
Peak memory 200068 kb
Host smart-aaf519fb-82f6-4c3a-89cf-3cc9395621cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005753241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4005753241
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.578137177
Short name T434
Test name
Test status
Simulation time 292321946 ps
CPU time 1.66 seconds
Started Jul 03 04:27:28 PM PDT 24
Finished Jul 03 04:27:30 PM PDT 24
Peak memory 200272 kb
Host smart-0a5fff97-d146-4551-b347-c5f285b2bc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578137177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.578137177
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.714030788
Short name T3
Test name
Test status
Simulation time 59740418 ps
CPU time 0.76 seconds
Started Jul 03 04:27:42 PM PDT 24
Finished Jul 03 04:27:43 PM PDT 24
Peak memory 199740 kb
Host smart-9ecb4322-d8cf-4d67-bf65-38893f8c84b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714030788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.714030788
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2709250474
Short name T245
Test name
Test status
Simulation time 1218131969 ps
CPU time 5.61 seconds
Started Jul 03 04:27:35 PM PDT 24
Finished Jul 03 04:27:41 PM PDT 24
Peak memory 217480 kb
Host smart-156267a2-de52-4e41-ba86-5329207460e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709250474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2709250474
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3190289309
Short name T141
Test name
Test status
Simulation time 243743604 ps
CPU time 1.07 seconds
Started Jul 03 04:27:27 PM PDT 24
Finished Jul 03 04:27:29 PM PDT 24
Peak memory 217328 kb
Host smart-aa431ead-2603-4108-b2a1-c1b498e83fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190289309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3190289309
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1086032084
Short name T297
Test name
Test status
Simulation time 100063360 ps
CPU time 0.8 seconds
Started Jul 03 04:27:35 PM PDT 24
Finished Jul 03 04:27:37 PM PDT 24
Peak memory 199900 kb
Host smart-7793a1c0-3819-4157-a021-b3655ee10b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086032084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1086032084
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2727051709
Short name T312
Test name
Test status
Simulation time 1575161306 ps
CPU time 5.67 seconds
Started Jul 03 04:27:19 PM PDT 24
Finished Jul 03 04:27:25 PM PDT 24
Peak memory 200276 kb
Host smart-2b7c185f-4131-4e83-8a82-a6923aca3bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727051709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2727051709
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1600887330
Short name T449
Test name
Test status
Simulation time 141440131 ps
CPU time 1.02 seconds
Started Jul 03 04:27:29 PM PDT 24
Finished Jul 03 04:27:31 PM PDT 24
Peak memory 199964 kb
Host smart-a26fccee-db25-41dc-bb0a-23023eda2e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600887330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1600887330
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.851639208
Short name T401
Test name
Test status
Simulation time 201489514 ps
CPU time 1.51 seconds
Started Jul 03 04:27:38 PM PDT 24
Finished Jul 03 04:27:40 PM PDT 24
Peak memory 200260 kb
Host smart-0163c596-445d-4fde-a29b-545ffbaeb484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851639208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.851639208
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1127517092
Short name T456
Test name
Test status
Simulation time 5892248447 ps
CPU time 25.26 seconds
Started Jul 03 04:28:52 PM PDT 24
Finished Jul 03 04:29:17 PM PDT 24
Peak memory 200268 kb
Host smart-a8eee40f-f712-48ce-9369-8b31f9cff314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127517092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1127517092
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.368328265
Short name T419
Test name
Test status
Simulation time 434037946 ps
CPU time 2.11 seconds
Started Jul 03 04:28:47 PM PDT 24
Finished Jul 03 04:28:49 PM PDT 24
Peak memory 208184 kb
Host smart-016a42a0-00bc-489b-a88b-5f8daf0f56d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368328265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.368328265
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3709725231
Short name T274
Test name
Test status
Simulation time 171698852 ps
CPU time 1.06 seconds
Started Jul 03 04:27:17 PM PDT 24
Finished Jul 03 04:27:18 PM PDT 24
Peak memory 200076 kb
Host smart-8efa6d99-c080-457f-a886-f89173ca347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709725231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3709725231
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3702462522
Short name T145
Test name
Test status
Simulation time 82864427 ps
CPU time 0.83 seconds
Started Jul 03 04:27:30 PM PDT 24
Finished Jul 03 04:27:32 PM PDT 24
Peak memory 199832 kb
Host smart-b0596783-ce8f-46d3-8b73-c92e9465b3c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702462522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3702462522
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3854805224
Short name T395
Test name
Test status
Simulation time 2189288682 ps
CPU time 8.23 seconds
Started Jul 03 04:27:43 PM PDT 24
Finished Jul 03 04:27:52 PM PDT 24
Peak memory 221608 kb
Host smart-73d096cb-d6e1-48cb-a751-c0b2f5e2dc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854805224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3854805224
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2732269185
Short name T281
Test name
Test status
Simulation time 244951828 ps
CPU time 1.24 seconds
Started Jul 03 04:27:41 PM PDT 24
Finished Jul 03 04:27:42 PM PDT 24
Peak memory 217348 kb
Host smart-d3afe8c3-f5af-4da9-b347-b6aa908062d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732269185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2732269185
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2314025765
Short name T397
Test name
Test status
Simulation time 216333455 ps
CPU time 0.86 seconds
Started Jul 03 04:27:27 PM PDT 24
Finished Jul 03 04:27:28 PM PDT 24
Peak memory 199900 kb
Host smart-088dd8da-edfc-4a46-beee-9cbb1f7a5527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314025765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2314025765
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1173011151
Short name T451
Test name
Test status
Simulation time 801413528 ps
CPU time 3.85 seconds
Started Jul 03 04:28:59 PM PDT 24
Finished Jul 03 04:29:03 PM PDT 24
Peak memory 200296 kb
Host smart-5d3ffe1f-9cd2-447f-ad3c-59e66d0a3f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173011151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1173011151
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1778935184
Short name T470
Test name
Test status
Simulation time 183481218 ps
CPU time 1.27 seconds
Started Jul 03 04:27:44 PM PDT 24
Finished Jul 03 04:27:46 PM PDT 24
Peak memory 200096 kb
Host smart-7f9e234a-da6d-43cd-87a8-e33641c78838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778935184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1778935184
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.119845981
Short name T365
Test name
Test status
Simulation time 197582830 ps
CPU time 1.28 seconds
Started Jul 03 04:27:43 PM PDT 24
Finished Jul 03 04:27:44 PM PDT 24
Peak memory 200208 kb
Host smart-dc13573a-c9ec-4c7a-a0bc-7149de11fcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119845981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.119845981
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1789067478
Short name T81
Test name
Test status
Simulation time 7381761742 ps
CPU time 23.52 seconds
Started Jul 03 04:27:40 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 216184 kb
Host smart-e562d733-f90b-4b3a-b1f8-410720ee6fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789067478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1789067478
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3555654881
Short name T88
Test name
Test status
Simulation time 425455982 ps
CPU time 2.28 seconds
Started Jul 03 04:27:33 PM PDT 24
Finished Jul 03 04:27:36 PM PDT 24
Peak memory 208236 kb
Host smart-01a2d5b4-9479-4b0b-b387-1513299a22da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555654881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3555654881
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.372128754
Short name T197
Test name
Test status
Simulation time 190773739 ps
CPU time 1.11 seconds
Started Jul 03 04:27:54 PM PDT 24
Finished Jul 03 04:27:55 PM PDT 24
Peak memory 200080 kb
Host smart-1a9a4cdb-f79e-4317-9c62-922239ea44ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372128754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.372128754
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.92173030
Short name T375
Test name
Test status
Simulation time 70159786 ps
CPU time 0.72 seconds
Started Jul 03 04:27:45 PM PDT 24
Finished Jul 03 04:27:46 PM PDT 24
Peak memory 199872 kb
Host smart-6304560d-1295-4d4c-9b52-514ada2aadd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92173030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.92173030
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3784514252
Short name T518
Test name
Test status
Simulation time 1225074747 ps
CPU time 5.22 seconds
Started Jul 03 04:27:46 PM PDT 24
Finished Jul 03 04:27:52 PM PDT 24
Peak memory 217488 kb
Host smart-7cc7f598-f1ae-46b9-888a-24c48ec8051f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784514252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3784514252
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.381826618
Short name T475
Test name
Test status
Simulation time 244108403 ps
CPU time 1.18 seconds
Started Jul 03 04:27:47 PM PDT 24
Finished Jul 03 04:27:49 PM PDT 24
Peak memory 217492 kb
Host smart-12c5edb4-e301-495c-9c51-05bdecabeaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381826618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.381826618
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.688820006
Short name T19
Test name
Test status
Simulation time 113448410 ps
CPU time 0.85 seconds
Started Jul 03 04:27:25 PM PDT 24
Finished Jul 03 04:27:27 PM PDT 24
Peak memory 199784 kb
Host smart-b30db425-f2b4-4364-bc79-742d346f6008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688820006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.688820006
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1982472397
Short name T319
Test name
Test status
Simulation time 1265207281 ps
CPU time 4.83 seconds
Started Jul 03 04:29:04 PM PDT 24
Finished Jul 03 04:29:09 PM PDT 24
Peak memory 200312 kb
Host smart-ca29335f-b6e7-4086-9fd4-aa882bf5da0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982472397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1982472397
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3695983972
Short name T533
Test name
Test status
Simulation time 96371368 ps
CPU time 0.97 seconds
Started Jul 03 04:27:31 PM PDT 24
Finished Jul 03 04:27:32 PM PDT 24
Peak memory 200076 kb
Host smart-987e0405-924f-4287-945b-03ff19259127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695983972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3695983972
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2695651595
Short name T242
Test name
Test status
Simulation time 201782098 ps
CPU time 1.37 seconds
Started Jul 03 04:27:38 PM PDT 24
Finished Jul 03 04:27:40 PM PDT 24
Peak memory 200260 kb
Host smart-e725946b-98c1-44f2-a19e-38058c7fb26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695651595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2695651595
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.39486563
Short name T108
Test name
Test status
Simulation time 956167406 ps
CPU time 4.39 seconds
Started Jul 03 04:27:49 PM PDT 24
Finished Jul 03 04:27:53 PM PDT 24
Peak memory 200236 kb
Host smart-1dd318c5-bdbd-429f-97c4-651a0ae11fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39486563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.39486563
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3569328680
Short name T205
Test name
Test status
Simulation time 464292157 ps
CPU time 2.3 seconds
Started Jul 03 04:27:31 PM PDT 24
Finished Jul 03 04:27:33 PM PDT 24
Peak memory 200120 kb
Host smart-21897228-6b14-4ac9-8d03-fbe968f537a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569328680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3569328680
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1849030438
Short name T175
Test name
Test status
Simulation time 138541216 ps
CPU time 1.15 seconds
Started Jul 03 04:27:44 PM PDT 24
Finished Jul 03 04:27:46 PM PDT 24
Peak memory 200056 kb
Host smart-43bccf22-075b-443a-b64b-785aec2c88ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849030438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1849030438
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3080192947
Short name T229
Test name
Test status
Simulation time 83313332 ps
CPU time 0.82 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 199848 kb
Host smart-dd72a064-71c2-4669-bf07-61824da73645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080192947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3080192947
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3166353060
Short name T295
Test name
Test status
Simulation time 1222747352 ps
CPU time 5.28 seconds
Started Jul 03 04:27:19 PM PDT 24
Finished Jul 03 04:27:24 PM PDT 24
Peak memory 221484 kb
Host smart-5a60c4fd-249a-4f82-aeaa-882077a04f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166353060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3166353060
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2656830014
Short name T452
Test name
Test status
Simulation time 244248849 ps
CPU time 1.06 seconds
Started Jul 03 04:27:23 PM PDT 24
Finished Jul 03 04:27:25 PM PDT 24
Peak memory 217480 kb
Host smart-29070286-d9a7-4392-a6e7-59335d68cdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656830014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2656830014
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2112908358
Short name T195
Test name
Test status
Simulation time 207939416 ps
CPU time 0.95 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 200192 kb
Host smart-36bc3017-ec1c-4469-a2ad-c90fcea09c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112908358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2112908358
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2042410046
Short name T509
Test name
Test status
Simulation time 1873094021 ps
CPU time 6.58 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:21 PM PDT 24
Peak memory 200404 kb
Host smart-d69f923a-6479-4217-a261-ce6d18792f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042410046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2042410046
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2390469769
Short name T73
Test name
Test status
Simulation time 8369138279 ps
CPU time 12.89 seconds
Started Jul 03 04:27:16 PM PDT 24
Finished Jul 03 04:27:29 PM PDT 24
Peak memory 217292 kb
Host smart-06f7b24a-ba44-4d2e-8a97-09f27fb0b6e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390469769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2390469769
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4031476548
Short name T258
Test name
Test status
Simulation time 111240446 ps
CPU time 1.07 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:12 PM PDT 24
Peak memory 200032 kb
Host smart-b6f47b83-61ce-4af9-9132-028fd71c3928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031476548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.4031476548
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1700065019
Short name T366
Test name
Test status
Simulation time 263369991 ps
CPU time 1.49 seconds
Started Jul 03 04:27:39 PM PDT 24
Finished Jul 03 04:27:41 PM PDT 24
Peak memory 200300 kb
Host smart-98309225-3192-4e02-9cd7-5555298f3ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700065019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1700065019
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.366269343
Short name T256
Test name
Test status
Simulation time 91369675 ps
CPU time 0.86 seconds
Started Jul 03 04:27:17 PM PDT 24
Finished Jul 03 04:27:19 PM PDT 24
Peak memory 199796 kb
Host smart-b5507623-77bb-4680-90c8-811f9d76abf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366269343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.366269343
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2978288155
Short name T179
Test name
Test status
Simulation time 133375020 ps
CPU time 1.72 seconds
Started Jul 03 04:27:18 PM PDT 24
Finished Jul 03 04:27:20 PM PDT 24
Peak memory 200068 kb
Host smart-903232b8-80e3-4401-91a1-3f2e957d395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978288155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2978288155
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.211392184
Short name T200
Test name
Test status
Simulation time 77355203 ps
CPU time 0.77 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 199988 kb
Host smart-bc5986d5-b9e7-469a-a2a0-8787f7deb8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211392184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.211392184
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3850004628
Short name T407
Test name
Test status
Simulation time 68688154 ps
CPU time 0.75 seconds
Started Jul 03 04:27:37 PM PDT 24
Finished Jul 03 04:27:39 PM PDT 24
Peak memory 199860 kb
Host smart-1ce3380c-f1b3-4fee-9d42-4fd07c85b62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850004628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3850004628
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2462378895
Short name T47
Test name
Test status
Simulation time 2184134820 ps
CPU time 7.46 seconds
Started Jul 03 04:27:44 PM PDT 24
Finished Jul 03 04:27:52 PM PDT 24
Peak memory 221696 kb
Host smart-00f771a9-e58c-460a-abbc-e77c76058d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462378895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2462378895
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3710096574
Short name T136
Test name
Test status
Simulation time 244654267 ps
CPU time 1.1 seconds
Started Jul 03 04:27:38 PM PDT 24
Finished Jul 03 04:27:40 PM PDT 24
Peak memory 217400 kb
Host smart-2db60e20-06fb-439f-915a-f7d564d1134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710096574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3710096574
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1458262646
Short name T537
Test name
Test status
Simulation time 193772996 ps
CPU time 0.93 seconds
Started Jul 03 04:27:50 PM PDT 24
Finished Jul 03 04:27:52 PM PDT 24
Peak memory 199900 kb
Host smart-377d69e0-0d03-4521-8674-df31bd6df30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458262646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1458262646
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1317443559
Short name T184
Test name
Test status
Simulation time 790833947 ps
CPU time 4.02 seconds
Started Jul 03 04:27:36 PM PDT 24
Finished Jul 03 04:27:40 PM PDT 24
Peak memory 200288 kb
Host smart-3703356e-c72c-4854-a062-3020eae3ebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317443559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1317443559
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2163992222
Short name T153
Test name
Test status
Simulation time 106231253 ps
CPU time 0.99 seconds
Started Jul 03 04:27:42 PM PDT 24
Finished Jul 03 04:27:43 PM PDT 24
Peak memory 199924 kb
Host smart-6f7dc0b1-2901-44a1-8cd2-d3039a0e78cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163992222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2163992222
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2198228963
Short name T422
Test name
Test status
Simulation time 115564958 ps
CPU time 1.12 seconds
Started Jul 03 04:27:45 PM PDT 24
Finished Jul 03 04:27:46 PM PDT 24
Peak memory 200272 kb
Host smart-d2b6429f-9fbc-49a1-97b7-0bc292b69660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198228963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2198228963
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1113995927
Short name T126
Test name
Test status
Simulation time 8307842765 ps
CPU time 28.31 seconds
Started Jul 03 04:27:49 PM PDT 24
Finished Jul 03 04:28:18 PM PDT 24
Peak memory 200416 kb
Host smart-a067d72e-d3b5-483c-a31d-0f654f4239e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113995927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1113995927
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2436713015
Short name T504
Test name
Test status
Simulation time 133495939 ps
CPU time 1.5 seconds
Started Jul 03 04:27:37 PM PDT 24
Finished Jul 03 04:27:39 PM PDT 24
Peak memory 208276 kb
Host smart-b39cb3a0-4a9a-4c65-8db1-de6df37b31bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436713015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2436713015
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3581395105
Short name T335
Test name
Test status
Simulation time 200949814 ps
CPU time 1.2 seconds
Started Jul 03 04:27:50 PM PDT 24
Finished Jul 03 04:27:51 PM PDT 24
Peak memory 200052 kb
Host smart-0cae2a4c-ec19-4e88-a5e6-53da4c69e0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581395105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3581395105
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3755769542
Short name T204
Test name
Test status
Simulation time 68813416 ps
CPU time 0.78 seconds
Started Jul 03 04:27:45 PM PDT 24
Finished Jul 03 04:27:47 PM PDT 24
Peak memory 199860 kb
Host smart-cb5ba49f-6444-4421-90bb-e2e5b775394b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755769542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3755769542
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1052543306
Short name T28
Test name
Test status
Simulation time 2166723386 ps
CPU time 7.35 seconds
Started Jul 03 04:27:48 PM PDT 24
Finished Jul 03 04:27:56 PM PDT 24
Peak memory 217756 kb
Host smart-c10d12b3-8fa1-4191-a65a-ad4bec5e7afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052543306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1052543306
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1001752515
Short name T166
Test name
Test status
Simulation time 244531797 ps
CPU time 1.03 seconds
Started Jul 03 04:27:38 PM PDT 24
Finished Jul 03 04:27:40 PM PDT 24
Peak memory 217380 kb
Host smart-73d8b646-f414-40f0-9727-234b72dc3155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001752515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1001752515
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.620289566
Short name T15
Test name
Test status
Simulation time 164563972 ps
CPU time 0.9 seconds
Started Jul 03 04:27:48 PM PDT 24
Finished Jul 03 04:27:50 PM PDT 24
Peak memory 199844 kb
Host smart-d43e8249-0f89-4c1d-97ed-f91c8e88c155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620289566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.620289566
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3299906815
Short name T233
Test name
Test status
Simulation time 893821721 ps
CPU time 4.63 seconds
Started Jul 03 04:27:46 PM PDT 24
Finished Jul 03 04:27:51 PM PDT 24
Peak memory 200332 kb
Host smart-f20c74cd-738e-4c44-8429-09bc461e9559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299906815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3299906815
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1616972263
Short name T82
Test name
Test status
Simulation time 98649855 ps
CPU time 0.94 seconds
Started Jul 03 04:27:47 PM PDT 24
Finished Jul 03 04:27:49 PM PDT 24
Peak memory 200056 kb
Host smart-1617e10e-80e7-4182-b739-04e801c8f888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616972263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1616972263
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3530993583
Short name T273
Test name
Test status
Simulation time 237459046 ps
CPU time 1.62 seconds
Started Jul 03 04:27:54 PM PDT 24
Finished Jul 03 04:27:56 PM PDT 24
Peak memory 200260 kb
Host smart-98e7de6e-385d-46d2-816a-3e3d736d8c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530993583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3530993583
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1626642803
Short name T453
Test name
Test status
Simulation time 3855598851 ps
CPU time 14.08 seconds
Started Jul 03 04:27:36 PM PDT 24
Finished Jul 03 04:27:51 PM PDT 24
Peak memory 200460 kb
Host smart-2caee652-ba45-41a1-8fe5-72e348a11fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626642803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1626642803
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2642311066
Short name T59
Test name
Test status
Simulation time 139204535 ps
CPU time 1.65 seconds
Started Jul 03 04:27:32 PM PDT 24
Finished Jul 03 04:27:34 PM PDT 24
Peak memory 199988 kb
Host smart-caa9991b-073d-4861-a5d4-5bd9b3323565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642311066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2642311066
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.755160408
Short name T1
Test name
Test status
Simulation time 148370441 ps
CPU time 1.19 seconds
Started Jul 03 04:27:43 PM PDT 24
Finished Jul 03 04:27:45 PM PDT 24
Peak memory 200056 kb
Host smart-e8fa3857-2a7a-4a07-a4ee-07fa1d70aa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755160408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.755160408
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.599589932
Short name T280
Test name
Test status
Simulation time 64658953 ps
CPU time 0.74 seconds
Started Jul 03 04:27:45 PM PDT 24
Finished Jul 03 04:27:46 PM PDT 24
Peak memory 199868 kb
Host smart-52d94eff-8151-4acd-be45-fdf4ad6968ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599589932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.599589932
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1394518967
Short name T408
Test name
Test status
Simulation time 1229045460 ps
CPU time 5.76 seconds
Started Jul 03 04:27:50 PM PDT 24
Finished Jul 03 04:27:56 PM PDT 24
Peak memory 217788 kb
Host smart-3dda3a45-ae6c-4ffb-96d4-6a5c8c905fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394518967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1394518967
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1365223434
Short name T431
Test name
Test status
Simulation time 246074657 ps
CPU time 0.99 seconds
Started Jul 03 04:27:55 PM PDT 24
Finished Jul 03 04:27:57 PM PDT 24
Peak memory 217356 kb
Host smart-1093dcd1-e6f4-4526-9a94-6d776204d20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365223434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1365223434
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3128686717
Short name T478
Test name
Test status
Simulation time 164243978 ps
CPU time 0.86 seconds
Started Jul 03 04:27:43 PM PDT 24
Finished Jul 03 04:27:44 PM PDT 24
Peak memory 199824 kb
Host smart-9cf16d3e-0841-42f4-946a-360f3c583c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128686717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3128686717
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3384078307
Short name T409
Test name
Test status
Simulation time 1922830044 ps
CPU time 6.67 seconds
Started Jul 03 04:27:53 PM PDT 24
Finished Jul 03 04:28:00 PM PDT 24
Peak memory 200308 kb
Host smart-ad91861b-b478-4384-8638-1a4b00f30dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384078307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3384078307
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1721562760
Short name T199
Test name
Test status
Simulation time 98657777 ps
CPU time 0.99 seconds
Started Jul 03 04:27:39 PM PDT 24
Finished Jul 03 04:27:41 PM PDT 24
Peak memory 200092 kb
Host smart-b0ffc832-b97e-4884-a440-32968c498f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721562760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1721562760
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2356013578
Short name T311
Test name
Test status
Simulation time 118566038 ps
CPU time 1.12 seconds
Started Jul 03 04:27:52 PM PDT 24
Finished Jul 03 04:27:54 PM PDT 24
Peak memory 200140 kb
Host smart-b61f0e25-a827-47a2-8f17-f21ad97f7470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356013578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2356013578
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1779458343
Short name T362
Test name
Test status
Simulation time 960667813 ps
CPU time 4.58 seconds
Started Jul 03 04:27:46 PM PDT 24
Finished Jul 03 04:27:51 PM PDT 24
Peak memory 208464 kb
Host smart-edb0e90e-e0e1-4d95-a3f4-01eba9677dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779458343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1779458343
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.4039883493
Short name T519
Test name
Test status
Simulation time 520745031 ps
CPU time 2.68 seconds
Started Jul 03 04:27:25 PM PDT 24
Finished Jul 03 04:27:28 PM PDT 24
Peak memory 199980 kb
Host smart-58da81fc-4525-4609-9cfd-27e0f3051f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039883493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.4039883493
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3886575590
Short name T37
Test name
Test status
Simulation time 153492783 ps
CPU time 1.1 seconds
Started Jul 03 04:27:46 PM PDT 24
Finished Jul 03 04:27:48 PM PDT 24
Peak memory 200060 kb
Host smart-e77c432c-edb3-4145-b3eb-bd57dc3cb427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886575590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3886575590
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2856999971
Short name T80
Test name
Test status
Simulation time 67577248 ps
CPU time 0.79 seconds
Started Jul 03 04:27:41 PM PDT 24
Finished Jul 03 04:27:43 PM PDT 24
Peak memory 199856 kb
Host smart-4ed70593-068c-4310-9361-a845dd4298b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856999971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2856999971
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2268744718
Short name T290
Test name
Test status
Simulation time 1883796791 ps
CPU time 6.47 seconds
Started Jul 03 04:27:50 PM PDT 24
Finished Jul 03 04:27:58 PM PDT 24
Peak memory 216820 kb
Host smart-21a62faa-1856-49ef-b323-c8bf13730436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268744718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2268744718
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1110108830
Short name T385
Test name
Test status
Simulation time 244871139 ps
CPU time 1.12 seconds
Started Jul 03 04:27:56 PM PDT 24
Finished Jul 03 04:27:58 PM PDT 24
Peak memory 217416 kb
Host smart-2f841017-b7eb-448f-923f-d9d20d6b65fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110108830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1110108830
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2793507225
Short name T485
Test name
Test status
Simulation time 79364887 ps
CPU time 0.75 seconds
Started Jul 03 04:27:49 PM PDT 24
Finished Jul 03 04:27:51 PM PDT 24
Peak memory 199864 kb
Host smart-d28ae1ff-ee0e-4b2f-8353-954412a769e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793507225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2793507225
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.4208084288
Short name T2
Test name
Test status
Simulation time 859128502 ps
CPU time 4.3 seconds
Started Jul 03 04:27:33 PM PDT 24
Finished Jul 03 04:27:37 PM PDT 24
Peak memory 200404 kb
Host smart-31093a8a-5309-4002-a158-cf12c0fac9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208084288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.4208084288
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.216431618
Short name T289
Test name
Test status
Simulation time 178902258 ps
CPU time 1.12 seconds
Started Jul 03 04:27:46 PM PDT 24
Finished Jul 03 04:27:47 PM PDT 24
Peak memory 200080 kb
Host smart-0ac36844-6fbc-4a56-abf3-58bc5c397ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216431618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.216431618
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.609146556
Short name T203
Test name
Test status
Simulation time 119037621 ps
CPU time 1.18 seconds
Started Jul 03 04:27:48 PM PDT 24
Finished Jul 03 04:27:49 PM PDT 24
Peak memory 200248 kb
Host smart-594ad3b4-4df2-42da-ad46-bd9fe2e2f9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609146556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.609146556
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3095501495
Short name T525
Test name
Test status
Simulation time 10808690939 ps
CPU time 34.15 seconds
Started Jul 03 04:27:41 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 208652 kb
Host smart-c46a3550-5dd1-4cb1-b6b0-94a45e635ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095501495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3095501495
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2336209452
Short name T371
Test name
Test status
Simulation time 136488930 ps
CPU time 1.58 seconds
Started Jul 03 04:27:55 PM PDT 24
Finished Jul 03 04:27:57 PM PDT 24
Peak memory 200056 kb
Host smart-21bd9b9f-d26d-4428-879a-b341374d742a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336209452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2336209452
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3206047609
Short name T315
Test name
Test status
Simulation time 160874905 ps
CPU time 1.22 seconds
Started Jul 03 04:27:37 PM PDT 24
Finished Jul 03 04:27:39 PM PDT 24
Peak memory 200240 kb
Host smart-51aaf7c1-7eff-4362-8a93-ac5170d8af4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206047609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3206047609
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.213184158
Short name T363
Test name
Test status
Simulation time 78615660 ps
CPU time 0.78 seconds
Started Jul 03 04:27:49 PM PDT 24
Finished Jul 03 04:27:50 PM PDT 24
Peak memory 199872 kb
Host smart-95a1473e-d4c9-4256-bec8-14360541122c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213184158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.213184158
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2514214147
Short name T48
Test name
Test status
Simulation time 1215625697 ps
CPU time 5.44 seconds
Started Jul 03 04:27:50 PM PDT 24
Finished Jul 03 04:27:57 PM PDT 24
Peak memory 217728 kb
Host smart-6a272dba-3946-43ad-a95c-d0e1f8a4e85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514214147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2514214147
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2391124276
Short name T168
Test name
Test status
Simulation time 245439969 ps
CPU time 0.99 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:10 PM PDT 24
Peak memory 217420 kb
Host smart-6d5966a4-15ff-4464-98dc-27d702c5bd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391124276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2391124276
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1148566869
Short name T462
Test name
Test status
Simulation time 227830169 ps
CPU time 0.94 seconds
Started Jul 03 04:27:51 PM PDT 24
Finished Jul 03 04:27:53 PM PDT 24
Peak memory 199856 kb
Host smart-c3dce714-ee21-43b4-830c-fe40c3b02ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148566869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1148566869
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2751960170
Short name T125
Test name
Test status
Simulation time 1838251845 ps
CPU time 7.04 seconds
Started Jul 03 04:27:40 PM PDT 24
Finished Jul 03 04:27:48 PM PDT 24
Peak memory 200296 kb
Host smart-a04d7b9e-6ca3-441c-aef5-ef73d5178d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751960170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2751960170
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1339334078
Short name T208
Test name
Test status
Simulation time 100240025 ps
CPU time 0.97 seconds
Started Jul 03 04:27:39 PM PDT 24
Finished Jul 03 04:27:40 PM PDT 24
Peak memory 200048 kb
Host smart-130df047-b149-4237-8a0e-7f2d15f8b917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339334078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1339334078
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1183354074
Short name T364
Test name
Test status
Simulation time 189074222 ps
CPU time 1.33 seconds
Started Jul 03 04:27:49 PM PDT 24
Finished Jul 03 04:27:51 PM PDT 24
Peak memory 200296 kb
Host smart-02fbbc22-3a22-4af5-85ba-5326a1565658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183354074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1183354074
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3737076620
Short name T430
Test name
Test status
Simulation time 7282043282 ps
CPU time 24.28 seconds
Started Jul 03 04:27:51 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 208612 kb
Host smart-265f8e35-6930-4214-8956-41b41fec9b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737076620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3737076620
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1652538084
Short name T458
Test name
Test status
Simulation time 136741254 ps
CPU time 1.68 seconds
Started Jul 03 04:27:37 PM PDT 24
Finished Jul 03 04:27:39 PM PDT 24
Peak memory 200092 kb
Host smart-817b41a8-aa00-4eab-8fde-ec4744f8a850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652538084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1652538084
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3670660041
Short name T469
Test name
Test status
Simulation time 61443900 ps
CPU time 0.78 seconds
Started Jul 03 04:27:49 PM PDT 24
Finished Jul 03 04:27:51 PM PDT 24
Peak memory 200076 kb
Host smart-a21511df-d5ff-4b38-b3e0-d15831fa733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670660041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3670660041
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3244029478
Short name T483
Test name
Test status
Simulation time 60649154 ps
CPU time 0.78 seconds
Started Jul 03 04:27:47 PM PDT 24
Finished Jul 03 04:27:48 PM PDT 24
Peak memory 199884 kb
Host smart-94bc60df-b2ee-4a0a-8fdc-d3838205ed29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244029478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3244029478
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2524401118
Short name T30
Test name
Test status
Simulation time 2157918259 ps
CPU time 7.68 seconds
Started Jul 03 04:27:54 PM PDT 24
Finished Jul 03 04:28:02 PM PDT 24
Peak memory 229876 kb
Host smart-ab09a966-59e8-4716-96d5-2dd9829d372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524401118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2524401118
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4087526291
Short name T495
Test name
Test status
Simulation time 244907925 ps
CPU time 1.03 seconds
Started Jul 03 04:27:44 PM PDT 24
Finished Jul 03 04:27:45 PM PDT 24
Peak memory 217436 kb
Host smart-041ff8b7-e085-4f97-bb3b-22e3a0abbeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087526291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4087526291
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1219698558
Short name T164
Test name
Test status
Simulation time 102083083 ps
CPU time 0.84 seconds
Started Jul 03 04:27:52 PM PDT 24
Finished Jul 03 04:27:54 PM PDT 24
Peak memory 199912 kb
Host smart-98f778b6-7b86-4d7f-ba9d-15d89cf5816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219698558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1219698558
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.449526038
Short name T107
Test name
Test status
Simulation time 1937251394 ps
CPU time 7.78 seconds
Started Jul 03 04:28:03 PM PDT 24
Finished Jul 03 04:28:15 PM PDT 24
Peak memory 200356 kb
Host smart-d56786ff-cfea-41cc-a36c-71b04960f1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449526038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.449526038
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3436322576
Short name T148
Test name
Test status
Simulation time 140732005 ps
CPU time 1.24 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 200076 kb
Host smart-d72a7e76-48ae-4c75-9c73-5ea4aa22b6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436322576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3436322576
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2590796549
Short name T501
Test name
Test status
Simulation time 115777628 ps
CPU time 1.13 seconds
Started Jul 03 04:27:57 PM PDT 24
Finished Jul 03 04:27:58 PM PDT 24
Peak memory 200264 kb
Host smart-89fc4afb-547a-45fa-a27c-4e40377221d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590796549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2590796549
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2529296652
Short name T104
Test name
Test status
Simulation time 7377422741 ps
CPU time 36.13 seconds
Started Jul 03 04:27:54 PM PDT 24
Finished Jul 03 04:28:31 PM PDT 24
Peak memory 208576 kb
Host smart-bfa09389-4c25-48b0-af1e-733818668d50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529296652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2529296652
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1336609801
Short name T186
Test name
Test status
Simulation time 152405477 ps
CPU time 1.81 seconds
Started Jul 03 04:27:52 PM PDT 24
Finished Jul 03 04:27:54 PM PDT 24
Peak memory 200024 kb
Host smart-1b10f682-bc71-4809-9097-f4a3e6c978ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336609801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1336609801
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.4030618965
Short name T182
Test name
Test status
Simulation time 163195933 ps
CPU time 1.18 seconds
Started Jul 03 04:27:51 PM PDT 24
Finished Jul 03 04:27:53 PM PDT 24
Peak memory 200172 kb
Host smart-48a70adf-db27-4fff-9a0e-a7e62884e6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030618965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.4030618965
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.83399100
Short name T194
Test name
Test status
Simulation time 62403590 ps
CPU time 0.75 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:10 PM PDT 24
Peak memory 199896 kb
Host smart-3072bcc1-81c9-418b-8415-8b24e4f726d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83399100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.83399100
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2875416646
Short name T272
Test name
Test status
Simulation time 1893791113 ps
CPU time 7.05 seconds
Started Jul 03 04:27:52 PM PDT 24
Finished Jul 03 04:27:59 PM PDT 24
Peak memory 216924 kb
Host smart-887746d1-3dc4-4ce0-8b6c-249dddab5d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875416646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2875416646
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2856707919
Short name T156
Test name
Test status
Simulation time 244445419 ps
CPU time 1.05 seconds
Started Jul 03 04:27:47 PM PDT 24
Finished Jul 03 04:27:49 PM PDT 24
Peak memory 217520 kb
Host smart-0af4f683-99ce-4daa-9fe6-0455e6d94cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856707919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2856707919
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2625599585
Short name T261
Test name
Test status
Simulation time 105905137 ps
CPU time 0.83 seconds
Started Jul 03 04:27:46 PM PDT 24
Finished Jul 03 04:27:47 PM PDT 24
Peak memory 199744 kb
Host smart-0266c7ca-a002-4386-b0a8-9aff84ea71e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625599585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2625599585
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1177374093
Short name T496
Test name
Test status
Simulation time 681918508 ps
CPU time 3.32 seconds
Started Jul 03 04:27:51 PM PDT 24
Finished Jul 03 04:27:55 PM PDT 24
Peak memory 200268 kb
Host smart-454de321-e0a2-4b3d-8254-73e41835aed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177374093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1177374093
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2233046091
Short name T331
Test name
Test status
Simulation time 104650835 ps
CPU time 0.94 seconds
Started Jul 03 04:27:51 PM PDT 24
Finished Jul 03 04:27:53 PM PDT 24
Peak memory 199952 kb
Host smart-c4e01f1e-ece8-4c68-a7a1-cdba216d7c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233046091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2233046091
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.4164017816
Short name T56
Test name
Test status
Simulation time 237071476 ps
CPU time 1.44 seconds
Started Jul 03 04:28:08 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 200248 kb
Host smart-f4f1288b-9264-4db6-b1a2-a447d9b50ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164017816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4164017816
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.232829607
Short name T85
Test name
Test status
Simulation time 2181381510 ps
CPU time 9.54 seconds
Started Jul 03 04:27:56 PM PDT 24
Finished Jul 03 04:28:06 PM PDT 24
Peak memory 200408 kb
Host smart-aeed8354-9689-4511-b379-b2b9e6e20c53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232829607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.232829607
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2064703000
Short name T506
Test name
Test status
Simulation time 531870268 ps
CPU time 2.62 seconds
Started Jul 03 04:27:50 PM PDT 24
Finished Jul 03 04:27:54 PM PDT 24
Peak memory 200000 kb
Host smart-3896e624-dd9d-4a15-bbdc-34c0a19178de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064703000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2064703000
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3389696809
Short name T342
Test name
Test status
Simulation time 63658353 ps
CPU time 0.77 seconds
Started Jul 03 04:27:45 PM PDT 24
Finished Jul 03 04:27:47 PM PDT 24
Peak memory 199872 kb
Host smart-4b58220f-04d8-4044-a785-b6410b2cc3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389696809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3389696809
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3205281148
Short name T528
Test name
Test status
Simulation time 244166820 ps
CPU time 1.04 seconds
Started Jul 03 04:27:43 PM PDT 24
Finished Jul 03 04:27:45 PM PDT 24
Peak memory 217464 kb
Host smart-853c4fd8-5366-421a-b220-7d85e1c12833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205281148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3205281148
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3431251371
Short name T517
Test name
Test status
Simulation time 118162591 ps
CPU time 0.75 seconds
Started Jul 03 04:27:55 PM PDT 24
Finished Jul 03 04:27:56 PM PDT 24
Peak memory 199764 kb
Host smart-036478cc-2c44-47b7-bbc7-a9fafcc94790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431251371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3431251371
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1920945401
Short name T432
Test name
Test status
Simulation time 1119994156 ps
CPU time 5.79 seconds
Started Jul 03 04:28:06 PM PDT 24
Finished Jul 03 04:28:17 PM PDT 24
Peak memory 200316 kb
Host smart-412f350b-aa74-49e7-a8fa-394b0bb44e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920945401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1920945401
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2717605670
Short name T369
Test name
Test status
Simulation time 99192441 ps
CPU time 0.96 seconds
Started Jul 03 04:27:51 PM PDT 24
Finished Jul 03 04:27:53 PM PDT 24
Peak memory 199952 kb
Host smart-1581d18f-0682-4301-b45e-ecd1ed12392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717605670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2717605670
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3376202194
Short name T359
Test name
Test status
Simulation time 122791505 ps
CPU time 1.17 seconds
Started Jul 03 04:27:49 PM PDT 24
Finished Jul 03 04:27:50 PM PDT 24
Peak memory 200236 kb
Host smart-a2734cec-4342-4773-80ce-b8f1896698a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376202194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3376202194
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3262247614
Short name T167
Test name
Test status
Simulation time 144773718 ps
CPU time 1.83 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:01 PM PDT 24
Peak memory 200108 kb
Host smart-bce64dee-b72f-4b87-a3e8-7f82311b9aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262247614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3262247614
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1446234118
Short name T492
Test name
Test status
Simulation time 238731200 ps
CPU time 1.41 seconds
Started Jul 03 04:27:51 PM PDT 24
Finished Jul 03 04:27:53 PM PDT 24
Peak memory 200220 kb
Host smart-c8b8e1ce-3f58-46ad-bdb8-57f1fcfa91f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446234118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1446234118
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2578907564
Short name T221
Test name
Test status
Simulation time 65408549 ps
CPU time 0.72 seconds
Started Jul 03 04:27:58 PM PDT 24
Finished Jul 03 04:27:59 PM PDT 24
Peak memory 199868 kb
Host smart-638d0820-e16d-41a7-b1ff-8e4704e411ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578907564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2578907564
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1917591517
Short name T325
Test name
Test status
Simulation time 1881593653 ps
CPU time 6.77 seconds
Started Jul 03 04:27:55 PM PDT 24
Finished Jul 03 04:28:02 PM PDT 24
Peak memory 217572 kb
Host smart-ed78ec45-7e03-478b-84e7-e510beca7271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917591517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1917591517
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2477526488
Short name T381
Test name
Test status
Simulation time 244233372 ps
CPU time 1.1 seconds
Started Jul 03 04:27:48 PM PDT 24
Finished Jul 03 04:27:50 PM PDT 24
Peak memory 217476 kb
Host smart-0b5a12db-f40a-47e7-aa1e-68dfc5505d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477526488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2477526488
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.725046067
Short name T215
Test name
Test status
Simulation time 144286664 ps
CPU time 0.8 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:01 PM PDT 24
Peak memory 199884 kb
Host smart-89124bb1-a043-46d9-8f97-e534367e3341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725046067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.725046067
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3779738358
Short name T11
Test name
Test status
Simulation time 1391667250 ps
CPU time 5.34 seconds
Started Jul 03 04:27:56 PM PDT 24
Finished Jul 03 04:28:02 PM PDT 24
Peak memory 200336 kb
Host smart-94659755-6666-49dd-b847-ea701df99079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779738358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3779738358
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2682557368
Short name T6
Test name
Test status
Simulation time 150833593 ps
CPU time 1.08 seconds
Started Jul 03 04:27:58 PM PDT 24
Finished Jul 03 04:27:59 PM PDT 24
Peak memory 200040 kb
Host smart-eef258a8-f6ab-4e7f-a7ec-6685dfb0384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682557368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2682557368
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.276725351
Short name T415
Test name
Test status
Simulation time 201694141 ps
CPU time 1.37 seconds
Started Jul 03 04:27:45 PM PDT 24
Finished Jul 03 04:27:47 PM PDT 24
Peak memory 200280 kb
Host smart-179ec6ba-dca1-4acb-927b-60b31c5ea908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276725351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.276725351
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.4152839262
Short name T154
Test name
Test status
Simulation time 3977276252 ps
CPU time 15.07 seconds
Started Jul 03 04:27:46 PM PDT 24
Finished Jul 03 04:28:01 PM PDT 24
Peak memory 208632 kb
Host smart-e1de0c2b-f8bd-46c9-b313-46555fb216d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152839262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.4152839262
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3782913511
Short name T52
Test name
Test status
Simulation time 135657346 ps
CPU time 1.69 seconds
Started Jul 03 04:27:52 PM PDT 24
Finished Jul 03 04:27:54 PM PDT 24
Peak memory 200020 kb
Host smart-823189d9-80c5-47cc-9676-b2ee05626fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782913511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3782913511
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2319546262
Short name T479
Test name
Test status
Simulation time 78286369 ps
CPU time 0.82 seconds
Started Jul 03 04:27:49 PM PDT 24
Finished Jul 03 04:27:50 PM PDT 24
Peak memory 200024 kb
Host smart-707493ba-5fb7-4118-acec-69c1243b5cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319546262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2319546262
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3043641980
Short name T159
Test name
Test status
Simulation time 70367831 ps
CPU time 0.76 seconds
Started Jul 03 04:27:58 PM PDT 24
Finished Jul 03 04:27:59 PM PDT 24
Peak memory 199832 kb
Host smart-27576735-871e-4d5e-b8d7-651062c204a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043641980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3043641980
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1269429972
Short name T387
Test name
Test status
Simulation time 1229255625 ps
CPU time 5.71 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:05 PM PDT 24
Peak memory 217644 kb
Host smart-b6e929fd-7bf6-4b05-894c-6b71607d41e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269429972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1269429972
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3336586228
Short name T224
Test name
Test status
Simulation time 243412622 ps
CPU time 1.08 seconds
Started Jul 03 04:27:55 PM PDT 24
Finished Jul 03 04:27:57 PM PDT 24
Peak memory 217456 kb
Host smart-ed8abec6-8838-43a7-98cd-8cc0999ed61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336586228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3336586228
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2214624936
Short name T238
Test name
Test status
Simulation time 142580904 ps
CPU time 0.8 seconds
Started Jul 03 04:28:03 PM PDT 24
Finished Jul 03 04:28:07 PM PDT 24
Peak memory 199712 kb
Host smart-db8ffbc3-c826-4da2-8c0a-be70842fa2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214624936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2214624936
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.871637044
Short name T157
Test name
Test status
Simulation time 1248872602 ps
CPU time 4.73 seconds
Started Jul 03 04:27:53 PM PDT 24
Finished Jul 03 04:27:58 PM PDT 24
Peak memory 200316 kb
Host smart-65db60a0-d72e-4325-b2f3-94076bf3a2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871637044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.871637044
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2531741691
Short name T505
Test name
Test status
Simulation time 106277722 ps
CPU time 1.01 seconds
Started Jul 03 04:28:00 PM PDT 24
Finished Jul 03 04:28:01 PM PDT 24
Peak memory 200080 kb
Host smart-edede46a-6911-47fb-92af-14b000658bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531741691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2531741691
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1559353835
Short name T516
Test name
Test status
Simulation time 244156146 ps
CPU time 1.49 seconds
Started Jul 03 04:28:09 PM PDT 24
Finished Jul 03 04:28:15 PM PDT 24
Peak memory 200296 kb
Host smart-f36ff8b8-01e2-4ea4-9def-8b43566f388d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559353835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1559353835
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.316204123
Short name T497
Test name
Test status
Simulation time 8180264899 ps
CPU time 29.44 seconds
Started Jul 03 04:27:55 PM PDT 24
Finished Jul 03 04:28:25 PM PDT 24
Peak memory 200436 kb
Host smart-aeea9ca8-afa1-41e5-bc90-d863b7773ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316204123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.316204123
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.284606544
Short name T386
Test name
Test status
Simulation time 523708704 ps
CPU time 2.61 seconds
Started Jul 03 04:27:55 PM PDT 24
Finished Jul 03 04:27:58 PM PDT 24
Peak memory 200084 kb
Host smart-99bdb566-881c-45c4-a24c-dacdbc3f4c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284606544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.284606544
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2946641587
Short name T240
Test name
Test status
Simulation time 139121818 ps
CPU time 1.12 seconds
Started Jul 03 04:28:12 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 199924 kb
Host smart-dc062a64-f7ce-401e-a880-bf7e9661e545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946641587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2946641587
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.358087919
Short name T137
Test name
Test status
Simulation time 76538310 ps
CPU time 0.83 seconds
Started Jul 03 04:27:34 PM PDT 24
Finished Jul 03 04:27:37 PM PDT 24
Peak memory 199896 kb
Host smart-99f6b030-d4d2-4f6a-8167-137b6b49188a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358087919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.358087919
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2973678471
Short name T321
Test name
Test status
Simulation time 1879792262 ps
CPU time 6.72 seconds
Started Jul 03 04:27:24 PM PDT 24
Finished Jul 03 04:27:31 PM PDT 24
Peak memory 217692 kb
Host smart-43a322fd-8e89-4c57-b488-6a4a62bf09db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973678471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2973678471
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3056764440
Short name T489
Test name
Test status
Simulation time 245037728 ps
CPU time 1.06 seconds
Started Jul 03 04:27:35 PM PDT 24
Finished Jul 03 04:27:36 PM PDT 24
Peak memory 217448 kb
Host smart-c592c760-7315-40bb-87fc-7489f94d78fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056764440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3056764440
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2848753552
Short name T429
Test name
Test status
Simulation time 107287709 ps
CPU time 0.84 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 199748 kb
Host smart-7844ee19-0136-4c4f-9d21-180359440c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848753552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2848753552
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.648518439
Short name T129
Test name
Test status
Simulation time 1345453051 ps
CPU time 5.6 seconds
Started Jul 03 04:27:09 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 200208 kb
Host smart-3fcd1f04-a926-4ccb-a252-c77c02b515db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648518439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.648518439
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.384742880
Short name T71
Test name
Test status
Simulation time 8287102863 ps
CPU time 14.97 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:19 PM PDT 24
Peak memory 217588 kb
Host smart-ee1c8e39-abcf-4365-a157-3a4bfaf0190d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384742880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.384742880
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.462606440
Short name T440
Test name
Test status
Simulation time 135329664 ps
CPU time 1.02 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:11 PM PDT 24
Peak memory 200020 kb
Host smart-d1fa9dba-e75b-4e5e-b629-f07c5e9cccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462606440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.462606440
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2570551985
Short name T399
Test name
Test status
Simulation time 234533887 ps
CPU time 1.45 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 200244 kb
Host smart-e5575115-a32f-4ca5-bd6b-901eded8787e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570551985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2570551985
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3771822396
Short name T523
Test name
Test status
Simulation time 8660590601 ps
CPU time 30.8 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:39 PM PDT 24
Peak memory 208412 kb
Host smart-72fb5da7-a944-47c3-bdd6-433ca27d9c27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771822396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3771822396
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2390142091
Short name T301
Test name
Test status
Simulation time 152450306 ps
CPU time 1.76 seconds
Started Jul 03 04:27:24 PM PDT 24
Finished Jul 03 04:27:26 PM PDT 24
Peak memory 200104 kb
Host smart-76580a89-8314-4b88-9c6e-84f7e8d7b4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390142091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2390142091
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2386870636
Short name T498
Test name
Test status
Simulation time 116732817 ps
CPU time 0.89 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 199724 kb
Host smart-18b7fb87-16af-4d8a-b56b-b83fd5d8e63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386870636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2386870636
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.935585839
Short name T147
Test name
Test status
Simulation time 60574903 ps
CPU time 0.74 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:09 PM PDT 24
Peak memory 199852 kb
Host smart-875ee230-8616-4a56-818b-b875a82b7858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935585839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.935585839
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3591010830
Short name T31
Test name
Test status
Simulation time 2184212132 ps
CPU time 7.7 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:10 PM PDT 24
Peak memory 217444 kb
Host smart-c03247d8-cdad-4f19-aafc-27eb9a681a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591010830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3591010830
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3351479965
Short name T40
Test name
Test status
Simulation time 243318174 ps
CPU time 1.1 seconds
Started Jul 03 04:27:55 PM PDT 24
Finished Jul 03 04:27:56 PM PDT 24
Peak memory 217476 kb
Host smart-ff354d24-006a-49d7-9552-ee439aacc306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351479965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3351479965
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.870184974
Short name T285
Test name
Test status
Simulation time 166488164 ps
CPU time 0.88 seconds
Started Jul 03 04:28:08 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 199804 kb
Host smart-c811143b-726f-4435-b31f-d0862d0fd130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870184974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.870184974
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.769463392
Short name T288
Test name
Test status
Simulation time 1390579004 ps
CPU time 5.2 seconds
Started Jul 03 04:27:58 PM PDT 24
Finished Jul 03 04:28:03 PM PDT 24
Peak memory 200360 kb
Host smart-46068c70-5199-40aa-b83e-5852146e03fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769463392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.769463392
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.272754156
Short name T282
Test name
Test status
Simulation time 107739070 ps
CPU time 0.95 seconds
Started Jul 03 04:27:56 PM PDT 24
Finished Jul 03 04:27:57 PM PDT 24
Peak memory 199976 kb
Host smart-f7dadda1-47be-4a95-a69b-dd65d8775e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272754156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.272754156
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1716629529
Short name T314
Test name
Test status
Simulation time 196731976 ps
CPU time 1.36 seconds
Started Jul 03 04:27:54 PM PDT 24
Finished Jul 03 04:27:55 PM PDT 24
Peak memory 200292 kb
Host smart-9da113d5-f783-44b4-8ccb-362b560d123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716629529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1716629529
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3232047238
Short name T527
Test name
Test status
Simulation time 1039581366 ps
CPU time 4.86 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 200644 kb
Host smart-919595ee-aafa-4426-a904-4eb05c50baa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232047238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3232047238
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2573961904
Short name T405
Test name
Test status
Simulation time 372828008 ps
CPU time 2.22 seconds
Started Jul 03 04:27:57 PM PDT 24
Finished Jul 03 04:28:00 PM PDT 24
Peak memory 200080 kb
Host smart-c3e4568f-6fd2-4cda-a5e4-9e3d4fbb0dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573961904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2573961904
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.4206242924
Short name T445
Test name
Test status
Simulation time 294530210 ps
CPU time 1.5 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:03 PM PDT 24
Peak memory 200292 kb
Host smart-2982ebc0-e2f6-45be-880b-35cfd64a12b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206242924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.4206242924
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1369383240
Short name T177
Test name
Test status
Simulation time 64032410 ps
CPU time 0.72 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:07 PM PDT 24
Peak memory 199884 kb
Host smart-aa0b2c9b-8548-472d-945d-21e3a210f917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369383240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1369383240
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2500641718
Short name T490
Test name
Test status
Simulation time 1221995232 ps
CPU time 5.78 seconds
Started Jul 03 04:28:03 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 217312 kb
Host smart-d3e97bfa-50c8-4629-bb57-4ec74a82d6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500641718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2500641718
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2962967496
Short name T217
Test name
Test status
Simulation time 243861160 ps
CPU time 1.11 seconds
Started Jul 03 04:28:06 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 217468 kb
Host smart-c17cb9c1-66ec-4bde-a4d0-bfdc194c275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962967496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2962967496
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2734787351
Short name T251
Test name
Test status
Simulation time 227906457 ps
CPU time 0.95 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:07 PM PDT 24
Peak memory 199900 kb
Host smart-39fc4373-c27f-4135-a8b0-77a742174f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734787351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2734787351
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2684693060
Short name T367
Test name
Test status
Simulation time 1012874618 ps
CPU time 4.9 seconds
Started Jul 03 04:27:57 PM PDT 24
Finished Jul 03 04:28:03 PM PDT 24
Peak memory 200348 kb
Host smart-4ad6982b-1f46-4946-b9d0-69448b4e6e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684693060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2684693060
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1165001889
Short name T420
Test name
Test status
Simulation time 147397073 ps
CPU time 1.1 seconds
Started Jul 03 04:28:03 PM PDT 24
Finished Jul 03 04:28:08 PM PDT 24
Peak memory 199900 kb
Host smart-d728055e-20b2-426e-86e7-a8a6ae59b346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165001889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1165001889
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3977865556
Short name T304
Test name
Test status
Simulation time 226415319 ps
CPU time 1.41 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:05 PM PDT 24
Peak memory 200240 kb
Host smart-e8da1689-fe35-41f0-871e-ecf77603beec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977865556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3977865556
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3773192086
Short name T384
Test name
Test status
Simulation time 220113897 ps
CPU time 1.19 seconds
Started Jul 03 04:28:09 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 200060 kb
Host smart-49ef465f-97d8-459b-b56e-9b5707b76e66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773192086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3773192086
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.4121942181
Short name T322
Test name
Test status
Simulation time 265775649 ps
CPU time 1.77 seconds
Started Jul 03 04:27:57 PM PDT 24
Finished Jul 03 04:27:59 PM PDT 24
Peak memory 200016 kb
Host smart-1ff0962a-b604-445d-9fd4-483a12520407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121942181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.4121942181
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3620821019
Short name T313
Test name
Test status
Simulation time 271237302 ps
CPU time 1.56 seconds
Started Jul 03 04:28:00 PM PDT 24
Finished Jul 03 04:28:03 PM PDT 24
Peak memory 200076 kb
Host smart-b0411cf6-58f5-47c0-bf66-bb0bc8213a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620821019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3620821019
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1543282971
Short name T534
Test name
Test status
Simulation time 64648944 ps
CPU time 0.78 seconds
Started Jul 03 04:28:10 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 199872 kb
Host smart-324af05c-9c0d-423f-aef7-9b69dfa37e6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543282971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1543282971
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3789464626
Short name T310
Test name
Test status
Simulation time 2357836209 ps
CPU time 7.64 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 221664 kb
Host smart-d1d5351d-08c3-45d0-aad9-e5d1a065e9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789464626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3789464626
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4235603361
Short name T292
Test name
Test status
Simulation time 244611924 ps
CPU time 1.02 seconds
Started Jul 03 04:29:21 PM PDT 24
Finished Jul 03 04:29:23 PM PDT 24
Peak memory 217352 kb
Host smart-a89ee58d-7674-4df9-865f-bbd02c09edaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235603361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4235603361
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3720178698
Short name T279
Test name
Test status
Simulation time 140785378 ps
CPU time 0.84 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:06 PM PDT 24
Peak memory 199900 kb
Host smart-bb2c7df9-72a4-4372-afcf-ae0d1dd7ce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720178698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3720178698
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3626892309
Short name T264
Test name
Test status
Simulation time 1130377640 ps
CPU time 4.96 seconds
Started Jul 03 04:28:06 PM PDT 24
Finished Jul 03 04:28:17 PM PDT 24
Peak memory 200360 kb
Host smart-21a044bf-792e-47aa-ad10-95818e14465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626892309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3626892309
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2176155902
Short name T174
Test name
Test status
Simulation time 174035650 ps
CPU time 1.1 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:03 PM PDT 24
Peak memory 199952 kb
Host smart-116bcaa1-d098-4d96-9d27-be17feceb4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176155902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2176155902
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1839081343
Short name T520
Test name
Test status
Simulation time 123777698 ps
CPU time 1.17 seconds
Started Jul 03 04:28:00 PM PDT 24
Finished Jul 03 04:28:02 PM PDT 24
Peak memory 200316 kb
Host smart-ae74a61c-e3f4-4665-9644-87b5b203ca3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839081343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1839081343
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.808145342
Short name T510
Test name
Test status
Simulation time 3985348419 ps
CPU time 13.85 seconds
Started Jul 03 04:28:13 PM PDT 24
Finished Jul 03 04:28:29 PM PDT 24
Peak memory 208616 kb
Host smart-e558e4c7-1932-4bf6-8a00-a60e83feeb23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808145342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.808145342
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2402210263
Short name T78
Test name
Test status
Simulation time 522864923 ps
CPU time 2.54 seconds
Started Jul 03 04:29:02 PM PDT 24
Finished Jul 03 04:29:05 PM PDT 24
Peak memory 199972 kb
Host smart-bce1572a-5cc0-4558-9755-319be8e2bbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402210263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2402210263
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3944868407
Short name T448
Test name
Test status
Simulation time 183315108 ps
CPU time 1.14 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:09 PM PDT 24
Peak memory 200052 kb
Host smart-fa176efd-32cd-4f83-9618-0d00757b47cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944868407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3944868407
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2476745288
Short name T139
Test name
Test status
Simulation time 82781762 ps
CPU time 0.77 seconds
Started Jul 03 04:28:13 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 199888 kb
Host smart-fdec33f6-393a-4430-aa0d-9f6c4b15c68b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476745288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2476745288
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1192470771
Short name T531
Test name
Test status
Simulation time 2360182092 ps
CPU time 7.73 seconds
Started Jul 03 04:27:57 PM PDT 24
Finished Jul 03 04:28:06 PM PDT 24
Peak memory 217844 kb
Host smart-1cd3c0fd-6af0-4b49-8363-ce24e305a4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192470771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1192470771
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.484118000
Short name T287
Test name
Test status
Simulation time 244697554 ps
CPU time 1.09 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:00 PM PDT 24
Peak memory 217432 kb
Host smart-5da4e9ee-b541-4bbc-8587-aba7adc6d5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484118000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.484118000
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.97063253
Short name T21
Test name
Test status
Simulation time 128691585 ps
CPU time 0.82 seconds
Started Jul 03 04:28:14 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 199848 kb
Host smart-f0180944-fdb3-40cd-9d0e-bad70ea2edfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97063253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.97063253
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.946520568
Short name T443
Test name
Test status
Simulation time 1635208297 ps
CPU time 6.28 seconds
Started Jul 03 04:27:55 PM PDT 24
Finished Jul 03 04:28:02 PM PDT 24
Peak memory 200288 kb
Host smart-7eb7996a-0963-4ebe-9574-161f20ea8fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946520568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.946520568
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.437970543
Short name T183
Test name
Test status
Simulation time 145288223 ps
CPU time 1.03 seconds
Started Jul 03 04:27:57 PM PDT 24
Finished Jul 03 04:27:59 PM PDT 24
Peak memory 199940 kb
Host smart-a359a15a-8c64-4083-a5b6-22a51cba972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437970543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.437970543
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2927621348
Short name T58
Test name
Test status
Simulation time 114490145 ps
CPU time 1.16 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:06 PM PDT 24
Peak memory 200240 kb
Host smart-a58d69c2-d756-4c2f-9655-222cccd49c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927621348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2927621348
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2110804336
Short name T87
Test name
Test status
Simulation time 1545494247 ps
CPU time 6.27 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 208536 kb
Host smart-658a1246-aef4-4147-a05a-e8e1380b8cc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110804336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2110804336
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1534906726
Short name T357
Test name
Test status
Simulation time 128537328 ps
CPU time 1.56 seconds
Started Jul 03 04:28:07 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 200104 kb
Host smart-1f7da1bf-0251-4fed-a7d1-6656bd82906f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534906726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1534906726
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.4182210076
Short name T83
Test name
Test status
Simulation time 165941433 ps
CPU time 1.1 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:01 PM PDT 24
Peak memory 199948 kb
Host smart-8afb8197-6222-4d18-aa0f-fa1c6ba24ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182210076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.4182210076
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.4058811512
Short name T10
Test name
Test status
Simulation time 75069185 ps
CPU time 0.75 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:00 PM PDT 24
Peak memory 199808 kb
Host smart-adc9ca40-c125-4c31-8348-ffcfde420ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058811512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.4058811512
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.4002710673
Short name T263
Test name
Test status
Simulation time 1230838137 ps
CPU time 5.34 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:07 PM PDT 24
Peak memory 221536 kb
Host smart-e7ce56a1-3091-4004-8072-3f91e17122d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002710673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.4002710673
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2603232652
Short name T253
Test name
Test status
Simulation time 244579067 ps
CPU time 1.02 seconds
Started Jul 03 04:27:57 PM PDT 24
Finished Jul 03 04:27:59 PM PDT 24
Peak memory 217336 kb
Host smart-dd69fdf8-5b9a-466d-99d5-adecc1794fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603232652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2603232652
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.865008089
Short name T14
Test name
Test status
Simulation time 154402946 ps
CPU time 0.8 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 199840 kb
Host smart-68cb9a1d-5018-4dd9-9738-7c152959803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865008089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.865008089
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2654118373
Short name T373
Test name
Test status
Simulation time 1026628704 ps
CPU time 5.04 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:08 PM PDT 24
Peak memory 200324 kb
Host smart-74c34ed2-b579-4140-983d-1a915b8659a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654118373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2654118373
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1152409768
Short name T151
Test name
Test status
Simulation time 145453274 ps
CPU time 1.11 seconds
Started Jul 03 04:28:17 PM PDT 24
Finished Jul 03 04:28:20 PM PDT 24
Peak memory 200040 kb
Host smart-b634e80e-1368-42c3-8d75-edc95d2789c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152409768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1152409768
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3033068183
Short name T338
Test name
Test status
Simulation time 124824798 ps
CPU time 1.23 seconds
Started Jul 03 04:28:09 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 200264 kb
Host smart-da0184a6-20a7-480c-8d5e-776ba405eb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033068183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3033068183
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3513463901
Short name T23
Test name
Test status
Simulation time 7055127053 ps
CPU time 22.87 seconds
Started Jul 03 04:28:00 PM PDT 24
Finished Jul 03 04:28:24 PM PDT 24
Peak memory 208576 kb
Host smart-8c859568-9e3e-4a11-9b71-58e9dab1e7a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513463901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3513463901
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.229300889
Short name T424
Test name
Test status
Simulation time 149700873 ps
CPU time 1.86 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:02 PM PDT 24
Peak memory 199988 kb
Host smart-9845b418-69aa-4d27-8412-313cca27a42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229300889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.229300889
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1190841756
Short name T433
Test name
Test status
Simulation time 139650255 ps
CPU time 0.99 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:07 PM PDT 24
Peak memory 200028 kb
Host smart-ef7a8497-49d5-4026-a78a-b06f5dbb1751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190841756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1190841756
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1077390730
Short name T382
Test name
Test status
Simulation time 75703288 ps
CPU time 0.78 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:09 PM PDT 24
Peak memory 199792 kb
Host smart-390b115c-86d5-4caa-9e9c-076ac97b4eed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077390730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1077390730
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2802835147
Short name T226
Test name
Test status
Simulation time 1228572417 ps
CPU time 5.62 seconds
Started Jul 03 04:27:58 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 221584 kb
Host smart-36703411-b94c-4ea3-891e-e915719d55c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802835147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2802835147
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2950144195
Short name T144
Test name
Test status
Simulation time 243785259 ps
CPU time 1.09 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 217176 kb
Host smart-0a9a3ef4-0f36-4971-bb3b-16adb43255a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950144195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2950144195
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.43454480
Short name T416
Test name
Test status
Simulation time 159665631 ps
CPU time 0.81 seconds
Started Jul 03 04:27:56 PM PDT 24
Finished Jul 03 04:27:57 PM PDT 24
Peak memory 199888 kb
Host smart-3b0d0127-25de-417d-870f-a3d569442299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43454480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.43454480
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.896496797
Short name T100
Test name
Test status
Simulation time 1172044084 ps
CPU time 4.84 seconds
Started Jul 03 04:27:51 PM PDT 24
Finished Jul 03 04:27:57 PM PDT 24
Peak memory 200232 kb
Host smart-b57b4c7c-b228-48ba-bb6a-ebeb3bb4f6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896496797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.896496797
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1633626073
Short name T444
Test name
Test status
Simulation time 103412422 ps
CPU time 0.96 seconds
Started Jul 03 04:27:57 PM PDT 24
Finished Jul 03 04:28:05 PM PDT 24
Peak memory 199996 kb
Host smart-3cef0faa-2059-46ca-9540-0d6ef2cd680b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633626073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1633626073
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1380153121
Short name T412
Test name
Test status
Simulation time 226957444 ps
CPU time 1.43 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:01 PM PDT 24
Peak memory 200160 kb
Host smart-75b52801-853b-435d-89c8-4c594aefd289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380153121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1380153121
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.817980798
Short name T487
Test name
Test status
Simulation time 6804506091 ps
CPU time 30.56 seconds
Started Jul 03 04:28:06 PM PDT 24
Finished Jul 03 04:28:42 PM PDT 24
Peak memory 200340 kb
Host smart-c92a0159-64f1-4844-a5f0-137a1b32d337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817980798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.817980798
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3191393082
Short name T225
Test name
Test status
Simulation time 362497623 ps
CPU time 2.18 seconds
Started Jul 03 04:27:57 PM PDT 24
Finished Jul 03 04:27:59 PM PDT 24
Peak memory 200028 kb
Host smart-330ab31e-5dfd-4e05-a625-dc1fa8737de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191393082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3191393082
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.523383696
Short name T455
Test name
Test status
Simulation time 206453122 ps
CPU time 1.29 seconds
Started Jul 03 04:28:08 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 199960 kb
Host smart-c67ccb68-a45d-4619-bd1a-f0efefd4af06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523383696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.523383696
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1586520958
Short name T228
Test name
Test status
Simulation time 64863285 ps
CPU time 0.76 seconds
Started Jul 03 04:28:08 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 199900 kb
Host smart-08cfda97-176d-40a8-922d-7cfae86489ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586520958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1586520958
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2128556797
Short name T49
Test name
Test status
Simulation time 2345262095 ps
CPU time 8.68 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:18 PM PDT 24
Peak memory 217848 kb
Host smart-e185769d-4a88-4ea1-a23d-d3cf7e71c0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128556797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2128556797
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3532547733
Short name T234
Test name
Test status
Simulation time 244692491 ps
CPU time 1.07 seconds
Started Jul 03 04:28:17 PM PDT 24
Finished Jul 03 04:28:20 PM PDT 24
Peak memory 217424 kb
Host smart-5c64286c-55b1-459b-a902-2fbe267e139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532547733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3532547733
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.4124893491
Short name T4
Test name
Test status
Simulation time 259080400 ps
CPU time 1.01 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:10 PM PDT 24
Peak memory 199864 kb
Host smart-b5a46291-7822-4bf7-be9e-2b55a3a1e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124893491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.4124893491
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1569959306
Short name T98
Test name
Test status
Simulation time 888078600 ps
CPU time 4.13 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:07 PM PDT 24
Peak memory 200128 kb
Host smart-cc814982-9ff7-4d0f-82fe-06ac84fbcd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569959306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1569959306
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4216463699
Short name T344
Test name
Test status
Simulation time 98284785 ps
CPU time 0.95 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:08 PM PDT 24
Peak memory 200076 kb
Host smart-ebb2ee2c-9030-4dc7-b826-1e56f6061272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216463699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4216463699
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1595412376
Short name T454
Test name
Test status
Simulation time 117283208 ps
CPU time 1.13 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:01 PM PDT 24
Peak memory 200296 kb
Host smart-49626d70-2485-4fbc-b69c-a2c41409de96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595412376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1595412376
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3709057923
Short name T423
Test name
Test status
Simulation time 4488269252 ps
CPU time 15.35 seconds
Started Jul 03 04:28:08 PM PDT 24
Finished Jul 03 04:28:28 PM PDT 24
Peak memory 200404 kb
Host smart-85909d78-c1ed-4ed7-ba97-e3443b7a38b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709057923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3709057923
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3774381864
Short name T390
Test name
Test status
Simulation time 141742033 ps
CPU time 1.69 seconds
Started Jul 03 04:28:06 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 200100 kb
Host smart-f9a99865-9ef4-4cec-aeb7-097e566f9189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774381864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3774381864
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3883292889
Short name T539
Test name
Test status
Simulation time 90822308 ps
CPU time 0.84 seconds
Started Jul 03 04:28:00 PM PDT 24
Finished Jul 03 04:28:02 PM PDT 24
Peak memory 199952 kb
Host smart-6bffb49d-90dc-4130-82ed-9e2a124725c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883292889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3883292889
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.381986547
Short name T172
Test name
Test status
Simulation time 70901951 ps
CPU time 0.72 seconds
Started Jul 03 04:28:17 PM PDT 24
Finished Jul 03 04:28:19 PM PDT 24
Peak memory 199880 kb
Host smart-d50e50e3-9861-40d8-a372-4ed0875a5252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381986547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.381986547
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.757223008
Short name T524
Test name
Test status
Simulation time 244483232 ps
CPU time 1.09 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:05 PM PDT 24
Peak memory 217440 kb
Host smart-3862d245-ea6a-4197-ba2c-c023e9910dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757223008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.757223008
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2909097197
Short name T22
Test name
Test status
Simulation time 198314097 ps
CPU time 0.94 seconds
Started Jul 03 04:27:58 PM PDT 24
Finished Jul 03 04:28:00 PM PDT 24
Peak memory 199900 kb
Host smart-08cd946d-a53e-4387-a9f6-125400777ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909097197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2909097197
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3023924188
Short name T13
Test name
Test status
Simulation time 1483412132 ps
CPU time 5.29 seconds
Started Jul 03 04:28:05 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 200408 kb
Host smart-7af79afd-5a10-4a3c-9f11-61c5dbbff441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023924188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3023924188
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3049006293
Short name T511
Test name
Test status
Simulation time 149819895 ps
CPU time 1.17 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:10 PM PDT 24
Peak memory 200076 kb
Host smart-a2a241e4-9376-46d9-ae2d-089b8816974e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049006293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3049006293
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1099838832
Short name T388
Test name
Test status
Simulation time 254205205 ps
CPU time 1.46 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:10 PM PDT 24
Peak memory 200260 kb
Host smart-20ce695a-e601-4b61-b4e2-15676fcc5500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099838832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1099838832
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3225215901
Short name T103
Test name
Test status
Simulation time 7187625032 ps
CPU time 26.82 seconds
Started Jul 03 04:28:00 PM PDT 24
Finished Jul 03 04:28:27 PM PDT 24
Peak memory 200376 kb
Host smart-7ae7d717-7d76-4220-8c26-a431d3ac6072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225215901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3225215901
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3986081911
Short name T404
Test name
Test status
Simulation time 107980641 ps
CPU time 1.33 seconds
Started Jul 03 04:28:05 PM PDT 24
Finished Jul 03 04:28:11 PM PDT 24
Peak memory 200100 kb
Host smart-bfe6ad86-1dd9-488c-8d6e-ca9b1e13b5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986081911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3986081911
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2811161364
Short name T247
Test name
Test status
Simulation time 88327550 ps
CPU time 0.86 seconds
Started Jul 03 04:28:03 PM PDT 24
Finished Jul 03 04:28:07 PM PDT 24
Peak memory 200044 kb
Host smart-b0e67a25-bb76-49fd-8f6c-b9dd739224a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811161364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2811161364
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2916345649
Short name T266
Test name
Test status
Simulation time 68446340 ps
CPU time 0.75 seconds
Started Jul 03 04:28:03 PM PDT 24
Finished Jul 03 04:28:08 PM PDT 24
Peak memory 199860 kb
Host smart-c10ab4a0-5362-47e0-a050-e842c74475a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916345649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2916345649
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2741286749
Short name T45
Test name
Test status
Simulation time 1222495367 ps
CPU time 5.53 seconds
Started Jul 03 04:28:07 PM PDT 24
Finished Jul 03 04:28:18 PM PDT 24
Peak memory 217492 kb
Host smart-0273c6ab-0be1-4aa5-a01d-b288f5815a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741286749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2741286749
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.4250198100
Short name T392
Test name
Test status
Simulation time 246947723 ps
CPU time 1.02 seconds
Started Jul 03 04:28:00 PM PDT 24
Finished Jul 03 04:28:11 PM PDT 24
Peak memory 217440 kb
Host smart-1abac372-4007-4853-8ab4-a3421120d32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250198100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.4250198100
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.158579556
Short name T198
Test name
Test status
Simulation time 183448609 ps
CPU time 0.83 seconds
Started Jul 03 04:28:21 PM PDT 24
Finished Jul 03 04:28:23 PM PDT 24
Peak memory 199844 kb
Host smart-f761d1b6-23fe-4be4-a74b-7994ac6d17a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158579556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.158579556
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3789228727
Short name T464
Test name
Test status
Simulation time 1126456042 ps
CPU time 4.37 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:11 PM PDT 24
Peak memory 200312 kb
Host smart-36752c9d-8d38-4b39-9f1a-ad77b0b175fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789228727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3789228727
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.4109214870
Short name T351
Test name
Test status
Simulation time 163653677 ps
CPU time 1.12 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:03 PM PDT 24
Peak memory 200076 kb
Host smart-78b96fcc-4541-4ec2-993c-ca149dd65ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109214870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.4109214870
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.607595232
Short name T79
Test name
Test status
Simulation time 192652092 ps
CPU time 1.27 seconds
Started Jul 03 04:28:03 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 200292 kb
Host smart-2852988d-063f-49b0-bf02-6f959fc8b7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607595232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.607595232
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1375671830
Short name T521
Test name
Test status
Simulation time 2802087518 ps
CPU time 11.57 seconds
Started Jul 03 04:28:05 PM PDT 24
Finished Jul 03 04:28:23 PM PDT 24
Peak memory 200392 kb
Host smart-7e75b5a5-9298-4c59-a2c3-a6fc8934e436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375671830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1375671830
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3078738715
Short name T41
Test name
Test status
Simulation time 122647130 ps
CPU time 1.55 seconds
Started Jul 03 04:28:10 PM PDT 24
Finished Jul 03 04:28:15 PM PDT 24
Peak memory 208320 kb
Host smart-fa9c2ffa-9634-4811-9f43-9ec311156096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078738715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3078738715
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.4050130778
Short name T276
Test name
Test status
Simulation time 92162061 ps
CPU time 0.88 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:10 PM PDT 24
Peak memory 200012 kb
Host smart-1786839c-5fff-4854-bf64-c37e4fd9800e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050130778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.4050130778
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2469886359
Short name T442
Test name
Test status
Simulation time 70481124 ps
CPU time 0.79 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 199832 kb
Host smart-ded1278b-e4fb-43ad-ac2e-d66cfca690d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469886359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2469886359
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2173636156
Short name T26
Test name
Test status
Simulation time 1218046756 ps
CPU time 5.3 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:09 PM PDT 24
Peak memory 217660 kb
Host smart-49432f32-f430-4a43-a2aa-bb50bc1ca047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173636156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2173636156
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.489445057
Short name T260
Test name
Test status
Simulation time 246824384 ps
CPU time 1.01 seconds
Started Jul 03 04:27:56 PM PDT 24
Finished Jul 03 04:27:58 PM PDT 24
Peak memory 217380 kb
Host smart-c78e495a-4c72-4c75-8917-46531316c1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489445057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.489445057
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.732907486
Short name T18
Test name
Test status
Simulation time 138618256 ps
CPU time 0.84 seconds
Started Jul 03 04:28:12 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 199732 kb
Host smart-ecde8290-9a73-431b-8ef0-16eff159f942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732907486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.732907486
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.225001989
Short name T323
Test name
Test status
Simulation time 936699659 ps
CPU time 4.8 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 200400 kb
Host smart-fcdbd788-5c5c-4ac9-9133-5dd792c98436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225001989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.225001989
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3693261547
Short name T202
Test name
Test status
Simulation time 138117422 ps
CPU time 1.05 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 200076 kb
Host smart-605a8980-2cd2-4e39-9504-499d1a2daccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693261547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3693261547
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2052063957
Short name T248
Test name
Test status
Simulation time 184485960 ps
CPU time 1.37 seconds
Started Jul 03 04:28:32 PM PDT 24
Finished Jul 03 04:28:35 PM PDT 24
Peak memory 200276 kb
Host smart-51c32f04-af70-4f56-9beb-4fa14b38ab66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052063957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2052063957
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.156329728
Short name T34
Test name
Test status
Simulation time 3615439124 ps
CPU time 15.31 seconds
Started Jul 03 04:28:19 PM PDT 24
Finished Jul 03 04:28:36 PM PDT 24
Peak memory 210124 kb
Host smart-b4b57c4b-aa27-4abf-aa52-f8554f5f5bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156329728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.156329728
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.922878746
Short name T536
Test name
Test status
Simulation time 452460546 ps
CPU time 2.39 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:08 PM PDT 24
Peak memory 200032 kb
Host smart-f12a342f-c142-46ab-80e9-2091f76bab2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922878746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.922878746
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1430061643
Short name T206
Test name
Test status
Simulation time 146112434 ps
CPU time 1 seconds
Started Jul 03 04:28:20 PM PDT 24
Finished Jul 03 04:28:23 PM PDT 24
Peak memory 200052 kb
Host smart-98de1801-f0ae-4966-8c4c-fb0c913b132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430061643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1430061643
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3587769881
Short name T237
Test name
Test status
Simulation time 70070230 ps
CPU time 0.77 seconds
Started Jul 03 04:27:19 PM PDT 24
Finished Jul 03 04:27:21 PM PDT 24
Peak memory 199736 kb
Host smart-3f945847-beea-44f2-a9c0-63c8e5584a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587769881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3587769881
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3300283376
Short name T269
Test name
Test status
Simulation time 1225883402 ps
CPU time 5.55 seconds
Started Jul 03 04:27:32 PM PDT 24
Finished Jul 03 04:27:38 PM PDT 24
Peak memory 217616 kb
Host smart-ec116f7e-9cc5-4c18-85f2-bfa9de33bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300283376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3300283376
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2537273101
Short name T35
Test name
Test status
Simulation time 244699651 ps
CPU time 1.12 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 217424 kb
Host smart-d8019251-d139-4088-814e-0be11ee50f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537273101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2537273101
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2310138340
Short name T336
Test name
Test status
Simulation time 90616896 ps
CPU time 0.72 seconds
Started Jul 03 04:27:28 PM PDT 24
Finished Jul 03 04:27:29 PM PDT 24
Peak memory 199852 kb
Host smart-f5603771-9323-4ace-9a0a-928e0f1cf244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310138340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2310138340
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1395314214
Short name T426
Test name
Test status
Simulation time 1010756367 ps
CPU time 5.26 seconds
Started Jul 03 04:27:32 PM PDT 24
Finished Jul 03 04:27:38 PM PDT 24
Peak memory 200360 kb
Host smart-aad417f2-71be-495f-a2b8-617660470d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395314214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1395314214
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1461290746
Short name T74
Test name
Test status
Simulation time 17370045253 ps
CPU time 25.24 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:38 PM PDT 24
Peak memory 217224 kb
Host smart-30fbf183-cc91-470d-9c5b-9e23fac3d9b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461290746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1461290746
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.736457970
Short name T257
Test name
Test status
Simulation time 182040734 ps
CPU time 1.19 seconds
Started Jul 03 04:27:42 PM PDT 24
Finished Jul 03 04:27:44 PM PDT 24
Peak memory 200040 kb
Host smart-e3933b75-75f9-44d5-8931-2d487c13dea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736457970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.736457970
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.773743631
Short name T328
Test name
Test status
Simulation time 201025970 ps
CPU time 1.39 seconds
Started Jul 03 04:27:38 PM PDT 24
Finished Jul 03 04:27:39 PM PDT 24
Peak memory 200160 kb
Host smart-9953a3df-ea78-47a8-a022-669779ba4bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773743631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.773743631
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3647682296
Short name T187
Test name
Test status
Simulation time 387084047 ps
CPU time 2.31 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:08 PM PDT 24
Peak memory 208296 kb
Host smart-e4aaf9db-12e2-47f1-9f79-d32ffe520058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647682296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3647682296
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.969056396
Short name T5
Test name
Test status
Simulation time 91331144 ps
CPU time 0.86 seconds
Started Jul 03 04:27:03 PM PDT 24
Finished Jul 03 04:27:05 PM PDT 24
Peak memory 200056 kb
Host smart-19dc7000-0b9a-43ae-999a-adf2d347894f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969056396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.969056396
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1884923986
Short name T465
Test name
Test status
Simulation time 67063334 ps
CPU time 0.7 seconds
Started Jul 03 04:28:14 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 199856 kb
Host smart-76f5ff15-2f8f-4281-bfad-30ae141f8762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884923986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1884923986
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2488847684
Short name T306
Test name
Test status
Simulation time 1900134560 ps
CPU time 6.74 seconds
Started Jul 03 04:28:22 PM PDT 24
Finished Jul 03 04:28:29 PM PDT 24
Peak memory 229788 kb
Host smart-eed33583-425b-4d90-8102-5268aab03ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488847684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2488847684
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1445464689
Short name T212
Test name
Test status
Simulation time 244200066 ps
CPU time 1.05 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 217408 kb
Host smart-dfc14523-2977-4a58-8e97-8b92def900cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445464689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1445464689
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.4222893158
Short name T262
Test name
Test status
Simulation time 147859602 ps
CPU time 0.82 seconds
Started Jul 03 04:28:16 PM PDT 24
Finished Jul 03 04:28:18 PM PDT 24
Peak memory 199864 kb
Host smart-1a5e8740-34ef-4698-8738-80fc7fe9e127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222893158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.4222893158
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3903925617
Short name T105
Test name
Test status
Simulation time 1223714081 ps
CPU time 5.73 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:08 PM PDT 24
Peak memory 200388 kb
Host smart-bc4357d5-0499-4ae2-933e-f51fe7f75494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903925617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3903925617
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3347162387
Short name T77
Test name
Test status
Simulation time 145195339 ps
CPU time 1.04 seconds
Started Jul 03 04:28:06 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 200076 kb
Host smart-0d0fac49-c0a3-4a9f-b376-95f57e7f7bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347162387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3347162387
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.865703003
Short name T303
Test name
Test status
Simulation time 255983319 ps
CPU time 1.54 seconds
Started Jul 03 04:28:18 PM PDT 24
Finished Jul 03 04:28:20 PM PDT 24
Peak memory 200212 kb
Host smart-10b9608d-b98a-4ccc-8323-71653f91c60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865703003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.865703003
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1328487463
Short name T254
Test name
Test status
Simulation time 231236939 ps
CPU time 1.45 seconds
Started Jul 03 04:28:06 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 200280 kb
Host smart-bae17201-8262-49b8-be41-8c43d19b0686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328487463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1328487463
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3234781851
Short name T378
Test name
Test status
Simulation time 143490951 ps
CPU time 1.74 seconds
Started Jul 03 04:28:03 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 200032 kb
Host smart-39a88323-e7a5-429e-9f90-99000b0a2ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234781851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3234781851
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2627090673
Short name T135
Test name
Test status
Simulation time 207909242 ps
CPU time 1.25 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 200040 kb
Host smart-536d3bf7-88a3-4037-89cf-bd5a7a1f0c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627090673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2627090673
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.4144339175
Short name T345
Test name
Test status
Simulation time 77665163 ps
CPU time 0.8 seconds
Started Jul 03 04:28:08 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 199864 kb
Host smart-626c2ce0-8c9d-4c58-9e23-0d9278009f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144339175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.4144339175
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.78400355
Short name T9
Test name
Test status
Simulation time 2348099156 ps
CPU time 8.28 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 217804 kb
Host smart-853de760-7ae8-4050-8851-0550a2049ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78400355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.78400355
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1863708433
Short name T507
Test name
Test status
Simulation time 244492290 ps
CPU time 1.09 seconds
Started Jul 03 04:28:14 PM PDT 24
Finished Jul 03 04:28:17 PM PDT 24
Peak memory 217472 kb
Host smart-50f4079a-74f9-49f2-9cb7-71390bdde93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863708433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1863708433
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4182928684
Short name T425
Test name
Test status
Simulation time 100106825 ps
CPU time 0.74 seconds
Started Jul 03 04:28:16 PM PDT 24
Finished Jul 03 04:28:19 PM PDT 24
Peak memory 199868 kb
Host smart-092b0440-f04c-4096-9a06-8b55c62b31f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182928684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4182928684
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3662229026
Short name T377
Test name
Test status
Simulation time 776777885 ps
CPU time 3.99 seconds
Started Jul 03 04:28:20 PM PDT 24
Finished Jul 03 04:28:26 PM PDT 24
Peak memory 200304 kb
Host smart-faa5c111-3dda-4365-bf0a-c908085afde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662229026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3662229026
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4292229218
Short name T218
Test name
Test status
Simulation time 108531158 ps
CPU time 0.97 seconds
Started Jul 03 04:28:21 PM PDT 24
Finished Jul 03 04:28:24 PM PDT 24
Peak memory 200032 kb
Host smart-e6479c10-5711-4d90-a600-483cc1edd819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292229218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4292229218
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3595744562
Short name T54
Test name
Test status
Simulation time 217614330 ps
CPU time 1.42 seconds
Started Jul 03 04:28:11 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 200228 kb
Host smart-06232129-d8e6-46b5-b662-9ae508778f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595744562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3595744562
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.715826848
Short name T291
Test name
Test status
Simulation time 2777928771 ps
CPU time 12.86 seconds
Started Jul 03 04:28:15 PM PDT 24
Finished Jul 03 04:28:34 PM PDT 24
Peak memory 200296 kb
Host smart-1963152e-7b24-4215-8a1c-94fecf70788d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715826848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.715826848
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3414884839
Short name T428
Test name
Test status
Simulation time 137080378 ps
CPU time 1.73 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 200040 kb
Host smart-b9f46c7e-e760-451f-98a9-9c4428844cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414884839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3414884839
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.405516215
Short name T249
Test name
Test status
Simulation time 98905838 ps
CPU time 0.9 seconds
Started Jul 03 04:28:05 PM PDT 24
Finished Jul 03 04:28:11 PM PDT 24
Peak memory 200084 kb
Host smart-d44ee019-936a-49bd-90da-6e58e4351eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405516215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.405516215
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3244380544
Short name T480
Test name
Test status
Simulation time 75363743 ps
CPU time 0.73 seconds
Started Jul 03 04:28:14 PM PDT 24
Finished Jul 03 04:28:17 PM PDT 24
Peak memory 199864 kb
Host smart-01e12b46-76b5-4929-91a4-987b74532ab3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244380544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3244380544
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2010698061
Short name T327
Test name
Test status
Simulation time 1232949131 ps
CPU time 5.3 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:09 PM PDT 24
Peak memory 217744 kb
Host smart-93ddb5f0-4577-4958-bf56-cc490d5f97c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010698061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2010698061
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.483612421
Short name T398
Test name
Test status
Simulation time 243865052 ps
CPU time 1.15 seconds
Started Jul 03 04:28:13 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 217436 kb
Host smart-607a3d86-b091-47d0-94cd-7a93938f573a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483612421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.483612421
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1841212219
Short name T17
Test name
Test status
Simulation time 144273541 ps
CPU time 0.8 seconds
Started Jul 03 04:28:22 PM PDT 24
Finished Jul 03 04:28:24 PM PDT 24
Peak memory 199852 kb
Host smart-7815813c-59b0-4dbd-b626-a2bd4a4bd5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841212219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1841212219
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1988197282
Short name T396
Test name
Test status
Simulation time 1495092196 ps
CPU time 5.39 seconds
Started Jul 03 04:28:10 PM PDT 24
Finished Jul 03 04:28:19 PM PDT 24
Peak memory 200384 kb
Host smart-bf7c8026-c6d7-4087-b378-d365ed20f274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988197282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1988197282
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3412214377
Short name T230
Test name
Test status
Simulation time 113997103 ps
CPU time 1.05 seconds
Started Jul 03 04:28:10 PM PDT 24
Finished Jul 03 04:28:15 PM PDT 24
Peak memory 200040 kb
Host smart-f4c2c47e-4b52-424d-81ff-1e9557272e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412214377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3412214377
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2772065014
Short name T318
Test name
Test status
Simulation time 208401886 ps
CPU time 1.3 seconds
Started Jul 03 04:28:10 PM PDT 24
Finished Jul 03 04:28:15 PM PDT 24
Peak memory 200232 kb
Host smart-6a410134-0fce-46a5-8e6e-832bbc542bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772065014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2772065014
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3164018762
Short name T514
Test name
Test status
Simulation time 3500350820 ps
CPU time 13.37 seconds
Started Jul 03 04:28:03 PM PDT 24
Finished Jul 03 04:28:21 PM PDT 24
Peak memory 200308 kb
Host smart-767dd2a6-d31d-4d9e-a30d-69cc4be55c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164018762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3164018762
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.586856421
Short name T343
Test name
Test status
Simulation time 177443581 ps
CPU time 1.18 seconds
Started Jul 03 04:28:11 PM PDT 24
Finished Jul 03 04:28:15 PM PDT 24
Peak memory 200024 kb
Host smart-9bada52a-7bd5-4779-b9eb-02914dbf0a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586856421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.586856421
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2597628080
Short name T143
Test name
Test status
Simulation time 99275909 ps
CPU time 0.84 seconds
Started Jul 03 04:29:40 PM PDT 24
Finished Jul 03 04:29:41 PM PDT 24
Peak memory 199804 kb
Host smart-f1235abb-03fb-4b5c-919a-41c14d9951bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597628080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2597628080
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1355500978
Short name T42
Test name
Test status
Simulation time 2193012393 ps
CPU time 7.14 seconds
Started Jul 03 04:28:09 PM PDT 24
Finished Jul 03 04:28:20 PM PDT 24
Peak memory 220660 kb
Host smart-e9a5e0d7-2bbd-4699-9109-924d2e727b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355500978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1355500978
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.716281105
Short name T339
Test name
Test status
Simulation time 245362096 ps
CPU time 1.04 seconds
Started Jul 03 04:28:19 PM PDT 24
Finished Jul 03 04:28:21 PM PDT 24
Peak memory 217428 kb
Host smart-15d59891-7605-4b46-ada7-1fb1288e00f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716281105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.716281105
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3559710410
Short name T532
Test name
Test status
Simulation time 75161728 ps
CPU time 0.72 seconds
Started Jul 03 04:28:16 PM PDT 24
Finished Jul 03 04:28:18 PM PDT 24
Peak memory 199892 kb
Host smart-8599becc-67a6-4dc3-8f63-245f044c4cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559710410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3559710410
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1113223468
Short name T278
Test name
Test status
Simulation time 1506830938 ps
CPU time 5.29 seconds
Started Jul 03 04:28:18 PM PDT 24
Finished Jul 03 04:28:24 PM PDT 24
Peak memory 200308 kb
Host smart-e3989db5-f1db-488e-9da8-f50f4c525094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113223468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1113223468
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2605393962
Short name T482
Test name
Test status
Simulation time 177036053 ps
CPU time 1.15 seconds
Started Jul 03 04:28:16 PM PDT 24
Finished Jul 03 04:28:19 PM PDT 24
Peak memory 200048 kb
Host smart-f97d1be2-243b-41ef-9118-15846b7fa99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605393962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2605393962
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2254085936
Short name T308
Test name
Test status
Simulation time 111862660 ps
CPU time 1.17 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:01 PM PDT 24
Peak memory 200336 kb
Host smart-ef38ce37-80c4-4bcc-80c3-5e38336549ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254085936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2254085936
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1645750384
Short name T402
Test name
Test status
Simulation time 4001525125 ps
CPU time 16.29 seconds
Started Jul 03 04:29:19 PM PDT 24
Finished Jul 03 04:29:35 PM PDT 24
Peak memory 210276 kb
Host smart-98925b89-ef2c-44b3-a9e0-b692ded99a86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645750384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1645750384
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.913821165
Short name T155
Test name
Test status
Simulation time 291817151 ps
CPU time 1.8 seconds
Started Jul 03 04:28:09 PM PDT 24
Finished Jul 03 04:28:15 PM PDT 24
Peak memory 199796 kb
Host smart-7d2763a1-c465-42f2-be83-771849a6e63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913821165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.913821165
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2267942704
Short name T350
Test name
Test status
Simulation time 132439131 ps
CPU time 0.93 seconds
Started Jul 03 04:28:13 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 200040 kb
Host smart-7024b2fe-aa0f-4f5a-a447-796f53d44810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267942704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2267942704
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.4145902764
Short name T138
Test name
Test status
Simulation time 69407026 ps
CPU time 0.79 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:06 PM PDT 24
Peak memory 199864 kb
Host smart-e6db8b3c-6373-4374-99e3-c10b1b8618d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145902764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4145902764
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3563461862
Short name T44
Test name
Test status
Simulation time 2343378580 ps
CPU time 7.58 seconds
Started Jul 03 04:28:15 PM PDT 24
Finished Jul 03 04:28:24 PM PDT 24
Peak memory 217872 kb
Host smart-e8129745-bf26-40ac-bfa4-11ea8fca3a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563461862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3563461862
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.206807005
Short name T284
Test name
Test status
Simulation time 245030073 ps
CPU time 1.02 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:05 PM PDT 24
Peak memory 217480 kb
Host smart-fb654f1e-84a5-407a-a39b-4c629b6647ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206807005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.206807005
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1183075410
Short name T526
Test name
Test status
Simulation time 111374476 ps
CPU time 0.79 seconds
Started Jul 03 04:28:00 PM PDT 24
Finished Jul 03 04:28:02 PM PDT 24
Peak memory 199732 kb
Host smart-a50fa84c-ecdd-4a40-9947-724fb26e0247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183075410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1183075410
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.804302219
Short name T267
Test name
Test status
Simulation time 1743076777 ps
CPU time 6.69 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:12 PM PDT 24
Peak memory 200344 kb
Host smart-37b09cc6-1e12-42fa-990d-b43c4d3e79d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804302219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.804302219
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2626222809
Short name T189
Test name
Test status
Simulation time 175450707 ps
CPU time 1.19 seconds
Started Jul 03 04:28:00 PM PDT 24
Finished Jul 03 04:28:02 PM PDT 24
Peak memory 199956 kb
Host smart-5f23140e-ecb8-4fa8-8781-b221fd4faa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626222809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2626222809
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1028161241
Short name T246
Test name
Test status
Simulation time 122910137 ps
CPU time 1.15 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:06 PM PDT 24
Peak memory 200248 kb
Host smart-c18a7c04-eeaf-41fd-b938-19ef22f51a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028161241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1028161241
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.785988169
Short name T499
Test name
Test status
Simulation time 10487824906 ps
CPU time 35.1 seconds
Started Jul 03 04:28:15 PM PDT 24
Finished Jul 03 04:28:51 PM PDT 24
Peak memory 208496 kb
Host smart-31ae0566-0b3c-4a94-b848-cb021ebf9072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785988169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.785988169
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1900211247
Short name T270
Test name
Test status
Simulation time 151784141 ps
CPU time 1.85 seconds
Started Jul 03 04:28:09 PM PDT 24
Finished Jul 03 04:28:15 PM PDT 24
Peak memory 200020 kb
Host smart-b3e50f69-e45e-44fc-893f-41b12b08a1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900211247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1900211247
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.4063602512
Short name T515
Test name
Test status
Simulation time 243491982 ps
CPU time 1.39 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:05 PM PDT 24
Peak memory 200264 kb
Host smart-c0a41110-ec8f-4805-ac7f-72b4b94eb1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063602512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.4063602512
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4117426310
Short name T488
Test name
Test status
Simulation time 70152105 ps
CPU time 0.78 seconds
Started Jul 03 04:29:40 PM PDT 24
Finished Jul 03 04:29:41 PM PDT 24
Peak memory 199792 kb
Host smart-7301dd4c-a5da-4a88-9678-fd3b1875f00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117426310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4117426310
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3832484252
Short name T324
Test name
Test status
Simulation time 1879297635 ps
CPU time 6.97 seconds
Started Jul 03 04:28:10 PM PDT 24
Finished Jul 03 04:28:21 PM PDT 24
Peak memory 217648 kb
Host smart-357183cb-4834-48ea-bbb9-8af60031e1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832484252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3832484252
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2022209589
Short name T307
Test name
Test status
Simulation time 247189587 ps
CPU time 1.02 seconds
Started Jul 03 04:27:56 PM PDT 24
Finished Jul 03 04:27:58 PM PDT 24
Peak memory 217444 kb
Host smart-15b29209-95b2-4a39-a5b7-a74c80022595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022209589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2022209589
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3173231777
Short name T216
Test name
Test status
Simulation time 81413191 ps
CPU time 0.72 seconds
Started Jul 03 04:28:05 PM PDT 24
Finished Jul 03 04:28:12 PM PDT 24
Peak memory 199904 kb
Host smart-9d24ddfc-84db-4b66-a7b5-bf193c9bcf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173231777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3173231777
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2712422674
Short name T389
Test name
Test status
Simulation time 800879722 ps
CPU time 3.67 seconds
Started Jul 03 04:28:00 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 200320 kb
Host smart-397f454b-70fe-4ede-bfbe-77307e6f28d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712422674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2712422674
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.320135852
Short name T214
Test name
Test status
Simulation time 97454212 ps
CPU time 1 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 200076 kb
Host smart-ef5bcdac-ab8f-4d32-99fa-7d8f5a7ad3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320135852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.320135852
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3913814018
Short name T438
Test name
Test status
Simulation time 114698316 ps
CPU time 1.16 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:03 PM PDT 24
Peak memory 200136 kb
Host smart-60833f65-c7ea-4947-941d-48498094ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913814018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3913814018
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.553194970
Short name T410
Test name
Test status
Simulation time 3743723635 ps
CPU time 11.96 seconds
Started Jul 03 04:28:20 PM PDT 24
Finished Jul 03 04:28:34 PM PDT 24
Peak memory 200432 kb
Host smart-c337e59f-436e-4008-8d15-48753237d545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553194970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.553194970
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2755962053
Short name T333
Test name
Test status
Simulation time 123945172 ps
CPU time 1.52 seconds
Started Jul 03 04:28:21 PM PDT 24
Finished Jul 03 04:28:24 PM PDT 24
Peak memory 208224 kb
Host smart-a575228a-0b00-460f-8c63-c0e2edfc3862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755962053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2755962053
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2621239171
Short name T163
Test name
Test status
Simulation time 159070636 ps
CPU time 1.3 seconds
Started Jul 03 04:28:13 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 200244 kb
Host smart-4a379bc9-414a-423d-8c64-7d53d0d449b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621239171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2621239171
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.140595029
Short name T436
Test name
Test status
Simulation time 124573867 ps
CPU time 0.93 seconds
Started Jul 03 04:28:21 PM PDT 24
Finished Jul 03 04:28:23 PM PDT 24
Peak memory 199856 kb
Host smart-aa0ae333-734b-4350-8763-f8a043eab014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140595029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.140595029
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1851436266
Short name T32
Test name
Test status
Simulation time 2358349073 ps
CPU time 8.16 seconds
Started Jul 03 04:28:17 PM PDT 24
Finished Jul 03 04:28:26 PM PDT 24
Peak memory 217584 kb
Host smart-8514fafe-360b-4f90-bc82-7089acd943c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851436266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1851436266
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1353820392
Short name T180
Test name
Test status
Simulation time 243481914 ps
CPU time 1.08 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 217360 kb
Host smart-8110c64f-88d1-4b2c-8e50-baff489480f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353820392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1353820392
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1829207963
Short name T337
Test name
Test status
Simulation time 115690567 ps
CPU time 0.8 seconds
Started Jul 03 04:28:31 PM PDT 24
Finished Jul 03 04:28:33 PM PDT 24
Peak memory 199880 kb
Host smart-8a4ed9ae-2bd4-42a7-a7de-2a8bb06c6adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829207963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1829207963
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2928294423
Short name T99
Test name
Test status
Simulation time 711402881 ps
CPU time 3.57 seconds
Started Jul 03 04:28:20 PM PDT 24
Finished Jul 03 04:28:26 PM PDT 24
Peak memory 200404 kb
Host smart-f4a50c71-c4d2-43fd-bc16-f49d109bec67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928294423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2928294423
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3072149926
Short name T146
Test name
Test status
Simulation time 180613202 ps
CPU time 1.16 seconds
Started Jul 03 04:28:13 PM PDT 24
Finished Jul 03 04:28:16 PM PDT 24
Peak memory 199924 kb
Host smart-d41ed728-4135-4414-8d36-2344ccf143b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072149926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3072149926
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4170548011
Short name T459
Test name
Test status
Simulation time 113527457 ps
CPU time 1.21 seconds
Started Jul 03 04:28:10 PM PDT 24
Finished Jul 03 04:28:15 PM PDT 24
Peak memory 200296 kb
Host smart-3670f1c2-6a5f-4c95-b33a-2db3b2893859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170548011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4170548011
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2069824106
Short name T379
Test name
Test status
Simulation time 13445517336 ps
CPU time 48.47 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:57 PM PDT 24
Peak memory 200428 kb
Host smart-a4ee4158-266f-4cd5-a94a-ec7a6cb6c682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069824106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2069824106
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3593557664
Short name T196
Test name
Test status
Simulation time 254034937 ps
CPU time 1.79 seconds
Started Jul 03 04:28:47 PM PDT 24
Finished Jul 03 04:28:49 PM PDT 24
Peak memory 200096 kb
Host smart-c50ad43e-d110-4b72-9375-e346a55d0cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593557664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3593557664
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.67830639
Short name T421
Test name
Test status
Simulation time 64953721 ps
CPU time 0.76 seconds
Started Jul 03 04:28:15 PM PDT 24
Finished Jul 03 04:28:17 PM PDT 24
Peak memory 200084 kb
Host smart-fe22611f-21aa-4621-90dc-82fa747384ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67830639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.67830639
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.82103792
Short name T222
Test name
Test status
Simulation time 67024226 ps
CPU time 0.74 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:05 PM PDT 24
Peak memory 199892 kb
Host smart-d1a84c98-cace-4309-b461-72a7dfcba773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82103792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.82103792
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1820288446
Short name T46
Test name
Test status
Simulation time 1234838657 ps
CPU time 5.44 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:08 PM PDT 24
Peak memory 217528 kb
Host smart-501f35ee-d469-4cff-8473-63920ca3fd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820288446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1820288446
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4128579687
Short name T513
Test name
Test status
Simulation time 244157451 ps
CPU time 1.12 seconds
Started Jul 03 04:28:09 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 217428 kb
Host smart-580b8be7-0703-468a-9aa2-5534696168f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128579687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4128579687
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2440471167
Short name T355
Test name
Test status
Simulation time 104285114 ps
CPU time 0.82 seconds
Started Jul 03 04:28:05 PM PDT 24
Finished Jul 03 04:28:11 PM PDT 24
Peak memory 199852 kb
Host smart-c779d61b-28f0-4f13-9442-4340cbb95a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440471167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2440471167
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3526282105
Short name T309
Test name
Test status
Simulation time 1936541720 ps
CPU time 6.75 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:11 PM PDT 24
Peak memory 200376 kb
Host smart-21140d20-ee2b-498a-930f-a27f8653ba9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526282105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3526282105
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2722552598
Short name T57
Test name
Test status
Simulation time 150329510 ps
CPU time 1.08 seconds
Started Jul 03 04:28:11 PM PDT 24
Finished Jul 03 04:28:15 PM PDT 24
Peak memory 200016 kb
Host smart-f0fb14be-ffc1-429a-bdd7-a2038c90ab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722552598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2722552598
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4148228210
Short name T346
Test name
Test status
Simulation time 116414595 ps
CPU time 1.11 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:03 PM PDT 24
Peak memory 200280 kb
Host smart-87b574e0-7cbb-4307-a2a0-81411f6e7090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148228210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4148228210
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3814586326
Short name T329
Test name
Test status
Simulation time 10194700490 ps
CPU time 38.01 seconds
Started Jul 03 04:28:03 PM PDT 24
Finished Jul 03 04:28:45 PM PDT 24
Peak memory 209836 kb
Host smart-3fe06776-ef3c-4b63-a5ae-279d7cac1297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814586326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3814586326
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2806712028
Short name T193
Test name
Test status
Simulation time 362739976 ps
CPU time 1.96 seconds
Started Jul 03 04:29:35 PM PDT 24
Finished Jul 03 04:29:38 PM PDT 24
Peak memory 199984 kb
Host smart-4484562e-4712-44e2-aebb-d270eeabc09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806712028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2806712028
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2593959698
Short name T400
Test name
Test status
Simulation time 159901814 ps
CPU time 1.3 seconds
Started Jul 03 04:28:18 PM PDT 24
Finished Jul 03 04:28:21 PM PDT 24
Peak memory 200256 kb
Host smart-25a71999-0d73-4e65-93cb-6567cc7aa969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593959698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2593959698
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.454264818
Short name T477
Test name
Test status
Simulation time 103124496 ps
CPU time 0.83 seconds
Started Jul 03 04:28:16 PM PDT 24
Finished Jul 03 04:28:18 PM PDT 24
Peak memory 199896 kb
Host smart-142317d7-ed49-4f63-b2e0-b81f25bfb30b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454264818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.454264818
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.646144353
Short name T283
Test name
Test status
Simulation time 1211872325 ps
CPU time 5.52 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 221584 kb
Host smart-84bf08c1-2468-4aa1-b825-54781d73986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646144353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.646144353
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1930055152
Short name T36
Test name
Test status
Simulation time 244082546 ps
CPU time 1.05 seconds
Started Jul 03 04:28:20 PM PDT 24
Finished Jul 03 04:28:22 PM PDT 24
Peak memory 217432 kb
Host smart-b1e90a90-f2f3-42bf-a133-e08e7ed4238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930055152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1930055152
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2844575395
Short name T268
Test name
Test status
Simulation time 138998966 ps
CPU time 0.77 seconds
Started Jul 03 04:29:18 PM PDT 24
Finished Jul 03 04:29:19 PM PDT 24
Peak memory 199724 kb
Host smart-a1a2cf53-a8cd-4bd0-8e19-674a5cdbfca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844575395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2844575395
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2063779670
Short name T484
Test name
Test status
Simulation time 1274675594 ps
CPU time 4.62 seconds
Started Jul 03 04:29:28 PM PDT 24
Finished Jul 03 04:29:33 PM PDT 24
Peak memory 200240 kb
Host smart-fd7d81d0-fa15-4172-8ecb-72f40c802d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063779670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2063779670
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.4044064203
Short name T133
Test name
Test status
Simulation time 142316006 ps
CPU time 1.09 seconds
Started Jul 03 04:28:05 PM PDT 24
Finished Jul 03 04:28:12 PM PDT 24
Peak memory 200040 kb
Host smart-b84e2536-899f-4775-8d29-c8c358d3693d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044064203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.4044064203
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3416820034
Short name T326
Test name
Test status
Simulation time 255234861 ps
CPU time 1.51 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 200248 kb
Host smart-ca2cd8cb-2130-42d5-822a-f1bd26b44a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416820034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3416820034
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.541617919
Short name T353
Test name
Test status
Simulation time 1244211401 ps
CPU time 5.72 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:09 PM PDT 24
Peak memory 208576 kb
Host smart-868c8e0d-2616-411a-81ef-5d481f42bf57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541617919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.541617919
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3802180595
Short name T370
Test name
Test status
Simulation time 370574118 ps
CPU time 2.21 seconds
Started Jul 03 04:29:38 PM PDT 24
Finished Jul 03 04:29:40 PM PDT 24
Peak memory 200012 kb
Host smart-3b772bc8-9feb-46de-b960-3110abfc6b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802180595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3802180595
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3430129380
Short name T53
Test name
Test status
Simulation time 169697476 ps
CPU time 1.3 seconds
Started Jul 03 04:28:02 PM PDT 24
Finished Jul 03 04:28:06 PM PDT 24
Peak memory 200344 kb
Host smart-72b85f23-84dc-4269-8bc2-49d996597594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430129380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3430129380
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3708965162
Short name T383
Test name
Test status
Simulation time 64202472 ps
CPU time 0.71 seconds
Started Jul 03 04:28:23 PM PDT 24
Finished Jul 03 04:28:25 PM PDT 24
Peak memory 199812 kb
Host smart-a2f8ccd2-4024-4941-9cfa-74c207ed3bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708965162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3708965162
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.652259514
Short name T394
Test name
Test status
Simulation time 1902549750 ps
CPU time 7.14 seconds
Started Jul 03 04:27:59 PM PDT 24
Finished Jul 03 04:28:19 PM PDT 24
Peak memory 218032 kb
Host smart-41901412-6f8f-42d2-aa38-376bc5109fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652259514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.652259514
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2390564019
Short name T360
Test name
Test status
Simulation time 243865208 ps
CPU time 1.08 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:05 PM PDT 24
Peak memory 217464 kb
Host smart-2f439b41-8f81-4a31-bf9d-75f4b13f1830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390564019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2390564019
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3527105729
Short name T20
Test name
Test status
Simulation time 130908856 ps
CPU time 0.83 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:10 PM PDT 24
Peak memory 199900 kb
Host smart-6f39e52d-bd26-4b28-bb85-1c61143d8759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527105729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3527105729
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2333295855
Short name T152
Test name
Test status
Simulation time 711697193 ps
CPU time 3.51 seconds
Started Jul 03 04:28:19 PM PDT 24
Finished Jul 03 04:28:23 PM PDT 24
Peak memory 200340 kb
Host smart-a29ca421-9668-48c6-9ba0-1c6a4dd5509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333295855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2333295855
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2398848092
Short name T236
Test name
Test status
Simulation time 109647365 ps
CPU time 1 seconds
Started Jul 03 04:28:17 PM PDT 24
Finished Jul 03 04:28:20 PM PDT 24
Peak memory 200020 kb
Host smart-77194cd3-b5a2-4095-a17d-630d599c1172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398848092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2398848092
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2414894841
Short name T227
Test name
Test status
Simulation time 252606727 ps
CPU time 1.45 seconds
Started Jul 03 04:28:01 PM PDT 24
Finished Jul 03 04:28:05 PM PDT 24
Peak memory 200292 kb
Host smart-7ebc4c93-7c1e-4709-91ed-b6127475c47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414894841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2414894841
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2821189170
Short name T316
Test name
Test status
Simulation time 6833287325 ps
CPU time 22.78 seconds
Started Jul 03 04:28:04 PM PDT 24
Finished Jul 03 04:28:31 PM PDT 24
Peak memory 200448 kb
Host smart-84579f7f-5e2b-4c40-b61c-3a33b932d79a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821189170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2821189170
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2372471440
Short name T231
Test name
Test status
Simulation time 353622315 ps
CPU time 2.36 seconds
Started Jul 03 04:28:16 PM PDT 24
Finished Jul 03 04:28:20 PM PDT 24
Peak memory 200092 kb
Host smart-d27d530d-04ca-4f04-8ae6-7ff918c4c205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372471440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2372471440
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1543378327
Short name T160
Test name
Test status
Simulation time 109701054 ps
CPU time 0.93 seconds
Started Jul 03 04:28:26 PM PDT 24
Finished Jul 03 04:28:28 PM PDT 24
Peak memory 200060 kb
Host smart-53da873a-04f3-45ca-9c2f-dd88fac7de24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543378327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1543378327
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.128229018
Short name T176
Test name
Test status
Simulation time 88897342 ps
CPU time 0.8 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:13 PM PDT 24
Peak memory 199848 kb
Host smart-e581e2e7-1eb6-4b16-aea3-2d8c7505120a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128229018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.128229018
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2477617993
Short name T235
Test name
Test status
Simulation time 2372046019 ps
CPU time 8.93 seconds
Started Jul 03 04:27:30 PM PDT 24
Finished Jul 03 04:27:39 PM PDT 24
Peak memory 217672 kb
Host smart-04742b68-d6ad-4d9e-9711-30fd8ceea5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477617993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2477617993
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.238849924
Short name T320
Test name
Test status
Simulation time 243992275 ps
CPU time 1.06 seconds
Started Jul 03 04:27:43 PM PDT 24
Finished Jul 03 04:27:44 PM PDT 24
Peak memory 217448 kb
Host smart-ede173ff-10e7-4ee3-90ba-d4c874557929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238849924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.238849924
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2922840590
Short name T277
Test name
Test status
Simulation time 121608946 ps
CPU time 0.75 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 199692 kb
Host smart-6b6cfa32-cdd9-4560-8088-81504ebe355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922840590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2922840590
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.795882708
Short name T347
Test name
Test status
Simulation time 1373826373 ps
CPU time 4.95 seconds
Started Jul 03 04:27:02 PM PDT 24
Finished Jul 03 04:27:08 PM PDT 24
Peak memory 200276 kb
Host smart-6e116fb5-6ce1-4f5f-bf18-e9c403f0cac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795882708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.795882708
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3706777448
Short name T457
Test name
Test status
Simulation time 100027238 ps
CPU time 0.98 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:08 PM PDT 24
Peak memory 199952 kb
Host smart-1f7da76e-57e3-4a41-bded-bf42737028e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706777448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3706777448
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2943064238
Short name T63
Test name
Test status
Simulation time 220321269 ps
CPU time 1.42 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:13 PM PDT 24
Peak memory 200240 kb
Host smart-248328e2-24fa-49a2-9e0d-61dc1e04ef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943064238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2943064238
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3429541974
Short name T418
Test name
Test status
Simulation time 12801548343 ps
CPU time 48.01 seconds
Started Jul 03 04:27:37 PM PDT 24
Finished Jul 03 04:28:25 PM PDT 24
Peak memory 208612 kb
Host smart-d3ec9098-cf00-4631-b02a-1ae623e9c808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429541974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3429541974
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3938944245
Short name T512
Test name
Test status
Simulation time 452788157 ps
CPU time 2.52 seconds
Started Jul 03 04:27:01 PM PDT 24
Finished Jul 03 04:27:05 PM PDT 24
Peak memory 200132 kb
Host smart-ebcd4bd1-45ff-45f5-9fcc-2f2c49284852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938944245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3938944245
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2969077328
Short name T232
Test name
Test status
Simulation time 226364989 ps
CPU time 1.33 seconds
Started Jul 03 04:27:02 PM PDT 24
Finished Jul 03 04:27:04 PM PDT 24
Peak memory 200044 kb
Host smart-844971fb-c7d8-420f-ae98-a65e876a871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969077328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2969077328
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3618047886
Short name T149
Test name
Test status
Simulation time 70945755 ps
CPU time 0.75 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 199836 kb
Host smart-fcd7ea2e-45c6-436a-b747-fd357865a737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618047886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3618047886
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2785830526
Short name T302
Test name
Test status
Simulation time 1231076468 ps
CPU time 5.92 seconds
Started Jul 03 04:27:09 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 221584 kb
Host smart-83f794ae-d311-41d6-af6b-75f3f3f0e8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785830526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2785830526
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.426016494
Short name T467
Test name
Test status
Simulation time 244791117 ps
CPU time 1.01 seconds
Started Jul 03 04:27:09 PM PDT 24
Finished Jul 03 04:27:12 PM PDT 24
Peak memory 217380 kb
Host smart-9408cd35-10ab-483b-a576-0455b97bb3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426016494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.426016494
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1894606392
Short name T171
Test name
Test status
Simulation time 167207597 ps
CPU time 0.85 seconds
Started Jul 03 04:28:28 PM PDT 24
Finished Jul 03 04:28:30 PM PDT 24
Peak memory 198848 kb
Host smart-ac19d49b-9a83-4c62-8c2a-0dada17ecfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894606392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1894606392
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2401938974
Short name T508
Test name
Test status
Simulation time 1196089053 ps
CPU time 4.81 seconds
Started Jul 03 04:28:55 PM PDT 24
Finished Jul 03 04:29:00 PM PDT 24
Peak memory 200284 kb
Host smart-0aa9a8dc-9983-4a19-a5e4-7e4b5e6c29ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401938974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2401938974
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1854399090
Short name T299
Test name
Test status
Simulation time 165356228 ps
CPU time 1.16 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 199996 kb
Host smart-1fa960c5-9cf1-4434-a6af-083aeaa68455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854399090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1854399090
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2467577751
Short name T244
Test name
Test status
Simulation time 129117689 ps
CPU time 1.16 seconds
Started Jul 03 04:27:33 PM PDT 24
Finished Jul 03 04:27:35 PM PDT 24
Peak memory 200256 kb
Host smart-3cffdd31-2647-44d1-bad0-46f9b85db13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467577751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2467577751
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2394913622
Short name T173
Test name
Test status
Simulation time 2469593710 ps
CPU time 9.38 seconds
Started Jul 03 04:27:33 PM PDT 24
Finished Jul 03 04:27:43 PM PDT 24
Peak memory 208572 kb
Host smart-c484d672-05fc-4347-b947-b5ea1885e7db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394913622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2394913622
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.846919603
Short name T190
Test name
Test status
Simulation time 141941419 ps
CPU time 1.71 seconds
Started Jul 03 04:27:26 PM PDT 24
Finished Jul 03 04:27:28 PM PDT 24
Peak memory 200068 kb
Host smart-bb511515-44e8-4592-868e-68bf7f1aa6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846919603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.846919603
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3416359724
Short name T435
Test name
Test status
Simulation time 93902754 ps
CPU time 0.82 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:12 PM PDT 24
Peak memory 200032 kb
Host smart-ee370e8f-7190-4612-9a8d-ab1287521460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416359724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3416359724
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1728362190
Short name T185
Test name
Test status
Simulation time 53401036 ps
CPU time 0.68 seconds
Started Jul 03 04:27:18 PM PDT 24
Finished Jul 03 04:27:19 PM PDT 24
Peak memory 199828 kb
Host smart-dbb81c20-48e8-45a5-9d12-21d0bf3dfc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728362190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1728362190
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3116620638
Short name T51
Test name
Test status
Simulation time 1233008971 ps
CPU time 5.26 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 217280 kb
Host smart-65c40db7-4f98-4efa-809b-d7eb839aaf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116620638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3116620638
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.847209706
Short name T162
Test name
Test status
Simulation time 244398846 ps
CPU time 1.08 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:11 PM PDT 24
Peak memory 217404 kb
Host smart-e2570feb-8c8a-44fe-b672-60e38bf71e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847209706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.847209706
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.747606885
Short name T503
Test name
Test status
Simulation time 85161533 ps
CPU time 0.72 seconds
Started Jul 03 04:27:01 PM PDT 24
Finished Jul 03 04:27:02 PM PDT 24
Peak memory 200180 kb
Host smart-f960aaa6-4642-4db5-bf20-79d49ac3627c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747606885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.747606885
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3651539211
Short name T376
Test name
Test status
Simulation time 980873047 ps
CPU time 4.48 seconds
Started Jul 03 04:27:05 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 200360 kb
Host smart-d36b499b-27de-4fc3-956e-8a4da05b2091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651539211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3651539211
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1788493388
Short name T223
Test name
Test status
Simulation time 149578480 ps
CPU time 1.11 seconds
Started Jul 03 04:27:09 PM PDT 24
Finished Jul 03 04:27:12 PM PDT 24
Peak memory 200004 kb
Host smart-a3f29f25-42fb-4781-ab18-1d62dae6aa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788493388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1788493388
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4001217488
Short name T317
Test name
Test status
Simulation time 116067936 ps
CPU time 1.29 seconds
Started Jul 03 04:27:40 PM PDT 24
Finished Jul 03 04:27:42 PM PDT 24
Peak memory 200264 kb
Host smart-a9dfe9a6-77fe-4fb3-ba46-acacfc5d1577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001217488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4001217488
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.4254398161
Short name T89
Test name
Test status
Simulation time 11961412203 ps
CPU time 38.83 seconds
Started Jul 03 04:27:09 PM PDT 24
Finished Jul 03 04:27:50 PM PDT 24
Peak memory 208488 kb
Host smart-8b885140-9fc2-45db-a987-09ea5bca2008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254398161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.4254398161
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1296001921
Short name T393
Test name
Test status
Simulation time 348916138 ps
CPU time 2.17 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:19 PM PDT 24
Peak memory 200056 kb
Host smart-d0b19e92-5d79-422c-81d8-5356a459e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296001921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1296001921
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1673859666
Short name T522
Test name
Test status
Simulation time 72742941 ps
CPU time 0.84 seconds
Started Jul 03 04:27:40 PM PDT 24
Finished Jul 03 04:27:41 PM PDT 24
Peak memory 200052 kb
Host smart-3cf60925-3fb2-4c1f-9bf8-4822d9b7fafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673859666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1673859666
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3405352640
Short name T473
Test name
Test status
Simulation time 85107747 ps
CPU time 0.77 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 199880 kb
Host smart-1669f9fc-8935-42de-9ed8-8ff6cc17bc02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405352640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3405352640
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1898529963
Short name T43
Test name
Test status
Simulation time 2349180979 ps
CPU time 8.25 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:21 PM PDT 24
Peak memory 217608 kb
Host smart-2d4f9a51-003d-4979-8016-29126ef0bf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898529963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1898529963
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1201323494
Short name T500
Test name
Test status
Simulation time 244654077 ps
CPU time 1.04 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 217380 kb
Host smart-c5ca49a6-9e33-46d1-9161-0e1568418c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201323494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1201323494
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3246602900
Short name T358
Test name
Test status
Simulation time 137820219 ps
CPU time 0.81 seconds
Started Jul 03 04:27:29 PM PDT 24
Finished Jul 03 04:27:30 PM PDT 24
Peak memory 199836 kb
Host smart-239d5b6b-18eb-45bb-98c8-2a7f5219b337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246602900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3246602900
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2054466103
Short name T250
Test name
Test status
Simulation time 1626083492 ps
CPU time 6.41 seconds
Started Jul 03 04:27:24 PM PDT 24
Finished Jul 03 04:27:31 PM PDT 24
Peak memory 200272 kb
Host smart-ccbcb694-91ee-45ec-b842-6713ace11f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054466103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2054466103
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1852847564
Short name T340
Test name
Test status
Simulation time 142243199 ps
CPU time 1.07 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 199976 kb
Host smart-481321b6-730e-4381-8637-af587284a396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852847564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1852847564
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1201702855
Short name T213
Test name
Test status
Simulation time 254869822 ps
CPU time 1.48 seconds
Started Jul 03 04:27:20 PM PDT 24
Finished Jul 03 04:27:21 PM PDT 24
Peak memory 200296 kb
Host smart-9c65e20b-01e9-4138-b41b-3100edc98b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201702855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1201702855
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2583369189
Short name T391
Test name
Test status
Simulation time 7074622971 ps
CPU time 25.91 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:36 PM PDT 24
Peak memory 208604 kb
Host smart-5a76b9f2-4a06-4dab-999b-115c2c1078dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583369189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2583369189
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3797514885
Short name T296
Test name
Test status
Simulation time 356038746 ps
CPU time 2.41 seconds
Started Jul 03 04:27:21 PM PDT 24
Finished Jul 03 04:27:24 PM PDT 24
Peak memory 200048 kb
Host smart-e459fb03-8b08-4aca-9712-c14eab56860e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797514885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3797514885
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2520428101
Short name T86
Test name
Test status
Simulation time 86830512 ps
CPU time 0.86 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 200020 kb
Host smart-52630c80-c377-4464-a8d6-801dabf05925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520428101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2520428101
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2620331941
Short name T158
Test name
Test status
Simulation time 62819932 ps
CPU time 0.83 seconds
Started Jul 03 04:27:03 PM PDT 24
Finished Jul 03 04:27:04 PM PDT 24
Peak memory 199872 kb
Host smart-1e2e9db4-e4b1-472b-b860-0113eb634685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620331941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2620331941
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3221545373
Short name T259
Test name
Test status
Simulation time 1904749988 ps
CPU time 6.84 seconds
Started Jul 03 04:27:35 PM PDT 24
Finished Jul 03 04:27:42 PM PDT 24
Peak memory 217664 kb
Host smart-956b9675-e4d9-4013-bd0e-20696cd07d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221545373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3221545373
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.548601550
Short name T530
Test name
Test status
Simulation time 244832168 ps
CPU time 1.08 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 217396 kb
Host smart-3e277230-8967-4bc4-ba95-c257c310ba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548601550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.548601550
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2511808880
Short name T460
Test name
Test status
Simulation time 136204186 ps
CPU time 0.77 seconds
Started Jul 03 04:27:12 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 199812 kb
Host smart-523e9ac6-f0d2-4308-af82-2810b03ceb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511808880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2511808880
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.715921547
Short name T474
Test name
Test status
Simulation time 1656874895 ps
CPU time 5.94 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:17 PM PDT 24
Peak memory 200276 kb
Host smart-cf758c77-622b-470f-bb42-a0e544120831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715921547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.715921547
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1559659709
Short name T211
Test name
Test status
Simulation time 106324489 ps
CPU time 0.99 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:13 PM PDT 24
Peak memory 199968 kb
Host smart-af1bd163-9425-4464-9032-13dc8aaf3eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559659709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1559659709
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4241678972
Short name T64
Test name
Test status
Simulation time 118611077 ps
CPU time 1.19 seconds
Started Jul 03 04:27:08 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 200212 kb
Host smart-536c608a-c557-4170-b548-95c1957182b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241678972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4241678972
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2698693064
Short name T447
Test name
Test status
Simulation time 4036308415 ps
CPU time 17.18 seconds
Started Jul 03 04:27:09 PM PDT 24
Finished Jul 03 04:27:29 PM PDT 24
Peak memory 208452 kb
Host smart-dfd099f6-a73a-4989-a85a-10129fed2917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698693064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2698693064
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1515105614
Short name T239
Test name
Test status
Simulation time 137481802 ps
CPU time 1.61 seconds
Started Jul 03 04:27:23 PM PDT 24
Finished Jul 03 04:27:25 PM PDT 24
Peak memory 208140 kb
Host smart-ef6d2553-0f43-42df-b83e-e5077d1d70bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515105614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1515105614
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2631793740
Short name T471
Test name
Test status
Simulation time 72869671 ps
CPU time 0.82 seconds
Started Jul 03 04:27:22 PM PDT 24
Finished Jul 03 04:27:23 PM PDT 24
Peak memory 200048 kb
Host smart-35ca0a58-2de2-43da-ab6d-a39b1d5188ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631793740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2631793740
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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