Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7763

1

T1

116

T6

31

T16

3

auto[1]

10692

1

T1

117

T2

4

T3

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5779	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6261	1			T1	72		T2	2		T3	2
reset_info_cp[2]	2856	1			T1	44		T2	1		T3	1
reset_info_cp[4]	3672	1			T1	55		T2	1		T3	1
reset_info_cp[8]	89	1			T1	1		T80	1		T90	1
reset_info_cp[16]	107	1			T1	1		T12	1		T29	1
reset_info_cp[32]	106	1			T1	1		T28	1		T29	1
reset_info_cp[64]	102	1			T1	2		T6	1		T29	1
reset_info_cp[128]	103	1			T16	2		T29	2		T125	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2962	1			T1	37		T6	8		T28	7
reset_info_cp[1]	auto[1]	2679	1			T1	34		T2	1		T3	1
reset_info_cp[2]	auto[0]	880	1			T1	21		T6	5		T28	2
reset_info_cp[2]	auto[1]	1976	1			T1	23		T2	1		T3	1
reset_info_cp[4]	auto[0]	1319	1			T1	22		T6	5		T28	6
reset_info_cp[4]	auto[1]	2353	1			T1	33		T2	1		T3	1
reset_info_cp[8]	auto[0]	34	1			T90	1		T81	1		T131	1
reset_info_cp[8]	auto[1]	55	1			T1	1		T80	1		T92	1
reset_info_cp[16]	auto[0]	38	1			T1	1		T125	1		T131	1
reset_info_cp[16]	auto[1]	69	1			T12	1		T29	1		T81	1
reset_info_cp[32]	auto[0]	39	1			T90	1		T131	2		T134	1
reset_info_cp[32]	auto[1]	67	1			T1	1		T28	1		T29	1
reset_info_cp[64]	auto[0]	47	1			T1	1		T6	1		T29	1
reset_info_cp[64]	auto[1]	55	1			T1	1		T53	1		T135	1
reset_info_cp[128]	auto[0]	42	1			T16	2		T29	1		T125	1
reset_info_cp[128]	auto[1]	61	1			T29	1		T90	1		T30	1