Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.4118423848 Jul 04 05:20:56 PM PDT 24 Jul 04 05:21:03 PM PDT 24 1884504752 ps
T539 /workspace/coverage/default/9.rstmgr_reset.2322667576 Jul 04 05:20:01 PM PDT 24 Jul 04 05:20:05 PM PDT 24 728365025 ps
T540 /workspace/coverage/default/48.rstmgr_smoke.4043357985 Jul 04 05:21:36 PM PDT 24 Jul 04 05:21:37 PM PDT 24 121443852 ps
T541 /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2163067664 Jul 04 05:20:18 PM PDT 24 Jul 04 05:20:19 PM PDT 24 169613768 ps
T542 /workspace/coverage/default/25.rstmgr_stress_all.3946065255 Jul 04 05:20:48 PM PDT 24 Jul 04 05:21:07 PM PDT 24 4005113374 ps
T59 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.126507451 Jul 04 06:45:39 PM PDT 24 Jul 04 06:45:41 PM PDT 24 421992850 ps
T60 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2255553418 Jul 04 06:45:40 PM PDT 24 Jul 04 06:45:42 PM PDT 24 245500618 ps
T61 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1346637532 Jul 04 06:45:16 PM PDT 24 Jul 04 06:45:20 PM PDT 24 946002756 ps
T62 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3482704951 Jul 04 06:46:01 PM PDT 24 Jul 04 06:46:04 PM PDT 24 892201530 ps
T63 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2865155190 Jul 04 06:45:38 PM PDT 24 Jul 04 06:45:39 PM PDT 24 189576325 ps
T543 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.81394501 Jul 04 06:45:31 PM PDT 24 Jul 04 06:45:33 PM PDT 24 205999790 ps
T100 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3901944171 Jul 04 06:45:37 PM PDT 24 Jul 04 06:45:38 PM PDT 24 83116951 ps
T101 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4073262756 Jul 04 06:45:48 PM PDT 24 Jul 04 06:45:49 PM PDT 24 59819747 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3850838259 Jul 04 06:45:18 PM PDT 24 Jul 04 06:45:19 PM PDT 24 80323075 ps
T64 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3555046863 Jul 04 06:45:52 PM PDT 24 Jul 04 06:45:53 PM PDT 24 119205062 ps
T65 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3862589557 Jul 04 06:45:39 PM PDT 24 Jul 04 06:45:41 PM PDT 24 226746497 ps
T83 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3605616872 Jul 04 06:45:31 PM PDT 24 Jul 04 06:45:34 PM PDT 24 343541624 ps
T89 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3976581089 Jul 04 06:45:49 PM PDT 24 Jul 04 06:45:53 PM PDT 24 881528031 ps
T102 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.495102578 Jul 04 06:45:46 PM PDT 24 Jul 04 06:45:48 PM PDT 24 126111122 ps
T103 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.870306745 Jul 04 06:45:39 PM PDT 24 Jul 04 06:45:40 PM PDT 24 123690845 ps
T84 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1460857976 Jul 04 06:45:40 PM PDT 24 Jul 04 06:45:42 PM PDT 24 109278778 ps
T85 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.247394123 Jul 04 06:45:40 PM PDT 24 Jul 04 06:45:43 PM PDT 24 867709529 ps
T86 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1754506308 Jul 04 06:45:16 PM PDT 24 Jul 04 06:45:17 PM PDT 24 90026870 ps
T104 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3812133845 Jul 04 06:46:01 PM PDT 24 Jul 04 06:46:03 PM PDT 24 190082024 ps
T87 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2466651353 Jul 04 06:45:47 PM PDT 24 Jul 04 06:45:49 PM PDT 24 133243189 ps
T88 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2835660237 Jul 04 06:45:24 PM PDT 24 Jul 04 06:45:26 PM PDT 24 247039958 ps
T105 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3017987604 Jul 04 06:45:31 PM PDT 24 Jul 04 06:45:32 PM PDT 24 75412061 ps
T545 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.749496502 Jul 04 06:45:53 PM PDT 24 Jul 04 06:45:55 PM PDT 24 130607112 ps
T110 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.510034503 Jul 04 06:46:02 PM PDT 24 Jul 04 06:46:06 PM PDT 24 194691155 ps
T113 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3577188641 Jul 04 06:45:17 PM PDT 24 Jul 04 06:45:20 PM PDT 24 788827887 ps
T546 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3102061804 Jul 04 06:46:01 PM PDT 24 Jul 04 06:46:02 PM PDT 24 71314828 ps
T106 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2474513079 Jul 04 06:46:04 PM PDT 24 Jul 04 06:46:05 PM PDT 24 75707134 ps
T117 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.514320939 Jul 04 06:45:52 PM PDT 24 Jul 04 06:45:56 PM PDT 24 378159693 ps
T107 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2787321903 Jul 04 06:46:02 PM PDT 24 Jul 04 06:46:03 PM PDT 24 68578254 ps
T93 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3489989377 Jul 04 06:45:24 PM PDT 24 Jul 04 06:45:25 PM PDT 24 97736580 ps
T120 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.668188487 Jul 04 06:45:53 PM PDT 24 Jul 04 06:45:55 PM PDT 24 125035377 ps
T547 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3028555364 Jul 04 06:45:54 PM PDT 24 Jul 04 06:45:55 PM PDT 24 66563860 ps
T108 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2521961824 Jul 04 06:45:23 PM PDT 24 Jul 04 06:45:24 PM PDT 24 129661571 ps
T548 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2462435692 Jul 04 06:45:18 PM PDT 24 Jul 04 06:45:22 PM PDT 24 445876142 ps
T118 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2406893409 Jul 04 06:45:53 PM PDT 24 Jul 04 06:45:54 PM PDT 24 129984933 ps
T549 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2308961928 Jul 04 06:45:17 PM PDT 24 Jul 04 06:45:24 PM PDT 24 489247562 ps
T550 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.344889189 Jul 04 06:45:55 PM PDT 24 Jul 04 06:45:57 PM PDT 24 474956465 ps
T115 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.990736185 Jul 04 06:46:02 PM PDT 24 Jul 04 06:46:06 PM PDT 24 1016244788 ps
T119 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2390572190 Jul 04 06:45:39 PM PDT 24 Jul 04 06:45:40 PM PDT 24 97367066 ps
T551 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.433797042 Jul 04 06:45:18 PM PDT 24 Jul 04 06:45:19 PM PDT 24 69531606 ps
T552 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1420190069 Jul 04 06:45:23 PM PDT 24 Jul 04 06:45:32 PM PDT 24 2005467006 ps
T553 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1395705651 Jul 04 06:46:03 PM PDT 24 Jul 04 06:46:04 PM PDT 24 59328905 ps
T554 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3431433975 Jul 04 06:45:23 PM PDT 24 Jul 04 06:45:24 PM PDT 24 81776790 ps
T111 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.241954364 Jul 04 06:46:01 PM PDT 24 Jul 04 06:46:05 PM PDT 24 929411380 ps
T109 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1000125164 Jul 04 06:45:40 PM PDT 24 Jul 04 06:45:42 PM PDT 24 251579525 ps
T555 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4238711035 Jul 04 06:45:23 PM PDT 24 Jul 04 06:45:24 PM PDT 24 130412833 ps
T556 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4002226375 Jul 04 06:45:32 PM PDT 24 Jul 04 06:45:34 PM PDT 24 107193185 ps
T557 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1972470393 Jul 04 06:45:47 PM PDT 24 Jul 04 06:45:49 PM PDT 24 149072789 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1206457217 Jul 04 06:45:28 PM PDT 24 Jul 04 06:45:29 PM PDT 24 105414951 ps
T559 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1721556193 Jul 04 06:45:46 PM PDT 24 Jul 04 06:45:47 PM PDT 24 74859481 ps
T560 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1478980961 Jul 04 06:45:22 PM PDT 24 Jul 04 06:45:24 PM PDT 24 164868136 ps
T561 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1282351245 Jul 04 06:45:38 PM PDT 24 Jul 04 06:45:39 PM PDT 24 60206755 ps
T562 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.307028642 Jul 04 06:45:59 PM PDT 24 Jul 04 06:46:01 PM PDT 24 141528907 ps
T116 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3173699645 Jul 04 06:45:28 PM PDT 24 Jul 04 06:45:31 PM PDT 24 220455492 ps
T563 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3877630859 Jul 04 06:45:53 PM PDT 24 Jul 04 06:45:54 PM PDT 24 143868006 ps
T564 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.158379049 Jul 04 06:45:31 PM PDT 24 Jul 04 06:45:32 PM PDT 24 81942776 ps
T565 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2496704854 Jul 04 06:45:49 PM PDT 24 Jul 04 06:45:51 PM PDT 24 434823175 ps
T566 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1601771899 Jul 04 06:45:53 PM PDT 24 Jul 04 06:45:56 PM PDT 24 790963343 ps
T567 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.458887248 Jul 04 06:45:32 PM PDT 24 Jul 04 06:45:33 PM PDT 24 171067223 ps
T112 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1648643520 Jul 04 06:45:45 PM PDT 24 Jul 04 06:45:49 PM PDT 24 920738165 ps
T568 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1598046710 Jul 04 06:46:02 PM PDT 24 Jul 04 06:46:04 PM PDT 24 123994258 ps
T569 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2037092246 Jul 04 06:45:24 PM PDT 24 Jul 04 06:45:27 PM PDT 24 441366825 ps
T570 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1978233847 Jul 04 06:45:54 PM PDT 24 Jul 04 06:45:56 PM PDT 24 107692148 ps
T571 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2755772987 Jul 04 06:45:16 PM PDT 24 Jul 04 06:45:18 PM PDT 24 129526964 ps
T572 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1258402186 Jul 04 06:45:53 PM PDT 24 Jul 04 06:45:55 PM PDT 24 185525617 ps
T573 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.877538706 Jul 04 06:45:17 PM PDT 24 Jul 04 06:45:19 PM PDT 24 187456624 ps
T574 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3030925652 Jul 04 06:45:46 PM PDT 24 Jul 04 06:45:48 PM PDT 24 129458116 ps
T575 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1967236126 Jul 04 06:45:38 PM PDT 24 Jul 04 06:45:42 PM PDT 24 482151392 ps
T576 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1694230719 Jul 04 06:45:40 PM PDT 24 Jul 04 06:45:41 PM PDT 24 95577955 ps
T577 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2660503581 Jul 04 06:45:20 PM PDT 24 Jul 04 06:45:26 PM PDT 24 1033131364 ps
T578 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3380374515 Jul 04 06:45:23 PM PDT 24 Jul 04 06:45:27 PM PDT 24 805571968 ps
T579 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1335289678 Jul 04 06:45:53 PM PDT 24 Jul 04 06:45:54 PM PDT 24 54820660 ps
T580 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1579114818 Jul 04 06:45:24 PM PDT 24 Jul 04 06:45:25 PM PDT 24 117940128 ps
T581 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.233456613 Jul 04 06:45:18 PM PDT 24 Jul 04 06:45:19 PM PDT 24 99618751 ps
T582 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3914140288 Jul 04 06:45:23 PM PDT 24 Jul 04 06:45:24 PM PDT 24 95898402 ps
T583 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2681864501 Jul 04 06:45:22 PM PDT 24 Jul 04 06:45:23 PM PDT 24 75271518 ps
T584 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1682484219 Jul 04 06:45:32 PM PDT 24 Jul 04 06:45:33 PM PDT 24 79822313 ps
T585 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3902227480 Jul 04 06:45:47 PM PDT 24 Jul 04 06:45:49 PM PDT 24 111939095 ps
T114 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.793263854 Jul 04 06:45:38 PM PDT 24 Jul 04 06:45:40 PM PDT 24 414616327 ps
T586 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1810763802 Jul 04 06:46:01 PM PDT 24 Jul 04 06:46:03 PM PDT 24 138865962 ps
T587 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2833206010 Jul 04 06:45:16 PM PDT 24 Jul 04 06:45:18 PM PDT 24 205953158 ps
T588 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2093377659 Jul 04 06:45:33 PM PDT 24 Jul 04 06:45:37 PM PDT 24 276940184 ps
T589 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4120805624 Jul 04 06:45:24 PM PDT 24 Jul 04 06:45:26 PM PDT 24 130314211 ps
T129 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2787553840 Jul 04 06:45:54 PM PDT 24 Jul 04 06:45:56 PM PDT 24 472448144 ps
T590 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3018309077 Jul 04 06:45:19 PM PDT 24 Jul 04 06:45:20 PM PDT 24 107689790 ps
T591 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.292290872 Jul 04 06:45:55 PM PDT 24 Jul 04 06:45:56 PM PDT 24 99109244 ps
T592 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3417948779 Jul 04 06:46:01 PM PDT 24 Jul 04 06:46:02 PM PDT 24 77246228 ps
T593 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.851823079 Jul 04 06:45:31 PM PDT 24 Jul 04 06:45:32 PM PDT 24 206904971 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1978259042 Jul 04 06:45:17 PM PDT 24 Jul 04 06:45:20 PM PDT 24 187285981 ps
T595 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2778522608 Jul 04 06:45:31 PM PDT 24 Jul 04 06:45:32 PM PDT 24 74781098 ps
T596 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1311295828 Jul 04 06:45:30 PM PDT 24 Jul 04 06:45:32 PM PDT 24 173446986 ps
T597 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3485428694 Jul 04 06:45:38 PM PDT 24 Jul 04 06:45:39 PM PDT 24 58825598 ps
T598 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3834573926 Jul 04 06:45:17 PM PDT 24 Jul 04 06:45:20 PM PDT 24 187407517 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.400254076 Jul 04 06:45:18 PM PDT 24 Jul 04 06:45:19 PM PDT 24 193821752 ps
T600 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3027219810 Jul 04 06:45:22 PM PDT 24 Jul 04 06:45:26 PM PDT 24 874751425 ps
T601 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2069447683 Jul 04 06:45:54 PM PDT 24 Jul 04 06:45:55 PM PDT 24 73908721 ps
T602 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.904127021 Jul 04 06:45:54 PM PDT 24 Jul 04 06:45:55 PM PDT 24 97989130 ps
T603 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4194159519 Jul 04 06:45:52 PM PDT 24 Jul 04 06:45:54 PM PDT 24 113983599 ps
T604 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.299367094 Jul 04 06:45:54 PM PDT 24 Jul 04 06:45:55 PM PDT 24 77064352 ps
T605 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.140840694 Jul 04 06:45:47 PM PDT 24 Jul 04 06:45:50 PM PDT 24 366915458 ps
T606 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2114231307 Jul 04 06:45:31 PM PDT 24 Jul 04 06:45:33 PM PDT 24 241440782 ps
T607 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3807290579 Jul 04 06:45:48 PM PDT 24 Jul 04 06:45:49 PM PDT 24 143983088 ps
T608 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1831357439 Jul 04 06:45:27 PM PDT 24 Jul 04 06:45:29 PM PDT 24 469707268 ps
T609 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1107607550 Jul 04 06:46:00 PM PDT 24 Jul 04 06:46:03 PM PDT 24 471738509 ps
T610 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4233908732 Jul 04 06:45:48 PM PDT 24 Jul 04 06:45:49 PM PDT 24 69234259 ps
T611 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2719001184 Jul 04 06:45:38 PM PDT 24 Jul 04 06:45:40 PM PDT 24 210916362 ps
T612 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3990487178 Jul 04 06:45:20 PM PDT 24 Jul 04 06:45:23 PM PDT 24 832000475 ps
T613 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.447072725 Jul 04 06:45:54 PM PDT 24 Jul 04 06:45:56 PM PDT 24 256000702 ps
T614 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2448530936 Jul 04 06:46:00 PM PDT 24 Jul 04 06:46:02 PM PDT 24 261940903 ps
T615 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1518301803 Jul 04 06:45:40 PM PDT 24 Jul 04 06:45:42 PM PDT 24 121123526 ps
T616 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2867546465 Jul 04 06:45:59 PM PDT 24 Jul 04 06:46:01 PM PDT 24 134864837 ps
T617 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1246393684 Jul 04 06:45:32 PM PDT 24 Jul 04 06:45:34 PM PDT 24 491121663 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.347836960 Jul 04 06:45:17 PM PDT 24 Jul 04 06:45:19 PM PDT 24 99695876 ps
T619 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2094943993 Jul 04 06:45:52 PM PDT 24 Jul 04 06:45:54 PM PDT 24 79449099 ps
T620 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.829182355 Jul 04 06:45:31 PM PDT 24 Jul 04 06:45:34 PM PDT 24 936957192 ps

Test location /workspace/coverage/default/46.rstmgr_stress_all.1762256230
Short name T1
Test name
Test status
Simulation time 3691820142 ps
CPU time 17.25 seconds
Started Jul 04 05:21:33 PM PDT 24
Finished Jul 04 05:21:51 PM PDT 24
Peak memory 208580 kb
Host smart-c5295719-6a51-452a-b3c4-c6cc9d7aa38e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762256230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1762256230
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2292571488
Short name T4
Test name
Test status
Simulation time 115480358 ps
CPU time 1.51 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:19:31 PM PDT 24
Peak memory 200112 kb
Host smart-90b93037-bdcd-41cd-bd5a-99cf8c3bf434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292571488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2292571488
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2865155190
Short name T63
Test name
Test status
Simulation time 189576325 ps
CPU time 1.5 seconds
Started Jul 04 06:45:38 PM PDT 24
Finished Jul 04 06:45:39 PM PDT 24
Peak memory 208640 kb
Host smart-9a12e967-51c7-4da9-9cc2-3eaf0a2e2b20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865155190 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2865155190
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3873794451
Short name T73
Test name
Test status
Simulation time 16534713971 ps
CPU time 25.6 seconds
Started Jul 04 05:19:12 PM PDT 24
Finished Jul 04 05:19:38 PM PDT 24
Peak memory 218256 kb
Host smart-cf566f39-e120-4712-a370-ede13dacf71b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873794451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3873794451
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3891156194
Short name T30
Test name
Test status
Simulation time 1228044268 ps
CPU time 5.61 seconds
Started Jul 04 05:20:54 PM PDT 24
Finished Jul 04 05:21:00 PM PDT 24
Peak memory 217328 kb
Host smart-78126d54-56a7-44aa-b2d6-cf85d9b2ace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891156194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3891156194
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3482704951
Short name T62
Test name
Test status
Simulation time 892201530 ps
CPU time 3.19 seconds
Started Jul 04 06:46:01 PM PDT 24
Finished Jul 04 06:46:04 PM PDT 24
Peak memory 200500 kb
Host smart-430889c9-2ec6-4f2c-8a7c-146daa727caf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482704951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3482704951
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1810805667
Short name T81
Test name
Test status
Simulation time 3092185510 ps
CPU time 11.78 seconds
Started Jul 04 05:20:18 PM PDT 24
Finished Jul 04 05:20:30 PM PDT 24
Peak memory 208592 kb
Host smart-4b14699d-d9f3-42ba-9919-211fbd0a073c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810805667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1810805667
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3025024576
Short name T10
Test name
Test status
Simulation time 81023335 ps
CPU time 0.79 seconds
Started Jul 04 05:19:25 PM PDT 24
Finished Jul 04 05:19:26 PM PDT 24
Peak memory 199816 kb
Host smart-c9f03613-919b-4914-9f5b-55f635b68f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025024576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3025024576
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3527364543
Short name T133
Test name
Test status
Simulation time 136153895 ps
CPU time 1.1 seconds
Started Jul 04 05:21:19 PM PDT 24
Finished Jul 04 05:21:20 PM PDT 24
Peak memory 199984 kb
Host smart-0e591bde-1c2b-4040-bff1-fe09730f9892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527364543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3527364543
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3173699645
Short name T116
Test name
Test status
Simulation time 220455492 ps
CPU time 3.08 seconds
Started Jul 04 06:45:28 PM PDT 24
Finished Jul 04 06:45:31 PM PDT 24
Peak memory 212064 kb
Host smart-b3bc911c-4c69-4361-9a5a-a6be85354a50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173699645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3173699645
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4059702990
Short name T125
Test name
Test status
Simulation time 134994020 ps
CPU time 1 seconds
Started Jul 04 05:20:40 PM PDT 24
Finished Jul 04 05:20:41 PM PDT 24
Peak memory 200060 kb
Host smart-fe983ffc-1408-4ce1-a1e6-3ce3b701cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059702990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4059702990
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3753477389
Short name T47
Test name
Test status
Simulation time 1868162050 ps
CPU time 6.82 seconds
Started Jul 04 05:21:33 PM PDT 24
Finished Jul 04 05:21:40 PM PDT 24
Peak memory 221716 kb
Host smart-dcc774af-7fa8-4228-9637-b0bd6fd9c53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753477389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3753477389
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2787553840
Short name T129
Test name
Test status
Simulation time 472448144 ps
CPU time 2.01 seconds
Started Jul 04 06:45:54 PM PDT 24
Finished Jul 04 06:45:56 PM PDT 24
Peak memory 200472 kb
Host smart-223c97ee-63e1-4b22-baee-1b299eaaeaa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787553840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2787553840
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1472146107
Short name T17
Test name
Test status
Simulation time 234375332 ps
CPU time 0.95 seconds
Started Jul 04 05:21:37 PM PDT 24
Finished Jul 04 05:21:39 PM PDT 24
Peak memory 199904 kb
Host smart-a498d7c5-966a-4a6e-89b3-c424516ed035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472146107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1472146107
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3211246600
Short name T134
Test name
Test status
Simulation time 1370841167 ps
CPU time 5.94 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:15 PM PDT 24
Peak memory 200348 kb
Host smart-63f60d1b-a471-48c3-920a-6ffcc8821363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211246600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3211246600
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.514320939
Short name T117
Test name
Test status
Simulation time 378159693 ps
CPU time 2.89 seconds
Started Jul 04 06:45:52 PM PDT 24
Finished Jul 04 06:45:56 PM PDT 24
Peak memory 208708 kb
Host smart-0e7fdeed-ed45-48b3-9115-2524d06b908f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514320939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.514320939
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1695630504
Short name T35
Test name
Test status
Simulation time 1225755379 ps
CPU time 5.76 seconds
Started Jul 04 05:20:40 PM PDT 24
Finished Jul 04 05:20:46 PM PDT 24
Peak memory 217772 kb
Host smart-6a87dd26-fa14-4c69-a414-a28e3557bf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695630504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1695630504
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1648643520
Short name T112
Test name
Test status
Simulation time 920738165 ps
CPU time 3.31 seconds
Started Jul 04 06:45:45 PM PDT 24
Finished Jul 04 06:45:49 PM PDT 24
Peak memory 200500 kb
Host smart-38765173-cac5-4245-88bd-6b0907608ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648643520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1648643520
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.495102578
Short name T102
Test name
Test status
Simulation time 126111122 ps
CPU time 1.07 seconds
Started Jul 04 06:45:46 PM PDT 24
Finished Jul 04 06:45:48 PM PDT 24
Peak memory 200312 kb
Host smart-a6ee7ed8-6790-490b-b600-4395819a89dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495102578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.495102578
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3577188641
Short name T113
Test name
Test status
Simulation time 788827887 ps
CPU time 2.75 seconds
Started Jul 04 06:45:17 PM PDT 24
Finished Jul 04 06:45:20 PM PDT 24
Peak memory 200492 kb
Host smart-186ad985-f785-4df6-bdae-69688a0fa00e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577188641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3577188641
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2833206010
Short name T587
Test name
Test status
Simulation time 205953158 ps
CPU time 1.58 seconds
Started Jul 04 06:45:16 PM PDT 24
Finished Jul 04 06:45:18 PM PDT 24
Peak memory 200524 kb
Host smart-ff75c229-be2f-4386-ad4a-17f864b2c936
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833206010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
833206010
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2660503581
Short name T577
Test name
Test status
Simulation time 1033131364 ps
CPU time 5.29 seconds
Started Jul 04 06:45:20 PM PDT 24
Finished Jul 04 06:45:26 PM PDT 24
Peak memory 200444 kb
Host smart-4e3d7a0f-c175-4912-a596-f79a7417697f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660503581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
660503581
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.233456613
Short name T581
Test name
Test status
Simulation time 99618751 ps
CPU time 0.85 seconds
Started Jul 04 06:45:18 PM PDT 24
Finished Jul 04 06:45:19 PM PDT 24
Peak memory 200296 kb
Host smart-0b8896fc-57ab-4ea4-b1d7-57e485ee8985
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233456613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.233456613
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.400254076
Short name T599
Test name
Test status
Simulation time 193821752 ps
CPU time 1.27 seconds
Started Jul 04 06:45:18 PM PDT 24
Finished Jul 04 06:45:19 PM PDT 24
Peak memory 208556 kb
Host smart-7bc95510-27e6-42ba-afd5-f59047a9bdd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400254076 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.400254076
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3850838259
Short name T544
Test name
Test status
Simulation time 80323075 ps
CPU time 0.88 seconds
Started Jul 04 06:45:18 PM PDT 24
Finished Jul 04 06:45:19 PM PDT 24
Peak memory 200256 kb
Host smart-0b90b3b3-6f6b-4772-b2c2-b3af7e912b95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850838259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3850838259
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.877538706
Short name T573
Test name
Test status
Simulation time 187456624 ps
CPU time 1.43 seconds
Started Jul 04 06:45:17 PM PDT 24
Finished Jul 04 06:45:19 PM PDT 24
Peak memory 200528 kb
Host smart-6d8424dc-2fe0-4eb3-b1ed-c29bcd8fd579
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877538706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.877538706
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1754506308
Short name T86
Test name
Test status
Simulation time 90026870 ps
CPU time 1.29 seconds
Started Jul 04 06:45:16 PM PDT 24
Finished Jul 04 06:45:17 PM PDT 24
Peak memory 208496 kb
Host smart-c5f311e6-4c5e-4c55-bd58-7b1d9bac7c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754506308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1754506308
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3990487178
Short name T612
Test name
Test status
Simulation time 832000475 ps
CPU time 2.85 seconds
Started Jul 04 06:45:20 PM PDT 24
Finished Jul 04 06:45:23 PM PDT 24
Peak memory 200576 kb
Host smart-39a354cf-965f-491c-99d8-ceb52d2fbb16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990487178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3990487178
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2462435692
Short name T548
Test name
Test status
Simulation time 445876142 ps
CPU time 3.06 seconds
Started Jul 04 06:45:18 PM PDT 24
Finished Jul 04 06:45:22 PM PDT 24
Peak memory 200440 kb
Host smart-0f952475-ccbb-4908-b201-5d8376259f82
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462435692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
462435692
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2308961928
Short name T549
Test name
Test status
Simulation time 489247562 ps
CPU time 6.29 seconds
Started Jul 04 06:45:17 PM PDT 24
Finished Jul 04 06:45:24 PM PDT 24
Peak memory 200504 kb
Host smart-9c2c281b-9f08-4dc6-815e-a759c32890f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308961928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
308961928
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3018309077
Short name T590
Test name
Test status
Simulation time 107689790 ps
CPU time 0.85 seconds
Started Jul 04 06:45:19 PM PDT 24
Finished Jul 04 06:45:20 PM PDT 24
Peak memory 200316 kb
Host smart-872c63d8-3d8a-4d46-9d9a-b0459aaea8a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018309077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
018309077
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.347836960
Short name T618
Test name
Test status
Simulation time 99695876 ps
CPU time 0.93 seconds
Started Jul 04 06:45:17 PM PDT 24
Finished Jul 04 06:45:19 PM PDT 24
Peak memory 200396 kb
Host smart-34b98977-18c3-4d7e-a593-26f5dec4088c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347836960 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.347836960
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.433797042
Short name T551
Test name
Test status
Simulation time 69531606 ps
CPU time 0.79 seconds
Started Jul 04 06:45:18 PM PDT 24
Finished Jul 04 06:45:19 PM PDT 24
Peak memory 200220 kb
Host smart-437710ba-a1e5-43f0-a77a-9a76688d7187
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433797042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.433797042
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2755772987
Short name T571
Test name
Test status
Simulation time 129526964 ps
CPU time 1.07 seconds
Started Jul 04 06:45:16 PM PDT 24
Finished Jul 04 06:45:18 PM PDT 24
Peak memory 200312 kb
Host smart-0fe6a3b3-4f2d-4189-97f7-4f0d26b30dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755772987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2755772987
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1978259042
Short name T594
Test name
Test status
Simulation time 187285981 ps
CPU time 2.78 seconds
Started Jul 04 06:45:17 PM PDT 24
Finished Jul 04 06:45:20 PM PDT 24
Peak memory 208700 kb
Host smart-d65c5433-9292-4c6d-a1a3-924b83a7a699
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978259042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1978259042
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1346637532
Short name T61
Test name
Test status
Simulation time 946002756 ps
CPU time 3.1 seconds
Started Jul 04 06:45:16 PM PDT 24
Finished Jul 04 06:45:20 PM PDT 24
Peak memory 200744 kb
Host smart-48b9577a-1b6f-422e-b835-e660d9c57803
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346637532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1346637532
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2466651353
Short name T87
Test name
Test status
Simulation time 133243189 ps
CPU time 1.15 seconds
Started Jul 04 06:45:47 PM PDT 24
Finished Jul 04 06:45:49 PM PDT 24
Peak memory 208672 kb
Host smart-90b9d568-3392-4fd7-8dcd-7a6709698b9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466651353 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2466651353
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1721556193
Short name T559
Test name
Test status
Simulation time 74859481 ps
CPU time 0.8 seconds
Started Jul 04 06:45:46 PM PDT 24
Finished Jul 04 06:45:47 PM PDT 24
Peak memory 200288 kb
Host smart-59bfaa6e-cfef-4cae-a39d-f488e4816f06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721556193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1721556193
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2719001184
Short name T611
Test name
Test status
Simulation time 210916362 ps
CPU time 1.71 seconds
Started Jul 04 06:45:38 PM PDT 24
Finished Jul 04 06:45:40 PM PDT 24
Peak memory 200412 kb
Host smart-aaf25fb5-718b-4e17-a437-a209f4778165
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719001184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2719001184
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3976581089
Short name T89
Test name
Test status
Simulation time 881528031 ps
CPU time 3.08 seconds
Started Jul 04 06:45:49 PM PDT 24
Finished Jul 04 06:45:53 PM PDT 24
Peak memory 200536 kb
Host smart-11a5d6a1-b674-46b0-9959-c8814853ba99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976581089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3976581089
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3807290579
Short name T607
Test name
Test status
Simulation time 143983088 ps
CPU time 1.12 seconds
Started Jul 04 06:45:48 PM PDT 24
Finished Jul 04 06:45:49 PM PDT 24
Peak memory 210608 kb
Host smart-806ae9a2-ebc1-4a5c-ac4f-6bfe6226bead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807290579 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3807290579
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4233908732
Short name T610
Test name
Test status
Simulation time 69234259 ps
CPU time 0.78 seconds
Started Jul 04 06:45:48 PM PDT 24
Finished Jul 04 06:45:49 PM PDT 24
Peak memory 200284 kb
Host smart-e41571d6-99ce-4148-b379-71b30bfc9238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233908732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4233908732
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3902227480
Short name T585
Test name
Test status
Simulation time 111939095 ps
CPU time 1.36 seconds
Started Jul 04 06:45:47 PM PDT 24
Finished Jul 04 06:45:49 PM PDT 24
Peak memory 200476 kb
Host smart-bfb75fc7-3974-4b48-a431-41d6fb30bf9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902227480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3902227480
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.140840694
Short name T605
Test name
Test status
Simulation time 366915458 ps
CPU time 2.66 seconds
Started Jul 04 06:45:47 PM PDT 24
Finished Jul 04 06:45:50 PM PDT 24
Peak memory 208612 kb
Host smart-7fbe60b0-d2c1-440a-9443-ed0a2431de78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140840694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.140840694
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2496704854
Short name T565
Test name
Test status
Simulation time 434823175 ps
CPU time 1.9 seconds
Started Jul 04 06:45:49 PM PDT 24
Finished Jul 04 06:45:51 PM PDT 24
Peak memory 200480 kb
Host smart-0aa78f4e-1a87-446c-bd88-a867469168d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496704854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2496704854
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2406893409
Short name T118
Test name
Test status
Simulation time 129984933 ps
CPU time 1.45 seconds
Started Jul 04 06:45:53 PM PDT 24
Finished Jul 04 06:45:54 PM PDT 24
Peak memory 208784 kb
Host smart-16a9dbd5-8423-4247-82c3-f16d0bfa81f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406893409 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2406893409
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4073262756
Short name T101
Test name
Test status
Simulation time 59819747 ps
CPU time 0.78 seconds
Started Jul 04 06:45:48 PM PDT 24
Finished Jul 04 06:45:49 PM PDT 24
Peak memory 200296 kb
Host smart-df5cd345-cd38-476e-ab94-e56456740961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073262756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.4073262756
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1972470393
Short name T557
Test name
Test status
Simulation time 149072789 ps
CPU time 1.28 seconds
Started Jul 04 06:45:47 PM PDT 24
Finished Jul 04 06:45:49 PM PDT 24
Peak memory 200380 kb
Host smart-f621c486-d738-4002-9940-225f0b21b0f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972470393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1972470393
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3030925652
Short name T574
Test name
Test status
Simulation time 129458116 ps
CPU time 1.83 seconds
Started Jul 04 06:45:46 PM PDT 24
Finished Jul 04 06:45:48 PM PDT 24
Peak memory 208672 kb
Host smart-adbb6264-6910-4c11-aec3-eaed41422966
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030925652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3030925652
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.749496502
Short name T545
Test name
Test status
Simulation time 130607112 ps
CPU time 1.07 seconds
Started Jul 04 06:45:53 PM PDT 24
Finished Jul 04 06:45:55 PM PDT 24
Peak memory 208644 kb
Host smart-6b67a0da-c341-480d-adcb-7a3869a7a339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749496502 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.749496502
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3028555364
Short name T547
Test name
Test status
Simulation time 66563860 ps
CPU time 0.76 seconds
Started Jul 04 06:45:54 PM PDT 24
Finished Jul 04 06:45:55 PM PDT 24
Peak memory 200272 kb
Host smart-9157839c-9d67-4f75-9797-9cda1cd600f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028555364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3028555364
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3417948779
Short name T592
Test name
Test status
Simulation time 77246228 ps
CPU time 0.97 seconds
Started Jul 04 06:46:01 PM PDT 24
Finished Jul 04 06:46:02 PM PDT 24
Peak memory 200296 kb
Host smart-e4be60d1-37b4-4b57-aa42-901eda9d2a08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417948779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3417948779
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3555046863
Short name T64
Test name
Test status
Simulation time 119205062 ps
CPU time 0.95 seconds
Started Jul 04 06:45:52 PM PDT 24
Finished Jul 04 06:45:53 PM PDT 24
Peak memory 200444 kb
Host smart-4b2731d4-1e9c-43f3-93d9-8fdc3ccc6aea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555046863 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3555046863
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2787321903
Short name T107
Test name
Test status
Simulation time 68578254 ps
CPU time 0.86 seconds
Started Jul 04 06:46:02 PM PDT 24
Finished Jul 04 06:46:03 PM PDT 24
Peak memory 200224 kb
Host smart-4bb18d87-806c-494f-8e9f-82561d234f1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787321903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2787321903
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2094943993
Short name T619
Test name
Test status
Simulation time 79449099 ps
CPU time 1.04 seconds
Started Jul 04 06:45:52 PM PDT 24
Finished Jul 04 06:45:54 PM PDT 24
Peak memory 200368 kb
Host smart-9af2a71e-bdf5-40f5-a268-3b2b6e5597fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094943993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2094943993
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.447072725
Short name T613
Test name
Test status
Simulation time 256000702 ps
CPU time 1.91 seconds
Started Jul 04 06:45:54 PM PDT 24
Finished Jul 04 06:45:56 PM PDT 24
Peak memory 208624 kb
Host smart-440cd03a-fa43-4026-b50a-75752d99573d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447072725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.447072725
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3877630859
Short name T563
Test name
Test status
Simulation time 143868006 ps
CPU time 1.11 seconds
Started Jul 04 06:45:53 PM PDT 24
Finished Jul 04 06:45:54 PM PDT 24
Peak memory 208904 kb
Host smart-16fc56b0-92e1-4dbe-9904-c84525b78d4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877630859 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3877630859
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2069447683
Short name T601
Test name
Test status
Simulation time 73908721 ps
CPU time 0.76 seconds
Started Jul 04 06:45:54 PM PDT 24
Finished Jul 04 06:45:55 PM PDT 24
Peak memory 200220 kb
Host smart-87c37ecc-be45-4f43-ab4d-7fa08afc5684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069447683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2069447683
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1258402186
Short name T572
Test name
Test status
Simulation time 185525617 ps
CPU time 1.49 seconds
Started Jul 04 06:45:53 PM PDT 24
Finished Jul 04 06:45:55 PM PDT 24
Peak memory 200524 kb
Host smart-ebb35e12-80b7-4b9d-a3bf-7256d52daaea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258402186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1258402186
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.904127021
Short name T602
Test name
Test status
Simulation time 97989130 ps
CPU time 1.26 seconds
Started Jul 04 06:45:54 PM PDT 24
Finished Jul 04 06:45:55 PM PDT 24
Peak memory 200284 kb
Host smart-ecb8601b-d1b2-45a2-9880-ee1d257d7d8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904127021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.904127021
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1601771899
Short name T566
Test name
Test status
Simulation time 790963343 ps
CPU time 2.82 seconds
Started Jul 04 06:45:53 PM PDT 24
Finished Jul 04 06:45:56 PM PDT 24
Peak memory 200552 kb
Host smart-eed4c557-5edd-44de-b774-0da95731bb65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601771899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1601771899
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.292290872
Short name T591
Test name
Test status
Simulation time 99109244 ps
CPU time 0.99 seconds
Started Jul 04 06:45:55 PM PDT 24
Finished Jul 04 06:45:56 PM PDT 24
Peak memory 200352 kb
Host smart-e4a29c0c-1600-4bea-a66e-f77843a747ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292290872 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.292290872
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1335289678
Short name T579
Test name
Test status
Simulation time 54820660 ps
CPU time 0.71 seconds
Started Jul 04 06:45:53 PM PDT 24
Finished Jul 04 06:45:54 PM PDT 24
Peak memory 200432 kb
Host smart-7a4cb282-18c8-4d17-b5d6-5872edb80414
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335289678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1335289678
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1810763802
Short name T586
Test name
Test status
Simulation time 138865962 ps
CPU time 1.17 seconds
Started Jul 04 06:46:01 PM PDT 24
Finished Jul 04 06:46:03 PM PDT 24
Peak memory 200300 kb
Host smart-ffc19d52-5de5-4a36-b982-f171bb13560e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810763802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1810763802
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.668188487
Short name T120
Test name
Test status
Simulation time 125035377 ps
CPU time 1.75 seconds
Started Jul 04 06:45:53 PM PDT 24
Finished Jul 04 06:45:55 PM PDT 24
Peak memory 200404 kb
Host smart-9654901d-e4cf-430c-a3ef-4f26b0ced5f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668188487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.668188487
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.990736185
Short name T115
Test name
Test status
Simulation time 1016244788 ps
CPU time 3.4 seconds
Started Jul 04 06:46:02 PM PDT 24
Finished Jul 04 06:46:06 PM PDT 24
Peak memory 200460 kb
Host smart-eb5b1e9d-c6b4-41f1-b340-5155ca662f15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990736185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.990736185
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4194159519
Short name T603
Test name
Test status
Simulation time 113983599 ps
CPU time 0.94 seconds
Started Jul 04 06:45:52 PM PDT 24
Finished Jul 04 06:45:54 PM PDT 24
Peak memory 200400 kb
Host smart-17e9cf74-0f5c-4b36-82cb-c6c1a5d52033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194159519 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.4194159519
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.299367094
Short name T604
Test name
Test status
Simulation time 77064352 ps
CPU time 0.86 seconds
Started Jul 04 06:45:54 PM PDT 24
Finished Jul 04 06:45:55 PM PDT 24
Peak memory 200292 kb
Host smart-2ea2d220-4f24-439c-871f-09c11c2847d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299367094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.299367094
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3812133845
Short name T104
Test name
Test status
Simulation time 190082024 ps
CPU time 1.49 seconds
Started Jul 04 06:46:01 PM PDT 24
Finished Jul 04 06:46:03 PM PDT 24
Peak memory 200420 kb
Host smart-978e537b-aae8-4381-9511-78346208cc33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812133845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3812133845
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1978233847
Short name T570
Test name
Test status
Simulation time 107692148 ps
CPU time 1.43 seconds
Started Jul 04 06:45:54 PM PDT 24
Finished Jul 04 06:45:56 PM PDT 24
Peak memory 210996 kb
Host smart-27ccc776-8cd5-44b3-bc65-cd867f9f79fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978233847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1978233847
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.344889189
Short name T550
Test name
Test status
Simulation time 474956465 ps
CPU time 2.22 seconds
Started Jul 04 06:45:55 PM PDT 24
Finished Jul 04 06:45:57 PM PDT 24
Peak memory 200520 kb
Host smart-9ab3d9ef-63b6-44fd-bc05-e45985513d18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344889189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.344889189
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1598046710
Short name T568
Test name
Test status
Simulation time 123994258 ps
CPU time 0.97 seconds
Started Jul 04 06:46:02 PM PDT 24
Finished Jul 04 06:46:04 PM PDT 24
Peak memory 200424 kb
Host smart-f3d80bb4-0bde-49c3-ba1e-4f5f37ff371f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598046710 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1598046710
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3102061804
Short name T546
Test name
Test status
Simulation time 71314828 ps
CPU time 0.83 seconds
Started Jul 04 06:46:01 PM PDT 24
Finished Jul 04 06:46:02 PM PDT 24
Peak memory 200228 kb
Host smart-a9187b0c-fdfe-4b9c-8d82-b309731963b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102061804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3102061804
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2474513079
Short name T106
Test name
Test status
Simulation time 75707134 ps
CPU time 0.98 seconds
Started Jul 04 06:46:04 PM PDT 24
Finished Jul 04 06:46:05 PM PDT 24
Peak memory 200340 kb
Host smart-620fae82-c7f4-4476-ab37-5c87d6f130f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474513079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2474513079
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.510034503
Short name T110
Test name
Test status
Simulation time 194691155 ps
CPU time 3.06 seconds
Started Jul 04 06:46:02 PM PDT 24
Finished Jul 04 06:46:06 PM PDT 24
Peak memory 208612 kb
Host smart-e0613d9c-c223-4c05-84c1-0e210c71e4ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510034503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.510034503
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.241954364
Short name T111
Test name
Test status
Simulation time 929411380 ps
CPU time 3.11 seconds
Started Jul 04 06:46:01 PM PDT 24
Finished Jul 04 06:46:05 PM PDT 24
Peak memory 200472 kb
Host smart-ef28694d-2497-43ed-893d-fad720633d58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241954364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.241954364
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2867546465
Short name T616
Test name
Test status
Simulation time 134864837 ps
CPU time 1.12 seconds
Started Jul 04 06:45:59 PM PDT 24
Finished Jul 04 06:46:01 PM PDT 24
Peak memory 200404 kb
Host smart-53d7c736-d7d6-4a2d-9bd9-5c40056113c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867546465 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2867546465
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1395705651
Short name T553
Test name
Test status
Simulation time 59328905 ps
CPU time 0.78 seconds
Started Jul 04 06:46:03 PM PDT 24
Finished Jul 04 06:46:04 PM PDT 24
Peak memory 200244 kb
Host smart-e46d363f-b716-4f8e-928a-1498967b5e44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395705651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1395705651
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.307028642
Short name T562
Test name
Test status
Simulation time 141528907 ps
CPU time 1.2 seconds
Started Jul 04 06:45:59 PM PDT 24
Finished Jul 04 06:46:01 PM PDT 24
Peak memory 200344 kb
Host smart-f957dca6-35a6-469e-98d9-d1805c3f72c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307028642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.307028642
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2448530936
Short name T614
Test name
Test status
Simulation time 261940903 ps
CPU time 2.26 seconds
Started Jul 04 06:46:00 PM PDT 24
Finished Jul 04 06:46:02 PM PDT 24
Peak memory 211232 kb
Host smart-8910916c-06a3-4d33-aa52-8d080bb815c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448530936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2448530936
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1107607550
Short name T609
Test name
Test status
Simulation time 471738509 ps
CPU time 2.07 seconds
Started Jul 04 06:46:00 PM PDT 24
Finished Jul 04 06:46:03 PM PDT 24
Peak memory 200536 kb
Host smart-e016dc0d-eb12-4b54-a4be-018d20b78747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107607550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1107607550
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2037092246
Short name T569
Test name
Test status
Simulation time 441366825 ps
CPU time 2.91 seconds
Started Jul 04 06:45:24 PM PDT 24
Finished Jul 04 06:45:27 PM PDT 24
Peak memory 208672 kb
Host smart-8c3cedff-9c05-4c57-9ce7-b83171f24e47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037092246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
037092246
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1420190069
Short name T552
Test name
Test status
Simulation time 2005467006 ps
CPU time 9.12 seconds
Started Jul 04 06:45:23 PM PDT 24
Finished Jul 04 06:45:32 PM PDT 24
Peak memory 200440 kb
Host smart-78afca23-e897-427e-9e6c-c21b413efd76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420190069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
420190069
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1206457217
Short name T558
Test name
Test status
Simulation time 105414951 ps
CPU time 0.85 seconds
Started Jul 04 06:45:28 PM PDT 24
Finished Jul 04 06:45:29 PM PDT 24
Peak memory 200176 kb
Host smart-d5e20865-9573-408a-a91d-9689a4c8278e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206457217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
206457217
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4120805624
Short name T589
Test name
Test status
Simulation time 130314211 ps
CPU time 1.57 seconds
Started Jul 04 06:45:24 PM PDT 24
Finished Jul 04 06:45:26 PM PDT 24
Peak memory 208692 kb
Host smart-9d648081-c307-439a-ae9d-2eefe9e3f057
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120805624 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.4120805624
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3431433975
Short name T554
Test name
Test status
Simulation time 81776790 ps
CPU time 0.87 seconds
Started Jul 04 06:45:23 PM PDT 24
Finished Jul 04 06:45:24 PM PDT 24
Peak memory 200256 kb
Host smart-6a13ecae-50d7-4d5c-ae3f-779d9c29cbd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431433975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3431433975
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4238711035
Short name T555
Test name
Test status
Simulation time 130412833 ps
CPU time 1.3 seconds
Started Jul 04 06:45:23 PM PDT 24
Finished Jul 04 06:45:24 PM PDT 24
Peak memory 200492 kb
Host smart-267a47a8-4c01-4d1f-a00b-d887c856edfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238711035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.4238711035
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3834573926
Short name T598
Test name
Test status
Simulation time 187407517 ps
CPU time 2.69 seconds
Started Jul 04 06:45:17 PM PDT 24
Finished Jul 04 06:45:20 PM PDT 24
Peak memory 212672 kb
Host smart-fee8c3fe-c0f3-4f0c-83fc-f42561aabbac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834573926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3834573926
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3489989377
Short name T93
Test name
Test status
Simulation time 97736580 ps
CPU time 1.28 seconds
Started Jul 04 06:45:24 PM PDT 24
Finished Jul 04 06:45:25 PM PDT 24
Peak memory 200468 kb
Host smart-b0981fdf-41e9-46e1-9417-5bbfc7c8e69e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489989377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
489989377
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3380374515
Short name T578
Test name
Test status
Simulation time 805571968 ps
CPU time 4.54 seconds
Started Jul 04 06:45:23 PM PDT 24
Finished Jul 04 06:45:27 PM PDT 24
Peak memory 200456 kb
Host smart-dc4470d8-9e43-4c74-a093-fed2dfbefe0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380374515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
380374515
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3914140288
Short name T582
Test name
Test status
Simulation time 95898402 ps
CPU time 0.79 seconds
Started Jul 04 06:45:23 PM PDT 24
Finished Jul 04 06:45:24 PM PDT 24
Peak memory 200276 kb
Host smart-9634eda5-6972-431a-890d-259b86738861
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914140288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
914140288
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1478980961
Short name T560
Test name
Test status
Simulation time 164868136 ps
CPU time 1.18 seconds
Started Jul 04 06:45:22 PM PDT 24
Finished Jul 04 06:45:24 PM PDT 24
Peak memory 208656 kb
Host smart-a29d0a77-64fc-427d-b1b4-644b2d45407d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478980961 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1478980961
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2681864501
Short name T583
Test name
Test status
Simulation time 75271518 ps
CPU time 0.8 seconds
Started Jul 04 06:45:22 PM PDT 24
Finished Jul 04 06:45:23 PM PDT 24
Peak memory 200296 kb
Host smart-636d8418-3cf0-4819-9458-127b15897d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681864501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2681864501
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2521961824
Short name T108
Test name
Test status
Simulation time 129661571 ps
CPU time 1.13 seconds
Started Jul 04 06:45:23 PM PDT 24
Finished Jul 04 06:45:24 PM PDT 24
Peak memory 200312 kb
Host smart-9a5bcf75-afb6-4a70-8fa0-61e3b8d17f43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521961824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2521961824
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2835660237
Short name T88
Test name
Test status
Simulation time 247039958 ps
CPU time 2.03 seconds
Started Jul 04 06:45:24 PM PDT 24
Finished Jul 04 06:45:26 PM PDT 24
Peak memory 200432 kb
Host smart-3d7c6734-23de-4e3d-814a-4e2e7331fbd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835660237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2835660237
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1831357439
Short name T608
Test name
Test status
Simulation time 469707268 ps
CPU time 2 seconds
Started Jul 04 06:45:27 PM PDT 24
Finished Jul 04 06:45:29 PM PDT 24
Peak memory 200504 kb
Host smart-0e1fb34e-251b-4b82-9a48-6a87a22a62af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831357439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1831357439
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.81394501
Short name T543
Test name
Test status
Simulation time 205999790 ps
CPU time 1.55 seconds
Started Jul 04 06:45:31 PM PDT 24
Finished Jul 04 06:45:33 PM PDT 24
Peak memory 200368 kb
Host smart-9aedb4b3-2f33-4f9b-9772-d10dfff41d29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81394501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.81394501
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2093377659
Short name T588
Test name
Test status
Simulation time 276940184 ps
CPU time 3.41 seconds
Started Jul 04 06:45:33 PM PDT 24
Finished Jul 04 06:45:37 PM PDT 24
Peak memory 200516 kb
Host smart-081e529b-c68d-44a0-a692-ccacca4151aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093377659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
093377659
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1579114818
Short name T580
Test name
Test status
Simulation time 117940128 ps
CPU time 0.92 seconds
Started Jul 04 06:45:24 PM PDT 24
Finished Jul 04 06:45:25 PM PDT 24
Peak memory 200240 kb
Host smart-dbebe976-3537-4f0e-b3ee-2e904ff7f0b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579114818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
579114818
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1311295828
Short name T596
Test name
Test status
Simulation time 173446986 ps
CPU time 1.65 seconds
Started Jul 04 06:45:30 PM PDT 24
Finished Jul 04 06:45:32 PM PDT 24
Peak memory 208764 kb
Host smart-eae92125-d34e-4d9c-89bf-2dd074ea5d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311295828 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1311295828
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2778522608
Short name T595
Test name
Test status
Simulation time 74781098 ps
CPU time 0.8 seconds
Started Jul 04 06:45:31 PM PDT 24
Finished Jul 04 06:45:32 PM PDT 24
Peak memory 200208 kb
Host smart-7d33dd36-1207-4a51-a9e5-fa578b7a2b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778522608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2778522608
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3017987604
Short name T105
Test name
Test status
Simulation time 75412061 ps
CPU time 0.9 seconds
Started Jul 04 06:45:31 PM PDT 24
Finished Jul 04 06:45:32 PM PDT 24
Peak memory 200288 kb
Host smart-9985c322-5b61-4838-83df-237a43490745
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017987604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3017987604
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3027219810
Short name T600
Test name
Test status
Simulation time 874751425 ps
CPU time 3.45 seconds
Started Jul 04 06:45:22 PM PDT 24
Finished Jul 04 06:45:26 PM PDT 24
Peak memory 200552 kb
Host smart-8059c628-ffca-4c5c-9901-81aa0ec86a21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027219810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3027219810
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.851823079
Short name T593
Test name
Test status
Simulation time 206904971 ps
CPU time 1.39 seconds
Started Jul 04 06:45:31 PM PDT 24
Finished Jul 04 06:45:32 PM PDT 24
Peak memory 208628 kb
Host smart-136b26d9-d9cf-4ef3-a603-d8d164eb9fa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851823079 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.851823079
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.158379049
Short name T564
Test name
Test status
Simulation time 81942776 ps
CPU time 0.85 seconds
Started Jul 04 06:45:31 PM PDT 24
Finished Jul 04 06:45:32 PM PDT 24
Peak memory 200244 kb
Host smart-d1327997-eafa-4430-a04a-5842bcc947b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158379049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.158379049
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.458887248
Short name T567
Test name
Test status
Simulation time 171067223 ps
CPU time 1.39 seconds
Started Jul 04 06:45:32 PM PDT 24
Finished Jul 04 06:45:33 PM PDT 24
Peak memory 200496 kb
Host smart-fb3c36fa-6b80-49ee-bc74-e05c61d2d250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458887248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.458887248
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3605616872
Short name T83
Test name
Test status
Simulation time 343541624 ps
CPU time 2.59 seconds
Started Jul 04 06:45:31 PM PDT 24
Finished Jul 04 06:45:34 PM PDT 24
Peak memory 208608 kb
Host smart-58e061d5-f73e-47f9-a0fc-ed8a2dd87a66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605616872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3605616872
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1246393684
Short name T617
Test name
Test status
Simulation time 491121663 ps
CPU time 2.02 seconds
Started Jul 04 06:45:32 PM PDT 24
Finished Jul 04 06:45:34 PM PDT 24
Peak memory 200588 kb
Host smart-611a141d-bce5-49ae-9b8c-2c0599c054e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246393684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1246393684
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1518301803
Short name T615
Test name
Test status
Simulation time 121123526 ps
CPU time 1.06 seconds
Started Jul 04 06:45:40 PM PDT 24
Finished Jul 04 06:45:42 PM PDT 24
Peak memory 200456 kb
Host smart-099090b6-94cb-4d78-b166-2cc9ca8d18ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518301803 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1518301803
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1682484219
Short name T584
Test name
Test status
Simulation time 79822313 ps
CPU time 0.85 seconds
Started Jul 04 06:45:32 PM PDT 24
Finished Jul 04 06:45:33 PM PDT 24
Peak memory 200296 kb
Host smart-96cbcfe2-1847-441e-bca7-15ba58788dca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682484219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1682484219
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4002226375
Short name T556
Test name
Test status
Simulation time 107193185 ps
CPU time 1.29 seconds
Started Jul 04 06:45:32 PM PDT 24
Finished Jul 04 06:45:34 PM PDT 24
Peak memory 200476 kb
Host smart-cbfbe4bc-175b-4426-9dcb-030dd7fd37c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002226375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.4002226375
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2114231307
Short name T606
Test name
Test status
Simulation time 241440782 ps
CPU time 1.79 seconds
Started Jul 04 06:45:31 PM PDT 24
Finished Jul 04 06:45:33 PM PDT 24
Peak memory 211336 kb
Host smart-6eabe96a-f6e4-4564-b55a-c7f316010c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114231307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2114231307
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.829182355
Short name T620
Test name
Test status
Simulation time 936957192 ps
CPU time 3.1 seconds
Started Jul 04 06:45:31 PM PDT 24
Finished Jul 04 06:45:34 PM PDT 24
Peak memory 200520 kb
Host smart-f8956629-8cc1-4c8e-953b-88309ba4b21f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829182355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
829182355
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3862589557
Short name T65
Test name
Test status
Simulation time 226746497 ps
CPU time 1.4 seconds
Started Jul 04 06:45:39 PM PDT 24
Finished Jul 04 06:45:41 PM PDT 24
Peak memory 208640 kb
Host smart-439fad81-5339-4ad3-b307-5397e40dd1d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862589557 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3862589557
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3485428694
Short name T597
Test name
Test status
Simulation time 58825598 ps
CPU time 0.77 seconds
Started Jul 04 06:45:38 PM PDT 24
Finished Jul 04 06:45:39 PM PDT 24
Peak memory 200264 kb
Host smart-4fc5627f-edb6-4d10-96b2-1f781f7c2e08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485428694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3485428694
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.870306745
Short name T103
Test name
Test status
Simulation time 123690845 ps
CPU time 1.13 seconds
Started Jul 04 06:45:39 PM PDT 24
Finished Jul 04 06:45:40 PM PDT 24
Peak memory 200348 kb
Host smart-95fd6aba-c610-4242-a8e2-3f0308429140
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870306745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.870306745
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2390572190
Short name T119
Test name
Test status
Simulation time 97367066 ps
CPU time 1.32 seconds
Started Jul 04 06:45:39 PM PDT 24
Finished Jul 04 06:45:40 PM PDT 24
Peak memory 200416 kb
Host smart-ebc7a8ec-c8a0-46a3-a1c5-cbef1b77bc58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390572190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2390572190
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.793263854
Short name T114
Test name
Test status
Simulation time 414616327 ps
CPU time 1.75 seconds
Started Jul 04 06:45:38 PM PDT 24
Finished Jul 04 06:45:40 PM PDT 24
Peak memory 200492 kb
Host smart-ba018919-0e84-49cb-9350-d1dfeb69e6da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793263854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
793263854
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3901944171
Short name T100
Test name
Test status
Simulation time 83116951 ps
CPU time 0.88 seconds
Started Jul 04 06:45:37 PM PDT 24
Finished Jul 04 06:45:38 PM PDT 24
Peak memory 200224 kb
Host smart-00424a0c-b956-4096-a360-591226b2ccea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901944171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3901944171
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1694230719
Short name T576
Test name
Test status
Simulation time 95577955 ps
CPU time 1.38 seconds
Started Jul 04 06:45:40 PM PDT 24
Finished Jul 04 06:45:41 PM PDT 24
Peak memory 200468 kb
Host smart-bf09573a-2260-4fc3-a129-a010de126d0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694230719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1694230719
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1000125164
Short name T109
Test name
Test status
Simulation time 251579525 ps
CPU time 1.91 seconds
Started Jul 04 06:45:40 PM PDT 24
Finished Jul 04 06:45:42 PM PDT 24
Peak memory 208628 kb
Host smart-e4df2cc8-0819-43cc-a746-8f5d19b023be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000125164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1000125164
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.247394123
Short name T85
Test name
Test status
Simulation time 867709529 ps
CPU time 3.12 seconds
Started Jul 04 06:45:40 PM PDT 24
Finished Jul 04 06:45:43 PM PDT 24
Peak memory 200500 kb
Host smart-c8640c8a-789b-4dd5-b400-b30838d2893f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247394123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
247394123
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1460857976
Short name T84
Test name
Test status
Simulation time 109278778 ps
CPU time 0.93 seconds
Started Jul 04 06:45:40 PM PDT 24
Finished Jul 04 06:45:42 PM PDT 24
Peak memory 200456 kb
Host smart-1c5a967c-a77f-4c21-84b3-adc09b34390a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460857976 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1460857976
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1282351245
Short name T561
Test name
Test status
Simulation time 60206755 ps
CPU time 0.78 seconds
Started Jul 04 06:45:38 PM PDT 24
Finished Jul 04 06:45:39 PM PDT 24
Peak memory 200244 kb
Host smart-ba9ad4c9-bc1e-4b00-94b6-b5c90f4da45a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282351245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1282351245
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2255553418
Short name T60
Test name
Test status
Simulation time 245500618 ps
CPU time 1.72 seconds
Started Jul 04 06:45:40 PM PDT 24
Finished Jul 04 06:45:42 PM PDT 24
Peak memory 200428 kb
Host smart-120bd332-d7c9-459f-90cb-0b91163b8963
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255553418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2255553418
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1967236126
Short name T575
Test name
Test status
Simulation time 482151392 ps
CPU time 3.92 seconds
Started Jul 04 06:45:38 PM PDT 24
Finished Jul 04 06:45:42 PM PDT 24
Peak memory 212224 kb
Host smart-7b99950b-a027-4282-b067-f8c8669b956c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967236126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1967236126
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.126507451
Short name T59
Test name
Test status
Simulation time 421992850 ps
CPU time 1.78 seconds
Started Jul 04 06:45:39 PM PDT 24
Finished Jul 04 06:45:41 PM PDT 24
Peak memory 200472 kb
Host smart-ce636560-16a2-4c51-94f8-fafa7ca2d48f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126507451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
126507451
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1014450358
Short name T334
Test name
Test status
Simulation time 67744574 ps
CPU time 0.78 seconds
Started Jul 04 05:19:11 PM PDT 24
Finished Jul 04 05:19:12 PM PDT 24
Peak memory 199904 kb
Host smart-cb3585f2-dc13-417f-96fc-ba4c96bc6a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014450358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1014450358
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2981833782
Short name T33
Test name
Test status
Simulation time 2358929614 ps
CPU time 8.12 seconds
Started Jul 04 05:19:11 PM PDT 24
Finished Jul 04 05:19:19 PM PDT 24
Peak memory 217772 kb
Host smart-d3e1261d-8fc2-4062-b60a-0a70094fef83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981833782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2981833782
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2466378491
Short name T344
Test name
Test status
Simulation time 246320317 ps
CPU time 1.02 seconds
Started Jul 04 05:19:13 PM PDT 24
Finished Jul 04 05:19:14 PM PDT 24
Peak memory 217476 kb
Host smart-e40204b5-8c76-47fe-9e2e-4539648cc242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466378491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2466378491
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3488638776
Short name T278
Test name
Test status
Simulation time 133941849 ps
CPU time 0.79 seconds
Started Jul 04 05:19:13 PM PDT 24
Finished Jul 04 05:19:14 PM PDT 24
Peak memory 199900 kb
Host smart-cddb588b-1dd5-4bcc-96be-85f00020995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488638776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3488638776
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2749270825
Short name T453
Test name
Test status
Simulation time 1575922704 ps
CPU time 5.88 seconds
Started Jul 04 05:19:11 PM PDT 24
Finished Jul 04 05:19:18 PM PDT 24
Peak memory 200356 kb
Host smart-cba69b2d-af4d-47e2-bb98-f0d9ec4ee2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749270825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2749270825
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.881641430
Short name T528
Test name
Test status
Simulation time 143439340 ps
CPU time 1.15 seconds
Started Jul 04 05:19:12 PM PDT 24
Finished Jul 04 05:19:14 PM PDT 24
Peak memory 200080 kb
Host smart-9c8a585d-b5fa-4042-b911-292c94d96b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881641430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.881641430
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2169016947
Short name T213
Test name
Test status
Simulation time 233358023 ps
CPU time 1.33 seconds
Started Jul 04 05:19:12 PM PDT 24
Finished Jul 04 05:19:13 PM PDT 24
Peak memory 200212 kb
Host smart-39fe80bf-0c5d-4c0d-8626-ab32d848c1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169016947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2169016947
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1648892983
Short name T29
Test name
Test status
Simulation time 3037398147 ps
CPU time 13.56 seconds
Started Jul 04 05:19:12 PM PDT 24
Finished Jul 04 05:19:26 PM PDT 24
Peak memory 200376 kb
Host smart-9e78b13f-88f8-4a92-bb6b-cb9579f95c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648892983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1648892983
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2071874282
Short name T5
Test name
Test status
Simulation time 312702589 ps
CPU time 2 seconds
Started Jul 04 05:19:13 PM PDT 24
Finished Jul 04 05:19:15 PM PDT 24
Peak memory 200088 kb
Host smart-d5b09276-b335-4f91-a0c3-29d0610b1009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071874282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2071874282
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.516353490
Short name T322
Test name
Test status
Simulation time 233114651 ps
CPU time 1.24 seconds
Started Jul 04 05:19:13 PM PDT 24
Finished Jul 04 05:19:14 PM PDT 24
Peak memory 200084 kb
Host smart-d169cfce-4ce1-4a6e-b18d-c11c14bb5134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516353490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.516353490
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3182253235
Short name T423
Test name
Test status
Simulation time 2165422205 ps
CPU time 7.54 seconds
Started Jul 04 05:19:20 PM PDT 24
Finished Jul 04 05:19:28 PM PDT 24
Peak memory 217744 kb
Host smart-d38c3fb6-2d10-45e9-a2b3-bf9b8498d516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182253235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3182253235
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1595320919
Short name T66
Test name
Test status
Simulation time 244276864 ps
CPU time 1.05 seconds
Started Jul 04 05:19:22 PM PDT 24
Finished Jul 04 05:19:24 PM PDT 24
Peak memory 217324 kb
Host smart-d2803bda-809b-489c-8916-0d22eb21a106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595320919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1595320919
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.242837386
Short name T536
Test name
Test status
Simulation time 117152659 ps
CPU time 0.8 seconds
Started Jul 04 05:19:12 PM PDT 24
Finished Jul 04 05:19:13 PM PDT 24
Peak memory 199892 kb
Host smart-e5fe2dec-6906-418a-bdbd-03b7a9108537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242837386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.242837386
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.526621548
Short name T307
Test name
Test status
Simulation time 1638493708 ps
CPU time 6.4 seconds
Started Jul 04 05:19:14 PM PDT 24
Finished Jul 04 05:19:20 PM PDT 24
Peak memory 200376 kb
Host smart-cd9c3698-d625-4e12-bdb0-d4c3958fc526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526621548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.526621548
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3772096492
Short name T72
Test name
Test status
Simulation time 8412232331 ps
CPU time 14.17 seconds
Started Jul 04 05:19:22 PM PDT 24
Finished Jul 04 05:19:36 PM PDT 24
Peak memory 217676 kb
Host smart-202d498e-443d-4c3e-a154-582f5bcfd717
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772096492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3772096492
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.536124491
Short name T197
Test name
Test status
Simulation time 184029109 ps
CPU time 1.21 seconds
Started Jul 04 05:19:12 PM PDT 24
Finished Jul 04 05:19:13 PM PDT 24
Peak memory 200076 kb
Host smart-254807c6-32be-4e10-8640-874603260a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536124491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.536124491
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3268044559
Short name T193
Test name
Test status
Simulation time 123746735 ps
CPU time 1.17 seconds
Started Jul 04 05:19:12 PM PDT 24
Finished Jul 04 05:19:13 PM PDT 24
Peak memory 200296 kb
Host smart-0bda00cd-c241-4418-8644-df854ce95797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268044559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3268044559
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3819295559
Short name T391
Test name
Test status
Simulation time 3285685973 ps
CPU time 12.03 seconds
Started Jul 04 05:19:22 PM PDT 24
Finished Jul 04 05:19:34 PM PDT 24
Peak memory 208604 kb
Host smart-7c1fe5e9-f399-493f-a4e5-9ba168ef47da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819295559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3819295559
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.30785512
Short name T242
Test name
Test status
Simulation time 134940082 ps
CPU time 1.87 seconds
Started Jul 04 05:19:11 PM PDT 24
Finished Jul 04 05:19:14 PM PDT 24
Peak memory 200100 kb
Host smart-5b336921-df14-4b84-83e4-f37bac05abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30785512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.30785512
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.211606622
Short name T321
Test name
Test status
Simulation time 148397575 ps
CPU time 1.16 seconds
Started Jul 04 05:19:13 PM PDT 24
Finished Jul 04 05:19:15 PM PDT 24
Peak memory 200100 kb
Host smart-879f68dd-d145-47f8-95ed-c40c35e0c4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211606622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.211606622
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.596421978
Short name T158
Test name
Test status
Simulation time 82030020 ps
CPU time 0.82 seconds
Started Jul 04 05:20:08 PM PDT 24
Finished Jul 04 05:20:09 PM PDT 24
Peak memory 199880 kb
Host smart-bd993274-bed3-4f71-afb9-959c0c1cb523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596421978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.596421978
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1482377233
Short name T497
Test name
Test status
Simulation time 1911707547 ps
CPU time 7.25 seconds
Started Jul 04 05:20:10 PM PDT 24
Finished Jul 04 05:20:17 PM PDT 24
Peak memory 217668 kb
Host smart-9b7d81ba-ae83-46e4-8f34-3437f1b2f477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482377233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1482377233
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.4060447115
Short name T408
Test name
Test status
Simulation time 244082144 ps
CPU time 1.08 seconds
Started Jul 04 05:20:10 PM PDT 24
Finished Jul 04 05:20:11 PM PDT 24
Peak memory 217456 kb
Host smart-e1ba5ffd-e889-47c7-bfcc-4878f7224a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060447115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.4060447115
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3651217261
Short name T24
Test name
Test status
Simulation time 77698903 ps
CPU time 0.78 seconds
Started Jul 04 05:20:11 PM PDT 24
Finished Jul 04 05:20:12 PM PDT 24
Peak memory 199916 kb
Host smart-d8994170-f014-4d78-b84a-43e3c74823e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651217261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3651217261
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2324173680
Short name T342
Test name
Test status
Simulation time 1796046429 ps
CPU time 6.79 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:16 PM PDT 24
Peak memory 200352 kb
Host smart-4319460f-5819-4284-83e8-fd991e020571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324173680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2324173680
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.642433549
Short name T326
Test name
Test status
Simulation time 109872546 ps
CPU time 1.04 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:10 PM PDT 24
Peak memory 200084 kb
Host smart-22255e70-e75c-4be9-a667-49ffe7dfec06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642433549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.642433549
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.662543450
Short name T399
Test name
Test status
Simulation time 229067668 ps
CPU time 1.51 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:11 PM PDT 24
Peak memory 200268 kb
Host smart-dbf152e4-6292-4366-9d70-e7fd32f45add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662543450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.662543450
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2508109925
Short name T265
Test name
Test status
Simulation time 1023918476 ps
CPU time 4.33 seconds
Started Jul 04 05:20:06 PM PDT 24
Finished Jul 04 05:20:11 PM PDT 24
Peak memory 200284 kb
Host smart-b62f93d9-de53-435a-a5a6-9d995d5ce802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508109925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2508109925
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1906865133
Short name T525
Test name
Test status
Simulation time 302108450 ps
CPU time 2.05 seconds
Started Jul 04 05:20:10 PM PDT 24
Finished Jul 04 05:20:12 PM PDT 24
Peak memory 208308 kb
Host smart-ee34cc97-cd04-4664-b445-f4a3c5116dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906865133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1906865133
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1831117697
Short name T156
Test name
Test status
Simulation time 149111062 ps
CPU time 1.26 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:11 PM PDT 24
Peak memory 200280 kb
Host smart-f7bb7717-fc16-4f07-a739-e76c650d3ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831117697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1831117697
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1574553374
Short name T354
Test name
Test status
Simulation time 72361358 ps
CPU time 0.76 seconds
Started Jul 04 05:20:08 PM PDT 24
Finished Jul 04 05:20:09 PM PDT 24
Peak memory 199824 kb
Host smart-8f948cef-ef59-40b5-871f-62ce0524934a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574553374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1574553374
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.235226429
Short name T365
Test name
Test status
Simulation time 1225166776 ps
CPU time 5.43 seconds
Started Jul 04 05:20:10 PM PDT 24
Finished Jul 04 05:20:16 PM PDT 24
Peak memory 217708 kb
Host smart-7e7d548f-65f0-4887-a059-559de3f047f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235226429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.235226429
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3041192634
Short name T336
Test name
Test status
Simulation time 244696463 ps
CPU time 1.04 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:11 PM PDT 24
Peak memory 217432 kb
Host smart-0ee5b5f3-b9d1-4173-a963-72945574d9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041192634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3041192634
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3284629041
Short name T19
Test name
Test status
Simulation time 77822397 ps
CPU time 0.73 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:10 PM PDT 24
Peak memory 199904 kb
Host smart-4ed5428b-2b4d-4ca1-9f66-37ca79c99230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284629041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3284629041
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3015799736
Short name T232
Test name
Test status
Simulation time 108438519 ps
CPU time 1.01 seconds
Started Jul 04 05:20:10 PM PDT 24
Finished Jul 04 05:20:11 PM PDT 24
Peak memory 200080 kb
Host smart-f2a093f7-2770-48bb-ae68-36b2aa0a019f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015799736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3015799736
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2910877575
Short name T260
Test name
Test status
Simulation time 228868498 ps
CPU time 1.48 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:10 PM PDT 24
Peak memory 200216 kb
Host smart-01314a25-539c-419e-b561-01bd082a879f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910877575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2910877575
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3509049632
Short name T179
Test name
Test status
Simulation time 10356787284 ps
CPU time 38.03 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:48 PM PDT 24
Peak memory 208612 kb
Host smart-46f71120-70b3-49b4-b194-71872218abf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509049632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3509049632
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.4106983204
Short name T205
Test name
Test status
Simulation time 365151700 ps
CPU time 2.1 seconds
Started Jul 04 05:20:10 PM PDT 24
Finished Jul 04 05:20:13 PM PDT 24
Peak memory 208288 kb
Host smart-fe107e06-4496-4ff8-908d-ca5107c21b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106983204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.4106983204
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1238830257
Short name T527
Test name
Test status
Simulation time 59738615 ps
CPU time 0.75 seconds
Started Jul 04 05:20:08 PM PDT 24
Finished Jul 04 05:20:09 PM PDT 24
Peak memory 200052 kb
Host smart-4da1976a-2777-44cf-9df9-c0ec65a9437a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238830257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1238830257
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.4266206892
Short name T455
Test name
Test status
Simulation time 58277050 ps
CPU time 0.74 seconds
Started Jul 04 05:20:11 PM PDT 24
Finished Jul 04 05:20:12 PM PDT 24
Peak memory 199900 kb
Host smart-0d15d0f4-a2d5-498e-8515-311a18953ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266206892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4266206892
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3425090165
Short name T341
Test name
Test status
Simulation time 1250046478 ps
CPU time 5.51 seconds
Started Jul 04 05:20:10 PM PDT 24
Finished Jul 04 05:20:16 PM PDT 24
Peak memory 217512 kb
Host smart-82cfb909-a350-4fdb-9211-ae1c264fbe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425090165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3425090165
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2090657365
Short name T244
Test name
Test status
Simulation time 245740448 ps
CPU time 1.05 seconds
Started Jul 04 05:20:11 PM PDT 24
Finished Jul 04 05:20:12 PM PDT 24
Peak memory 217476 kb
Host smart-1b90235b-b6c9-4bf1-bb1e-0b5a5948ea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090657365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2090657365
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3136384357
Short name T360
Test name
Test status
Simulation time 127651225 ps
CPU time 0.77 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:10 PM PDT 24
Peak memory 199876 kb
Host smart-827bb5f8-d3b8-4fdf-ba98-2ed4c9a3bf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136384357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3136384357
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1984802061
Short name T301
Test name
Test status
Simulation time 1555344884 ps
CPU time 5.85 seconds
Started Jul 04 05:20:11 PM PDT 24
Finished Jul 04 05:20:17 PM PDT 24
Peak memory 200364 kb
Host smart-f1de9ac0-728c-418e-aebe-824c4bd0a362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984802061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1984802061
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3697632159
Short name T77
Test name
Test status
Simulation time 177206700 ps
CPU time 1.26 seconds
Started Jul 04 05:20:10 PM PDT 24
Finished Jul 04 05:20:12 PM PDT 24
Peak memory 200084 kb
Host smart-305d061c-6b08-42ba-954f-bdd5bd768e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697632159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3697632159
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3813615427
Short name T327
Test name
Test status
Simulation time 210152907 ps
CPU time 1.38 seconds
Started Jul 04 05:20:08 PM PDT 24
Finished Jul 04 05:20:09 PM PDT 24
Peak memory 200232 kb
Host smart-01bd8375-652f-4068-9c64-9c62da4a19e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813615427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3813615427
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.714091282
Short name T203
Test name
Test status
Simulation time 7371553606 ps
CPU time 23.6 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:32 PM PDT 24
Peak memory 216824 kb
Host smart-3368b348-a603-4e1c-af4d-19619139f613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714091282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.714091282
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.4164563099
Short name T284
Test name
Test status
Simulation time 390914677 ps
CPU time 2.06 seconds
Started Jul 04 05:20:08 PM PDT 24
Finished Jul 04 05:20:10 PM PDT 24
Peak memory 200088 kb
Host smart-6a9fe69d-7416-41c3-a024-3ff74d445e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164563099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.4164563099
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3862411797
Short name T485
Test name
Test status
Simulation time 144746604 ps
CPU time 1.05 seconds
Started Jul 04 05:20:06 PM PDT 24
Finished Jul 04 05:20:07 PM PDT 24
Peak memory 200076 kb
Host smart-8e2bbe77-3140-4007-a76e-d0cd82c8c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862411797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3862411797
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.439388962
Short name T237
Test name
Test status
Simulation time 93454691 ps
CPU time 0.88 seconds
Started Jul 04 05:20:20 PM PDT 24
Finished Jul 04 05:20:21 PM PDT 24
Peak memory 199900 kb
Host smart-e97d1b05-64ee-4d72-b406-46f854cadb03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439388962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.439388962
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3870668933
Short name T51
Test name
Test status
Simulation time 1907459112 ps
CPU time 6.99 seconds
Started Jul 04 05:20:17 PM PDT 24
Finished Jul 04 05:20:24 PM PDT 24
Peak memory 217660 kb
Host smart-53e9a2e0-332a-4676-be9c-32668027b251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870668933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3870668933
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3263064813
Short name T235
Test name
Test status
Simulation time 245106885 ps
CPU time 1.04 seconds
Started Jul 04 05:20:17 PM PDT 24
Finished Jul 04 05:20:18 PM PDT 24
Peak memory 217456 kb
Host smart-441ee68e-aafd-46c8-904e-f89c44c9184c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263064813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3263064813
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2468139108
Short name T20
Test name
Test status
Simulation time 114565191 ps
CPU time 0.8 seconds
Started Jul 04 05:20:20 PM PDT 24
Finished Jul 04 05:20:21 PM PDT 24
Peak memory 199904 kb
Host smart-02b32824-5e5a-4655-8db7-26d95891f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468139108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2468139108
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.106459638
Short name T465
Test name
Test status
Simulation time 1219505476 ps
CPU time 4.62 seconds
Started Jul 04 05:20:16 PM PDT 24
Finished Jul 04 05:20:21 PM PDT 24
Peak memory 200364 kb
Host smart-af1510ae-5cc6-4b89-a4b5-826cb1c76097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106459638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.106459638
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.187566758
Short name T420
Test name
Test status
Simulation time 115148887 ps
CPU time 1 seconds
Started Jul 04 05:20:16 PM PDT 24
Finished Jul 04 05:20:18 PM PDT 24
Peak memory 200056 kb
Host smart-610e4b20-f151-4b21-900f-21b9be09057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187566758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.187566758
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.4210922642
Short name T140
Test name
Test status
Simulation time 190864994 ps
CPU time 1.39 seconds
Started Jul 04 05:20:16 PM PDT 24
Finished Jul 04 05:20:17 PM PDT 24
Peak memory 200304 kb
Host smart-3d21d994-46f4-4252-a8c3-5b6de52be442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210922642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.4210922642
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.307999595
Short name T406
Test name
Test status
Simulation time 373791570 ps
CPU time 2.49 seconds
Started Jul 04 05:20:16 PM PDT 24
Finished Jul 04 05:20:19 PM PDT 24
Peak memory 200084 kb
Host smart-d4c4fcbc-d45f-484c-bd31-a816d379f1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307999595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.307999595
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4077815065
Short name T467
Test name
Test status
Simulation time 204407846 ps
CPU time 1.34 seconds
Started Jul 04 05:20:21 PM PDT 24
Finished Jul 04 05:20:23 PM PDT 24
Peak memory 200092 kb
Host smart-e22eb98c-9bc5-479b-97e0-d68c931254ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077815065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4077815065
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.647605632
Short name T52
Test name
Test status
Simulation time 76447550 ps
CPU time 0.81 seconds
Started Jul 04 05:20:18 PM PDT 24
Finished Jul 04 05:20:19 PM PDT 24
Peak memory 199880 kb
Host smart-b9387c4d-dbf2-4f00-80c9-964754c8f934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647605632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.647605632
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1184831844
Short name T358
Test name
Test status
Simulation time 1225450681 ps
CPU time 5.54 seconds
Started Jul 04 05:20:16 PM PDT 24
Finished Jul 04 05:20:22 PM PDT 24
Peak memory 217732 kb
Host smart-15be5ff8-194e-445c-9cfa-2a2ae4511c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184831844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1184831844
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3122827290
Short name T45
Test name
Test status
Simulation time 244454596 ps
CPU time 1.11 seconds
Started Jul 04 05:20:16 PM PDT 24
Finished Jul 04 05:20:17 PM PDT 24
Peak memory 217472 kb
Host smart-3047185a-4cdf-4cb8-be8a-23e03a052b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122827290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3122827290
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3701085568
Short name T517
Test name
Test status
Simulation time 144123277 ps
CPU time 0.85 seconds
Started Jul 04 05:20:16 PM PDT 24
Finished Jul 04 05:20:17 PM PDT 24
Peak memory 199872 kb
Host smart-42d4b120-d49b-4953-a231-d6c7b750bc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701085568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3701085568
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3836647125
Short name T277
Test name
Test status
Simulation time 941153939 ps
CPU time 4.43 seconds
Started Jul 04 05:20:16 PM PDT 24
Finished Jul 04 05:20:21 PM PDT 24
Peak memory 200340 kb
Host smart-fe036529-cac0-489a-b212-bd92e8e85e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836647125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3836647125
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3248451402
Short name T256
Test name
Test status
Simulation time 144034255 ps
CPU time 1.04 seconds
Started Jul 04 05:20:16 PM PDT 24
Finished Jul 04 05:20:17 PM PDT 24
Peak memory 200076 kb
Host smart-dc540048-58be-4773-ae75-e53832ca632e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248451402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3248451402
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2681814018
Short name T503
Test name
Test status
Simulation time 186942996 ps
CPU time 1.33 seconds
Started Jul 04 05:20:22 PM PDT 24
Finished Jul 04 05:20:23 PM PDT 24
Peak memory 200308 kb
Host smart-d5154f60-c5b9-424f-8d86-5c8524716ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681814018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2681814018
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.799668468
Short name T279
Test name
Test status
Simulation time 6959078369 ps
CPU time 25.13 seconds
Started Jul 04 05:20:15 PM PDT 24
Finished Jul 04 05:20:40 PM PDT 24
Peak memory 200424 kb
Host smart-d439cf26-1429-448f-a6d3-01119221ba31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799668468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.799668468
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.768252788
Short name T173
Test name
Test status
Simulation time 516784124 ps
CPU time 2.95 seconds
Started Jul 04 05:20:18 PM PDT 24
Finished Jul 04 05:20:21 PM PDT 24
Peak memory 200108 kb
Host smart-79aa29c9-d994-47a0-aec7-aef3ed2e750e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768252788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.768252788
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2163067664
Short name T541
Test name
Test status
Simulation time 169613768 ps
CPU time 1.15 seconds
Started Jul 04 05:20:18 PM PDT 24
Finished Jul 04 05:20:19 PM PDT 24
Peak memory 200092 kb
Host smart-51675f53-8e14-4322-a84f-5dab169a07a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163067664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2163067664
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3810594452
Short name T373
Test name
Test status
Simulation time 61499112 ps
CPU time 0.75 seconds
Started Jul 04 05:20:24 PM PDT 24
Finished Jul 04 05:20:25 PM PDT 24
Peak memory 199892 kb
Host smart-5005f447-56a5-40cf-8a51-d3e228b555e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810594452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3810594452
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1268483763
Short name T34
Test name
Test status
Simulation time 1229171183 ps
CPU time 5.68 seconds
Started Jul 04 05:20:17 PM PDT 24
Finished Jul 04 05:20:23 PM PDT 24
Peak memory 217712 kb
Host smart-16962ec4-7f0e-4017-956c-4fe9f4a1b795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268483763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1268483763
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.4188891467
Short name T374
Test name
Test status
Simulation time 245154234 ps
CPU time 1.07 seconds
Started Jul 04 05:20:25 PM PDT 24
Finished Jul 04 05:20:27 PM PDT 24
Peak memory 217500 kb
Host smart-eea88f31-4dd9-4736-ae51-e506b9f1dd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188891467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.4188891467
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3251932960
Short name T167
Test name
Test status
Simulation time 202120091 ps
CPU time 1.02 seconds
Started Jul 04 05:20:18 PM PDT 24
Finished Jul 04 05:20:19 PM PDT 24
Peak memory 199904 kb
Host smart-bf0e3ad0-5da9-41b9-9103-642a04292371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251932960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3251932960
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1817591624
Short name T306
Test name
Test status
Simulation time 1944627346 ps
CPU time 7.13 seconds
Started Jul 04 05:20:20 PM PDT 24
Finished Jul 04 05:20:27 PM PDT 24
Peak memory 200368 kb
Host smart-d7d40e7a-282c-42bd-8e97-d10591fdcdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817591624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1817591624
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3367270731
Short name T191
Test name
Test status
Simulation time 103119391 ps
CPU time 1.01 seconds
Started Jul 04 05:20:17 PM PDT 24
Finished Jul 04 05:20:19 PM PDT 24
Peak memory 200084 kb
Host smart-c48bf47f-cbb3-410c-85a7-0213b2b69559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367270731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3367270731
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.275344278
Short name T415
Test name
Test status
Simulation time 113245536 ps
CPU time 1.18 seconds
Started Jul 04 05:20:18 PM PDT 24
Finished Jul 04 05:20:19 PM PDT 24
Peak memory 200312 kb
Host smart-2400a450-f778-4aeb-9245-a64061d10446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275344278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.275344278
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1893647652
Short name T471
Test name
Test status
Simulation time 4063521599 ps
CPU time 18.07 seconds
Started Jul 04 05:20:27 PM PDT 24
Finished Jul 04 05:20:45 PM PDT 24
Peak memory 200424 kb
Host smart-773378a0-4b9b-488d-baf4-90d52549356c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893647652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1893647652
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2619729128
Short name T271
Test name
Test status
Simulation time 366363976 ps
CPU time 1.96 seconds
Started Jul 04 05:20:15 PM PDT 24
Finished Jul 04 05:20:18 PM PDT 24
Peak memory 200088 kb
Host smart-f22132e4-4aed-480b-9829-b82f91457439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619729128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2619729128
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3478793622
Short name T164
Test name
Test status
Simulation time 93989735 ps
CPU time 0.86 seconds
Started Jul 04 05:20:17 PM PDT 24
Finished Jul 04 05:20:18 PM PDT 24
Peak memory 200080 kb
Host smart-1cd3522c-1da8-4e64-8850-9a6db42786ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478793622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3478793622
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3512157185
Short name T484
Test name
Test status
Simulation time 78495482 ps
CPU time 0.78 seconds
Started Jul 04 05:20:26 PM PDT 24
Finished Jul 04 05:20:27 PM PDT 24
Peak memory 199880 kb
Host smart-d081c82a-2e31-406f-a93f-eb1d2120b304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512157185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3512157185
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1245547669
Short name T412
Test name
Test status
Simulation time 1907626191 ps
CPU time 6.81 seconds
Started Jul 04 05:20:25 PM PDT 24
Finished Jul 04 05:20:32 PM PDT 24
Peak memory 216736 kb
Host smart-7eb4d64e-044e-481b-b0b3-f5b55860ca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245547669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1245547669
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2862480344
Short name T361
Test name
Test status
Simulation time 246623283 ps
CPU time 1.03 seconds
Started Jul 04 05:20:26 PM PDT 24
Finished Jul 04 05:20:27 PM PDT 24
Peak memory 217444 kb
Host smart-1661720d-9f35-4600-8e12-34934ef4d7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862480344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2862480344
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2947547731
Short name T234
Test name
Test status
Simulation time 208028645 ps
CPU time 0.89 seconds
Started Jul 04 05:20:26 PM PDT 24
Finished Jul 04 05:20:27 PM PDT 24
Peak memory 199900 kb
Host smart-b0d710de-03ae-4f5d-ba6d-5bd83ec9d711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947547731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2947547731
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1217994419
Short name T230
Test name
Test status
Simulation time 1425205529 ps
CPU time 5.25 seconds
Started Jul 04 05:20:25 PM PDT 24
Finished Jul 04 05:20:30 PM PDT 24
Peak memory 200296 kb
Host smart-05bb8e6d-1b72-41bb-af8b-abc5f59a7715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217994419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1217994419
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.623924662
Short name T149
Test name
Test status
Simulation time 180774166 ps
CPU time 1.21 seconds
Started Jul 04 05:20:28 PM PDT 24
Finished Jul 04 05:20:29 PM PDT 24
Peak memory 200084 kb
Host smart-d2be36f9-c271-4bc3-b896-6335e0c94a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623924662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.623924662
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3473090053
Short name T222
Test name
Test status
Simulation time 115072898 ps
CPU time 1.23 seconds
Started Jul 04 05:20:25 PM PDT 24
Finished Jul 04 05:20:26 PM PDT 24
Peak memory 200268 kb
Host smart-d0f05b29-10c5-4f7b-83df-7778b7ec00d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473090053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3473090053
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2779701575
Short name T335
Test name
Test status
Simulation time 5496275623 ps
CPU time 21.09 seconds
Started Jul 04 05:20:25 PM PDT 24
Finished Jul 04 05:20:46 PM PDT 24
Peak memory 208592 kb
Host smart-aca3e422-4d47-487c-8d6b-be9c960b2cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779701575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2779701575
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.985539618
Short name T146
Test name
Test status
Simulation time 113331586 ps
CPU time 1.54 seconds
Started Jul 04 05:20:23 PM PDT 24
Finished Jul 04 05:20:25 PM PDT 24
Peak memory 200088 kb
Host smart-8aea2f87-fcc1-4d54-9ff6-b8f1c6749f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985539618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.985539618
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3641040492
Short name T429
Test name
Test status
Simulation time 201108992 ps
CPU time 1.29 seconds
Started Jul 04 05:20:24 PM PDT 24
Finished Jul 04 05:20:25 PM PDT 24
Peak memory 200076 kb
Host smart-0dc0367a-88b4-478a-b309-c40fd5578db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641040492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3641040492
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3204932151
Short name T209
Test name
Test status
Simulation time 71158095 ps
CPU time 0.74 seconds
Started Jul 04 05:20:26 PM PDT 24
Finished Jul 04 05:20:27 PM PDT 24
Peak memory 199880 kb
Host smart-f289367c-870b-48d2-ac71-ee8935df856c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204932151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3204932151
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2500511570
Short name T462
Test name
Test status
Simulation time 2355224761 ps
CPU time 9.35 seconds
Started Jul 04 05:20:24 PM PDT 24
Finished Jul 04 05:20:34 PM PDT 24
Peak memory 221760 kb
Host smart-297e9a23-71ef-4221-9ff2-18f16905564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500511570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2500511570
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2735654094
Short name T67
Test name
Test status
Simulation time 243957931 ps
CPU time 1.09 seconds
Started Jul 04 05:20:27 PM PDT 24
Finished Jul 04 05:20:28 PM PDT 24
Peak memory 217488 kb
Host smart-78889048-e44c-436c-b266-b0d20e387af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735654094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2735654094
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1641739648
Short name T229
Test name
Test status
Simulation time 90786627 ps
CPU time 0.76 seconds
Started Jul 04 05:20:25 PM PDT 24
Finished Jul 04 05:20:26 PM PDT 24
Peak memory 199904 kb
Host smart-95a7f212-93e7-4e0f-a568-325d295b83d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641739648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1641739648
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.150902679
Short name T250
Test name
Test status
Simulation time 982869601 ps
CPU time 5.1 seconds
Started Jul 04 05:20:26 PM PDT 24
Finished Jul 04 05:20:31 PM PDT 24
Peak memory 200376 kb
Host smart-5f885197-ea39-43ab-827f-61f78b042be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150902679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.150902679
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3624379402
Short name T359
Test name
Test status
Simulation time 114242747 ps
CPU time 1.05 seconds
Started Jul 04 05:20:25 PM PDT 24
Finished Jul 04 05:20:26 PM PDT 24
Peak memory 200020 kb
Host smart-2411eb63-a13e-4677-be81-d408fae50bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624379402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3624379402
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1984574172
Short name T249
Test name
Test status
Simulation time 116859395 ps
CPU time 1.17 seconds
Started Jul 04 05:20:28 PM PDT 24
Finished Jul 04 05:20:29 PM PDT 24
Peak memory 200304 kb
Host smart-09b4c60a-1cd5-41e9-b0ec-1328fb829869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984574172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1984574172
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.4048368604
Short name T124
Test name
Test status
Simulation time 5021740731 ps
CPU time 17.09 seconds
Started Jul 04 05:20:24 PM PDT 24
Finished Jul 04 05:20:42 PM PDT 24
Peak memory 210256 kb
Host smart-bd7d590d-cb69-446f-9887-a10490457fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048368604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.4048368604
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1411842059
Short name T537
Test name
Test status
Simulation time 494115341 ps
CPU time 2.55 seconds
Started Jul 04 05:20:24 PM PDT 24
Finished Jul 04 05:20:27 PM PDT 24
Peak memory 200064 kb
Host smart-1624bdb2-e2aa-4aac-8de5-4a95696e7c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411842059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1411842059
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1950071549
Short name T177
Test name
Test status
Simulation time 285495821 ps
CPU time 1.62 seconds
Started Jul 04 05:20:24 PM PDT 24
Finished Jul 04 05:20:26 PM PDT 24
Peak memory 200056 kb
Host smart-6b690958-c9df-4c49-a51b-b47815ea40f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950071549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1950071549
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2658096522
Short name T139
Test name
Test status
Simulation time 54781864 ps
CPU time 0.71 seconds
Started Jul 04 05:20:35 PM PDT 24
Finished Jul 04 05:20:36 PM PDT 24
Peak memory 199852 kb
Host smart-6698cec0-248b-4702-aa7b-bb913b0afdbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658096522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2658096522
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3272124988
Short name T294
Test name
Test status
Simulation time 1218839530 ps
CPU time 5.92 seconds
Started Jul 04 05:20:34 PM PDT 24
Finished Jul 04 05:20:40 PM PDT 24
Peak memory 216968 kb
Host smart-698b32bb-bcf8-45d0-a95d-106e44b5ee11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272124988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3272124988
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4216818273
Short name T350
Test name
Test status
Simulation time 245250381 ps
CPU time 1.03 seconds
Started Jul 04 05:20:34 PM PDT 24
Finished Jul 04 05:20:35 PM PDT 24
Peak memory 217480 kb
Host smart-9f2fa5a6-bea1-47da-aea9-a1aec65565f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216818273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4216818273
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3149750769
Short name T199
Test name
Test status
Simulation time 75980240 ps
CPU time 0.71 seconds
Started Jul 04 05:20:25 PM PDT 24
Finished Jul 04 05:20:26 PM PDT 24
Peak memory 199840 kb
Host smart-f9a53e0a-d08c-4487-9ea5-ef8fbab50883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149750769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3149750769
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1431570239
Short name T231
Test name
Test status
Simulation time 2026710113 ps
CPU time 7.28 seconds
Started Jul 04 05:20:25 PM PDT 24
Finished Jul 04 05:20:33 PM PDT 24
Peak memory 200376 kb
Host smart-e4e8f9d8-951b-4d90-9345-5bac7b1dc3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431570239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1431570239
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1653022194
Short name T27
Test name
Test status
Simulation time 97907194 ps
CPU time 1.03 seconds
Started Jul 04 05:20:34 PM PDT 24
Finished Jul 04 05:20:35 PM PDT 24
Peak memory 200084 kb
Host smart-a6491d9b-04b6-4719-a941-ffae9bb32c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653022194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1653022194
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3867897709
Short name T126
Test name
Test status
Simulation time 252524793 ps
CPU time 1.61 seconds
Started Jul 04 05:20:26 PM PDT 24
Finished Jul 04 05:20:28 PM PDT 24
Peak memory 200292 kb
Host smart-a2d36c01-4861-477b-b508-861c83b49a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867897709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3867897709
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1268372001
Short name T92
Test name
Test status
Simulation time 1344749097 ps
CPU time 5.29 seconds
Started Jul 04 05:20:32 PM PDT 24
Finished Jul 04 05:20:38 PM PDT 24
Peak memory 200280 kb
Host smart-2a87228d-f7d8-487a-a573-c4135ae5313c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268372001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1268372001
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1852994431
Short name T468
Test name
Test status
Simulation time 283166577 ps
CPU time 1.9 seconds
Started Jul 04 05:20:34 PM PDT 24
Finished Jul 04 05:20:36 PM PDT 24
Peak memory 200024 kb
Host smart-f82f6947-feaa-49d6-9429-83596c8e5744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852994431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1852994431
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2110467880
Short name T131
Test name
Test status
Simulation time 99694242 ps
CPU time 0.98 seconds
Started Jul 04 05:20:26 PM PDT 24
Finished Jul 04 05:20:28 PM PDT 24
Peak memory 200080 kb
Host smart-e0172c69-faf2-4d5b-af5c-cf612fa22ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110467880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2110467880
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2154229218
Short name T500
Test name
Test status
Simulation time 81526612 ps
CPU time 0.83 seconds
Started Jul 04 05:20:33 PM PDT 24
Finished Jul 04 05:20:34 PM PDT 24
Peak memory 199840 kb
Host smart-a302859c-814b-4739-914c-d424ba48ebf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154229218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2154229218
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2798663901
Short name T309
Test name
Test status
Simulation time 2164674590 ps
CPU time 8.49 seconds
Started Jul 04 05:20:34 PM PDT 24
Finished Jul 04 05:20:43 PM PDT 24
Peak memory 217628 kb
Host smart-b7b6e98a-f053-45ec-9e7f-137168557149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798663901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2798663901
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.524587788
Short name T245
Test name
Test status
Simulation time 244074687 ps
CPU time 1.06 seconds
Started Jul 04 05:20:31 PM PDT 24
Finished Jul 04 05:20:33 PM PDT 24
Peak memory 217432 kb
Host smart-ed9cdd64-9fe1-4ff0-a920-713300ffd936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524587788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.524587788
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.251903793
Short name T369
Test name
Test status
Simulation time 137832869 ps
CPU time 0.81 seconds
Started Jul 04 05:20:33 PM PDT 24
Finished Jul 04 05:20:34 PM PDT 24
Peak memory 199872 kb
Host smart-24e76239-28dd-47b7-9db7-fb23609cb2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251903793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.251903793
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3414577493
Short name T323
Test name
Test status
Simulation time 922448478 ps
CPU time 5.05 seconds
Started Jul 04 05:20:32 PM PDT 24
Finished Jul 04 05:20:37 PM PDT 24
Peak memory 200412 kb
Host smart-9ab2f0a6-2bf0-4499-8b7a-70db97d57138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414577493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3414577493
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2993292058
Short name T518
Test name
Test status
Simulation time 109897067 ps
CPU time 1.04 seconds
Started Jul 04 05:20:31 PM PDT 24
Finished Jul 04 05:20:33 PM PDT 24
Peak memory 200068 kb
Host smart-ed21b60f-433d-49af-9d23-13dbebe18db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993292058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2993292058
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.407634931
Short name T273
Test name
Test status
Simulation time 199816150 ps
CPU time 1.52 seconds
Started Jul 04 05:20:32 PM PDT 24
Finished Jul 04 05:20:33 PM PDT 24
Peak memory 200272 kb
Host smart-9fd5ec4f-976e-477c-b727-969f85748455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407634931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.407634931
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3799016898
Short name T325
Test name
Test status
Simulation time 9976231097 ps
CPU time 33.74 seconds
Started Jul 04 05:20:35 PM PDT 24
Finished Jul 04 05:21:09 PM PDT 24
Peak memory 208576 kb
Host smart-06b3dd06-82d4-4cf9-8a81-9aca82977624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799016898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3799016898
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3886624852
Short name T457
Test name
Test status
Simulation time 114331302 ps
CPU time 1.54 seconds
Started Jul 04 05:20:34 PM PDT 24
Finished Jul 04 05:20:36 PM PDT 24
Peak memory 200108 kb
Host smart-b145586c-6eee-4909-a145-43462aed0f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886624852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3886624852
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.846850975
Short name T372
Test name
Test status
Simulation time 127787448 ps
CPU time 1.11 seconds
Started Jul 04 05:20:32 PM PDT 24
Finished Jul 04 05:20:34 PM PDT 24
Peak memory 200052 kb
Host smart-7d7efac5-5cef-491e-bae6-03ec01e27fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846850975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.846850975
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.966652728
Short name T185
Test name
Test status
Simulation time 86652930 ps
CPU time 0.82 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:19:31 PM PDT 24
Peak memory 199900 kb
Host smart-609d1973-eeab-4200-a9e8-1f004fabe2cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966652728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.966652728
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3398697825
Short name T31
Test name
Test status
Simulation time 1234951456 ps
CPU time 5.8 seconds
Started Jul 04 05:19:29 PM PDT 24
Finished Jul 04 05:19:35 PM PDT 24
Peak memory 217668 kb
Host smart-6fe9c194-8733-46e9-b153-afb77bddda0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398697825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3398697825
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.4172040791
Short name T145
Test name
Test status
Simulation time 244238085 ps
CPU time 1.04 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:19:31 PM PDT 24
Peak memory 217452 kb
Host smart-b0a62949-a75e-4679-9d83-b054a23770e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172040791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.4172040791
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1437695567
Short name T330
Test name
Test status
Simulation time 234984832 ps
CPU time 1.01 seconds
Started Jul 04 05:19:21 PM PDT 24
Finished Jul 04 05:19:22 PM PDT 24
Peak memory 199848 kb
Host smart-93bd651f-1d7a-4d2a-8cb8-4256b77581a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437695567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1437695567
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1257799284
Short name T57
Test name
Test status
Simulation time 871278620 ps
CPU time 4.67 seconds
Started Jul 04 05:19:21 PM PDT 24
Finished Jul 04 05:19:26 PM PDT 24
Peak memory 200348 kb
Host smart-1b89edc6-64c7-4839-b206-e69b34a19f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257799284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1257799284
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3156361451
Short name T70
Test name
Test status
Simulation time 8293595489 ps
CPU time 13.55 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:19:44 PM PDT 24
Peak memory 217216 kb
Host smart-030ba8ce-1bf1-4b08-b848-728c6cd91ec0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156361451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3156361451
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2070113788
Short name T263
Test name
Test status
Simulation time 107740158 ps
CPU time 1.01 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:19:31 PM PDT 24
Peak memory 200060 kb
Host smart-446b70ba-65fb-4585-bee0-0593cdceb7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070113788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2070113788
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3418724685
Short name T8
Test name
Test status
Simulation time 119581489 ps
CPU time 1.17 seconds
Started Jul 04 05:19:21 PM PDT 24
Finished Jul 04 05:19:23 PM PDT 24
Peak memory 200184 kb
Host smart-f1114c3a-4a94-4de0-b8ee-7551b72bcc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418724685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3418724685
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2436610504
Short name T135
Test name
Test status
Simulation time 9879075874 ps
CPU time 32.74 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:20:03 PM PDT 24
Peak memory 208572 kb
Host smart-8301c3fe-9cf5-4469-8d6e-12da048b5a23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436610504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2436610504
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2211203607
Short name T254
Test name
Test status
Simulation time 156617814 ps
CPU time 1.05 seconds
Started Jul 04 05:19:39 PM PDT 24
Finished Jul 04 05:19:40 PM PDT 24
Peak memory 200084 kb
Host smart-07d3ca6e-4702-4e28-a882-4f98bd8f0c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211203607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2211203607
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3800240060
Short name T217
Test name
Test status
Simulation time 91161014 ps
CPU time 0.82 seconds
Started Jul 04 05:20:40 PM PDT 24
Finished Jul 04 05:20:41 PM PDT 24
Peak memory 199864 kb
Host smart-6167e91b-cdb7-45bf-9161-6df9c1b9f105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800240060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3800240060
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2389636032
Short name T424
Test name
Test status
Simulation time 2364262667 ps
CPU time 8.89 seconds
Started Jul 04 05:20:33 PM PDT 24
Finished Jul 04 05:20:42 PM PDT 24
Peak memory 217800 kb
Host smart-a4850b18-2bed-4121-8b8b-d7e6ebe8e5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389636032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2389636032
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.4162606672
Short name T214
Test name
Test status
Simulation time 244408402 ps
CPU time 1.05 seconds
Started Jul 04 05:20:34 PM PDT 24
Finished Jul 04 05:20:35 PM PDT 24
Peak memory 217408 kb
Host smart-cadc3907-e485-4232-9721-47a74261e61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162606672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.4162606672
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3533804654
Short name T14
Test name
Test status
Simulation time 115242431 ps
CPU time 0.8 seconds
Started Jul 04 05:20:32 PM PDT 24
Finished Jul 04 05:20:33 PM PDT 24
Peak memory 199896 kb
Host smart-1b32599c-f47b-46cf-9ba6-b417923019cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533804654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3533804654
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1933735862
Short name T162
Test name
Test status
Simulation time 1276797059 ps
CPU time 5.04 seconds
Started Jul 04 05:20:33 PM PDT 24
Finished Jul 04 05:20:38 PM PDT 24
Peak memory 200300 kb
Host smart-91db6e9a-6488-4adf-9156-d7614a8d6d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933735862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1933735862
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.731319078
Short name T426
Test name
Test status
Simulation time 157372994 ps
CPU time 1.1 seconds
Started Jul 04 05:20:34 PM PDT 24
Finished Jul 04 05:20:36 PM PDT 24
Peak memory 200084 kb
Host smart-6655cf8e-412d-4b40-a9a6-9fcdc6e66bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731319078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.731319078
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.4261294626
Short name T257
Test name
Test status
Simulation time 191743380 ps
CPU time 1.34 seconds
Started Jul 04 05:20:34 PM PDT 24
Finished Jul 04 05:20:35 PM PDT 24
Peak memory 200268 kb
Host smart-2156b075-20b9-4a8b-865b-c5b86ac62d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261294626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.4261294626
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2357558143
Short name T463
Test name
Test status
Simulation time 3427484577 ps
CPU time 14.05 seconds
Started Jul 04 05:20:34 PM PDT 24
Finished Jul 04 05:20:48 PM PDT 24
Peak memory 200344 kb
Host smart-7a84c279-4484-4799-93b1-4ecba41aec60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357558143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2357558143
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3844474057
Short name T379
Test name
Test status
Simulation time 159942528 ps
CPU time 1.91 seconds
Started Jul 04 05:20:34 PM PDT 24
Finished Jul 04 05:20:36 PM PDT 24
Peak memory 200076 kb
Host smart-0fd23fca-e575-4a82-b2ec-268dda6166cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844474057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3844474057
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.775683990
Short name T532
Test name
Test status
Simulation time 179497321 ps
CPU time 1.31 seconds
Started Jul 04 05:20:32 PM PDT 24
Finished Jul 04 05:20:33 PM PDT 24
Peak memory 200264 kb
Host smart-646e208c-f619-4b7d-8225-224572cc2976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775683990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.775683990
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3698021787
Short name T240
Test name
Test status
Simulation time 84410323 ps
CPU time 0.84 seconds
Started Jul 04 05:20:43 PM PDT 24
Finished Jul 04 05:20:44 PM PDT 24
Peak memory 199888 kb
Host smart-5e98aab2-946b-4296-8a99-3063f096c959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698021787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3698021787
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2422892510
Short name T295
Test name
Test status
Simulation time 1218367029 ps
CPU time 5.83 seconds
Started Jul 04 05:20:40 PM PDT 24
Finished Jul 04 05:20:46 PM PDT 24
Peak memory 221764 kb
Host smart-9867a988-032d-4e15-8c12-7d1f7a940da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422892510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2422892510
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2172495540
Short name T425
Test name
Test status
Simulation time 244792635 ps
CPU time 1.01 seconds
Started Jul 04 05:20:40 PM PDT 24
Finished Jul 04 05:20:41 PM PDT 24
Peak memory 217756 kb
Host smart-68306d31-ea95-47d3-834f-863bcf9bbe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172495540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2172495540
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3715862714
Short name T315
Test name
Test status
Simulation time 103360402 ps
CPU time 0.74 seconds
Started Jul 04 05:20:39 PM PDT 24
Finished Jul 04 05:20:40 PM PDT 24
Peak memory 199896 kb
Host smart-36d88034-912f-4c33-80bb-362f1ca5c62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715862714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3715862714
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3408799270
Short name T28
Test name
Test status
Simulation time 1367532502 ps
CPU time 5.69 seconds
Started Jul 04 05:20:39 PM PDT 24
Finished Jul 04 05:20:45 PM PDT 24
Peak memory 200348 kb
Host smart-7b879c5f-80b2-4758-8e1d-286f9b1339e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408799270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3408799270
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2512031876
Short name T150
Test name
Test status
Simulation time 175237439 ps
CPU time 1.15 seconds
Started Jul 04 05:20:40 PM PDT 24
Finished Jul 04 05:20:41 PM PDT 24
Peak memory 200096 kb
Host smart-321a2620-190b-421f-85a3-0185e812cfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512031876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2512031876
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2322630460
Short name T152
Test name
Test status
Simulation time 205400691 ps
CPU time 1.43 seconds
Started Jul 04 05:20:41 PM PDT 24
Finished Jul 04 05:20:42 PM PDT 24
Peak memory 200272 kb
Host smart-e3dfbcf1-2a1d-4ba5-8f99-8ce344fc0f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322630460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2322630460
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3442416512
Short name T168
Test name
Test status
Simulation time 2450972912 ps
CPU time 10.32 seconds
Started Jul 04 05:20:40 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 200468 kb
Host smart-f6d06b1b-66e3-4742-b187-a662673747b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442416512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3442416512
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1794134294
Short name T26
Test name
Test status
Simulation time 340492259 ps
CPU time 2.22 seconds
Started Jul 04 05:20:39 PM PDT 24
Finished Jul 04 05:20:41 PM PDT 24
Peak memory 208288 kb
Host smart-4d86bfa0-ff5f-44b1-bf89-ec1812e279b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794134294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1794134294
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3302985561
Short name T178
Test name
Test status
Simulation time 108908462 ps
CPU time 1.06 seconds
Started Jul 04 05:20:42 PM PDT 24
Finished Jul 04 05:20:44 PM PDT 24
Peak memory 199996 kb
Host smart-9d33849e-9105-4d56-98c5-7353c5ac88b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302985561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3302985561
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1712907667
Short name T439
Test name
Test status
Simulation time 57106630 ps
CPU time 0.76 seconds
Started Jul 04 05:20:38 PM PDT 24
Finished Jul 04 05:20:39 PM PDT 24
Peak memory 199884 kb
Host smart-512e203d-3f22-45eb-ba70-290f1a2d6ddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712907667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1712907667
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3343136029
Short name T526
Test name
Test status
Simulation time 244536699 ps
CPU time 1.14 seconds
Started Jul 04 05:20:41 PM PDT 24
Finished Jul 04 05:20:42 PM PDT 24
Peak memory 217488 kb
Host smart-b039b78b-de05-4719-9a54-a36df24b61d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343136029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3343136029
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.905572776
Short name T166
Test name
Test status
Simulation time 212942758 ps
CPU time 0.86 seconds
Started Jul 04 05:20:41 PM PDT 24
Finished Jul 04 05:20:42 PM PDT 24
Peak memory 199904 kb
Host smart-00b16aa8-c930-4af8-a703-493b4e51ffc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905572776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.905572776
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.971812301
Short name T440
Test name
Test status
Simulation time 976866814 ps
CPU time 4.6 seconds
Started Jul 04 05:20:39 PM PDT 24
Finished Jul 04 05:20:44 PM PDT 24
Peak memory 200388 kb
Host smart-6dcb5b1a-72fa-4754-b20d-0edb0f39a567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971812301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.971812301
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1069098554
Short name T289
Test name
Test status
Simulation time 101438665 ps
CPU time 0.99 seconds
Started Jul 04 05:20:40 PM PDT 24
Finished Jul 04 05:20:41 PM PDT 24
Peak memory 200004 kb
Host smart-bb74f7f4-5f8e-4d6c-93cd-d9388fcbc643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069098554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1069098554
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1360997067
Short name T371
Test name
Test status
Simulation time 116913930 ps
CPU time 1.25 seconds
Started Jul 04 05:20:40 PM PDT 24
Finished Jul 04 05:20:41 PM PDT 24
Peak memory 200200 kb
Host smart-e5a6caeb-a8f6-4a93-a501-e2b44e24c7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360997067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1360997067
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.621544388
Short name T241
Test name
Test status
Simulation time 218077118 ps
CPU time 1.57 seconds
Started Jul 04 05:20:39 PM PDT 24
Finished Jul 04 05:20:41 PM PDT 24
Peak memory 200328 kb
Host smart-1fe19fc0-6739-40d9-8c64-a853bf8d2bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621544388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.621544388
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3899323526
Short name T281
Test name
Test status
Simulation time 150190916 ps
CPU time 1.79 seconds
Started Jul 04 05:20:43 PM PDT 24
Finished Jul 04 05:20:45 PM PDT 24
Peak memory 200108 kb
Host smart-9b42ae3a-4a12-4ebc-87d9-009a27968ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899323526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3899323526
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1753035446
Short name T274
Test name
Test status
Simulation time 153612571 ps
CPU time 1.21 seconds
Started Jul 04 05:20:40 PM PDT 24
Finished Jul 04 05:20:41 PM PDT 24
Peak memory 200200 kb
Host smart-1f8006a1-e817-4dc6-a3f8-c2119043f916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753035446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1753035446
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3807645797
Short name T469
Test name
Test status
Simulation time 67536934 ps
CPU time 0.76 seconds
Started Jul 04 05:20:47 PM PDT 24
Finished Jul 04 05:20:48 PM PDT 24
Peak memory 199852 kb
Host smart-581d4cd8-c8ea-4a3b-ac4c-8c620887c5c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807645797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3807645797
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1595891346
Short name T498
Test name
Test status
Simulation time 2349754502 ps
CPU time 9.22 seconds
Started Jul 04 05:20:47 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 217860 kb
Host smart-4d8ae70c-afb0-473c-ad89-612d5dd0359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595891346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1595891346
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.219678988
Short name T524
Test name
Test status
Simulation time 244073500 ps
CPU time 1.15 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 217460 kb
Host smart-c1b677cb-93e6-4792-901c-f6151545773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219678988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.219678988
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2371919353
Short name T475
Test name
Test status
Simulation time 133105917 ps
CPU time 0.83 seconds
Started Jul 04 05:20:38 PM PDT 24
Finished Jul 04 05:20:40 PM PDT 24
Peak memory 199876 kb
Host smart-bdd1e8b3-cda7-44f5-974d-baa9eeeeda03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371919353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2371919353
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3500313104
Short name T385
Test name
Test status
Simulation time 1063656668 ps
CPU time 5.46 seconds
Started Jul 04 05:20:40 PM PDT 24
Finished Jul 04 05:20:45 PM PDT 24
Peak memory 200264 kb
Host smart-f72a2ac7-5007-4d24-b6c8-15188d6f0051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500313104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3500313104
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2271472267
Short name T142
Test name
Test status
Simulation time 149734016 ps
CPU time 1.16 seconds
Started Jul 04 05:20:42 PM PDT 24
Finished Jul 04 05:20:43 PM PDT 24
Peak memory 200068 kb
Host smart-b0ee2d61-bf8f-4eaa-998d-87576f207f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271472267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2271472267
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1837684673
Short name T318
Test name
Test status
Simulation time 123575031 ps
CPU time 1.18 seconds
Started Jul 04 05:20:38 PM PDT 24
Finished Jul 04 05:20:40 PM PDT 24
Peak memory 200312 kb
Host smart-be778838-ef61-4cb9-9923-b598cb53bb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837684673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1837684673
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1093987569
Short name T474
Test name
Test status
Simulation time 5863625506 ps
CPU time 19.19 seconds
Started Jul 04 05:20:49 PM PDT 24
Finished Jul 04 05:21:08 PM PDT 24
Peak memory 208608 kb
Host smart-72fb04e7-33db-4903-a463-64431686011f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093987569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1093987569
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2695941586
Short name T147
Test name
Test status
Simulation time 146914117 ps
CPU time 1.79 seconds
Started Jul 04 05:20:42 PM PDT 24
Finished Jul 04 05:20:44 PM PDT 24
Peak memory 200084 kb
Host smart-a7a719f3-651d-4898-99b7-caeed9292165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695941586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2695941586
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1492819570
Short name T356
Test name
Test status
Simulation time 75623931 ps
CPU time 0.81 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:49 PM PDT 24
Peak memory 199888 kb
Host smart-b6b0fadd-60e7-4ac9-a556-532c2c35dd3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492819570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1492819570
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.917283378
Short name T486
Test name
Test status
Simulation time 1222370427 ps
CPU time 5.85 seconds
Started Jul 04 05:20:50 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 217696 kb
Host smart-97298506-496f-4c7c-8c28-5046504fac24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917283378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.917283378
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4012564727
Short name T215
Test name
Test status
Simulation time 243899963 ps
CPU time 1.16 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 217468 kb
Host smart-7a1c6aa0-8280-47f7-8124-e58f66e7f9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012564727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4012564727
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1179230711
Short name T74
Test name
Test status
Simulation time 179329871 ps
CPU time 0.95 seconds
Started Jul 04 05:20:47 PM PDT 24
Finished Jul 04 05:20:49 PM PDT 24
Peak memory 199884 kb
Host smart-3256c57a-c5e8-465f-823d-2a41f71316c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179230711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1179230711
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3789264940
Short name T511
Test name
Test status
Simulation time 1234667059 ps
CPU time 5.28 seconds
Started Jul 04 05:20:49 PM PDT 24
Finished Jul 04 05:20:54 PM PDT 24
Peak memory 200344 kb
Host smart-f83a886f-7e89-42e3-85e1-38154e228e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789264940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3789264940
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2995993704
Short name T375
Test name
Test status
Simulation time 114163342 ps
CPU time 1.03 seconds
Started Jul 04 05:20:47 PM PDT 24
Finished Jul 04 05:20:49 PM PDT 24
Peak memory 200076 kb
Host smart-5a8a44f1-8165-4939-b737-07adf4dac9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995993704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2995993704
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1480746893
Short name T433
Test name
Test status
Simulation time 187365171 ps
CPU time 1.29 seconds
Started Jul 04 05:20:46 PM PDT 24
Finished Jul 04 05:20:48 PM PDT 24
Peak memory 200304 kb
Host smart-71b5abfe-825b-4aa9-81d0-20ad27f505a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480746893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1480746893
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1407999574
Short name T329
Test name
Test status
Simulation time 8864466875 ps
CPU time 33.64 seconds
Started Jul 04 05:20:47 PM PDT 24
Finished Jul 04 05:21:21 PM PDT 24
Peak memory 200324 kb
Host smart-5db3d7ff-fed8-44d4-84de-2b1eb5a874e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407999574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1407999574
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.604672711
Short name T11
Test name
Test status
Simulation time 130322671 ps
CPU time 1.61 seconds
Started Jul 04 05:20:47 PM PDT 24
Finished Jul 04 05:20:49 PM PDT 24
Peak memory 200100 kb
Host smart-3bbeaec7-580a-4016-8a0f-68c2b92d7277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604672711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.604672711
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3367689404
Short name T343
Test name
Test status
Simulation time 146620722 ps
CPU time 1.19 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 199996 kb
Host smart-cc24ccb0-25ec-4162-aaab-63910a972037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367689404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3367689404
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.99133061
Short name T377
Test name
Test status
Simulation time 70749495 ps
CPU time 0.74 seconds
Started Jul 04 05:20:47 PM PDT 24
Finished Jul 04 05:20:49 PM PDT 24
Peak memory 199876 kb
Host smart-c6e7efc3-cfd9-41a3-9421-b60d29875aff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99133061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.99133061
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.611599578
Short name T50
Test name
Test status
Simulation time 2366137235 ps
CPU time 8.99 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:58 PM PDT 24
Peak memory 221720 kb
Host smart-a2ca80d2-1dcb-4422-8bd8-1e2144fabebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611599578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.611599578
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4274083125
Short name T75
Test name
Test status
Simulation time 243826101 ps
CPU time 1.09 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 217392 kb
Host smart-2668814b-ccbd-4068-ae9e-45c0d36b8d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274083125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4274083125
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.4091065336
Short name T396
Test name
Test status
Simulation time 79981935 ps
CPU time 0.8 seconds
Started Jul 04 05:20:47 PM PDT 24
Finished Jul 04 05:20:48 PM PDT 24
Peak memory 199864 kb
Host smart-8c733447-10fe-4398-9b7e-7bde0822669b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091065336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.4091065336
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1026987474
Short name T478
Test name
Test status
Simulation time 981617368 ps
CPU time 4.7 seconds
Started Jul 04 05:20:46 PM PDT 24
Finished Jul 04 05:20:51 PM PDT 24
Peak memory 200408 kb
Host smart-724ab06e-3a0e-4792-861d-108f5ff1898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026987474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1026987474
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.884666197
Short name T304
Test name
Test status
Simulation time 103034518 ps
CPU time 1 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 200084 kb
Host smart-f7f4195d-9b78-4844-b31f-53fa66311130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884666197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.884666197
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2181534276
Short name T512
Test name
Test status
Simulation time 237647739 ps
CPU time 1.45 seconds
Started Jul 04 05:20:49 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 200284 kb
Host smart-14a8c532-9af1-47d1-a3f7-c00c832878e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181534276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2181534276
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3946065255
Short name T542
Test name
Test status
Simulation time 4005113374 ps
CPU time 18.48 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:21:07 PM PDT 24
Peak memory 208576 kb
Host smart-82f6f5af-d1c1-4ec2-af91-10e4ff29e481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946065255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3946065255
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.860559996
Short name T340
Test name
Test status
Simulation time 259998507 ps
CPU time 1.82 seconds
Started Jul 04 05:20:51 PM PDT 24
Finished Jul 04 05:20:53 PM PDT 24
Peak memory 200104 kb
Host smart-b7ff0870-7ce8-4b9d-9e7a-70d019ad7ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860559996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.860559996
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.186649518
Short name T255
Test name
Test status
Simulation time 89537636 ps
CPU time 0.84 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:49 PM PDT 24
Peak memory 200064 kb
Host smart-871f419b-5c72-491b-9f32-8c8f4b3a27ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186649518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.186649518
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.855738081
Short name T460
Test name
Test status
Simulation time 54816363 ps
CPU time 0.71 seconds
Started Jul 04 05:20:47 PM PDT 24
Finished Jul 04 05:20:49 PM PDT 24
Peak memory 199868 kb
Host smart-778b39e1-683a-454d-b796-29ba3c12b812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855738081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.855738081
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1981038994
Short name T448
Test name
Test status
Simulation time 2363051615 ps
CPU time 8 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:57 PM PDT 24
Peak memory 217888 kb
Host smart-f83eebe5-83e3-48ac-b317-c1903b955a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981038994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1981038994
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1213151839
Short name T268
Test name
Test status
Simulation time 244827299 ps
CPU time 1.13 seconds
Started Jul 04 05:20:46 PM PDT 24
Finished Jul 04 05:20:47 PM PDT 24
Peak memory 217464 kb
Host smart-0edc9503-9e17-4a27-bdcf-3b258ee17a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213151839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1213151839
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3708571120
Short name T447
Test name
Test status
Simulation time 91901592 ps
CPU time 0.78 seconds
Started Jul 04 05:20:47 PM PDT 24
Finished Jul 04 05:20:48 PM PDT 24
Peak memory 199900 kb
Host smart-a67dd9ed-c8ac-48f9-a160-23fb3ff5544b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708571120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3708571120
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1438619705
Short name T159
Test name
Test status
Simulation time 1123591181 ps
CPU time 4.95 seconds
Started Jul 04 05:20:46 PM PDT 24
Finished Jul 04 05:20:51 PM PDT 24
Peak memory 200392 kb
Host smart-01b317ce-e22f-40fd-b82b-42dbf2c35167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438619705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1438619705
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.390138167
Short name T461
Test name
Test status
Simulation time 146332887 ps
CPU time 1.08 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 200096 kb
Host smart-5f0450a1-8a3a-4b73-acdf-1336549a61e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390138167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.390138167
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1086063278
Short name T2
Test name
Test status
Simulation time 190246183 ps
CPU time 1.35 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 200288 kb
Host smart-0adf3682-74af-4fad-9217-267a82e2979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086063278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1086063278
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2238582377
Short name T91
Test name
Test status
Simulation time 4061895450 ps
CPU time 14.73 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:21:03 PM PDT 24
Peak memory 210264 kb
Host smart-baea93b0-a811-4392-b8cc-4dd46d9483fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238582377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2238582377
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2273889034
Short name T430
Test name
Test status
Simulation time 374746070 ps
CPU time 2.28 seconds
Started Jul 04 05:20:51 PM PDT 24
Finished Jul 04 05:20:53 PM PDT 24
Peak memory 200108 kb
Host smart-c109ee52-7f7e-46d3-8a98-b7b85337a217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273889034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2273889034
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3952094772
Short name T367
Test name
Test status
Simulation time 83942598 ps
CPU time 0.84 seconds
Started Jul 04 05:20:46 PM PDT 24
Finished Jul 04 05:20:47 PM PDT 24
Peak memory 200080 kb
Host smart-7dcee7fd-1c45-4b1a-bcd3-590d9cb04abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952094772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3952094772
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2737002311
Short name T476
Test name
Test status
Simulation time 71581668 ps
CPU time 0.74 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 199896 kb
Host smart-0b7b51b9-6c40-42fd-bf98-953bcf0fffc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737002311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2737002311
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.689268264
Short name T390
Test name
Test status
Simulation time 1221462408 ps
CPU time 5.63 seconds
Started Jul 04 05:20:56 PM PDT 24
Finished Jul 04 05:21:01 PM PDT 24
Peak memory 221644 kb
Host smart-1d119b50-8912-4d0e-9bba-100eaba7ac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689268264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.689268264
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.451574540
Short name T437
Test name
Test status
Simulation time 245661892 ps
CPU time 1.12 seconds
Started Jul 04 05:20:58 PM PDT 24
Finished Jul 04 05:20:59 PM PDT 24
Peak memory 217488 kb
Host smart-4f0aa8c8-1129-44e7-9ae1-c7f3f32140b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451574540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.451574540
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1310514786
Short name T210
Test name
Test status
Simulation time 97318820 ps
CPU time 0.77 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 199904 kb
Host smart-862cc848-d576-4dc5-90cd-b000c743920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310514786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1310514786
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.275144246
Short name T523
Test name
Test status
Simulation time 1555177769 ps
CPU time 6.69 seconds
Started Jul 04 05:20:47 PM PDT 24
Finished Jul 04 05:20:55 PM PDT 24
Peak memory 200296 kb
Host smart-afc55f59-d6f9-43fd-9d2d-af2b2042272b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275144246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.275144246
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.699757252
Short name T161
Test name
Test status
Simulation time 164747932 ps
CPU time 1.09 seconds
Started Jul 04 05:20:54 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 200076 kb
Host smart-611b0685-c56a-4a50-aeb8-396358b8522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699757252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.699757252
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3982363944
Short name T216
Test name
Test status
Simulation time 119563882 ps
CPU time 1.14 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 200300 kb
Host smart-1c3c9dfa-c04b-4a0d-a56a-bc6f6c805701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982363944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3982363944
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.4069789273
Short name T172
Test name
Test status
Simulation time 226817280 ps
CPU time 1.57 seconds
Started Jul 04 05:20:54 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 208448 kb
Host smart-f6572ab5-2b19-424c-8c3f-e8581de14f7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069789273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.4069789273
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.4044649902
Short name T410
Test name
Test status
Simulation time 366609983 ps
CPU time 2.23 seconds
Started Jul 04 05:20:48 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 200092 kb
Host smart-b448bdc3-5b40-463b-ae32-ed954e72eb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044649902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4044649902
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.4156814776
Short name T509
Test name
Test status
Simulation time 141406037 ps
CPU time 1.16 seconds
Started Jul 04 05:20:50 PM PDT 24
Finished Jul 04 05:20:51 PM PDT 24
Peak memory 200072 kb
Host smart-f552d521-e3a8-4302-af05-7a883155d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156814776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.4156814776
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3074563912
Short name T378
Test name
Test status
Simulation time 62829885 ps
CPU time 0.75 seconds
Started Jul 04 05:20:54 PM PDT 24
Finished Jul 04 05:20:55 PM PDT 24
Peak memory 199860 kb
Host smart-d3fe45c2-44fe-4cf5-bfb7-1895680b7e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074563912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3074563912
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1855474638
Short name T529
Test name
Test status
Simulation time 2363627675 ps
CPU time 7.94 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:21:03 PM PDT 24
Peak memory 217856 kb
Host smart-17e83773-541d-4e75-85d8-60dfba0ea1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855474638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1855474638
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1815540526
Short name T7
Test name
Test status
Simulation time 244620240 ps
CPU time 1.08 seconds
Started Jul 04 05:20:53 PM PDT 24
Finished Jul 04 05:20:55 PM PDT 24
Peak memory 217476 kb
Host smart-dec4c1a3-cd91-4e76-9170-9d2e29d4d676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815540526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1815540526
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3314696489
Short name T182
Test name
Test status
Simulation time 197024895 ps
CPU time 0.9 seconds
Started Jul 04 05:20:54 PM PDT 24
Finished Jul 04 05:20:55 PM PDT 24
Peak memory 199904 kb
Host smart-aa69740c-a56d-48b5-a7d7-19665971bb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314696489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3314696489
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2754979728
Short name T94
Test name
Test status
Simulation time 1869919573 ps
CPU time 6.93 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:21:02 PM PDT 24
Peak memory 200408 kb
Host smart-b49834a5-03f8-4dc5-8747-b8177f4d7197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754979728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2754979728
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1013806712
Short name T261
Test name
Test status
Simulation time 151530683 ps
CPU time 1.08 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 200084 kb
Host smart-5570e4ba-fce5-434e-aa6b-0844417370ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013806712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1013806712
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3862474158
Short name T400
Test name
Test status
Simulation time 207943948 ps
CPU time 1.45 seconds
Started Jul 04 05:20:59 PM PDT 24
Finished Jul 04 05:21:00 PM PDT 24
Peak memory 200304 kb
Host smart-d295d070-ba17-48eb-bbcb-60fadfe6649e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862474158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3862474158
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.4263316625
Short name T95
Test name
Test status
Simulation time 1962471588 ps
CPU time 9.95 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:21:05 PM PDT 24
Peak memory 208556 kb
Host smart-b7ce1160-2896-47fa-89b7-4ba1a629c2ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263316625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.4263316625
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2672967396
Short name T506
Test name
Test status
Simulation time 421790283 ps
CPU time 2.21 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:20:58 PM PDT 24
Peak memory 208316 kb
Host smart-257c4113-6c0d-4f60-9a5a-d394b43512d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672967396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2672967396
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1583965402
Short name T282
Test name
Test status
Simulation time 287821799 ps
CPU time 1.55 seconds
Started Jul 04 05:20:57 PM PDT 24
Finished Jul 04 05:20:59 PM PDT 24
Peak memory 200280 kb
Host smart-876b4d2d-5093-4d82-8d3f-6b69c9da93ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583965402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1583965402
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1737019303
Short name T364
Test name
Test status
Simulation time 64741511 ps
CPU time 0.82 seconds
Started Jul 04 05:20:53 PM PDT 24
Finished Jul 04 05:20:55 PM PDT 24
Peak memory 199888 kb
Host smart-eb010f8b-2d23-4031-9e82-0f4d5a158115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737019303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1737019303
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1033255007
Short name T516
Test name
Test status
Simulation time 244417583 ps
CPU time 1.04 seconds
Started Jul 04 05:20:54 PM PDT 24
Finished Jul 04 05:20:55 PM PDT 24
Peak memory 217496 kb
Host smart-916e470c-2310-4c4d-b457-0ae054409113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033255007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1033255007
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3391965485
Short name T432
Test name
Test status
Simulation time 98283032 ps
CPU time 0.75 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 199904 kb
Host smart-53437e4e-460f-45ae-8a4a-9f690f70201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391965485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3391965485
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1270757687
Short name T258
Test name
Test status
Simulation time 1640367690 ps
CPU time 6.1 seconds
Started Jul 04 05:20:58 PM PDT 24
Finished Jul 04 05:21:04 PM PDT 24
Peak memory 200368 kb
Host smart-98d84f6c-5c58-42c3-a033-d7fa3d30e238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270757687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1270757687
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1928619264
Short name T130
Test name
Test status
Simulation time 155204004 ps
CPU time 1.11 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 200064 kb
Host smart-afc6ee61-7a06-4001-9db4-9bff961bad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928619264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1928619264
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2419187057
Short name T398
Test name
Test status
Simulation time 197029478 ps
CPU time 1.4 seconds
Started Jul 04 05:20:54 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 200300 kb
Host smart-eb805b0a-2cfd-4c1d-bfa0-e1334ed32a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419187057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2419187057
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2595991597
Short name T225
Test name
Test status
Simulation time 16895998386 ps
CPU time 57.67 seconds
Started Jul 04 05:20:54 PM PDT 24
Finished Jul 04 05:21:52 PM PDT 24
Peak memory 210332 kb
Host smart-2218693c-073b-4b34-a829-6d2ed9a8a200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595991597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2595991597
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1111384751
Short name T276
Test name
Test status
Simulation time 146748384 ps
CPU time 1.85 seconds
Started Jul 04 05:20:54 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 200068 kb
Host smart-917fef87-b0c5-4bc4-b6ab-cd9ff99ae474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111384751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1111384751
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1649953703
Short name T188
Test name
Test status
Simulation time 74945720 ps
CPU time 0.78 seconds
Started Jul 04 05:20:56 PM PDT 24
Finished Jul 04 05:20:57 PM PDT 24
Peak memory 200056 kb
Host smart-8413f4e5-deff-4df9-8781-a4aa120f2533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649953703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1649953703
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2534625269
Short name T513
Test name
Test status
Simulation time 81623814 ps
CPU time 0.8 seconds
Started Jul 04 05:19:39 PM PDT 24
Finished Jul 04 05:19:40 PM PDT 24
Peak memory 199892 kb
Host smart-539e4c44-fc14-4eed-a510-b1779a535fe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534625269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2534625269
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.248532559
Short name T446
Test name
Test status
Simulation time 2361925268 ps
CPU time 7.81 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:19:38 PM PDT 24
Peak memory 217756 kb
Host smart-098353ab-9507-472f-a3e9-c46dd847f56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248532559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.248532559
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.745459633
Short name T293
Test name
Test status
Simulation time 244905952 ps
CPU time 1.06 seconds
Started Jul 04 05:19:31 PM PDT 24
Finished Jul 04 05:19:32 PM PDT 24
Peak memory 217464 kb
Host smart-3b7cf5ec-60cd-4a22-a15e-1707f86c20d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745459633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.745459633
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1834772183
Short name T514
Test name
Test status
Simulation time 113147272 ps
CPU time 0.79 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:19:31 PM PDT 24
Peak memory 199864 kb
Host smart-d828d815-bf06-4b97-bd0e-35128ce3f657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834772183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1834772183
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1909482219
Short name T6
Test name
Test status
Simulation time 1844802982 ps
CPU time 6.82 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:19:37 PM PDT 24
Peak memory 200340 kb
Host smart-59ae601b-e925-4caa-9757-f802b7c9a270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909482219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1909482219
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.817627990
Short name T69
Test name
Test status
Simulation time 16755284250 ps
CPU time 24.31 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:19:54 PM PDT 24
Peak memory 218240 kb
Host smart-1b1db104-4937-4fa2-87ee-cd4cbb191dee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817627990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.817627990
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2551266848
Short name T386
Test name
Test status
Simulation time 187864691 ps
CPU time 1.3 seconds
Started Jul 04 05:19:29 PM PDT 24
Finished Jul 04 05:19:30 PM PDT 24
Peak memory 200016 kb
Host smart-c2aeb672-e65f-4d07-95c1-3de70e5e7865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551266848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2551266848
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2744915275
Short name T196
Test name
Test status
Simulation time 230786006 ps
CPU time 1.43 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:19:32 PM PDT 24
Peak memory 200272 kb
Host smart-271775ef-85b8-49dd-a9fd-e5ff8f9233bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744915275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2744915275
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2274217273
Short name T392
Test name
Test status
Simulation time 2683389343 ps
CPU time 11.22 seconds
Started Jul 04 05:19:30 PM PDT 24
Finished Jul 04 05:19:42 PM PDT 24
Peak memory 208584 kb
Host smart-7171fb79-a0f9-462f-9fb0-8401c6c6f305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274217273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2274217273
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3310160765
Short name T480
Test name
Test status
Simulation time 148690323 ps
CPU time 1.75 seconds
Started Jul 04 05:19:29 PM PDT 24
Finished Jul 04 05:19:31 PM PDT 24
Peak memory 200092 kb
Host smart-c144f17b-5c14-4179-ab09-24e0b772e805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310160765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3310160765
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3291745384
Short name T332
Test name
Test status
Simulation time 168705299 ps
CPU time 1.11 seconds
Started Jul 04 05:19:29 PM PDT 24
Finished Jul 04 05:19:30 PM PDT 24
Peak memory 200080 kb
Host smart-f47d54a8-14fc-4923-9bc9-8d68a08b87a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291745384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3291745384
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.4277451221
Short name T137
Test name
Test status
Simulation time 74706999 ps
CPU time 0.79 seconds
Started Jul 04 05:21:01 PM PDT 24
Finished Jul 04 05:21:02 PM PDT 24
Peak memory 199864 kb
Host smart-50a26e87-5e87-4b30-b73e-1fd741210037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277451221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.4277451221
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.4118423848
Short name T538
Test name
Test status
Simulation time 1884504752 ps
CPU time 7.18 seconds
Started Jul 04 05:20:56 PM PDT 24
Finished Jul 04 05:21:03 PM PDT 24
Peak memory 217516 kb
Host smart-cdb8270a-b7d8-4d2c-9477-6327a30a97d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118423848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.4118423848
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.371182514
Short name T382
Test name
Test status
Simulation time 245492317 ps
CPU time 1 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 217432 kb
Host smart-308f9bdc-4ef9-4472-89cc-82b503fedb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371182514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.371182514
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.4220523929
Short name T317
Test name
Test status
Simulation time 147955995 ps
CPU time 0.81 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 199896 kb
Host smart-b1ce7c68-30ad-493e-9ded-c4e6e1fc08da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220523929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.4220523929
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1616233630
Short name T123
Test name
Test status
Simulation time 1658588396 ps
CPU time 6.29 seconds
Started Jul 04 05:20:54 PM PDT 24
Finished Jul 04 05:21:00 PM PDT 24
Peak memory 200324 kb
Host smart-8fc9e6e2-f5a3-46c3-82af-181bb70cf30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616233630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1616233630
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.644957999
Short name T12
Test name
Test status
Simulation time 111530783 ps
CPU time 0.99 seconds
Started Jul 04 05:20:54 PM PDT 24
Finished Jul 04 05:20:56 PM PDT 24
Peak memory 200060 kb
Host smart-70b955a1-5fb1-4289-9440-8f2ed8453bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644957999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.644957999
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.120664865
Short name T411
Test name
Test status
Simulation time 127693183 ps
CPU time 1.26 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:20:57 PM PDT 24
Peak memory 200292 kb
Host smart-a86de78b-2c4d-43a4-8484-b119f24c51b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120664865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.120664865
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2279320480
Short name T366
Test name
Test status
Simulation time 10361238632 ps
CPU time 32.29 seconds
Started Jul 04 05:20:55 PM PDT 24
Finished Jul 04 05:21:27 PM PDT 24
Peak memory 200416 kb
Host smart-b6959dd6-5454-4a7d-bd87-4f010e6b2cc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279320480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2279320480
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3521400466
Short name T82
Test name
Test status
Simulation time 126156653 ps
CPU time 1.5 seconds
Started Jul 04 05:20:57 PM PDT 24
Finished Jul 04 05:20:59 PM PDT 24
Peak memory 200096 kb
Host smart-eff0de10-d488-4170-b13e-180138c8e56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521400466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3521400466
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.803227637
Short name T507
Test name
Test status
Simulation time 74951025 ps
CPU time 0.76 seconds
Started Jul 04 05:20:53 PM PDT 24
Finished Jul 04 05:20:54 PM PDT 24
Peak memory 200096 kb
Host smart-11dec34d-0f7a-47e5-9ff9-af457fb7ed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803227637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.803227637
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3563065695
Short name T153
Test name
Test status
Simulation time 69404684 ps
CPU time 0.75 seconds
Started Jul 04 05:21:02 PM PDT 24
Finished Jul 04 05:21:03 PM PDT 24
Peak memory 199888 kb
Host smart-9399635e-c22c-4626-9b7d-f0b9d6e609e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563065695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3563065695
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.4053388131
Short name T49
Test name
Test status
Simulation time 2158420662 ps
CPU time 7.63 seconds
Started Jul 04 05:20:59 PM PDT 24
Finished Jul 04 05:21:07 PM PDT 24
Peak memory 216884 kb
Host smart-d36c8d89-5a56-435d-92fd-5d13a5686c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053388131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.4053388131
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3281874696
Short name T170
Test name
Test status
Simulation time 244245997 ps
CPU time 1.06 seconds
Started Jul 04 05:21:04 PM PDT 24
Finished Jul 04 05:21:05 PM PDT 24
Peak memory 217484 kb
Host smart-78eafa21-2793-4192-a394-245fd3ed6691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281874696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3281874696
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1971542372
Short name T487
Test name
Test status
Simulation time 217155349 ps
CPU time 0.9 seconds
Started Jul 04 05:20:59 PM PDT 24
Finished Jul 04 05:21:00 PM PDT 24
Peak memory 199864 kb
Host smart-c532a6c6-6b3a-43fa-837c-857c191970f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971542372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1971542372
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3346568787
Short name T148
Test name
Test status
Simulation time 727824917 ps
CPU time 3.89 seconds
Started Jul 04 05:21:01 PM PDT 24
Finished Jul 04 05:21:06 PM PDT 24
Peak memory 200360 kb
Host smart-a69cf9b1-3073-4e30-a07d-d640d17b67f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346568787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3346568787
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1098066756
Short name T489
Test name
Test status
Simulation time 110572967 ps
CPU time 1.06 seconds
Started Jul 04 05:21:01 PM PDT 24
Finished Jul 04 05:21:03 PM PDT 24
Peak memory 200084 kb
Host smart-a944e2c8-cbad-40fd-9e0d-dfcbb5fb7591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098066756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1098066756
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.4085810402
Short name T417
Test name
Test status
Simulation time 114319941 ps
CPU time 1.28 seconds
Started Jul 04 05:21:01 PM PDT 24
Finished Jul 04 05:21:03 PM PDT 24
Peak memory 200340 kb
Host smart-73aafbc7-5eee-410d-9f5a-b1985a949b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085810402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.4085810402
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.437106040
Short name T355
Test name
Test status
Simulation time 10134038170 ps
CPU time 36.16 seconds
Started Jul 04 05:21:02 PM PDT 24
Finished Jul 04 05:21:38 PM PDT 24
Peak memory 208592 kb
Host smart-6b66c86b-83f3-46fb-a386-297e4157af77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437106040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.437106040
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2585635935
Short name T160
Test name
Test status
Simulation time 123157212 ps
CPU time 1.5 seconds
Started Jul 04 05:21:03 PM PDT 24
Finished Jul 04 05:21:05 PM PDT 24
Peak memory 200136 kb
Host smart-84a475d5-9ea5-4acf-b577-c5aef0482f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585635935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2585635935
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.324733902
Short name T127
Test name
Test status
Simulation time 270074907 ps
CPU time 1.57 seconds
Started Jul 04 05:21:02 PM PDT 24
Finished Jul 04 05:21:04 PM PDT 24
Peak memory 200084 kb
Host smart-01fad9dd-dc1c-46b1-972f-b8918ebc1456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324733902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.324733902
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3244297510
Short name T275
Test name
Test status
Simulation time 82332481 ps
CPU time 0.88 seconds
Started Jul 04 05:21:01 PM PDT 24
Finished Jul 04 05:21:03 PM PDT 24
Peak memory 199888 kb
Host smart-7715751b-ef55-47d4-8afe-d3667f3e3c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244297510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3244297510
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1684884383
Short name T483
Test name
Test status
Simulation time 2180347602 ps
CPU time 7.44 seconds
Started Jul 04 05:21:01 PM PDT 24
Finished Jul 04 05:21:09 PM PDT 24
Peak memory 217836 kb
Host smart-6106d429-6443-4433-994d-a510a311343e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684884383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1684884383
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.21993428
Short name T521
Test name
Test status
Simulation time 244400648 ps
CPU time 1.06 seconds
Started Jul 04 05:21:00 PM PDT 24
Finished Jul 04 05:21:02 PM PDT 24
Peak memory 217380 kb
Host smart-fd16e524-8fd6-48bd-8931-1670acc2be54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21993428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.21993428
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.844009052
Short name T25
Test name
Test status
Simulation time 183451111 ps
CPU time 0.85 seconds
Started Jul 04 05:21:06 PM PDT 24
Finished Jul 04 05:21:08 PM PDT 24
Peak memory 199904 kb
Host smart-a8cc2add-84c8-4234-92a7-fe80c024b8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844009052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.844009052
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.233428313
Short name T206
Test name
Test status
Simulation time 1567201764 ps
CPU time 5.8 seconds
Started Jul 04 05:21:06 PM PDT 24
Finished Jul 04 05:21:12 PM PDT 24
Peak memory 200376 kb
Host smart-8754f6bb-2a20-40b4-8307-3c62457b3b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233428313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.233428313
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2070856250
Short name T202
Test name
Test status
Simulation time 102856469 ps
CPU time 0.99 seconds
Started Jul 04 05:21:06 PM PDT 24
Finished Jul 04 05:21:08 PM PDT 24
Peak memory 200096 kb
Host smart-a5c5984d-8860-43b3-a5b3-20cb3c513809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070856250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2070856250
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2809130588
Short name T388
Test name
Test status
Simulation time 253441077 ps
CPU time 1.47 seconds
Started Jul 04 05:21:00 PM PDT 24
Finished Jul 04 05:21:01 PM PDT 24
Peak memory 200324 kb
Host smart-70aa3b4b-c4ea-443a-8ee9-69a0dda4f80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809130588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2809130588
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1121060034
Short name T346
Test name
Test status
Simulation time 541533187 ps
CPU time 2.85 seconds
Started Jul 04 05:21:00 PM PDT 24
Finished Jul 04 05:21:03 PM PDT 24
Peak memory 200320 kb
Host smart-daff1be8-8988-4a6b-af04-073a57dc9773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121060034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1121060034
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3660246736
Short name T427
Test name
Test status
Simulation time 117605330 ps
CPU time 1.65 seconds
Started Jul 04 05:21:05 PM PDT 24
Finished Jul 04 05:21:06 PM PDT 24
Peak memory 200008 kb
Host smart-387ec314-2f5a-449b-9ac1-580a5f6edf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660246736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3660246736
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.4159299844
Short name T357
Test name
Test status
Simulation time 207398939 ps
CPU time 1.31 seconds
Started Jul 04 05:21:02 PM PDT 24
Finished Jul 04 05:21:04 PM PDT 24
Peak memory 200060 kb
Host smart-2834e462-bc67-48c7-a89b-9de25bc070dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159299844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.4159299844
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2161818063
Short name T165
Test name
Test status
Simulation time 75272669 ps
CPU time 0.86 seconds
Started Jul 04 05:21:01 PM PDT 24
Finished Jul 04 05:21:02 PM PDT 24
Peak memory 199824 kb
Host smart-10d255c8-1df2-4653-a116-3e3f39902a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161818063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2161818063
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2225494413
Short name T37
Test name
Test status
Simulation time 1883836530 ps
CPU time 8 seconds
Started Jul 04 05:21:05 PM PDT 24
Finished Jul 04 05:21:13 PM PDT 24
Peak memory 216684 kb
Host smart-063f72dc-d5d0-4df1-bb74-bd6e289883b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225494413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2225494413
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1577759173
Short name T78
Test name
Test status
Simulation time 245194670 ps
CPU time 1.05 seconds
Started Jul 04 05:21:02 PM PDT 24
Finished Jul 04 05:21:03 PM PDT 24
Peak memory 217468 kb
Host smart-4c4efe45-4487-429c-88bb-b9a025105947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577759173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1577759173
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1854369038
Short name T393
Test name
Test status
Simulation time 192147901 ps
CPU time 0.87 seconds
Started Jul 04 05:21:03 PM PDT 24
Finished Jul 04 05:21:04 PM PDT 24
Peak memory 199904 kb
Host smart-e9a4bc47-f754-497a-972a-13f58647d0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854369038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1854369038
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1858044841
Short name T208
Test name
Test status
Simulation time 814031785 ps
CPU time 4.66 seconds
Started Jul 04 05:21:01 PM PDT 24
Finished Jul 04 05:21:07 PM PDT 24
Peak memory 200344 kb
Host smart-55f4283f-7bbc-4eea-b58c-5b4fda53a215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858044841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1858044841
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1858957240
Short name T228
Test name
Test status
Simulation time 102869557 ps
CPU time 0.99 seconds
Started Jul 04 05:21:01 PM PDT 24
Finished Jul 04 05:21:02 PM PDT 24
Peak memory 200060 kb
Host smart-c3ee986d-e3b0-4b09-8ee1-80f065c099c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858957240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1858957240
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3649757334
Short name T533
Test name
Test status
Simulation time 208537405 ps
CPU time 1.47 seconds
Started Jul 04 05:21:01 PM PDT 24
Finished Jul 04 05:21:03 PM PDT 24
Peak memory 200300 kb
Host smart-0ec2d431-7ae5-47e5-a65a-68462e1079ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649757334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3649757334
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.802441336
Short name T387
Test name
Test status
Simulation time 5268815394 ps
CPU time 25.21 seconds
Started Jul 04 05:21:05 PM PDT 24
Finished Jul 04 05:21:31 PM PDT 24
Peak memory 200312 kb
Host smart-24b67377-c13a-43bc-ad14-e9a020d22c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802441336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.802441336
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2313153454
Short name T267
Test name
Test status
Simulation time 411362690 ps
CPU time 2.56 seconds
Started Jul 04 05:21:05 PM PDT 24
Finished Jul 04 05:21:08 PM PDT 24
Peak memory 208252 kb
Host smart-f176cc33-7ab6-4e83-8588-bc1c90932e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313153454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2313153454
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3251947263
Short name T238
Test name
Test status
Simulation time 69359463 ps
CPU time 0.74 seconds
Started Jul 04 05:21:07 PM PDT 24
Finished Jul 04 05:21:08 PM PDT 24
Peak memory 200088 kb
Host smart-040b8df5-f308-4699-abb8-fb079e8993e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251947263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3251947263
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3424380478
Short name T41
Test name
Test status
Simulation time 74533175 ps
CPU time 0.81 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:13 PM PDT 24
Peak memory 199912 kb
Host smart-7f00e53a-05fc-44d1-87f7-39c08a53d174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424380478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3424380478
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2544434165
Short name T220
Test name
Test status
Simulation time 1876129102 ps
CPU time 7.11 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:19 PM PDT 24
Peak memory 220796 kb
Host smart-dba8e594-d6dc-43ae-9afe-048a0cbeb34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544434165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2544434165
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1521895493
Short name T246
Test name
Test status
Simulation time 249953950 ps
CPU time 1.07 seconds
Started Jul 04 05:21:11 PM PDT 24
Finished Jul 04 05:21:12 PM PDT 24
Peak memory 217360 kb
Host smart-44452d3a-447d-424c-bb97-0876f000de92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521895493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1521895493
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.77506207
Short name T403
Test name
Test status
Simulation time 164865238 ps
CPU time 0.91 seconds
Started Jul 04 05:21:01 PM PDT 24
Finished Jul 04 05:21:02 PM PDT 24
Peak memory 199856 kb
Host smart-e7646e95-0738-42a9-ac76-834c73b4439f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77506207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.77506207
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2008811928
Short name T384
Test name
Test status
Simulation time 704503189 ps
CPU time 3.8 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:17 PM PDT 24
Peak memory 200376 kb
Host smart-2f8d214d-260b-4e94-842d-23e570fe9114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008811928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2008811928
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2765150644
Short name T143
Test name
Test status
Simulation time 142441997 ps
CPU time 1.06 seconds
Started Jul 04 05:21:13 PM PDT 24
Finished Jul 04 05:21:15 PM PDT 24
Peak memory 200068 kb
Host smart-3edac484-743e-4905-ac49-5e8926724ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765150644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2765150644
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2047128347
Short name T13
Test name
Test status
Simulation time 199540772 ps
CPU time 1.41 seconds
Started Jul 04 05:21:07 PM PDT 24
Finished Jul 04 05:21:09 PM PDT 24
Peak memory 200316 kb
Host smart-30ebd562-ebcb-4dc1-8ea2-10f7a25bad03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047128347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2047128347
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.510999183
Short name T347
Test name
Test status
Simulation time 1689756052 ps
CPU time 7.66 seconds
Started Jul 04 05:21:11 PM PDT 24
Finished Jul 04 05:21:19 PM PDT 24
Peak memory 200316 kb
Host smart-40dd679a-36ef-4cfe-a16a-cf98adde089a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510999183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.510999183
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2849771601
Short name T431
Test name
Test status
Simulation time 159028158 ps
CPU time 1.81 seconds
Started Jul 04 05:21:13 PM PDT 24
Finished Jul 04 05:21:15 PM PDT 24
Peak memory 200104 kb
Host smart-2cb50f0a-eddb-4c7f-bc75-852f3cd6d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849771601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2849771601
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.722643207
Short name T141
Test name
Test status
Simulation time 103534667 ps
CPU time 0.84 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:14 PM PDT 24
Peak memory 200076 kb
Host smart-3d33c520-f3b5-4858-a8f4-428f5d4d2afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722643207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.722643207
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2015648844
Short name T312
Test name
Test status
Simulation time 85285614 ps
CPU time 0.84 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:13 PM PDT 24
Peak memory 199880 kb
Host smart-cf5ed3f4-14cd-4d10-82ce-3d6928114bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015648844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2015648844
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2291005977
Short name T53
Test name
Test status
Simulation time 2342601015 ps
CPU time 9.17 seconds
Started Jul 04 05:21:11 PM PDT 24
Finished Jul 04 05:21:21 PM PDT 24
Peak memory 217844 kb
Host smart-82103f09-a032-494b-841f-aea27ba05a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291005977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2291005977
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1324330393
Short name T264
Test name
Test status
Simulation time 245121905 ps
CPU time 1.01 seconds
Started Jul 04 05:21:13 PM PDT 24
Finished Jul 04 05:21:14 PM PDT 24
Peak memory 217404 kb
Host smart-7868cf66-0568-4920-a048-35a09e55f395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324330393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1324330393
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1500376832
Short name T504
Test name
Test status
Simulation time 120403320 ps
CPU time 0.8 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:13 PM PDT 24
Peak memory 199884 kb
Host smart-49319029-b883-4524-9457-9800a03d9cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500376832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1500376832
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.4082087989
Short name T422
Test name
Test status
Simulation time 1453130412 ps
CPU time 5.76 seconds
Started Jul 04 05:21:11 PM PDT 24
Finished Jul 04 05:21:18 PM PDT 24
Peak memory 200360 kb
Host smart-8dcd666b-4f06-455b-8c35-238ce4332bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082087989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.4082087989
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.157314041
Short name T313
Test name
Test status
Simulation time 145776621 ps
CPU time 1.06 seconds
Started Jul 04 05:21:13 PM PDT 24
Finished Jul 04 05:21:14 PM PDT 24
Peak memory 200096 kb
Host smart-d04b769d-bd41-42fe-8e7a-982b2a0f08cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157314041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.157314041
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3951341951
Short name T44
Test name
Test status
Simulation time 232274541 ps
CPU time 1.48 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:14 PM PDT 24
Peak memory 200296 kb
Host smart-1e0bb7c6-f6fe-4bee-8868-0699501804ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951341951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3951341951
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2892682826
Short name T97
Test name
Test status
Simulation time 9254570895 ps
CPU time 35.83 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:48 PM PDT 24
Peak memory 208640 kb
Host smart-b0dd835a-4d5f-42d1-b012-8d30312f12ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892682826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2892682826
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.4280162786
Short name T488
Test name
Test status
Simulation time 390863767 ps
CPU time 2.48 seconds
Started Jul 04 05:21:11 PM PDT 24
Finished Jul 04 05:21:14 PM PDT 24
Peak memory 200068 kb
Host smart-9432b4c1-e24d-420b-a53b-921600374168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280162786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4280162786
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1345395624
Short name T144
Test name
Test status
Simulation time 91862729 ps
CPU time 0.87 seconds
Started Jul 04 05:21:11 PM PDT 24
Finished Jul 04 05:21:13 PM PDT 24
Peak memory 200096 kb
Host smart-da7e9fbc-86eb-43b8-a9a7-480bd33e66a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345395624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1345395624
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.488541439
Short name T71
Test name
Test status
Simulation time 66398417 ps
CPU time 0.77 seconds
Started Jul 04 05:21:21 PM PDT 24
Finished Jul 04 05:21:22 PM PDT 24
Peak memory 199920 kb
Host smart-090d5a9e-306a-4297-b752-eb780257f539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488541439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.488541439
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2107786109
Short name T435
Test name
Test status
Simulation time 1234083316 ps
CPU time 5.87 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:19 PM PDT 24
Peak memory 221728 kb
Host smart-eb53ac89-9a80-4758-814f-550ea64bff78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107786109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2107786109
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2211358585
Short name T169
Test name
Test status
Simulation time 244779388 ps
CPU time 1.1 seconds
Started Jul 04 05:21:13 PM PDT 24
Finished Jul 04 05:21:15 PM PDT 24
Peak memory 217488 kb
Host smart-64b7e71c-2c54-4403-8a7c-76a81f937fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211358585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2211358585
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.748302900
Short name T212
Test name
Test status
Simulation time 113077201 ps
CPU time 0.83 seconds
Started Jul 04 05:21:14 PM PDT 24
Finished Jul 04 05:21:15 PM PDT 24
Peak memory 199904 kb
Host smart-bcdf6028-7bc6-4be1-9ce7-c9ebb122e9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748302900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.748302900
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3321923470
Short name T272
Test name
Test status
Simulation time 1457666273 ps
CPU time 6.09 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:19 PM PDT 24
Peak memory 200332 kb
Host smart-ab193ae6-9919-4bcf-ae34-ec7d8e216690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321923470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3321923470
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.417433173
Short name T466
Test name
Test status
Simulation time 98742011 ps
CPU time 1.04 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:14 PM PDT 24
Peak memory 200060 kb
Host smart-b4f9c60c-4312-4bee-979b-c1b38371331c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417433173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.417433173
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3318755022
Short name T239
Test name
Test status
Simulation time 112161009 ps
CPU time 1.14 seconds
Started Jul 04 05:21:12 PM PDT 24
Finished Jul 04 05:21:14 PM PDT 24
Peak memory 200232 kb
Host smart-9aec9c08-3d2a-420a-87ec-1ca2c2332889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318755022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3318755022
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2695582745
Short name T186
Test name
Test status
Simulation time 8944484447 ps
CPU time 30.83 seconds
Started Jul 04 05:21:22 PM PDT 24
Finished Jul 04 05:21:53 PM PDT 24
Peak memory 200460 kb
Host smart-104b5b3a-f0df-4828-b7d7-5069181895ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695582745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2695582745
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3253195408
Short name T248
Test name
Test status
Simulation time 151997876 ps
CPU time 1.9 seconds
Started Jul 04 05:21:13 PM PDT 24
Finished Jul 04 05:21:15 PM PDT 24
Peak memory 200112 kb
Host smart-20d3b7b7-df5a-432b-962e-1786e110cf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253195408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3253195408
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3762570413
Short name T519
Test name
Test status
Simulation time 252732887 ps
CPU time 1.47 seconds
Started Jul 04 05:21:11 PM PDT 24
Finished Jul 04 05:21:13 PM PDT 24
Peak memory 200316 kb
Host smart-7c2b3474-1f37-49f1-95b9-7c2d1c3cc184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762570413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3762570413
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2171114546
Short name T368
Test name
Test status
Simulation time 66817030 ps
CPU time 0.81 seconds
Started Jul 04 05:21:22 PM PDT 24
Finished Jul 04 05:21:24 PM PDT 24
Peak memory 199824 kb
Host smart-af1a2b4a-20af-493c-a0d0-c883a4eb2a29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171114546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2171114546
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2934381886
Short name T331
Test name
Test status
Simulation time 1895300023 ps
CPU time 6.86 seconds
Started Jul 04 05:21:26 PM PDT 24
Finished Jul 04 05:21:33 PM PDT 24
Peak memory 217496 kb
Host smart-f84454c5-4973-4f7b-a264-cc1f5e09fa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934381886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2934381886
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1855408330
Short name T522
Test name
Test status
Simulation time 244609237 ps
CPU time 1.11 seconds
Started Jul 04 05:21:25 PM PDT 24
Finished Jul 04 05:21:27 PM PDT 24
Peak memory 217092 kb
Host smart-8a758ab7-d81f-4b4c-875d-d83438a84883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855408330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1855408330
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2258093459
Short name T243
Test name
Test status
Simulation time 107454502 ps
CPU time 0.8 seconds
Started Jul 04 05:21:19 PM PDT 24
Finished Jul 04 05:21:20 PM PDT 24
Peak memory 199868 kb
Host smart-ee57858c-be3b-4f0e-9ae8-16cbffdc049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258093459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2258093459
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.4158280225
Short name T190
Test name
Test status
Simulation time 1385662031 ps
CPU time 5.74 seconds
Started Jul 04 05:21:20 PM PDT 24
Finished Jul 04 05:21:26 PM PDT 24
Peak memory 200284 kb
Host smart-4b364133-48cf-46dd-9c9c-c7776ba2077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158280225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.4158280225
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3045955783
Short name T15
Test name
Test status
Simulation time 197106837 ps
CPU time 1.39 seconds
Started Jul 04 05:21:22 PM PDT 24
Finished Jul 04 05:21:23 PM PDT 24
Peak memory 200276 kb
Host smart-de76441a-c2e8-40bb-9550-006a089028ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045955783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3045955783
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1727988128
Short name T405
Test name
Test status
Simulation time 229456853 ps
CPU time 1.38 seconds
Started Jul 04 05:21:22 PM PDT 24
Finished Jul 04 05:21:24 PM PDT 24
Peak memory 200080 kb
Host smart-4b387024-adf6-4201-92ab-f3c4946a6aac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727988128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1727988128
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3522246998
Short name T444
Test name
Test status
Simulation time 143998696 ps
CPU time 1.68 seconds
Started Jul 04 05:21:24 PM PDT 24
Finished Jul 04 05:21:26 PM PDT 24
Peak memory 200120 kb
Host smart-5b2e7c5d-a7ac-46e9-bb83-fde8277c3499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522246998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3522246998
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1636977002
Short name T16
Test name
Test status
Simulation time 108108482 ps
CPU time 0.91 seconds
Started Jul 04 05:21:21 PM PDT 24
Finished Jul 04 05:21:22 PM PDT 24
Peak memory 200040 kb
Host smart-7975964a-559f-4182-ad21-35c7c7bcdbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636977002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1636977002
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.175892367
Short name T449
Test name
Test status
Simulation time 94363457 ps
CPU time 0.79 seconds
Started Jul 04 05:21:23 PM PDT 24
Finished Jul 04 05:21:24 PM PDT 24
Peak memory 199900 kb
Host smart-f4c75bc5-7635-4dc1-bdeb-f732103e624b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175892367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.175892367
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1839087480
Short name T493
Test name
Test status
Simulation time 1887248927 ps
CPU time 7.16 seconds
Started Jul 04 05:21:23 PM PDT 24
Finished Jul 04 05:21:31 PM PDT 24
Peak memory 217744 kb
Host smart-66edc2ad-05c8-4a45-9304-8a3ed0236742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839087480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1839087480
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.577650835
Short name T414
Test name
Test status
Simulation time 243942130 ps
CPU time 1.04 seconds
Started Jul 04 05:21:20 PM PDT 24
Finished Jul 04 05:21:21 PM PDT 24
Peak memory 217460 kb
Host smart-11a52a1f-e6f0-4458-b358-370cbc77d992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577650835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.577650835
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2793077264
Short name T221
Test name
Test status
Simulation time 213689359 ps
CPU time 0.9 seconds
Started Jul 04 05:21:25 PM PDT 24
Finished Jul 04 05:21:26 PM PDT 24
Peak memory 199476 kb
Host smart-6d54eb39-e79b-4816-8d8c-860257056d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793077264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2793077264
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3332417173
Short name T96
Test name
Test status
Simulation time 885325561 ps
CPU time 4.4 seconds
Started Jul 04 05:21:21 PM PDT 24
Finished Jul 04 05:21:26 PM PDT 24
Peak memory 200348 kb
Host smart-d46c0072-49ee-456f-8415-836726f28841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332417173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3332417173
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3667702778
Short name T226
Test name
Test status
Simulation time 178487464 ps
CPU time 1.2 seconds
Started Jul 04 05:21:21 PM PDT 24
Finished Jul 04 05:21:22 PM PDT 24
Peak memory 200020 kb
Host smart-6cc1400b-116a-426f-ac95-8ae9fa8ac738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667702778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3667702778
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3269532631
Short name T401
Test name
Test status
Simulation time 190949673 ps
CPU time 1.41 seconds
Started Jul 04 05:21:20 PM PDT 24
Finished Jul 04 05:21:21 PM PDT 24
Peak memory 200316 kb
Host smart-5e0cbec1-a195-4ac9-b5c6-384f9996df18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269532631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3269532631
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2948037535
Short name T479
Test name
Test status
Simulation time 6171161633 ps
CPU time 29.08 seconds
Started Jul 04 05:21:23 PM PDT 24
Finished Jul 04 05:21:52 PM PDT 24
Peak memory 208508 kb
Host smart-2bc69d0c-8865-4437-a46b-ac3bbd3a36bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948037535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2948037535
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1352671095
Short name T236
Test name
Test status
Simulation time 132614973 ps
CPU time 1.75 seconds
Started Jul 04 05:21:23 PM PDT 24
Finished Jul 04 05:21:25 PM PDT 24
Peak memory 208244 kb
Host smart-e95db1ee-5548-49c7-a520-3f7572388bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352671095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1352671095
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.967213263
Short name T303
Test name
Test status
Simulation time 174906590 ps
CPU time 1.14 seconds
Started Jul 04 05:21:22 PM PDT 24
Finished Jul 04 05:21:24 PM PDT 24
Peak memory 200020 kb
Host smart-5866fe59-36f7-450c-91f8-1fab8e61e481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967213263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.967213263
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1242513599
Short name T376
Test name
Test status
Simulation time 63249371 ps
CPU time 0.77 seconds
Started Jul 04 05:21:22 PM PDT 24
Finished Jul 04 05:21:23 PM PDT 24
Peak memory 199824 kb
Host smart-7a8d992f-01b1-4136-badd-aaf6e8270fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242513599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1242513599
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3878307929
Short name T352
Test name
Test status
Simulation time 1232197558 ps
CPU time 5.82 seconds
Started Jul 04 05:21:22 PM PDT 24
Finished Jul 04 05:21:28 PM PDT 24
Peak memory 217784 kb
Host smart-70982bdb-a012-4cb2-8045-16526ff21619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878307929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3878307929
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1807429121
Short name T291
Test name
Test status
Simulation time 244449323 ps
CPU time 1.09 seconds
Started Jul 04 05:21:20 PM PDT 24
Finished Jul 04 05:21:21 PM PDT 24
Peak memory 217452 kb
Host smart-40caaef6-b055-4950-af0e-4c9a02346d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807429121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1807429121
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.417135317
Short name T287
Test name
Test status
Simulation time 132190356 ps
CPU time 0.76 seconds
Started Jul 04 05:21:19 PM PDT 24
Finished Jul 04 05:21:20 PM PDT 24
Peak memory 199872 kb
Host smart-25a2860a-579b-4afc-886d-bb0913a7d0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417135317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.417135317
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2298909736
Short name T494
Test name
Test status
Simulation time 1090326143 ps
CPU time 5.7 seconds
Started Jul 04 05:21:24 PM PDT 24
Finished Jul 04 05:21:30 PM PDT 24
Peak memory 200360 kb
Host smart-d8f032d6-840c-4a1a-a166-a8a7f8bc8006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298909736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2298909736
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.789111796
Short name T535
Test name
Test status
Simulation time 164166204 ps
CPU time 1.16 seconds
Started Jul 04 05:21:21 PM PDT 24
Finished Jul 04 05:21:23 PM PDT 24
Peak memory 200060 kb
Host smart-8d991482-4ca6-43a0-afee-41e898c6de86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789111796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.789111796
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.4034562799
Short name T43
Test name
Test status
Simulation time 193365609 ps
CPU time 1.32 seconds
Started Jul 04 05:21:19 PM PDT 24
Finished Jul 04 05:21:21 PM PDT 24
Peak memory 200280 kb
Host smart-e3188522-cc68-4022-8c36-6936d5465742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034562799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.4034562799
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3824114626
Short name T80
Test name
Test status
Simulation time 1450327785 ps
CPU time 6.96 seconds
Started Jul 04 05:21:22 PM PDT 24
Finished Jul 04 05:21:29 PM PDT 24
Peak memory 200356 kb
Host smart-7f292461-66a1-4f74-abbe-020ccca30887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824114626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3824114626
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1501033348
Short name T308
Test name
Test status
Simulation time 123365380 ps
CPU time 1.54 seconds
Started Jul 04 05:21:24 PM PDT 24
Finished Jul 04 05:21:26 PM PDT 24
Peak memory 200080 kb
Host smart-5d30f748-805b-4bb7-844a-0b0f0455e212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501033348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1501033348
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.828736489
Short name T441
Test name
Test status
Simulation time 190023173 ps
CPU time 1.29 seconds
Started Jul 04 05:21:23 PM PDT 24
Finished Jul 04 05:21:25 PM PDT 24
Peak memory 200084 kb
Host smart-a8e7548c-3a43-4a6a-8776-a5f10908c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828736489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.828736489
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3486424740
Short name T269
Test name
Test status
Simulation time 74896961 ps
CPU time 0.8 seconds
Started Jul 04 05:19:40 PM PDT 24
Finished Jul 04 05:19:41 PM PDT 24
Peak memory 199856 kb
Host smart-038dc3f0-7dbe-4263-b439-ba816a843b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486424740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3486424740
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2679735943
Short name T397
Test name
Test status
Simulation time 1901004765 ps
CPU time 7.31 seconds
Started Jul 04 05:19:40 PM PDT 24
Finished Jul 04 05:19:48 PM PDT 24
Peak memory 221652 kb
Host smart-6a967e5b-0b3b-45c0-ba9b-e2ef2bd35a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679735943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2679735943
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2258955916
Short name T285
Test name
Test status
Simulation time 243529013 ps
CPU time 1.1 seconds
Started Jul 04 05:19:39 PM PDT 24
Finished Jul 04 05:19:41 PM PDT 24
Peak memory 217440 kb
Host smart-86cf5f7a-0631-45c2-8b9f-ea96a4c9b0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258955916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2258955916
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3295677934
Short name T419
Test name
Test status
Simulation time 186982352 ps
CPU time 0.83 seconds
Started Jul 04 05:19:39 PM PDT 24
Finished Jul 04 05:19:41 PM PDT 24
Peak memory 199840 kb
Host smart-c1bb628c-4fa5-4349-a286-5851a833edfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295677934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3295677934
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1057738314
Short name T207
Test name
Test status
Simulation time 1841428314 ps
CPU time 7.03 seconds
Started Jul 04 05:19:39 PM PDT 24
Finished Jul 04 05:19:47 PM PDT 24
Peak memory 200364 kb
Host smart-b34a67ea-4118-4028-a767-b8369113ea6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057738314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1057738314
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.250797401
Short name T68
Test name
Test status
Simulation time 8332977522 ps
CPU time 12.92 seconds
Started Jul 04 05:19:39 PM PDT 24
Finished Jul 04 05:19:53 PM PDT 24
Peak memory 221072 kb
Host smart-e9b4e651-2a0c-454f-8674-254f2264f3d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250797401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.250797401
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2999999367
Short name T311
Test name
Test status
Simulation time 134614410 ps
CPU time 1.11 seconds
Started Jul 04 05:19:39 PM PDT 24
Finished Jul 04 05:19:41 PM PDT 24
Peak memory 200060 kb
Host smart-e885bae3-311b-48cb-8cb2-17eaa1829265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999999367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2999999367
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3866257717
Short name T339
Test name
Test status
Simulation time 259783226 ps
CPU time 1.6 seconds
Started Jul 04 05:19:40 PM PDT 24
Finished Jul 04 05:19:42 PM PDT 24
Peak memory 200232 kb
Host smart-49c00248-5590-431c-a082-531a56b949f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866257717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3866257717
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1464067865
Short name T472
Test name
Test status
Simulation time 6881050463 ps
CPU time 25.18 seconds
Started Jul 04 05:19:38 PM PDT 24
Finished Jul 04 05:20:04 PM PDT 24
Peak memory 216740 kb
Host smart-3ae92747-572a-4fc4-9e36-183c02ff056b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464067865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1464067865
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2467793875
Short name T416
Test name
Test status
Simulation time 458582377 ps
CPU time 2.46 seconds
Started Jul 04 05:19:39 PM PDT 24
Finished Jul 04 05:19:42 PM PDT 24
Peak memory 200120 kb
Host smart-79004cd3-cff3-40b5-b1e1-10b051349764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467793875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2467793875
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1079624970
Short name T515
Test name
Test status
Simulation time 131316973 ps
CPU time 0.95 seconds
Started Jul 04 05:19:39 PM PDT 24
Finished Jul 04 05:19:40 PM PDT 24
Peak memory 200084 kb
Host smart-81ed8187-f545-4037-87c6-f1e42a8e7f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079624970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1079624970
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.986664170
Short name T428
Test name
Test status
Simulation time 77403404 ps
CPU time 0.75 seconds
Started Jul 04 05:21:19 PM PDT 24
Finished Jul 04 05:21:20 PM PDT 24
Peak memory 199876 kb
Host smart-9033d9d8-8772-427e-8a6b-5c08829a8e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986664170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.986664170
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3043250331
Short name T389
Test name
Test status
Simulation time 2359920767 ps
CPU time 7.92 seconds
Started Jul 04 05:21:23 PM PDT 24
Finished Jul 04 05:21:31 PM PDT 24
Peak memory 217888 kb
Host smart-27093fb0-9e8c-4023-9296-6922bbf7ed92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043250331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3043250331
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3633981439
Short name T175
Test name
Test status
Simulation time 243916888 ps
CPU time 1.11 seconds
Started Jul 04 05:21:22 PM PDT 24
Finished Jul 04 05:21:24 PM PDT 24
Peak memory 217448 kb
Host smart-b8872db1-9d71-4e10-9bff-371cd15ef48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633981439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3633981439
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.188762086
Short name T259
Test name
Test status
Simulation time 197277266 ps
CPU time 0.87 seconds
Started Jul 04 05:21:20 PM PDT 24
Finished Jul 04 05:21:21 PM PDT 24
Peak memory 199812 kb
Host smart-38bb5ef5-d1e6-40ca-a539-8122f63bf156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188762086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.188762086
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3263287034
Short name T251
Test name
Test status
Simulation time 1208830807 ps
CPU time 4.96 seconds
Started Jul 04 05:21:24 PM PDT 24
Finished Jul 04 05:21:30 PM PDT 24
Peak memory 200340 kb
Host smart-81f9f5e2-2761-439b-875a-45a7db697033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263287034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3263287034
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.564640861
Short name T363
Test name
Test status
Simulation time 101581494 ps
CPU time 1.02 seconds
Started Jul 04 05:21:20 PM PDT 24
Finished Jul 04 05:21:21 PM PDT 24
Peak memory 200084 kb
Host smart-1cfe315b-8030-448a-b52c-9baae0e75257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564640861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.564640861
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2046570653
Short name T290
Test name
Test status
Simulation time 238399162 ps
CPU time 1.51 seconds
Started Jul 04 05:21:21 PM PDT 24
Finished Jul 04 05:21:22 PM PDT 24
Peak memory 200264 kb
Host smart-085b0abf-2c66-48ed-8973-ceba6c04d277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046570653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2046570653
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1061156524
Short name T204
Test name
Test status
Simulation time 2707842710 ps
CPU time 12.17 seconds
Started Jul 04 05:21:23 PM PDT 24
Finished Jul 04 05:21:36 PM PDT 24
Peak memory 208656 kb
Host smart-713a1f27-9d7f-4e29-8e29-ca17b3d7f940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061156524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1061156524
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3458214647
Short name T450
Test name
Test status
Simulation time 124702166 ps
CPU time 1.57 seconds
Started Jul 04 05:21:21 PM PDT 24
Finished Jul 04 05:21:22 PM PDT 24
Peak memory 208284 kb
Host smart-bdb626da-30eb-4f32-928a-7cd88b0ff8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458214647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3458214647
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3048954840
Short name T418
Test name
Test status
Simulation time 144442499 ps
CPU time 1.19 seconds
Started Jul 04 05:21:22 PM PDT 24
Finished Jul 04 05:21:23 PM PDT 24
Peak memory 200084 kb
Host smart-724df38c-0b16-4934-a0db-08bcf4cf3308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048954840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3048954840
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.178983788
Short name T298
Test name
Test status
Simulation time 62444859 ps
CPU time 0.76 seconds
Started Jul 04 05:21:31 PM PDT 24
Finished Jul 04 05:21:32 PM PDT 24
Peak memory 199884 kb
Host smart-35442099-d6ce-4c82-867c-c374e851a8eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178983788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.178983788
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3479187848
Short name T39
Test name
Test status
Simulation time 1227284494 ps
CPU time 5.78 seconds
Started Jul 04 05:21:31 PM PDT 24
Finished Jul 04 05:21:37 PM PDT 24
Peak memory 217536 kb
Host smart-f22f5d85-3f56-46e7-a380-ddc79c3fcf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479187848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3479187848
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3846923434
Short name T189
Test name
Test status
Simulation time 244774596 ps
CPU time 1.06 seconds
Started Jul 04 05:21:27 PM PDT 24
Finished Jul 04 05:21:29 PM PDT 24
Peak memory 217460 kb
Host smart-c0573b3a-40ae-4b0d-a8df-57a5635ce29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846923434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3846923434
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.495807415
Short name T348
Test name
Test status
Simulation time 141649185 ps
CPU time 0.81 seconds
Started Jul 04 05:21:19 PM PDT 24
Finished Jul 04 05:21:20 PM PDT 24
Peak memory 199856 kb
Host smart-6a6e5212-dc3f-4f08-864a-47dae7f37e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495807415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.495807415
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1058036483
Short name T99
Test name
Test status
Simulation time 839282088 ps
CPU time 4.34 seconds
Started Jul 04 05:21:23 PM PDT 24
Finished Jul 04 05:21:28 PM PDT 24
Peak memory 200364 kb
Host smart-4c432505-99f1-4458-9968-8aa48e491f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058036483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1058036483
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2793078382
Short name T337
Test name
Test status
Simulation time 102523823 ps
CPU time 0.99 seconds
Started Jul 04 05:21:27 PM PDT 24
Finished Jul 04 05:21:28 PM PDT 24
Peak memory 200080 kb
Host smart-9f85e1a7-90a7-48a5-b13f-e6e09fab6919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793078382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2793078382
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1295822112
Short name T302
Test name
Test status
Simulation time 207498602 ps
CPU time 1.43 seconds
Started Jul 04 05:21:24 PM PDT 24
Finished Jul 04 05:21:26 PM PDT 24
Peak memory 200308 kb
Host smart-d0b8899a-7cff-403b-a4f7-b0b6b6b43615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295822112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1295822112
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1317936894
Short name T233
Test name
Test status
Simulation time 3312934606 ps
CPU time 14.67 seconds
Started Jul 04 05:21:30 PM PDT 24
Finished Jul 04 05:21:45 PM PDT 24
Peak memory 208628 kb
Host smart-53227c6c-9188-4fba-869a-68e12bf0dda9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317936894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1317936894
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.55826599
Short name T79
Test name
Test status
Simulation time 139532517 ps
CPU time 1.84 seconds
Started Jul 04 05:21:25 PM PDT 24
Finished Jul 04 05:21:27 PM PDT 24
Peak memory 200100 kb
Host smart-d7ed6087-6ee7-4cb6-9292-80a8a117a973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55826599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.55826599
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.101143459
Short name T481
Test name
Test status
Simulation time 296152910 ps
CPU time 1.56 seconds
Started Jul 04 05:21:23 PM PDT 24
Finished Jul 04 05:21:25 PM PDT 24
Peak memory 200300 kb
Host smart-5f97045b-167b-40ce-a5f7-4cdd32016499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101143459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.101143459
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1569819519
Short name T434
Test name
Test status
Simulation time 61659620 ps
CPU time 0.73 seconds
Started Jul 04 05:21:28 PM PDT 24
Finished Jul 04 05:21:29 PM PDT 24
Peak memory 199892 kb
Host smart-b36798f3-d2e7-4b05-8120-2b2f8f8e4b7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569819519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1569819519
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1453256575
Short name T48
Test name
Test status
Simulation time 2359303967 ps
CPU time 7.86 seconds
Started Jul 04 05:21:27 PM PDT 24
Finished Jul 04 05:21:35 PM PDT 24
Peak memory 217776 kb
Host smart-5b46e264-2091-4139-aae9-2072bdfa98f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453256575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1453256575
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.820689074
Short name T157
Test name
Test status
Simulation time 244582176 ps
CPU time 1.16 seconds
Started Jul 04 05:21:30 PM PDT 24
Finished Jul 04 05:21:32 PM PDT 24
Peak memory 217476 kb
Host smart-745a6419-1df4-4f22-88a8-9557c8d372a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820689074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.820689074
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.77493436
Short name T320
Test name
Test status
Simulation time 204907442 ps
CPU time 0.96 seconds
Started Jul 04 05:21:34 PM PDT 24
Finished Jul 04 05:21:36 PM PDT 24
Peak memory 199884 kb
Host smart-fba33ac8-2672-474b-9bab-8371f6780461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77493436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.77493436
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2665138791
Short name T456
Test name
Test status
Simulation time 1561632473 ps
CPU time 6.72 seconds
Started Jul 04 05:21:33 PM PDT 24
Finished Jul 04 05:21:40 PM PDT 24
Peak memory 200360 kb
Host smart-fce975a6-1aa5-4239-9be9-f700f035a995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665138791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2665138791
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.604143619
Short name T501
Test name
Test status
Simulation time 104658977 ps
CPU time 1.12 seconds
Started Jul 04 05:21:32 PM PDT 24
Finished Jul 04 05:21:34 PM PDT 24
Peak memory 200072 kb
Host smart-09c18c43-8b7d-463a-a6fe-59c5ddc530f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604143619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.604143619
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.349518381
Short name T181
Test name
Test status
Simulation time 245747216 ps
CPU time 1.57 seconds
Started Jul 04 05:21:32 PM PDT 24
Finished Jul 04 05:21:33 PM PDT 24
Peak memory 200292 kb
Host smart-28e37a63-f1de-4a18-b226-b67bc1595d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349518381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.349518381
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2132154326
Short name T194
Test name
Test status
Simulation time 2896421627 ps
CPU time 12.98 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:42 PM PDT 24
Peak memory 208580 kb
Host smart-ac81ac58-483a-4644-b868-117e78e3a5cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132154326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2132154326
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1060216350
Short name T176
Test name
Test status
Simulation time 291944241 ps
CPU time 2 seconds
Started Jul 04 05:21:32 PM PDT 24
Finished Jul 04 05:21:34 PM PDT 24
Peak memory 200084 kb
Host smart-84c9742a-cccb-4d24-b00e-1ea280d45893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060216350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1060216350
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3648257319
Short name T316
Test name
Test status
Simulation time 151816189 ps
CPU time 1.04 seconds
Started Jul 04 05:21:26 PM PDT 24
Finished Jul 04 05:21:28 PM PDT 24
Peak memory 200080 kb
Host smart-67180395-eb04-4073-b544-0eacf1ad3345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648257319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3648257319
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1499308542
Short name T288
Test name
Test status
Simulation time 58410535 ps
CPU time 0.74 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:30 PM PDT 24
Peak memory 199876 kb
Host smart-5b994776-a062-4892-8af6-d994719fa90c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499308542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1499308542
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3520020508
Short name T381
Test name
Test status
Simulation time 2150459195 ps
CPU time 7.58 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:37 PM PDT 24
Peak memory 217808 kb
Host smart-15e2d087-cfc0-4d8a-91bc-51ab9546b231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520020508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3520020508
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.981968053
Short name T55
Test name
Test status
Simulation time 245535061 ps
CPU time 1.02 seconds
Started Jul 04 05:21:27 PM PDT 24
Finished Jul 04 05:21:29 PM PDT 24
Peak memory 217468 kb
Host smart-f3289dfa-89d3-406c-a626-db75f7a82ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981968053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.981968053
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1317042091
Short name T23
Test name
Test status
Simulation time 120448375 ps
CPU time 0.78 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:30 PM PDT 24
Peak memory 199904 kb
Host smart-6675599a-71e9-473c-96e7-78ebd9eb3fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317042091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1317042091
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2145303897
Short name T90
Test name
Test status
Simulation time 933044935 ps
CPU time 4.95 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:34 PM PDT 24
Peak memory 200340 kb
Host smart-abbdc971-f10e-4684-9d57-53011ed75419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145303897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2145303897
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.789331863
Short name T454
Test name
Test status
Simulation time 148198338 ps
CPU time 1.11 seconds
Started Jul 04 05:21:30 PM PDT 24
Finished Jul 04 05:21:31 PM PDT 24
Peak memory 200084 kb
Host smart-91d3bde3-1f27-4242-a9d9-f96b05421778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789331863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.789331863
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2018313306
Short name T464
Test name
Test status
Simulation time 196616963 ps
CPU time 1.38 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:31 PM PDT 24
Peak memory 200300 kb
Host smart-94c40928-8d58-49d6-aef3-8c7b3a5c43e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018313306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2018313306
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.4164586638
Short name T409
Test name
Test status
Simulation time 7192622073 ps
CPU time 24.49 seconds
Started Jul 04 05:21:33 PM PDT 24
Finished Jul 04 05:21:58 PM PDT 24
Peak memory 200408 kb
Host smart-4cca93fb-3580-4110-9aa3-635d78e40f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164586638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.4164586638
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.85731182
Short name T473
Test name
Test status
Simulation time 111454238 ps
CPU time 1.36 seconds
Started Jul 04 05:21:28 PM PDT 24
Finished Jul 04 05:21:30 PM PDT 24
Peak memory 200088 kb
Host smart-27db2b97-96ef-43a4-8061-7240a77dc078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85731182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.85731182
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.324698972
Short name T132
Test name
Test status
Simulation time 113522231 ps
CPU time 1.08 seconds
Started Jul 04 05:21:34 PM PDT 24
Finished Jul 04 05:21:36 PM PDT 24
Peak memory 200076 kb
Host smart-8eb0763d-1531-4b62-b19c-75476a42562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324698972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.324698972
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2723202552
Short name T183
Test name
Test status
Simulation time 65037446 ps
CPU time 0.75 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:30 PM PDT 24
Peak memory 200232 kb
Host smart-c19c81aa-c266-463e-8eab-efc3e2f6a255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723202552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2723202552
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1643327933
Short name T36
Test name
Test status
Simulation time 2179420632 ps
CPU time 7.68 seconds
Started Jul 04 05:21:27 PM PDT 24
Finished Jul 04 05:21:35 PM PDT 24
Peak memory 217812 kb
Host smart-0ed9bfe1-27dd-4841-b79e-9430bb701c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643327933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1643327933
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3110592133
Short name T351
Test name
Test status
Simulation time 252195391 ps
CPU time 1.1 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:31 PM PDT 24
Peak memory 217488 kb
Host smart-9c2956bd-1d7c-4f1a-89e9-b98c51a30122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110592133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3110592133
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3752621676
Short name T491
Test name
Test status
Simulation time 200400373 ps
CPU time 0.9 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:31 PM PDT 24
Peak memory 199908 kb
Host smart-338b28c1-f84d-48a5-864a-a23516c1a2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752621676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3752621676
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2910080546
Short name T121
Test name
Test status
Simulation time 1584926895 ps
CPU time 6.72 seconds
Started Jul 04 05:21:32 PM PDT 24
Finished Jul 04 05:21:39 PM PDT 24
Peak memory 200332 kb
Host smart-ffd3d350-78a5-4b9e-8079-d34840709cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910080546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2910080546
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2338312144
Short name T452
Test name
Test status
Simulation time 96867838 ps
CPU time 1.05 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:30 PM PDT 24
Peak memory 200064 kb
Host smart-c99d28c8-e8c1-464d-a29d-99a6801de843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338312144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2338312144
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.482769716
Short name T333
Test name
Test status
Simulation time 129605329 ps
CPU time 1.16 seconds
Started Jul 04 05:21:32 PM PDT 24
Finished Jul 04 05:21:34 PM PDT 24
Peak memory 200292 kb
Host smart-628f253b-7d34-477e-8ca6-b3ceb4fe07bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482769716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.482769716
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1297986478
Short name T187
Test name
Test status
Simulation time 8638261136 ps
CPU time 43.04 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:22:13 PM PDT 24
Peak memory 208588 kb
Host smart-8601aa39-d7f8-425d-812c-714da10b149f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297986478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1297986478
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4222658072
Short name T349
Test name
Test status
Simulation time 138077742 ps
CPU time 1.66 seconds
Started Jul 04 05:21:28 PM PDT 24
Finished Jul 04 05:21:30 PM PDT 24
Peak memory 200092 kb
Host smart-ae2d6f55-b795-43e0-b73a-11a68d113e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222658072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4222658072
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1584647012
Short name T413
Test name
Test status
Simulation time 78871619 ps
CPU time 0.88 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:30 PM PDT 24
Peak memory 200076 kb
Host smart-d8b7ba04-f431-4a29-8659-b71a3215eac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584647012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1584647012
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3242164245
Short name T421
Test name
Test status
Simulation time 78856781 ps
CPU time 0.78 seconds
Started Jul 04 05:21:30 PM PDT 24
Finished Jul 04 05:21:31 PM PDT 24
Peak memory 199884 kb
Host smart-b983413b-6535-473e-a7d2-76ff7a7fd5bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242164245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3242164245
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3530178268
Short name T154
Test name
Test status
Simulation time 243955768 ps
CPU time 1.08 seconds
Started Jul 04 05:21:31 PM PDT 24
Finished Jul 04 05:21:32 PM PDT 24
Peak memory 217492 kb
Host smart-87e490e6-892e-482e-9cfe-d828448ee062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530178268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3530178268
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3948343512
Short name T22
Test name
Test status
Simulation time 85023993 ps
CPU time 0.78 seconds
Started Jul 04 05:21:31 PM PDT 24
Finished Jul 04 05:21:33 PM PDT 24
Peak memory 199896 kb
Host smart-e70891de-767a-4fbc-8755-0f4c9f96e74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948343512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3948343512
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.677487491
Short name T253
Test name
Test status
Simulation time 1634834750 ps
CPU time 6.46 seconds
Started Jul 04 05:21:27 PM PDT 24
Finished Jul 04 05:21:34 PM PDT 24
Peak memory 200324 kb
Host smart-843b8aa0-42af-406d-9e06-43746bdf43c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677487491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.677487491
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1632441576
Short name T219
Test name
Test status
Simulation time 105401221 ps
CPU time 1.06 seconds
Started Jul 04 05:21:33 PM PDT 24
Finished Jul 04 05:21:34 PM PDT 24
Peak memory 199992 kb
Host smart-17a34f2c-60e7-4a89-a68e-3cd135697fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632441576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1632441576
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3015664635
Short name T3
Test name
Test status
Simulation time 241982996 ps
CPU time 1.43 seconds
Started Jul 04 05:21:28 PM PDT 24
Finished Jul 04 05:21:30 PM PDT 24
Peak memory 200280 kb
Host smart-d966e536-3727-4e52-af79-d248f2be1178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015664635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3015664635
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2722080324
Short name T510
Test name
Test status
Simulation time 1571798690 ps
CPU time 7.03 seconds
Started Jul 04 05:21:31 PM PDT 24
Finished Jul 04 05:21:39 PM PDT 24
Peak memory 200348 kb
Host smart-664699e9-1854-4480-a761-ec47de6d4853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722080324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2722080324
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3576416130
Short name T192
Test name
Test status
Simulation time 368041714 ps
CPU time 2.44 seconds
Started Jul 04 05:21:31 PM PDT 24
Finished Jul 04 05:21:34 PM PDT 24
Peak memory 200084 kb
Host smart-0ba0ce5a-e447-4044-9d5d-eca8a993d5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576416130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3576416130
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2280177357
Short name T76
Test name
Test status
Simulation time 261578891 ps
CPU time 1.65 seconds
Started Jul 04 05:21:33 PM PDT 24
Finished Jul 04 05:21:35 PM PDT 24
Peak memory 200064 kb
Host smart-2713e5d8-678e-4cf6-984b-06f120fdd571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280177357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2280177357
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2626348777
Short name T438
Test name
Test status
Simulation time 57074817 ps
CPU time 0.76 seconds
Started Jul 04 05:21:40 PM PDT 24
Finished Jul 04 05:21:41 PM PDT 24
Peak memory 199896 kb
Host smart-91527136-7641-4d66-acf6-15dd6b205843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626348777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2626348777
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1005579235
Short name T310
Test name
Test status
Simulation time 2369045054 ps
CPU time 8.42 seconds
Started Jul 04 05:21:36 PM PDT 24
Finished Jul 04 05:21:45 PM PDT 24
Peak memory 217888 kb
Host smart-8d0a5e53-c49f-4ba9-b6fa-5d8838f4b974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005579235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1005579235
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1042141424
Short name T370
Test name
Test status
Simulation time 243621565 ps
CPU time 1.15 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:44 PM PDT 24
Peak memory 217472 kb
Host smart-7503ee87-16d3-4ec7-99b9-617995f1a1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042141424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1042141424
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.819148060
Short name T495
Test name
Test status
Simulation time 161659523 ps
CPU time 0.87 seconds
Started Jul 04 05:21:27 PM PDT 24
Finished Jul 04 05:21:28 PM PDT 24
Peak memory 199928 kb
Host smart-99e522d6-5557-453e-8411-e336f4673d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819148060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.819148060
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.881565109
Short name T520
Test name
Test status
Simulation time 994041521 ps
CPU time 5.13 seconds
Started Jul 04 05:21:33 PM PDT 24
Finished Jul 04 05:21:38 PM PDT 24
Peak memory 200240 kb
Host smart-01aaaa7a-1985-4eee-874b-50222b01b729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881565109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.881565109
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.4268546154
Short name T496
Test name
Test status
Simulation time 95146787 ps
CPU time 1.02 seconds
Started Jul 04 05:21:36 PM PDT 24
Finished Jul 04 05:21:38 PM PDT 24
Peak memory 200076 kb
Host smart-20195795-20c0-4772-a2ae-0a41aea5ed47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268546154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.4268546154
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2433591525
Short name T283
Test name
Test status
Simulation time 198956881 ps
CPU time 1.44 seconds
Started Jul 04 05:21:28 PM PDT 24
Finished Jul 04 05:21:30 PM PDT 24
Peak memory 200276 kb
Host smart-33ca9cb8-008b-4c63-8fa1-b4716210dafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433591525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2433591525
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.141042102
Short name T262
Test name
Test status
Simulation time 429025435 ps
CPU time 2.39 seconds
Started Jul 04 05:21:39 PM PDT 24
Finished Jul 04 05:21:42 PM PDT 24
Peak memory 208348 kb
Host smart-21e6054e-77b1-463e-bae0-d2374a3ab954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141042102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.141042102
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.787541578
Short name T445
Test name
Test status
Simulation time 200532499 ps
CPU time 1.27 seconds
Started Jul 04 05:21:29 PM PDT 24
Finished Jul 04 05:21:31 PM PDT 24
Peak memory 200084 kb
Host smart-382d1dfe-44c1-4cf3-9b4d-1aa79dd44395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787541578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.787541578
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3497893077
Short name T184
Test name
Test status
Simulation time 60156580 ps
CPU time 0.71 seconds
Started Jul 04 05:21:33 PM PDT 24
Finished Jul 04 05:21:35 PM PDT 24
Peak memory 199888 kb
Host smart-c5a39a59-980c-49f8-bd4d-d4e2c98b433a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497893077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3497893077
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.4098720487
Short name T353
Test name
Test status
Simulation time 1219214114 ps
CPU time 5.45 seconds
Started Jul 04 05:21:37 PM PDT 24
Finished Jul 04 05:21:43 PM PDT 24
Peak memory 217736 kb
Host smart-8e5b15fd-7a14-4955-807e-e50cc7b51bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098720487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.4098720487
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1232193604
Short name T502
Test name
Test status
Simulation time 244703889 ps
CPU time 1.06 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:44 PM PDT 24
Peak memory 217472 kb
Host smart-63e57ad3-169f-44f8-b4be-e34b190f443c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232193604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1232193604
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1748940040
Short name T345
Test name
Test status
Simulation time 181439781 ps
CPU time 0.86 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:44 PM PDT 24
Peak memory 199904 kb
Host smart-9f8f815b-7930-4a4f-95f1-f4968b36b296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748940040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1748940040
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1022617030
Short name T394
Test name
Test status
Simulation time 1439759097 ps
CPU time 5.71 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:49 PM PDT 24
Peak memory 200364 kb
Host smart-9cf3b86c-6e05-4b59-a33a-6916cd61da50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022617030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1022617030
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1338381199
Short name T42
Test name
Test status
Simulation time 93325329 ps
CPU time 0.96 seconds
Started Jul 04 05:21:39 PM PDT 24
Finished Jul 04 05:21:40 PM PDT 24
Peak memory 200084 kb
Host smart-178792cf-57f4-4493-90b5-baac0a0f7ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338381199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1338381199
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1642198950
Short name T128
Test name
Test status
Simulation time 253495858 ps
CPU time 1.57 seconds
Started Jul 04 05:21:35 PM PDT 24
Finished Jul 04 05:21:37 PM PDT 24
Peak memory 200264 kb
Host smart-227e7cba-9db9-4a84-a9da-fc8668cd44c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642198950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1642198950
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2742766393
Short name T299
Test name
Test status
Simulation time 2041385610 ps
CPU time 7.79 seconds
Started Jul 04 05:21:34 PM PDT 24
Finished Jul 04 05:21:42 PM PDT 24
Peak memory 209596 kb
Host smart-63dd0c62-8796-497c-b466-7aeaefa4bc6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742766393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2742766393
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1004353102
Short name T9
Test name
Test status
Simulation time 113540861 ps
CPU time 1.55 seconds
Started Jul 04 05:21:35 PM PDT 24
Finished Jul 04 05:21:38 PM PDT 24
Peak memory 200096 kb
Host smart-b59be7c9-5577-4769-9776-fdd474d69946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004353102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1004353102
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.4150370619
Short name T195
Test name
Test status
Simulation time 193828818 ps
CPU time 1.23 seconds
Started Jul 04 05:21:36 PM PDT 24
Finished Jul 04 05:21:37 PM PDT 24
Peak memory 200080 kb
Host smart-6c33e85f-ca02-4b41-a9fc-d094166cf1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150370619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4150370619
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1119808632
Short name T155
Test name
Test status
Simulation time 84661568 ps
CPU time 0.86 seconds
Started Jul 04 05:21:35 PM PDT 24
Finished Jul 04 05:21:36 PM PDT 24
Peak memory 199884 kb
Host smart-d9806abe-3a15-4e33-bc5a-9f61bc3840cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119808632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1119808632
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2263532997
Short name T490
Test name
Test status
Simulation time 1225675506 ps
CPU time 6.53 seconds
Started Jul 04 05:21:37 PM PDT 24
Finished Jul 04 05:21:44 PM PDT 24
Peak memory 217764 kb
Host smart-82b0f2b0-45a7-4f70-bc56-d2f239b4ca5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263532997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2263532997
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1743626200
Short name T201
Test name
Test status
Simulation time 243621795 ps
CPU time 1.05 seconds
Started Jul 04 05:21:35 PM PDT 24
Finished Jul 04 05:21:37 PM PDT 24
Peak memory 217432 kb
Host smart-c7383e56-5178-43e4-80a8-dc5c522ac1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743626200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1743626200
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3837744541
Short name T314
Test name
Test status
Simulation time 956919368 ps
CPU time 4.5 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:48 PM PDT 24
Peak memory 200364 kb
Host smart-49c95e0c-fb78-4bec-b240-7f1337d60e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837744541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3837744541
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2955128586
Short name T499
Test name
Test status
Simulation time 142570334 ps
CPU time 1.11 seconds
Started Jul 04 05:21:36 PM PDT 24
Finished Jul 04 05:21:38 PM PDT 24
Peak memory 200084 kb
Host smart-c38fb08d-e5f3-4812-8800-a12e6acc3bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955128586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2955128586
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.4043357985
Short name T540
Test name
Test status
Simulation time 121443852 ps
CPU time 1.17 seconds
Started Jul 04 05:21:36 PM PDT 24
Finished Jul 04 05:21:37 PM PDT 24
Peak memory 200324 kb
Host smart-01b58ee7-e0d3-48a0-b1c0-2b581c827b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043357985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.4043357985
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.359558525
Short name T252
Test name
Test status
Simulation time 1071196171 ps
CPU time 5.05 seconds
Started Jul 04 05:21:36 PM PDT 24
Finished Jul 04 05:21:42 PM PDT 24
Peak memory 200348 kb
Host smart-dda69d84-a95c-4463-9956-e0615d2f812b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359558525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.359558525
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3906579353
Short name T223
Test name
Test status
Simulation time 267490303 ps
CPU time 2.08 seconds
Started Jul 04 05:21:34 PM PDT 24
Finished Jul 04 05:21:37 PM PDT 24
Peak memory 200076 kb
Host smart-6dd90760-3e93-4e82-a237-d7176cf9cf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906579353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3906579353
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3753003295
Short name T136
Test name
Test status
Simulation time 84152727 ps
CPU time 0.81 seconds
Started Jul 04 05:21:35 PM PDT 24
Finished Jul 04 05:21:36 PM PDT 24
Peak memory 200072 kb
Host smart-6467f6be-3931-4695-bf37-8be79c54e7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753003295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3753003295
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2632449414
Short name T395
Test name
Test status
Simulation time 73689172 ps
CPU time 0.73 seconds
Started Jul 04 05:21:37 PM PDT 24
Finished Jul 04 05:21:38 PM PDT 24
Peak memory 199868 kb
Host smart-4d144fe5-3fa2-4436-a883-a6a902d75c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632449414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2632449414
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1622265458
Short name T38
Test name
Test status
Simulation time 2357674100 ps
CPU time 7.98 seconds
Started Jul 04 05:21:35 PM PDT 24
Finished Jul 04 05:21:43 PM PDT 24
Peak memory 217716 kb
Host smart-7933037e-bb04-4da7-bfa0-e207397cf5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622265458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1622265458
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3403931743
Short name T443
Test name
Test status
Simulation time 244696218 ps
CPU time 1.09 seconds
Started Jul 04 05:21:39 PM PDT 24
Finished Jul 04 05:21:40 PM PDT 24
Peak memory 217412 kb
Host smart-3f562429-175b-4457-b970-43f886ec1026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403931743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3403931743
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1020335263
Short name T534
Test name
Test status
Simulation time 148873165 ps
CPU time 0.82 seconds
Started Jul 04 05:21:34 PM PDT 24
Finished Jul 04 05:21:35 PM PDT 24
Peak memory 199888 kb
Host smart-839f02b6-f872-4ec6-8f88-836f8032685b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020335263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1020335263
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2964598628
Short name T505
Test name
Test status
Simulation time 1561993704 ps
CPU time 6.27 seconds
Started Jul 04 05:21:39 PM PDT 24
Finished Jul 04 05:21:46 PM PDT 24
Peak memory 200348 kb
Host smart-7e4a5fe8-c103-4d79-9d42-dfc143bc8605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964598628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2964598628
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1963583053
Short name T508
Test name
Test status
Simulation time 186900640 ps
CPU time 1.15 seconds
Started Jul 04 05:21:36 PM PDT 24
Finished Jul 04 05:21:37 PM PDT 24
Peak memory 200072 kb
Host smart-16e3dce3-7758-4f2f-b529-96b159bbbc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963583053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1963583053
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3628728328
Short name T218
Test name
Test status
Simulation time 193190561 ps
CPU time 1.47 seconds
Started Jul 04 05:21:36 PM PDT 24
Finished Jul 04 05:21:38 PM PDT 24
Peak memory 200268 kb
Host smart-758fdd0a-fe06-434f-8ac0-1cc3ff66cba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628728328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3628728328
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1537306099
Short name T56
Test name
Test status
Simulation time 4227811196 ps
CPU time 13.71 seconds
Started Jul 04 05:21:37 PM PDT 24
Finished Jul 04 05:21:51 PM PDT 24
Peak memory 208548 kb
Host smart-aedb343f-2780-434b-830a-3a48c02b8246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537306099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1537306099
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1003283415
Short name T492
Test name
Test status
Simulation time 132075755 ps
CPU time 1.68 seconds
Started Jul 04 05:21:37 PM PDT 24
Finished Jul 04 05:21:39 PM PDT 24
Peak memory 200092 kb
Host smart-d37b8e25-2f89-4851-9f90-88859096977d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003283415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1003283415
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3946968230
Short name T305
Test name
Test status
Simulation time 174951719 ps
CPU time 1.41 seconds
Started Jul 04 05:21:39 PM PDT 24
Finished Jul 04 05:21:41 PM PDT 24
Peak memory 200068 kb
Host smart-bf6ae9f1-e988-4514-acfa-14b19f45d2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946968230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3946968230
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1224132305
Short name T300
Test name
Test status
Simulation time 65452713 ps
CPU time 0.8 seconds
Started Jul 04 05:19:50 PM PDT 24
Finished Jul 04 05:19:51 PM PDT 24
Peak memory 199860 kb
Host smart-913b8570-1553-4c77-b16c-294a419bc723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224132305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1224132305
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2880905232
Short name T32
Test name
Test status
Simulation time 1894545452 ps
CPU time 6.86 seconds
Started Jul 04 05:19:48 PM PDT 24
Finished Jul 04 05:19:55 PM PDT 24
Peak memory 217768 kb
Host smart-947e9808-5941-45be-b317-2050675166d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880905232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2880905232
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.493776277
Short name T224
Test name
Test status
Simulation time 245116397 ps
CPU time 1.12 seconds
Started Jul 04 05:19:47 PM PDT 24
Finished Jul 04 05:19:48 PM PDT 24
Peak memory 217348 kb
Host smart-47967f53-9cf9-4ab6-9aab-b8c70f4c821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493776277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.493776277
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.4009488032
Short name T451
Test name
Test status
Simulation time 91904861 ps
CPU time 0.78 seconds
Started Jul 04 05:19:40 PM PDT 24
Finished Jul 04 05:19:41 PM PDT 24
Peak memory 199872 kb
Host smart-fd8acbc1-95c6-41d3-8f9b-0ea56d6c3c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009488032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.4009488032
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2295923795
Short name T338
Test name
Test status
Simulation time 1796912396 ps
CPU time 6.95 seconds
Started Jul 04 05:19:40 PM PDT 24
Finished Jul 04 05:19:47 PM PDT 24
Peak memory 200340 kb
Host smart-b8f5f60f-cf49-4d41-be4d-cd4e151bc0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295923795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2295923795
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.9049734
Short name T530
Test name
Test status
Simulation time 112453143 ps
CPU time 1.04 seconds
Started Jul 04 05:19:49 PM PDT 24
Finished Jul 04 05:19:50 PM PDT 24
Peak memory 200064 kb
Host smart-cd6e3359-449e-4cdb-81f4-d1f265f35cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9049734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.9049734
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1071645407
Short name T151
Test name
Test status
Simulation time 113814107 ps
CPU time 1.19 seconds
Started Jul 04 05:19:40 PM PDT 24
Finished Jul 04 05:19:41 PM PDT 24
Peak memory 200276 kb
Host smart-ffb456c1-381e-45d6-876f-73a5faf52f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071645407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1071645407
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2055419129
Short name T227
Test name
Test status
Simulation time 2244831541 ps
CPU time 10.7 seconds
Started Jul 04 05:19:49 PM PDT 24
Finished Jul 04 05:20:00 PM PDT 24
Peak memory 209808 kb
Host smart-03a2fab1-41dc-45ed-be21-bff06af2adea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055419129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2055419129
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1912698412
Short name T407
Test name
Test status
Simulation time 432455573 ps
CPU time 2.57 seconds
Started Jul 04 05:19:48 PM PDT 24
Finished Jul 04 05:19:51 PM PDT 24
Peak memory 208308 kb
Host smart-d10d9364-6da7-400d-915e-22fa077ac791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912698412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1912698412
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.418851408
Short name T404
Test name
Test status
Simulation time 195814989 ps
CPU time 1.26 seconds
Started Jul 04 05:19:48 PM PDT 24
Finished Jul 04 05:19:50 PM PDT 24
Peak memory 200048 kb
Host smart-f4484d3c-31f1-4e8d-bec9-ff752b9bdf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418851408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.418851408
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3231168861
Short name T292
Test name
Test status
Simulation time 67818929 ps
CPU time 0.77 seconds
Started Jul 04 05:19:48 PM PDT 24
Finished Jul 04 05:19:49 PM PDT 24
Peak memory 199880 kb
Host smart-28d5758b-045d-4b12-bc7d-c7b4831313f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231168861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3231168861
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3594712687
Short name T324
Test name
Test status
Simulation time 1224405782 ps
CPU time 5.27 seconds
Started Jul 04 05:19:49 PM PDT 24
Finished Jul 04 05:19:55 PM PDT 24
Peak memory 221604 kb
Host smart-ce70bee5-62b0-4281-a032-a202a54f6b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594712687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3594712687
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3215828332
Short name T198
Test name
Test status
Simulation time 244273323 ps
CPU time 1.18 seconds
Started Jul 04 05:19:47 PM PDT 24
Finished Jul 04 05:19:49 PM PDT 24
Peak memory 217368 kb
Host smart-ffa23618-33c3-4f67-9b21-1bae13cfc78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215828332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3215828332
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.106298372
Short name T21
Test name
Test status
Simulation time 170527804 ps
CPU time 0.84 seconds
Started Jul 04 05:19:49 PM PDT 24
Finished Jul 04 05:19:50 PM PDT 24
Peak memory 199828 kb
Host smart-77ee5e44-ceb1-4a90-ac28-7a3cb29be718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106298372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.106298372
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1100959065
Short name T482
Test name
Test status
Simulation time 892658827 ps
CPU time 4.36 seconds
Started Jul 04 05:19:48 PM PDT 24
Finished Jul 04 05:19:53 PM PDT 24
Peak memory 200388 kb
Host smart-fa21facc-df58-4cb5-b427-ec6da2eda155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100959065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1100959065
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.208857630
Short name T40
Test name
Test status
Simulation time 103331219 ps
CPU time 1.01 seconds
Started Jul 04 05:19:49 PM PDT 24
Finished Jul 04 05:19:50 PM PDT 24
Peak memory 200072 kb
Host smart-ad2d5b44-1a3d-43b9-bb07-175950250c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208857630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.208857630
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2918204115
Short name T470
Test name
Test status
Simulation time 203077060 ps
CPU time 1.36 seconds
Started Jul 04 05:19:49 PM PDT 24
Finished Jul 04 05:19:51 PM PDT 24
Peak memory 200236 kb
Host smart-2ff98793-61a1-4251-9995-561f47473a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918204115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2918204115
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3724959951
Short name T171
Test name
Test status
Simulation time 4984103631 ps
CPU time 18.55 seconds
Started Jul 04 05:19:49 PM PDT 24
Finished Jul 04 05:20:08 PM PDT 24
Peak memory 200344 kb
Host smart-784ec46f-4e04-4954-9b04-6a67d5d1dae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724959951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3724959951
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3982174783
Short name T270
Test name
Test status
Simulation time 397488120 ps
CPU time 2.14 seconds
Started Jul 04 05:19:49 PM PDT 24
Finished Jul 04 05:19:51 PM PDT 24
Peak memory 200100 kb
Host smart-82621583-743a-4ab0-a9b2-523bdc7fc807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982174783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3982174783
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2870432239
Short name T46
Test name
Test status
Simulation time 71039443 ps
CPU time 0.81 seconds
Started Jul 04 05:19:49 PM PDT 24
Finished Jul 04 05:19:50 PM PDT 24
Peak memory 200084 kb
Host smart-6e8bf75c-ef59-4b2a-ace1-cb25ec4b8edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870432239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2870432239
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.195504563
Short name T531
Test name
Test status
Simulation time 73790618 ps
CPU time 0.81 seconds
Started Jul 04 05:20:01 PM PDT 24
Finished Jul 04 05:20:02 PM PDT 24
Peak memory 199876 kb
Host smart-3d248a7b-75a9-4eac-9439-66e65b5209ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195504563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.195504563
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1900748496
Short name T58
Test name
Test status
Simulation time 1246533226 ps
CPU time 5.29 seconds
Started Jul 04 05:20:03 PM PDT 24
Finished Jul 04 05:20:09 PM PDT 24
Peak memory 220752 kb
Host smart-af54fdd6-3537-4a18-9ba9-9fd59024bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900748496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1900748496
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2076588641
Short name T200
Test name
Test status
Simulation time 247204163 ps
CPU time 1.07 seconds
Started Jul 04 05:20:01 PM PDT 24
Finished Jul 04 05:20:02 PM PDT 24
Peak memory 218292 kb
Host smart-d479e5ad-8ed9-4732-a2fc-f1d44943cd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076588641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2076588641
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3722839178
Short name T266
Test name
Test status
Simulation time 143827153 ps
CPU time 0.82 seconds
Started Jul 04 05:20:02 PM PDT 24
Finished Jul 04 05:20:03 PM PDT 24
Peak memory 199900 kb
Host smart-cdeec597-5b9f-40b4-8ded-325680fd8748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722839178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3722839178
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1409721310
Short name T458
Test name
Test status
Simulation time 1494499512 ps
CPU time 5.88 seconds
Started Jul 04 05:20:01 PM PDT 24
Finished Jul 04 05:20:08 PM PDT 24
Peak memory 200348 kb
Host smart-6ad77d7b-f6f8-47bc-8fb7-5f370788bcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409721310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1409721310
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2351384350
Short name T436
Test name
Test status
Simulation time 102580536 ps
CPU time 0.99 seconds
Started Jul 04 05:20:01 PM PDT 24
Finished Jul 04 05:20:02 PM PDT 24
Peak memory 200000 kb
Host smart-5b421e71-a3b4-4cd1-9b84-6de0eebba48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351384350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2351384350
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2697878292
Short name T163
Test name
Test status
Simulation time 106442008 ps
CPU time 1.17 seconds
Started Jul 04 05:19:48 PM PDT 24
Finished Jul 04 05:19:50 PM PDT 24
Peak memory 200304 kb
Host smart-58930ae8-bf59-4d9d-a9c3-77d280e26dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697878292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2697878292
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1049916758
Short name T98
Test name
Test status
Simulation time 6965385123 ps
CPU time 29.72 seconds
Started Jul 04 05:20:01 PM PDT 24
Finished Jul 04 05:20:31 PM PDT 24
Peak memory 216820 kb
Host smart-937d921c-cddd-4ec5-bb7f-68268ecfad07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049916758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1049916758
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.659383381
Short name T319
Test name
Test status
Simulation time 107239474 ps
CPU time 1.42 seconds
Started Jul 04 05:20:03 PM PDT 24
Finished Jul 04 05:20:04 PM PDT 24
Peak memory 200000 kb
Host smart-79c226a6-4424-4968-8710-636b4fdb59fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659383381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.659383381
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.476527242
Short name T362
Test name
Test status
Simulation time 253782679 ps
CPU time 1.32 seconds
Started Jul 04 05:20:02 PM PDT 24
Finished Jul 04 05:20:04 PM PDT 24
Peak memory 199984 kb
Host smart-9c58a51e-c1ba-4544-9baa-2137c6da7401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476527242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.476527242
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1336461591
Short name T138
Test name
Test status
Simulation time 64871420 ps
CPU time 0.75 seconds
Started Jul 04 05:20:01 PM PDT 24
Finished Jul 04 05:20:02 PM PDT 24
Peak memory 199880 kb
Host smart-63c5d07b-e10b-4034-bbfa-75678a137a1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336461591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1336461591
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1659644455
Short name T54
Test name
Test status
Simulation time 2354096398 ps
CPU time 8.29 seconds
Started Jul 04 05:20:07 PM PDT 24
Finished Jul 04 05:20:15 PM PDT 24
Peak memory 221564 kb
Host smart-e29cac4f-9b5c-4b83-9b56-8ad6d7b5d2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659644455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1659644455
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2099681321
Short name T380
Test name
Test status
Simulation time 243732476 ps
CPU time 1 seconds
Started Jul 04 05:20:02 PM PDT 24
Finished Jul 04 05:20:03 PM PDT 24
Peak memory 217444 kb
Host smart-0b992aeb-a1d2-457b-863c-f6e73efe2f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099681321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2099681321
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.788879322
Short name T18
Test name
Test status
Simulation time 117908464 ps
CPU time 0.8 seconds
Started Jul 04 05:20:00 PM PDT 24
Finished Jul 04 05:20:01 PM PDT 24
Peak memory 199888 kb
Host smart-8c5596e1-131b-4783-b3a4-eee4d35a70b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788879322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.788879322
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2484035263
Short name T122
Test name
Test status
Simulation time 2006413566 ps
CPU time 7.32 seconds
Started Jul 04 05:20:00 PM PDT 24
Finished Jul 04 05:20:08 PM PDT 24
Peak memory 200280 kb
Host smart-e8173182-47c1-4251-9cd3-c7b6cbab2d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484035263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2484035263
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2011613338
Short name T286
Test name
Test status
Simulation time 95950966 ps
CPU time 1 seconds
Started Jul 04 05:20:00 PM PDT 24
Finished Jul 04 05:20:02 PM PDT 24
Peak memory 200064 kb
Host smart-f3304782-fe6f-4724-b734-31840aa3687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011613338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2011613338
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2702607727
Short name T180
Test name
Test status
Simulation time 200663362 ps
CPU time 1.42 seconds
Started Jul 04 05:20:00 PM PDT 24
Finished Jul 04 05:20:02 PM PDT 24
Peak memory 200300 kb
Host smart-2655f571-d140-476e-8589-321fe39ada66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702607727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2702607727
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.4023958135
Short name T297
Test name
Test status
Simulation time 6593001013 ps
CPU time 22.41 seconds
Started Jul 04 05:20:04 PM PDT 24
Finished Jul 04 05:20:26 PM PDT 24
Peak memory 210260 kb
Host smart-2f5bffbc-d81d-4b1a-b6c4-96f76d68c1bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023958135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4023958135
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3132314333
Short name T174
Test name
Test status
Simulation time 137080279 ps
CPU time 1.95 seconds
Started Jul 04 05:20:02 PM PDT 24
Finished Jul 04 05:20:04 PM PDT 24
Peak memory 200032 kb
Host smart-06a02f6a-de1f-496d-a4dd-b2395f21cdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132314333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3132314333
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1008376019
Short name T459
Test name
Test status
Simulation time 78148774 ps
CPU time 0.83 seconds
Started Jul 04 05:20:01 PM PDT 24
Finished Jul 04 05:20:03 PM PDT 24
Peak memory 200004 kb
Host smart-028eddd3-df46-4b88-abf1-94e6c997b50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008376019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1008376019
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1402765342
Short name T211
Test name
Test status
Simulation time 74744564 ps
CPU time 0.79 seconds
Started Jul 04 05:20:08 PM PDT 24
Finished Jul 04 05:20:09 PM PDT 24
Peak memory 199900 kb
Host smart-98ab62b6-ef9f-4611-a573-d5edaa4d79ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402765342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1402765342
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1276997999
Short name T280
Test name
Test status
Simulation time 2355260208 ps
CPU time 9.2 seconds
Started Jul 04 05:20:10 PM PDT 24
Finished Jul 04 05:20:20 PM PDT 24
Peak memory 217896 kb
Host smart-660185b0-709c-44b0-b070-db0824c3b187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276997999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1276997999
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3402058443
Short name T402
Test name
Test status
Simulation time 243958766 ps
CPU time 1.06 seconds
Started Jul 04 05:20:10 PM PDT 24
Finished Jul 04 05:20:12 PM PDT 24
Peak memory 217444 kb
Host smart-d4e3877c-8e9a-41ef-8e84-772c7c840079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402058443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3402058443
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.209766716
Short name T477
Test name
Test status
Simulation time 164998856 ps
CPU time 0.88 seconds
Started Jul 04 05:20:02 PM PDT 24
Finished Jul 04 05:20:03 PM PDT 24
Peak memory 199892 kb
Host smart-7c1bebb9-692f-4f96-b327-e7b4030a1b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209766716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.209766716
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2322667576
Short name T539
Test name
Test status
Simulation time 728365025 ps
CPU time 4 seconds
Started Jul 04 05:20:01 PM PDT 24
Finished Jul 04 05:20:05 PM PDT 24
Peak memory 200376 kb
Host smart-bdd56345-63cc-42b2-a0d4-375f3db65a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322667576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2322667576
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3607403677
Short name T296
Test name
Test status
Simulation time 148993750 ps
CPU time 1.13 seconds
Started Jul 04 05:20:09 PM PDT 24
Finished Jul 04 05:20:10 PM PDT 24
Peak memory 200072 kb
Host smart-d2b3c570-f1de-4f77-9a9b-c79cea5ddb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607403677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3607403677
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1455704842
Short name T247
Test name
Test status
Simulation time 235203118 ps
CPU time 1.49 seconds
Started Jul 04 05:20:02 PM PDT 24
Finished Jul 04 05:20:04 PM PDT 24
Peak memory 200276 kb
Host smart-d58a530d-5838-4af6-8b4b-668e92eccbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455704842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1455704842
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3319171194
Short name T328
Test name
Test status
Simulation time 11408539291 ps
CPU time 40.64 seconds
Started Jul 04 05:20:10 PM PDT 24
Finished Jul 04 05:20:51 PM PDT 24
Peak memory 200532 kb
Host smart-39403627-da73-4993-9519-4e0e5a324ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319171194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3319171194
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2555481420
Short name T383
Test name
Test status
Simulation time 147359301 ps
CPU time 1.96 seconds
Started Jul 04 05:20:08 PM PDT 24
Finished Jul 04 05:20:10 PM PDT 24
Peak memory 200076 kb
Host smart-1df90ec0-7172-42a7-8638-963bb5f8bb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555481420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2555481420
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.917943176
Short name T442
Test name
Test status
Simulation time 166945554 ps
CPU time 1.24 seconds
Started Jul 04 05:20:00 PM PDT 24
Finished Jul 04 05:20:01 PM PDT 24
Peak memory 200280 kb
Host smart-572e9cbd-c2be-4203-a7a4-dc80e27aeb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917943176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.917943176
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%