Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8304

1

T3

19

T5

39

T10

21

auto[1]

11468

1

T3

82

T5

19

T6

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6016	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6654	1			T1	1		T2	1		T3	27
reset_info_cp[2]	3082	1			T3	16		T5	14		T6	1
reset_info_cp[4]	4076	1			T3	16		T5	18		T6	1
reset_info_cp[8]	115	1			T10	1		T22	1		T87	4
reset_info_cp[16]	114	1			T10	1		T23	2		T87	1
reset_info_cp[32]	112	1			T5	1		T10	2		T22	3
reset_info_cp[64]	110	1			T3	1		T10	1		T22	1
reset_info_cp[128]	113	1			T22	4		T87	1		T88	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3190	1			T3	19		T5	5		T10	21
reset_info_cp[1]	auto[1]	2844	1			T3	7		T5	3		T6	1
reset_info_cp[2]	auto[0]	983	1			T5	8		T13	6		T22	22
reset_info_cp[2]	auto[1]	2099	1			T3	16		T5	6		T6	1
reset_info_cp[4]	auto[0]	1474	1			T5	11		T13	9		T22	24
reset_info_cp[4]	auto[1]	2602	1			T3	16		T5	7		T6	1
reset_info_cp[8]	auto[0]	42	1			T87	1		T88	1		T90	1
reset_info_cp[8]	auto[1]	73	1			T10	1		T22	1		T87	3
reset_info_cp[16]	auto[0]	40	1			T88	1		T90	1		T91	1
reset_info_cp[16]	auto[1]	74	1			T10	1		T23	2		T87	1
reset_info_cp[32]	auto[0]	53	1			T5	1		T22	2		T88	1
reset_info_cp[32]	auto[1]	59	1			T10	2		T22	1		T90	2
reset_info_cp[64]	auto[0]	36	1			T23	1		T88	1		T90	1
reset_info_cp[64]	auto[1]	74	1			T3	1		T10	1		T22	1
reset_info_cp[128]	auto[0]	40	1			T22	3		T88	1		T95	1
reset_info_cp[128]	auto[1]	73	1			T22	1		T87	1		T25	1