Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T536 /workspace/coverage/default/19.rstmgr_por_stretcher.993145353 Jul 05 05:36:08 PM PDT 24 Jul 05 05:36:10 PM PDT 24 204950677 ps
T537 /workspace/coverage/default/30.rstmgr_reset.2013273353 Jul 05 05:36:23 PM PDT 24 Jul 05 05:36:29 PM PDT 24 967834177 ps
T538 /workspace/coverage/default/49.rstmgr_por_stretcher.1304855249 Jul 05 05:36:51 PM PDT 24 Jul 05 05:36:55 PM PDT 24 152776578 ps
T539 /workspace/coverage/default/12.rstmgr_smoke.2413086823 Jul 05 05:35:54 PM PDT 24 Jul 05 05:35:56 PM PDT 24 126988667 ps
T540 /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2183637422 Jul 05 05:36:05 PM PDT 24 Jul 05 05:36:07 PM PDT 24 245375120 ps
T69 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2999124018 Jul 05 04:33:34 PM PDT 24 Jul 05 04:33:38 PM PDT 24 452159461 ps
T65 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2445216157 Jul 05 04:33:11 PM PDT 24 Jul 05 04:33:16 PM PDT 24 69616960 ps
T66 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3949476715 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:20 PM PDT 24 459858318 ps
T67 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2347525510 Jul 05 04:33:17 PM PDT 24 Jul 05 04:33:23 PM PDT 24 108203211 ps
T68 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2543573623 Jul 05 04:33:30 PM PDT 24 Jul 05 04:33:34 PM PDT 24 175120572 ps
T96 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2273162913 Jul 05 04:33:16 PM PDT 24 Jul 05 04:33:22 PM PDT 24 107274670 ps
T97 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1255602152 Jul 05 04:33:32 PM PDT 24 Jul 05 04:33:36 PM PDT 24 500919685 ps
T98 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1934062940 Jul 05 04:33:11 PM PDT 24 Jul 05 04:33:15 PM PDT 24 110652963 ps
T123 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.772822697 Jul 05 04:33:35 PM PDT 24 Jul 05 04:33:37 PM PDT 24 93580245 ps
T99 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2427717396 Jul 05 04:33:37 PM PDT 24 Jul 05 04:33:40 PM PDT 24 172948697 ps
T100 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3533191158 Jul 05 04:33:24 PM PDT 24 Jul 05 04:33:30 PM PDT 24 184864497 ps
T101 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3389747153 Jul 05 04:33:13 PM PDT 24 Jul 05 04:33:20 PM PDT 24 935160734 ps
T70 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1829230097 Jul 05 04:33:12 PM PDT 24 Jul 05 04:33:18 PM PDT 24 516817343 ps
T113 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2777267926 Jul 05 04:33:20 PM PDT 24 Jul 05 04:33:27 PM PDT 24 85480010 ps
T103 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3951709016 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:21 PM PDT 24 877588069 ps
T102 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.673170078 Jul 05 04:33:17 PM PDT 24 Jul 05 04:33:26 PM PDT 24 199287377 ps
T135 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3785149353 Jul 05 04:33:18 PM PDT 24 Jul 05 04:33:26 PM PDT 24 497899868 ps
T114 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1873944256 Jul 05 04:33:16 PM PDT 24 Jul 05 04:33:22 PM PDT 24 64196062 ps
T541 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1618931149 Jul 05 04:33:02 PM PDT 24 Jul 05 04:33:05 PM PDT 24 100457242 ps
T124 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2633912777 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:20 PM PDT 24 117777571 ps
T542 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1619585146 Jul 05 04:33:20 PM PDT 24 Jul 05 04:33:28 PM PDT 24 161124946 ps
T543 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.680221794 Jul 05 04:33:27 PM PDT 24 Jul 05 04:33:32 PM PDT 24 90072128 ps
T544 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2751390797 Jul 05 04:33:15 PM PDT 24 Jul 05 04:33:20 PM PDT 24 104902051 ps
T545 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.523865031 Jul 05 04:33:27 PM PDT 24 Jul 05 04:33:34 PM PDT 24 474078539 ps
T546 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3613007901 Jul 05 04:33:16 PM PDT 24 Jul 05 04:33:22 PM PDT 24 156446815 ps
T547 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1853323833 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:19 PM PDT 24 136495174 ps
T125 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3201075656 Jul 05 04:33:18 PM PDT 24 Jul 05 04:33:27 PM PDT 24 773822340 ps
T548 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2021814087 Jul 05 04:33:35 PM PDT 24 Jul 05 04:33:39 PM PDT 24 130698854 ps
T115 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.47609431 Jul 05 04:33:13 PM PDT 24 Jul 05 04:33:19 PM PDT 24 282277966 ps
T549 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4028443103 Jul 05 04:33:24 PM PDT 24 Jul 05 04:33:34 PM PDT 24 799254240 ps
T137 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1873779417 Jul 05 04:33:17 PM PDT 24 Jul 05 04:33:24 PM PDT 24 501568232 ps
T116 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.550579118 Jul 05 04:33:18 PM PDT 24 Jul 05 04:33:25 PM PDT 24 62872467 ps
T117 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2484869239 Jul 05 04:33:17 PM PDT 24 Jul 05 04:33:24 PM PDT 24 229916599 ps
T118 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.118280149 Jul 05 04:33:10 PM PDT 24 Jul 05 04:33:13 PM PDT 24 74873231 ps
T550 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.659543171 Jul 05 04:33:16 PM PDT 24 Jul 05 04:33:22 PM PDT 24 113166469 ps
T551 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2421642307 Jul 05 04:33:27 PM PDT 24 Jul 05 04:33:33 PM PDT 24 193498016 ps
T119 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2496442441 Jul 05 04:33:21 PM PDT 24 Jul 05 04:33:27 PM PDT 24 94909883 ps
T552 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3466875493 Jul 05 04:33:15 PM PDT 24 Jul 05 04:33:21 PM PDT 24 124856441 ps
T553 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3286590144 Jul 05 04:33:20 PM PDT 24 Jul 05 04:33:28 PM PDT 24 191106903 ps
T120 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.630415823 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:18 PM PDT 24 60657592 ps
T554 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4174222788 Jul 05 04:33:22 PM PDT 24 Jul 05 04:33:30 PM PDT 24 153648139 ps
T555 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2174004881 Jul 05 04:33:19 PM PDT 24 Jul 05 04:33:28 PM PDT 24 154030325 ps
T556 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.342769935 Jul 05 04:33:12 PM PDT 24 Jul 05 04:33:17 PM PDT 24 91409601 ps
T557 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.209264393 Jul 05 04:33:25 PM PDT 24 Jul 05 04:33:31 PM PDT 24 170195097 ps
T128 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3450748369 Jul 05 04:33:25 PM PDT 24 Jul 05 04:33:32 PM PDT 24 496913103 ps
T121 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.457375764 Jul 05 04:33:24 PM PDT 24 Jul 05 04:33:30 PM PDT 24 145943997 ps
T558 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2708772843 Jul 05 04:33:18 PM PDT 24 Jul 05 04:33:28 PM PDT 24 534830344 ps
T122 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3093652676 Jul 05 04:33:05 PM PDT 24 Jul 05 04:33:08 PM PDT 24 59786814 ps
T559 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1552333580 Jul 05 04:33:19 PM PDT 24 Jul 05 04:33:26 PM PDT 24 124899854 ps
T560 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3902112644 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:20 PM PDT 24 505000718 ps
T561 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.759361357 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:19 PM PDT 24 245789330 ps
T138 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1089642568 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:21 PM PDT 24 772542348 ps
T562 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1934595682 Jul 05 04:33:33 PM PDT 24 Jul 05 04:33:38 PM PDT 24 425373249 ps
T563 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3075327874 Jul 05 04:33:11 PM PDT 24 Jul 05 04:33:20 PM PDT 24 1168120490 ps
T564 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1216219300 Jul 05 04:33:05 PM PDT 24 Jul 05 04:33:08 PM PDT 24 249986570 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2422975792 Jul 05 04:33:22 PM PDT 24 Jul 05 04:33:29 PM PDT 24 161362914 ps
T566 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2962092400 Jul 05 04:33:07 PM PDT 24 Jul 05 04:33:12 PM PDT 24 424784355 ps
T567 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1247614306 Jul 05 04:33:16 PM PDT 24 Jul 05 04:33:22 PM PDT 24 194450340 ps
T568 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1264604616 Jul 05 04:33:26 PM PDT 24 Jul 05 04:33:32 PM PDT 24 116039359 ps
T569 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2748427428 Jul 05 04:33:10 PM PDT 24 Jul 05 04:33:14 PM PDT 24 119580255 ps
T570 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3099727763 Jul 05 04:33:08 PM PDT 24 Jul 05 04:33:12 PM PDT 24 180535149 ps
T571 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.963774677 Jul 05 04:33:29 PM PDT 24 Jul 05 04:33:33 PM PDT 24 78480897 ps
T572 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1504906013 Jul 05 04:33:15 PM PDT 24 Jul 05 04:33:19 PM PDT 24 128025346 ps
T573 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3018989359 Jul 05 04:33:17 PM PDT 24 Jul 05 04:33:25 PM PDT 24 414195593 ps
T574 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2254460798 Jul 05 04:33:07 PM PDT 24 Jul 05 04:33:12 PM PDT 24 170664861 ps
T575 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4163307798 Jul 05 04:33:16 PM PDT 24 Jul 05 04:33:22 PM PDT 24 133749322 ps
T576 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4180019417 Jul 05 04:33:24 PM PDT 24 Jul 05 04:33:30 PM PDT 24 73284791 ps
T577 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1521535322 Jul 05 04:33:28 PM PDT 24 Jul 05 04:33:33 PM PDT 24 128700395 ps
T578 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.752453717 Jul 05 04:33:22 PM PDT 24 Jul 05 04:33:29 PM PDT 24 65528226 ps
T579 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1905392216 Jul 05 04:33:21 PM PDT 24 Jul 05 04:33:29 PM PDT 24 145946735 ps
T580 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1555486206 Jul 05 04:33:08 PM PDT 24 Jul 05 04:33:13 PM PDT 24 772368173 ps
T127 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3558712049 Jul 05 04:33:25 PM PDT 24 Jul 05 04:33:32 PM PDT 24 425910725 ps
T581 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1123516387 Jul 05 04:33:22 PM PDT 24 Jul 05 04:33:29 PM PDT 24 135531285 ps
T582 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3966099115 Jul 05 04:33:17 PM PDT 24 Jul 05 04:33:23 PM PDT 24 92987047 ps
T583 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2031024110 Jul 05 04:33:11 PM PDT 24 Jul 05 04:33:18 PM PDT 24 362204462 ps
T584 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.212347845 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:19 PM PDT 24 74081590 ps
T585 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.448739152 Jul 05 04:33:08 PM PDT 24 Jul 05 04:33:12 PM PDT 24 127525411 ps
T129 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3632915363 Jul 05 04:33:15 PM PDT 24 Jul 05 04:33:22 PM PDT 24 899867185 ps
T136 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3532189800 Jul 05 04:33:21 PM PDT 24 Jul 05 04:33:30 PM PDT 24 1017660706 ps
T586 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4258608383 Jul 05 04:33:09 PM PDT 24 Jul 05 04:33:13 PM PDT 24 114121950 ps
T587 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3208289806 Jul 05 04:33:07 PM PDT 24 Jul 05 04:33:10 PM PDT 24 95855894 ps
T588 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2439840555 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:19 PM PDT 24 125698036 ps
T589 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1509950247 Jul 05 04:33:15 PM PDT 24 Jul 05 04:33:22 PM PDT 24 943236859 ps
T590 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3611884437 Jul 05 04:33:34 PM PDT 24 Jul 05 04:33:36 PM PDT 24 176498488 ps
T591 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2662107241 Jul 05 04:33:18 PM PDT 24 Jul 05 04:33:26 PM PDT 24 147105975 ps
T592 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4233049350 Jul 05 04:33:15 PM PDT 24 Jul 05 04:33:20 PM PDT 24 196908011 ps
T593 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2014250656 Jul 05 04:33:05 PM PDT 24 Jul 05 04:33:08 PM PDT 24 68942597 ps
T594 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1122334550 Jul 05 04:33:27 PM PDT 24 Jul 05 04:33:33 PM PDT 24 111370663 ps
T595 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2829490439 Jul 05 04:33:35 PM PDT 24 Jul 05 04:33:42 PM PDT 24 137458446 ps
T596 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2436284835 Jul 05 04:33:12 PM PDT 24 Jul 05 04:33:19 PM PDT 24 775027272 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.472774364 Jul 05 04:33:10 PM PDT 24 Jul 05 04:33:13 PM PDT 24 132370958 ps
T598 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1090016376 Jul 05 04:33:13 PM PDT 24 Jul 05 04:33:18 PM PDT 24 246866191 ps
T599 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3898279653 Jul 05 04:33:13 PM PDT 24 Jul 05 04:33:18 PM PDT 24 128245000 ps
T600 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4187842703 Jul 05 04:33:22 PM PDT 24 Jul 05 04:33:29 PM PDT 24 65274713 ps
T601 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2195970414 Jul 05 04:33:16 PM PDT 24 Jul 05 04:33:22 PM PDT 24 187661893 ps
T602 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2434121479 Jul 05 04:33:15 PM PDT 24 Jul 05 04:33:21 PM PDT 24 435661795 ps
T603 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2669324818 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:20 PM PDT 24 147989863 ps
T604 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2914929263 Jul 05 04:33:27 PM PDT 24 Jul 05 04:33:33 PM PDT 24 91243546 ps
T605 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2332791582 Jul 05 04:33:19 PM PDT 24 Jul 05 04:33:26 PM PDT 24 74074052 ps
T606 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2032913555 Jul 05 04:33:07 PM PDT 24 Jul 05 04:33:10 PM PDT 24 68370809 ps
T607 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1725783085 Jul 05 04:33:20 PM PDT 24 Jul 05 04:33:27 PM PDT 24 125486387 ps
T126 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.921622677 Jul 05 04:33:12 PM PDT 24 Jul 05 04:33:20 PM PDT 24 977376855 ps
T608 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.8041325 Jul 05 04:33:38 PM PDT 24 Jul 05 04:33:42 PM PDT 24 884875760 ps
T609 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.799842612 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:20 PM PDT 24 208694643 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2607145294 Jul 05 04:33:17 PM PDT 24 Jul 05 04:33:29 PM PDT 24 489114577 ps
T611 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3952673402 Jul 05 04:33:22 PM PDT 24 Jul 05 04:33:29 PM PDT 24 134568757 ps
T612 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3486857418 Jul 05 04:33:13 PM PDT 24 Jul 05 04:33:18 PM PDT 24 113611480 ps
T613 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.864358264 Jul 05 04:33:19 PM PDT 24 Jul 05 04:33:26 PM PDT 24 82077218 ps
T614 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3983273054 Jul 05 04:33:36 PM PDT 24 Jul 05 04:33:39 PM PDT 24 216042209 ps
T615 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2536838012 Jul 05 04:33:08 PM PDT 24 Jul 05 04:33:16 PM PDT 24 486864606 ps
T616 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2923874139 Jul 05 04:33:11 PM PDT 24 Jul 05 04:33:18 PM PDT 24 462493235 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3686402998 Jul 05 04:33:11 PM PDT 24 Jul 05 04:33:15 PM PDT 24 93242709 ps
T618 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.87477199 Jul 05 04:33:07 PM PDT 24 Jul 05 04:33:10 PM PDT 24 64662807 ps
T619 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2297918606 Jul 05 04:33:15 PM PDT 24 Jul 05 04:33:21 PM PDT 24 319947151 ps
T620 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1520500268 Jul 05 04:33:15 PM PDT 24 Jul 05 04:33:24 PM PDT 24 1176506468 ps

Test location /workspace/coverage/default/15.rstmgr_reset.2686567148
Short name T5
Test name
Test status
Simulation time 1207239605 ps
CPU time 5.34 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:14 PM PDT 24
Peak memory 200412 kb
Host smart-7595360b-4ecf-4965-9f22-355f755c9226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686567148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2686567148
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3536320079
Short name T89
Test name
Test status
Simulation time 384193534 ps
CPU time 2.07 seconds
Started Jul 05 05:36:30 PM PDT 24
Finished Jul 05 05:36:33 PM PDT 24
Peak memory 200160 kb
Host smart-e321c557-9d61-4937-ab3e-7ad22cc00836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536320079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3536320079
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3659896387
Short name T88
Test name
Test status
Simulation time 10749067059 ps
CPU time 35.5 seconds
Started Jul 05 05:35:52 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 200536 kb
Host smart-dac8cf41-7e49-40cd-9ae6-95f214bfb9fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659896387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3659896387
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2543573623
Short name T68
Test name
Test status
Simulation time 175120572 ps
CPU time 1.66 seconds
Started Jul 05 04:33:30 PM PDT 24
Finished Jul 05 04:33:34 PM PDT 24
Peak memory 208724 kb
Host smart-f4ba4fd2-0e17-4152-b5a5-3483472dce1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543573623 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2543573623
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3258351185
Short name T76
Test name
Test status
Simulation time 8450720697 ps
CPU time 13.47 seconds
Started Jul 05 05:35:32 PM PDT 24
Finished Jul 05 05:35:46 PM PDT 24
Peak memory 217120 kb
Host smart-915e34e9-3eae-4eb6-bdf6-44311272aa49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258351185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3258351185
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2989185819
Short name T10
Test name
Test status
Simulation time 2171247181 ps
CPU time 7.64 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:59 PM PDT 24
Peak memory 221692 kb
Host smart-8960a352-ad61-4641-895f-ad6a921b734d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989185819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2989185819
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3951709016
Short name T103
Test name
Test status
Simulation time 877588069 ps
CPU time 2.95 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:21 PM PDT 24
Peak memory 200352 kb
Host smart-35b89ac1-5b4e-4be4-a570-9d601d8df19c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951709016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3951709016
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1469278345
Short name T9
Test name
Test status
Simulation time 76732589 ps
CPU time 0.8 seconds
Started Jul 05 05:36:04 PM PDT 24
Finished Jul 05 05:36:05 PM PDT 24
Peak memory 199960 kb
Host smart-8249d295-0f38-47b7-91e3-4c80171db44f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469278345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1469278345
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3874069778
Short name T48
Test name
Test status
Simulation time 145736300 ps
CPU time 1.17 seconds
Started Jul 05 05:35:48 PM PDT 24
Finished Jul 05 05:35:51 PM PDT 24
Peak memory 200160 kb
Host smart-cdcbe5aa-f154-4b71-a1a6-4ad9b7dddaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874069778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3874069778
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3044124165
Short name T25
Test name
Test status
Simulation time 1878251007 ps
CPU time 7.24 seconds
Started Jul 05 05:35:48 PM PDT 24
Finished Jul 05 05:35:57 PM PDT 24
Peak memory 221716 kb
Host smart-1f8b7aef-4c53-42de-98cf-e554e5cb56b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044124165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3044124165
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2021814087
Short name T548
Test name
Test status
Simulation time 130698854 ps
CPU time 1.8 seconds
Started Jul 05 04:33:35 PM PDT 24
Finished Jul 05 04:33:39 PM PDT 24
Peak memory 211084 kb
Host smart-24c13cfe-26ec-4115-bd63-db0411fb472f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021814087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2021814087
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.9946940
Short name T87
Test name
Test status
Simulation time 6729508560 ps
CPU time 30.18 seconds
Started Jul 05 05:35:57 PM PDT 24
Finished Jul 05 05:36:28 PM PDT 24
Peak memory 208700 kb
Host smart-b66c7738-57f2-46a4-8bc3-9b6e571b575c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9946940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.9946940
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3558712049
Short name T127
Test name
Test status
Simulation time 425910725 ps
CPU time 1.94 seconds
Started Jul 05 04:33:25 PM PDT 24
Finished Jul 05 04:33:32 PM PDT 24
Peak memory 200504 kb
Host smart-ff67bea8-1976-4d04-a9d0-11ee534e5d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558712049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3558712049
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1427267235
Short name T44
Test name
Test status
Simulation time 1230454095 ps
CPU time 5.55 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:49 PM PDT 24
Peak memory 217484 kb
Host smart-58971368-43fb-4b9a-b0c8-6f577afce129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427267235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1427267235
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.61750783
Short name T195
Test name
Test status
Simulation time 243415578 ps
CPU time 1.33 seconds
Started Jul 05 05:35:55 PM PDT 24
Finished Jul 05 05:35:57 PM PDT 24
Peak memory 200072 kb
Host smart-10f77fe6-cdc6-4a51-a969-7ca08a723773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61750783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.61750783
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.630415823
Short name T120
Test name
Test status
Simulation time 60657592 ps
CPU time 0.8 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:18 PM PDT 24
Peak memory 200244 kb
Host smart-4d83d683-287b-4c9f-baf4-86d116866253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630415823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.630415823
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2991367637
Short name T17
Test name
Test status
Simulation time 206781313 ps
CPU time 0.9 seconds
Started Jul 05 05:35:33 PM PDT 24
Finished Jul 05 05:35:35 PM PDT 24
Peak memory 199968 kb
Host smart-ea0ef602-ed94-45fd-8178-2da6ec075274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991367637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2991367637
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3430107757
Short name T153
Test name
Test status
Simulation time 243439523 ps
CPU time 1.1 seconds
Started Jul 05 05:36:01 PM PDT 24
Finished Jul 05 05:36:03 PM PDT 24
Peak memory 217564 kb
Host smart-3813e75a-5b78-4b3f-9c6b-a8801437b1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430107757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3430107757
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2436284835
Short name T596
Test name
Test status
Simulation time 775027272 ps
CPU time 3.05 seconds
Started Jul 05 04:33:12 PM PDT 24
Finished Jul 05 04:33:19 PM PDT 24
Peak memory 200360 kb
Host smart-1cb17232-3a29-402a-99e0-7490925c08c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436284835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2436284835
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.523865031
Short name T545
Test name
Test status
Simulation time 474078539 ps
CPU time 2.92 seconds
Started Jul 05 04:33:27 PM PDT 24
Finished Jul 05 04:33:34 PM PDT 24
Peak memory 200424 kb
Host smart-e291e79f-77f7-4aec-9ac8-1e809a27fd1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523865031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.523865031
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3075327874
Short name T563
Test name
Test status
Simulation time 1168120490 ps
CPU time 5.42 seconds
Started Jul 05 04:33:11 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 200376 kb
Host smart-efb8afd8-b868-4150-94ae-f7c0e936b3cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075327874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
075327874
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2748427428
Short name T569
Test name
Test status
Simulation time 119580255 ps
CPU time 0.89 seconds
Started Jul 05 04:33:10 PM PDT 24
Finished Jul 05 04:33:14 PM PDT 24
Peak memory 200260 kb
Host smart-2d28163b-8198-490e-a58f-6bd08675595c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748427428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
748427428
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1618931149
Short name T541
Test name
Test status
Simulation time 100457242 ps
CPU time 0.92 seconds
Started Jul 05 04:33:02 PM PDT 24
Finished Jul 05 04:33:05 PM PDT 24
Peak memory 200220 kb
Host smart-5e40a5f9-4f46-450b-870d-18d6ec44d587
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618931149 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1618931149
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2032913555
Short name T606
Test name
Test status
Simulation time 68370809 ps
CPU time 0.78 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:33:10 PM PDT 24
Peak memory 200120 kb
Host smart-785fdc2c-62b2-4ba6-b1d1-95601e10d953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032913555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2032913555
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1216219300
Short name T564
Test name
Test status
Simulation time 249986570 ps
CPU time 1.47 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:33:08 PM PDT 24
Peak memory 208504 kb
Host smart-78ff7e5d-aca0-463d-8f8d-e7c0d8eaf086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216219300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1216219300
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1905392216
Short name T579
Test name
Test status
Simulation time 145946735 ps
CPU time 2.16 seconds
Started Jul 05 04:33:21 PM PDT 24
Finished Jul 05 04:33:29 PM PDT 24
Peak memory 208572 kb
Host smart-d8b51ec4-b5f7-4d6b-9c0b-c6e17d45083f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905392216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1905392216
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1829230097
Short name T70
Test name
Test status
Simulation time 516817343 ps
CPU time 1.95 seconds
Started Jul 05 04:33:12 PM PDT 24
Finished Jul 05 04:33:18 PM PDT 24
Peak memory 200348 kb
Host smart-758d9586-1ed5-46cd-aa6b-c3b34eeed51b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829230097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1829230097
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2031024110
Short name T583
Test name
Test status
Simulation time 362204462 ps
CPU time 2.38 seconds
Started Jul 05 04:33:11 PM PDT 24
Finished Jul 05 04:33:18 PM PDT 24
Peak memory 208656 kb
Host smart-3ff2a8c1-d964-4d04-99d5-7840c0dec6f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031024110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
031024110
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1520500268
Short name T620
Test name
Test status
Simulation time 1176506468 ps
CPU time 5.11 seconds
Started Jul 05 04:33:15 PM PDT 24
Finished Jul 05 04:33:24 PM PDT 24
Peak memory 200396 kb
Host smart-06de5c96-b4e6-4bb1-b92c-13595b679301
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520500268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
520500268
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3208289806
Short name T587
Test name
Test status
Simulation time 95855894 ps
CPU time 0.89 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:33:10 PM PDT 24
Peak memory 200136 kb
Host smart-a9522d36-1387-450b-82bb-7ebdf824eb48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208289806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
208289806
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1853323833
Short name T547
Test name
Test status
Simulation time 136495174 ps
CPU time 1.06 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:19 PM PDT 24
Peak memory 209588 kb
Host smart-268a1f44-9767-42bc-97bc-383add2eb5b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853323833 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1853323833
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2445216157
Short name T65
Test name
Test status
Simulation time 69616960 ps
CPU time 0.76 seconds
Started Jul 05 04:33:11 PM PDT 24
Finished Jul 05 04:33:16 PM PDT 24
Peak memory 200120 kb
Host smart-dadb6529-27d9-433e-aaf7-4d4ec2b4c904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445216157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2445216157
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3486857418
Short name T612
Test name
Test status
Simulation time 113611480 ps
CPU time 1.25 seconds
Started Jul 05 04:33:13 PM PDT 24
Finished Jul 05 04:33:18 PM PDT 24
Peak memory 208492 kb
Host smart-d7fe7ed4-9853-4473-a53b-6be6ca79bd83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486857418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3486857418
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2254460798
Short name T574
Test name
Test status
Simulation time 170664861 ps
CPU time 2.36 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:33:12 PM PDT 24
Peak memory 208448 kb
Host smart-27d194a0-ccfe-464a-bdfb-0a0ce5b36b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254460798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2254460798
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.799842612
Short name T609
Test name
Test status
Simulation time 208694643 ps
CPU time 2.04 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 208748 kb
Host smart-17694ba5-73ef-4e5e-b43f-79d95d11cdbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799842612 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.799842612
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2914929263
Short name T604
Test name
Test status
Simulation time 91243546 ps
CPU time 1.01 seconds
Started Jul 05 04:33:27 PM PDT 24
Finished Jul 05 04:33:33 PM PDT 24
Peak memory 200176 kb
Host smart-ff552644-e5cb-442b-9a92-bd40e4463080
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914929263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2914929263
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.673170078
Short name T102
Test name
Test status
Simulation time 199287377 ps
CPU time 2.94 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:26 PM PDT 24
Peak memory 208672 kb
Host smart-f3983fa3-e182-4d88-a934-e0bab5221cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673170078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.673170078
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3450748369
Short name T128
Test name
Test status
Simulation time 496913103 ps
CPU time 1.97 seconds
Started Jul 05 04:33:25 PM PDT 24
Finished Jul 05 04:33:32 PM PDT 24
Peak memory 200712 kb
Host smart-b6ace399-c362-4189-8b08-1aba3ab5a630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450748369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3450748369
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2195970414
Short name T601
Test name
Test status
Simulation time 187661893 ps
CPU time 1.81 seconds
Started Jul 05 04:33:16 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 213700 kb
Host smart-f5dd6854-fa3b-4283-a111-a37cc49e5731
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195970414 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2195970414
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2496442441
Short name T119
Test name
Test status
Simulation time 94909883 ps
CPU time 0.84 seconds
Started Jul 05 04:33:21 PM PDT 24
Finished Jul 05 04:33:27 PM PDT 24
Peak memory 200172 kb
Host smart-b9781560-e9ff-4157-9b12-7a7de28aa31f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496442441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2496442441
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1504906013
Short name T572
Test name
Test status
Simulation time 128025346 ps
CPU time 1.07 seconds
Started Jul 05 04:33:15 PM PDT 24
Finished Jul 05 04:33:19 PM PDT 24
Peak memory 200320 kb
Host smart-2b4cf029-1185-4e9e-ade3-72933db1f756
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504906013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1504906013
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2427717396
Short name T99
Test name
Test status
Simulation time 172948697 ps
CPU time 2.38 seconds
Started Jul 05 04:33:37 PM PDT 24
Finished Jul 05 04:33:40 PM PDT 24
Peak memory 208560 kb
Host smart-3172378e-512d-477b-9297-f058c9d5b6fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427717396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2427717396
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1255602152
Short name T97
Test name
Test status
Simulation time 500919685 ps
CPU time 1.95 seconds
Started Jul 05 04:33:32 PM PDT 24
Finished Jul 05 04:33:36 PM PDT 24
Peak memory 200448 kb
Host smart-19348f04-6ff3-4aa0-afda-e1c6555ed286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255602152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1255602152
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3099727763
Short name T570
Test name
Test status
Simulation time 180535149 ps
CPU time 1.25 seconds
Started Jul 05 04:33:08 PM PDT 24
Finished Jul 05 04:33:12 PM PDT 24
Peak memory 200360 kb
Host smart-4070f529-9248-43da-a026-24bf657f0440
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099727763 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3099727763
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.212347845
Short name T584
Test name
Test status
Simulation time 74081590 ps
CPU time 0.84 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:19 PM PDT 24
Peak memory 200248 kb
Host smart-04be82c4-489e-4bc6-828d-e802373d1d58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212347845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.212347845
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2439840555
Short name T588
Test name
Test status
Simulation time 125698036 ps
CPU time 1.25 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:19 PM PDT 24
Peak memory 200332 kb
Host smart-b7e96120-14c4-4463-a886-e45041707907
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439840555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2439840555
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4174222788
Short name T554
Test name
Test status
Simulation time 153648139 ps
CPU time 2.25 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 04:33:30 PM PDT 24
Peak memory 208504 kb
Host smart-10d63206-7e22-4602-8178-5e660fafac92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174222788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.4174222788
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2434121479
Short name T602
Test name
Test status
Simulation time 435661795 ps
CPU time 1.77 seconds
Started Jul 05 04:33:15 PM PDT 24
Finished Jul 05 04:33:21 PM PDT 24
Peak memory 200512 kb
Host smart-c93962e9-ceec-4f49-8747-492e3cfad052
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434121479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2434121479
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2347525510
Short name T67
Test name
Test status
Simulation time 108203211 ps
CPU time 0.95 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:23 PM PDT 24
Peak memory 200272 kb
Host smart-352ecbe0-8075-416d-a874-f994bc67e028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347525510 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2347525510
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.550579118
Short name T116
Test name
Test status
Simulation time 62872467 ps
CPU time 0.78 seconds
Started Jul 05 04:33:18 PM PDT 24
Finished Jul 05 04:33:25 PM PDT 24
Peak memory 200272 kb
Host smart-515de5db-5f93-461a-86a8-c40b1c055eaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550579118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.550579118
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.963774677
Short name T571
Test name
Test status
Simulation time 78480897 ps
CPU time 1 seconds
Started Jul 05 04:33:29 PM PDT 24
Finished Jul 05 04:33:33 PM PDT 24
Peak memory 200200 kb
Host smart-73280fa2-d10c-4c3f-a883-99c3603e4299
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963774677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.963774677
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3201075656
Short name T125
Test name
Test status
Simulation time 773822340 ps
CPU time 2.91 seconds
Started Jul 05 04:33:18 PM PDT 24
Finished Jul 05 04:33:27 PM PDT 24
Peak memory 200404 kb
Host smart-3622ca47-6ae8-472b-97ce-bc90984647e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201075656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3201075656
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3533191158
Short name T100
Test name
Test status
Simulation time 184864497 ps
CPU time 1.2 seconds
Started Jul 05 04:33:24 PM PDT 24
Finished Jul 05 04:33:30 PM PDT 24
Peak memory 208464 kb
Host smart-92f782ba-e430-445b-a327-46b22ae91fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533191158 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3533191158
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3966099115
Short name T582
Test name
Test status
Simulation time 92987047 ps
CPU time 0.9 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:23 PM PDT 24
Peak memory 200280 kb
Host smart-f2d1bcbf-f8ad-4402-9dc4-c75a4c9d6977
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966099115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3966099115
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1552333580
Short name T559
Test name
Test status
Simulation time 124899854 ps
CPU time 1.09 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 04:33:26 PM PDT 24
Peak memory 200236 kb
Host smart-deaf5090-ae3a-4323-8abb-c2b567b049b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552333580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1552333580
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3466875493
Short name T552
Test name
Test status
Simulation time 124856441 ps
CPU time 1.61 seconds
Started Jul 05 04:33:15 PM PDT 24
Finished Jul 05 04:33:21 PM PDT 24
Peak memory 216568 kb
Host smart-f7e7a15b-4c5f-4dce-933b-51622608c2cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466875493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3466875493
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.8041325
Short name T608
Test name
Test status
Simulation time 884875760 ps
CPU time 3.01 seconds
Started Jul 05 04:33:38 PM PDT 24
Finished Jul 05 04:33:42 PM PDT 24
Peak memory 200488 kb
Host smart-14933c5e-f21b-43bd-9b91-d070698bf765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8041325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.8041325
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1247614306
Short name T567
Test name
Test status
Simulation time 194450340 ps
CPU time 1.95 seconds
Started Jul 05 04:33:16 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 208688 kb
Host smart-83e89538-9de9-45c2-aabc-9d0d9b20349d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247614306 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1247614306
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.752453717
Short name T578
Test name
Test status
Simulation time 65528226 ps
CPU time 0.82 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 04:33:29 PM PDT 24
Peak memory 200168 kb
Host smart-60a889fc-e2f7-4532-b2ec-f123e6939221
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752453717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.752453717
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4163307798
Short name T575
Test name
Test status
Simulation time 133749322 ps
CPU time 1.05 seconds
Started Jul 05 04:33:16 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 200584 kb
Host smart-d0c9e738-4c09-4cd4-a484-cc9d653c99cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163307798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.4163307798
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1122334550
Short name T594
Test name
Test status
Simulation time 111370663 ps
CPU time 1.55 seconds
Started Jul 05 04:33:27 PM PDT 24
Finished Jul 05 04:33:33 PM PDT 24
Peak memory 200340 kb
Host smart-24aba30d-c3a5-4576-a5f2-1b91f82a6f98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122334550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1122334550
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.209264393
Short name T557
Test name
Test status
Simulation time 170195097 ps
CPU time 1.15 seconds
Started Jul 05 04:33:25 PM PDT 24
Finished Jul 05 04:33:31 PM PDT 24
Peak memory 208592 kb
Host smart-c97e4220-3cc7-4c78-8402-d2bd38bfcd0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209264393 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.209264393
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2332791582
Short name T605
Test name
Test status
Simulation time 74074052 ps
CPU time 0.77 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 04:33:26 PM PDT 24
Peak memory 200188 kb
Host smart-6307e05d-4500-45dd-a8a7-9111d5eebaaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332791582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2332791582
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1725783085
Short name T607
Test name
Test status
Simulation time 125486387 ps
CPU time 1.13 seconds
Started Jul 05 04:33:20 PM PDT 24
Finished Jul 05 04:33:27 PM PDT 24
Peak memory 200288 kb
Host smart-d39336d1-9cb2-4df2-86f7-199b8ff14c22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725783085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1725783085
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2174004881
Short name T555
Test name
Test status
Simulation time 154030325 ps
CPU time 2.22 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 04:33:28 PM PDT 24
Peak memory 208476 kb
Host smart-1005042c-6873-4817-9122-726990d6baca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174004881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2174004881
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3902112644
Short name T560
Test name
Test status
Simulation time 505000718 ps
CPU time 1.84 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 200492 kb
Host smart-c7f66f64-8c55-4e72-b15e-96bb6de0a208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902112644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3902112644
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.659543171
Short name T550
Test name
Test status
Simulation time 113166469 ps
CPU time 0.94 seconds
Started Jul 05 04:33:16 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 200272 kb
Host smart-048e25ea-651b-4c26-b219-b6ee009af489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659543171 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.659543171
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.680221794
Short name T543
Test name
Test status
Simulation time 90072128 ps
CPU time 0.85 seconds
Started Jul 05 04:33:27 PM PDT 24
Finished Jul 05 04:33:32 PM PDT 24
Peak memory 200208 kb
Host smart-17580272-794b-4d7f-b559-1e1a560fb7b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680221794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.680221794
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.448739152
Short name T585
Test name
Test status
Simulation time 127525411 ps
CPU time 1.22 seconds
Started Jul 05 04:33:08 PM PDT 24
Finished Jul 05 04:33:12 PM PDT 24
Peak memory 200420 kb
Host smart-beeef944-8e5e-45d2-ac0f-337574cabb37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448739152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.448739152
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2421642307
Short name T551
Test name
Test status
Simulation time 193498016 ps
CPU time 1.57 seconds
Started Jul 05 04:33:27 PM PDT 24
Finished Jul 05 04:33:33 PM PDT 24
Peak memory 200208 kb
Host smart-67a5b02e-976d-4f57-a46c-858da4fa3604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421642307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2421642307
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3785149353
Short name T135
Test name
Test status
Simulation time 497899868 ps
CPU time 1.88 seconds
Started Jul 05 04:33:18 PM PDT 24
Finished Jul 05 04:33:26 PM PDT 24
Peak memory 200468 kb
Host smart-bb832a58-2657-4cce-b17f-1512a930d75b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785149353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3785149353
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1521535322
Short name T577
Test name
Test status
Simulation time 128700395 ps
CPU time 1.1 seconds
Started Jul 05 04:33:28 PM PDT 24
Finished Jul 05 04:33:33 PM PDT 24
Peak memory 200316 kb
Host smart-202e5008-9091-4c8b-8f92-b96d1dc05054
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521535322 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1521535322
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.772822697
Short name T123
Test name
Test status
Simulation time 93580245 ps
CPU time 0.85 seconds
Started Jul 05 04:33:35 PM PDT 24
Finished Jul 05 04:33:37 PM PDT 24
Peak memory 200280 kb
Host smart-f5f95de2-4c61-47e9-8a4d-c1272e12321f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772822697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.772822697
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3952673402
Short name T611
Test name
Test status
Simulation time 134568757 ps
CPU time 1.13 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 04:33:29 PM PDT 24
Peak memory 200312 kb
Host smart-01e3e970-41b0-40ed-8262-16587271d870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952673402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3952673402
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3983273054
Short name T614
Test name
Test status
Simulation time 216042209 ps
CPU time 1.87 seconds
Started Jul 05 04:33:36 PM PDT 24
Finished Jul 05 04:33:39 PM PDT 24
Peak memory 216764 kb
Host smart-738e0964-baca-478c-9190-d91770b57778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983273054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3983273054
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3949476715
Short name T66
Test name
Test status
Simulation time 459858318 ps
CPU time 1.8 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 200568 kb
Host smart-1aa3e768-6424-4e19-8c04-6c05ca99d4af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949476715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3949476715
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3286590144
Short name T553
Test name
Test status
Simulation time 191106903 ps
CPU time 1.27 seconds
Started Jul 05 04:33:20 PM PDT 24
Finished Jul 05 04:33:28 PM PDT 24
Peak memory 200424 kb
Host smart-c60f840b-deb3-4986-967c-587c11f2e69c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286590144 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3286590144
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4180019417
Short name T576
Test name
Test status
Simulation time 73284791 ps
CPU time 0.88 seconds
Started Jul 05 04:33:24 PM PDT 24
Finished Jul 05 04:33:30 PM PDT 24
Peak memory 200280 kb
Host smart-1b65f707-603c-4531-b295-e17ef45ce7ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180019417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.4180019417
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.864358264
Short name T613
Test name
Test status
Simulation time 82077218 ps
CPU time 1.1 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 04:33:26 PM PDT 24
Peak memory 200208 kb
Host smart-0c5b68d6-a84c-4ed8-883f-b6871e4f4853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864358264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.864358264
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3018989359
Short name T573
Test name
Test status
Simulation time 414195593 ps
CPU time 2.73 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:25 PM PDT 24
Peak memory 208440 kb
Host smart-e9f61e76-be1a-45b0-bb6f-b7682fce9fbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018989359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3018989359
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1873779417
Short name T137
Test name
Test status
Simulation time 501568232 ps
CPU time 2 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:24 PM PDT 24
Peak memory 200492 kb
Host smart-c5aaf074-f9dc-44c7-8c25-49704d86e9a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873779417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1873779417
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2669324818
Short name T603
Test name
Test status
Simulation time 147989863 ps
CPU time 1.82 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 200392 kb
Host smart-1a334c41-c901-4f0b-ad34-4c33846df408
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669324818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
669324818
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2536838012
Short name T615
Test name
Test status
Simulation time 486864606 ps
CPU time 5.48 seconds
Started Jul 05 04:33:08 PM PDT 24
Finished Jul 05 04:33:16 PM PDT 24
Peak memory 200424 kb
Host smart-0d9be418-36c3-4778-bfd6-c91a91d10fdb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536838012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
536838012
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2751390797
Short name T544
Test name
Test status
Simulation time 104902051 ps
CPU time 0.85 seconds
Started Jul 05 04:33:15 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 200148 kb
Host smart-eb2869cf-2692-479e-aa0d-cb923799f180
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751390797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
751390797
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1123516387
Short name T581
Test name
Test status
Simulation time 135531285 ps
CPU time 1.14 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 04:33:29 PM PDT 24
Peak memory 209036 kb
Host smart-7a5d5093-d4f7-4757-8ff1-46df69ca1c1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123516387 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1123516387
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.118280149
Short name T118
Test name
Test status
Simulation time 74873231 ps
CPU time 0.83 seconds
Started Jul 05 04:33:10 PM PDT 24
Finished Jul 05 04:33:13 PM PDT 24
Peak memory 200132 kb
Host smart-a32eedea-7188-4ac2-bcb4-445d651cb8ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118280149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.118280149
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2484869239
Short name T117
Test name
Test status
Simulation time 229916599 ps
CPU time 1.5 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:24 PM PDT 24
Peak memory 200464 kb
Host smart-888027e0-c848-47fe-8fa1-3543dea039cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484869239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2484869239
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2999124018
Short name T69
Test name
Test status
Simulation time 452159461 ps
CPU time 3.27 seconds
Started Jul 05 04:33:34 PM PDT 24
Finished Jul 05 04:33:38 PM PDT 24
Peak memory 208596 kb
Host smart-d007052b-607d-4871-9931-3d4a940457a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999124018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2999124018
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3632915363
Short name T129
Test name
Test status
Simulation time 899867185 ps
CPU time 3.02 seconds
Started Jul 05 04:33:15 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 200556 kb
Host smart-68fd96f4-7055-4ae4-8f10-c18178754449
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632915363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3632915363
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.759361357
Short name T561
Test name
Test status
Simulation time 245789330 ps
CPU time 1.57 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:19 PM PDT 24
Peak memory 200264 kb
Host smart-91e6130c-8e8a-4ee2-a385-8a292dbe58fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759361357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.759361357
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2607145294
Short name T610
Test name
Test status
Simulation time 489114577 ps
CPU time 5.53 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:29 PM PDT 24
Peak memory 200268 kb
Host smart-14b2fac1-a36d-43cf-a69b-7b407f280ed9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607145294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
607145294
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.472774364
Short name T597
Test name
Test status
Simulation time 132370958 ps
CPU time 0.89 seconds
Started Jul 05 04:33:10 PM PDT 24
Finished Jul 05 04:33:13 PM PDT 24
Peak memory 200168 kb
Host smart-82d8201d-3ad4-407b-95c0-7c1baf2adbf9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472774364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.472774364
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3611884437
Short name T590
Test name
Test status
Simulation time 176498488 ps
CPU time 1.12 seconds
Started Jul 05 04:33:34 PM PDT 24
Finished Jul 05 04:33:36 PM PDT 24
Peak memory 200428 kb
Host smart-d9060e65-2abc-4c74-a700-8c319c04ad7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611884437 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3611884437
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3686402998
Short name T617
Test name
Test status
Simulation time 93242709 ps
CPU time 0.85 seconds
Started Jul 05 04:33:11 PM PDT 24
Finished Jul 05 04:33:15 PM PDT 24
Peak memory 200276 kb
Host smart-31c6b655-f6b1-475c-b9a2-219bcd221a63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686402998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3686402998
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2422975792
Short name T565
Test name
Test status
Simulation time 161362914 ps
CPU time 1.2 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 04:33:29 PM PDT 24
Peak memory 200216 kb
Host smart-c52ab0f0-f0fe-48fb-bceb-ca070971c991
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422975792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2422975792
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2923874139
Short name T616
Test name
Test status
Simulation time 462493235 ps
CPU time 3.34 seconds
Started Jul 05 04:33:11 PM PDT 24
Finished Jul 05 04:33:18 PM PDT 24
Peak memory 212336 kb
Host smart-d708ab1a-fecd-4d61-b0ad-bb8f8efec679
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923874139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2923874139
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3389747153
Short name T101
Test name
Test status
Simulation time 935160734 ps
CPU time 3.1 seconds
Started Jul 05 04:33:13 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 200556 kb
Host smart-e671966e-605c-49a3-85ef-5564070fd921
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389747153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3389747153
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3613007901
Short name T546
Test name
Test status
Simulation time 156446815 ps
CPU time 1.95 seconds
Started Jul 05 04:33:16 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 200488 kb
Host smart-6e12d782-0196-41f8-85b2-9f7bad320d9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613007901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
613007901
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4028443103
Short name T549
Test name
Test status
Simulation time 799254240 ps
CPU time 4.4 seconds
Started Jul 05 04:33:24 PM PDT 24
Finished Jul 05 04:33:34 PM PDT 24
Peak memory 200448 kb
Host smart-27b610ca-408f-464c-9ac2-1b7617508f0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028443103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4
028443103
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3898279653
Short name T599
Test name
Test status
Simulation time 128245000 ps
CPU time 0.89 seconds
Started Jul 05 04:33:13 PM PDT 24
Finished Jul 05 04:33:18 PM PDT 24
Peak memory 200216 kb
Host smart-f6932a21-e415-48e9-bc71-34467ddd1c09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898279653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
898279653
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1619585146
Short name T542
Test name
Test status
Simulation time 161124946 ps
CPU time 1.41 seconds
Started Jul 05 04:33:20 PM PDT 24
Finished Jul 05 04:33:28 PM PDT 24
Peak memory 208464 kb
Host smart-2c3428fd-4baa-4c5d-a311-218acb516ef4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619585146 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1619585146
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1873944256
Short name T114
Test name
Test status
Simulation time 64196062 ps
CPU time 0.82 seconds
Started Jul 05 04:33:16 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 200124 kb
Host smart-1e3dd043-56b3-4be9-a10f-57508bfacdcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873944256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1873944256
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1090016376
Short name T598
Test name
Test status
Simulation time 246866191 ps
CPU time 1.62 seconds
Started Jul 05 04:33:13 PM PDT 24
Finished Jul 05 04:33:18 PM PDT 24
Peak memory 200360 kb
Host smart-a5055f79-02df-4fc2-8907-854d7647f43f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090016376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1090016376
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2708772843
Short name T558
Test name
Test status
Simulation time 534830344 ps
CPU time 3.98 seconds
Started Jul 05 04:33:18 PM PDT 24
Finished Jul 05 04:33:28 PM PDT 24
Peak memory 212596 kb
Host smart-9c2a31fc-12ab-4887-a2f9-7d289084f79c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708772843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2708772843
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1555486206
Short name T580
Test name
Test status
Simulation time 772368173 ps
CPU time 2.79 seconds
Started Jul 05 04:33:08 PM PDT 24
Finished Jul 05 04:33:13 PM PDT 24
Peak memory 200400 kb
Host smart-d3de2ff1-ef77-4127-a098-0ff792488806
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555486206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1555486206
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2829490439
Short name T595
Test name
Test status
Simulation time 137458446 ps
CPU time 1.14 seconds
Started Jul 05 04:33:35 PM PDT 24
Finished Jul 05 04:33:42 PM PDT 24
Peak memory 208508 kb
Host smart-81bd77e8-cf44-41eb-9157-8a8c8a3ddec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829490439 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2829490439
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.342769935
Short name T556
Test name
Test status
Simulation time 91409601 ps
CPU time 0.85 seconds
Started Jul 05 04:33:12 PM PDT 24
Finished Jul 05 04:33:17 PM PDT 24
Peak memory 200172 kb
Host smart-2821dc48-622e-4fe5-bb40-1447313bcfee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342769935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.342769935
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2662107241
Short name T591
Test name
Test status
Simulation time 147105975 ps
CPU time 1.21 seconds
Started Jul 05 04:33:18 PM PDT 24
Finished Jul 05 04:33:26 PM PDT 24
Peak memory 200168 kb
Host smart-af9d5014-3560-455f-a8ae-07cc849848b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662107241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2662107241
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2962092400
Short name T566
Test name
Test status
Simulation time 424784355 ps
CPU time 3.01 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:33:12 PM PDT 24
Peak memory 216604 kb
Host smart-fbd1fe6b-501d-4956-94a6-b100be175b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962092400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2962092400
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1089642568
Short name T138
Test name
Test status
Simulation time 772542348 ps
CPU time 3.04 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:21 PM PDT 24
Peak memory 208580 kb
Host smart-d93f99f5-e315-4116-8951-9842a255b2fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089642568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1089642568
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4258608383
Short name T586
Test name
Test status
Simulation time 114121950 ps
CPU time 1.16 seconds
Started Jul 05 04:33:09 PM PDT 24
Finished Jul 05 04:33:13 PM PDT 24
Peak memory 208548 kb
Host smart-4422daef-c4bf-4ca5-9f96-9fcff9396540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258608383 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.4258608383
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2014250656
Short name T593
Test name
Test status
Simulation time 68942597 ps
CPU time 0.77 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:33:08 PM PDT 24
Peak memory 200168 kb
Host smart-15b28435-406c-4d2b-884d-5056f3550427
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014250656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2014250656
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2777267926
Short name T113
Test name
Test status
Simulation time 85480010 ps
CPU time 0.99 seconds
Started Jul 05 04:33:20 PM PDT 24
Finished Jul 05 04:33:27 PM PDT 24
Peak memory 200236 kb
Host smart-7d6a03de-805d-4497-b002-528a21e2adc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777267926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2777267926
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1934062940
Short name T98
Test name
Test status
Simulation time 110652963 ps
CPU time 1.6 seconds
Started Jul 05 04:33:11 PM PDT 24
Finished Jul 05 04:33:15 PM PDT 24
Peak memory 216600 kb
Host smart-d7ecc01e-ac81-4059-b5d8-9a354769db20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934062940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1934062940
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3532189800
Short name T136
Test name
Test status
Simulation time 1017660706 ps
CPU time 3.04 seconds
Started Jul 05 04:33:21 PM PDT 24
Finished Jul 05 04:33:30 PM PDT 24
Peak memory 200384 kb
Host smart-b8e23bfc-8c9e-439d-951a-ee02ef2a8dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532189800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3532189800
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1264604616
Short name T568
Test name
Test status
Simulation time 116039359 ps
CPU time 0.96 seconds
Started Jul 05 04:33:26 PM PDT 24
Finished Jul 05 04:33:32 PM PDT 24
Peak memory 200344 kb
Host smart-23d48802-ca44-42b4-9e53-42c11ff4a784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264604616 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1264604616
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3093652676
Short name T122
Test name
Test status
Simulation time 59786814 ps
CPU time 0.77 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:33:08 PM PDT 24
Peak memory 200124 kb
Host smart-fda6d47c-6191-4693-acce-32cb8a44cf1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093652676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3093652676
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4233049350
Short name T592
Test name
Test status
Simulation time 196908011 ps
CPU time 1.36 seconds
Started Jul 05 04:33:15 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 200540 kb
Host smart-68c34512-aabf-4883-9265-7d1800d41a7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233049350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.4233049350
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2633912777
Short name T124
Test name
Test status
Simulation time 117777571 ps
CPU time 1.61 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 208572 kb
Host smart-0820637b-be1a-4904-9bf4-52fd0adcabc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633912777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2633912777
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2273162913
Short name T96
Test name
Test status
Simulation time 107274670 ps
CPU time 0.94 seconds
Started Jul 05 04:33:16 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 200268 kb
Host smart-7ab4ff51-4108-4de2-a337-19aacb72296c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273162913 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2273162913
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.87477199
Short name T618
Test name
Test status
Simulation time 64662807 ps
CPU time 0.77 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:33:10 PM PDT 24
Peak memory 200100 kb
Host smart-694276ec-fe6a-4c4a-a18c-11fea24fabaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87477199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.87477199
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.457375764
Short name T121
Test name
Test status
Simulation time 145943997 ps
CPU time 1.18 seconds
Started Jul 05 04:33:24 PM PDT 24
Finished Jul 05 04:33:30 PM PDT 24
Peak memory 200232 kb
Host smart-daeb7977-146d-4c72-9a61-7fdad1f9454f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457375764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.457375764
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1934595682
Short name T562
Test name
Test status
Simulation time 425373249 ps
CPU time 3.21 seconds
Started Jul 05 04:33:33 PM PDT 24
Finished Jul 05 04:33:38 PM PDT 24
Peak memory 216744 kb
Host smart-25327a23-5d7d-492d-9e88-6c9ef06c7601
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934595682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1934595682
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1509950247
Short name T589
Test name
Test status
Simulation time 943236859 ps
CPU time 3.05 seconds
Started Jul 05 04:33:15 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 200600 kb
Host smart-e91a4c89-82f0-4133-b00f-ba7e557ea68e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509950247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1509950247
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4187842703
Short name T600
Test name
Test status
Simulation time 65274713 ps
CPU time 0.79 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 04:33:29 PM PDT 24
Peak memory 200232 kb
Host smart-906cbc92-065d-4c61-8cf2-b7493011568d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187842703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.4187842703
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.47609431
Short name T115
Test name
Test status
Simulation time 282277966 ps
CPU time 1.76 seconds
Started Jul 05 04:33:13 PM PDT 24
Finished Jul 05 04:33:19 PM PDT 24
Peak memory 200476 kb
Host smart-0b3656a9-657f-409f-a101-0924e19511a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47609431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same
_csr_outstanding.47609431
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2297918606
Short name T619
Test name
Test status
Simulation time 319947151 ps
CPU time 2.22 seconds
Started Jul 05 04:33:15 PM PDT 24
Finished Jul 05 04:33:21 PM PDT 24
Peak memory 208528 kb
Host smart-f457d14b-7729-42f1-98c1-e3113766c0bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297918606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2297918606
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.921622677
Short name T126
Test name
Test status
Simulation time 977376855 ps
CPU time 3.05 seconds
Started Jul 05 04:33:12 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 200392 kb
Host smart-737a1d01-d983-4019-b633-a4d749484ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921622677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
921622677
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.51535753
Short name T534
Test name
Test status
Simulation time 75315507 ps
CPU time 0.82 seconds
Started Jul 05 05:35:33 PM PDT 24
Finished Jul 05 05:35:35 PM PDT 24
Peak memory 199952 kb
Host smart-4f89c5c8-9c1b-4e4c-a29e-865fec72c7c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51535753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.51535753
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3679447524
Short name T333
Test name
Test status
Simulation time 1220420890 ps
CPU time 5.57 seconds
Started Jul 05 05:35:38 PM PDT 24
Finished Jul 05 05:35:45 PM PDT 24
Peak memory 221772 kb
Host smart-2038d6c7-32d3-4616-b349-f5751f2609b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679447524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3679447524
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2562266476
Short name T244
Test name
Test status
Simulation time 244113741 ps
CPU time 1.1 seconds
Started Jul 05 05:35:33 PM PDT 24
Finished Jul 05 05:35:35 PM PDT 24
Peak memory 217492 kb
Host smart-3d51af17-4f5b-4312-8cbb-900a6e0c2673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562266476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2562266476
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1879380288
Short name T428
Test name
Test status
Simulation time 106990622 ps
CPU time 0.8 seconds
Started Jul 05 05:35:41 PM PDT 24
Finished Jul 05 05:35:42 PM PDT 24
Peak memory 199980 kb
Host smart-a10167ec-6789-450c-9293-f54380e6c414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879380288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1879380288
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1279985602
Short name T221
Test name
Test status
Simulation time 875871360 ps
CPU time 4.45 seconds
Started Jul 05 05:35:36 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 200444 kb
Host smart-33e2f32e-7064-44dc-a694-90ab339dcb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279985602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1279985602
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.4138202607
Short name T73
Test name
Test status
Simulation time 9714890332 ps
CPU time 14.75 seconds
Started Jul 05 05:35:31 PM PDT 24
Finished Jul 05 05:35:47 PM PDT 24
Peak memory 217004 kb
Host smart-ed63b100-824b-4338-b08a-31b3fde0e062
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138202607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4138202607
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3161496645
Short name T229
Test name
Test status
Simulation time 168995693 ps
CPU time 1.17 seconds
Started Jul 05 05:35:34 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 200152 kb
Host smart-d1c95270-04a9-48e4-83ec-bf0da8705047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161496645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3161496645
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1218723589
Short name T241
Test name
Test status
Simulation time 116082042 ps
CPU time 1.21 seconds
Started Jul 05 05:35:37 PM PDT 24
Finished Jul 05 05:35:39 PM PDT 24
Peak memory 200388 kb
Host smart-fc819058-20c0-4193-b166-bd4fb2937f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218723589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1218723589
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3528278178
Short name T353
Test name
Test status
Simulation time 5438986247 ps
CPU time 22.82 seconds
Started Jul 05 05:35:35 PM PDT 24
Finished Jul 05 05:35:59 PM PDT 24
Peak memory 208660 kb
Host smart-cd3411aa-1725-4d44-92c6-c2abd7290b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528278178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3528278178
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3959171467
Short name T427
Test name
Test status
Simulation time 344538461 ps
CPU time 1.94 seconds
Started Jul 05 05:35:34 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 200076 kb
Host smart-64bc83c4-2c32-4b47-98cb-4761046327df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959171467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3959171467
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3109205102
Short name T80
Test name
Test status
Simulation time 255647989 ps
CPU time 1.51 seconds
Started Jul 05 05:35:33 PM PDT 24
Finished Jul 05 05:35:35 PM PDT 24
Peak memory 200028 kb
Host smart-45972491-80ca-4ab8-9d2e-afd053b5666b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109205102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3109205102
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1103643354
Short name T308
Test name
Test status
Simulation time 65238053 ps
CPU time 0.81 seconds
Started Jul 05 05:35:33 PM PDT 24
Finished Jul 05 05:35:35 PM PDT 24
Peak memory 199888 kb
Host smart-b06dea99-a621-4513-b055-a1e9693846a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103643354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1103643354
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3030940783
Short name T54
Test name
Test status
Simulation time 2369755325 ps
CPU time 7.8 seconds
Started Jul 05 05:35:32 PM PDT 24
Finished Jul 05 05:35:40 PM PDT 24
Peak memory 221696 kb
Host smart-6a5fed41-3bd5-4a1f-a8b4-6879432dac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030940783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3030940783
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.4217671376
Short name T81
Test name
Test status
Simulation time 243788019 ps
CPU time 1.17 seconds
Started Jul 05 05:35:41 PM PDT 24
Finished Jul 05 05:35:44 PM PDT 24
Peak memory 217544 kb
Host smart-b1aa09e4-c230-4f34-9ecf-b7d168461ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217671376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.4217671376
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.320783916
Short name T376
Test name
Test status
Simulation time 2028216997 ps
CPU time 6.97 seconds
Started Jul 05 05:35:35 PM PDT 24
Finished Jul 05 05:35:43 PM PDT 24
Peak memory 200436 kb
Host smart-d1d5552e-d806-46f2-89a9-74fb2cda7d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320783916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.320783916
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.450464874
Short name T346
Test name
Test status
Simulation time 178279627 ps
CPU time 1.21 seconds
Started Jul 05 05:35:32 PM PDT 24
Finished Jul 05 05:35:34 PM PDT 24
Peak memory 200160 kb
Host smart-756e4292-b13e-4f8d-bf93-a6bfb6ba2571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450464874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.450464874
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.685518417
Short name T251
Test name
Test status
Simulation time 195034979 ps
CPU time 1.41 seconds
Started Jul 05 05:35:35 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 200368 kb
Host smart-b7e8830f-6e39-48a9-ad5a-f1586cad1c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685518417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.685518417
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1116702953
Short name T455
Test name
Test status
Simulation time 4134530499 ps
CPU time 18.16 seconds
Started Jul 05 05:35:33 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 200440 kb
Host smart-5e7ebc88-ddf3-455a-9f35-6bda38e17e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116702953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1116702953
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1107072976
Short name T210
Test name
Test status
Simulation time 118109627 ps
CPU time 1.49 seconds
Started Jul 05 05:35:36 PM PDT 24
Finished Jul 05 05:35:38 PM PDT 24
Peak memory 200180 kb
Host smart-8113c04c-267f-4d0d-b85b-7fee9ca3d79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107072976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1107072976
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.4089478899
Short name T520
Test name
Test status
Simulation time 166404471 ps
CPU time 1.08 seconds
Started Jul 05 05:35:32 PM PDT 24
Finished Jul 05 05:35:33 PM PDT 24
Peak memory 200108 kb
Host smart-96791ac1-962a-42f5-a85e-016e64a04480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089478899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.4089478899
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3448506877
Short name T318
Test name
Test status
Simulation time 74741792 ps
CPU time 0.85 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:35:51 PM PDT 24
Peak memory 199960 kb
Host smart-b624b4be-1a2f-4664-8355-52da2ab289aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448506877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3448506877
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.236785438
Short name T220
Test name
Test status
Simulation time 245028891 ps
CPU time 1.08 seconds
Started Jul 05 05:35:48 PM PDT 24
Finished Jul 05 05:35:50 PM PDT 24
Peak memory 217492 kb
Host smart-d1d7212a-1c6e-4fe9-8de7-3494a0d8cf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236785438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.236785438
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.605254692
Short name T460
Test name
Test status
Simulation time 226360181 ps
CPU time 1 seconds
Started Jul 05 05:35:51 PM PDT 24
Finished Jul 05 05:35:53 PM PDT 24
Peak memory 199880 kb
Host smart-d33711c7-97d1-4d27-ab1a-586ff7a0739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605254692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.605254692
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2773814710
Short name T344
Test name
Test status
Simulation time 1355213954 ps
CPU time 5.5 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:35:55 PM PDT 24
Peak memory 200440 kb
Host smart-00fcbadf-74db-436d-8adb-4d52878c6bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773814710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2773814710
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2143007383
Short name T395
Test name
Test status
Simulation time 125567623 ps
CPU time 1.18 seconds
Started Jul 05 05:35:51 PM PDT 24
Finished Jul 05 05:35:53 PM PDT 24
Peak memory 200372 kb
Host smart-c3b69f7d-3dbe-4fdc-8ed2-e4a81820839f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143007383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2143007383
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2048223728
Short name T230
Test name
Test status
Simulation time 6045377168 ps
CPU time 22.17 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:36:13 PM PDT 24
Peak memory 208660 kb
Host smart-58318b28-380d-449f-891d-03c5c00cee22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048223728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2048223728
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.4035771256
Short name T2
Test name
Test status
Simulation time 115819170 ps
CPU time 1.46 seconds
Started Jul 05 05:35:50 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 200140 kb
Host smart-3885dcce-6eb3-4fc6-beb2-8b9b92ae5f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035771256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.4035771256
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3817591188
Short name T337
Test name
Test status
Simulation time 87904049 ps
CPU time 0.84 seconds
Started Jul 05 05:35:47 PM PDT 24
Finished Jul 05 05:35:49 PM PDT 24
Peak memory 200148 kb
Host smart-60e2980f-c7b7-4b3a-9ec5-23143f558568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817591188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3817591188
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3926935946
Short name T183
Test name
Test status
Simulation time 114866549 ps
CPU time 0.96 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:03 PM PDT 24
Peak memory 199956 kb
Host smart-a2bc3cd3-e285-4d67-b8f8-46a9acbc4f91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926935946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3926935946
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3253492282
Short name T462
Test name
Test status
Simulation time 1220627462 ps
CPU time 5.49 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:07 PM PDT 24
Peak memory 217312 kb
Host smart-09bfa536-edcb-4e93-9123-e741056b794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253492282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3253492282
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1891136132
Short name T531
Test name
Test status
Simulation time 244457981 ps
CPU time 1.09 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:03 PM PDT 24
Peak memory 217548 kb
Host smart-de27cbeb-9d04-4f61-941a-d6c27b2c6a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891136132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1891136132
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2355968303
Short name T401
Test name
Test status
Simulation time 240039401 ps
CPU time 0.94 seconds
Started Jul 05 05:35:58 PM PDT 24
Finished Jul 05 05:35:59 PM PDT 24
Peak memory 199980 kb
Host smart-a63e9b4c-0436-484c-9f29-9819abf565a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355968303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2355968303
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1395164549
Short name T417
Test name
Test status
Simulation time 1161407570 ps
CPU time 5.62 seconds
Started Jul 05 05:35:59 PM PDT 24
Finished Jul 05 05:36:06 PM PDT 24
Peak memory 200020 kb
Host smart-9ae3f399-3380-4c95-b121-afad2940cb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395164549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1395164549
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2255658031
Short name T485
Test name
Test status
Simulation time 182699197 ps
CPU time 1.31 seconds
Started Jul 05 05:36:01 PM PDT 24
Finished Jul 05 05:36:03 PM PDT 24
Peak memory 200160 kb
Host smart-671b26cf-489a-48d8-a8d1-71bb243b4c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255658031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2255658031
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3278633733
Short name T359
Test name
Test status
Simulation time 262279821 ps
CPU time 1.69 seconds
Started Jul 05 05:35:57 PM PDT 24
Finished Jul 05 05:36:00 PM PDT 24
Peak memory 200376 kb
Host smart-4263d48a-8fa8-4de5-87fd-a1d92e3b457e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278633733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3278633733
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.781368573
Short name T175
Test name
Test status
Simulation time 5148826704 ps
CPU time 19.25 seconds
Started Jul 05 05:35:56 PM PDT 24
Finished Jul 05 05:36:16 PM PDT 24
Peak memory 208664 kb
Host smart-c6489844-fff4-448f-a09e-7f0c5b111752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781368573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.781368573
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2313867695
Short name T184
Test name
Test status
Simulation time 307360365 ps
CPU time 1.96 seconds
Started Jul 05 05:35:58 PM PDT 24
Finished Jul 05 05:36:01 PM PDT 24
Peak memory 208428 kb
Host smart-d7529010-a33a-45b0-83e2-928741e5c0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313867695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2313867695
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1698174182
Short name T315
Test name
Test status
Simulation time 132447574 ps
CPU time 1.07 seconds
Started Jul 05 05:35:58 PM PDT 24
Finished Jul 05 05:36:00 PM PDT 24
Peak memory 200164 kb
Host smart-bf458e63-7697-4e60-8c12-f20631143bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698174182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1698174182
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.862944819
Short name T275
Test name
Test status
Simulation time 80205210 ps
CPU time 0.84 seconds
Started Jul 05 05:35:59 PM PDT 24
Finished Jul 05 05:36:01 PM PDT 24
Peak memory 199924 kb
Host smart-14ce0a7a-14cf-4bee-a87e-4a51862082fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862944819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.862944819
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2163823558
Short name T24
Test name
Test status
Simulation time 2351515921 ps
CPU time 8.21 seconds
Started Jul 05 05:35:55 PM PDT 24
Finished Jul 05 05:36:04 PM PDT 24
Peak memory 217152 kb
Host smart-b236238e-1ade-43eb-b1e3-24f2d56a9752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163823558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2163823558
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1421057389
Short name T390
Test name
Test status
Simulation time 107620181 ps
CPU time 0.81 seconds
Started Jul 05 05:35:59 PM PDT 24
Finished Jul 05 05:36:01 PM PDT 24
Peak memory 199528 kb
Host smart-8741f294-eddc-4552-aeaf-1df6e3c5c861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421057389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1421057389
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.899109453
Short name T185
Test name
Test status
Simulation time 689001077 ps
CPU time 3.71 seconds
Started Jul 05 05:35:56 PM PDT 24
Finished Jul 05 05:36:01 PM PDT 24
Peak memory 200436 kb
Host smart-662245bd-810d-426d-ab03-a45231b1dc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899109453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.899109453
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2108223516
Short name T381
Test name
Test status
Simulation time 171331487 ps
CPU time 1.16 seconds
Started Jul 05 05:35:56 PM PDT 24
Finished Jul 05 05:35:58 PM PDT 24
Peak memory 200160 kb
Host smart-b115f0bc-7c5b-4c35-9e61-1d43adaef553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108223516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2108223516
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2413086823
Short name T539
Test name
Test status
Simulation time 126988667 ps
CPU time 1.18 seconds
Started Jul 05 05:35:54 PM PDT 24
Finished Jul 05 05:35:56 PM PDT 24
Peak memory 200296 kb
Host smart-bae47aaa-b103-4a31-94d7-d573893caf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413086823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2413086823
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2877477992
Short name T363
Test name
Test status
Simulation time 2933880146 ps
CPU time 13.07 seconds
Started Jul 05 05:35:55 PM PDT 24
Finished Jul 05 05:36:09 PM PDT 24
Peak memory 200416 kb
Host smart-e66228b6-265d-4b9b-93ae-313a62e91766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877477992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2877477992
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1887399958
Short name T499
Test name
Test status
Simulation time 366153751 ps
CPU time 2.23 seconds
Started Jul 05 05:35:58 PM PDT 24
Finished Jul 05 05:36:01 PM PDT 24
Peak memory 200184 kb
Host smart-78ee36c5-e600-4609-8c30-6cd897505cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887399958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1887399958
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2405178219
Short name T78
Test name
Test status
Simulation time 111827851 ps
CPU time 1.01 seconds
Started Jul 05 05:35:55 PM PDT 24
Finished Jul 05 05:35:57 PM PDT 24
Peak memory 200076 kb
Host smart-150048ee-61f9-4070-a867-3046db99889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405178219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2405178219
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.631887331
Short name T502
Test name
Test status
Simulation time 69033715 ps
CPU time 0.77 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:03 PM PDT 24
Peak memory 199932 kb
Host smart-43d6414e-bc2f-4c18-aea4-93dd7d2118d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631887331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.631887331
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2546507880
Short name T530
Test name
Test status
Simulation time 1221291643 ps
CPU time 6 seconds
Started Jul 05 05:35:58 PM PDT 24
Finished Jul 05 05:36:05 PM PDT 24
Peak memory 217860 kb
Host smart-c3fd7969-9dda-4a74-a4c8-e353771b5a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546507880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2546507880
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2579299258
Short name T191
Test name
Test status
Simulation time 243734372 ps
CPU time 1.04 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:03 PM PDT 24
Peak memory 217544 kb
Host smart-dd4e7005-394b-4dea-b565-76fc73255b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579299258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2579299258
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.120137456
Short name T235
Test name
Test status
Simulation time 136397803 ps
CPU time 0.81 seconds
Started Jul 05 05:35:57 PM PDT 24
Finished Jul 05 05:35:59 PM PDT 24
Peak memory 199964 kb
Host smart-2e73a4ef-1756-44af-97da-2812967c333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120137456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.120137456
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2630285956
Short name T105
Test name
Test status
Simulation time 866078740 ps
CPU time 4.32 seconds
Started Jul 05 05:35:56 PM PDT 24
Finished Jul 05 05:36:01 PM PDT 24
Peak memory 200436 kb
Host smart-429a9edb-060b-403a-984e-462b5862aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630285956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2630285956
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3467534490
Short name T483
Test name
Test status
Simulation time 157491755 ps
CPU time 1.14 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:02 PM PDT 24
Peak memory 200140 kb
Host smart-caefc597-cc87-458b-8c8c-f5088a6808ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467534490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3467534490
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2207947121
Short name T415
Test name
Test status
Simulation time 111071090 ps
CPU time 1.17 seconds
Started Jul 05 05:35:56 PM PDT 24
Finished Jul 05 05:35:57 PM PDT 24
Peak memory 200404 kb
Host smart-e5e86d72-8112-448a-af25-a10a6c12e120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207947121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2207947121
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1304464268
Short name T478
Test name
Test status
Simulation time 140579160 ps
CPU time 1.74 seconds
Started Jul 05 05:35:56 PM PDT 24
Finished Jul 05 05:35:58 PM PDT 24
Peak memory 208272 kb
Host smart-dff513f7-accd-40e4-a708-4043b46e016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304464268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1304464268
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2692643358
Short name T12
Test name
Test status
Simulation time 86365272 ps
CPU time 0.83 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:02 PM PDT 24
Peak memory 200136 kb
Host smart-daaa29c3-03e3-4bfa-91ef-ad651e5de93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692643358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2692643358
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2813595492
Short name T378
Test name
Test status
Simulation time 60664862 ps
CPU time 0.77 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:09 PM PDT 24
Peak memory 199968 kb
Host smart-0648ac1a-cccc-4ed4-9bb1-338f9e0bb98e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813595492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2813595492
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.101152835
Short name T32
Test name
Test status
Simulation time 1227450029 ps
CPU time 5.44 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:07 PM PDT 24
Peak memory 229912 kb
Host smart-8a4603a4-6e66-4c44-b6fa-40fdd86ff9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101152835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.101152835
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3907685080
Short name T491
Test name
Test status
Simulation time 244161814 ps
CPU time 1.17 seconds
Started Jul 05 05:35:57 PM PDT 24
Finished Jul 05 05:35:59 PM PDT 24
Peak memory 217428 kb
Host smart-d30cf350-34e3-4ad0-a033-c6cf1a377ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907685080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3907685080
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.613559435
Short name T21
Test name
Test status
Simulation time 111279989 ps
CPU time 0.77 seconds
Started Jul 05 05:35:57 PM PDT 24
Finished Jul 05 05:35:58 PM PDT 24
Peak memory 199940 kb
Host smart-87ba5f17-1e34-4fe9-b232-11b85eec8d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613559435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.613559435
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2397409981
Short name T267
Test name
Test status
Simulation time 1271175813 ps
CPU time 4.98 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:07 PM PDT 24
Peak memory 200432 kb
Host smart-60e93bf2-d7bf-454e-b3ed-47ab225057a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397409981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2397409981
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.116690044
Short name T449
Test name
Test status
Simulation time 106995008 ps
CPU time 1.02 seconds
Started Jul 05 05:35:59 PM PDT 24
Finished Jul 05 05:36:01 PM PDT 24
Peak memory 200120 kb
Host smart-72ac70b3-bc27-4b6f-ab79-60f54f751b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116690044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.116690044
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4257439006
Short name T8
Test name
Test status
Simulation time 190661775 ps
CPU time 1.5 seconds
Started Jul 05 05:35:57 PM PDT 24
Finished Jul 05 05:35:59 PM PDT 24
Peak memory 200372 kb
Host smart-34ee2c7f-a52b-4aff-920e-fde5760ffc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257439006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4257439006
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.33034377
Short name T63
Test name
Test status
Simulation time 8309178909 ps
CPU time 27.42 seconds
Started Jul 05 05:35:59 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 200664 kb
Host smart-a4753369-d147-49a2-bd29-5173390879d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33034377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.33034377
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3678369713
Short name T258
Test name
Test status
Simulation time 152814963 ps
CPU time 1.92 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:04 PM PDT 24
Peak memory 200140 kb
Host smart-6ac534c5-b271-4f65-a6c3-85c8ff174cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678369713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3678369713
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.836504049
Short name T172
Test name
Test status
Simulation time 64164474 ps
CPU time 0.78 seconds
Started Jul 05 05:36:06 PM PDT 24
Finished Jul 05 05:36:07 PM PDT 24
Peak memory 199936 kb
Host smart-4c066fc7-7b29-4fd7-9a70-bb713916701d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836504049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.836504049
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1164539517
Short name T27
Test name
Test status
Simulation time 1916878765 ps
CPU time 7.69 seconds
Started Jul 05 05:36:04 PM PDT 24
Finished Jul 05 05:36:12 PM PDT 24
Peak memory 217448 kb
Host smart-ff850ff4-3a4a-417a-a97e-dfc091f730fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164539517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1164539517
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.353758919
Short name T369
Test name
Test status
Simulation time 243486840 ps
CPU time 1.04 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:09 PM PDT 24
Peak memory 217504 kb
Host smart-e0cab180-b14d-4f98-9a5a-9ec1c407bff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353758919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.353758919
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1702190150
Short name T272
Test name
Test status
Simulation time 134776552 ps
CPU time 0.82 seconds
Started Jul 05 05:36:04 PM PDT 24
Finished Jul 05 05:36:05 PM PDT 24
Peak memory 199976 kb
Host smart-348bb790-fbba-4fe3-8132-1ac03a31e2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702190150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1702190150
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1481071792
Short name T150
Test name
Test status
Simulation time 149707092 ps
CPU time 1.16 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:10 PM PDT 24
Peak memory 200132 kb
Host smart-92bbc667-37fb-4af1-8353-267241de3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481071792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1481071792
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.976492805
Short name T362
Test name
Test status
Simulation time 112232041 ps
CPU time 1.19 seconds
Started Jul 05 05:36:08 PM PDT 24
Finished Jul 05 05:36:10 PM PDT 24
Peak memory 200368 kb
Host smart-33b1a223-4d04-4ed0-93f0-b3bb19d1a0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976492805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.976492805
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3389016999
Short name T104
Test name
Test status
Simulation time 1629215641 ps
CPU time 5.96 seconds
Started Jul 05 05:36:10 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 200416 kb
Host smart-61e074e4-081a-49a3-956e-9bef10dd7368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389016999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3389016999
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2010263290
Short name T265
Test name
Test status
Simulation time 501699228 ps
CPU time 2.59 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:10 PM PDT 24
Peak memory 200188 kb
Host smart-4868b1ac-7e66-4599-baf8-38ec9722af18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010263290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2010263290
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2463841072
Short name T158
Test name
Test status
Simulation time 140690466 ps
CPU time 1.23 seconds
Started Jul 05 05:36:08 PM PDT 24
Finished Jul 05 05:36:11 PM PDT 24
Peak memory 200152 kb
Host smart-1a8f57b2-f7d0-4cb2-938c-764cfb7c9142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463841072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2463841072
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4268164765
Short name T435
Test name
Test status
Simulation time 70774365 ps
CPU time 0.8 seconds
Started Jul 05 05:36:10 PM PDT 24
Finished Jul 05 05:36:11 PM PDT 24
Peak memory 199960 kb
Host smart-eddb07e5-3776-4498-aa7b-7e69dbc03c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268164765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4268164765
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3243771749
Short name T405
Test name
Test status
Simulation time 1888257123 ps
CPU time 6.96 seconds
Started Jul 05 05:36:05 PM PDT 24
Finished Jul 05 05:36:13 PM PDT 24
Peak memory 216892 kb
Host smart-7020a301-6d17-4e25-a14e-67e8ac3e6df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243771749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3243771749
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1806175834
Short name T162
Test name
Test status
Simulation time 250241935 ps
CPU time 1.06 seconds
Started Jul 05 05:36:06 PM PDT 24
Finished Jul 05 05:36:08 PM PDT 24
Peak memory 217544 kb
Host smart-96798d8b-ef64-4f54-a5ba-c2631f2c1f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806175834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1806175834
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3216496564
Short name T216
Test name
Test status
Simulation time 190363302 ps
CPU time 0.92 seconds
Started Jul 05 05:36:09 PM PDT 24
Finished Jul 05 05:36:11 PM PDT 24
Peak memory 200000 kb
Host smart-bec8ae52-6985-4ac5-a283-e44596d161b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216496564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3216496564
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1254010497
Short name T215
Test name
Test status
Simulation time 1743260618 ps
CPU time 6.44 seconds
Started Jul 05 05:36:05 PM PDT 24
Finished Jul 05 05:36:13 PM PDT 24
Peak memory 200436 kb
Host smart-58014080-412c-48ba-a801-5d0aa180a056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254010497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1254010497
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2773129388
Short name T219
Test name
Test status
Simulation time 160540689 ps
CPU time 1.3 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:09 PM PDT 24
Peak memory 200164 kb
Host smart-05c853dd-535a-4c17-90e9-3ec975c98591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773129388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2773129388
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4181082460
Short name T234
Test name
Test status
Simulation time 239165798 ps
CPU time 1.42 seconds
Started Jul 05 05:36:10 PM PDT 24
Finished Jul 05 05:36:12 PM PDT 24
Peak memory 200372 kb
Host smart-389bd2f8-445a-49cc-922f-e4b6706ac028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181082460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4181082460
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1248080101
Short name T254
Test name
Test status
Simulation time 14535529052 ps
CPU time 51.37 seconds
Started Jul 05 05:36:05 PM PDT 24
Finished Jul 05 05:36:58 PM PDT 24
Peak memory 208604 kb
Host smart-0842a065-d455-4c5d-8715-ebc79a898c1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248080101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1248080101
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1169580696
Short name T132
Test name
Test status
Simulation time 386445611 ps
CPU time 2.17 seconds
Started Jul 05 05:36:05 PM PDT 24
Finished Jul 05 05:36:08 PM PDT 24
Peak memory 200184 kb
Host smart-f24f439f-0047-46fc-bf6b-468b9533f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169580696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1169580696
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3771590838
Short name T452
Test name
Test status
Simulation time 165701814 ps
CPU time 1.4 seconds
Started Jul 05 05:36:09 PM PDT 24
Finished Jul 05 05:36:11 PM PDT 24
Peak memory 200368 kb
Host smart-7e582bad-61bf-48d4-a8dd-409d55eb6662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771590838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3771590838
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1669240890
Short name T290
Test name
Test status
Simulation time 92039832 ps
CPU time 0.91 seconds
Started Jul 05 05:36:06 PM PDT 24
Finished Jul 05 05:36:09 PM PDT 24
Peak memory 199956 kb
Host smart-2ac95c0d-731a-40a5-86b2-43f84e01ddd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669240890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1669240890
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2012675160
Short name T340
Test name
Test status
Simulation time 2354600954 ps
CPU time 8.78 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 217856 kb
Host smart-3884cbed-9054-47f2-93c7-8655afb41d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012675160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2012675160
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2183637422
Short name T540
Test name
Test status
Simulation time 245375120 ps
CPU time 1.06 seconds
Started Jul 05 05:36:05 PM PDT 24
Finished Jul 05 05:36:07 PM PDT 24
Peak memory 217480 kb
Host smart-a11e42ec-c379-4bda-99db-f9765ca4e5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183637422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2183637422
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1931250002
Short name T204
Test name
Test status
Simulation time 84413070 ps
CPU time 0.78 seconds
Started Jul 05 05:36:06 PM PDT 24
Finished Jul 05 05:36:08 PM PDT 24
Peak memory 199976 kb
Host smart-a4254037-de4e-40a4-b388-43b398855b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931250002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1931250002
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1384284400
Short name T110
Test name
Test status
Simulation time 679959128 ps
CPU time 3.91 seconds
Started Jul 05 05:36:06 PM PDT 24
Finished Jul 05 05:36:12 PM PDT 24
Peak memory 200408 kb
Host smart-3e369b62-ec37-4a3b-8329-6d253d9c51de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384284400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1384284400
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1342633699
Short name T39
Test name
Test status
Simulation time 114573898 ps
CPU time 1.05 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:09 PM PDT 24
Peak memory 200108 kb
Host smart-ab87e989-397b-4f07-8742-c9ca32027eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342633699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1342633699
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.255097382
Short name T35
Test name
Test status
Simulation time 116330613 ps
CPU time 1.2 seconds
Started Jul 05 05:36:08 PM PDT 24
Finished Jul 05 05:36:11 PM PDT 24
Peak memory 200244 kb
Host smart-3c2ab32d-4808-41d0-85f9-79a272f75ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255097382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.255097382
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1002521184
Short name T280
Test name
Test status
Simulation time 6758340736 ps
CPU time 23.1 seconds
Started Jul 05 05:36:08 PM PDT 24
Finished Jul 05 05:36:33 PM PDT 24
Peak memory 208632 kb
Host smart-3b7359cd-5264-4f28-b72d-1dac4870d708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002521184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1002521184
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1127091897
Short name T434
Test name
Test status
Simulation time 491776710 ps
CPU time 2.78 seconds
Started Jul 05 05:36:04 PM PDT 24
Finished Jul 05 05:36:08 PM PDT 24
Peak memory 200160 kb
Host smart-7d7dff1a-1e7a-474c-994e-983f61c83bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127091897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1127091897
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2270282582
Short name T240
Test name
Test status
Simulation time 139490281 ps
CPU time 1.14 seconds
Started Jul 05 05:36:08 PM PDT 24
Finished Jul 05 05:36:11 PM PDT 24
Peak memory 200068 kb
Host smart-59c9fa93-2a95-4fcd-94f3-512119068569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270282582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2270282582
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3482384043
Short name T26
Test name
Test status
Simulation time 2175588029 ps
CPU time 8.23 seconds
Started Jul 05 05:36:08 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 217876 kb
Host smart-9901725a-4ceb-43ae-aac9-8d15fce96989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482384043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3482384043
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.131815635
Short name T334
Test name
Test status
Simulation time 243999772 ps
CPU time 1.24 seconds
Started Jul 05 05:36:08 PM PDT 24
Finished Jul 05 05:36:11 PM PDT 24
Peak memory 217548 kb
Host smart-ef865b18-74c2-44a2-bcfd-c2cf222bc9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131815635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.131815635
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2983339670
Short name T397
Test name
Test status
Simulation time 152939552 ps
CPU time 0.9 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:09 PM PDT 24
Peak memory 199944 kb
Host smart-c93c3bae-c92f-4b98-897b-ca0bce990c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983339670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2983339670
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.54594261
Short name T79
Test name
Test status
Simulation time 801621149 ps
CPU time 3.98 seconds
Started Jul 05 05:36:06 PM PDT 24
Finished Jul 05 05:36:11 PM PDT 24
Peak memory 200448 kb
Host smart-6a65b5f7-e95e-4867-bef5-07678dc0825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54594261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.54594261
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.4125725450
Short name T429
Test name
Test status
Simulation time 174483929 ps
CPU time 1.19 seconds
Started Jul 05 05:36:05 PM PDT 24
Finished Jul 05 05:36:07 PM PDT 24
Peak memory 200160 kb
Host smart-b33a28b8-8807-4a45-bd4d-60861ad26aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125725450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.4125725450
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1406047978
Short name T441
Test name
Test status
Simulation time 109863991 ps
CPU time 1.13 seconds
Started Jul 05 05:36:05 PM PDT 24
Finished Jul 05 05:36:08 PM PDT 24
Peak memory 200284 kb
Host smart-0a830d60-e5da-4b9c-9442-fe31aea5a309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406047978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1406047978
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1109863281
Short name T392
Test name
Test status
Simulation time 11957336239 ps
CPU time 42.97 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 200436 kb
Host smart-6219bb92-56c7-4c7b-a516-bb68ce297645
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109863281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1109863281
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3412511129
Short name T264
Test name
Test status
Simulation time 395110292 ps
CPU time 2.54 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:11 PM PDT 24
Peak memory 200188 kb
Host smart-a9ebec6f-6a00-406e-af31-20f813a7513e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412511129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3412511129
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2575412854
Short name T348
Test name
Test status
Simulation time 192667077 ps
CPU time 1.24 seconds
Started Jul 05 05:36:06 PM PDT 24
Finished Jul 05 05:36:08 PM PDT 24
Peak memory 200116 kb
Host smart-19fd4e36-5d95-459e-9373-14f5191b6be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575412854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2575412854
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2233537942
Short name T75
Test name
Test status
Simulation time 74415773 ps
CPU time 0.8 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:18 PM PDT 24
Peak memory 199888 kb
Host smart-fb77ec3c-6c29-4c63-a975-b8a9cd240634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233537942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2233537942
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1704538282
Short name T472
Test name
Test status
Simulation time 2353761952 ps
CPU time 8.32 seconds
Started Jul 05 05:36:05 PM PDT 24
Finished Jul 05 05:36:14 PM PDT 24
Peak memory 217920 kb
Host smart-51be13f0-882a-4c9b-8619-d450a3bfbfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704538282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1704538282
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2954620785
Short name T51
Test name
Test status
Simulation time 244279286 ps
CPU time 1.19 seconds
Started Jul 05 05:36:08 PM PDT 24
Finished Jul 05 05:36:10 PM PDT 24
Peak memory 217544 kb
Host smart-b17cd9f0-3ae4-4294-bce7-b9465cc612a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954620785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2954620785
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.993145353
Short name T536
Test name
Test status
Simulation time 204950677 ps
CPU time 0.92 seconds
Started Jul 05 05:36:08 PM PDT 24
Finished Jul 05 05:36:10 PM PDT 24
Peak memory 199908 kb
Host smart-db1b5a31-0174-45d4-bbc2-98ab32d265a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993145353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.993145353
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3099472730
Short name T310
Test name
Test status
Simulation time 876838346 ps
CPU time 4.24 seconds
Started Jul 05 05:36:10 PM PDT 24
Finished Jul 05 05:36:15 PM PDT 24
Peak memory 200436 kb
Host smart-d5e606ed-af73-48f0-aa5b-a77595b624b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099472730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3099472730
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.4172138249
Short name T151
Test name
Test status
Simulation time 151414712 ps
CPU time 1.29 seconds
Started Jul 05 05:36:07 PM PDT 24
Finished Jul 05 05:36:10 PM PDT 24
Peak memory 200160 kb
Host smart-c701a6a9-bf21-423d-bbf8-edd9437e0920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172138249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.4172138249
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.369522149
Short name T144
Test name
Test status
Simulation time 114022111 ps
CPU time 1.18 seconds
Started Jul 05 05:36:10 PM PDT 24
Finished Jul 05 05:36:12 PM PDT 24
Peak memory 200412 kb
Host smart-2627afe0-9a08-4a1a-9b70-72108d867a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369522149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.369522149
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1968169924
Short name T469
Test name
Test status
Simulation time 10321779560 ps
CPU time 40.59 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:56 PM PDT 24
Peak memory 208684 kb
Host smart-d0923893-e8d9-4785-8cfd-36646826ed97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968169924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1968169924
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1133051677
Short name T416
Test name
Test status
Simulation time 257276966 ps
CPU time 1.67 seconds
Started Jul 05 05:36:03 PM PDT 24
Finished Jul 05 05:36:06 PM PDT 24
Peak memory 200388 kb
Host smart-84b0abb3-f86d-4c1f-bf9a-9996b6e647de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133051677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1133051677
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4144215096
Short name T154
Test name
Test status
Simulation time 95074333 ps
CPU time 0.95 seconds
Started Jul 05 05:36:05 PM PDT 24
Finished Jul 05 05:36:07 PM PDT 24
Peak memory 200160 kb
Host smart-851a8859-3073-41e2-a7b6-5f2ad7856fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144215096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4144215096
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2776290648
Short name T292
Test name
Test status
Simulation time 75441041 ps
CPU time 0.76 seconds
Started Jul 05 05:35:52 PM PDT 24
Finished Jul 05 05:35:54 PM PDT 24
Peak memory 199976 kb
Host smart-39563838-4f92-46d8-8e1e-4b01cce07777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776290648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2776290648
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1271392580
Short name T31
Test name
Test status
Simulation time 1228787708 ps
CPU time 5.78 seconds
Started Jul 05 05:35:44 PM PDT 24
Finished Jul 05 05:35:50 PM PDT 24
Peak memory 221704 kb
Host smart-8d1054d4-8196-4f4e-ae14-78dab19e11e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271392580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1271392580
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3974853488
Short name T436
Test name
Test status
Simulation time 244315108 ps
CPU time 1 seconds
Started Jul 05 05:35:40 PM PDT 24
Finished Jul 05 05:35:42 PM PDT 24
Peak memory 217528 kb
Host smart-18452be8-cf5e-4d97-b54b-04ada681a541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974853488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3974853488
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.553741418
Short name T374
Test name
Test status
Simulation time 170819452 ps
CPU time 0.82 seconds
Started Jul 05 05:35:36 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 199960 kb
Host smart-0d11c36e-1fc5-46d1-8cee-bbe2d439abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553741418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.553741418
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3209434594
Short name T189
Test name
Test status
Simulation time 1838877984 ps
CPU time 6.65 seconds
Started Jul 05 05:35:34 PM PDT 24
Finished Jul 05 05:35:42 PM PDT 24
Peak memory 200440 kb
Host smart-f57c282f-a0e3-4fe6-b8be-ac3d4e43325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209434594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3209434594
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1849183635
Short name T71
Test name
Test status
Simulation time 16507408158 ps
CPU time 33.32 seconds
Started Jul 05 05:35:42 PM PDT 24
Finished Jul 05 05:36:16 PM PDT 24
Peak memory 217344 kb
Host smart-eb0f77f0-d34e-4934-95fb-f3cbd6b0499a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849183635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1849183635
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1657740677
Short name T190
Test name
Test status
Simulation time 105162291 ps
CPU time 1.1 seconds
Started Jul 05 05:35:39 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 200084 kb
Host smart-edded31e-63f0-48af-8ebb-7a5fae4e090c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657740677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1657740677
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.612466233
Short name T271
Test name
Test status
Simulation time 121981813 ps
CPU time 1.26 seconds
Started Jul 05 05:35:34 PM PDT 24
Finished Jul 05 05:35:36 PM PDT 24
Peak memory 200276 kb
Host smart-d7b27c21-4932-4e43-8b9f-034f127b9d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612466233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.612466233
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3914667388
Short name T62
Test name
Test status
Simulation time 11648133964 ps
CPU time 42.34 seconds
Started Jul 05 05:35:39 PM PDT 24
Finished Jul 05 05:36:22 PM PDT 24
Peak memory 200536 kb
Host smart-bbbe4c2c-08f0-41df-a02d-a3bb9ff6d205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914667388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3914667388
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2478746974
Short name T442
Test name
Test status
Simulation time 288283210 ps
CPU time 2.06 seconds
Started Jul 05 05:35:38 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 208384 kb
Host smart-2fd7baa9-2516-41b4-9388-48a81b8b082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478746974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2478746974
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1877680045
Short name T444
Test name
Test status
Simulation time 253404858 ps
CPU time 1.36 seconds
Started Jul 05 05:35:35 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 200156 kb
Host smart-31d5f80c-d271-48ed-a59d-080a27a16543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877680045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1877680045
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.219973389
Short name T197
Test name
Test status
Simulation time 64984726 ps
CPU time 0.8 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 199952 kb
Host smart-134b9d21-3fa3-4fb4-a3c4-031e58ec78b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219973389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.219973389
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2195607504
Short name T475
Test name
Test status
Simulation time 2179421683 ps
CPU time 7.95 seconds
Started Jul 05 05:36:16 PM PDT 24
Finished Jul 05 05:36:25 PM PDT 24
Peak memory 229952 kb
Host smart-9a79250f-ec66-4a4b-9029-b828dd113254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195607504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2195607504
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3097966536
Short name T413
Test name
Test status
Simulation time 244189721 ps
CPU time 1.22 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 217504 kb
Host smart-1afb668a-039b-4a99-a902-09e9c0862260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097966536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3097966536
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3688222350
Short name T266
Test name
Test status
Simulation time 219536921 ps
CPU time 0.91 seconds
Started Jul 05 05:36:13 PM PDT 24
Finished Jul 05 05:36:14 PM PDT 24
Peak memory 199980 kb
Host smart-9c33c391-a2f3-4ff1-a4b0-27ec320caa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688222350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3688222350
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2693977320
Short name T398
Test name
Test status
Simulation time 1282794638 ps
CPU time 4.92 seconds
Started Jul 05 05:36:14 PM PDT 24
Finished Jul 05 05:36:19 PM PDT 24
Peak memory 200436 kb
Host smart-2300fd53-fd15-475c-8b17-2ba314dac60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693977320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2693977320
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3235314615
Short name T330
Test name
Test status
Simulation time 108499988 ps
CPU time 1.02 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:19 PM PDT 24
Peak memory 200108 kb
Host smart-0eb19299-f07d-47a8-9573-216c215773d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235314615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3235314615
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.365607068
Short name T284
Test name
Test status
Simulation time 120035301 ps
CPU time 1.2 seconds
Started Jul 05 05:36:14 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 200356 kb
Host smart-d12e7064-df86-40dc-af0e-20cf3a1891fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365607068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.365607068
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2976761710
Short name T306
Test name
Test status
Simulation time 2308456909 ps
CPU time 8.34 seconds
Started Jul 05 05:36:19 PM PDT 24
Finished Jul 05 05:36:28 PM PDT 24
Peak memory 200456 kb
Host smart-42273b49-eff0-4cf3-9dd1-8c044cca5028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976761710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2976761710
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1494134646
Short name T303
Test name
Test status
Simulation time 413403285 ps
CPU time 2.25 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:21 PM PDT 24
Peak memory 208380 kb
Host smart-81d02d70-a9ac-4986-a185-dfd9c1e20eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494134646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1494134646
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3570313849
Short name T167
Test name
Test status
Simulation time 294740217 ps
CPU time 1.55 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:20 PM PDT 24
Peak memory 200352 kb
Host smart-c285258b-f53b-487c-9563-016eedda4915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570313849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3570313849
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3599203318
Short name T439
Test name
Test status
Simulation time 66821447 ps
CPU time 0.78 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:19 PM PDT 24
Peak memory 199960 kb
Host smart-fc6bccf7-ab12-4dcd-9e59-9bd2025241aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599203318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3599203318
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3919708486
Short name T288
Test name
Test status
Simulation time 1889091962 ps
CPU time 8.38 seconds
Started Jul 05 05:36:14 PM PDT 24
Finished Jul 05 05:36:23 PM PDT 24
Peak memory 217812 kb
Host smart-c4e90d3b-47a7-4cd2-ad96-2b1dc0987673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919708486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3919708486
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.4226675009
Short name T41
Test name
Test status
Simulation time 244417147 ps
CPU time 1.04 seconds
Started Jul 05 05:36:12 PM PDT 24
Finished Jul 05 05:36:14 PM PDT 24
Peak memory 217532 kb
Host smart-eb113e31-8d63-429d-a4d8-6e34a164fc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226675009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.4226675009
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.5561355
Short name T209
Test name
Test status
Simulation time 148033956 ps
CPU time 0.88 seconds
Started Jul 05 05:36:14 PM PDT 24
Finished Jul 05 05:36:15 PM PDT 24
Peak memory 199964 kb
Host smart-abcc06bf-77b5-4e98-a5bb-9a9a3c1ae6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5561355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.5561355
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1688393494
Short name T23
Test name
Test status
Simulation time 1903296846 ps
CPU time 6.81 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:23 PM PDT 24
Peak memory 200484 kb
Host smart-91f55093-c8b2-42bc-b8dc-baae0278c2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688393494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1688393494
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1179229370
Short name T6
Test name
Test status
Simulation time 183740604 ps
CPU time 1.17 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:18 PM PDT 24
Peak memory 200160 kb
Host smart-91962174-3cf1-448b-b419-24dc3c3dcca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179229370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1179229370
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.4111974615
Short name T402
Test name
Test status
Simulation time 118038297 ps
CPU time 1.21 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 200272 kb
Host smart-0e212fc9-31c3-412e-8ff1-e0c0d0bedc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111974615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.4111974615
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3316107991
Short name T505
Test name
Test status
Simulation time 9025594683 ps
CPU time 34.36 seconds
Started Jul 05 05:36:12 PM PDT 24
Finished Jul 05 05:36:46 PM PDT 24
Peak memory 208612 kb
Host smart-27824b1f-3bcb-4a76-a45d-1363a4b7148d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316107991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3316107991
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2546296841
Short name T454
Test name
Test status
Simulation time 123699983 ps
CPU time 1.6 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:20 PM PDT 24
Peak memory 200180 kb
Host smart-0b3902b6-3d68-4a2c-acf2-5dd6521d3362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546296841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2546296841
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.311490404
Short name T213
Test name
Test status
Simulation time 90577975 ps
CPU time 0.84 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:19 PM PDT 24
Peak memory 200112 kb
Host smart-2846895b-f609-45d1-a8fc-ffe39c20cb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311490404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.311490404
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1401139678
Short name T173
Test name
Test status
Simulation time 83989193 ps
CPU time 0.81 seconds
Started Jul 05 05:36:16 PM PDT 24
Finished Jul 05 05:36:18 PM PDT 24
Peak memory 199948 kb
Host smart-81b46b17-6345-468f-82ed-0a1b05d27cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401139678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1401139678
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.606327707
Short name T412
Test name
Test status
Simulation time 1890386560 ps
CPU time 6.86 seconds
Started Jul 05 05:36:19 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 216884 kb
Host smart-ba7e547e-c871-4531-bf2c-891183a2e084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606327707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.606327707
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2194202552
Short name T208
Test name
Test status
Simulation time 245205398 ps
CPU time 1.04 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:18 PM PDT 24
Peak memory 217412 kb
Host smart-13587c46-a5fc-44d9-8d9f-62dbfe9de472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194202552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2194202552
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1586965258
Short name T508
Test name
Test status
Simulation time 150787702 ps
CPU time 0.91 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 199980 kb
Host smart-dd70a27d-2faf-4549-8c82-42a042e02a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586965258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1586965258
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2496215682
Short name T399
Test name
Test status
Simulation time 2037377274 ps
CPU time 7.89 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:24 PM PDT 24
Peak memory 200336 kb
Host smart-caa1f3ec-4937-4f01-a921-bd0c561b52c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496215682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2496215682
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2509648296
Short name T147
Test name
Test status
Simulation time 105324725 ps
CPU time 1.05 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:19 PM PDT 24
Peak memory 200160 kb
Host smart-751fc52a-ba24-4f6d-a894-b01001318fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509648296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2509648296
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2618060045
Short name T394
Test name
Test status
Simulation time 260333244 ps
CPU time 1.62 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:18 PM PDT 24
Peak memory 200376 kb
Host smart-507631f0-df71-4354-bf33-e19eca503fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618060045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2618060045
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1256985241
Short name T109
Test name
Test status
Simulation time 7462832902 ps
CPU time 27.49 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:45 PM PDT 24
Peak memory 208636 kb
Host smart-7cb6ae4f-9064-4331-823d-9938f1b19f8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256985241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1256985241
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3580709369
Short name T49
Test name
Test status
Simulation time 245784542 ps
CPU time 1.92 seconds
Started Jul 05 05:36:19 PM PDT 24
Finished Jul 05 05:36:22 PM PDT 24
Peak memory 200152 kb
Host smart-eaa38d01-5042-4ebf-8b68-3bc0cf0f1a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580709369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3580709369
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3623279659
Short name T305
Test name
Test status
Simulation time 70748159 ps
CPU time 0.8 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 200160 kb
Host smart-407f8618-f0a4-447d-be39-f6d73c9cb42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623279659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3623279659
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1214690118
Short name T174
Test name
Test status
Simulation time 78648719 ps
CPU time 0.82 seconds
Started Jul 05 05:36:18 PM PDT 24
Finished Jul 05 05:36:20 PM PDT 24
Peak memory 199876 kb
Host smart-18d7a549-7405-4f99-a371-39c8361314b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214690118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1214690118
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1197195907
Short name T86
Test name
Test status
Simulation time 1225329346 ps
CPU time 5.43 seconds
Started Jul 05 05:36:13 PM PDT 24
Finished Jul 05 05:36:19 PM PDT 24
Peak memory 217516 kb
Host smart-75dbebb9-a157-4e06-97fd-b9260bbd00dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197195907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1197195907
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3555781724
Short name T60
Test name
Test status
Simulation time 244575005 ps
CPU time 1.06 seconds
Started Jul 05 05:36:13 PM PDT 24
Finished Jul 05 05:36:15 PM PDT 24
Peak memory 217540 kb
Host smart-a05cf455-2332-433f-8ccf-ce4ef38f243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555781724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3555781724
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.590838932
Short name T379
Test name
Test status
Simulation time 162992066 ps
CPU time 0.87 seconds
Started Jul 05 05:36:13 PM PDT 24
Finished Jul 05 05:36:14 PM PDT 24
Peak memory 199976 kb
Host smart-7ccb983d-fe97-4382-bd07-906012e1a83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590838932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.590838932
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1278157976
Short name T518
Test name
Test status
Simulation time 1669380590 ps
CPU time 6.29 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:23 PM PDT 24
Peak memory 200416 kb
Host smart-49317129-18e5-49cf-b654-13d151c872fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278157976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1278157976
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2717150937
Short name T366
Test name
Test status
Simulation time 185563981 ps
CPU time 1.32 seconds
Started Jul 05 05:36:14 PM PDT 24
Finished Jul 05 05:36:16 PM PDT 24
Peak memory 200100 kb
Host smart-8ff0e1a9-4893-42d7-89c3-2fe8e7d435dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717150937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2717150937
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.971850774
Short name T180
Test name
Test status
Simulation time 114454218 ps
CPU time 1.18 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:19 PM PDT 24
Peak memory 200376 kb
Host smart-a47bf783-e694-4342-bb30-b6bb8d4b0f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971850774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.971850774
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3531660110
Short name T90
Test name
Test status
Simulation time 12232550861 ps
CPU time 40.59 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:59 PM PDT 24
Peak memory 200536 kb
Host smart-8e7d072b-da6a-4463-9bda-2558d2942702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531660110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3531660110
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2359889974
Short name T56
Test name
Test status
Simulation time 150123187 ps
CPU time 1.85 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 200184 kb
Host smart-38bc3b24-169d-4a40-b600-e8ae45cc7493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359889974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2359889974
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2717494145
Short name T309
Test name
Test status
Simulation time 128863534 ps
CPU time 1.12 seconds
Started Jul 05 05:36:18 PM PDT 24
Finished Jul 05 05:36:20 PM PDT 24
Peak memory 200112 kb
Host smart-80e26695-145f-4241-9cba-0f2c9e429520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717494145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2717494145
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1143392750
Short name T323
Test name
Test status
Simulation time 66779790 ps
CPU time 0.76 seconds
Started Jul 05 05:36:18 PM PDT 24
Finished Jul 05 05:36:20 PM PDT 24
Peak memory 199924 kb
Host smart-6f972cfc-1d28-4e27-b058-4cfadc951fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143392750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1143392750
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3197038832
Short name T3
Test name
Test status
Simulation time 1223590502 ps
CPU time 5.65 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:24 PM PDT 24
Peak memory 217732 kb
Host smart-0cb1b965-7233-4fa4-ba49-ab8f31d8ade5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197038832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3197038832
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1566836966
Short name T57
Test name
Test status
Simulation time 244666984 ps
CPU time 1.1 seconds
Started Jul 05 05:36:14 PM PDT 24
Finished Jul 05 05:36:15 PM PDT 24
Peak memory 217476 kb
Host smart-28edc842-f6e8-42c8-b17b-f5052934d93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566836966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1566836966
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1859997647
Short name T364
Test name
Test status
Simulation time 95814393 ps
CPU time 0.76 seconds
Started Jul 05 05:36:13 PM PDT 24
Finished Jul 05 05:36:15 PM PDT 24
Peak memory 199976 kb
Host smart-4a5d3caf-09ef-4c2c-9697-807c0d9388db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859997647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1859997647
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3243400335
Short name T277
Test name
Test status
Simulation time 831709603 ps
CPU time 3.86 seconds
Started Jul 05 05:36:16 PM PDT 24
Finished Jul 05 05:36:21 PM PDT 24
Peak memory 200428 kb
Host smart-f660f9e1-a08b-4d29-8434-505da65b54e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243400335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3243400335
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.391564997
Short name T433
Test name
Test status
Simulation time 161072547 ps
CPU time 1.19 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:20 PM PDT 24
Peak memory 200108 kb
Host smart-a62129d1-6a30-49ae-82fe-474b97caf91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391564997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.391564997
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1461207290
Short name T535
Test name
Test status
Simulation time 251658446 ps
CPU time 1.66 seconds
Started Jul 05 05:38:06 PM PDT 24
Finished Jul 05 05:38:08 PM PDT 24
Peak memory 200340 kb
Host smart-9b3c7091-bddd-441e-ba9b-20b53b750185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461207290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1461207290
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2717670049
Short name T194
Test name
Test status
Simulation time 5530621268 ps
CPU time 25.69 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:44 PM PDT 24
Peak memory 208640 kb
Host smart-09ab1f6e-e7f0-4c24-b831-100eb15cd5c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717670049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2717670049
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.308035842
Short name T160
Test name
Test status
Simulation time 121527156 ps
CPU time 1.67 seconds
Started Jul 05 05:36:14 PM PDT 24
Finished Jul 05 05:36:16 PM PDT 24
Peak memory 200224 kb
Host smart-3c99e63b-6d61-40b3-8813-6e2a95b4239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308035842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.308035842
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.289747942
Short name T228
Test name
Test status
Simulation time 181824302 ps
CPU time 1.15 seconds
Started Jul 05 05:36:16 PM PDT 24
Finished Jul 05 05:36:18 PM PDT 24
Peak memory 200160 kb
Host smart-02717340-9089-44e5-9f4e-7f8f527cefec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289747942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.289747942
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1041997286
Short name T152
Test name
Test status
Simulation time 83944752 ps
CPU time 0.83 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:26 PM PDT 24
Peak memory 199888 kb
Host smart-d48b7f17-ec5d-4b99-9606-7994ee3f9894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041997286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1041997286
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2159539340
Short name T504
Test name
Test status
Simulation time 1221408741 ps
CPU time 6.21 seconds
Started Jul 05 05:36:21 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 217768 kb
Host smart-5327ffda-614c-4c13-84c1-08a137cce148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159539340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2159539340
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1665733721
Short name T529
Test name
Test status
Simulation time 244373709 ps
CPU time 1.05 seconds
Started Jul 05 05:36:22 PM PDT 24
Finished Jul 05 05:36:23 PM PDT 24
Peak memory 217488 kb
Host smart-6eb1d2b6-09a0-4e25-a843-bd691c8b01ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665733721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1665733721
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1691050118
Short name T15
Test name
Test status
Simulation time 163867350 ps
CPU time 0.89 seconds
Started Jul 05 05:36:14 PM PDT 24
Finished Jul 05 05:36:16 PM PDT 24
Peak memory 199976 kb
Host smart-7deae4b4-fa13-4152-b2d0-bf9aa39898d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691050118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1691050118
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3306582481
Short name T301
Test name
Test status
Simulation time 2028465226 ps
CPU time 7.74 seconds
Started Jul 05 05:36:17 PM PDT 24
Finished Jul 05 05:36:26 PM PDT 24
Peak memory 200348 kb
Host smart-64de0256-c89c-4135-8058-40a47b146235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306582481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3306582481
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1835931772
Short name T347
Test name
Test status
Simulation time 185498264 ps
CPU time 1.19 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:26 PM PDT 24
Peak memory 200156 kb
Host smart-d6fb43a7-2e24-4e63-81bc-379af53d645b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835931772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1835931772
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.636995220
Short name T525
Test name
Test status
Simulation time 185664954 ps
CPU time 1.48 seconds
Started Jul 05 05:36:14 PM PDT 24
Finished Jul 05 05:36:16 PM PDT 24
Peak memory 200288 kb
Host smart-64945343-8ac1-4dae-b567-30ffbef1ea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636995220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.636995220
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1153123364
Short name T214
Test name
Test status
Simulation time 1717246928 ps
CPU time 6.72 seconds
Started Jul 05 05:36:21 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 200372 kb
Host smart-f445b0b6-78c8-4812-bd31-0fb7ec1addd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153123364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1153123364
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1312540186
Short name T380
Test name
Test status
Simulation time 130285969 ps
CPU time 1.62 seconds
Started Jul 05 05:36:21 PM PDT 24
Finished Jul 05 05:36:23 PM PDT 24
Peak memory 200228 kb
Host smart-d64cb364-d50d-4696-a7fd-5012971a6e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312540186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1312540186
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2166025115
Short name T42
Test name
Test status
Simulation time 113984146 ps
CPU time 0.91 seconds
Started Jul 05 05:36:15 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 200132 kb
Host smart-3ada44ba-8df3-42a4-9922-a5e3e323d930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166025115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2166025115
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1854662036
Short name T74
Test name
Test status
Simulation time 70361129 ps
CPU time 0.79 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:26 PM PDT 24
Peak memory 199888 kb
Host smart-3921827e-a4b4-4876-bdce-98b9d84e0a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854662036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1854662036
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1549442028
Short name T53
Test name
Test status
Simulation time 1871006771 ps
CPU time 7.4 seconds
Started Jul 05 05:36:26 PM PDT 24
Finished Jul 05 05:36:34 PM PDT 24
Peak memory 217464 kb
Host smart-13d49c9c-33a3-4066-a9b5-8366c0d12779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549442028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1549442028
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2138326953
Short name T299
Test name
Test status
Simulation time 243453074 ps
CPU time 1.16 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:25 PM PDT 24
Peak memory 217548 kb
Host smart-159a6187-819d-4a2a-97f5-426530088f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138326953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2138326953
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2221287751
Short name T368
Test name
Test status
Simulation time 124073892 ps
CPU time 0.81 seconds
Started Jul 05 05:36:22 PM PDT 24
Finished Jul 05 05:36:24 PM PDT 24
Peak memory 199976 kb
Host smart-b1a8b422-542b-4c6e-8c7a-2bb08df24fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221287751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2221287751
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.72947602
Short name T269
Test name
Test status
Simulation time 1000326846 ps
CPU time 5.17 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:30 PM PDT 24
Peak memory 200440 kb
Host smart-44619c12-ea9a-41a7-88f6-caa57f3d6669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72947602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.72947602
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.287486861
Short name T253
Test name
Test status
Simulation time 152248413 ps
CPU time 1.14 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 200160 kb
Host smart-8ce5fb7c-29b7-4ab5-ae65-1787e002404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287486861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.287486861
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1327363449
Short name T296
Test name
Test status
Simulation time 243607435 ps
CPU time 1.44 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:25 PM PDT 24
Peak memory 199756 kb
Host smart-fed344d1-b6ab-42f3-b2d9-5e0eb948e517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327363449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1327363449
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.392195099
Short name T515
Test name
Test status
Simulation time 7318293013 ps
CPU time 26.83 seconds
Started Jul 05 05:36:22 PM PDT 24
Finished Jul 05 05:36:49 PM PDT 24
Peak memory 200432 kb
Host smart-ff4de3cf-90df-49e6-82a2-88872de4ab43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392195099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.392195099
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2892799253
Short name T257
Test name
Test status
Simulation time 544525449 ps
CPU time 2.72 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 200108 kb
Host smart-a104b8bb-ee2d-423d-b914-c7b2b787554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892799253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2892799253
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3365688611
Short name T533
Test name
Test status
Simulation time 153574890 ps
CPU time 1.21 seconds
Started Jul 05 05:36:20 PM PDT 24
Finished Jul 05 05:36:22 PM PDT 24
Peak memory 200324 kb
Host smart-2ef30e1b-ee27-4298-9cd4-4995caff5e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365688611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3365688611
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.4229247957
Short name T274
Test name
Test status
Simulation time 67315943 ps
CPU time 0.75 seconds
Started Jul 05 05:36:21 PM PDT 24
Finished Jul 05 05:36:23 PM PDT 24
Peak memory 199960 kb
Host smart-0f33ec55-a798-461d-8a7f-c5213adeb529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229247957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.4229247957
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2882817325
Short name T423
Test name
Test status
Simulation time 2185915512 ps
CPU time 7.54 seconds
Started Jul 05 05:36:21 PM PDT 24
Finished Jul 05 05:36:30 PM PDT 24
Peak memory 221856 kb
Host smart-cee39847-0e01-45e1-8db9-9406c9b090f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882817325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2882817325
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.218366104
Short name T312
Test name
Test status
Simulation time 244582471 ps
CPU time 1.07 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:25 PM PDT 24
Peak memory 217568 kb
Host smart-10855bd9-32df-4a2d-92f4-f500fa07c918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218366104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.218366104
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.936970958
Short name T459
Test name
Test status
Simulation time 77624346 ps
CPU time 0.78 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:25 PM PDT 24
Peak memory 199876 kb
Host smart-6839685a-7dd1-42f3-9373-45ef20a9a877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936970958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.936970958
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3497546802
Short name T495
Test name
Test status
Simulation time 1991789129 ps
CPU time 7.19 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:32 PM PDT 24
Peak memory 200392 kb
Host smart-1f4a9357-b829-4fb7-be61-4b53ab8b8dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497546802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3497546802
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.4032180152
Short name T231
Test name
Test status
Simulation time 185652868 ps
CPU time 1.21 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 200156 kb
Host smart-59c18d83-a189-47a8-9a94-104660b8bfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032180152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.4032180152
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.433235750
Short name T332
Test name
Test status
Simulation time 128706659 ps
CPU time 1.21 seconds
Started Jul 05 05:36:22 PM PDT 24
Finished Jul 05 05:36:24 PM PDT 24
Peak memory 200372 kb
Host smart-9518cf05-fbaa-4220-995a-b449e37b17dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433235750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.433235750
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2861608726
Short name T320
Test name
Test status
Simulation time 14086311835 ps
CPU time 46.78 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:37:13 PM PDT 24
Peak memory 200484 kb
Host smart-51b2cd42-afe9-4af0-bd4e-eb0434ff69d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861608726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2861608726
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2464636764
Short name T321
Test name
Test status
Simulation time 258703094 ps
CPU time 1.66 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:25 PM PDT 24
Peak memory 200184 kb
Host smart-dced922e-3ec5-40c1-bd78-f123c167cef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464636764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2464636764
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.177600704
Short name T139
Test name
Test status
Simulation time 72198240 ps
CPU time 0.82 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 200028 kb
Host smart-48bb911a-c6c0-4169-833b-e0d49077b642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177600704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.177600704
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1259439250
Short name T155
Test name
Test status
Simulation time 75742337 ps
CPU time 0.79 seconds
Started Jul 05 05:36:26 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 199976 kb
Host smart-67608973-20f0-4426-98a4-a07c1c06b7b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259439250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1259439250
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.708220974
Short name T425
Test name
Test status
Simulation time 1225866268 ps
CPU time 5.86 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:31 PM PDT 24
Peak memory 217840 kb
Host smart-e70a5799-ecd7-4366-b587-b3b4998ece14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708220974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.708220974
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.422176802
Short name T52
Test name
Test status
Simulation time 244703247 ps
CPU time 1.12 seconds
Started Jul 05 05:36:26 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 217528 kb
Host smart-fbf0c91e-ff1b-4bcd-b1f8-e350845c8845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422176802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.422176802
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.789470069
Short name T422
Test name
Test status
Simulation time 146456460 ps
CPU time 0.94 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:26 PM PDT 24
Peak memory 199984 kb
Host smart-7023bd5e-1cac-451d-b864-09494a3567db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789470069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.789470069
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2888602582
Short name T224
Test name
Test status
Simulation time 1092329273 ps
CPU time 5.06 seconds
Started Jul 05 05:36:22 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 200408 kb
Host smart-7f193553-e2f2-4fdf-bcd3-10ec16cada1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888602582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2888602582
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1260280751
Short name T396
Test name
Test status
Simulation time 154458032 ps
CPU time 1.14 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:26 PM PDT 24
Peak memory 200160 kb
Host smart-24701a9f-3c7a-4d02-bdab-42c4306c2bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260280751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1260280751
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3428516491
Short name T516
Test name
Test status
Simulation time 116450316 ps
CPU time 1.18 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 200376 kb
Host smart-9154aefa-af6e-4794-bbc3-7df2ac064810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428516491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3428516491
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3540851785
Short name T291
Test name
Test status
Simulation time 325696507 ps
CPU time 1.61 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:36:28 PM PDT 24
Peak memory 200160 kb
Host smart-feaf38aa-574e-4de9-a928-1412d4717591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540851785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3540851785
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3797465695
Short name T522
Test name
Test status
Simulation time 526953492 ps
CPU time 2.89 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 200104 kb
Host smart-b7b5d2b8-ae87-499f-b28d-47d55799bc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797465695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3797465695
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1669896232
Short name T451
Test name
Test status
Simulation time 73314970 ps
CPU time 0.78 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:25 PM PDT 24
Peak memory 200156 kb
Host smart-1d21893e-5074-46d2-bdf9-f0a22737e176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669896232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1669896232
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3901696728
Short name T370
Test name
Test status
Simulation time 79995353 ps
CPU time 0.81 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:26 PM PDT 24
Peak memory 199832 kb
Host smart-b59c6edb-7b5b-4c88-aeb5-c92e2e2457e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901696728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3901696728
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2008251226
Short name T45
Test name
Test status
Simulation time 2395464322 ps
CPU time 8.98 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 221800 kb
Host smart-55df4598-06f7-48aa-bc9a-37df154181c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008251226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2008251226
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.902662917
Short name T164
Test name
Test status
Simulation time 244237282 ps
CPU time 1.02 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:24 PM PDT 24
Peak memory 217548 kb
Host smart-055ae8a6-52ca-45a0-b025-5f97f76afd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902662917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.902662917
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1918696922
Short name T84
Test name
Test status
Simulation time 111416416 ps
CPU time 0.79 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:24 PM PDT 24
Peak memory 199340 kb
Host smart-7856f1e2-4b42-4a44-bd3f-c9769878a424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918696922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1918696922
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1449794514
Short name T282
Test name
Test status
Simulation time 1455712379 ps
CPU time 5.95 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:31 PM PDT 24
Peak memory 200428 kb
Host smart-782cbf4a-d8dc-4fe6-ad47-a40cd03a6199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449794514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1449794514
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2167359698
Short name T7
Test name
Test status
Simulation time 185319380 ps
CPU time 1.19 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:36:28 PM PDT 24
Peak memory 200160 kb
Host smart-b518fa03-71ea-41f7-a8b8-e5eb08657dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167359698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2167359698
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1915349408
Short name T83
Test name
Test status
Simulation time 114573725 ps
CPU time 1.18 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:25 PM PDT 24
Peak memory 200424 kb
Host smart-7ca08a53-c1df-4d29-8ec6-729f9c048a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915349408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1915349408
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1947631330
Short name T466
Test name
Test status
Simulation time 2880299023 ps
CPU time 14.35 seconds
Started Jul 05 05:36:26 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 208672 kb
Host smart-2ca4ef4d-e634-4268-bbb8-293eae631a61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947631330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1947631330
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1477956678
Short name T461
Test name
Test status
Simulation time 319989477 ps
CPU time 2.1 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:35 PM PDT 24
Peak memory 200228 kb
Host smart-74719eff-ecdc-4b9e-8bd9-82f39662b3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477956678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1477956678
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1412475950
Short name T313
Test name
Test status
Simulation time 57121785 ps
CPU time 0.75 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:26 PM PDT 24
Peak memory 200024 kb
Host smart-82abff74-9938-40ab-9839-3bd0c5daa302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412475950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1412475950
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1387114852
Short name T477
Test name
Test status
Simulation time 55164208 ps
CPU time 0.72 seconds
Started Jul 05 05:35:52 PM PDT 24
Finished Jul 05 05:35:54 PM PDT 24
Peak memory 199972 kb
Host smart-48f30be9-3fd9-4d33-b761-b5d02c04d40f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387114852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1387114852
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1270234749
Short name T523
Test name
Test status
Simulation time 1218418272 ps
CPU time 5.55 seconds
Started Jul 05 05:35:39 PM PDT 24
Finished Jul 05 05:35:45 PM PDT 24
Peak memory 217816 kb
Host smart-38cb4620-b187-4d7d-990e-ccd7cd5dfad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270234749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1270234749
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1419429389
Short name T233
Test name
Test status
Simulation time 245117637 ps
CPU time 1.11 seconds
Started Jul 05 05:35:40 PM PDT 24
Finished Jul 05 05:35:42 PM PDT 24
Peak memory 217412 kb
Host smart-c5a83522-c655-4f8f-a819-499640a71ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419429389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1419429389
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2923608206
Short name T355
Test name
Test status
Simulation time 120146936 ps
CPU time 0.78 seconds
Started Jul 05 05:35:52 PM PDT 24
Finished Jul 05 05:35:54 PM PDT 24
Peak memory 199980 kb
Host smart-a3de239f-5307-457a-9d1d-b4cb27a3d8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923608206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2923608206
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3961962664
Short name T270
Test name
Test status
Simulation time 539235464 ps
CPU time 3.35 seconds
Started Jul 05 05:35:56 PM PDT 24
Finished Jul 05 05:36:00 PM PDT 24
Peak memory 200440 kb
Host smart-1ca99194-fc36-476b-87aa-a1756050bdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961962664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3961962664
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.92806716
Short name T72
Test name
Test status
Simulation time 16514407918 ps
CPU time 27.02 seconds
Started Jul 05 05:35:39 PM PDT 24
Finished Jul 05 05:36:07 PM PDT 24
Peak memory 218280 kb
Host smart-45cab912-2ec4-466e-ae7c-1c44a7607031
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92806716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.92806716
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.475523563
Short name T350
Test name
Test status
Simulation time 146489047 ps
CPU time 1.08 seconds
Started Jul 05 05:35:39 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 200068 kb
Host smart-829dc6ce-e675-4f86-89b9-33a20856b084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475523563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.475523563
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2806279373
Short name T500
Test name
Test status
Simulation time 251942608 ps
CPU time 1.65 seconds
Started Jul 05 05:35:41 PM PDT 24
Finished Jul 05 05:35:43 PM PDT 24
Peak memory 200380 kb
Host smart-e005a3f7-793f-4e9e-8bb4-5d93fd56ffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806279373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2806279373
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1010178553
Short name T111
Test name
Test status
Simulation time 3399517382 ps
CPU time 15.4 seconds
Started Jul 05 05:35:41 PM PDT 24
Finished Jul 05 05:35:58 PM PDT 24
Peak memory 208684 kb
Host smart-91a03151-9b3e-40ea-bc56-0d298e8a8a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010178553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1010178553
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.249804993
Short name T354
Test name
Test status
Simulation time 122606821 ps
CPU time 1.04 seconds
Started Jul 05 05:35:41 PM PDT 24
Finished Jul 05 05:35:43 PM PDT 24
Peak memory 200028 kb
Host smart-159540be-5325-4460-8143-28efd9f9440e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249804993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.249804993
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3358651774
Short name T207
Test name
Test status
Simulation time 59622909 ps
CPU time 0.72 seconds
Started Jul 05 05:36:27 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 199944 kb
Host smart-06713da4-19f3-4dfb-b87d-2b1f9bb30c52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358651774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3358651774
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.649438618
Short name T64
Test name
Test status
Simulation time 1226957425 ps
CPU time 5.92 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:31 PM PDT 24
Peak memory 217456 kb
Host smart-3a93d18d-ec6a-4c14-b7eb-dc5ab1a03cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649438618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.649438618
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1693305874
Short name T279
Test name
Test status
Simulation time 244651984 ps
CPU time 1.05 seconds
Started Jul 05 05:36:27 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 217528 kb
Host smart-5f7a427a-57ff-4080-b094-ad0d2a30fae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693305874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1693305874
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1230942326
Short name T85
Test name
Test status
Simulation time 84230750 ps
CPU time 0.75 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 199980 kb
Host smart-fd92dab9-983d-436b-80af-fdfe98a5f6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230942326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1230942326
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2013273353
Short name T537
Test name
Test status
Simulation time 967834177 ps
CPU time 5.22 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 200444 kb
Host smart-e578bc33-ae55-4f21-9123-059a0a230a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013273353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2013273353
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1394485440
Short name T149
Test name
Test status
Simulation time 102773157 ps
CPU time 0.98 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 200160 kb
Host smart-d6b7be4b-4a3b-4923-bd6f-e6a9073a53a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394485440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1394485440
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.594763678
Short name T133
Test name
Test status
Simulation time 248399322 ps
CPU time 1.7 seconds
Started Jul 05 05:36:23 PM PDT 24
Finished Jul 05 05:36:26 PM PDT 24
Peak memory 200360 kb
Host smart-bc34750f-8210-40b0-ba3c-acf1083fe7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594763678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.594763678
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.287630520
Short name T519
Test name
Test status
Simulation time 10031942602 ps
CPU time 35.63 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:37:02 PM PDT 24
Peak memory 208692 kb
Host smart-316d14c5-decf-446f-bbb8-a1030244da09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287630520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.287630520
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2194173131
Short name T11
Test name
Test status
Simulation time 257991073 ps
CPU time 2.01 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 200188 kb
Host smart-4bc976dc-409e-4d40-9e32-c95315cb1474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194173131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2194173131
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.316981340
Short name T450
Test name
Test status
Simulation time 143488872 ps
CPU time 1.13 seconds
Started Jul 05 05:36:24 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 200072 kb
Host smart-aa8d4351-bc98-4957-a72c-ef715807a9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316981340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.316981340
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3304307948
Short name T326
Test name
Test status
Simulation time 59399824 ps
CPU time 0.76 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:34 PM PDT 24
Peak memory 199960 kb
Host smart-74b798e2-ae26-490e-bb5e-36282fff37c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304307948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3304307948
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2627567654
Short name T33
Test name
Test status
Simulation time 2367508753 ps
CPU time 7.77 seconds
Started Jul 05 05:36:26 PM PDT 24
Finished Jul 05 05:36:36 PM PDT 24
Peak memory 221644 kb
Host smart-db419064-1063-432e-9a61-2f913031998d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627567654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2627567654
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1128282893
Short name T242
Test name
Test status
Simulation time 245405783 ps
CPU time 1.16 seconds
Started Jul 05 05:36:26 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 217428 kb
Host smart-f47e57c5-4b67-4173-89af-c1199e9ef832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128282893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1128282893
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1841619013
Short name T18
Test name
Test status
Simulation time 205403039 ps
CPU time 0.92 seconds
Started Jul 05 05:36:26 PM PDT 24
Finished Jul 05 05:36:28 PM PDT 24
Peak memory 199980 kb
Host smart-ebefc669-92d2-4b17-ac5e-f47ff3f0344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841619013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1841619013
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1324681679
Short name T510
Test name
Test status
Simulation time 758116833 ps
CPU time 3.79 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:37 PM PDT 24
Peak memory 200412 kb
Host smart-4bad8b31-0e8c-48d3-a5f8-1caad7a97e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324681679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1324681679
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2706074401
Short name T212
Test name
Test status
Simulation time 155402797 ps
CPU time 1.19 seconds
Started Jul 05 05:36:35 PM PDT 24
Finished Jul 05 05:36:38 PM PDT 24
Peak memory 200160 kb
Host smart-6b283eb7-b52f-4d15-892f-5665b7a4aec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706074401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2706074401
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3446063353
Short name T181
Test name
Test status
Simulation time 199660500 ps
CPU time 1.34 seconds
Started Jul 05 05:36:27 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 200384 kb
Host smart-4c3c20d4-4511-4da0-8b9b-1d9c29f9509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446063353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3446063353
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1578892598
Short name T527
Test name
Test status
Simulation time 129203674 ps
CPU time 1.07 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:36:28 PM PDT 24
Peak memory 200152 kb
Host smart-9adc1f3b-27fc-4d85-bda7-b96da9bbc196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578892598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1578892598
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.680522167
Short name T295
Test name
Test status
Simulation time 251280191 ps
CPU time 1.81 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:35 PM PDT 24
Peak memory 200152 kb
Host smart-10fc058a-3317-4ee6-9aee-de88f0dc7bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680522167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.680522167
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1184254305
Short name T456
Test name
Test status
Simulation time 89749383 ps
CPU time 0.93 seconds
Started Jul 05 05:36:25 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 200156 kb
Host smart-78a2cba5-158b-4944-8592-9520a3693a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184254305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1184254305
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.721892483
Short name T391
Test name
Test status
Simulation time 55122210 ps
CPU time 0.74 seconds
Started Jul 05 05:36:33 PM PDT 24
Finished Jul 05 05:36:35 PM PDT 24
Peak memory 199936 kb
Host smart-0620077e-bda1-44a1-b537-532e05698ace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721892483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.721892483
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.4008684188
Short name T286
Test name
Test status
Simulation time 1911761863 ps
CPU time 6.61 seconds
Started Jul 05 05:36:37 PM PDT 24
Finished Jul 05 05:36:46 PM PDT 24
Peak memory 216876 kb
Host smart-33d56527-c066-4fb1-9c49-0452c48efeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008684188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.4008684188
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1907471492
Short name T211
Test name
Test status
Simulation time 244662558 ps
CPU time 1.14 seconds
Started Jul 05 05:36:33 PM PDT 24
Finished Jul 05 05:36:35 PM PDT 24
Peak memory 217504 kb
Host smart-201bae0c-57ff-4303-b873-6bb02df1e0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907471492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1907471492
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1325128234
Short name T20
Test name
Test status
Simulation time 166564579 ps
CPU time 0.88 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:34 PM PDT 24
Peak memory 199976 kb
Host smart-f229b1a3-07a3-45a2-854d-172f4cff325f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325128234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1325128234
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1943208508
Short name T514
Test name
Test status
Simulation time 732416154 ps
CPU time 3.95 seconds
Started Jul 05 05:36:40 PM PDT 24
Finished Jul 05 05:36:45 PM PDT 24
Peak memory 200496 kb
Host smart-0e394f17-27ce-4163-a7dd-5f554165e8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943208508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1943208508
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1728757907
Short name T58
Test name
Test status
Simulation time 103989926 ps
CPU time 1.08 seconds
Started Jul 05 05:36:31 PM PDT 24
Finished Jul 05 05:36:32 PM PDT 24
Peak memory 200168 kb
Host smart-af9a4a9b-73bb-44e4-a40e-8341ef07958d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728757907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1728757907
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.177221600
Short name T407
Test name
Test status
Simulation time 119039951 ps
CPU time 1.14 seconds
Started Jul 05 05:36:26 PM PDT 24
Finished Jul 05 05:36:29 PM PDT 24
Peak memory 200372 kb
Host smart-efe73238-7566-4e38-9d01-7be08e574a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177221600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.177221600
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3866465061
Short name T319
Test name
Test status
Simulation time 6127669887 ps
CPU time 27.92 seconds
Started Jul 05 05:36:38 PM PDT 24
Finished Jul 05 05:37:08 PM PDT 24
Peak memory 208580 kb
Host smart-5d548fa8-70d7-4c63-a620-e79595123227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866465061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3866465061
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2997723355
Short name T463
Test name
Test status
Simulation time 140702314 ps
CPU time 1.96 seconds
Started Jul 05 05:36:36 PM PDT 24
Finished Jul 05 05:36:40 PM PDT 24
Peak memory 200196 kb
Host smart-e6d2c943-4df5-490d-857f-d0804b027521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997723355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2997723355
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1219994056
Short name T470
Test name
Test status
Simulation time 159786632 ps
CPU time 1.43 seconds
Started Jul 05 05:36:41 PM PDT 24
Finished Jul 05 05:36:44 PM PDT 24
Peak memory 200368 kb
Host smart-377b1f56-2850-4c19-b25e-7909aaa97ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219994056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1219994056
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2354904733
Short name T237
Test name
Test status
Simulation time 73073563 ps
CPU time 0.79 seconds
Started Jul 05 05:36:33 PM PDT 24
Finished Jul 05 05:36:35 PM PDT 24
Peak memory 199960 kb
Host smart-ec69c11f-11c4-4f5a-8128-674f593eb241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354904733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2354904733
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3915776219
Short name T393
Test name
Test status
Simulation time 1225706482 ps
CPU time 5.55 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:39 PM PDT 24
Peak memory 221752 kb
Host smart-fcec41ce-3573-443d-b915-012077b19adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915776219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3915776219
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.640015830
Short name T445
Test name
Test status
Simulation time 243658740 ps
CPU time 1.11 seconds
Started Jul 05 05:36:38 PM PDT 24
Finished Jul 05 05:36:41 PM PDT 24
Peak memory 217520 kb
Host smart-1672d95f-11b5-4d26-8195-bc4fadd9a95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640015830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.640015830
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3331212702
Short name T467
Test name
Test status
Simulation time 75531859 ps
CPU time 0.75 seconds
Started Jul 05 05:36:37 PM PDT 24
Finished Jul 05 05:36:40 PM PDT 24
Peak memory 199944 kb
Host smart-ae1c54e7-bf54-4a74-8a74-fac7a07b9914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331212702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3331212702
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.210263542
Short name T261
Test name
Test status
Simulation time 1544754971 ps
CPU time 5.4 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:39 PM PDT 24
Peak memory 200436 kb
Host smart-23808703-bb10-4d15-b439-e8fe391373c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210263542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.210263542
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1857260323
Short name T259
Test name
Test status
Simulation time 148863361 ps
CPU time 1.12 seconds
Started Jul 05 05:36:35 PM PDT 24
Finished Jul 05 05:36:38 PM PDT 24
Peak memory 200160 kb
Host smart-b87a615b-ab68-4837-8e0d-316ef12b3e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857260323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1857260323
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.4030916958
Short name T131
Test name
Test status
Simulation time 250326720 ps
CPU time 1.58 seconds
Started Jul 05 05:36:35 PM PDT 24
Finished Jul 05 05:36:38 PM PDT 24
Peak memory 200380 kb
Host smart-fd5116ff-4380-4aa7-a5da-9408266f02cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030916958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.4030916958
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3721330215
Short name T349
Test name
Test status
Simulation time 1007367149 ps
CPU time 4.79 seconds
Started Jul 05 05:36:34 PM PDT 24
Finished Jul 05 05:36:40 PM PDT 24
Peak memory 208380 kb
Host smart-0c03ca5a-1135-4e04-9a10-3cf604d77629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721330215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3721330215
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.387365829
Short name T325
Test name
Test status
Simulation time 492416793 ps
CPU time 2.65 seconds
Started Jul 05 05:36:33 PM PDT 24
Finished Jul 05 05:36:37 PM PDT 24
Peak memory 200108 kb
Host smart-14c3a238-e7d5-4a9c-b56a-fa40a6d878ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387365829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.387365829
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.4005585180
Short name T202
Test name
Test status
Simulation time 124108592 ps
CPU time 1.01 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:35 PM PDT 24
Peak memory 200152 kb
Host smart-5cd1da9f-d241-4140-aa7c-9a59889a8c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005585180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.4005585180
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.35268982
Short name T496
Test name
Test status
Simulation time 79651857 ps
CPU time 0.8 seconds
Started Jul 05 05:36:34 PM PDT 24
Finished Jul 05 05:36:36 PM PDT 24
Peak memory 199920 kb
Host smart-55cbcb1e-1053-4a68-b5fa-846aeba6a766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35268982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.35268982
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3344568144
Short name T46
Test name
Test status
Simulation time 2380628360 ps
CPU time 8.54 seconds
Started Jul 05 05:36:36 PM PDT 24
Finished Jul 05 05:36:47 PM PDT 24
Peak memory 221856 kb
Host smart-24357b30-b797-40f7-9619-e27da6595783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344568144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3344568144
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3125518978
Short name T448
Test name
Test status
Simulation time 244371939 ps
CPU time 1.08 seconds
Started Jul 05 05:36:35 PM PDT 24
Finished Jul 05 05:36:37 PM PDT 24
Peak memory 217544 kb
Host smart-6866c6d0-d351-4123-8b35-198a26ea8288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125518978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3125518978
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1633824457
Short name T331
Test name
Test status
Simulation time 88358339 ps
CPU time 0.79 seconds
Started Jul 05 05:36:35 PM PDT 24
Finished Jul 05 05:36:37 PM PDT 24
Peak memory 199944 kb
Host smart-4a8e3c09-816e-4f3c-abeb-f4eff42c7358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633824457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1633824457
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1721653674
Short name T493
Test name
Test status
Simulation time 1343591621 ps
CPU time 5.03 seconds
Started Jul 05 05:36:34 PM PDT 24
Finished Jul 05 05:36:41 PM PDT 24
Peak memory 200432 kb
Host smart-3d265b71-7027-4f6f-a332-1c45cb4fd394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721653674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1721653674
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1144849450
Short name T482
Test name
Test status
Simulation time 186607141 ps
CPU time 1.22 seconds
Started Jul 05 05:36:29 PM PDT 24
Finished Jul 05 05:36:31 PM PDT 24
Peak memory 200136 kb
Host smart-3293addf-1961-4694-bed8-5b33d91cfa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144849450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1144849450
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3674257060
Short name T503
Test name
Test status
Simulation time 228998800 ps
CPU time 1.54 seconds
Started Jul 05 05:36:33 PM PDT 24
Finished Jul 05 05:36:36 PM PDT 24
Peak memory 200376 kb
Host smart-c4454ebb-50fc-4678-ad4c-256f549710e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674257060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3674257060
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1379044108
Short name T365
Test name
Test status
Simulation time 7850213363 ps
CPU time 30.35 seconds
Started Jul 05 05:36:35 PM PDT 24
Finished Jul 05 05:37:07 PM PDT 24
Peak memory 200456 kb
Host smart-2fae7343-9e6d-4c92-a4a5-9d6cf0daf384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379044108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1379044108
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.4018785237
Short name T146
Test name
Test status
Simulation time 307856675 ps
CPU time 2.22 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:35 PM PDT 24
Peak memory 208424 kb
Host smart-52a370d6-b4e4-4567-919f-5255e49d3e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018785237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4018785237
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1848723558
Short name T351
Test name
Test status
Simulation time 126287801 ps
CPU time 1.17 seconds
Started Jul 05 05:36:33 PM PDT 24
Finished Jul 05 05:36:36 PM PDT 24
Peak memory 200048 kb
Host smart-98eca354-8af4-493a-a9a4-16d25b72e843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848723558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1848723558
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.149954304
Short name T432
Test name
Test status
Simulation time 77443307 ps
CPU time 0.83 seconds
Started Jul 05 05:36:37 PM PDT 24
Finished Jul 05 05:36:39 PM PDT 24
Peak memory 199972 kb
Host smart-e6515846-7df5-4cde-b99a-2f42465d7ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149954304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.149954304
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3767722948
Short name T134
Test name
Test status
Simulation time 1228241104 ps
CPU time 5.68 seconds
Started Jul 05 05:36:36 PM PDT 24
Finished Jul 05 05:36:44 PM PDT 24
Peak memory 217780 kb
Host smart-6af94018-d67e-4289-8cd8-80ff92622966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767722948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3767722948
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.804005226
Short name T140
Test name
Test status
Simulation time 244115825 ps
CPU time 1.04 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:34 PM PDT 24
Peak memory 217544 kb
Host smart-b012a728-cc46-4935-ab97-f60cf48d745e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804005226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.804005226
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2071847833
Short name T14
Test name
Test status
Simulation time 78273866 ps
CPU time 0.73 seconds
Started Jul 05 05:36:34 PM PDT 24
Finished Jul 05 05:36:36 PM PDT 24
Peak memory 199980 kb
Host smart-9bdaaa80-587c-4e80-af9c-c3d02791202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071847833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2071847833
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.342939425
Short name T201
Test name
Test status
Simulation time 1805635250 ps
CPU time 7.42 seconds
Started Jul 05 05:36:37 PM PDT 24
Finished Jul 05 05:36:46 PM PDT 24
Peak memory 200436 kb
Host smart-3982c0ea-6db2-496b-aa43-30cb9ba97255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342939425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.342939425
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4044884585
Short name T159
Test name
Test status
Simulation time 101481560 ps
CPU time 1.13 seconds
Started Jul 05 05:36:34 PM PDT 24
Finished Jul 05 05:36:36 PM PDT 24
Peak memory 200160 kb
Host smart-6aa70ec0-7c9b-49f6-8bd4-5f3289c2fe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044884585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4044884585
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3402152318
Short name T411
Test name
Test status
Simulation time 250329711 ps
CPU time 1.66 seconds
Started Jul 05 05:36:37 PM PDT 24
Finished Jul 05 05:36:40 PM PDT 24
Peak memory 200300 kb
Host smart-f04d1f11-a59c-4a08-85a5-223d6cc6f7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402152318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3402152318
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2239627816
Short name T34
Test name
Test status
Simulation time 2049387821 ps
CPU time 9.01 seconds
Started Jul 05 05:36:39 PM PDT 24
Finished Jul 05 05:36:50 PM PDT 24
Peak memory 208640 kb
Host smart-d6c434bd-9c93-461c-81ed-8d2938a51289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239627816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2239627816
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2003536857
Short name T371
Test name
Test status
Simulation time 298358798 ps
CPU time 1.99 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:34 PM PDT 24
Peak memory 208380 kb
Host smart-fe4cd9a3-dcf3-43ef-a038-f3d03ec1fc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003536857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2003536857
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2456547773
Short name T329
Test name
Test status
Simulation time 123617280 ps
CPU time 1.04 seconds
Started Jul 05 05:36:33 PM PDT 24
Finished Jul 05 05:36:35 PM PDT 24
Peak memory 200156 kb
Host smart-2742c1da-ffb3-43d5-92bc-571505f71c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456547773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2456547773
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2775138020
Short name T352
Test name
Test status
Simulation time 67081116 ps
CPU time 0.77 seconds
Started Jul 05 05:36:35 PM PDT 24
Finished Jul 05 05:36:38 PM PDT 24
Peak memory 199964 kb
Host smart-881eae0a-e77d-4b20-ab58-7502a0eb671d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775138020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2775138020
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2530862021
Short name T324
Test name
Test status
Simulation time 2359672954 ps
CPU time 8.92 seconds
Started Jul 05 05:36:33 PM PDT 24
Finished Jul 05 05:36:43 PM PDT 24
Peak memory 217776 kb
Host smart-991e33d9-95d3-49f6-9937-84a7b885f8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530862021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2530862021
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3455794840
Short name T217
Test name
Test status
Simulation time 244160823 ps
CPU time 1.16 seconds
Started Jul 05 05:36:34 PM PDT 24
Finished Jul 05 05:36:36 PM PDT 24
Peak memory 217528 kb
Host smart-717d609b-6d6d-42c7-a467-8f345d3d334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455794840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3455794840
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1269192655
Short name T226
Test name
Test status
Simulation time 173327402 ps
CPU time 0.87 seconds
Started Jul 05 05:36:36 PM PDT 24
Finished Jul 05 05:36:39 PM PDT 24
Peak memory 199976 kb
Host smart-d2e86cfc-a5a1-485b-bfa3-e2e11e342222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269192655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1269192655
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.502930119
Short name T289
Test name
Test status
Simulation time 819497093 ps
CPU time 4.39 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:37 PM PDT 24
Peak memory 200436 kb
Host smart-eb82b5f2-3886-40de-94ae-935f999469b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502930119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.502930119
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3249067699
Short name T36
Test name
Test status
Simulation time 178192431 ps
CPU time 1.23 seconds
Started Jul 05 05:36:36 PM PDT 24
Finished Jul 05 05:36:39 PM PDT 24
Peak memory 200156 kb
Host smart-919416b8-1b80-4913-8d82-1d434cc338b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249067699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3249067699
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2849392995
Short name T339
Test name
Test status
Simulation time 196282503 ps
CPU time 1.32 seconds
Started Jul 05 05:36:37 PM PDT 24
Finished Jul 05 05:36:41 PM PDT 24
Peak memory 200372 kb
Host smart-e175c885-023f-4666-8ee0-7c7adc43ef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849392995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2849392995
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3978105895
Short name T182
Test name
Test status
Simulation time 5851115782 ps
CPU time 22.75 seconds
Started Jul 05 05:36:34 PM PDT 24
Finished Jul 05 05:36:58 PM PDT 24
Peak memory 208444 kb
Host smart-6cb057e4-7178-4ced-b0aa-9d009cdbcd33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978105895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3978105895
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3254316774
Short name T166
Test name
Test status
Simulation time 290125949 ps
CPU time 2 seconds
Started Jul 05 05:36:36 PM PDT 24
Finished Jul 05 05:36:40 PM PDT 24
Peak memory 200144 kb
Host smart-1cb87c02-254b-414c-b7dc-7ffe802b99f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254316774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3254316774
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2485693457
Short name T196
Test name
Test status
Simulation time 67161953 ps
CPU time 0.81 seconds
Started Jul 05 05:36:36 PM PDT 24
Finished Jul 05 05:36:38 PM PDT 24
Peak memory 200120 kb
Host smart-3f743c79-ea95-422a-8e37-6bbad7c24e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485693457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2485693457
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1518089335
Short name T421
Test name
Test status
Simulation time 74123536 ps
CPU time 0.85 seconds
Started Jul 05 05:36:34 PM PDT 24
Finished Jul 05 05:36:36 PM PDT 24
Peak memory 199904 kb
Host smart-eb80f24d-c4de-4e86-b8c9-b5e59a951df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518089335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1518089335
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3784596931
Short name T471
Test name
Test status
Simulation time 2367211346 ps
CPU time 8.52 seconds
Started Jul 05 05:36:36 PM PDT 24
Finished Jul 05 05:36:46 PM PDT 24
Peak memory 217948 kb
Host smart-041e8914-4fc8-46d0-ac03-99ebf4112412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784596931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3784596931
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3421164568
Short name T143
Test name
Test status
Simulation time 244207712 ps
CPU time 1.08 seconds
Started Jul 05 05:36:33 PM PDT 24
Finished Jul 05 05:36:35 PM PDT 24
Peak memory 217444 kb
Host smart-08c844c4-7f55-48fc-87bb-619d7d02fe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421164568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3421164568
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1061309899
Short name T293
Test name
Test status
Simulation time 135582786 ps
CPU time 0.78 seconds
Started Jul 05 05:36:30 PM PDT 24
Finished Jul 05 05:36:31 PM PDT 24
Peak memory 199980 kb
Host smart-c8176af6-fe3a-4f90-9076-18a4ca805ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061309899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1061309899
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.436048311
Short name T236
Test name
Test status
Simulation time 814236594 ps
CPU time 4.31 seconds
Started Jul 05 05:36:35 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 200348 kb
Host smart-1fa897ef-6e0c-4e74-a125-6756e32f73e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436048311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.436048311
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3742238875
Short name T142
Test name
Test status
Simulation time 104333085 ps
CPU time 1.02 seconds
Started Jul 05 05:36:32 PM PDT 24
Finished Jul 05 05:36:34 PM PDT 24
Peak memory 200116 kb
Host smart-901d5e7d-98e1-4820-9364-5696daa43877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742238875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3742238875
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2477513261
Short name T404
Test name
Test status
Simulation time 187107911 ps
CPU time 1.38 seconds
Started Jul 05 05:36:36 PM PDT 24
Finished Jul 05 05:36:40 PM PDT 24
Peak memory 200296 kb
Host smart-780debb8-0333-401e-8def-6f58e5d7bc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477513261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2477513261
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4183952442
Short name T490
Test name
Test status
Simulation time 1324091913 ps
CPU time 5.13 seconds
Started Jul 05 05:36:34 PM PDT 24
Finished Jul 05 05:36:40 PM PDT 24
Peak memory 200332 kb
Host smart-c2e3c942-c521-4176-a919-8b87b656bce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183952442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4183952442
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3515933371
Short name T400
Test name
Test status
Simulation time 481985494 ps
CPU time 2.71 seconds
Started Jul 05 05:36:44 PM PDT 24
Finished Jul 05 05:36:49 PM PDT 24
Peak memory 200136 kb
Host smart-b1c740e0-dfa4-458c-b02c-8ec423869828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515933371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3515933371
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2962652731
Short name T458
Test name
Test status
Simulation time 75366654 ps
CPU time 0.81 seconds
Started Jul 05 05:36:36 PM PDT 24
Finished Jul 05 05:36:38 PM PDT 24
Peak memory 200160 kb
Host smart-a0eab153-8680-47d8-b988-6759e4aa30fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962652731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2962652731
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2919752376
Short name T335
Test name
Test status
Simulation time 65372944 ps
CPU time 0.75 seconds
Started Jul 05 05:36:40 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 199960 kb
Host smart-c56bf5f4-9060-4751-9635-7a84edd71096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919752376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2919752376
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2568733155
Short name T336
Test name
Test status
Simulation time 1909135549 ps
CPU time 7.16 seconds
Started Jul 05 05:36:39 PM PDT 24
Finished Jul 05 05:36:48 PM PDT 24
Peak memory 216944 kb
Host smart-b9e19be3-5072-4b77-89a8-1b69728d317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568733155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2568733155
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1536941540
Short name T40
Test name
Test status
Simulation time 244328018 ps
CPU time 1.05 seconds
Started Jul 05 05:36:38 PM PDT 24
Finished Jul 05 05:36:41 PM PDT 24
Peak memory 217548 kb
Host smart-739eef56-c0c9-4986-879d-101484170082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536941540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1536941540
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3899867119
Short name T1
Test name
Test status
Simulation time 81283639 ps
CPU time 0.78 seconds
Started Jul 05 05:36:37 PM PDT 24
Finished Jul 05 05:36:40 PM PDT 24
Peak memory 199976 kb
Host smart-8ade07fe-18ad-46a8-a6bd-743949627a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899867119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3899867119
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1523687301
Short name T170
Test name
Test status
Simulation time 742834689 ps
CPU time 4.04 seconds
Started Jul 05 05:36:40 PM PDT 24
Finished Jul 05 05:36:46 PM PDT 24
Peak memory 200452 kb
Host smart-982e901c-44c7-4a29-bfeb-6355f5e10899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523687301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1523687301
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3641608207
Short name T476
Test name
Test status
Simulation time 174567018 ps
CPU time 1.16 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:46 PM PDT 24
Peak memory 200132 kb
Host smart-609f7b79-53a5-4dd5-b677-bad0fd6eaf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641608207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3641608207
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2365586297
Short name T171
Test name
Test status
Simulation time 250956391 ps
CPU time 1.51 seconds
Started Jul 05 05:36:36 PM PDT 24
Finished Jul 05 05:36:40 PM PDT 24
Peak memory 200372 kb
Host smart-71c80714-0769-4636-beb9-3b5875272112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365586297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2365586297
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.690562840
Short name T420
Test name
Test status
Simulation time 4672570400 ps
CPU time 15.9 seconds
Started Jul 05 05:36:40 PM PDT 24
Finished Jul 05 05:36:57 PM PDT 24
Peak memory 210324 kb
Host smart-145eeedf-b17b-4702-abdf-f4be4e8fa149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690562840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.690562840
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1565137714
Short name T239
Test name
Test status
Simulation time 113485549 ps
CPU time 1.52 seconds
Started Jul 05 05:36:34 PM PDT 24
Finished Jul 05 05:36:37 PM PDT 24
Peak memory 200224 kb
Host smart-95f22956-6803-4a8a-9ec9-9e7b509304f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565137714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1565137714
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2767038953
Short name T176
Test name
Test status
Simulation time 134689212 ps
CPU time 1.02 seconds
Started Jul 05 05:36:37 PM PDT 24
Finished Jul 05 05:36:40 PM PDT 24
Peak memory 200148 kb
Host smart-c5eb4181-35cb-427e-9d43-fddcf401aa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767038953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2767038953
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2462848759
Short name T358
Test name
Test status
Simulation time 81363143 ps
CPU time 0.79 seconds
Started Jul 05 05:36:40 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 199856 kb
Host smart-ba8d152c-4277-4a6b-b256-dde9df290d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462848759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2462848759
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4159007576
Short name T29
Test name
Test status
Simulation time 2353095732 ps
CPU time 8.24 seconds
Started Jul 05 05:36:39 PM PDT 24
Finished Jul 05 05:36:49 PM PDT 24
Peak memory 221784 kb
Host smart-61f1dd84-e9bc-416f-9db5-7ed7b0e40dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159007576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4159007576
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3042083848
Short name T50
Test name
Test status
Simulation time 243359889 ps
CPU time 1.21 seconds
Started Jul 05 05:36:41 PM PDT 24
Finished Jul 05 05:36:44 PM PDT 24
Peak memory 217552 kb
Host smart-af73fda6-c4df-4493-8297-7b23b263c9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042083848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3042083848
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.156834084
Short name T281
Test name
Test status
Simulation time 182245893 ps
CPU time 0.87 seconds
Started Jul 05 05:36:40 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 199964 kb
Host smart-b7bda1bf-96ae-4090-afd7-50d61aa12120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156834084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.156834084
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.435383202
Short name T13
Test name
Test status
Simulation time 1220335441 ps
CPU time 4.94 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:49 PM PDT 24
Peak memory 200364 kb
Host smart-fdc57cbc-6dff-46a1-9a12-08bec1cd5236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435383202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.435383202
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2869012603
Short name T225
Test name
Test status
Simulation time 146574981 ps
CPU time 1.12 seconds
Started Jul 05 05:36:39 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 200160 kb
Host smart-53007e25-47fd-4747-84cb-1a08c45c8c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869012603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2869012603
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.4033308016
Short name T199
Test name
Test status
Simulation time 124781546 ps
CPU time 1.22 seconds
Started Jul 05 05:36:39 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 200364 kb
Host smart-ce10f745-051a-4994-9084-26a907c7e319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033308016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.4033308016
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.287348277
Short name T130
Test name
Test status
Simulation time 6882756818 ps
CPU time 22.93 seconds
Started Jul 05 05:36:38 PM PDT 24
Finished Jul 05 05:37:02 PM PDT 24
Peak memory 200492 kb
Host smart-8b274893-4018-40d4-9a2f-b49de0956428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287348277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.287348277
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.708901912
Short name T297
Test name
Test status
Simulation time 278956829 ps
CPU time 1.86 seconds
Started Jul 05 05:36:45 PM PDT 24
Finished Jul 05 05:36:48 PM PDT 24
Peak memory 200180 kb
Host smart-af55a748-d65e-4aa7-bdb8-101ae6fcadbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708901912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.708901912
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1379647055
Short name T356
Test name
Test status
Simulation time 184402351 ps
CPU time 1.23 seconds
Started Jul 05 05:36:41 PM PDT 24
Finished Jul 05 05:36:44 PM PDT 24
Peak memory 200156 kb
Host smart-834e2045-eef3-4250-abd6-cd875ce3d97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379647055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1379647055
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3508649264
Short name T169
Test name
Test status
Simulation time 57564566 ps
CPU time 0.74 seconds
Started Jul 05 05:35:52 PM PDT 24
Finished Jul 05 05:35:54 PM PDT 24
Peak memory 199976 kb
Host smart-6ceef879-02ca-47f7-a646-6636194d5363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508649264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3508649264
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.222823374
Short name T488
Test name
Test status
Simulation time 1879423275 ps
CPU time 7.74 seconds
Started Jul 05 05:35:41 PM PDT 24
Finished Jul 05 05:35:50 PM PDT 24
Peak memory 221712 kb
Host smart-a65bfc1d-90a2-4c47-98be-bc83289f289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222823374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.222823374
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.241473261
Short name T192
Test name
Test status
Simulation time 243775520 ps
CPU time 1.08 seconds
Started Jul 05 05:35:41 PM PDT 24
Finished Jul 05 05:35:44 PM PDT 24
Peak memory 217548 kb
Host smart-0f3b23da-7f7f-42e7-858d-cee6e69fa167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241473261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.241473261
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3364941228
Short name T187
Test name
Test status
Simulation time 191326943 ps
CPU time 0.91 seconds
Started Jul 05 05:35:46 PM PDT 24
Finished Jul 05 05:35:47 PM PDT 24
Peak memory 199980 kb
Host smart-b1a24d30-f905-4b34-a5a0-a9da9c51ceb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364941228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3364941228
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2635444922
Short name T419
Test name
Test status
Simulation time 1000539704 ps
CPU time 4.95 seconds
Started Jul 05 05:35:55 PM PDT 24
Finished Jul 05 05:36:01 PM PDT 24
Peak memory 200360 kb
Host smart-61c26af2-1223-4da5-9da5-1f8f5520e0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635444922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2635444922
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.790877407
Short name T77
Test name
Test status
Simulation time 16513662822 ps
CPU time 27.37 seconds
Started Jul 05 05:35:39 PM PDT 24
Finished Jul 05 05:36:07 PM PDT 24
Peak memory 218312 kb
Host smart-11856bc2-596c-4867-b2f9-a518d16f6be5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790877407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.790877407
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.284970314
Short name T314
Test name
Test status
Simulation time 100708029 ps
CPU time 1.02 seconds
Started Jul 05 05:35:46 PM PDT 24
Finished Jul 05 05:35:47 PM PDT 24
Peak memory 200160 kb
Host smart-6cf38966-25a5-426e-9074-4c8dedf1b790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284970314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.284970314
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.189656854
Short name T263
Test name
Test status
Simulation time 115949157 ps
CPU time 1.23 seconds
Started Jul 05 05:35:40 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 200372 kb
Host smart-4a69713d-7b8d-4d5c-8e18-385fafb43d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189656854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.189656854
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3686837231
Short name T287
Test name
Test status
Simulation time 124246632 ps
CPU time 1.6 seconds
Started Jul 05 05:35:43 PM PDT 24
Finished Jul 05 05:35:45 PM PDT 24
Peak memory 208356 kb
Host smart-d88a018f-89c7-42c7-a90c-7020603f971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686837231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3686837231
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1495762071
Short name T222
Test name
Test status
Simulation time 215072504 ps
CPU time 1.3 seconds
Started Jul 05 05:35:40 PM PDT 24
Finished Jul 05 05:35:42 PM PDT 24
Peak memory 200136 kb
Host smart-1dfdfdd7-e95f-4d57-8c54-44c07279a03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495762071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1495762071
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.76262665
Short name T360
Test name
Test status
Simulation time 83862823 ps
CPU time 0.86 seconds
Started Jul 05 05:36:40 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 199964 kb
Host smart-20be2d7a-9c9f-4056-be38-dc8e6ad32d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76262665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.76262665
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3214400401
Short name T30
Test name
Test status
Simulation time 1215503767 ps
CPU time 5.42 seconds
Started Jul 05 05:36:37 PM PDT 24
Finished Jul 05 05:36:44 PM PDT 24
Peak memory 221680 kb
Host smart-1c008880-ce7f-4d15-a38f-f9677b5bad04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214400401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3214400401
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3898926283
Short name T145
Test name
Test status
Simulation time 243786031 ps
CPU time 1.06 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:45 PM PDT 24
Peak memory 217548 kb
Host smart-7f4b5d3b-0589-411c-90f1-c9049a8acb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898926283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3898926283
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.4235999670
Short name T317
Test name
Test status
Simulation time 205573751 ps
CPU time 0.97 seconds
Started Jul 05 05:36:44 PM PDT 24
Finished Jul 05 05:36:47 PM PDT 24
Peak memory 199800 kb
Host smart-c49efbe4-cafa-416f-8afd-3dc43d1cdd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235999670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.4235999670
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3271360921
Short name T388
Test name
Test status
Simulation time 862415661 ps
CPU time 4.13 seconds
Started Jul 05 05:36:39 PM PDT 24
Finished Jul 05 05:36:45 PM PDT 24
Peak memory 200440 kb
Host smart-990870df-362e-4cb7-ae12-8c38290b138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271360921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3271360921
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1609919049
Short name T223
Test name
Test status
Simulation time 169648610 ps
CPU time 1.25 seconds
Started Jul 05 05:36:41 PM PDT 24
Finished Jul 05 05:36:44 PM PDT 24
Peak memory 200168 kb
Host smart-e448898e-12e5-4a22-9d2c-639b694b9eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609919049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1609919049
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2639035652
Short name T38
Test name
Test status
Simulation time 118198746 ps
CPU time 1.15 seconds
Started Jul 05 05:36:39 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 200420 kb
Host smart-78bbb083-cc26-4b24-89b7-8bee475071fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639035652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2639035652
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.520426108
Short name T91
Test name
Test status
Simulation time 1946503727 ps
CPU time 8.57 seconds
Started Jul 05 05:36:43 PM PDT 24
Finished Jul 05 05:36:53 PM PDT 24
Peak memory 208640 kb
Host smart-0ac62a8c-10a2-4612-90b1-d0972eb01c93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520426108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.520426108
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2721650005
Short name T480
Test name
Test status
Simulation time 502615581 ps
CPU time 2.55 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:47 PM PDT 24
Peak memory 200180 kb
Host smart-0515c3b6-5752-4752-a478-5adac0b3d05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721650005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2721650005
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1773649172
Short name T179
Test name
Test status
Simulation time 73649148 ps
CPU time 0.78 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:50 PM PDT 24
Peak memory 200100 kb
Host smart-fef3ba91-b090-43b2-981a-9b5315874027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773649172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1773649172
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1102845193
Short name T200
Test name
Test status
Simulation time 101780533 ps
CPU time 0.84 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 199964 kb
Host smart-28c7a1a0-4664-4986-8649-e4f3ddf2132f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102845193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1102845193
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4159579587
Short name T418
Test name
Test status
Simulation time 245280616 ps
CPU time 1.05 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:44 PM PDT 24
Peak memory 217552 kb
Host smart-69c96cef-27b3-4471-8e33-30d8a6c7bfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159579587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4159579587
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2879441147
Short name T227
Test name
Test status
Simulation time 218858177 ps
CPU time 0.93 seconds
Started Jul 05 05:36:45 PM PDT 24
Finished Jul 05 05:36:47 PM PDT 24
Peak memory 199976 kb
Host smart-23b67f98-cff4-425b-a59d-4226ac29060c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879441147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2879441147
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1754558074
Short name T256
Test name
Test status
Simulation time 785577694 ps
CPU time 4.07 seconds
Started Jul 05 05:36:44 PM PDT 24
Finished Jul 05 05:36:50 PM PDT 24
Peak memory 200440 kb
Host smart-8ccc126f-d402-490c-962e-958800ac84a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754558074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1754558074
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.9390402
Short name T489
Test name
Test status
Simulation time 115282226 ps
CPU time 1.02 seconds
Started Jul 05 05:36:40 PM PDT 24
Finished Jul 05 05:36:43 PM PDT 24
Peak memory 200156 kb
Host smart-8c9a11a4-7574-4989-8ebe-03d004d42e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9390402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.9390402
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3813862159
Short name T161
Test name
Test status
Simulation time 199292176 ps
CPU time 1.43 seconds
Started Jul 05 05:36:41 PM PDT 24
Finished Jul 05 05:36:44 PM PDT 24
Peak memory 200368 kb
Host smart-d3810fa6-fa0b-43f2-852a-a82028238f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813862159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3813862159
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2456521032
Short name T107
Test name
Test status
Simulation time 7659790463 ps
CPU time 25.86 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:37:10 PM PDT 24
Peak memory 210704 kb
Host smart-6560831d-02a1-4e2e-979e-fe1c8dbeac31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456521032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2456521032
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2415711745
Short name T424
Test name
Test status
Simulation time 138703686 ps
CPU time 1.7 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:45 PM PDT 24
Peak memory 200176 kb
Host smart-b25ad274-1d3e-402c-ba41-6036ec6c4898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415711745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2415711745
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2227824087
Short name T342
Test name
Test status
Simulation time 73982603 ps
CPU time 0.84 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:45 PM PDT 24
Peak memory 200152 kb
Host smart-0f1c0efd-9960-44df-b9b2-8bd80e0cd1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227824087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2227824087
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3866490938
Short name T148
Test name
Test status
Simulation time 58455832 ps
CPU time 0.75 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:45 PM PDT 24
Peak memory 199920 kb
Host smart-1da23f23-ced6-45ae-ba3c-ce4901380a7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866490938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3866490938
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1730832423
Short name T61
Test name
Test status
Simulation time 2348668403 ps
CPU time 8.14 seconds
Started Jul 05 05:36:41 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 217584 kb
Host smart-37eeb701-5e05-4834-97b8-968d6d59a0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730832423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1730832423
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.490968745
Short name T521
Test name
Test status
Simulation time 244361433 ps
CPU time 1.11 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:45 PM PDT 24
Peak memory 217544 kb
Host smart-34be64e5-575f-4d79-8dcf-2094504c5314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490968745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.490968745
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1257057862
Short name T464
Test name
Test status
Simulation time 247733942 ps
CPU time 1.05 seconds
Started Jul 05 05:36:43 PM PDT 24
Finished Jul 05 05:36:46 PM PDT 24
Peak memory 199900 kb
Host smart-7ea36b24-da05-449f-95f7-f9354be81b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257057862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1257057862
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3630000740
Short name T59
Test name
Test status
Simulation time 1783458227 ps
CPU time 6.34 seconds
Started Jul 05 05:36:43 PM PDT 24
Finished Jul 05 05:36:52 PM PDT 24
Peak memory 200016 kb
Host smart-6f740db8-1a39-463e-8e37-f986878d0e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630000740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3630000740
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2247783189
Short name T468
Test name
Test status
Simulation time 148482095 ps
CPU time 1.07 seconds
Started Jul 05 05:36:43 PM PDT 24
Finished Jul 05 05:36:46 PM PDT 24
Peak memory 200160 kb
Host smart-75cab127-7c4a-4455-8efd-71f5f74614e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247783189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2247783189
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3587890031
Short name T94
Test name
Test status
Simulation time 192163551 ps
CPU time 1.36 seconds
Started Jul 05 05:36:41 PM PDT 24
Finished Jul 05 05:36:44 PM PDT 24
Peak memory 200352 kb
Host smart-99e41d57-47eb-445d-a4d7-54301fcd4cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587890031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3587890031
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2670568474
Short name T479
Test name
Test status
Simulation time 2176715019 ps
CPU time 8.42 seconds
Started Jul 05 05:36:44 PM PDT 24
Finished Jul 05 05:36:54 PM PDT 24
Peak memory 208556 kb
Host smart-ff281fea-d185-4e22-840a-d1fb75275c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670568474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2670568474
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3121569414
Short name T406
Test name
Test status
Simulation time 376277675 ps
CPU time 2.65 seconds
Started Jul 05 05:36:43 PM PDT 24
Finished Jul 05 05:36:48 PM PDT 24
Peak memory 200104 kb
Host smart-fa579565-eb0b-4d9b-af71-520db8c7fdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121569414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3121569414
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2796102529
Short name T447
Test name
Test status
Simulation time 66828428 ps
CPU time 0.76 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:45 PM PDT 24
Peak memory 200060 kb
Host smart-65647adb-f294-4064-9226-cba5d95737c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796102529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2796102529
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3871690378
Short name T512
Test name
Test status
Simulation time 80565910 ps
CPU time 0.82 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:50 PM PDT 24
Peak memory 199912 kb
Host smart-6e9d32c2-b6c9-40bd-9630-379ab59057e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871690378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3871690378
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2205854259
Short name T43
Test name
Test status
Simulation time 1898257608 ps
CPU time 7.02 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:59 PM PDT 24
Peak memory 221752 kb
Host smart-250ecb7d-1e56-4582-8874-b385ba99f870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205854259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2205854259
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.565239942
Short name T273
Test name
Test status
Simulation time 244277481 ps
CPU time 1.17 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 217520 kb
Host smart-967fcd86-9ed7-4006-80d5-c12bee57f133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565239942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.565239942
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2758450066
Short name T304
Test name
Test status
Simulation time 157369087 ps
CPU time 0.89 seconds
Started Jul 05 05:36:43 PM PDT 24
Finished Jul 05 05:36:46 PM PDT 24
Peak memory 199900 kb
Host smart-cef1a0a8-a409-4dc9-9b25-45b335946b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758450066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2758450066
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.501259522
Short name T260
Test name
Test status
Simulation time 1041741169 ps
CPU time 4.54 seconds
Started Jul 05 05:36:44 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 200240 kb
Host smart-24bc4af7-0979-4c28-82cf-6abbc5c2260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501259522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.501259522
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.932558750
Short name T375
Test name
Test status
Simulation time 186575988 ps
CPU time 1.14 seconds
Started Jul 05 05:36:37 PM PDT 24
Finished Jul 05 05:36:40 PM PDT 24
Peak memory 200432 kb
Host smart-4e8fee2e-b8e3-4c19-99be-730493820c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932558750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.932558750
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.335718881
Short name T506
Test name
Test status
Simulation time 200163221 ps
CPU time 1.37 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:53 PM PDT 24
Peak memory 200372 kb
Host smart-498a85f2-f183-4b71-bbde-ed65ee199567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335718881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.335718881
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1692270694
Short name T82
Test name
Test status
Simulation time 4516323490 ps
CPU time 17.36 seconds
Started Jul 05 05:36:38 PM PDT 24
Finished Jul 05 05:36:57 PM PDT 24
Peak memory 216876 kb
Host smart-1032a44d-be7e-4733-81bf-74232147be35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692270694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1692270694
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1017197333
Short name T206
Test name
Test status
Simulation time 275649892 ps
CPU time 1.95 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:50 PM PDT 24
Peak memory 200128 kb
Host smart-8a516d72-e946-4e41-a133-9cfb1dfa06eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017197333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1017197333
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2681192969
Short name T178
Test name
Test status
Simulation time 98582508 ps
CPU time 0.86 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 200156 kb
Host smart-c7e83793-316a-4c05-8cf2-70b46e9b7835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681192969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2681192969
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1925014904
Short name T372
Test name
Test status
Simulation time 64192922 ps
CPU time 0.83 seconds
Started Jul 05 05:36:40 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 199960 kb
Host smart-7b4136a4-9dd8-4846-807d-e799b23201e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925014904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1925014904
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1941658042
Short name T382
Test name
Test status
Simulation time 1212206356 ps
CPU time 5.71 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:54 PM PDT 24
Peak memory 217760 kb
Host smart-4ac1a0cf-4988-43e1-b3e5-22764e599b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941658042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1941658042
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3841888439
Short name T255
Test name
Test status
Simulation time 244327215 ps
CPU time 1.05 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:53 PM PDT 24
Peak memory 217544 kb
Host smart-9534f73d-05bf-44cc-9057-0f0fcbcda5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841888439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3841888439
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3449503129
Short name T338
Test name
Test status
Simulation time 88495148 ps
CPU time 0.74 seconds
Started Jul 05 05:36:47 PM PDT 24
Finished Jul 05 05:36:49 PM PDT 24
Peak memory 199924 kb
Host smart-f3826242-df8e-4b25-8399-5485d190a6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449503129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3449503129
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2631605588
Short name T484
Test name
Test status
Simulation time 1617417042 ps
CPU time 6.69 seconds
Started Jul 05 05:36:43 PM PDT 24
Finished Jul 05 05:36:52 PM PDT 24
Peak memory 200056 kb
Host smart-20f8ebe0-81bc-4593-8843-d410a6ac36bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631605588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2631605588
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2622348696
Short name T285
Test name
Test status
Simulation time 147659667 ps
CPU time 1.09 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 200160 kb
Host smart-d6e7e4fa-8a78-4df9-9468-c2a5cf0abf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622348696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2622348696
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1124369707
Short name T386
Test name
Test status
Simulation time 244542115 ps
CPU time 1.45 seconds
Started Jul 05 05:36:44 PM PDT 24
Finished Jul 05 05:36:47 PM PDT 24
Peak memory 200372 kb
Host smart-759bdc1b-0809-4c31-9400-e6533f5a6cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124369707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1124369707
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.567467765
Short name T430
Test name
Test status
Simulation time 6256917252 ps
CPU time 27.09 seconds
Started Jul 05 05:36:56 PM PDT 24
Finished Jul 05 05:37:24 PM PDT 24
Peak memory 208668 kb
Host smart-3e95be5f-f628-4aa2-b3c8-527aaed1bcd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567467765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.567467765
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4063578381
Short name T341
Test name
Test status
Simulation time 154367458 ps
CPU time 1.81 seconds
Started Jul 05 05:36:42 PM PDT 24
Finished Jul 05 05:36:45 PM PDT 24
Peak memory 200188 kb
Host smart-3b277f30-a836-45c0-87f6-dd6a7715aa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063578381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4063578381
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.525219826
Short name T218
Test name
Test status
Simulation time 96069641 ps
CPU time 0.91 seconds
Started Jul 05 05:36:45 PM PDT 24
Finished Jul 05 05:36:47 PM PDT 24
Peak memory 200152 kb
Host smart-6795a3f0-db6a-4722-9a31-54928a4302cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525219826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.525219826
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1443784165
Short name T383
Test name
Test status
Simulation time 58706841 ps
CPU time 0.75 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:52 PM PDT 24
Peak memory 199968 kb
Host smart-a50d41d2-1f4a-4ce1-b132-0d964b4c9adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443784165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1443784165
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.512735673
Short name T106
Test name
Test status
Simulation time 244402724 ps
CPU time 1.18 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:52 PM PDT 24
Peak memory 217540 kb
Host smart-b9351a03-1ce3-4331-8514-5d0aea8f6600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512735673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.512735673
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2214618518
Short name T492
Test name
Test status
Simulation time 162234146 ps
CPU time 0.87 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:53 PM PDT 24
Peak memory 199976 kb
Host smart-b255829a-0d13-4c04-9117-2549ff076363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214618518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2214618518
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.928463555
Short name T384
Test name
Test status
Simulation time 865671965 ps
CPU time 4.27 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:56 PM PDT 24
Peak memory 200388 kb
Host smart-724a0b99-20d9-4b17-a2ab-fd7b55d153ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928463555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.928463555
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2662620669
Short name T389
Test name
Test status
Simulation time 143534390 ps
CPU time 1.12 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:54 PM PDT 24
Peak memory 200168 kb
Host smart-28c6dd57-98a3-4927-a7fa-544e2ad6ee9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662620669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2662620669
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2623888067
Short name T250
Test name
Test status
Simulation time 254332359 ps
CPU time 1.58 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 200324 kb
Host smart-80b21cb7-dd82-49bb-bad4-6ef9eea1f2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623888067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2623888067
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.102486069
Short name T517
Test name
Test status
Simulation time 3467353682 ps
CPU time 16.19 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:37:09 PM PDT 24
Peak memory 208668 kb
Host smart-aa0f39fc-73c3-48ac-915e-3a48787b24e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102486069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.102486069
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3609642270
Short name T55
Test name
Test status
Simulation time 126565907 ps
CPU time 1.62 seconds
Started Jul 05 05:36:55 PM PDT 24
Finished Jul 05 05:36:57 PM PDT 24
Peak memory 208360 kb
Host smart-5e7d18cf-0996-4eec-963b-310673c19950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609642270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3609642270
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.4179527189
Short name T526
Test name
Test status
Simulation time 206947366 ps
CPU time 1.28 seconds
Started Jul 05 05:36:51 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 200120 kb
Host smart-0e9a5e21-0eba-414e-bc20-e965892cbef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179527189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.4179527189
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1869646564
Short name T367
Test name
Test status
Simulation time 65537693 ps
CPU time 0.75 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:49 PM PDT 24
Peak memory 199896 kb
Host smart-9c248ac1-1f79-43e1-87b4-6a0857880c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869646564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1869646564
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.173102626
Short name T278
Test name
Test status
Simulation time 1904803690 ps
CPU time 6.93 seconds
Started Jul 05 05:36:52 PM PDT 24
Finished Jul 05 05:37:01 PM PDT 24
Peak memory 217676 kb
Host smart-906d106e-3b15-42e3-b5ef-144311756024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173102626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.173102626
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.554430722
Short name T494
Test name
Test status
Simulation time 244194395 ps
CPU time 1.02 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:53 PM PDT 24
Peak memory 217448 kb
Host smart-11b1e613-af8d-41fe-b5d0-5ba900187823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554430722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.554430722
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3767565635
Short name T16
Test name
Test status
Simulation time 187574936 ps
CPU time 0.87 seconds
Started Jul 05 05:36:53 PM PDT 24
Finished Jul 05 05:36:56 PM PDT 24
Peak memory 199984 kb
Host smart-87d81a79-0482-4213-be31-6676571df3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767565635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3767565635
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2836433600
Short name T198
Test name
Test status
Simulation time 2009255586 ps
CPU time 7.52 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:57 PM PDT 24
Peak memory 200436 kb
Host smart-6abb429f-e118-4713-8ed7-3a4f88b1fa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836433600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2836433600
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3302159267
Short name T474
Test name
Test status
Simulation time 173442524 ps
CPU time 1.19 seconds
Started Jul 05 05:36:51 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 200120 kb
Host smart-07fa67b5-720d-4981-bf34-005a4c9c0c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302159267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3302159267
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3251911763
Short name T377
Test name
Test status
Simulation time 190527134 ps
CPU time 1.44 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:53 PM PDT 24
Peak memory 200376 kb
Host smart-2f3a15ad-1bce-42b6-979b-fff695ad8276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251911763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3251911763
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1479131240
Short name T108
Test name
Test status
Simulation time 4595729682 ps
CPU time 21.73 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:37:14 PM PDT 24
Peak memory 200360 kb
Host smart-8d487c7f-5acd-498c-8522-9a0a4ac99320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479131240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1479131240
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1211736709
Short name T193
Test name
Test status
Simulation time 375024593 ps
CPU time 2.15 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 208288 kb
Host smart-bf13d719-099a-4512-b8c4-823611d49117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211736709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1211736709
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2972119297
Short name T440
Test name
Test status
Simulation time 138952427 ps
CPU time 0.99 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:53 PM PDT 24
Peak memory 200104 kb
Host smart-07cc13d7-e241-4b27-a91d-d39a5033f0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972119297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2972119297
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3830956499
Short name T245
Test name
Test status
Simulation time 64871645 ps
CPU time 0.78 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:52 PM PDT 24
Peak memory 199960 kb
Host smart-68ea84ba-b58e-4c59-bfd6-556a6d35f0f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830956499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3830956499
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3769381509
Short name T294
Test name
Test status
Simulation time 2356015965 ps
CPU time 8.76 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:59 PM PDT 24
Peak memory 221260 kb
Host smart-092b4430-d580-40a4-83ea-804579c643a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769381509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3769381509
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3741830129
Short name T168
Test name
Test status
Simulation time 243910386 ps
CPU time 1.14 seconds
Started Jul 05 05:36:52 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 217556 kb
Host smart-560749aa-b24c-4a0d-bf44-2c6f16c97be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741830129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3741830129
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.928400045
Short name T302
Test name
Test status
Simulation time 190454430 ps
CPU time 0.91 seconds
Started Jul 05 05:36:53 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 199980 kb
Host smart-7dea0a91-5178-4e3c-9553-f267265282cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928400045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.928400045
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2141316784
Short name T328
Test name
Test status
Simulation time 1880347432 ps
CPU time 7.73 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:56 PM PDT 24
Peak memory 200484 kb
Host smart-6a5e6068-c9cc-4652-b44e-e04c2bf62c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141316784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2141316784
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2567060393
Short name T385
Test name
Test status
Simulation time 186249099 ps
CPU time 1.2 seconds
Started Jul 05 05:36:51 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 200152 kb
Host smart-318a1d54-9668-4462-8573-50e4aa3dd9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567060393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2567060393
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1222798454
Short name T93
Test name
Test status
Simulation time 197235976 ps
CPU time 1.38 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 200380 kb
Host smart-7959be49-be1f-49a9-96cc-5c32afa7632a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222798454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1222798454
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1044360113
Short name T345
Test name
Test status
Simulation time 6790634502 ps
CPU time 22.61 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:37:13 PM PDT 24
Peak memory 210000 kb
Host smart-7d533387-1b3e-4711-b611-c2a5ae1b25cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044360113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1044360113
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2414806874
Short name T327
Test name
Test status
Simulation time 471667825 ps
CPU time 2.61 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 200196 kb
Host smart-754b198d-4394-4a02-94fc-abf24802ade1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414806874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2414806874
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3583497307
Short name T248
Test name
Test status
Simulation time 159155787 ps
CPU time 1.14 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 200116 kb
Host smart-013edc2d-d1f2-46e3-bd36-c98e21c59943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583497307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3583497307
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3739412315
Short name T238
Test name
Test status
Simulation time 76783301 ps
CPU time 0.81 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:51 PM PDT 24
Peak memory 199964 kb
Host smart-a1d09c75-f5a7-422f-bbb4-bfaa22150494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739412315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3739412315
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1505309828
Short name T513
Test name
Test status
Simulation time 1231660168 ps
CPU time 5.3 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:57 PM PDT 24
Peak memory 221636 kb
Host smart-043f0fd9-4349-4c7f-8031-0da10a49e9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505309828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1505309828
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.931835803
Short name T283
Test name
Test status
Simulation time 244648410 ps
CPU time 1.1 seconds
Started Jul 05 05:36:52 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 217552 kb
Host smart-6bf14cd0-5c8d-485a-abf9-bbfd52670856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931835803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.931835803
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2833798017
Short name T19
Test name
Test status
Simulation time 182583236 ps
CPU time 0.88 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:52 PM PDT 24
Peak memory 199980 kb
Host smart-8a9fdac3-eeaa-400d-9e81-f132f12a29ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833798017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2833798017
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.4031983452
Short name T112
Test name
Test status
Simulation time 2021204565 ps
CPU time 7.34 seconds
Started Jul 05 05:36:48 PM PDT 24
Finished Jul 05 05:36:56 PM PDT 24
Peak memory 200436 kb
Host smart-19d2b9ce-fd3e-4897-95eb-e3470a6de635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031983452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4031983452
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1006032564
Short name T322
Test name
Test status
Simulation time 98238430 ps
CPU time 1.07 seconds
Started Jul 05 05:36:49 PM PDT 24
Finished Jul 05 05:36:52 PM PDT 24
Peak memory 200160 kb
Host smart-c23ec932-dabc-4f5f-82b5-057b86176aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006032564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1006032564
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2363810648
Short name T361
Test name
Test status
Simulation time 193647906 ps
CPU time 1.31 seconds
Started Jul 05 05:36:47 PM PDT 24
Finished Jul 05 05:36:49 PM PDT 24
Peak memory 200324 kb
Host smart-a8fbe3a7-5e53-4605-b828-aba430c41d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363810648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2363810648
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1461155962
Short name T95
Test name
Test status
Simulation time 7160751461 ps
CPU time 31.36 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:37:24 PM PDT 24
Peak memory 208656 kb
Host smart-d152c1c4-a7a0-4742-aed3-1f7f69cefd06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461155962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1461155962
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.4020952262
Short name T165
Test name
Test status
Simulation time 151327431 ps
CPU time 1.85 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:54 PM PDT 24
Peak memory 200124 kb
Host smart-73d42873-78b9-48d4-b393-fc15bf064de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020952262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.4020952262
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3962491241
Short name T92
Test name
Test status
Simulation time 101498808 ps
CPU time 0.89 seconds
Started Jul 05 05:36:51 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 200152 kb
Host smart-64322bd1-01a7-4be2-81d6-1800b8242115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962491241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3962491241
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.174239375
Short name T426
Test name
Test status
Simulation time 58662777 ps
CPU time 0.74 seconds
Started Jul 05 05:36:51 PM PDT 24
Finished Jul 05 05:36:54 PM PDT 24
Peak memory 199972 kb
Host smart-6c5addc5-2894-420a-8a17-25986871ecac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174239375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.174239375
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1461096489
Short name T298
Test name
Test status
Simulation time 1885664460 ps
CPU time 7.83 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:37:00 PM PDT 24
Peak memory 217608 kb
Host smart-d1cac1ea-4cfa-42ad-8d67-d7435ae73b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461096489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1461096489
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.209745834
Short name T524
Test name
Test status
Simulation time 244786052 ps
CPU time 1.05 seconds
Started Jul 05 05:36:51 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 217560 kb
Host smart-4f40a92a-7fd8-4591-835d-f1b044d4c324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209745834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.209745834
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1304855249
Short name T538
Test name
Test status
Simulation time 152776578 ps
CPU time 0.87 seconds
Started Jul 05 05:36:51 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 199980 kb
Host smart-0299759f-8eb5-4902-b496-ffcb258909b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304855249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1304855249
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3909170953
Short name T457
Test name
Test status
Simulation time 710111383 ps
CPU time 3.55 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:56 PM PDT 24
Peak memory 200432 kb
Host smart-0d847f29-8a56-47a1-886b-719dd1c71de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909170953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3909170953
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2257973031
Short name T203
Test name
Test status
Simulation time 184985538 ps
CPU time 1.24 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:54 PM PDT 24
Peak memory 200156 kb
Host smart-6436e7b4-49d3-4bbe-a350-be1b49bba45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257973031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2257973031
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.58310770
Short name T252
Test name
Test status
Simulation time 186576427 ps
CPU time 1.34 seconds
Started Jul 05 05:36:57 PM PDT 24
Finished Jul 05 05:36:59 PM PDT 24
Peak memory 200384 kb
Host smart-7bf5e645-0366-4ffe-89a1-50c461b8df87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58310770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.58310770
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2372179143
Short name T311
Test name
Test status
Simulation time 2975478425 ps
CPU time 10.97 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:37:04 PM PDT 24
Peak memory 208688 kb
Host smart-a8717fe7-9ba4-4cd8-a762-370aba91756e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372179143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2372179143
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3545680715
Short name T443
Test name
Test status
Simulation time 120289612 ps
CPU time 1.6 seconds
Started Jul 05 05:36:51 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 208356 kb
Host smart-8785e211-1f0c-4b37-8464-dd827fd0fcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545680715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3545680715
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2613729617
Short name T316
Test name
Test status
Simulation time 92203739 ps
CPU time 0.86 seconds
Started Jul 05 05:36:52 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 200152 kb
Host smart-dc5c2a5e-c2a0-4f76-9bd0-ffe0582b4643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613729617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2613729617
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1884545242
Short name T453
Test name
Test status
Simulation time 58565418 ps
CPU time 0.77 seconds
Started Jul 05 05:35:41 PM PDT 24
Finished Jul 05 05:35:42 PM PDT 24
Peak memory 199976 kb
Host smart-0b70d877-d3e0-4600-bdc0-b469d39d5d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884545242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1884545242
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2765460752
Short name T414
Test name
Test status
Simulation time 1218495426 ps
CPU time 5.98 seconds
Started Jul 05 05:35:46 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 217724 kb
Host smart-e5dd89fa-90dd-44e9-a6c6-eb8e1dfdd02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765460752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2765460752
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1780948598
Short name T343
Test name
Test status
Simulation time 243652862 ps
CPU time 1.08 seconds
Started Jul 05 05:35:39 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 217528 kb
Host smart-958b89b6-7acb-4322-9dba-eab7e41f26f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780948598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1780948598
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1259198690
Short name T481
Test name
Test status
Simulation time 185370350 ps
CPU time 0.86 seconds
Started Jul 05 05:35:43 PM PDT 24
Finished Jul 05 05:35:44 PM PDT 24
Peak memory 199980 kb
Host smart-96394335-7765-4c16-b942-ed8b091268ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259198690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1259198690
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.472539881
Short name T410
Test name
Test status
Simulation time 1135782740 ps
CPU time 4.59 seconds
Started Jul 05 05:35:55 PM PDT 24
Finished Jul 05 05:36:00 PM PDT 24
Peak memory 200364 kb
Host smart-6959c624-028f-4d95-8ca0-b8c62cd601f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472539881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.472539881
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4082999312
Short name T156
Test name
Test status
Simulation time 147416649 ps
CPU time 1.17 seconds
Started Jul 05 05:35:42 PM PDT 24
Finished Jul 05 05:35:44 PM PDT 24
Peak memory 200156 kb
Host smart-3fde2d0d-c83c-471b-a06d-1b62415ca86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082999312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4082999312
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3351345710
Short name T373
Test name
Test status
Simulation time 197325900 ps
CPU time 1.42 seconds
Started Jul 05 05:35:39 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 200304 kb
Host smart-ac4ee3d0-b938-4d7a-8e0e-0e89c76e7968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351345710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3351345710
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2134788524
Short name T528
Test name
Test status
Simulation time 1697171036 ps
CPU time 6.49 seconds
Started Jul 05 05:35:41 PM PDT 24
Finished Jul 05 05:35:49 PM PDT 24
Peak memory 200424 kb
Host smart-45f25420-19a3-4be6-a686-f55ca5b21647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134788524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2134788524
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.463835921
Short name T268
Test name
Test status
Simulation time 267575816 ps
CPU time 1.81 seconds
Started Jul 05 05:35:38 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 200184 kb
Host smart-e2a7d87e-0244-4fa4-8efd-b626ebfbe9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463835921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.463835921
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1279670033
Short name T446
Test name
Test status
Simulation time 117327738 ps
CPU time 0.88 seconds
Started Jul 05 05:35:40 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 200124 kb
Host smart-4ee8adb7-a7dc-4070-b948-0a42318a2196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279670033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1279670033
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2515225481
Short name T249
Test name
Test status
Simulation time 68826648 ps
CPU time 0.82 seconds
Started Jul 05 05:35:50 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 199972 kb
Host smart-5999c68f-c4c6-4031-9fe5-20927a020f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515225481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2515225481
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.344010481
Short name T487
Test name
Test status
Simulation time 1220752986 ps
CPU time 5.78 seconds
Started Jul 05 05:35:48 PM PDT 24
Finished Jul 05 05:35:54 PM PDT 24
Peak memory 229952 kb
Host smart-e9181d94-19c9-4dc2-9932-990493d98a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344010481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.344010481
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.4234806537
Short name T141
Test name
Test status
Simulation time 243694389 ps
CPU time 1.1 seconds
Started Jul 05 05:35:51 PM PDT 24
Finished Jul 05 05:35:53 PM PDT 24
Peak memory 217560 kb
Host smart-bf311135-552d-4914-8490-3b2dc8336c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234806537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.4234806537
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.683468907
Short name T4
Test name
Test status
Simulation time 237789267 ps
CPU time 1.07 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 199968 kb
Host smart-c5167627-aa76-481b-804f-c0801a7b8a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683468907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.683468907
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2766291918
Short name T507
Test name
Test status
Simulation time 2004298046 ps
CPU time 8.04 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:09 PM PDT 24
Peak memory 200432 kb
Host smart-53283277-e6c8-4019-b7db-d11c4ecbd40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766291918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2766291918
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.578285372
Short name T262
Test name
Test status
Simulation time 145995946 ps
CPU time 1.1 seconds
Started Jul 05 05:35:50 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 200148 kb
Host smart-37f4f2aa-d7cc-4cd8-8bce-18b5acda33a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578285372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.578285372
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2932243686
Short name T37
Test name
Test status
Simulation time 243404805 ps
CPU time 1.47 seconds
Started Jul 05 05:35:46 PM PDT 24
Finished Jul 05 05:35:47 PM PDT 24
Peak memory 200376 kb
Host smart-27c7c595-fa8b-48df-a338-a0b653895e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932243686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2932243686
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2360553926
Short name T486
Test name
Test status
Simulation time 2494419825 ps
CPU time 13.82 seconds
Started Jul 05 05:35:50 PM PDT 24
Finished Jul 05 05:36:05 PM PDT 24
Peak memory 200488 kb
Host smart-29740b57-c6c5-4296-bacf-7414869ede76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360553926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2360553926
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3814890619
Short name T205
Test name
Test status
Simulation time 141914689 ps
CPU time 1.76 seconds
Started Jul 05 05:35:51 PM PDT 24
Finished Jul 05 05:35:54 PM PDT 24
Peak memory 208304 kb
Host smart-44b53685-2ab9-4862-8a3b-e18e31685fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814890619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3814890619
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2983385222
Short name T232
Test name
Test status
Simulation time 229698345 ps
CPU time 1.41 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 200160 kb
Host smart-53351ed8-102d-496e-bb1f-87dff088ba81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983385222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2983385222
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2727382487
Short name T403
Test name
Test status
Simulation time 55188531 ps
CPU time 0.72 seconds
Started Jul 05 05:35:50 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 199972 kb
Host smart-18d46262-77fd-4c81-827f-b9bca531037f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727382487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2727382487
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1914799709
Short name T431
Test name
Test status
Simulation time 1888880349 ps
CPU time 7.5 seconds
Started Jul 05 05:35:52 PM PDT 24
Finished Jul 05 05:36:00 PM PDT 24
Peak memory 221696 kb
Host smart-7bbc4a5d-7225-4c4a-a794-3af8b528b8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914799709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1914799709
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3854152177
Short name T465
Test name
Test status
Simulation time 244778061 ps
CPU time 1.11 seconds
Started Jul 05 05:35:47 PM PDT 24
Finished Jul 05 05:35:49 PM PDT 24
Peak memory 217520 kb
Host smart-c0d7548e-a862-46e8-b424-e70693fbed35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854152177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3854152177
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.905251396
Short name T473
Test name
Test status
Simulation time 120165852 ps
CPU time 0.83 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:35:50 PM PDT 24
Peak memory 199848 kb
Host smart-888893fc-c2b2-4973-82ad-0555a8267601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905251396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.905251396
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1991618326
Short name T247
Test name
Test status
Simulation time 1874624684 ps
CPU time 6.99 seconds
Started Jul 05 05:35:50 PM PDT 24
Finished Jul 05 05:35:58 PM PDT 24
Peak memory 200396 kb
Host smart-dd4b2062-492b-4069-883e-c57d9f828dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991618326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1991618326
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.379658733
Short name T532
Test name
Test status
Simulation time 149491083 ps
CPU time 1.11 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:02 PM PDT 24
Peak memory 200136 kb
Host smart-0171fe24-83eb-4df8-bcc1-47ee87285388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379658733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.379658733
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.186371070
Short name T188
Test name
Test status
Simulation time 248774564 ps
CPU time 1.57 seconds
Started Jul 05 05:35:48 PM PDT 24
Finished Jul 05 05:35:50 PM PDT 24
Peak memory 200368 kb
Host smart-c2a08213-ed54-4fe3-aa85-8158a1c7b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186371070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.186371070
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1831651329
Short name T246
Test name
Test status
Simulation time 9983772932 ps
CPU time 36.84 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:36:27 PM PDT 24
Peak memory 200432 kb
Host smart-9c1f808a-3253-4638-a86b-0f63046b4862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831651329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1831651329
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1210374893
Short name T157
Test name
Test status
Simulation time 147371137 ps
CPU time 1.81 seconds
Started Jul 05 05:35:48 PM PDT 24
Finished Jul 05 05:35:50 PM PDT 24
Peak memory 200132 kb
Host smart-a08c895d-3131-4d70-a411-ccca527b83e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210374893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1210374893
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.4178935697
Short name T501
Test name
Test status
Simulation time 130993209 ps
CPU time 1.05 seconds
Started Jul 05 05:35:51 PM PDT 24
Finished Jul 05 05:35:53 PM PDT 24
Peak memory 200080 kb
Host smart-5871650a-b0ee-4287-9aa0-8e523554086b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178935697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.4178935697
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2512848377
Short name T409
Test name
Test status
Simulation time 75166364 ps
CPU time 0.85 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 199856 kb
Host smart-6a0a57e2-1354-42f9-80f5-8c082b0599d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512848377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2512848377
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3368623158
Short name T47
Test name
Test status
Simulation time 1229780692 ps
CPU time 5.6 seconds
Started Jul 05 05:35:51 PM PDT 24
Finished Jul 05 05:35:57 PM PDT 24
Peak memory 221632 kb
Host smart-f35fe5e7-3bc3-424c-9733-e9443777488b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368623158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3368623158
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2789901601
Short name T511
Test name
Test status
Simulation time 243904239 ps
CPU time 1.15 seconds
Started Jul 05 05:35:47 PM PDT 24
Finished Jul 05 05:35:49 PM PDT 24
Peak memory 217544 kb
Host smart-4aac2bf9-86f1-48f6-b706-2b0c9dd74441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789901601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2789901601
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1276269457
Short name T497
Test name
Test status
Simulation time 113410910 ps
CPU time 0.8 seconds
Started Jul 05 05:35:51 PM PDT 24
Finished Jul 05 05:35:53 PM PDT 24
Peak memory 199980 kb
Host smart-31f6bc02-47cc-44d0-9374-396cb65802c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276269457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1276269457
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.4249618582
Short name T307
Test name
Test status
Simulation time 1053118521 ps
CPU time 4.82 seconds
Started Jul 05 05:35:52 PM PDT 24
Finished Jul 05 05:35:58 PM PDT 24
Peak memory 200488 kb
Host smart-3e493793-acaa-476c-b326-416437375040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249618582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4249618582
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2510895888
Short name T243
Test name
Test status
Simulation time 179613325 ps
CPU time 1.26 seconds
Started Jul 05 05:35:50 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 200148 kb
Host smart-54d27493-2a80-4142-bf84-9f81b3aa0df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510895888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2510895888
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1601397200
Short name T387
Test name
Test status
Simulation time 120855954 ps
CPU time 1.2 seconds
Started Jul 05 05:35:48 PM PDT 24
Finished Jul 05 05:35:50 PM PDT 24
Peak memory 200376 kb
Host smart-94c4dde4-19f9-40ee-93a4-b22177b05001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601397200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1601397200
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.351760024
Short name T437
Test name
Test status
Simulation time 4494686645 ps
CPU time 16.38 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:36:07 PM PDT 24
Peak memory 208632 kb
Host smart-33a972f0-b1d7-4e3c-ad7e-da2118e49971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351760024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.351760024
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.665933199
Short name T438
Test name
Test status
Simulation time 363744850 ps
CPU time 2.45 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:35:53 PM PDT 24
Peak memory 200204 kb
Host smart-c0c97164-5d2d-4d15-a6da-31ed3df4e7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665933199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.665933199
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2193528356
Short name T177
Test name
Test status
Simulation time 80162267 ps
CPU time 0.83 seconds
Started Jul 05 05:35:53 PM PDT 24
Finished Jul 05 05:35:54 PM PDT 24
Peak memory 200188 kb
Host smart-95d32217-2bed-48dc-822f-37a383b17581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193528356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2193528356
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3637725188
Short name T357
Test name
Test status
Simulation time 69827875 ps
CPU time 0.77 seconds
Started Jul 05 05:35:50 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 199920 kb
Host smart-cb5f1f21-ead0-4564-86a6-fdaeee66da59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637725188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3637725188
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.603071412
Short name T28
Test name
Test status
Simulation time 2177180406 ps
CPU time 8.57 seconds
Started Jul 05 05:35:59 PM PDT 24
Finished Jul 05 05:36:09 PM PDT 24
Peak memory 217864 kb
Host smart-3e8b9df1-1312-499c-a27e-f53d2341dda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603071412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.603071412
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3046424898
Short name T408
Test name
Test status
Simulation time 244360953 ps
CPU time 1.12 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:35:51 PM PDT 24
Peak memory 217504 kb
Host smart-778ca80d-7803-4333-ad97-0abedf4080dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046424898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3046424898
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.4160147520
Short name T498
Test name
Test status
Simulation time 209528031 ps
CPU time 0.97 seconds
Started Jul 05 05:35:50 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 199968 kb
Host smart-e084d034-a700-4061-807f-e08ba0b7efb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160147520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.4160147520
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2894417203
Short name T186
Test name
Test status
Simulation time 1413292830 ps
CPU time 5.56 seconds
Started Jul 05 05:35:48 PM PDT 24
Finished Jul 05 05:35:54 PM PDT 24
Peak memory 200440 kb
Host smart-a1d11b18-11cb-4961-b5c8-b1fc051f83df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894417203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2894417203
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2251389562
Short name T509
Test name
Test status
Simulation time 154204473 ps
CPU time 1.17 seconds
Started Jul 05 05:35:50 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 200080 kb
Host smart-06cf60b5-c8d6-4a3b-a264-129e81df562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251389562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2251389562
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4082443009
Short name T163
Test name
Test status
Simulation time 195486581 ps
CPU time 1.42 seconds
Started Jul 05 05:35:49 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 200372 kb
Host smart-206ad7a7-55e9-4edc-915b-1b9d5c314027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082443009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4082443009
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.4009704454
Short name T22
Test name
Test status
Simulation time 8236840543 ps
CPU time 28.76 seconds
Started Jul 05 05:35:47 PM PDT 24
Finished Jul 05 05:36:16 PM PDT 24
Peak memory 209604 kb
Host smart-bf9921bb-4a7f-49aa-9382-13d34fa0c5f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009704454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.4009704454
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.681253262
Short name T276
Test name
Test status
Simulation time 147956817 ps
CPU time 1.75 seconds
Started Jul 05 05:35:46 PM PDT 24
Finished Jul 05 05:35:49 PM PDT 24
Peak memory 200104 kb
Host smart-0572c9fc-87cb-4961-a235-9e4347230098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681253262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.681253262
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.228996376
Short name T300
Test name
Test status
Simulation time 94078675 ps
CPU time 0.97 seconds
Started Jul 05 05:36:00 PM PDT 24
Finished Jul 05 05:36:02 PM PDT 24
Peak memory 200144 kb
Host smart-0e67ddb9-1a4c-47fd-a025-3681d4ca4011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228996376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.228996376
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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