Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7911

1

T3

18

T5

30

T7

9

auto[1]

10672

1

T1

1

T2

1

T3

83

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5708	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6333	1			T1	1		T2	1		T3	27
reset_info_cp[2]	2881	1			T3	16		T4	1		T5	11
reset_info_cp[4]	3717	1			T3	17		T4	1		T5	10
reset_info_cp[8]	123	1			T9	1		T26	1		T81	2
reset_info_cp[16]	116	1			T3	2		T21	1		T23	1
reset_info_cp[32]	104	1			T26	1		T84	1		T29	1
reset_info_cp[64]	109	1			T3	2		T5	1		T102	1
reset_info_cp[128]	111	1			T9	1		T81	3		T29	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3041	1			T3	18		T5	14		T8	9
reset_info_cp[1]	auto[1]	2673	1			T3	8		T4	1		T5	5
reset_info_cp[2]	auto[0]	893	1			T5	4		T8	6		T24	3
reset_info_cp[2]	auto[1]	1988	1			T3	16		T4	1		T5	7
reset_info_cp[4]	auto[0]	1356	1			T5	5		T8	5		T24	9
reset_info_cp[4]	auto[1]	2361	1			T3	17		T4	1		T5	5
reset_info_cp[8]	auto[0]	51	1			T26	1		T84	1		T86	3
reset_info_cp[8]	auto[1]	72	1			T9	1		T81	2		T29	1
reset_info_cp[16]	auto[0]	47	1			T23	1		T55	1		T112	1
reset_info_cp[16]	auto[1]	69	1			T3	2		T21	1		T81	1
reset_info_cp[32]	auto[0]	39	1			T84	1		T55	2		T137	1
reset_info_cp[32]	auto[1]	65	1			T26	1		T29	1		T53	1
reset_info_cp[64]	auto[0]	50	1			T5	1		T102	1		T137	1
reset_info_cp[64]	auto[1]	59	1			T3	2		T33	2		T85	1
reset_info_cp[128]	auto[0]	44	1			T85	1		T111	1		T112	1
reset_info_cp[128]	auto[1]	67	1			T9	1		T81	3		T29	2