Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 619
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/43.rstmgr_smoke.1933332955 Jul 06 05:06:18 PM PDT 24 Jul 06 05:06:20 PM PDT 24 199828677 ps
T539 /workspace/coverage/default/29.rstmgr_reset.3386170244 Jul 06 05:05:50 PM PDT 24 Jul 06 05:05:55 PM PDT 24 998531348 ps
T540 /workspace/coverage/default/12.rstmgr_reset.3089868841 Jul 06 05:05:13 PM PDT 24 Jul 06 05:05:18 PM PDT 24 850254827 ps
T541 /workspace/coverage/default/7.rstmgr_smoke.3366941254 Jul 06 05:05:09 PM PDT 24 Jul 06 05:05:10 PM PDT 24 107980847 ps
T59 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2797702252 Jul 06 05:04:48 PM PDT 24 Jul 06 05:04:52 PM PDT 24 910796722 ps
T64 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1322936530 Jul 06 05:04:39 PM PDT 24 Jul 06 05:04:43 PM PDT 24 484369290 ps
T60 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1601577149 Jul 06 05:04:33 PM PDT 24 Jul 06 05:04:42 PM PDT 24 1558458663 ps
T61 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3356746025 Jul 06 05:04:30 PM PDT 24 Jul 06 05:04:31 PM PDT 24 67189062 ps
T62 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2167534354 Jul 06 05:04:51 PM PDT 24 Jul 06 05:04:53 PM PDT 24 172833414 ps
T114 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2385917240 Jul 06 05:04:52 PM PDT 24 Jul 06 05:04:53 PM PDT 24 89164979 ps
T66 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2359159301 Jul 06 05:04:33 PM PDT 24 Jul 06 05:04:37 PM PDT 24 896912961 ps
T65 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1092026158 Jul 06 05:04:33 PM PDT 24 Jul 06 05:04:35 PM PDT 24 210447834 ps
T93 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.159775307 Jul 06 05:04:26 PM PDT 24 Jul 06 05:04:28 PM PDT 24 502025349 ps
T67 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2956456080 Jul 06 05:04:42 PM PDT 24 Jul 06 05:04:46 PM PDT 24 798912240 ps
T115 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2032447495 Jul 06 05:04:26 PM PDT 24 Jul 06 05:04:27 PM PDT 24 73897471 ps
T94 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.465556436 Jul 06 05:04:30 PM PDT 24 Jul 06 05:04:33 PM PDT 24 875953675 ps
T116 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3745782917 Jul 06 05:04:46 PM PDT 24 Jul 06 05:04:48 PM PDT 24 114036202 ps
T98 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3394575997 Jul 06 05:04:35 PM PDT 24 Jul 06 05:04:38 PM PDT 24 410791334 ps
T117 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1332538531 Jul 06 05:04:50 PM PDT 24 Jul 06 05:04:51 PM PDT 24 148439518 ps
T95 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.882476946 Jul 06 05:04:52 PM PDT 24 Jul 06 05:04:55 PM PDT 24 458787015 ps
T96 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3920938983 Jul 06 05:04:51 PM PDT 24 Jul 06 05:04:53 PM PDT 24 149247522 ps
T97 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3634932026 Jul 06 05:04:35 PM PDT 24 Jul 06 05:04:38 PM PDT 24 131238751 ps
T542 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1121833212 Jul 06 05:04:32 PM PDT 24 Jul 06 05:04:33 PM PDT 24 90856112 ps
T99 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2384622740 Jul 06 05:04:32 PM PDT 24 Jul 06 05:04:35 PM PDT 24 299325385 ps
T100 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.870564374 Jul 06 05:04:46 PM PDT 24 Jul 06 05:04:47 PM PDT 24 119446445 ps
T128 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3025350498 Jul 06 05:04:33 PM PDT 24 Jul 06 05:04:38 PM PDT 24 670496245 ps
T118 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.971795464 Jul 06 05:04:39 PM PDT 24 Jul 06 05:04:40 PM PDT 24 86398618 ps
T543 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3983488262 Jul 06 05:04:52 PM PDT 24 Jul 06 05:04:53 PM PDT 24 194566047 ps
T544 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2225622938 Jul 06 05:04:43 PM PDT 24 Jul 06 05:04:44 PM PDT 24 127207398 ps
T545 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2809981781 Jul 06 05:04:47 PM PDT 24 Jul 06 05:04:48 PM PDT 24 128523477 ps
T129 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1367941284 Jul 06 05:04:50 PM PDT 24 Jul 06 05:04:53 PM PDT 24 226536807 ps
T119 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2578500081 Jul 06 05:04:45 PM PDT 24 Jul 06 05:04:47 PM PDT 24 83482840 ps
T126 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2977855583 Jul 06 05:04:41 PM PDT 24 Jul 06 05:04:43 PM PDT 24 508741478 ps
T546 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1953242790 Jul 06 05:04:46 PM PDT 24 Jul 06 05:04:48 PM PDT 24 231191117 ps
T547 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1212716630 Jul 06 05:04:34 PM PDT 24 Jul 06 05:04:36 PM PDT 24 124483634 ps
T548 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4172762603 Jul 06 05:04:51 PM PDT 24 Jul 06 05:04:53 PM PDT 24 191276982 ps
T125 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2457815769 Jul 06 05:04:35 PM PDT 24 Jul 06 05:04:39 PM PDT 24 949878497 ps
T549 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3042617335 Jul 06 05:04:41 PM PDT 24 Jul 06 05:04:44 PM PDT 24 411953448 ps
T550 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.267775728 Jul 06 05:04:36 PM PDT 24 Jul 06 05:04:38 PM PDT 24 129029064 ps
T551 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1304491140 Jul 06 05:04:41 PM PDT 24 Jul 06 05:04:42 PM PDT 24 73115895 ps
T552 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2131381958 Jul 06 05:04:36 PM PDT 24 Jul 06 05:04:38 PM PDT 24 157288863 ps
T553 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2297205306 Jul 06 05:04:30 PM PDT 24 Jul 06 05:04:32 PM PDT 24 136779247 ps
T554 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2444937171 Jul 06 05:04:53 PM PDT 24 Jul 06 05:04:56 PM PDT 24 403942589 ps
T555 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2156657865 Jul 06 05:04:47 PM PDT 24 Jul 06 05:04:50 PM PDT 24 876993186 ps
T556 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2650909169 Jul 06 05:04:50 PM PDT 24 Jul 06 05:04:52 PM PDT 24 108329073 ps
T120 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2208111232 Jul 06 05:04:53 PM PDT 24 Jul 06 05:04:55 PM PDT 24 138494531 ps
T121 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.4104244237 Jul 06 05:04:36 PM PDT 24 Jul 06 05:04:38 PM PDT 24 67623783 ps
T557 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1877905044 Jul 06 05:04:48 PM PDT 24 Jul 06 05:04:50 PM PDT 24 79943561 ps
T122 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.176270769 Jul 06 05:04:48 PM PDT 24 Jul 06 05:04:50 PM PDT 24 128121763 ps
T123 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1665412712 Jul 06 05:04:50 PM PDT 24 Jul 06 05:04:51 PM PDT 24 87072186 ps
T558 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.421031656 Jul 06 05:04:46 PM PDT 24 Jul 06 05:04:48 PM PDT 24 120069797 ps
T134 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.624548543 Jul 06 05:04:36 PM PDT 24 Jul 06 05:04:38 PM PDT 24 468115637 ps
T559 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.648587342 Jul 06 05:04:39 PM PDT 24 Jul 06 05:04:42 PM PDT 24 498072430 ps
T560 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1119396877 Jul 06 05:04:36 PM PDT 24 Jul 06 05:04:37 PM PDT 24 138736344 ps
T561 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1911892136 Jul 06 05:04:41 PM PDT 24 Jul 06 05:04:43 PM PDT 24 103613153 ps
T562 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1334511012 Jul 06 05:04:31 PM PDT 24 Jul 06 05:04:33 PM PDT 24 154208146 ps
T563 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1328650236 Jul 06 05:04:33 PM PDT 24 Jul 06 05:04:35 PM PDT 24 234778069 ps
T135 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3598355935 Jul 06 05:04:45 PM PDT 24 Jul 06 05:04:49 PM PDT 24 764375263 ps
T564 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3099509411 Jul 06 05:04:44 PM PDT 24 Jul 06 05:04:46 PM PDT 24 209692101 ps
T127 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1405821215 Jul 06 05:04:47 PM PDT 24 Jul 06 05:04:49 PM PDT 24 488542178 ps
T124 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3294685086 Jul 06 05:04:55 PM PDT 24 Jul 06 05:04:59 PM PDT 24 971199748 ps
T565 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3557616812 Jul 06 05:04:35 PM PDT 24 Jul 06 05:04:36 PM PDT 24 108398747 ps
T566 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.207503621 Jul 06 05:04:31 PM PDT 24 Jul 06 05:04:35 PM PDT 24 416368536 ps
T567 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3194113538 Jul 06 05:04:37 PM PDT 24 Jul 06 05:04:39 PM PDT 24 136065323 ps
T568 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1980303894 Jul 06 05:04:31 PM PDT 24 Jul 06 05:04:33 PM PDT 24 113402833 ps
T569 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2421746801 Jul 06 05:04:33 PM PDT 24 Jul 06 05:04:35 PM PDT 24 144947522 ps
T570 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2854292528 Jul 06 05:04:26 PM PDT 24 Jul 06 05:04:28 PM PDT 24 134242773 ps
T571 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3296708528 Jul 06 05:04:53 PM PDT 24 Jul 06 05:04:54 PM PDT 24 90575336 ps
T572 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.598863109 Jul 06 05:04:32 PM PDT 24 Jul 06 05:04:41 PM PDT 24 1995457850 ps
T573 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3719870175 Jul 06 05:04:48 PM PDT 24 Jul 06 05:04:49 PM PDT 24 117738193 ps
T133 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1731976910 Jul 06 05:04:35 PM PDT 24 Jul 06 05:04:38 PM PDT 24 780741629 ps
T574 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.643917074 Jul 06 05:04:51 PM PDT 24 Jul 06 05:04:52 PM PDT 24 78290906 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4093818637 Jul 06 05:04:31 PM PDT 24 Jul 06 05:04:32 PM PDT 24 83238988 ps
T576 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2379443854 Jul 06 05:04:47 PM PDT 24 Jul 06 05:04:49 PM PDT 24 239031220 ps
T577 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1306138924 Jul 06 05:04:35 PM PDT 24 Jul 06 05:04:36 PM PDT 24 79581629 ps
T578 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2729159383 Jul 06 05:04:49 PM PDT 24 Jul 06 05:04:53 PM PDT 24 1085416000 ps
T579 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3616804050 Jul 06 05:04:35 PM PDT 24 Jul 06 05:04:37 PM PDT 24 103027082 ps
T580 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3535029537 Jul 06 05:04:53 PM PDT 24 Jul 06 05:04:55 PM PDT 24 194109014 ps
T581 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3332422682 Jul 06 05:04:36 PM PDT 24 Jul 06 05:04:38 PM PDT 24 67990783 ps
T582 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.84309043 Jul 06 05:04:47 PM PDT 24 Jul 06 05:04:49 PM PDT 24 472960982 ps
T583 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3537525522 Jul 06 05:04:53 PM PDT 24 Jul 06 05:04:55 PM PDT 24 106117482 ps
T584 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3832435132 Jul 06 05:04:41 PM PDT 24 Jul 06 05:04:44 PM PDT 24 121949720 ps
T585 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1088316150 Jul 06 05:04:36 PM PDT 24 Jul 06 05:04:41 PM PDT 24 809793658 ps
T586 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.700411589 Jul 06 05:04:52 PM PDT 24 Jul 06 05:04:56 PM PDT 24 511125518 ps
T587 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3623761237 Jul 06 05:04:26 PM PDT 24 Jul 06 05:04:31 PM PDT 24 805488264 ps
T588 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1084771943 Jul 06 05:04:41 PM PDT 24 Jul 06 05:04:43 PM PDT 24 122617142 ps
T589 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2244326076 Jul 06 05:04:53 PM PDT 24 Jul 06 05:04:55 PM PDT 24 113745061 ps
T590 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1779882371 Jul 06 05:04:33 PM PDT 24 Jul 06 05:04:35 PM PDT 24 228828871 ps
T591 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2289007828 Jul 06 05:04:32 PM PDT 24 Jul 06 05:04:34 PM PDT 24 89982658 ps
T104 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.261730862 Jul 06 05:04:31 PM PDT 24 Jul 06 05:04:34 PM PDT 24 402370255 ps
T105 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2099260938 Jul 06 05:04:26 PM PDT 24 Jul 06 05:04:28 PM PDT 24 102025264 ps
T592 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1380873752 Jul 06 05:04:51 PM PDT 24 Jul 06 05:04:55 PM PDT 24 874789801 ps
T593 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1645818404 Jul 06 05:04:48 PM PDT 24 Jul 06 05:04:49 PM PDT 24 68704045 ps
T594 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3699046589 Jul 06 05:04:42 PM PDT 24 Jul 06 05:04:45 PM PDT 24 295663252 ps
T595 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1001890825 Jul 06 05:04:47 PM PDT 24 Jul 06 05:04:49 PM PDT 24 297783575 ps
T596 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3807315836 Jul 06 05:04:33 PM PDT 24 Jul 06 05:04:35 PM PDT 24 113494025 ps
T597 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.904510564 Jul 06 05:04:31 PM PDT 24 Jul 06 05:04:32 PM PDT 24 113036263 ps
T598 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3136453592 Jul 06 05:04:45 PM PDT 24 Jul 06 05:04:47 PM PDT 24 194155927 ps
T599 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2974267187 Jul 06 05:04:55 PM PDT 24 Jul 06 05:04:57 PM PDT 24 424453225 ps
T600 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.498227728 Jul 06 05:04:42 PM PDT 24 Jul 06 05:04:44 PM PDT 24 86689222 ps
T601 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.8434753 Jul 06 05:04:30 PM PDT 24 Jul 06 05:04:32 PM PDT 24 90577631 ps
T602 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2619820017 Jul 06 05:04:51 PM PDT 24 Jul 06 05:04:53 PM PDT 24 76526663 ps
T603 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.4000209822 Jul 06 05:04:36 PM PDT 24 Jul 06 05:04:38 PM PDT 24 207440902 ps
T604 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.848724129 Jul 06 05:04:26 PM PDT 24 Jul 06 05:04:27 PM PDT 24 88404779 ps
T605 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4129250239 Jul 06 05:04:48 PM PDT 24 Jul 06 05:04:49 PM PDT 24 77785444 ps
T606 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.361739558 Jul 06 05:04:45 PM PDT 24 Jul 06 05:04:47 PM PDT 24 77737677 ps
T607 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.971152987 Jul 06 05:04:41 PM PDT 24 Jul 06 05:04:42 PM PDT 24 124735302 ps
T608 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1528161461 Jul 06 05:04:34 PM PDT 24 Jul 06 05:04:36 PM PDT 24 111234631 ps
T609 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1886260395 Jul 06 05:04:36 PM PDT 24 Jul 06 05:04:38 PM PDT 24 88069992 ps
T610 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.612331671 Jul 06 05:04:41 PM PDT 24 Jul 06 05:04:43 PM PDT 24 75147066 ps
T611 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3702916649 Jul 06 05:04:31 PM PDT 24 Jul 06 05:04:34 PM PDT 24 354112939 ps
T612 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.938035804 Jul 06 05:04:33 PM PDT 24 Jul 06 05:04:37 PM PDT 24 275564907 ps
T613 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2200353676 Jul 06 05:04:53 PM PDT 24 Jul 06 05:04:55 PM PDT 24 90109028 ps
T614 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1933733687 Jul 06 05:04:46 PM PDT 24 Jul 06 05:04:49 PM PDT 24 171289097 ps
T615 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1758422958 Jul 06 05:04:48 PM PDT 24 Jul 06 05:04:49 PM PDT 24 87105031 ps
T616 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1463963300 Jul 06 05:04:48 PM PDT 24 Jul 06 05:04:49 PM PDT 24 94357347 ps
T617 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.64504293 Jul 06 05:04:53 PM PDT 24 Jul 06 05:04:54 PM PDT 24 75111417 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1660007647 Jul 06 05:04:33 PM PDT 24 Jul 06 05:04:35 PM PDT 24 129780305 ps
T619 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1410175531 Jul 06 05:04:49 PM PDT 24 Jul 06 05:04:52 PM PDT 24 195121393 ps

Test location /workspace/coverage/default/9.rstmgr_reset.2265949719
Short name T5
Test name
Test status
Simulation time 1827885165 ps
CPU time 6.53 seconds
Started Jul 06 05:05:13 PM PDT 24
Finished Jul 06 05:05:20 PM PDT 24
Peak memory 200444 kb
Host smart-c88f6d26-a500-4123-84c6-0122491690ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265949719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2265949719
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1818739064
Short name T28
Test name
Test status
Simulation time 379912784 ps
CPU time 2.32 seconds
Started Jul 06 05:05:43 PM PDT 24
Finished Jul 06 05:05:46 PM PDT 24
Peak memory 208380 kb
Host smart-19e17017-c66e-49f5-820a-e296d5e13dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818739064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1818739064
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2359159301
Short name T66
Test name
Test status
Simulation time 896912961 ps
CPU time 3.3 seconds
Started Jul 06 05:04:33 PM PDT 24
Finished Jul 06 05:04:37 PM PDT 24
Peak memory 200392 kb
Host smart-917e78fd-5b3a-45e2-b718-c2b0c1888191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359159301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2359159301
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.753544916
Short name T9
Test name
Test status
Simulation time 2355375045 ps
CPU time 9.49 seconds
Started Jul 06 05:06:08 PM PDT 24
Finished Jul 06 05:06:18 PM PDT 24
Peak memory 221784 kb
Host smart-6f9aa4c0-1084-4ea7-aed2-7f7081a135f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753544916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.753544916
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3373210520
Short name T70
Test name
Test status
Simulation time 16507158218 ps
CPU time 28.8 seconds
Started Jul 06 05:04:53 PM PDT 24
Finished Jul 06 05:05:22 PM PDT 24
Peak memory 218444 kb
Host smart-ae3da323-c138-4707-8ce8-de5ec60004a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373210520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3373210520
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3634932026
Short name T97
Test name
Test status
Simulation time 131238751 ps
CPU time 1.87 seconds
Started Jul 06 05:04:35 PM PDT 24
Finished Jul 06 05:04:38 PM PDT 24
Peak memory 210860 kb
Host smart-6bc80ebe-6311-4288-8a0e-633a063eb788
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634932026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3634932026
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2594727009
Short name T55
Test name
Test status
Simulation time 8991218179 ps
CPU time 32.53 seconds
Started Jul 06 05:05:52 PM PDT 24
Finished Jul 06 05:06:25 PM PDT 24
Peak memory 208604 kb
Host smart-4ba57cee-7824-48b2-a930-45c47951f8d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594727009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2594727009
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2254705635
Short name T144
Test name
Test status
Simulation time 72230411 ps
CPU time 0.88 seconds
Started Jul 06 05:05:02 PM PDT 24
Finished Jul 06 05:05:04 PM PDT 24
Peak memory 199884 kb
Host smart-9504e6bf-4375-40bc-a8df-ccbd51f29ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254705635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2254705635
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1452134069
Short name T89
Test name
Test status
Simulation time 6052449147 ps
CPU time 25.08 seconds
Started Jul 06 05:06:15 PM PDT 24
Finished Jul 06 05:06:41 PM PDT 24
Peak memory 210180 kb
Host smart-ed5810b4-7d0a-4746-9f31-95bc1e141022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452134069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1452134069
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.4261588237
Short name T30
Test name
Test status
Simulation time 1225668656 ps
CPU time 5.5 seconds
Started Jul 06 05:05:52 PM PDT 24
Finished Jul 06 05:05:58 PM PDT 24
Peak memory 217700 kb
Host smart-a3d511ee-a1f8-4413-9a2c-935661b9ed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261588237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.4261588237
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3722165393
Short name T145
Test name
Test status
Simulation time 143231990 ps
CPU time 1.13 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:04:59 PM PDT 24
Peak memory 200136 kb
Host smart-8c8f7b40-5b13-44c5-b0c7-1f442c24256d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722165393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3722165393
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2956456080
Short name T67
Test name
Test status
Simulation time 798912240 ps
CPU time 2.88 seconds
Started Jul 06 05:04:42 PM PDT 24
Finished Jul 06 05:04:46 PM PDT 24
Peak memory 200384 kb
Host smart-e0ee858d-416b-4daa-8689-aed77b0eb7fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956456080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2956456080
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1406415930
Short name T47
Test name
Test status
Simulation time 1224007425 ps
CPU time 5.7 seconds
Started Jul 06 05:06:22 PM PDT 24
Finished Jul 06 05:06:28 PM PDT 24
Peak memory 217868 kb
Host smart-c2b80be7-2611-4baf-8603-40fbfb0d69c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406415930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1406415930
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1585854764
Short name T86
Test name
Test status
Simulation time 130275597 ps
CPU time 1.19 seconds
Started Jul 06 05:04:52 PM PDT 24
Finished Jul 06 05:04:54 PM PDT 24
Peak memory 200016 kb
Host smart-3026a446-deb3-4e19-9faa-1b0e607e4a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585854764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1585854764
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2032447495
Short name T115
Test name
Test status
Simulation time 73897471 ps
CPU time 0.85 seconds
Started Jul 06 05:04:26 PM PDT 24
Finished Jul 06 05:04:27 PM PDT 24
Peak memory 200196 kb
Host smart-cf6080b1-4274-4f0c-8679-4b5961704748
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032447495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2032447495
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2066250809
Short name T17
Test name
Test status
Simulation time 233655869 ps
CPU time 0.96 seconds
Started Jul 06 05:05:18 PM PDT 24
Finished Jul 06 05:05:20 PM PDT 24
Peak memory 199972 kb
Host smart-f801f56d-4945-43f0-a353-1bc253027029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066250809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2066250809
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.159775307
Short name T93
Test name
Test status
Simulation time 502025349 ps
CPU time 1.92 seconds
Started Jul 06 05:04:26 PM PDT 24
Finished Jul 06 05:04:28 PM PDT 24
Peak memory 200480 kb
Host smart-ea5b7cf7-2004-40bd-9036-0a610e4b882f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159775307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
159775307
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1405821215
Short name T127
Test name
Test status
Simulation time 488542178 ps
CPU time 1.85 seconds
Started Jul 06 05:04:47 PM PDT 24
Finished Jul 06 05:04:49 PM PDT 24
Peak memory 200496 kb
Host smart-9d57593c-06b0-4689-8533-97cd2bf71838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405821215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1405821215
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3359072869
Short name T241
Test name
Test status
Simulation time 2282100222 ps
CPU time 10.86 seconds
Started Jul 06 05:05:22 PM PDT 24
Finished Jul 06 05:05:33 PM PDT 24
Peak memory 208600 kb
Host smart-1b33acbd-f0ef-489e-834c-bf600b0d8006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359072869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3359072869
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2099260938
Short name T105
Test name
Test status
Simulation time 102025264 ps
CPU time 1.35 seconds
Started Jul 06 05:04:26 PM PDT 24
Finished Jul 06 05:04:28 PM PDT 24
Peak memory 200304 kb
Host smart-79c17f10-ddb6-4f88-bd58-4a0a9ec8c8f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099260938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
099260938
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3623761237
Short name T587
Test name
Test status
Simulation time 805488264 ps
CPU time 4.36 seconds
Started Jul 06 05:04:26 PM PDT 24
Finished Jul 06 05:04:31 PM PDT 24
Peak memory 200500 kb
Host smart-c63f5a29-113f-4aee-bff6-819f6f6c9b97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623761237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
623761237
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.848724129
Short name T604
Test name
Test status
Simulation time 88404779 ps
CPU time 0.82 seconds
Started Jul 06 05:04:26 PM PDT 24
Finished Jul 06 05:04:27 PM PDT 24
Peak memory 200184 kb
Host smart-9c472889-931e-4d2b-bd2e-2cbbde6a6189
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848724129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.848724129
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.904510564
Short name T597
Test name
Test status
Simulation time 113036263 ps
CPU time 0.95 seconds
Started Jul 06 05:04:31 PM PDT 24
Finished Jul 06 05:04:32 PM PDT 24
Peak memory 200376 kb
Host smart-44fd91e7-9550-4b5e-bdc3-22d0b08ddf62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904510564 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.904510564
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2854292528
Short name T570
Test name
Test status
Simulation time 134242773 ps
CPU time 1.26 seconds
Started Jul 06 05:04:26 PM PDT 24
Finished Jul 06 05:04:28 PM PDT 24
Peak memory 200368 kb
Host smart-4db98303-e283-4797-8ac8-de09b1116dbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854292528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2854292528
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2384622740
Short name T99
Test name
Test status
Simulation time 299325385 ps
CPU time 2.27 seconds
Started Jul 06 05:04:32 PM PDT 24
Finished Jul 06 05:04:35 PM PDT 24
Peak memory 208432 kb
Host smart-c49ba1e7-4bda-4ca1-a1c1-601d98e6bdb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384622740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2384622740
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.261730862
Short name T104
Test name
Test status
Simulation time 402370255 ps
CPU time 2.68 seconds
Started Jul 06 05:04:31 PM PDT 24
Finished Jul 06 05:04:34 PM PDT 24
Peak memory 200396 kb
Host smart-9da41686-3f4e-4c74-b40d-c71e8c1427a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261730862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.261730862
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.938035804
Short name T612
Test name
Test status
Simulation time 275564907 ps
CPU time 3.23 seconds
Started Jul 06 05:04:33 PM PDT 24
Finished Jul 06 05:04:37 PM PDT 24
Peak memory 200484 kb
Host smart-db94f20f-26cb-46f9-b3e5-4791262de727
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938035804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.938035804
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.8434753
Short name T601
Test name
Test status
Simulation time 90577631 ps
CPU time 0.89 seconds
Started Jul 06 05:04:30 PM PDT 24
Finished Jul 06 05:04:32 PM PDT 24
Peak memory 200272 kb
Host smart-fff290ff-9a7b-4830-8895-eb1e57e7b204
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8434753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.8434753
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1660007647
Short name T618
Test name
Test status
Simulation time 129780305 ps
CPU time 1.12 seconds
Started Jul 06 05:04:33 PM PDT 24
Finished Jul 06 05:04:35 PM PDT 24
Peak memory 200332 kb
Host smart-6d651067-e1e0-4845-8761-ce779abfdcda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660007647 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1660007647
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4093818637
Short name T575
Test name
Test status
Simulation time 83238988 ps
CPU time 0.87 seconds
Started Jul 06 05:04:31 PM PDT 24
Finished Jul 06 05:04:32 PM PDT 24
Peak memory 200288 kb
Host smart-ef6e147a-fde6-42fc-af17-8a39f3f77273
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093818637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.4093818637
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1328650236
Short name T563
Test name
Test status
Simulation time 234778069 ps
CPU time 1.67 seconds
Started Jul 06 05:04:33 PM PDT 24
Finished Jul 06 05:04:35 PM PDT 24
Peak memory 200480 kb
Host smart-9e728011-6a72-4cd7-b60a-e8933e04763d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328650236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1328650236
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.207503621
Short name T566
Test name
Test status
Simulation time 416368536 ps
CPU time 3.34 seconds
Started Jul 06 05:04:31 PM PDT 24
Finished Jul 06 05:04:35 PM PDT 24
Peak memory 200472 kb
Host smart-2729b7ff-41c2-47e6-828c-30a46c2dc573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207503621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.207503621
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.465556436
Short name T94
Test name
Test status
Simulation time 875953675 ps
CPU time 3.08 seconds
Started Jul 06 05:04:30 PM PDT 24
Finished Jul 06 05:04:33 PM PDT 24
Peak memory 200364 kb
Host smart-4ce0e1bb-cada-457c-a14a-30820a891013
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465556436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
465556436
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1911892136
Short name T561
Test name
Test status
Simulation time 103613153 ps
CPU time 0.9 seconds
Started Jul 06 05:04:41 PM PDT 24
Finished Jul 06 05:04:43 PM PDT 24
Peak memory 200324 kb
Host smart-0c77a181-b5ca-4c35-a105-415b357d459c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911892136 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1911892136
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1665412712
Short name T123
Test name
Test status
Simulation time 87072186 ps
CPU time 0.99 seconds
Started Jul 06 05:04:50 PM PDT 24
Finished Jul 06 05:04:51 PM PDT 24
Peak memory 200260 kb
Host smart-bbe074d1-179e-41fd-8850-352197bc1c8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665412712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1665412712
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3099509411
Short name T564
Test name
Test status
Simulation time 209692101 ps
CPU time 1.36 seconds
Started Jul 06 05:04:44 PM PDT 24
Finished Jul 06 05:04:46 PM PDT 24
Peak memory 200552 kb
Host smart-10a59eda-1082-450d-b0d0-380d37db795c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099509411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3099509411
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1367941284
Short name T129
Test name
Test status
Simulation time 226536807 ps
CPU time 3.13 seconds
Started Jul 06 05:04:50 PM PDT 24
Finished Jul 06 05:04:53 PM PDT 24
Peak memory 208576 kb
Host smart-ae897f9d-ed94-438f-8900-2b7277ed2deb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367941284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1367941284
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2809981781
Short name T545
Test name
Test status
Simulation time 128523477 ps
CPU time 1.02 seconds
Started Jul 06 05:04:47 PM PDT 24
Finished Jul 06 05:04:48 PM PDT 24
Peak memory 208448 kb
Host smart-5eb3330a-74b0-474e-94ca-faf4a77c0b69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809981781 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2809981781
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4129250239
Short name T605
Test name
Test status
Simulation time 77785444 ps
CPU time 0.94 seconds
Started Jul 06 05:04:48 PM PDT 24
Finished Jul 06 05:04:49 PM PDT 24
Peak memory 200284 kb
Host smart-025f0c66-e90d-4455-902a-6634cd1246f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129250239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4129250239
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2578500081
Short name T119
Test name
Test status
Simulation time 83482840 ps
CPU time 0.97 seconds
Started Jul 06 05:04:45 PM PDT 24
Finished Jul 06 05:04:47 PM PDT 24
Peak memory 200244 kb
Host smart-13b53971-2921-4366-b064-8fe13530327d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578500081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2578500081
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3699046589
Short name T594
Test name
Test status
Simulation time 295663252 ps
CPU time 2.17 seconds
Started Jul 06 05:04:42 PM PDT 24
Finished Jul 06 05:04:45 PM PDT 24
Peak memory 200272 kb
Host smart-6b8e3466-adea-41ca-9cd9-d5bf4c552b32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699046589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3699046589
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2156657865
Short name T555
Test name
Test status
Simulation time 876993186 ps
CPU time 3.23 seconds
Started Jul 06 05:04:47 PM PDT 24
Finished Jul 06 05:04:50 PM PDT 24
Peak memory 200452 kb
Host smart-9cdf7f61-918d-4bc9-9119-ea8e2ca4a318
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156657865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2156657865
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1953242790
Short name T546
Test name
Test status
Simulation time 231191117 ps
CPU time 1.48 seconds
Started Jul 06 05:04:46 PM PDT 24
Finished Jul 06 05:04:48 PM PDT 24
Peak memory 208624 kb
Host smart-aa1d8028-7633-484d-a94a-40358439a90b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953242790 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1953242790
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2619820017
Short name T602
Test name
Test status
Simulation time 76526663 ps
CPU time 0.85 seconds
Started Jul 06 05:04:51 PM PDT 24
Finished Jul 06 05:04:53 PM PDT 24
Peak memory 200192 kb
Host smart-082623c8-dedd-4668-b18e-57c2d9926c10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619820017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2619820017
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1332538531
Short name T117
Test name
Test status
Simulation time 148439518 ps
CPU time 1.12 seconds
Started Jul 06 05:04:50 PM PDT 24
Finished Jul 06 05:04:51 PM PDT 24
Peak memory 200320 kb
Host smart-c3b5bce0-c44a-440c-a8cf-e9fabf08eeab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332538531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1332538531
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2650909169
Short name T556
Test name
Test status
Simulation time 108329073 ps
CPU time 1.62 seconds
Started Jul 06 05:04:50 PM PDT 24
Finished Jul 06 05:04:52 PM PDT 24
Peak memory 216720 kb
Host smart-c8389bd9-8037-4d5a-ae70-87830109f516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650909169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2650909169
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2797702252
Short name T59
Test name
Test status
Simulation time 910796722 ps
CPU time 3.33 seconds
Started Jul 06 05:04:48 PM PDT 24
Finished Jul 06 05:04:52 PM PDT 24
Peak memory 200440 kb
Host smart-9f096ee3-c77f-4093-8da5-b8980660e11d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797702252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2797702252
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3136453592
Short name T598
Test name
Test status
Simulation time 194155927 ps
CPU time 1.22 seconds
Started Jul 06 05:04:45 PM PDT 24
Finished Jul 06 05:04:47 PM PDT 24
Peak memory 200268 kb
Host smart-e28d6329-f9bc-4b1b-a216-e46a98f54aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136453592 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3136453592
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1463963300
Short name T616
Test name
Test status
Simulation time 94357347 ps
CPU time 0.86 seconds
Started Jul 06 05:04:48 PM PDT 24
Finished Jul 06 05:04:49 PM PDT 24
Peak memory 200300 kb
Host smart-10abacc1-9739-4eec-842c-786b13a7874e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463963300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1463963300
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1758422958
Short name T615
Test name
Test status
Simulation time 87105031 ps
CPU time 0.97 seconds
Started Jul 06 05:04:48 PM PDT 24
Finished Jul 06 05:04:49 PM PDT 24
Peak memory 200320 kb
Host smart-7efbada0-8789-4481-913a-a47faed3a89e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758422958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1758422958
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2200353676
Short name T613
Test name
Test status
Simulation time 90109028 ps
CPU time 1.22 seconds
Started Jul 06 05:04:53 PM PDT 24
Finished Jul 06 05:04:55 PM PDT 24
Peak memory 208456 kb
Host smart-8ac10b9d-4f11-4971-8b5a-7bd67a5083c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200353676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2200353676
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3598355935
Short name T135
Test name
Test status
Simulation time 764375263 ps
CPU time 2.87 seconds
Started Jul 06 05:04:45 PM PDT 24
Finished Jul 06 05:04:49 PM PDT 24
Peak memory 200448 kb
Host smart-10b4c33e-38cf-4835-a590-10b0644cfd0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598355935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3598355935
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.870564374
Short name T100
Test name
Test status
Simulation time 119446445 ps
CPU time 1.15 seconds
Started Jul 06 05:04:46 PM PDT 24
Finished Jul 06 05:04:47 PM PDT 24
Peak memory 208528 kb
Host smart-dd28f263-a893-46af-9f6d-83881c0958fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870564374 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.870564374
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1645818404
Short name T593
Test name
Test status
Simulation time 68704045 ps
CPU time 0.9 seconds
Started Jul 06 05:04:48 PM PDT 24
Finished Jul 06 05:04:49 PM PDT 24
Peak memory 200284 kb
Host smart-8440c055-2e99-4bb4-b5a5-feeec7067286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645818404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1645818404
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2208111232
Short name T120
Test name
Test status
Simulation time 138494531 ps
CPU time 1.33 seconds
Started Jul 06 05:04:53 PM PDT 24
Finished Jul 06 05:04:55 PM PDT 24
Peak memory 200472 kb
Host smart-ce3a488f-cba1-4ad6-a36e-2023d18e8368
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208111232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2208111232
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1001890825
Short name T595
Test name
Test status
Simulation time 297783575 ps
CPU time 2.02 seconds
Started Jul 06 05:04:47 PM PDT 24
Finished Jul 06 05:04:49 PM PDT 24
Peak memory 216612 kb
Host smart-3f60237b-d68c-4c3b-a9f4-2bd92fe6020a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001890825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1001890825
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.84309043
Short name T582
Test name
Test status
Simulation time 472960982 ps
CPU time 1.88 seconds
Started Jul 06 05:04:47 PM PDT 24
Finished Jul 06 05:04:49 PM PDT 24
Peak memory 200488 kb
Host smart-9cf6b1f5-3ad4-4dcc-a83f-018af623d277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84309043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.84309043
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3719870175
Short name T573
Test name
Test status
Simulation time 117738193 ps
CPU time 0.94 seconds
Started Jul 06 05:04:48 PM PDT 24
Finished Jul 06 05:04:49 PM PDT 24
Peak memory 200316 kb
Host smart-f3958112-383a-4ef9-b9d8-800298184b7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719870175 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3719870175
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1877905044
Short name T557
Test name
Test status
Simulation time 79943561 ps
CPU time 0.96 seconds
Started Jul 06 05:04:48 PM PDT 24
Finished Jul 06 05:04:50 PM PDT 24
Peak memory 200156 kb
Host smart-c0bd1f75-9760-4314-80a2-619101144986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877905044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1877905044
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2379443854
Short name T576
Test name
Test status
Simulation time 239031220 ps
CPU time 1.44 seconds
Started Jul 06 05:04:47 PM PDT 24
Finished Jul 06 05:04:49 PM PDT 24
Peak memory 200532 kb
Host smart-5e86f604-3407-45a9-b443-23c4215ccda1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379443854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2379443854
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2244326076
Short name T589
Test name
Test status
Simulation time 113745061 ps
CPU time 1.47 seconds
Started Jul 06 05:04:53 PM PDT 24
Finished Jul 06 05:04:55 PM PDT 24
Peak memory 200376 kb
Host smart-041079c7-5ac2-4d9f-bee8-ff880b80b205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244326076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2244326076
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.882476946
Short name T95
Test name
Test status
Simulation time 458787015 ps
CPU time 1.88 seconds
Started Jul 06 05:04:52 PM PDT 24
Finished Jul 06 05:04:55 PM PDT 24
Peak memory 200456 kb
Host smart-9384ab89-7577-4e53-8f5d-990fdc05746b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882476946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.882476946
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.421031656
Short name T558
Test name
Test status
Simulation time 120069797 ps
CPU time 1.21 seconds
Started Jul 06 05:04:46 PM PDT 24
Finished Jul 06 05:04:48 PM PDT 24
Peak memory 208516 kb
Host smart-59baa006-600b-479a-b35d-679a2024ecda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421031656 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.421031656
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.64504293
Short name T617
Test name
Test status
Simulation time 75111417 ps
CPU time 0.8 seconds
Started Jul 06 05:04:53 PM PDT 24
Finished Jul 06 05:04:54 PM PDT 24
Peak memory 200256 kb
Host smart-01f76fdf-1a4c-4aad-86c0-8cfb3cc92843
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64504293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.64504293
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.176270769
Short name T122
Test name
Test status
Simulation time 128121763 ps
CPU time 1.11 seconds
Started Jul 06 05:04:48 PM PDT 24
Finished Jul 06 05:04:50 PM PDT 24
Peak memory 200300 kb
Host smart-951155cc-e985-4a3d-b778-ea1f1e2a265d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176270769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.176270769
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1933733687
Short name T614
Test name
Test status
Simulation time 171289097 ps
CPU time 2.4 seconds
Started Jul 06 05:04:46 PM PDT 24
Finished Jul 06 05:04:49 PM PDT 24
Peak memory 208584 kb
Host smart-f357484f-c8f4-490f-81b1-f50203403aba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933733687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1933733687
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3983488262
Short name T543
Test name
Test status
Simulation time 194566047 ps
CPU time 1.39 seconds
Started Jul 06 05:04:52 PM PDT 24
Finished Jul 06 05:04:53 PM PDT 24
Peak memory 208496 kb
Host smart-7600ca40-dffb-4488-b3c7-71ae9b691c0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983488262 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3983488262
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.361739558
Short name T606
Test name
Test status
Simulation time 77737677 ps
CPU time 0.81 seconds
Started Jul 06 05:04:45 PM PDT 24
Finished Jul 06 05:04:47 PM PDT 24
Peak memory 200564 kb
Host smart-3cea4e60-14f1-4a00-afaf-a5cf86b3d002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361739558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.361739558
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3537525522
Short name T583
Test name
Test status
Simulation time 106117482 ps
CPU time 1.27 seconds
Started Jul 06 05:04:53 PM PDT 24
Finished Jul 06 05:04:55 PM PDT 24
Peak memory 200436 kb
Host smart-4b25ffe4-2bd2-47c2-ab0f-ac2227490d64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537525522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3537525522
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2444937171
Short name T554
Test name
Test status
Simulation time 403942589 ps
CPU time 2.85 seconds
Started Jul 06 05:04:53 PM PDT 24
Finished Jul 06 05:04:56 PM PDT 24
Peak memory 212128 kb
Host smart-c6bdeabc-5b70-4f4a-b9ef-6719d2bafa89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444937171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2444937171
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1380873752
Short name T592
Test name
Test status
Simulation time 874789801 ps
CPU time 3.2 seconds
Started Jul 06 05:04:51 PM PDT 24
Finished Jul 06 05:04:55 PM PDT 24
Peak memory 200468 kb
Host smart-0d71e854-5421-42f6-9add-5edeb2bdbe4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380873752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1380873752
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2167534354
Short name T62
Test name
Test status
Simulation time 172833414 ps
CPU time 1.53 seconds
Started Jul 06 05:04:51 PM PDT 24
Finished Jul 06 05:04:53 PM PDT 24
Peak memory 208700 kb
Host smart-f2f9f039-d677-42b4-8368-661773b6ab99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167534354 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2167534354
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.643917074
Short name T574
Test name
Test status
Simulation time 78290906 ps
CPU time 0.78 seconds
Started Jul 06 05:04:51 PM PDT 24
Finished Jul 06 05:04:52 PM PDT 24
Peak memory 200048 kb
Host smart-db98721e-cfd0-4d62-b576-e3f520ba719b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643917074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.643917074
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3535029537
Short name T580
Test name
Test status
Simulation time 194109014 ps
CPU time 1.5 seconds
Started Jul 06 05:04:53 PM PDT 24
Finished Jul 06 05:04:55 PM PDT 24
Peak memory 200324 kb
Host smart-e7506477-2936-405f-bafe-36d3cc603ecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535029537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3535029537
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.700411589
Short name T586
Test name
Test status
Simulation time 511125518 ps
CPU time 4 seconds
Started Jul 06 05:04:52 PM PDT 24
Finished Jul 06 05:04:56 PM PDT 24
Peak memory 212184 kb
Host smart-3001fef1-20ee-4fb9-97be-fd8b63808aac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700411589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.700411589
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2974267187
Short name T599
Test name
Test status
Simulation time 424453225 ps
CPU time 1.68 seconds
Started Jul 06 05:04:55 PM PDT 24
Finished Jul 06 05:04:57 PM PDT 24
Peak memory 200516 kb
Host smart-061157fc-bd1c-471b-89d9-a7d66e0ec30b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974267187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2974267187
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4172762603
Short name T548
Test name
Test status
Simulation time 191276982 ps
CPU time 1.22 seconds
Started Jul 06 05:04:51 PM PDT 24
Finished Jul 06 05:04:53 PM PDT 24
Peak memory 208376 kb
Host smart-6ea4f543-b3f0-425f-8091-fc54c3c5b6ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172762603 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4172762603
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3296708528
Short name T571
Test name
Test status
Simulation time 90575336 ps
CPU time 0.91 seconds
Started Jul 06 05:04:53 PM PDT 24
Finished Jul 06 05:04:54 PM PDT 24
Peak memory 200280 kb
Host smart-4943e060-3720-4443-8392-6b00c819d756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296708528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3296708528
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2385917240
Short name T114
Test name
Test status
Simulation time 89164979 ps
CPU time 1 seconds
Started Jul 06 05:04:52 PM PDT 24
Finished Jul 06 05:04:53 PM PDT 24
Peak memory 200184 kb
Host smart-c21ca090-f006-4a98-8395-01d31d8e5c15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385917240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2385917240
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3920938983
Short name T96
Test name
Test status
Simulation time 149247522 ps
CPU time 2.06 seconds
Started Jul 06 05:04:51 PM PDT 24
Finished Jul 06 05:04:53 PM PDT 24
Peak memory 212436 kb
Host smart-0ed3c7d2-cfab-46b0-b8ed-3f4f62e1064c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920938983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3920938983
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3294685086
Short name T124
Test name
Test status
Simulation time 971199748 ps
CPU time 3.22 seconds
Started Jul 06 05:04:55 PM PDT 24
Finished Jul 06 05:04:59 PM PDT 24
Peak memory 200512 kb
Host smart-46d02aa7-a926-4b5f-9bb9-0375c02e9ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294685086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3294685086
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3702916649
Short name T611
Test name
Test status
Simulation time 354112939 ps
CPU time 2.35 seconds
Started Jul 06 05:04:31 PM PDT 24
Finished Jul 06 05:04:34 PM PDT 24
Peak memory 200340 kb
Host smart-38798f18-41f2-4fb9-866f-35b51dfeecaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702916649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
702916649
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.598863109
Short name T572
Test name
Test status
Simulation time 1995457850 ps
CPU time 8.77 seconds
Started Jul 06 05:04:32 PM PDT 24
Finished Jul 06 05:04:41 PM PDT 24
Peak memory 200304 kb
Host smart-eb83d134-824d-4e4b-8d31-1657eae9a265
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598863109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.598863109
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1121833212
Short name T542
Test name
Test status
Simulation time 90856112 ps
CPU time 0.79 seconds
Started Jul 06 05:04:32 PM PDT 24
Finished Jul 06 05:04:33 PM PDT 24
Peak memory 200136 kb
Host smart-8b856b83-bac8-4f66-bec4-12eb824c9235
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121833212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
121833212
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3807315836
Short name T596
Test name
Test status
Simulation time 113494025 ps
CPU time 1.16 seconds
Started Jul 06 05:04:33 PM PDT 24
Finished Jul 06 05:04:35 PM PDT 24
Peak memory 208464 kb
Host smart-928c348c-4669-468b-b644-8e03b60d6646
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807315836 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3807315836
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3356746025
Short name T61
Test name
Test status
Simulation time 67189062 ps
CPU time 0.73 seconds
Started Jul 06 05:04:30 PM PDT 24
Finished Jul 06 05:04:31 PM PDT 24
Peak memory 200220 kb
Host smart-5f9fba29-331c-4aba-8e6f-9088521f1cab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356746025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3356746025
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1980303894
Short name T568
Test name
Test status
Simulation time 113402833 ps
CPU time 1.3 seconds
Started Jul 06 05:04:31 PM PDT 24
Finished Jul 06 05:04:33 PM PDT 24
Peak memory 200348 kb
Host smart-d897e778-818f-469a-a8a0-d63fc9046733
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980303894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1980303894
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1334511012
Short name T562
Test name
Test status
Simulation time 154208146 ps
CPU time 2.27 seconds
Started Jul 06 05:04:31 PM PDT 24
Finished Jul 06 05:04:33 PM PDT 24
Peak memory 208636 kb
Host smart-edda320c-fc77-426c-b3fe-611a87ae516d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334511012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1334511012
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1779882371
Short name T590
Test name
Test status
Simulation time 228828871 ps
CPU time 1.64 seconds
Started Jul 06 05:04:33 PM PDT 24
Finished Jul 06 05:04:35 PM PDT 24
Peak memory 200504 kb
Host smart-4ab4a587-74f2-48a2-a054-fd585cae7d37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779882371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
779882371
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1601577149
Short name T60
Test name
Test status
Simulation time 1558458663 ps
CPU time 8.41 seconds
Started Jul 06 05:04:33 PM PDT 24
Finished Jul 06 05:04:42 PM PDT 24
Peak memory 200412 kb
Host smart-3fe898b8-3788-4070-ac4c-b023ae89063c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601577149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
601577149
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2297205306
Short name T553
Test name
Test status
Simulation time 136779247 ps
CPU time 0.93 seconds
Started Jul 06 05:04:30 PM PDT 24
Finished Jul 06 05:04:32 PM PDT 24
Peak memory 200192 kb
Host smart-bfa9938e-2e30-46a4-bcfc-687a9cb4312b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297205306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
297205306
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1092026158
Short name T65
Test name
Test status
Simulation time 210447834 ps
CPU time 1.33 seconds
Started Jul 06 05:04:33 PM PDT 24
Finished Jul 06 05:04:35 PM PDT 24
Peak memory 208740 kb
Host smart-59b32589-b412-4bca-9949-b6b8d4c0b386
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092026158 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1092026158
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2289007828
Short name T591
Test name
Test status
Simulation time 89982658 ps
CPU time 0.88 seconds
Started Jul 06 05:04:32 PM PDT 24
Finished Jul 06 05:04:34 PM PDT 24
Peak memory 200180 kb
Host smart-4cf59aee-5cac-4b8d-b648-7fded0b3f8fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289007828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2289007828
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2421746801
Short name T569
Test name
Test status
Simulation time 144947522 ps
CPU time 1.16 seconds
Started Jul 06 05:04:33 PM PDT 24
Finished Jul 06 05:04:35 PM PDT 24
Peak memory 200312 kb
Host smart-5af3bf50-08e9-4bb6-89ac-a2087db4091f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421746801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2421746801
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3025350498
Short name T128
Test name
Test status
Simulation time 670496245 ps
CPU time 4.4 seconds
Started Jul 06 05:04:33 PM PDT 24
Finished Jul 06 05:04:38 PM PDT 24
Peak memory 208492 kb
Host smart-2c2c28c5-212c-4319-954a-3c99dd61d221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025350498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3025350498
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1731976910
Short name T133
Test name
Test status
Simulation time 780741629 ps
CPU time 3.04 seconds
Started Jul 06 05:04:35 PM PDT 24
Finished Jul 06 05:04:38 PM PDT 24
Peak memory 200356 kb
Host smart-3fdb9761-c434-45d7-bfca-0ec63a99913a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731976910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1731976910
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.4000209822
Short name T603
Test name
Test status
Simulation time 207440902 ps
CPU time 1.61 seconds
Started Jul 06 05:04:36 PM PDT 24
Finished Jul 06 05:04:38 PM PDT 24
Peak memory 200320 kb
Host smart-e0fa02df-938d-491b-9996-526aaade15b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000209822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.4
000209822
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1088316150
Short name T585
Test name
Test status
Simulation time 809793658 ps
CPU time 4.81 seconds
Started Jul 06 05:04:36 PM PDT 24
Finished Jul 06 05:04:41 PM PDT 24
Peak memory 200328 kb
Host smart-15453743-7a83-48c1-bc75-5d6bd158af40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088316150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
088316150
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1119396877
Short name T560
Test name
Test status
Simulation time 138736344 ps
CPU time 0.92 seconds
Started Jul 06 05:04:36 PM PDT 24
Finished Jul 06 05:04:37 PM PDT 24
Peak memory 200252 kb
Host smart-cb0c6961-bb16-4b68-8a8a-90751c633862
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119396877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
119396877
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1528161461
Short name T608
Test name
Test status
Simulation time 111234631 ps
CPU time 1.11 seconds
Started Jul 06 05:04:34 PM PDT 24
Finished Jul 06 05:04:36 PM PDT 24
Peak memory 208592 kb
Host smart-521ce2b5-bf8a-4954-bb23-55515db4fe9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528161461 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1528161461
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.4104244237
Short name T121
Test name
Test status
Simulation time 67623783 ps
CPU time 0.81 seconds
Started Jul 06 05:04:36 PM PDT 24
Finished Jul 06 05:04:38 PM PDT 24
Peak memory 200164 kb
Host smart-883589fb-44a9-4826-8e0f-c33aeb96ea24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104244237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.4104244237
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3616804050
Short name T579
Test name
Test status
Simulation time 103027082 ps
CPU time 1.35 seconds
Started Jul 06 05:04:35 PM PDT 24
Finished Jul 06 05:04:37 PM PDT 24
Peak memory 200356 kb
Host smart-5facc8f8-e746-4acd-84cf-60f04ec97d00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616804050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3616804050
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2131381958
Short name T552
Test name
Test status
Simulation time 157288863 ps
CPU time 2.25 seconds
Started Jul 06 05:04:36 PM PDT 24
Finished Jul 06 05:04:38 PM PDT 24
Peak memory 208568 kb
Host smart-c3036870-189d-4d69-a07c-2f48d5124eff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131381958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2131381958
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.648587342
Short name T559
Test name
Test status
Simulation time 498072430 ps
CPU time 1.88 seconds
Started Jul 06 05:04:39 PM PDT 24
Finished Jul 06 05:04:42 PM PDT 24
Peak memory 200500 kb
Host smart-46c57ec0-4620-48f9-b0c9-b70cf9f573f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648587342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
648587342
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3194113538
Short name T567
Test name
Test status
Simulation time 136065323 ps
CPU time 1.06 seconds
Started Jul 06 05:04:37 PM PDT 24
Finished Jul 06 05:04:39 PM PDT 24
Peak memory 209536 kb
Host smart-92033803-1120-4ead-8b2b-4f3a0637385c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194113538 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3194113538
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1304491140
Short name T551
Test name
Test status
Simulation time 73115895 ps
CPU time 0.78 seconds
Started Jul 06 05:04:41 PM PDT 24
Finished Jul 06 05:04:42 PM PDT 24
Peak memory 200064 kb
Host smart-607b0250-0172-49dd-9fd8-536b66d64e59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304491140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1304491140
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.971795464
Short name T118
Test name
Test status
Simulation time 86398618 ps
CPU time 0.98 seconds
Started Jul 06 05:04:39 PM PDT 24
Finished Jul 06 05:04:40 PM PDT 24
Peak memory 200348 kb
Host smart-6d59770a-ddd8-417a-9b5b-44757cbae4dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971795464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.971795464
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.267775728
Short name T550
Test name
Test status
Simulation time 129029064 ps
CPU time 1.93 seconds
Started Jul 06 05:04:36 PM PDT 24
Finished Jul 06 05:04:38 PM PDT 24
Peak memory 211276 kb
Host smart-c68ff314-a6d8-4bea-92ad-a8824f0d9c38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267775728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.267775728
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3394575997
Short name T98
Test name
Test status
Simulation time 410791334 ps
CPU time 1.78 seconds
Started Jul 06 05:04:35 PM PDT 24
Finished Jul 06 05:04:38 PM PDT 24
Peak memory 200352 kb
Host smart-06efcb95-c2c3-458b-b4bc-bb6fc93650fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394575997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3394575997
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1212716630
Short name T547
Test name
Test status
Simulation time 124483634 ps
CPU time 1.33 seconds
Started Jul 06 05:04:34 PM PDT 24
Finished Jul 06 05:04:36 PM PDT 24
Peak memory 208584 kb
Host smart-b5deb382-b94a-4586-8b5d-9f02cb468ea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212716630 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1212716630
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1886260395
Short name T609
Test name
Test status
Simulation time 88069992 ps
CPU time 0.88 seconds
Started Jul 06 05:04:36 PM PDT 24
Finished Jul 06 05:04:38 PM PDT 24
Peak memory 200288 kb
Host smart-0ade9f91-e10e-4bef-95ef-151fc84f38b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886260395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1886260395
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3557616812
Short name T565
Test name
Test status
Simulation time 108398747 ps
CPU time 1.24 seconds
Started Jul 06 05:04:35 PM PDT 24
Finished Jul 06 05:04:36 PM PDT 24
Peak memory 200452 kb
Host smart-224d5770-db7a-4c4e-9a9b-3ea21f7bfe8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557616812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3557616812
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.624548543
Short name T134
Test name
Test status
Simulation time 468115637 ps
CPU time 1.94 seconds
Started Jul 06 05:04:36 PM PDT 24
Finished Jul 06 05:04:38 PM PDT 24
Peak memory 200352 kb
Host smart-93ce5584-0cda-4679-ac84-50f7a02a2660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624548543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
624548543
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2225622938
Short name T544
Test name
Test status
Simulation time 127207398 ps
CPU time 1.04 seconds
Started Jul 06 05:04:43 PM PDT 24
Finished Jul 06 05:04:44 PM PDT 24
Peak memory 200380 kb
Host smart-e98a0461-bf88-45b1-b6e5-f9a3dd4cca6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225622938 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2225622938
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3332422682
Short name T581
Test name
Test status
Simulation time 67990783 ps
CPU time 0.77 seconds
Started Jul 06 05:04:36 PM PDT 24
Finished Jul 06 05:04:38 PM PDT 24
Peak memory 200112 kb
Host smart-072cf047-7df2-479b-b448-1c403141baf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332422682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3332422682
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1306138924
Short name T577
Test name
Test status
Simulation time 79581629 ps
CPU time 0.97 seconds
Started Jul 06 05:04:35 PM PDT 24
Finished Jul 06 05:04:36 PM PDT 24
Peak memory 200344 kb
Host smart-39ef7dd8-21a5-4a4c-b010-72ab414d0ad9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306138924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1306138924
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1322936530
Short name T64
Test name
Test status
Simulation time 484369290 ps
CPU time 3.14 seconds
Started Jul 06 05:04:39 PM PDT 24
Finished Jul 06 05:04:43 PM PDT 24
Peak memory 208636 kb
Host smart-bfb3dae5-bd46-4f63-82c8-dbbd018a929e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322936530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1322936530
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2457815769
Short name T125
Test name
Test status
Simulation time 949878497 ps
CPU time 3.53 seconds
Started Jul 06 05:04:35 PM PDT 24
Finished Jul 06 05:04:39 PM PDT 24
Peak memory 200548 kb
Host smart-acac3300-63e6-4a86-88be-16c8ca0275ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457815769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2457815769
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1084771943
Short name T588
Test name
Test status
Simulation time 122617142 ps
CPU time 1.32 seconds
Started Jul 06 05:04:41 PM PDT 24
Finished Jul 06 05:04:43 PM PDT 24
Peak memory 208628 kb
Host smart-db856611-bd1e-4c1c-b8fa-012b719d87c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084771943 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1084771943
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.498227728
Short name T600
Test name
Test status
Simulation time 86689222 ps
CPU time 0.89 seconds
Started Jul 06 05:04:42 PM PDT 24
Finished Jul 06 05:04:44 PM PDT 24
Peak memory 200148 kb
Host smart-01895ee9-e63a-4735-9b8c-8e80c48a40a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498227728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.498227728
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.971152987
Short name T607
Test name
Test status
Simulation time 124735302 ps
CPU time 1.25 seconds
Started Jul 06 05:04:41 PM PDT 24
Finished Jul 06 05:04:42 PM PDT 24
Peak memory 200408 kb
Host smart-4f7a48d5-feac-41e8-ab9b-05ca28822241
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971152987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.971152987
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3042617335
Short name T549
Test name
Test status
Simulation time 411953448 ps
CPU time 3.01 seconds
Started Jul 06 05:04:41 PM PDT 24
Finished Jul 06 05:04:44 PM PDT 24
Peak memory 208484 kb
Host smart-7b39e8e5-07c4-4c56-b7a8-6a5b57ca580f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042617335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3042617335
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2977855583
Short name T126
Test name
Test status
Simulation time 508741478 ps
CPU time 1.98 seconds
Started Jul 06 05:04:41 PM PDT 24
Finished Jul 06 05:04:43 PM PDT 24
Peak memory 200396 kb
Host smart-993d6cea-2c59-49d0-987f-07a4f1856a75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977855583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2977855583
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1410175531
Short name T619
Test name
Test status
Simulation time 195121393 ps
CPU time 2.18 seconds
Started Jul 06 05:04:49 PM PDT 24
Finished Jul 06 05:04:52 PM PDT 24
Peak memory 208800 kb
Host smart-551d4e1d-a2f4-4640-b5de-0d14d14e4529
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410175531 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1410175531
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.612331671
Short name T610
Test name
Test status
Simulation time 75147066 ps
CPU time 0.76 seconds
Started Jul 06 05:04:41 PM PDT 24
Finished Jul 06 05:04:43 PM PDT 24
Peak memory 200196 kb
Host smart-3156f0cf-e1c6-41d6-8fd6-85d4981709e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612331671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.612331671
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3745782917
Short name T116
Test name
Test status
Simulation time 114036202 ps
CPU time 1.4 seconds
Started Jul 06 05:04:46 PM PDT 24
Finished Jul 06 05:04:48 PM PDT 24
Peak memory 200476 kb
Host smart-40d4b218-7ad0-42ae-a030-ebc11cbe8547
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745782917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3745782917
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3832435132
Short name T584
Test name
Test status
Simulation time 121949720 ps
CPU time 1.75 seconds
Started Jul 06 05:04:41 PM PDT 24
Finished Jul 06 05:04:44 PM PDT 24
Peak memory 208560 kb
Host smart-3b380c77-c8ef-42bd-bfbd-d1d29b47f33d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832435132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3832435132
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2729159383
Short name T578
Test name
Test status
Simulation time 1085416000 ps
CPU time 3.4 seconds
Started Jul 06 05:04:49 PM PDT 24
Finished Jul 06 05:04:53 PM PDT 24
Peak memory 200484 kb
Host smart-d5d7bcf2-670d-4a82-b0ee-c928a33b7b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729159383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2729159383
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3657321049
Short name T226
Test name
Test status
Simulation time 84993388 ps
CPU time 0.85 seconds
Started Jul 06 05:04:52 PM PDT 24
Finished Jul 06 05:04:53 PM PDT 24
Peak memory 200208 kb
Host smart-0f12260b-9a20-4ef0-8ca7-d2b7867df422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657321049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3657321049
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.454710921
Short name T509
Test name
Test status
Simulation time 1225000814 ps
CPU time 5.86 seconds
Started Jul 06 05:04:52 PM PDT 24
Finished Jul 06 05:04:59 PM PDT 24
Peak memory 221728 kb
Host smart-218faf55-271d-4b26-a344-64f589f7cd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454710921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.454710921
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.798832615
Short name T493
Test name
Test status
Simulation time 244666833 ps
CPU time 1.07 seconds
Started Jul 06 05:04:55 PM PDT 24
Finished Jul 06 05:04:56 PM PDT 24
Peak memory 217512 kb
Host smart-12e33c17-c28e-446a-aa37-edefc0934c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798832615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.798832615
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2789353862
Short name T445
Test name
Test status
Simulation time 93575731 ps
CPU time 0.76 seconds
Started Jul 06 05:04:53 PM PDT 24
Finished Jul 06 05:04:54 PM PDT 24
Peak memory 199972 kb
Host smart-9cc760cb-9400-4de8-a3ce-d3e2dfccab43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789353862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2789353862
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3080780572
Short name T408
Test name
Test status
Simulation time 1722581078 ps
CPU time 6.65 seconds
Started Jul 06 05:04:58 PM PDT 24
Finished Jul 06 05:05:05 PM PDT 24
Peak memory 200432 kb
Host smart-43c6b84d-5c76-4439-b548-11fd4531442a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080780572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3080780572
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2543818442
Short name T22
Test name
Test status
Simulation time 226273180 ps
CPU time 1.46 seconds
Started Jul 06 05:04:55 PM PDT 24
Finished Jul 06 05:04:56 PM PDT 24
Peak memory 200264 kb
Host smart-87d6e371-d1e6-4845-9f55-0306c2648074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543818442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2543818442
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3433073377
Short name T108
Test name
Test status
Simulation time 8037382903 ps
CPU time 30.47 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:05:28 PM PDT 24
Peak memory 200480 kb
Host smart-27a684c5-c57e-4f3e-b30b-6a742c708af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433073377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3433073377
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3966078019
Short name T161
Test name
Test status
Simulation time 436650369 ps
CPU time 2.32 seconds
Started Jul 06 05:04:54 PM PDT 24
Finished Jul 06 05:04:57 PM PDT 24
Peak memory 200068 kb
Host smart-03c82f18-acdc-4434-926e-897b50841426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966078019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3966078019
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1522287284
Short name T309
Test name
Test status
Simulation time 2362795773 ps
CPU time 8.09 seconds
Started Jul 06 05:05:00 PM PDT 24
Finished Jul 06 05:05:08 PM PDT 24
Peak memory 217860 kb
Host smart-16d57daf-7b87-4cab-94d3-5879a1c78076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522287284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1522287284
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2851689164
Short name T358
Test name
Test status
Simulation time 244655011 ps
CPU time 1.12 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:04:58 PM PDT 24
Peak memory 217408 kb
Host smart-514d1ba6-7242-48b3-aa67-7a6759e3d473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851689164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2851689164
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.4175752646
Short name T413
Test name
Test status
Simulation time 131698938 ps
CPU time 0.85 seconds
Started Jul 06 05:04:53 PM PDT 24
Finished Jul 06 05:04:54 PM PDT 24
Peak memory 199920 kb
Host smart-93586a6d-0881-4ccd-b70d-2c70d9ce8cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175752646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.4175752646
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.327682625
Short name T197
Test name
Test status
Simulation time 1458051148 ps
CPU time 5.79 seconds
Started Jul 06 05:04:52 PM PDT 24
Finished Jul 06 05:04:58 PM PDT 24
Peak memory 200428 kb
Host smart-3dfa992d-e2fa-4c6e-a4f5-172703b9336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327682625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.327682625
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3540177697
Short name T68
Test name
Test status
Simulation time 8547939575 ps
CPU time 13.27 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:05:11 PM PDT 24
Peak memory 217632 kb
Host smart-3ddd6dc1-67e2-4942-bd28-796e2c48dbbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540177697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3540177697
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.4053390735
Short name T418
Test name
Test status
Simulation time 94735168 ps
CPU time 1.05 seconds
Started Jul 06 05:04:58 PM PDT 24
Finished Jul 06 05:05:00 PM PDT 24
Peak memory 200028 kb
Host smart-3e1d1403-cb75-43ce-8bb3-a24dbe67c0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053390735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.4053390735
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3494869760
Short name T336
Test name
Test status
Simulation time 246024677 ps
CPU time 1.45 seconds
Started Jul 06 05:04:52 PM PDT 24
Finished Jul 06 05:04:54 PM PDT 24
Peak memory 200348 kb
Host smart-0ce6309c-1b8e-4829-a717-43943e699e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494869760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3494869760
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1012865166
Short name T504
Test name
Test status
Simulation time 9899736343 ps
CPU time 37.94 seconds
Started Jul 06 05:05:00 PM PDT 24
Finished Jul 06 05:05:38 PM PDT 24
Peak memory 200484 kb
Host smart-bdf4c02b-59c0-4e42-9fd8-5430689510cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012865166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1012865166
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1085369926
Short name T302
Test name
Test status
Simulation time 486859068 ps
CPU time 2.42 seconds
Started Jul 06 05:04:52 PM PDT 24
Finished Jul 06 05:04:55 PM PDT 24
Peak memory 200180 kb
Host smart-643db9e5-6eb7-4216-8761-d6b3040ea9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085369926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1085369926
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3280300314
Short name T217
Test name
Test status
Simulation time 250329790 ps
CPU time 1.48 seconds
Started Jul 06 05:04:55 PM PDT 24
Finished Jul 06 05:04:57 PM PDT 24
Peak memory 200256 kb
Host smart-f3b6cd41-f806-42bd-885e-beaacda6a65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280300314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3280300314
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3025896851
Short name T143
Test name
Test status
Simulation time 77110259 ps
CPU time 0.79 seconds
Started Jul 06 05:05:18 PM PDT 24
Finished Jul 06 05:05:19 PM PDT 24
Peak memory 199576 kb
Host smart-d2b184ee-fc3b-4d76-838c-0aa2b2c53467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025896851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3025896851
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.568009231
Short name T376
Test name
Test status
Simulation time 2375752020 ps
CPU time 8.03 seconds
Started Jul 06 05:05:18 PM PDT 24
Finished Jul 06 05:05:26 PM PDT 24
Peak memory 217728 kb
Host smart-98d0c8d1-5102-4c91-aee0-e116e79dc166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568009231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.568009231
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.577882559
Short name T218
Test name
Test status
Simulation time 243486466 ps
CPU time 1.07 seconds
Started Jul 06 05:05:15 PM PDT 24
Finished Jul 06 05:05:17 PM PDT 24
Peak memory 217452 kb
Host smart-e78f4f93-2aaa-4b24-935d-b4718faf7b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577882559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.577882559
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1914028060
Short name T362
Test name
Test status
Simulation time 197405315 ps
CPU time 0.92 seconds
Started Jul 06 05:05:15 PM PDT 24
Finished Jul 06 05:05:17 PM PDT 24
Peak memory 199976 kb
Host smart-0b4873b1-75cd-4a90-af17-1c8dc32d817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914028060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1914028060
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3718224663
Short name T351
Test name
Test status
Simulation time 1656577154 ps
CPU time 6.43 seconds
Started Jul 06 05:05:13 PM PDT 24
Finished Jul 06 05:05:20 PM PDT 24
Peak memory 200408 kb
Host smart-f65e8cf1-8d68-4599-9315-f1467768411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718224663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3718224663
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3514794038
Short name T398
Test name
Test status
Simulation time 96622740 ps
CPU time 1 seconds
Started Jul 06 05:05:16 PM PDT 24
Finished Jul 06 05:05:18 PM PDT 24
Peak memory 200064 kb
Host smart-997c6f88-b4b6-4a05-bc2c-889cd2b41453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514794038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3514794038
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2915766057
Short name T296
Test name
Test status
Simulation time 199369105 ps
CPU time 1.3 seconds
Started Jul 06 05:05:18 PM PDT 24
Finished Jul 06 05:05:19 PM PDT 24
Peak memory 200364 kb
Host smart-df689d11-e738-47ef-8221-80acdaf348b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915766057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2915766057
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3571806740
Short name T472
Test name
Test status
Simulation time 4048556301 ps
CPU time 17.69 seconds
Started Jul 06 05:05:16 PM PDT 24
Finished Jul 06 05:05:34 PM PDT 24
Peak memory 208596 kb
Host smart-1b51c6b7-0669-4449-844c-64a9bef453f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571806740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3571806740
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1938691050
Short name T213
Test name
Test status
Simulation time 343701902 ps
CPU time 2.07 seconds
Started Jul 06 05:05:13 PM PDT 24
Finished Jul 06 05:05:15 PM PDT 24
Peak memory 200176 kb
Host smart-0513941f-f2cb-4e67-a3d4-07eea5637373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938691050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1938691050
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3299152073
Short name T453
Test name
Test status
Simulation time 122658865 ps
CPU time 1.13 seconds
Started Jul 06 05:05:12 PM PDT 24
Finished Jul 06 05:05:14 PM PDT 24
Peak memory 200148 kb
Host smart-823d8f60-246c-4760-ab65-61fb4f8da1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299152073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3299152073
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.80503397
Short name T153
Test name
Test status
Simulation time 80158849 ps
CPU time 0.83 seconds
Started Jul 06 05:05:15 PM PDT 24
Finished Jul 06 05:05:17 PM PDT 24
Peak memory 199884 kb
Host smart-903826ae-ffbe-45ca-8a31-f52ef804a43b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80503397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.80503397
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1409232465
Short name T446
Test name
Test status
Simulation time 1876124820 ps
CPU time 6.91 seconds
Started Jul 06 05:05:15 PM PDT 24
Finished Jul 06 05:05:22 PM PDT 24
Peak memory 221472 kb
Host smart-14d31f94-aa43-48bc-a747-5d8f7ff62f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409232465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1409232465
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1689019557
Short name T297
Test name
Test status
Simulation time 244443169 ps
CPU time 1.05 seconds
Started Jul 06 05:05:13 PM PDT 24
Finished Jul 06 05:05:14 PM PDT 24
Peak memory 217500 kb
Host smart-0348f9b8-406e-461d-9f8e-1f54bdbf1d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689019557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1689019557
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.37969627
Short name T393
Test name
Test status
Simulation time 82022747 ps
CPU time 0.78 seconds
Started Jul 06 05:05:14 PM PDT 24
Finished Jul 06 05:05:15 PM PDT 24
Peak memory 199944 kb
Host smart-93fd5b88-c131-4644-bfe3-4eb6b8e26b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37969627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.37969627
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3220292604
Short name T273
Test name
Test status
Simulation time 897168417 ps
CPU time 4.83 seconds
Started Jul 06 05:05:18 PM PDT 24
Finished Jul 06 05:05:23 PM PDT 24
Peak memory 200368 kb
Host smart-39538c0f-e5da-48fc-94b3-6b5bf146aca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220292604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3220292604
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1618622732
Short name T420
Test name
Test status
Simulation time 171989601 ps
CPU time 1.22 seconds
Started Jul 06 05:05:14 PM PDT 24
Finished Jul 06 05:05:16 PM PDT 24
Peak memory 200040 kb
Host smart-19455bc1-b81c-41b7-a446-fec033c15cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618622732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1618622732
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1569447208
Short name T284
Test name
Test status
Simulation time 241650869 ps
CPU time 1.48 seconds
Started Jul 06 05:05:14 PM PDT 24
Finished Jul 06 05:05:16 PM PDT 24
Peak memory 200276 kb
Host smart-62afb019-0580-4e80-a6c4-2547e336051f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569447208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1569447208
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.989894787
Short name T77
Test name
Test status
Simulation time 6913667983 ps
CPU time 26.39 seconds
Started Jul 06 05:05:14 PM PDT 24
Finished Jul 06 05:05:41 PM PDT 24
Peak memory 208724 kb
Host smart-294a7df2-a2a9-4cc2-bb70-cae482ebacf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989894787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.989894787
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.4117211907
Short name T281
Test name
Test status
Simulation time 353989205 ps
CPU time 2.3 seconds
Started Jul 06 05:05:15 PM PDT 24
Finished Jul 06 05:05:18 PM PDT 24
Peak memory 200180 kb
Host smart-3e4a20f2-eda6-4370-b7b7-7196b9e2548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117211907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.4117211907
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2469948419
Short name T7
Test name
Test status
Simulation time 110738143 ps
CPU time 1.03 seconds
Started Jul 06 05:05:14 PM PDT 24
Finished Jul 06 05:05:15 PM PDT 24
Peak memory 200132 kb
Host smart-ec9d2534-c7aa-44f6-b260-2ac541ce05a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469948419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2469948419
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.4086805182
Short name T142
Test name
Test status
Simulation time 65287931 ps
CPU time 0.78 seconds
Started Jul 06 05:05:18 PM PDT 24
Finished Jul 06 05:05:19 PM PDT 24
Peak memory 199868 kb
Host smart-4aa33807-247a-4198-a5ff-511b86fd68d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086805182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4086805182
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3095803029
Short name T42
Test name
Test status
Simulation time 1899380773 ps
CPU time 7.15 seconds
Started Jul 06 05:05:21 PM PDT 24
Finished Jul 06 05:05:28 PM PDT 24
Peak memory 221708 kb
Host smart-1b34068c-ad23-4d08-b4b9-1efb9b5230cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095803029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3095803029
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1179493131
Short name T158
Test name
Test status
Simulation time 244282866 ps
CPU time 1.09 seconds
Started Jul 06 05:05:20 PM PDT 24
Finished Jul 06 05:05:21 PM PDT 24
Peak memory 217432 kb
Host smart-2693c0c3-7324-4c10-9e98-d5299b9520f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179493131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1179493131
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1662394730
Short name T160
Test name
Test status
Simulation time 99071538 ps
CPU time 0.8 seconds
Started Jul 06 05:05:13 PM PDT 24
Finished Jul 06 05:05:14 PM PDT 24
Peak memory 199932 kb
Host smart-3171117a-62a9-4bef-bfe3-4c38970d4392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662394730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1662394730
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3089868841
Short name T540
Test name
Test status
Simulation time 850254827 ps
CPU time 4.21 seconds
Started Jul 06 05:05:13 PM PDT 24
Finished Jul 06 05:05:18 PM PDT 24
Peak memory 200348 kb
Host smart-943ad226-3db3-4e8c-8eaf-2358e350c68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089868841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3089868841
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2079391064
Short name T437
Test name
Test status
Simulation time 152701194 ps
CPU time 1.14 seconds
Started Jul 06 05:05:19 PM PDT 24
Finished Jul 06 05:05:20 PM PDT 24
Peak memory 200152 kb
Host smart-c4b657ec-341f-4c58-ba15-2161d4c75b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079391064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2079391064
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.493709359
Short name T289
Test name
Test status
Simulation time 222400260 ps
CPU time 1.45 seconds
Started Jul 06 05:05:17 PM PDT 24
Finished Jul 06 05:05:19 PM PDT 24
Peak memory 200344 kb
Host smart-cbaffa91-9a45-4212-8828-c47c8a3b87a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493709359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.493709359
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.65830092
Short name T512
Test name
Test status
Simulation time 1742371582 ps
CPU time 6.3 seconds
Started Jul 06 05:05:22 PM PDT 24
Finished Jul 06 05:05:28 PM PDT 24
Peak memory 200364 kb
Host smart-8588cc95-7af2-4242-9c5f-a4b39c269bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65830092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.65830092
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2579746741
Short name T220
Test name
Test status
Simulation time 479403048 ps
CPU time 2.58 seconds
Started Jul 06 05:05:18 PM PDT 24
Finished Jul 06 05:05:21 PM PDT 24
Peak memory 200176 kb
Host smart-b2e98fc9-ebc7-4b4a-81d7-50502ccb93a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579746741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2579746741
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3110059354
Short name T484
Test name
Test status
Simulation time 205114925 ps
CPU time 1.32 seconds
Started Jul 06 05:05:21 PM PDT 24
Finished Jul 06 05:05:23 PM PDT 24
Peak memory 200148 kb
Host smart-f112fd7f-5155-4c00-a159-b997333b6bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110059354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3110059354
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1240577072
Short name T146
Test name
Test status
Simulation time 53448012 ps
CPU time 0.75 seconds
Started Jul 06 05:05:19 PM PDT 24
Finished Jul 06 05:05:20 PM PDT 24
Peak memory 199952 kb
Host smart-fece7ed5-2b1b-4884-9883-089d6717687a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240577072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1240577072
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3628449463
Short name T44
Test name
Test status
Simulation time 2173722678 ps
CPU time 7.62 seconds
Started Jul 06 05:05:20 PM PDT 24
Finished Jul 06 05:05:28 PM PDT 24
Peak memory 217876 kb
Host smart-4ff5a848-3b60-4c59-8cc1-5d29a4555bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628449463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3628449463
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2003994676
Short name T198
Test name
Test status
Simulation time 244534737 ps
CPU time 1.04 seconds
Started Jul 06 05:05:19 PM PDT 24
Finished Jul 06 05:05:21 PM PDT 24
Peak memory 217460 kb
Host smart-70d53a30-da3c-42d3-930f-6b3a52ed0df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003994676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2003994676
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.4210586743
Short name T247
Test name
Test status
Simulation time 150615320 ps
CPU time 0.81 seconds
Started Jul 06 05:05:20 PM PDT 24
Finished Jul 06 05:05:22 PM PDT 24
Peak memory 199972 kb
Host smart-94defa26-fa0a-4311-a7a0-2817aa8297a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210586743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.4210586743
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.906790915
Short name T407
Test name
Test status
Simulation time 780917070 ps
CPU time 3.94 seconds
Started Jul 06 05:05:21 PM PDT 24
Finished Jul 06 05:05:25 PM PDT 24
Peak memory 200432 kb
Host smart-66b85153-28e7-4681-b0ef-347ece064cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906790915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.906790915
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2166679403
Short name T206
Test name
Test status
Simulation time 109541326 ps
CPU time 1.01 seconds
Started Jul 06 05:05:22 PM PDT 24
Finished Jul 06 05:05:23 PM PDT 24
Peak memory 199988 kb
Host smart-ba2f94eb-7ee8-4cf8-bb98-d3bdf958b207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166679403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2166679403
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1983871372
Short name T180
Test name
Test status
Simulation time 200231784 ps
CPU time 1.35 seconds
Started Jul 06 05:05:20 PM PDT 24
Finished Jul 06 05:05:21 PM PDT 24
Peak memory 200352 kb
Host smart-6752472a-1027-4875-b429-decc958e1008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983871372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1983871372
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3992133286
Short name T389
Test name
Test status
Simulation time 117577559 ps
CPU time 1.6 seconds
Started Jul 06 05:05:18 PM PDT 24
Finished Jul 06 05:05:20 PM PDT 24
Peak memory 208296 kb
Host smart-8cc7b407-83c2-4efc-be9c-4a6952ba26b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992133286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3992133286
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2019898583
Short name T346
Test name
Test status
Simulation time 220992560 ps
CPU time 1.3 seconds
Started Jul 06 05:05:20 PM PDT 24
Finished Jul 06 05:05:22 PM PDT 24
Peak memory 200068 kb
Host smart-12c8d57f-8a5f-43df-86f0-c8c5120b70ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019898583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2019898583
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1406443723
Short name T317
Test name
Test status
Simulation time 91915701 ps
CPU time 0.83 seconds
Started Jul 06 05:05:27 PM PDT 24
Finished Jul 06 05:05:28 PM PDT 24
Peak memory 199904 kb
Host smart-e2400f78-25e3-4918-9cea-1b6eea62d023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406443723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1406443723
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2364167108
Short name T386
Test name
Test status
Simulation time 2358591189 ps
CPU time 8.19 seconds
Started Jul 06 05:05:29 PM PDT 24
Finished Jul 06 05:05:37 PM PDT 24
Peak memory 217908 kb
Host smart-506ac4c1-1661-4e76-baed-5bf29d44291b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364167108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2364167108
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3242295207
Short name T235
Test name
Test status
Simulation time 243997931 ps
CPU time 1.11 seconds
Started Jul 06 05:05:31 PM PDT 24
Finished Jul 06 05:05:32 PM PDT 24
Peak memory 217428 kb
Host smart-50353cc4-3e08-4d78-ac88-36f14cce7d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242295207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3242295207
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3202624233
Short name T347
Test name
Test status
Simulation time 1604761012 ps
CPU time 6.89 seconds
Started Jul 06 05:05:20 PM PDT 24
Finished Jul 06 05:05:28 PM PDT 24
Peak memory 200416 kb
Host smart-35d45c01-b875-402b-a4b7-0a4ee5adf7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202624233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3202624233
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.792065440
Short name T395
Test name
Test status
Simulation time 182993405 ps
CPU time 1.21 seconds
Started Jul 06 05:05:24 PM PDT 24
Finished Jul 06 05:05:26 PM PDT 24
Peak memory 200144 kb
Host smart-b182bc85-dd08-4767-8153-1e029c7527fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792065440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.792065440
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3879439112
Short name T458
Test name
Test status
Simulation time 118564809 ps
CPU time 1.13 seconds
Started Jul 06 05:05:19 PM PDT 24
Finished Jul 06 05:05:21 PM PDT 24
Peak memory 200280 kb
Host smart-b133f4eb-eac5-44ab-8c7e-c6a0de366789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879439112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3879439112
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.353380686
Short name T392
Test name
Test status
Simulation time 5113907861 ps
CPU time 18.13 seconds
Started Jul 06 05:05:26 PM PDT 24
Finished Jul 06 05:05:44 PM PDT 24
Peak memory 208524 kb
Host smart-83177443-50bd-4358-b600-6817799c67ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353380686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.353380686
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1701627946
Short name T454
Test name
Test status
Simulation time 379530264 ps
CPU time 2.33 seconds
Started Jul 06 05:05:20 PM PDT 24
Finished Jul 06 05:05:22 PM PDT 24
Peak memory 200100 kb
Host smart-3bafa72f-7e90-4de2-b07e-b4d33ee749b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701627946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1701627946
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.403172028
Short name T222
Test name
Test status
Simulation time 251117772 ps
CPU time 1.46 seconds
Started Jul 06 05:05:21 PM PDT 24
Finished Jul 06 05:05:23 PM PDT 24
Peak memory 200040 kb
Host smart-5a7e4a92-945a-45eb-b0fe-54c919170773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403172028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.403172028
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.4150872807
Short name T495
Test name
Test status
Simulation time 58529313 ps
CPU time 0.78 seconds
Started Jul 06 05:05:25 PM PDT 24
Finished Jul 06 05:05:26 PM PDT 24
Peak memory 199968 kb
Host smart-c81ad14c-08ac-44f8-b9a1-3dbf7fde5d7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150872807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.4150872807
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2150423094
Short name T304
Test name
Test status
Simulation time 2191665038 ps
CPU time 8.31 seconds
Started Jul 06 05:05:25 PM PDT 24
Finished Jul 06 05:05:33 PM PDT 24
Peak memory 217112 kb
Host smart-ba431b3d-e501-496e-a3c7-17f5f9b11b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150423094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2150423094
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3083836383
Short name T285
Test name
Test status
Simulation time 244251046 ps
CPU time 1.09 seconds
Started Jul 06 05:05:27 PM PDT 24
Finished Jul 06 05:05:29 PM PDT 24
Peak memory 217376 kb
Host smart-f5a647a3-5bdb-4722-bc87-5bcdfdafaa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083836383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3083836383
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3872184040
Short name T426
Test name
Test status
Simulation time 94290977 ps
CPU time 0.76 seconds
Started Jul 06 05:05:26 PM PDT 24
Finished Jul 06 05:05:27 PM PDT 24
Peak memory 199924 kb
Host smart-d01b548e-a482-4f89-ba95-d517fd655eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872184040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3872184040
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3590074098
Short name T341
Test name
Test status
Simulation time 1620046479 ps
CPU time 6.78 seconds
Started Jul 06 05:05:27 PM PDT 24
Finished Jul 06 05:05:34 PM PDT 24
Peak memory 200344 kb
Host smart-8bd22e83-4f13-4e2c-9468-66bf8e2e6f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590074098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3590074098
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.819290355
Short name T75
Test name
Test status
Simulation time 97986046 ps
CPU time 0.99 seconds
Started Jul 06 05:05:23 PM PDT 24
Finished Jul 06 05:05:24 PM PDT 24
Peak memory 200116 kb
Host smart-244f6670-db07-456b-a5b2-f6829dae258b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819290355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.819290355
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1206753974
Short name T50
Test name
Test status
Simulation time 110865479 ps
CPU time 1.15 seconds
Started Jul 06 05:05:25 PM PDT 24
Finished Jul 06 05:05:26 PM PDT 24
Peak memory 200276 kb
Host smart-5dd4ff92-2323-4e5e-82a0-af9069206e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206753974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1206753974
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.4293087078
Short name T268
Test name
Test status
Simulation time 7799179339 ps
CPU time 26.41 seconds
Started Jul 06 05:05:27 PM PDT 24
Finished Jul 06 05:05:54 PM PDT 24
Peak memory 210456 kb
Host smart-765a0b63-b96d-4e50-9dd7-5a42e8c906a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293087078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.4293087078
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1020268861
Short name T227
Test name
Test status
Simulation time 113745848 ps
CPU time 1.47 seconds
Started Jul 06 05:05:28 PM PDT 24
Finished Jul 06 05:05:30 PM PDT 24
Peak memory 200136 kb
Host smart-3ea5fcee-1290-4eeb-8a30-21e96e99a855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020268861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1020268861
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2087925317
Short name T331
Test name
Test status
Simulation time 108533733 ps
CPU time 1.02 seconds
Started Jul 06 05:05:25 PM PDT 24
Finished Jul 06 05:05:27 PM PDT 24
Peak memory 200040 kb
Host smart-4d3b0935-d6ca-4778-a569-3797d363c7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087925317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2087925317
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.557203649
Short name T375
Test name
Test status
Simulation time 71528805 ps
CPU time 0.76 seconds
Started Jul 06 05:05:39 PM PDT 24
Finished Jul 06 05:05:40 PM PDT 24
Peak memory 199972 kb
Host smart-5e948c43-1f83-4432-9406-8eb7c630218e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557203649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.557203649
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3990801074
Short name T367
Test name
Test status
Simulation time 1896622833 ps
CPU time 7.25 seconds
Started Jul 06 05:05:24 PM PDT 24
Finished Jul 06 05:05:32 PM PDT 24
Peak memory 217824 kb
Host smart-f1e7b87c-f03d-4933-9e52-9c946c85b95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990801074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3990801074
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2059528120
Short name T527
Test name
Test status
Simulation time 244495385 ps
CPU time 1.05 seconds
Started Jul 06 05:05:40 PM PDT 24
Finished Jul 06 05:05:42 PM PDT 24
Peak memory 217540 kb
Host smart-c9a7b882-2c1b-457f-8750-87851d91db99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059528120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2059528120
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2271350633
Short name T517
Test name
Test status
Simulation time 181022824 ps
CPU time 0.86 seconds
Started Jul 06 05:05:24 PM PDT 24
Finished Jul 06 05:05:25 PM PDT 24
Peak memory 199972 kb
Host smart-bfc50d94-09b1-4994-b31e-2cea5f7f3bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271350633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2271350633
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2424289292
Short name T520
Test name
Test status
Simulation time 1574830297 ps
CPU time 7.13 seconds
Started Jul 06 05:05:27 PM PDT 24
Finished Jul 06 05:05:35 PM PDT 24
Peak memory 200392 kb
Host smart-d49931de-48b7-4882-b07e-f99c5fc1e0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424289292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2424289292
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2424449300
Short name T356
Test name
Test status
Simulation time 146898920 ps
CPU time 1.11 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:34 PM PDT 24
Peak memory 200124 kb
Host smart-8ff0e86b-f84c-49ad-82c8-0c40660604e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424449300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2424449300
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3862406234
Short name T186
Test name
Test status
Simulation time 249036138 ps
CPU time 1.56 seconds
Started Jul 06 05:05:24 PM PDT 24
Finished Jul 06 05:05:26 PM PDT 24
Peak memory 200276 kb
Host smart-a654c519-579e-4030-9b33-0a091a1b7773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862406234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3862406234
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.89755882
Short name T500
Test name
Test status
Simulation time 8228643338 ps
CPU time 28.86 seconds
Started Jul 06 05:05:27 PM PDT 24
Finished Jul 06 05:05:57 PM PDT 24
Peak memory 208608 kb
Host smart-0f03e795-c35e-4299-8063-90b242139bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89755882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.89755882
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2802884192
Short name T387
Test name
Test status
Simulation time 339443808 ps
CPU time 2.05 seconds
Started Jul 06 05:05:25 PM PDT 24
Finished Jul 06 05:05:28 PM PDT 24
Peak memory 200172 kb
Host smart-1ae4c465-4937-4d01-8720-8dfcd92c04b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802884192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2802884192
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1043652842
Short name T399
Test name
Test status
Simulation time 96022976 ps
CPU time 1 seconds
Started Jul 06 05:05:26 PM PDT 24
Finished Jul 06 05:05:27 PM PDT 24
Peak memory 200064 kb
Host smart-f1353539-be67-41aa-8039-c71261ed7458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043652842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1043652842
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2072490547
Short name T71
Test name
Test status
Simulation time 68995144 ps
CPU time 0.74 seconds
Started Jul 06 05:05:45 PM PDT 24
Finished Jul 06 05:05:46 PM PDT 24
Peak memory 199976 kb
Host smart-3436569b-1cec-4149-96a3-e80bf113dd3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072490547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2072490547
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2208314352
Short name T436
Test name
Test status
Simulation time 2168842145 ps
CPU time 7.64 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:40 PM PDT 24
Peak memory 217832 kb
Host smart-16341590-7224-426c-9c73-4ca59eb5a50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208314352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2208314352
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.689673608
Short name T352
Test name
Test status
Simulation time 245411140 ps
CPU time 1.02 seconds
Started Jul 06 05:05:30 PM PDT 24
Finished Jul 06 05:05:32 PM PDT 24
Peak memory 217456 kb
Host smart-83bb2ffb-5e63-43db-9c1e-99f13cb7079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689673608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.689673608
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.556108389
Short name T510
Test name
Test status
Simulation time 113524274 ps
CPU time 0.77 seconds
Started Jul 06 05:05:24 PM PDT 24
Finished Jul 06 05:05:25 PM PDT 24
Peak memory 199876 kb
Host smart-f2747ea0-87b7-4da7-9569-19b7af5b4817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556108389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.556108389
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1302189843
Short name T107
Test name
Test status
Simulation time 2010704271 ps
CPU time 6.94 seconds
Started Jul 06 05:05:45 PM PDT 24
Finished Jul 06 05:05:52 PM PDT 24
Peak memory 200484 kb
Host smart-1d4b4c51-4fef-4305-b100-e0ac869de43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302189843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1302189843
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1473607050
Short name T10
Test name
Test status
Simulation time 147957551 ps
CPU time 1.2 seconds
Started Jul 06 05:05:30 PM PDT 24
Finished Jul 06 05:05:31 PM PDT 24
Peak memory 200124 kb
Host smart-e100b0ce-968e-4f6e-8401-49eb1426540b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473607050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1473607050
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.401622812
Short name T316
Test name
Test status
Simulation time 113115962 ps
CPU time 1.24 seconds
Started Jul 06 05:05:25 PM PDT 24
Finished Jul 06 05:05:27 PM PDT 24
Peak memory 200344 kb
Host smart-51a77937-aa9c-4233-83e2-aab9552c5039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401622812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.401622812
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2062240399
Short name T344
Test name
Test status
Simulation time 10481077756 ps
CPU time 31.78 seconds
Started Jul 06 05:05:30 PM PDT 24
Finished Jul 06 05:06:02 PM PDT 24
Peak memory 210768 kb
Host smart-09500d9d-0c6e-4b7e-94ca-41552ce09d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062240399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2062240399
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1841678290
Short name T58
Test name
Test status
Simulation time 500112536 ps
CPU time 2.59 seconds
Started Jul 06 05:05:29 PM PDT 24
Finished Jul 06 05:05:32 PM PDT 24
Peak memory 200112 kb
Host smart-fb41800b-d755-4674-ad7c-7d30ad5948ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841678290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1841678290
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2662618126
Short name T431
Test name
Test status
Simulation time 91905046 ps
CPU time 0.88 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:34 PM PDT 24
Peak memory 200128 kb
Host smart-a251dee0-38fc-432d-bc86-b8e3a8c42e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662618126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2662618126
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3672455624
Short name T176
Test name
Test status
Simulation time 70411362 ps
CPU time 0.79 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:33 PM PDT 24
Peak memory 199920 kb
Host smart-7cdbbe15-4b05-49bd-ac86-4e045b1fcfa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672455624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3672455624
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1526009906
Short name T41
Test name
Test status
Simulation time 1896794233 ps
CPU time 7.46 seconds
Started Jul 06 05:05:30 PM PDT 24
Finished Jul 06 05:05:38 PM PDT 24
Peak memory 221696 kb
Host smart-fd0937c2-d2a3-4545-9a94-46c5a991f051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526009906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1526009906
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.217653291
Short name T311
Test name
Test status
Simulation time 244696370 ps
CPU time 1.03 seconds
Started Jul 06 05:05:45 PM PDT 24
Finished Jul 06 05:05:47 PM PDT 24
Peak memory 217544 kb
Host smart-dde3a26d-7f97-49f4-a614-bac4be9e3c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217653291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.217653291
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2748361719
Short name T259
Test name
Test status
Simulation time 125449335 ps
CPU time 0.82 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:33 PM PDT 24
Peak memory 199924 kb
Host smart-94ba6ae8-b399-47df-bb53-3fbce36aacae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748361719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2748361719
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1222174184
Short name T301
Test name
Test status
Simulation time 795446612 ps
CPU time 4.45 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:37 PM PDT 24
Peak memory 200476 kb
Host smart-37f6432f-4116-49c9-aacc-e6d365bae92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222174184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1222174184
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1977363709
Short name T498
Test name
Test status
Simulation time 178166272 ps
CPU time 1.21 seconds
Started Jul 06 05:05:30 PM PDT 24
Finished Jul 06 05:05:32 PM PDT 24
Peak memory 200112 kb
Host smart-6cbd73ee-bacd-410e-b3a4-faf5dfc379d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977363709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1977363709
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1101340123
Short name T519
Test name
Test status
Simulation time 120068215 ps
CPU time 1.19 seconds
Started Jul 06 05:05:31 PM PDT 24
Finished Jul 06 05:05:33 PM PDT 24
Peak memory 200312 kb
Host smart-d8e67bdc-7af1-45fb-8084-758dd3540c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101340123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1101340123
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2055202941
Short name T321
Test name
Test status
Simulation time 5083395269 ps
CPU time 21.74 seconds
Started Jul 06 05:05:31 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 216380 kb
Host smart-6acb08a5-1d31-45d6-af99-2ccbded23851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055202941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2055202941
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3926431054
Short name T443
Test name
Test status
Simulation time 315450300 ps
CPU time 2.15 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:35 PM PDT 24
Peak memory 200132 kb
Host smart-cb895000-2864-42ef-b8ec-8a1180f0cc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926431054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3926431054
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2896865172
Short name T291
Test name
Test status
Simulation time 122698721 ps
CPU time 1.03 seconds
Started Jul 06 05:05:30 PM PDT 24
Finished Jul 06 05:05:31 PM PDT 24
Peak memory 200092 kb
Host smart-8980bbb4-4da0-41a2-81d3-23a758eb2e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896865172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2896865172
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.782405020
Short name T388
Test name
Test status
Simulation time 68397787 ps
CPU time 0.86 seconds
Started Jul 06 05:05:30 PM PDT 24
Finished Jul 06 05:05:32 PM PDT 24
Peak memory 199888 kb
Host smart-127e0ddf-9ee2-41fd-a261-3a7d2b58a3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782405020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.782405020
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1618819208
Short name T422
Test name
Test status
Simulation time 1895264044 ps
CPU time 7.05 seconds
Started Jul 06 05:05:30 PM PDT 24
Finished Jul 06 05:05:38 PM PDT 24
Peak memory 216864 kb
Host smart-12a0ebb8-2f38-4611-9c08-973d372217ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618819208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1618819208
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1003588837
Short name T181
Test name
Test status
Simulation time 244579747 ps
CPU time 1.07 seconds
Started Jul 06 05:05:41 PM PDT 24
Finished Jul 06 05:05:42 PM PDT 24
Peak memory 217528 kb
Host smart-6e5d4e6e-989e-456f-a0bc-a330c15ca248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003588837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1003588837
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.739534997
Short name T451
Test name
Test status
Simulation time 112317963 ps
CPU time 0.78 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:33 PM PDT 24
Peak memory 199884 kb
Host smart-e3c7c440-db4a-4e7f-911f-30ceb4dfa076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739534997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.739534997
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2385611970
Short name T113
Test name
Test status
Simulation time 815206690 ps
CPU time 3.99 seconds
Started Jul 06 05:05:30 PM PDT 24
Finished Jul 06 05:05:34 PM PDT 24
Peak memory 200272 kb
Host smart-537ae42d-6ddc-4681-9ddd-9d808727f3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385611970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2385611970
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2051355254
Short name T447
Test name
Test status
Simulation time 155408809 ps
CPU time 1.15 seconds
Started Jul 06 05:05:30 PM PDT 24
Finished Jul 06 05:05:31 PM PDT 24
Peak memory 200056 kb
Host smart-04daa708-4e63-4fba-bed5-a62986d40a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051355254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2051355254
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.214365684
Short name T537
Test name
Test status
Simulation time 113277908 ps
CPU time 1.24 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:34 PM PDT 24
Peak memory 200332 kb
Host smart-b810b81a-fe50-417b-bce2-a045b6d4733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214365684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.214365684
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1435430287
Short name T239
Test name
Test status
Simulation time 6384382183 ps
CPU time 25.09 seconds
Started Jul 06 05:05:41 PM PDT 24
Finished Jul 06 05:06:07 PM PDT 24
Peak memory 208456 kb
Host smart-bbe63791-3e5a-4faa-819d-0bb504f8cce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435430287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1435430287
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1762942026
Short name T57
Test name
Test status
Simulation time 403416028 ps
CPU time 2.09 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:35 PM PDT 24
Peak memory 200172 kb
Host smart-b703b60e-da8d-4cd4-be09-f619435c6edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762942026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1762942026
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1953918470
Short name T2
Test name
Test status
Simulation time 59493300 ps
CPU time 0.8 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:34 PM PDT 24
Peak memory 200072 kb
Host smart-894ea388-de4f-4a8c-82a0-61de16bb5faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953918470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1953918470
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3224750940
Short name T479
Test name
Test status
Simulation time 69370303 ps
CPU time 0.77 seconds
Started Jul 06 05:04:58 PM PDT 24
Finished Jul 06 05:04:59 PM PDT 24
Peak memory 199968 kb
Host smart-39ece248-0d75-4925-9267-fc670fefb069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224750940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3224750940
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.238112312
Short name T429
Test name
Test status
Simulation time 2365468389 ps
CPU time 8.26 seconds
Started Jul 06 05:05:00 PM PDT 24
Finished Jul 06 05:05:09 PM PDT 24
Peak memory 217844 kb
Host smart-a5280b2d-6e19-4cf7-ae1d-db77766d8558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238112312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.238112312
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3866491927
Short name T152
Test name
Test status
Simulation time 244786136 ps
CPU time 1.13 seconds
Started Jul 06 05:05:02 PM PDT 24
Finished Jul 06 05:05:04 PM PDT 24
Peak memory 217452 kb
Host smart-8908afee-4066-4191-a1ce-45074a2a2d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866491927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3866491927
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2304521202
Short name T524
Test name
Test status
Simulation time 183454717 ps
CPU time 0.88 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:04:58 PM PDT 24
Peak memory 199956 kb
Host smart-4dd6e280-0554-45d4-831d-b278d834f441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304521202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2304521202
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.299718405
Short name T112
Test name
Test status
Simulation time 1295709420 ps
CPU time 5.37 seconds
Started Jul 06 05:04:59 PM PDT 24
Finished Jul 06 05:05:05 PM PDT 24
Peak memory 200404 kb
Host smart-42260c9e-577a-4eb6-ba07-eb650368ac8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299718405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.299718405
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3571607290
Short name T73
Test name
Test status
Simulation time 8278229626 ps
CPU time 15.98 seconds
Started Jul 06 05:04:59 PM PDT 24
Finished Jul 06 05:05:15 PM PDT 24
Peak memory 217348 kb
Host smart-c602262e-d3f7-400b-8fa8-4af4dfa7c695
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571607290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3571607290
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.645101897
Short name T440
Test name
Test status
Simulation time 107072542 ps
CPU time 1.04 seconds
Started Jul 06 05:05:01 PM PDT 24
Finished Jul 06 05:05:03 PM PDT 24
Peak memory 200056 kb
Host smart-dd37b015-bec7-46b8-9b5e-7e0c8636fef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645101897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.645101897
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3689627
Short name T478
Test name
Test status
Simulation time 196693859 ps
CPU time 1.41 seconds
Started Jul 06 05:04:56 PM PDT 24
Finished Jul 06 05:04:58 PM PDT 24
Peak memory 200256 kb
Host smart-78f0aaa7-b66d-472a-b426-447d27c090f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3689627
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.4258493132
Short name T325
Test name
Test status
Simulation time 6134751245 ps
CPU time 28.33 seconds
Started Jul 06 05:04:59 PM PDT 24
Finished Jul 06 05:05:27 PM PDT 24
Peak memory 208660 kb
Host smart-4e610b9d-217f-4e00-a9a0-7860a78e0193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258493132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.4258493132
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2444747347
Short name T523
Test name
Test status
Simulation time 126413270 ps
CPU time 1.64 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:04:59 PM PDT 24
Peak memory 208256 kb
Host smart-ea269bc5-0ab7-4d7d-9b99-1ff7ea2fc7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444747347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2444747347
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.437858368
Short name T23
Test name
Test status
Simulation time 198314855 ps
CPU time 1.2 seconds
Started Jul 06 05:04:59 PM PDT 24
Finished Jul 06 05:05:01 PM PDT 24
Peak memory 200140 kb
Host smart-57c88604-05a7-4444-a6ad-fea4307d985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437858368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.437858368
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1859275196
Short name T456
Test name
Test status
Simulation time 77913382 ps
CPU time 0.83 seconds
Started Jul 06 05:05:36 PM PDT 24
Finished Jul 06 05:05:37 PM PDT 24
Peak memory 199860 kb
Host smart-50f0d924-a3b8-44bd-891a-baaaa3d58ea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859275196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1859275196
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1245080148
Short name T35
Test name
Test status
Simulation time 1883579229 ps
CPU time 7.56 seconds
Started Jul 06 05:05:29 PM PDT 24
Finished Jul 06 05:05:37 PM PDT 24
Peak memory 221756 kb
Host smart-ef48c7a3-79fb-48f5-a47a-1ffbf356448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245080148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1245080148
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2293992297
Short name T252
Test name
Test status
Simulation time 244831614 ps
CPU time 1.07 seconds
Started Jul 06 05:05:30 PM PDT 24
Finished Jul 06 05:05:32 PM PDT 24
Peak memory 217552 kb
Host smart-130c4d79-d1f0-41dd-8717-e3a6d41abf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293992297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2293992297
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3581481765
Short name T225
Test name
Test status
Simulation time 119914295 ps
CPU time 0.82 seconds
Started Jul 06 05:05:36 PM PDT 24
Finished Jul 06 05:05:38 PM PDT 24
Peak memory 199936 kb
Host smart-3206c183-3520-40ab-8882-8440d19ff9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581481765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3581481765
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.842010549
Short name T482
Test name
Test status
Simulation time 1320001635 ps
CPU time 5.32 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:38 PM PDT 24
Peak memory 200476 kb
Host smart-620bf0b5-b12d-414e-aa56-814b697bcbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842010549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.842010549
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4222832097
Short name T455
Test name
Test status
Simulation time 146075406 ps
CPU time 1.14 seconds
Started Jul 06 05:05:45 PM PDT 24
Finished Jul 06 05:05:47 PM PDT 24
Peak memory 200156 kb
Host smart-a345bdc9-9c03-4aab-a34b-07a8e834f731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222832097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4222832097
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3778451257
Short name T491
Test name
Test status
Simulation time 199494210 ps
CPU time 1.33 seconds
Started Jul 06 05:05:33 PM PDT 24
Finished Jul 06 05:05:35 PM PDT 24
Peak memory 200368 kb
Host smart-6c977549-4d24-4a6c-aeba-218dc523b006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778451257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3778451257
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.313461132
Short name T25
Test name
Test status
Simulation time 155105484 ps
CPU time 1.11 seconds
Started Jul 06 05:05:35 PM PDT 24
Finished Jul 06 05:05:36 PM PDT 24
Peak memory 200140 kb
Host smart-7328c0eb-485a-4ede-b171-f7261ecf1172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313461132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.313461132
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.719624808
Short name T465
Test name
Test status
Simulation time 504623716 ps
CPU time 2.64 seconds
Started Jul 06 05:05:33 PM PDT 24
Finished Jul 06 05:05:36 PM PDT 24
Peak memory 200152 kb
Host smart-65080ebe-1ba7-41d4-b1c9-6a458f8bdf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719624808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.719624808
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3803742072
Short name T211
Test name
Test status
Simulation time 107238582 ps
CPU time 0.93 seconds
Started Jul 06 05:05:32 PM PDT 24
Finished Jul 06 05:05:34 PM PDT 24
Peak memory 200072 kb
Host smart-139ae05d-3f34-4108-92bf-213a51aac4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803742072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3803742072
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1883406636
Short name T423
Test name
Test status
Simulation time 61113259 ps
CPU time 0.74 seconds
Started Jul 06 05:05:35 PM PDT 24
Finished Jul 06 05:05:36 PM PDT 24
Peak memory 199956 kb
Host smart-c5a95bf1-2726-4cd3-8dc6-009d158e43b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883406636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1883406636
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3037726545
Short name T261
Test name
Test status
Simulation time 1884497281 ps
CPU time 6.72 seconds
Started Jul 06 05:05:41 PM PDT 24
Finished Jul 06 05:05:48 PM PDT 24
Peak memory 217744 kb
Host smart-ee419bbd-5a7d-4608-8382-f1517f4206a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037726545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3037726545
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2888183354
Short name T350
Test name
Test status
Simulation time 243831667 ps
CPU time 1.04 seconds
Started Jul 06 05:05:38 PM PDT 24
Finished Jul 06 05:05:39 PM PDT 24
Peak memory 217536 kb
Host smart-748a5cdc-86bb-41df-b8ea-472291db9046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888183354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2888183354
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.777699639
Short name T182
Test name
Test status
Simulation time 236244854 ps
CPU time 0.92 seconds
Started Jul 06 05:05:36 PM PDT 24
Finished Jul 06 05:05:38 PM PDT 24
Peak memory 199896 kb
Host smart-7c206320-5019-41f4-858e-22cf77ad7e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777699639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.777699639
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1043522476
Short name T101
Test name
Test status
Simulation time 1505503669 ps
CPU time 6.4 seconds
Started Jul 06 05:05:37 PM PDT 24
Finished Jul 06 05:05:44 PM PDT 24
Peak memory 200472 kb
Host smart-c6cb4a15-0467-4f0a-86ae-c511f99b97ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043522476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1043522476
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1854135811
Short name T262
Test name
Test status
Simulation time 147615653 ps
CPU time 1.16 seconds
Started Jul 06 05:05:46 PM PDT 24
Finished Jul 06 05:05:48 PM PDT 24
Peak memory 200136 kb
Host smart-b0b884ab-3c94-4f31-95f4-fc3df106b564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854135811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1854135811
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1673340407
Short name T248
Test name
Test status
Simulation time 252527561 ps
CPU time 1.47 seconds
Started Jul 06 05:05:45 PM PDT 24
Finished Jul 06 05:05:48 PM PDT 24
Peak memory 200352 kb
Host smart-f3109a1e-85f4-47f4-8297-dfb0c92b0637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673340407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1673340407
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3937433749
Short name T174
Test name
Test status
Simulation time 384165533 ps
CPU time 1.75 seconds
Started Jul 06 05:05:37 PM PDT 24
Finished Jul 06 05:05:39 PM PDT 24
Peak memory 200232 kb
Host smart-88f2408b-6a65-4a6d-879f-e204a8148099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937433749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3937433749
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3622584910
Short name T294
Test name
Test status
Simulation time 145396970 ps
CPU time 1.78 seconds
Started Jul 06 05:05:36 PM PDT 24
Finished Jul 06 05:05:38 PM PDT 24
Peak memory 208316 kb
Host smart-1a2a0b80-314a-45f3-b186-9e4c9a550d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622584910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3622584910
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.253073167
Short name T384
Test name
Test status
Simulation time 155117254 ps
CPU time 1.2 seconds
Started Jul 06 05:05:45 PM PDT 24
Finished Jul 06 05:05:48 PM PDT 24
Peak memory 200384 kb
Host smart-f170bdd4-6a1b-4be9-8088-23a920c2ed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253073167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.253073167
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1328887162
Short name T80
Test name
Test status
Simulation time 84659307 ps
CPU time 0.77 seconds
Started Jul 06 05:05:35 PM PDT 24
Finished Jul 06 05:05:37 PM PDT 24
Peak memory 199864 kb
Host smart-0dfae37a-7540-44aa-9f25-0ea90651987d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328887162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1328887162
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1079661464
Short name T34
Test name
Test status
Simulation time 2180759246 ps
CPU time 8.72 seconds
Started Jul 06 05:05:38 PM PDT 24
Finished Jul 06 05:05:47 PM PDT 24
Peak memory 221816 kb
Host smart-6514c38f-db69-40f8-b00e-212276c38ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079661464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1079661464
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1390448093
Short name T360
Test name
Test status
Simulation time 244982357 ps
CPU time 1.03 seconds
Started Jul 06 05:05:41 PM PDT 24
Finished Jul 06 05:05:43 PM PDT 24
Peak memory 217508 kb
Host smart-9679376c-3661-4b71-9c47-4961f6db0ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390448093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1390448093
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3143378878
Short name T372
Test name
Test status
Simulation time 117486903 ps
CPU time 0.78 seconds
Started Jul 06 05:05:37 PM PDT 24
Finished Jul 06 05:05:38 PM PDT 24
Peak memory 199956 kb
Host smart-7b384c4c-e3f3-4304-8da8-58f963081b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143378878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3143378878
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2238432488
Short name T462
Test name
Test status
Simulation time 1466907851 ps
CPU time 6.26 seconds
Started Jul 06 05:05:46 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 200416 kb
Host smart-3124a23f-7501-45c7-a4f7-374b11a1e209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238432488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2238432488
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2711216346
Short name T132
Test name
Test status
Simulation time 105747350 ps
CPU time 1.05 seconds
Started Jul 06 05:05:41 PM PDT 24
Finished Jul 06 05:05:43 PM PDT 24
Peak memory 199924 kb
Host smart-9bcf2acf-64cc-48d4-9552-597214b2995c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711216346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2711216346
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3090710618
Short name T300
Test name
Test status
Simulation time 197525978 ps
CPU time 1.38 seconds
Started Jul 06 05:05:41 PM PDT 24
Finished Jul 06 05:05:43 PM PDT 24
Peak memory 200344 kb
Host smart-2720d9c3-db32-4826-ac79-211fc8068649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090710618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3090710618
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1004413248
Short name T280
Test name
Test status
Simulation time 2911003982 ps
CPU time 10.15 seconds
Started Jul 06 05:05:46 PM PDT 24
Finished Jul 06 05:05:57 PM PDT 24
Peak memory 200472 kb
Host smart-7b0cdb55-5179-41a3-a23c-0825db02c129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004413248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1004413248
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.985276300
Short name T178
Test name
Test status
Simulation time 143707156 ps
CPU time 1.77 seconds
Started Jul 06 05:05:46 PM PDT 24
Finished Jul 06 05:05:49 PM PDT 24
Peak memory 200160 kb
Host smart-014a064f-d090-463c-ab2a-3e1454a5b68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985276300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.985276300
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2938699672
Short name T207
Test name
Test status
Simulation time 220240137 ps
CPU time 1.23 seconds
Started Jul 06 05:05:35 PM PDT 24
Finished Jul 06 05:05:37 PM PDT 24
Peak memory 199988 kb
Host smart-be5e64f7-7b5d-4117-8ac3-0e225406d40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938699672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2938699672
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.90420474
Short name T340
Test name
Test status
Simulation time 59606122 ps
CPU time 0.76 seconds
Started Jul 06 05:05:41 PM PDT 24
Finished Jul 06 05:05:42 PM PDT 24
Peak memory 199880 kb
Host smart-9d7042c3-e8de-4910-924d-34372fd4e1fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90420474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.90420474
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2341209980
Short name T428
Test name
Test status
Simulation time 2358886976 ps
CPU time 8.93 seconds
Started Jul 06 05:05:40 PM PDT 24
Finished Jul 06 05:05:49 PM PDT 24
Peak memory 217900 kb
Host smart-4e4d0edd-a1a1-4dac-882b-cd1eecb15b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341209980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2341209980
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3228079013
Short name T271
Test name
Test status
Simulation time 243620982 ps
CPU time 1.12 seconds
Started Jul 06 05:05:39 PM PDT 24
Finished Jul 06 05:05:40 PM PDT 24
Peak memory 217472 kb
Host smart-a697c053-bb81-4710-9a10-7a385e7c99a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228079013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3228079013
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.663259235
Short name T19
Test name
Test status
Simulation time 173663189 ps
CPU time 0.87 seconds
Started Jul 06 05:05:37 PM PDT 24
Finished Jul 06 05:05:38 PM PDT 24
Peak memory 199972 kb
Host smart-e7a696af-0e2b-4590-96cd-a85801ed0f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663259235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.663259235
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.5973450
Short name T169
Test name
Test status
Simulation time 1440283664 ps
CPU time 6.05 seconds
Started Jul 06 05:05:38 PM PDT 24
Finished Jul 06 05:05:44 PM PDT 24
Peak memory 200328 kb
Host smart-38b381e3-e976-410c-96e5-185ee9d4626d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5973450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.5973450
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1104647820
Short name T179
Test name
Test status
Simulation time 153541990 ps
CPU time 1.17 seconds
Started Jul 06 05:05:41 PM PDT 24
Finished Jul 06 05:05:43 PM PDT 24
Peak memory 200064 kb
Host smart-182a0fee-83eb-4318-8f27-157189bb1443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104647820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1104647820
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1770635164
Short name T345
Test name
Test status
Simulation time 209277325 ps
CPU time 1.44 seconds
Started Jul 06 05:05:37 PM PDT 24
Finished Jul 06 05:05:39 PM PDT 24
Peak memory 200344 kb
Host smart-1f2d1311-732a-4f65-8047-50e761b53627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770635164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1770635164
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3838758744
Short name T272
Test name
Test status
Simulation time 17306496155 ps
CPU time 56.8 seconds
Started Jul 06 05:05:39 PM PDT 24
Finished Jul 06 05:06:37 PM PDT 24
Peak memory 208628 kb
Host smart-26ba3264-101b-4954-b126-b84c842109c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838758744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3838758744
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3128336380
Short name T461
Test name
Test status
Simulation time 365038519 ps
CPU time 2.05 seconds
Started Jul 06 05:05:44 PM PDT 24
Finished Jul 06 05:05:47 PM PDT 24
Peak memory 200452 kb
Host smart-7b011bf1-6c4e-4f95-91e8-52bf8578c48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128336380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3128336380
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1441865782
Short name T137
Test name
Test status
Simulation time 178648926 ps
CPU time 1.16 seconds
Started Jul 06 05:05:47 PM PDT 24
Finished Jul 06 05:05:48 PM PDT 24
Peak memory 200132 kb
Host smart-6922293b-8bba-4a2e-bf5e-f36bab004534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441865782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1441865782
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3003460032
Short name T530
Test name
Test status
Simulation time 66771903 ps
CPU time 0.74 seconds
Started Jul 06 05:05:46 PM PDT 24
Finished Jul 06 05:05:47 PM PDT 24
Peak memory 199916 kb
Host smart-55ad2dce-fdbe-4faf-8de9-036c709fcc9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003460032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3003460032
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.4112089313
Short name T40
Test name
Test status
Simulation time 2360125273 ps
CPU time 9.31 seconds
Started Jul 06 05:05:45 PM PDT 24
Finished Jul 06 05:05:56 PM PDT 24
Peak memory 217864 kb
Host smart-eb34f8b2-5943-4f8e-b502-167acd4efb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112089313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.4112089313
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2930995225
Short name T534
Test name
Test status
Simulation time 244197321 ps
CPU time 1.08 seconds
Started Jul 06 05:05:43 PM PDT 24
Finished Jul 06 05:05:45 PM PDT 24
Peak memory 217464 kb
Host smart-04bc9b53-f9a1-47d5-8501-43c7f2de5239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930995225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2930995225
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1191219006
Short name T379
Test name
Test status
Simulation time 206108015 ps
CPU time 0.89 seconds
Started Jul 06 05:05:40 PM PDT 24
Finished Jul 06 05:05:41 PM PDT 24
Peak memory 199852 kb
Host smart-45cac0cd-7c44-4f5a-86e5-7a9b05e04ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191219006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1191219006
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3846804457
Short name T536
Test name
Test status
Simulation time 1059954289 ps
CPU time 4.99 seconds
Started Jul 06 05:05:43 PM PDT 24
Finished Jul 06 05:05:49 PM PDT 24
Peak memory 200400 kb
Host smart-4208c2db-2c6a-40d2-a0f2-f56805fc7dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846804457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3846804457
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3508056017
Short name T147
Test name
Test status
Simulation time 104356455 ps
CPU time 1.04 seconds
Started Jul 06 05:05:44 PM PDT 24
Finished Jul 06 05:05:46 PM PDT 24
Peak memory 200408 kb
Host smart-55082cae-81fc-47f1-8144-2eb7eaa4b10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508056017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3508056017
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3669831902
Short name T438
Test name
Test status
Simulation time 127075606 ps
CPU time 1.22 seconds
Started Jul 06 05:05:42 PM PDT 24
Finished Jul 06 05:05:44 PM PDT 24
Peak memory 200276 kb
Host smart-26b9690e-4eec-4ed0-b7cb-809187bb7b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669831902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3669831902
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.912334499
Short name T109
Test name
Test status
Simulation time 6890964102 ps
CPU time 34.45 seconds
Started Jul 06 05:05:42 PM PDT 24
Finished Jul 06 05:06:17 PM PDT 24
Peak memory 216856 kb
Host smart-ef69124f-1799-42bb-9cb6-3c7fb94b0dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912334499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.912334499
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3152750301
Short name T92
Test name
Test status
Simulation time 150410965 ps
CPU time 1.93 seconds
Started Jul 06 05:05:42 PM PDT 24
Finished Jul 06 05:05:45 PM PDT 24
Peak memory 200176 kb
Host smart-bb7ac6d7-e2ea-4875-a80e-b46b008a56a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152750301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3152750301
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2234512548
Short name T151
Test name
Test status
Simulation time 134827474 ps
CPU time 1.14 seconds
Started Jul 06 05:05:40 PM PDT 24
Finished Jul 06 05:05:41 PM PDT 24
Peak memory 200116 kb
Host smart-b8e9c62e-1114-4e10-bb2f-511605470c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234512548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2234512548
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3582020537
Short name T265
Test name
Test status
Simulation time 71025010 ps
CPU time 0.81 seconds
Started Jul 06 05:05:40 PM PDT 24
Finished Jul 06 05:05:41 PM PDT 24
Peak memory 199924 kb
Host smart-dd5b0576-616e-475d-806c-efc15a5d12ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582020537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3582020537
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.4249986073
Short name T45
Test name
Test status
Simulation time 1216159525 ps
CPU time 6.24 seconds
Started Jul 06 05:05:43 PM PDT 24
Finished Jul 06 05:05:50 PM PDT 24
Peak memory 217736 kb
Host smart-d20e9bba-79e6-4a89-adea-8b3342f97bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249986073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.4249986073
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3414347993
Short name T503
Test name
Test status
Simulation time 244983216 ps
CPU time 1.03 seconds
Started Jul 06 05:05:40 PM PDT 24
Finished Jul 06 05:05:41 PM PDT 24
Peak memory 217524 kb
Host smart-f10138c0-a84a-4eef-9473-a926f5e59e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414347993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3414347993
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.466294688
Short name T20
Test name
Test status
Simulation time 163652592 ps
CPU time 0.92 seconds
Started Jul 06 05:05:46 PM PDT 24
Finished Jul 06 05:05:48 PM PDT 24
Peak memory 199912 kb
Host smart-d0721812-bd4d-46fb-92d3-98f8bcec857c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466294688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.466294688
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.571040602
Short name T8
Test name
Test status
Simulation time 917252822 ps
CPU time 4.82 seconds
Started Jul 06 05:05:42 PM PDT 24
Finished Jul 06 05:05:48 PM PDT 24
Peak memory 200436 kb
Host smart-49ec3abc-b810-451d-9db6-23c2673eeb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571040602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.571040602
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1339390132
Short name T140
Test name
Test status
Simulation time 101487626 ps
CPU time 1.06 seconds
Started Jul 06 05:05:42 PM PDT 24
Finished Jul 06 05:05:44 PM PDT 24
Peak memory 200152 kb
Host smart-b4a70c33-d233-4c61-bbb3-c1d2cbb99148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339390132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1339390132
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.4182523001
Short name T195
Test name
Test status
Simulation time 113981642 ps
CPU time 1.2 seconds
Started Jul 06 05:05:40 PM PDT 24
Finished Jul 06 05:05:41 PM PDT 24
Peak memory 200396 kb
Host smart-b0778071-051f-496e-95c2-bdcf9e95b2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182523001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4182523001
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1547386272
Short name T406
Test name
Test status
Simulation time 14701812704 ps
CPU time 49.58 seconds
Started Jul 06 05:05:43 PM PDT 24
Finished Jul 06 05:06:33 PM PDT 24
Peak memory 216820 kb
Host smart-46ecb268-1a83-4fb2-839e-e7e173712742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547386272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1547386272
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2603732931
Short name T525
Test name
Test status
Simulation time 109903663 ps
CPU time 1.43 seconds
Started Jul 06 05:05:42 PM PDT 24
Finished Jul 06 05:05:44 PM PDT 24
Peak memory 200088 kb
Host smart-3f1a811d-506c-4d98-826e-6a98af5eed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603732931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2603732931
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3073517854
Short name T1
Test name
Test status
Simulation time 68329188 ps
CPU time 0.78 seconds
Started Jul 06 05:05:43 PM PDT 24
Finished Jul 06 05:05:44 PM PDT 24
Peak memory 200436 kb
Host smart-18814ee1-390a-4a47-90da-5bae74cac19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073517854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3073517854
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3203527625
Short name T184
Test name
Test status
Simulation time 77289818 ps
CPU time 0.78 seconds
Started Jul 06 05:05:50 PM PDT 24
Finished Jul 06 05:05:52 PM PDT 24
Peak memory 199936 kb
Host smart-bca8b671-bcff-48c4-a766-5d2ea069582b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203527625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3203527625
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3028620621
Short name T353
Test name
Test status
Simulation time 1223623279 ps
CPU time 5.95 seconds
Started Jul 06 05:05:49 PM PDT 24
Finished Jul 06 05:05:55 PM PDT 24
Peak memory 217004 kb
Host smart-e6ec8670-c6b8-4c7b-aec3-961b632f80e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028620621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3028620621
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.847096147
Short name T430
Test name
Test status
Simulation time 244746564 ps
CPU time 1.07 seconds
Started Jul 06 05:05:46 PM PDT 24
Finished Jul 06 05:05:48 PM PDT 24
Peak memory 217500 kb
Host smart-54cf78a1-404a-41bd-936c-8ed120304bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847096147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.847096147
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2290140748
Short name T240
Test name
Test status
Simulation time 77900800 ps
CPU time 0.73 seconds
Started Jul 06 05:05:41 PM PDT 24
Finished Jul 06 05:05:42 PM PDT 24
Peak memory 199888 kb
Host smart-8fe0ac7f-6bbd-492f-b146-55e8d171a890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290140748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2290140748
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.592070761
Short name T102
Test name
Test status
Simulation time 824706785 ps
CPU time 3.97 seconds
Started Jul 06 05:05:42 PM PDT 24
Finished Jul 06 05:05:47 PM PDT 24
Peak memory 200432 kb
Host smart-2ca88df7-9ae9-4179-9f2e-8f3295bc571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592070761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.592070761
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3741948481
Short name T288
Test name
Test status
Simulation time 103659322 ps
CPU time 1.05 seconds
Started Jul 06 05:05:44 PM PDT 24
Finished Jul 06 05:05:46 PM PDT 24
Peak memory 200060 kb
Host smart-83309629-418c-42c9-8768-9e3b3a8e4c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741948481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3741948481
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1797195699
Short name T6
Test name
Test status
Simulation time 121622762 ps
CPU time 1.27 seconds
Started Jul 06 05:05:45 PM PDT 24
Finished Jul 06 05:05:47 PM PDT 24
Peak memory 200688 kb
Host smart-ea246db3-ffc8-48ec-963e-47704b882d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797195699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1797195699
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1903452828
Short name T215
Test name
Test status
Simulation time 332358413 ps
CPU time 1.61 seconds
Started Jul 06 05:05:47 PM PDT 24
Finished Jul 06 05:05:49 PM PDT 24
Peak memory 200148 kb
Host smart-859fc6bd-9c61-49d0-b0dc-724bba872a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903452828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1903452828
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.4042634774
Short name T219
Test name
Test status
Simulation time 95776569 ps
CPU time 0.88 seconds
Started Jul 06 05:05:45 PM PDT 24
Finished Jul 06 05:05:47 PM PDT 24
Peak memory 200056 kb
Host smart-99dbc3d1-0837-4c5b-a3ce-2c9231c3d686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042634774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.4042634774
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1892349621
Short name T254
Test name
Test status
Simulation time 58324237 ps
CPU time 0.72 seconds
Started Jul 06 05:05:47 PM PDT 24
Finished Jul 06 05:05:49 PM PDT 24
Peak memory 199880 kb
Host smart-d88da3f4-6700-404a-b35a-c71b09d1553f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892349621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1892349621
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3272222263
Short name T33
Test name
Test status
Simulation time 1230208555 ps
CPU time 5.31 seconds
Started Jul 06 05:05:49 PM PDT 24
Finished Jul 06 05:05:54 PM PDT 24
Peak memory 217828 kb
Host smart-590ca635-fcc7-4629-a158-72fc8aa50da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272222263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3272222263
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3606797142
Short name T231
Test name
Test status
Simulation time 244625015 ps
CPU time 1.1 seconds
Started Jul 06 05:05:47 PM PDT 24
Finished Jul 06 05:05:49 PM PDT 24
Peak memory 217552 kb
Host smart-a1083c62-dd02-4bed-8091-a916e05e5a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606797142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3606797142
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.729407463
Short name T409
Test name
Test status
Simulation time 118872219 ps
CPU time 0.77 seconds
Started Jul 06 05:05:46 PM PDT 24
Finished Jul 06 05:05:47 PM PDT 24
Peak memory 199880 kb
Host smart-a5a19635-f491-4994-a23c-f94a1ec73f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729407463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.729407463
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1472319859
Short name T201
Test name
Test status
Simulation time 1146576905 ps
CPU time 5.15 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:05:57 PM PDT 24
Peak memory 200392 kb
Host smart-03ff1f96-4c27-4d4f-bc43-85b54394d33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472319859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1472319859
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1521136326
Short name T202
Test name
Test status
Simulation time 157452692 ps
CPU time 1.16 seconds
Started Jul 06 05:05:50 PM PDT 24
Finished Jul 06 05:05:51 PM PDT 24
Peak memory 200152 kb
Host smart-60b01d6d-b49d-4fee-935d-29eab1be0c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521136326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1521136326
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2396641260
Short name T494
Test name
Test status
Simulation time 200734624 ps
CPU time 1.31 seconds
Started Jul 06 05:05:46 PM PDT 24
Finished Jul 06 05:05:48 PM PDT 24
Peak memory 200340 kb
Host smart-fcc0d8f6-d43c-40ba-a47d-3bfdb92b1394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396641260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2396641260
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3490969599
Short name T175
Test name
Test status
Simulation time 7467008415 ps
CPU time 28.8 seconds
Started Jul 06 05:05:49 PM PDT 24
Finished Jul 06 05:06:18 PM PDT 24
Peak memory 200528 kb
Host smart-afed3a59-fdc7-47d0-95aa-e11af8165d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490969599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3490969599
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3997679190
Short name T232
Test name
Test status
Simulation time 117024092 ps
CPU time 1.49 seconds
Started Jul 06 05:05:48 PM PDT 24
Finished Jul 06 05:05:50 PM PDT 24
Peak memory 200160 kb
Host smart-11bd6fcc-7014-4c71-a907-15dc466fad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997679190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3997679190
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.7536736
Short name T529
Test name
Test status
Simulation time 228951285 ps
CPU time 1.34 seconds
Started Jul 06 05:05:49 PM PDT 24
Finished Jul 06 05:05:51 PM PDT 24
Peak memory 200048 kb
Host smart-14d88307-465c-42e5-b0e8-a6fe048522e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7536736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.7536736
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.717311752
Short name T52
Test name
Test status
Simulation time 65286366 ps
CPU time 0.74 seconds
Started Jul 06 05:05:50 PM PDT 24
Finished Jul 06 05:05:51 PM PDT 24
Peak memory 199936 kb
Host smart-493ea32b-0e6a-4f40-9a20-591f2e3729bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717311752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.717311752
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2060271389
Short name T37
Test name
Test status
Simulation time 1218367201 ps
CPU time 5.76 seconds
Started Jul 06 05:05:49 PM PDT 24
Finished Jul 06 05:05:56 PM PDT 24
Peak memory 216764 kb
Host smart-807ec427-f872-486f-adf6-4dd185aeb8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060271389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2060271389
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1010202271
Short name T234
Test name
Test status
Simulation time 243833480 ps
CPU time 1.14 seconds
Started Jul 06 05:05:48 PM PDT 24
Finished Jul 06 05:05:50 PM PDT 24
Peak memory 217536 kb
Host smart-7237c84f-718d-42c9-93bb-564593bb502d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010202271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1010202271
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2009097872
Short name T204
Test name
Test status
Simulation time 194649326 ps
CPU time 0.89 seconds
Started Jul 06 05:05:47 PM PDT 24
Finished Jul 06 05:05:48 PM PDT 24
Peak memory 199936 kb
Host smart-bc10ee36-7f5c-4170-b453-90df17121cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009097872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2009097872
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1485776749
Short name T382
Test name
Test status
Simulation time 918671222 ps
CPU time 4.59 seconds
Started Jul 06 05:05:48 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 200476 kb
Host smart-f0134168-b3d0-4304-a682-561ca6870883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485776749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1485776749
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3463352656
Short name T4
Test name
Test status
Simulation time 157078556 ps
CPU time 1.1 seconds
Started Jul 06 05:05:48 PM PDT 24
Finished Jul 06 05:05:49 PM PDT 24
Peak memory 200112 kb
Host smart-40455d45-6b30-44a1-99d8-c0f52901c825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463352656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3463352656
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2931298205
Short name T535
Test name
Test status
Simulation time 260542325 ps
CPU time 1.41 seconds
Started Jul 06 05:05:50 PM PDT 24
Finished Jul 06 05:05:52 PM PDT 24
Peak memory 200180 kb
Host smart-77bb4f30-10f7-425d-aba7-840425f76eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931298205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2931298205
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1656441348
Short name T439
Test name
Test status
Simulation time 1442705229 ps
CPU time 6.03 seconds
Started Jul 06 05:05:45 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 200336 kb
Host smart-a648b5f0-a31f-4b6b-9736-0692f328aa79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656441348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1656441348
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3962144282
Short name T516
Test name
Test status
Simulation time 127697504 ps
CPU time 1.5 seconds
Started Jul 06 05:05:50 PM PDT 24
Finished Jul 06 05:05:52 PM PDT 24
Peak memory 199988 kb
Host smart-fc0da691-2c1d-4ce0-8355-dbf57484e702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962144282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3962144282
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2233058535
Short name T138
Test name
Test status
Simulation time 146365930 ps
CPU time 1.07 seconds
Started Jul 06 05:05:47 PM PDT 24
Finished Jul 06 05:05:49 PM PDT 24
Peak memory 200148 kb
Host smart-2aab235c-fc68-4377-b616-216231c422a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233058535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2233058535
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1166777503
Short name T433
Test name
Test status
Simulation time 86195346 ps
CPU time 0.82 seconds
Started Jul 06 05:05:52 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 199956 kb
Host smart-05c913d9-3713-43d3-8630-a2ce7407d9d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166777503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1166777503
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3918060873
Short name T370
Test name
Test status
Simulation time 244161184 ps
CPU time 1.09 seconds
Started Jul 06 05:05:53 PM PDT 24
Finished Jul 06 05:05:55 PM PDT 24
Peak memory 217424 kb
Host smart-0a209885-3912-4b25-9604-adea1ec32062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918060873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3918060873
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1303915982
Short name T14
Test name
Test status
Simulation time 148397141 ps
CPU time 0.82 seconds
Started Jul 06 05:05:52 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 199888 kb
Host smart-7a9c84ea-7b11-4d24-971b-0e472439c8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303915982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1303915982
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3386170244
Short name T539
Test name
Test status
Simulation time 998531348 ps
CPU time 4.8 seconds
Started Jul 06 05:05:50 PM PDT 24
Finished Jul 06 05:05:55 PM PDT 24
Peak memory 200432 kb
Host smart-5a9094fb-a964-496c-884a-2b5350aea225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386170244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3386170244
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4094870630
Short name T163
Test name
Test status
Simulation time 96652255 ps
CPU time 1 seconds
Started Jul 06 05:05:50 PM PDT 24
Finished Jul 06 05:05:52 PM PDT 24
Peak memory 200112 kb
Host smart-28c2c89c-88da-49f6-b5cb-2ddaac148abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094870630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4094870630
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3729082457
Short name T54
Test name
Test status
Simulation time 190945735 ps
CPU time 1.41 seconds
Started Jul 06 05:05:47 PM PDT 24
Finished Jul 06 05:05:49 PM PDT 24
Peak memory 200332 kb
Host smart-63ff1580-e55d-4741-814f-8e3fc1e2bd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729082457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3729082457
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3845613290
Short name T434
Test name
Test status
Simulation time 1669253384 ps
CPU time 7.07 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:05:59 PM PDT 24
Peak memory 200440 kb
Host smart-e3039370-c334-4ed4-a840-9b5f08268c59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845613290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3845613290
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2077671805
Short name T513
Test name
Test status
Simulation time 157233595 ps
CPU time 1.96 seconds
Started Jul 06 05:05:49 PM PDT 24
Finished Jul 06 05:05:52 PM PDT 24
Peak memory 200176 kb
Host smart-59aeedea-773d-483e-bad8-4140eb6c81cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077671805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2077671805
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3645717994
Short name T228
Test name
Test status
Simulation time 89818370 ps
CPU time 0.84 seconds
Started Jul 06 05:05:48 PM PDT 24
Finished Jul 06 05:05:49 PM PDT 24
Peak memory 200148 kb
Host smart-bdc3fecc-535c-4b8a-b275-652699293f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645717994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3645717994
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.4118519446
Short name T78
Test name
Test status
Simulation time 63282286 ps
CPU time 0.75 seconds
Started Jul 06 05:04:58 PM PDT 24
Finished Jul 06 05:04:59 PM PDT 24
Peak memory 199844 kb
Host smart-0bd8c6c6-8eee-4ee7-a2d2-57f0c09c7473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118519446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.4118519446
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3660023336
Short name T46
Test name
Test status
Simulation time 1230797006 ps
CPU time 5.52 seconds
Started Jul 06 05:05:03 PM PDT 24
Finished Jul 06 05:05:09 PM PDT 24
Peak memory 217052 kb
Host smart-b79fd710-e1f6-4720-ab41-abe1cc8887aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660023336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3660023336
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1815302640
Short name T258
Test name
Test status
Simulation time 244319729 ps
CPU time 1.09 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:04:59 PM PDT 24
Peak memory 217428 kb
Host smart-8a72d072-af0b-47b4-ac2c-8b6451200581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815302640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1815302640
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2869192312
Short name T490
Test name
Test status
Simulation time 105650547 ps
CPU time 0.78 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:04:58 PM PDT 24
Peak memory 199924 kb
Host smart-53670fd9-a6bf-4b25-aa0d-9323ac468086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869192312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2869192312
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2581662218
Short name T282
Test name
Test status
Simulation time 1388451713 ps
CPU time 5.72 seconds
Started Jul 06 05:05:00 PM PDT 24
Finished Jul 06 05:05:06 PM PDT 24
Peak memory 200412 kb
Host smart-2e858453-8df9-4e64-a5c1-cb7d6ba1c360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581662218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2581662218
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2289062233
Short name T69
Test name
Test status
Simulation time 8422938443 ps
CPU time 12.6 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:05:10 PM PDT 24
Peak memory 217564 kb
Host smart-a525ea5e-1a1d-438b-bd81-9b9bc8637bd2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289062233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2289062233
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1430191516
Short name T170
Test name
Test status
Simulation time 153943486 ps
CPU time 1.08 seconds
Started Jul 06 05:05:03 PM PDT 24
Finished Jul 06 05:05:05 PM PDT 24
Peak memory 200136 kb
Host smart-29692c08-3f4c-482d-a94f-7d47a9db2048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430191516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1430191516
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.623413835
Short name T90
Test name
Test status
Simulation time 121946310 ps
CPU time 1.21 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:04:59 PM PDT 24
Peak memory 200240 kb
Host smart-4045e542-076a-4b90-9159-f5d132d52306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623413835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.623413835
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3233584338
Short name T390
Test name
Test status
Simulation time 10572985068 ps
CPU time 36.8 seconds
Started Jul 06 05:05:01 PM PDT 24
Finished Jul 06 05:05:38 PM PDT 24
Peak memory 208588 kb
Host smart-2c117c5c-ae0b-49c0-b8a8-4db3d48e92f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233584338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3233584338
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3279571179
Short name T324
Test name
Test status
Simulation time 328705847 ps
CPU time 2.28 seconds
Started Jul 06 05:05:02 PM PDT 24
Finished Jul 06 05:05:04 PM PDT 24
Peak memory 200136 kb
Host smart-6f7323c9-5a53-43c0-88be-23b7ce5c6847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279571179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3279571179
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.582012421
Short name T355
Test name
Test status
Simulation time 128528786 ps
CPU time 1.02 seconds
Started Jul 06 05:05:01 PM PDT 24
Finished Jul 06 05:05:03 PM PDT 24
Peak memory 200060 kb
Host smart-3a929993-a4c9-480a-a057-a2592351ac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582012421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.582012421
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.4052664589
Short name T416
Test name
Test status
Simulation time 74942523 ps
CPU time 0.77 seconds
Started Jul 06 05:05:50 PM PDT 24
Finished Jul 06 05:05:52 PM PDT 24
Peak memory 199928 kb
Host smart-f0c92a9a-eaa4-466d-bc83-c7aace35ef08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052664589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.4052664589
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1996154653
Short name T337
Test name
Test status
Simulation time 1872706700 ps
CPU time 7.48 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:05:59 PM PDT 24
Peak memory 217716 kb
Host smart-d381a865-c3bf-44b8-a4b0-0347256f7327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996154653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1996154653
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2798027288
Short name T82
Test name
Test status
Simulation time 243409127 ps
CPU time 1.2 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 217432 kb
Host smart-64759009-9fab-4cba-b26f-8b20f0f01248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798027288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2798027288
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2531434109
Short name T12
Test name
Test status
Simulation time 134817305 ps
CPU time 0.83 seconds
Started Jul 06 05:05:53 PM PDT 24
Finished Jul 06 05:05:54 PM PDT 24
Peak memory 199968 kb
Host smart-75ff4c7c-e48b-434e-bca0-f94d9bbc5b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531434109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2531434109
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.504824729
Short name T303
Test name
Test status
Simulation time 1538251201 ps
CPU time 6.08 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:05:58 PM PDT 24
Peak memory 200424 kb
Host smart-bc58bb65-8d5d-46ad-8282-7c91a616f419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504824729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.504824729
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.448457331
Short name T298
Test name
Test status
Simulation time 169788084 ps
CPU time 1.24 seconds
Started Jul 06 05:05:50 PM PDT 24
Finished Jul 06 05:05:52 PM PDT 24
Peak memory 200152 kb
Host smart-12e5b8f8-be95-477f-a616-800cd673ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448457331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.448457331
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2021991147
Short name T203
Test name
Test status
Simulation time 110115944 ps
CPU time 1.23 seconds
Started Jul 06 05:05:54 PM PDT 24
Finished Jul 06 05:05:56 PM PDT 24
Peak memory 200196 kb
Host smart-d6d1d867-b02e-4840-80a7-7b5f8f50dbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021991147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2021991147
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2812871079
Short name T167
Test name
Test status
Simulation time 337824025 ps
CPU time 2.17 seconds
Started Jul 06 05:05:53 PM PDT 24
Finished Jul 06 05:05:55 PM PDT 24
Peak memory 200180 kb
Host smart-fc59ba05-0741-497e-90dc-16f983f50466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812871079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2812871079
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1359357374
Short name T444
Test name
Test status
Simulation time 69912936 ps
CPU time 0.8 seconds
Started Jul 06 05:05:53 PM PDT 24
Finished Jul 06 05:05:54 PM PDT 24
Peak memory 200040 kb
Host smart-6b5b558b-9331-4de5-ac27-b7240dcb3732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359357374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1359357374
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1061583214
Short name T187
Test name
Test status
Simulation time 72371662 ps
CPU time 0.8 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 199924 kb
Host smart-da9952e4-40b1-4c60-a7fd-4751ef3ee539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061583214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1061583214
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3367359540
Short name T359
Test name
Test status
Simulation time 1900339346 ps
CPU time 8.24 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:06:00 PM PDT 24
Peak memory 221756 kb
Host smart-13c52674-9ca6-472f-8f8d-a6abcb580f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367359540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3367359540
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3766105112
Short name T264
Test name
Test status
Simulation time 243955381 ps
CPU time 1.19 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 217468 kb
Host smart-20fea471-2323-4ed6-9990-12d0ec92fca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766105112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3766105112
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2104824323
Short name T16
Test name
Test status
Simulation time 164235986 ps
CPU time 0.81 seconds
Started Jul 06 05:05:52 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 199784 kb
Host smart-29e3ed7d-8a93-4c9d-9394-26346cf0fa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104824323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2104824323
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3372289590
Short name T287
Test name
Test status
Simulation time 969241545 ps
CPU time 4.89 seconds
Started Jul 06 05:05:53 PM PDT 24
Finished Jul 06 05:05:58 PM PDT 24
Peak memory 200364 kb
Host smart-c6cecbcf-d038-4158-b3c9-0f48ce200060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372289590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3372289590
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.844203318
Short name T385
Test name
Test status
Simulation time 100749184 ps
CPU time 1 seconds
Started Jul 06 05:05:53 PM PDT 24
Finished Jul 06 05:05:54 PM PDT 24
Peak memory 200144 kb
Host smart-75f21330-c310-4238-b311-7b403d38ac3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844203318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.844203318
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2224264390
Short name T87
Test name
Test status
Simulation time 198787676 ps
CPU time 1.36 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 200368 kb
Host smart-e659a485-53d7-4af1-9f8f-f22d0b88ec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224264390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2224264390
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2192882032
Short name T196
Test name
Test status
Simulation time 6952883853 ps
CPU time 26.41 seconds
Started Jul 06 05:05:54 PM PDT 24
Finished Jul 06 05:06:21 PM PDT 24
Peak memory 208684 kb
Host smart-5787abb1-edf0-46a8-9712-4d6980b0440c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192882032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2192882032
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3864794631
Short name T521
Test name
Test status
Simulation time 326995166 ps
CPU time 2.27 seconds
Started Jul 06 05:05:54 PM PDT 24
Finished Jul 06 05:05:57 PM PDT 24
Peak memory 199900 kb
Host smart-8dcc9059-57c2-4594-9833-edc256eaf43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864794631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3864794631
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3369149921
Short name T354
Test name
Test status
Simulation time 117290855 ps
CPU time 1.02 seconds
Started Jul 06 05:05:56 PM PDT 24
Finished Jul 06 05:05:57 PM PDT 24
Peak memory 200124 kb
Host smart-018d9e55-888d-4393-be85-b0bb79933cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369149921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3369149921
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2088353437
Short name T476
Test name
Test status
Simulation time 61703783 ps
CPU time 0.76 seconds
Started Jul 06 05:05:52 PM PDT 24
Finished Jul 06 05:05:54 PM PDT 24
Peak memory 199972 kb
Host smart-2fd967d9-27c4-40a6-923f-e1d5b58830fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088353437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2088353437
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2428307628
Short name T3
Test name
Test status
Simulation time 1884680306 ps
CPU time 6.94 seconds
Started Jul 06 05:05:53 PM PDT 24
Finished Jul 06 05:06:01 PM PDT 24
Peak memory 217704 kb
Host smart-8f3a7d1c-d1d8-401c-8cc9-2d80beb41afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428307628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2428307628
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1761098646
Short name T154
Test name
Test status
Simulation time 243292276 ps
CPU time 1.05 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 217364 kb
Host smart-4fa01ce3-ac51-45a9-95ce-11f8fb1c1091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761098646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1761098646
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3437208508
Short name T11
Test name
Test status
Simulation time 86915137 ps
CPU time 0.8 seconds
Started Jul 06 05:05:54 PM PDT 24
Finished Jul 06 05:05:55 PM PDT 24
Peak memory 199888 kb
Host smart-816df39e-5888-4327-914a-0dc8c75bdba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437208508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3437208508
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2542779979
Short name T53
Test name
Test status
Simulation time 881287189 ps
CPU time 4.5 seconds
Started Jul 06 05:05:56 PM PDT 24
Finished Jul 06 05:06:01 PM PDT 24
Peak memory 200416 kb
Host smart-aeee7755-49ff-4ffe-984a-87d7d30e6024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542779979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2542779979
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2862785787
Short name T327
Test name
Test status
Simulation time 101407408 ps
CPU time 1 seconds
Started Jul 06 05:05:54 PM PDT 24
Finished Jul 06 05:05:55 PM PDT 24
Peak memory 200104 kb
Host smart-42b7ad7d-f548-4687-bbe3-5d9ca82ac7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862785787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2862785787
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.809843878
Short name T210
Test name
Test status
Simulation time 195661446 ps
CPU time 1.32 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 200176 kb
Host smart-b5ee406e-4b3c-4c95-95b9-a86fa8905ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809843878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.809843878
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1156819253
Short name T313
Test name
Test status
Simulation time 1088532389 ps
CPU time 5.46 seconds
Started Jul 06 05:05:53 PM PDT 24
Finished Jul 06 05:05:59 PM PDT 24
Peak memory 200376 kb
Host smart-288c6e1c-2b6d-4771-9a39-dad74c7048ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156819253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1156819253
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.390102606
Short name T91
Test name
Test status
Simulation time 130073334 ps
CPU time 1.65 seconds
Started Jul 06 05:05:50 PM PDT 24
Finished Jul 06 05:05:52 PM PDT 24
Peak memory 208332 kb
Host smart-eb44faa7-b946-4634-8c25-32bc0e1fcb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390102606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.390102606
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2269489183
Short name T514
Test name
Test status
Simulation time 118407895 ps
CPU time 0.96 seconds
Started Jul 06 05:05:51 PM PDT 24
Finished Jul 06 05:05:53 PM PDT 24
Peak memory 200148 kb
Host smart-f1cc2e4e-3b54-4c9a-8219-dce04495779d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269489183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2269489183
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2809132707
Short name T308
Test name
Test status
Simulation time 74067767 ps
CPU time 0.77 seconds
Started Jul 06 05:05:55 PM PDT 24
Finished Jul 06 05:05:56 PM PDT 24
Peak memory 199960 kb
Host smart-4cdfa7b3-4c03-49ed-a4d0-df4834c19108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809132707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2809132707
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2673490370
Short name T39
Test name
Test status
Simulation time 2168259810 ps
CPU time 7.56 seconds
Started Jul 06 05:05:59 PM PDT 24
Finished Jul 06 05:06:07 PM PDT 24
Peak memory 217888 kb
Host smart-53d37c76-aff5-4f66-975c-2c3445190788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673490370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2673490370
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3543485033
Short name T56
Test name
Test status
Simulation time 244536206 ps
CPU time 1.05 seconds
Started Jul 06 05:05:57 PM PDT 24
Finished Jul 06 05:05:58 PM PDT 24
Peak memory 217548 kb
Host smart-22eedff0-1082-40e2-99eb-d9094958fed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543485033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3543485033
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3673321981
Short name T13
Test name
Test status
Simulation time 97830616 ps
CPU time 0.79 seconds
Started Jul 06 05:05:55 PM PDT 24
Finished Jul 06 05:05:57 PM PDT 24
Peak memory 199940 kb
Host smart-2df22f4b-b1e0-4bf1-ba2f-a409a715af3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673321981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3673321981
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.443124151
Short name T343
Test name
Test status
Simulation time 1261257163 ps
CPU time 4.93 seconds
Started Jul 06 05:05:55 PM PDT 24
Finished Jul 06 05:06:00 PM PDT 24
Peak memory 200424 kb
Host smart-a33df8a9-1cf1-4fdd-bf44-783dc2d14d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443124151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.443124151
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2213088647
Short name T342
Test name
Test status
Simulation time 103945459 ps
CPU time 0.97 seconds
Started Jul 06 05:05:55 PM PDT 24
Finished Jul 06 05:05:56 PM PDT 24
Peak memory 200064 kb
Host smart-f5546a4f-2302-4857-b8cc-1129a6b1a56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213088647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2213088647
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1904851685
Short name T190
Test name
Test status
Simulation time 200410170 ps
CPU time 1.38 seconds
Started Jul 06 05:05:58 PM PDT 24
Finished Jul 06 05:06:00 PM PDT 24
Peak memory 200352 kb
Host smart-140fb028-c586-45d3-a193-f980343450c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904851685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1904851685
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1240324120
Short name T414
Test name
Test status
Simulation time 4126723963 ps
CPU time 16.83 seconds
Started Jul 06 05:05:58 PM PDT 24
Finished Jul 06 05:06:15 PM PDT 24
Peak memory 216876 kb
Host smart-ca7c7172-a3e4-484f-97a1-0c5c32375656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240324120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1240324120
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1762727572
Short name T467
Test name
Test status
Simulation time 462699967 ps
CPU time 2.57 seconds
Started Jul 06 05:05:57 PM PDT 24
Finished Jul 06 05:06:00 PM PDT 24
Peak memory 200160 kb
Host smart-e95155ff-781d-42e3-ad80-4a42cfe8df0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762727572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1762727572
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2902334644
Short name T246
Test name
Test status
Simulation time 149231062 ps
CPU time 1.22 seconds
Started Jul 06 05:06:02 PM PDT 24
Finished Jul 06 05:06:04 PM PDT 24
Peak memory 200288 kb
Host smart-1a46f3f4-ee9b-47cd-bbd3-d3a84b9ccd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902334644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2902334644
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3084549620
Short name T260
Test name
Test status
Simulation time 71487581 ps
CPU time 0.79 seconds
Started Jul 06 05:05:55 PM PDT 24
Finished Jul 06 05:05:56 PM PDT 24
Peak memory 199920 kb
Host smart-869b3b5d-c8d7-48ec-8a83-6721b0e2bc68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084549620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3084549620
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.4080468649
Short name T502
Test name
Test status
Simulation time 2362176941 ps
CPU time 8.22 seconds
Started Jul 06 05:05:57 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 229972 kb
Host smart-ed56c5fe-f0bf-4c13-b440-454b69fa674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080468649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.4080468649
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1011066668
Short name T306
Test name
Test status
Simulation time 245083591 ps
CPU time 1.04 seconds
Started Jul 06 05:06:05 PM PDT 24
Finished Jul 06 05:06:07 PM PDT 24
Peak memory 217508 kb
Host smart-67393c95-1a68-4ca1-b133-e971df7a0e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011066668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1011066668
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3834420317
Short name T442
Test name
Test status
Simulation time 121415135 ps
CPU time 0.78 seconds
Started Jul 06 05:06:06 PM PDT 24
Finished Jul 06 05:06:07 PM PDT 24
Peak memory 199924 kb
Host smart-75cb0d79-cef7-4971-b3f3-1f4f0dc3d1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834420317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3834420317
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.700787303
Short name T130
Test name
Test status
Simulation time 1774954401 ps
CPU time 6.48 seconds
Started Jul 06 05:05:58 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 200432 kb
Host smart-e840691a-881c-4b8c-9a84-aae7a303d6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700787303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.700787303
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.381726498
Short name T377
Test name
Test status
Simulation time 159953176 ps
CPU time 1.13 seconds
Started Jul 06 05:05:57 PM PDT 24
Finished Jul 06 05:05:59 PM PDT 24
Peak memory 200152 kb
Host smart-d4bcd57b-f128-4c6a-8c55-67e61c82f048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381726498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.381726498
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.4209416388
Short name T373
Test name
Test status
Simulation time 205664076 ps
CPU time 1.36 seconds
Started Jul 06 05:05:58 PM PDT 24
Finished Jul 06 05:05:59 PM PDT 24
Peak memory 200364 kb
Host smart-316a9578-3390-42af-8104-6d0aa801a4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209416388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.4209416388
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1874113009
Short name T501
Test name
Test status
Simulation time 218286027 ps
CPU time 1.39 seconds
Started Jul 06 05:06:03 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 200280 kb
Host smart-ed269e7b-49f4-42e1-b417-b697fafa4768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874113009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1874113009
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3265193059
Short name T79
Test name
Test status
Simulation time 345028847 ps
CPU time 2.05 seconds
Started Jul 06 05:05:57 PM PDT 24
Finished Jul 06 05:05:59 PM PDT 24
Peak memory 200172 kb
Host smart-8989f185-d6a0-484c-9129-5cd1e4f22ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265193059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3265193059
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.545946004
Short name T183
Test name
Test status
Simulation time 171497844 ps
CPU time 1.35 seconds
Started Jul 06 05:05:57 PM PDT 24
Finished Jul 06 05:05:59 PM PDT 24
Peak memory 200316 kb
Host smart-066ea2a9-94e8-4f48-a24d-c9f9da3202af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545946004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.545946004
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2093055273
Short name T315
Test name
Test status
Simulation time 71290823 ps
CPU time 0.82 seconds
Started Jul 06 05:06:08 PM PDT 24
Finished Jul 06 05:06:09 PM PDT 24
Peak memory 199816 kb
Host smart-0a5a9ad6-b4e8-4c0c-9c27-6a62a119bf96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093055273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2093055273
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2773159158
Short name T38
Test name
Test status
Simulation time 1897750869 ps
CPU time 7.48 seconds
Started Jul 06 05:06:01 PM PDT 24
Finished Jul 06 05:06:09 PM PDT 24
Peak memory 217812 kb
Host smart-33a43c12-6bcf-4704-8b24-ce3a80365078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773159158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2773159158
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1770093432
Short name T257
Test name
Test status
Simulation time 244029733 ps
CPU time 1.04 seconds
Started Jul 06 05:06:05 PM PDT 24
Finished Jul 06 05:06:07 PM PDT 24
Peak memory 217556 kb
Host smart-bf031323-0817-48d5-88a5-062c3ab93f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770093432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1770093432
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.262163082
Short name T421
Test name
Test status
Simulation time 114661051 ps
CPU time 0.75 seconds
Started Jul 06 05:05:56 PM PDT 24
Finished Jul 06 05:05:57 PM PDT 24
Peak memory 199964 kb
Host smart-a4068fe0-5f1a-4c29-aa88-e8753096328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262163082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.262163082
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1921602977
Short name T26
Test name
Test status
Simulation time 1645171299 ps
CPU time 6.13 seconds
Started Jul 06 05:06:09 PM PDT 24
Finished Jul 06 05:06:16 PM PDT 24
Peak memory 200404 kb
Host smart-055d9a2a-760d-47ed-bf8c-15605b3b56dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921602977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1921602977
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.194014535
Short name T266
Test name
Test status
Simulation time 109064375 ps
CPU time 1.15 seconds
Started Jul 06 05:06:03 PM PDT 24
Finished Jul 06 05:06:04 PM PDT 24
Peak memory 200152 kb
Host smart-d402f6f7-70d0-4b8a-af50-668e24abefd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194014535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.194014535
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3176380638
Short name T27
Test name
Test status
Simulation time 131896892 ps
CPU time 1.18 seconds
Started Jul 06 05:05:55 PM PDT 24
Finished Jul 06 05:05:56 PM PDT 24
Peak memory 200368 kb
Host smart-2c1c2848-1a22-453e-84bc-064c5c0d482a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176380638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3176380638
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2296539350
Short name T110
Test name
Test status
Simulation time 6339822727 ps
CPU time 22.68 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:27 PM PDT 24
Peak memory 200440 kb
Host smart-16d7374e-704b-444e-ad0b-0cd4d7bf9f63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296539350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2296539350
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3853433160
Short name T165
Test name
Test status
Simulation time 131582034 ps
CPU time 1.67 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:06 PM PDT 24
Peak memory 200176 kb
Host smart-63424f08-5785-4de3-b581-2cb9f61c87bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853433160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3853433160
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2804014244
Short name T357
Test name
Test status
Simulation time 154702118 ps
CPU time 1.26 seconds
Started Jul 06 05:06:01 PM PDT 24
Finished Jul 06 05:06:03 PM PDT 24
Peak memory 200352 kb
Host smart-14e87c5c-acb1-47c2-b092-6072965f526e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804014244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2804014244
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1044351282
Short name T486
Test name
Test status
Simulation time 73575893 ps
CPU time 0.8 seconds
Started Jul 06 05:06:06 PM PDT 24
Finished Jul 06 05:06:07 PM PDT 24
Peak memory 199940 kb
Host smart-283887c4-a3ab-4633-ad0e-f8259b4449cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044351282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1044351282
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1750229457
Short name T31
Test name
Test status
Simulation time 1890797461 ps
CPU time 6.97 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:11 PM PDT 24
Peak memory 217756 kb
Host smart-2f48a3dd-7c3a-47d5-bbe4-64084bbeddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750229457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1750229457
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.988615404
Short name T214
Test name
Test status
Simulation time 243995634 ps
CPU time 1.12 seconds
Started Jul 06 05:06:08 PM PDT 24
Finished Jul 06 05:06:09 PM PDT 24
Peak memory 217408 kb
Host smart-4100b616-bd84-451d-a049-1e688f6ab952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988615404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.988615404
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1932879186
Short name T323
Test name
Test status
Simulation time 80356933 ps
CPU time 0.77 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 199964 kb
Host smart-b6d4a28f-94be-42d9-bb46-72a7f14ec800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932879186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1932879186
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2739725618
Short name T185
Test name
Test status
Simulation time 755163161 ps
CPU time 3.81 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:08 PM PDT 24
Peak memory 200432 kb
Host smart-a0cee296-8f87-4488-bd42-dacd55042dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739725618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2739725618
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1120952411
Short name T168
Test name
Test status
Simulation time 160455717 ps
CPU time 1.16 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:06 PM PDT 24
Peak memory 200124 kb
Host smart-fcdc037c-d40b-40fb-b210-3ff372e4e825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120952411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1120952411
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1594186740
Short name T481
Test name
Test status
Simulation time 112411247 ps
CPU time 1.16 seconds
Started Jul 06 05:05:59 PM PDT 24
Finished Jul 06 05:06:00 PM PDT 24
Peak memory 200360 kb
Host smart-10e57c48-8ab7-4f5a-953f-1a0165039163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594186740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1594186740
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2268831253
Short name T290
Test name
Test status
Simulation time 9831241017 ps
CPU time 34.41 seconds
Started Jul 06 05:06:02 PM PDT 24
Finished Jul 06 05:06:37 PM PDT 24
Peak memory 216832 kb
Host smart-97734b07-9739-422f-be06-3fa25fe3b57d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268831253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2268831253
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2475992781
Short name T441
Test name
Test status
Simulation time 516365660 ps
CPU time 2.77 seconds
Started Jul 06 05:06:00 PM PDT 24
Finished Jul 06 05:06:03 PM PDT 24
Peak memory 200176 kb
Host smart-8afde241-31f5-465a-8b84-18b290ef9d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475992781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2475992781
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.281416371
Short name T339
Test name
Test status
Simulation time 169323779 ps
CPU time 1.14 seconds
Started Jul 06 05:06:00 PM PDT 24
Finished Jul 06 05:06:01 PM PDT 24
Peak memory 200120 kb
Host smart-933fd7c2-72c0-4489-8b25-a2abe07193d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281416371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.281416371
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3374032821
Short name T173
Test name
Test status
Simulation time 68902440 ps
CPU time 0.77 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 199968 kb
Host smart-edffb238-c9c2-4724-b085-01bd5b83c6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374032821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3374032821
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3418226025
Short name T410
Test name
Test status
Simulation time 1217614173 ps
CPU time 5.54 seconds
Started Jul 06 05:06:03 PM PDT 24
Finished Jul 06 05:06:09 PM PDT 24
Peak memory 217752 kb
Host smart-4a0fb848-3d22-4a4d-bfa7-63d624ffbe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418226025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3418226025
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2949707543
Short name T263
Test name
Test status
Simulation time 245282484 ps
CPU time 1.05 seconds
Started Jul 06 05:06:03 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 217508 kb
Host smart-f501e524-bc68-47c9-8af1-0211fa8b0c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949707543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2949707543
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.543607092
Short name T457
Test name
Test status
Simulation time 178147514 ps
CPU time 0.88 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 199972 kb
Host smart-a9beb53b-9875-4cee-aa67-3f91b22ff868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543607092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.543607092
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2066163153
Short name T250
Test name
Test status
Simulation time 842488334 ps
CPU time 4.13 seconds
Started Jul 06 05:06:03 PM PDT 24
Finished Jul 06 05:06:08 PM PDT 24
Peak memory 200352 kb
Host smart-5d872f6d-f66f-4135-a97a-e513aa63031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066163153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2066163153
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2832423662
Short name T338
Test name
Test status
Simulation time 117150284 ps
CPU time 1.15 seconds
Started Jul 06 05:06:02 PM PDT 24
Finished Jul 06 05:06:04 PM PDT 24
Peak memory 200152 kb
Host smart-168adc33-0014-4639-86c9-d921bff3cd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832423662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2832423662
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1800451302
Short name T452
Test name
Test status
Simulation time 230121484 ps
CPU time 1.49 seconds
Started Jul 06 05:06:01 PM PDT 24
Finished Jul 06 05:06:03 PM PDT 24
Peak memory 200280 kb
Host smart-74728ab9-851e-40be-8400-8519944a2a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800451302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1800451302
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3706408879
Short name T131
Test name
Test status
Simulation time 8167012641 ps
CPU time 31.25 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:35 PM PDT 24
Peak memory 208736 kb
Host smart-c8f84783-2ca8-4e55-a2d5-14ccc7013841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706408879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3706408879
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1759327551
Short name T177
Test name
Test status
Simulation time 140324405 ps
CPU time 1.8 seconds
Started Jul 06 05:06:03 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 200176 kb
Host smart-bb0ede91-f4d7-4150-b0a9-1c0a0d13b452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759327551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1759327551
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1113321034
Short name T199
Test name
Test status
Simulation time 156624425 ps
CPU time 1.23 seconds
Started Jul 06 05:06:02 PM PDT 24
Finished Jul 06 05:06:04 PM PDT 24
Peak memory 200296 kb
Host smart-43c2d5c9-c7e7-4fef-905c-bb7b0def6265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113321034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1113321034
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2551282009
Short name T141
Test name
Test status
Simulation time 69563910 ps
CPU time 0.77 seconds
Started Jul 06 05:06:07 PM PDT 24
Finished Jul 06 05:06:08 PM PDT 24
Peak memory 199920 kb
Host smart-2bcf17fc-6d94-48dc-a7bd-206779969b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551282009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2551282009
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2403664093
Short name T470
Test name
Test status
Simulation time 243959354 ps
CPU time 1.03 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:06 PM PDT 24
Peak memory 217504 kb
Host smart-816caf54-4e20-4cb1-b6f8-37850d984ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403664093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2403664093
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2485198659
Short name T492
Test name
Test status
Simulation time 216943445 ps
CPU time 0.95 seconds
Started Jul 06 05:06:02 PM PDT 24
Finished Jul 06 05:06:03 PM PDT 24
Peak memory 199972 kb
Host smart-b9cfd156-d8bf-4220-ad76-34f8cd4bea91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485198659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2485198659
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2102443320
Short name T361
Test name
Test status
Simulation time 848917373 ps
CPU time 4.34 seconds
Started Jul 06 05:06:02 PM PDT 24
Finished Jul 06 05:06:06 PM PDT 24
Peak memory 200392 kb
Host smart-690b6450-31fc-41ac-b716-6ab6c5a23613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102443320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2102443320
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1724409289
Short name T188
Test name
Test status
Simulation time 156862643 ps
CPU time 1.14 seconds
Started Jul 06 05:06:08 PM PDT 24
Finished Jul 06 05:06:10 PM PDT 24
Peak memory 200140 kb
Host smart-083ecb81-707b-4dfc-956d-180f232874f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724409289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1724409289
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2954678310
Short name T63
Test name
Test status
Simulation time 112115879 ps
CPU time 1.16 seconds
Started Jul 06 05:06:03 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 200360 kb
Host smart-f1ae010c-0226-47f2-9599-3b771e0b8af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954678310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2954678310
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2991093143
Short name T212
Test name
Test status
Simulation time 6031417203 ps
CPU time 22.25 seconds
Started Jul 06 05:06:09 PM PDT 24
Finished Jul 06 05:06:32 PM PDT 24
Peak memory 208728 kb
Host smart-7d4a598b-e5c9-4775-b778-f3760e655396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991093143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2991093143
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2010641275
Short name T251
Test name
Test status
Simulation time 411571783 ps
CPU time 2.1 seconds
Started Jul 06 05:06:05 PM PDT 24
Finished Jul 06 05:06:08 PM PDT 24
Peak memory 208320 kb
Host smart-9faea03d-6cf9-40c2-9e22-2f189d7efdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010641275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2010641275
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2403176334
Short name T374
Test name
Test status
Simulation time 227075511 ps
CPU time 1.41 seconds
Started Jul 06 05:06:02 PM PDT 24
Finished Jul 06 05:06:04 PM PDT 24
Peak memory 200072 kb
Host smart-63783924-c35a-47e4-a52d-9c8a289db763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403176334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2403176334
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1092548324
Short name T427
Test name
Test status
Simulation time 74996346 ps
CPU time 0.8 seconds
Started Jul 06 05:06:06 PM PDT 24
Finished Jul 06 05:06:08 PM PDT 24
Peak memory 199956 kb
Host smart-41630365-3e04-4ecb-aa18-999dde28f625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092548324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1092548324
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1684990560
Short name T526
Test name
Test status
Simulation time 1226925426 ps
CPU time 5.51 seconds
Started Jul 06 05:06:07 PM PDT 24
Finished Jul 06 05:06:13 PM PDT 24
Peak memory 217424 kb
Host smart-d4201c3c-ed17-4fc9-a484-3b4e7f78c23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684990560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1684990560
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3713215840
Short name T349
Test name
Test status
Simulation time 244946411 ps
CPU time 1.05 seconds
Started Jul 06 05:06:07 PM PDT 24
Finished Jul 06 05:06:09 PM PDT 24
Peak memory 217552 kb
Host smart-517365e0-444f-4259-b71e-6dbb56c74721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713215840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3713215840
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.456384357
Short name T435
Test name
Test status
Simulation time 115914185 ps
CPU time 0.8 seconds
Started Jul 06 05:06:05 PM PDT 24
Finished Jul 06 05:06:07 PM PDT 24
Peak memory 199884 kb
Host smart-29094b00-caf0-41c8-b89b-000c09f231ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456384357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.456384357
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2404927272
Short name T415
Test name
Test status
Simulation time 950122885 ps
CPU time 5 seconds
Started Jul 06 05:06:05 PM PDT 24
Finished Jul 06 05:06:11 PM PDT 24
Peak memory 200348 kb
Host smart-f57abcea-2461-4d37-af2f-1cc9f938e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404927272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2404927272
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1713384705
Short name T162
Test name
Test status
Simulation time 98398494 ps
CPU time 0.96 seconds
Started Jul 06 05:06:05 PM PDT 24
Finished Jul 06 05:06:06 PM PDT 24
Peak memory 200116 kb
Host smart-296461b9-9f49-4075-84d3-1573cceb968b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713384705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1713384705
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.4020687817
Short name T412
Test name
Test status
Simulation time 122905011 ps
CPU time 1.2 seconds
Started Jul 06 05:06:07 PM PDT 24
Finished Jul 06 05:06:08 PM PDT 24
Peak memory 200344 kb
Host smart-7def1437-054f-4991-b119-132bdea512da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020687817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.4020687817
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1525491484
Short name T276
Test name
Test status
Simulation time 897919464 ps
CPU time 3.61 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:08 PM PDT 24
Peak memory 200312 kb
Host smart-4d0552f0-df3e-4ff0-9cd3-cba8241dc1dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525491484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1525491484
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3510787438
Short name T322
Test name
Test status
Simulation time 122526650 ps
CPU time 1.63 seconds
Started Jul 06 05:06:07 PM PDT 24
Finished Jul 06 05:06:09 PM PDT 24
Peak memory 208312 kb
Host smart-11e1d320-7238-4bdd-ad97-8cff0621ae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510787438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3510787438
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1269116521
Short name T528
Test name
Test status
Simulation time 124647706 ps
CPU time 1.07 seconds
Started Jul 06 05:06:07 PM PDT 24
Finished Jul 06 05:06:09 PM PDT 24
Peak memory 200068 kb
Host smart-1dff0457-0db9-48ed-87ed-5a524a2e3c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269116521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1269116521
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.293974640
Short name T401
Test name
Test status
Simulation time 66330054 ps
CPU time 0.78 seconds
Started Jul 06 05:05:03 PM PDT 24
Finished Jul 06 05:05:04 PM PDT 24
Peak memory 199968 kb
Host smart-c7aa2e9e-2b19-4418-83ba-a64fad45916a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293974640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.293974640
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1026861608
Short name T283
Test name
Test status
Simulation time 1239700936 ps
CPU time 5.91 seconds
Started Jul 06 05:05:02 PM PDT 24
Finished Jul 06 05:05:09 PM PDT 24
Peak memory 217788 kb
Host smart-6b9ad2e1-08b5-4c2f-b3e8-bb29e3d7363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026861608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1026861608
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3237273146
Short name T320
Test name
Test status
Simulation time 244039148 ps
CPU time 1.08 seconds
Started Jul 06 05:05:01 PM PDT 24
Finished Jul 06 05:05:03 PM PDT 24
Peak memory 217504 kb
Host smart-e4822adf-f216-4083-ab79-c7ec236f12c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237273146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3237273146
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2338966184
Short name T464
Test name
Test status
Simulation time 215244337 ps
CPU time 0.92 seconds
Started Jul 06 05:04:58 PM PDT 24
Finished Jul 06 05:04:59 PM PDT 24
Peak memory 199884 kb
Host smart-2f1d57f1-e760-4edb-9776-bc6df34de999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338966184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2338966184
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3436745219
Short name T532
Test name
Test status
Simulation time 1421623661 ps
CPU time 5.44 seconds
Started Jul 06 05:04:58 PM PDT 24
Finished Jul 06 05:05:04 PM PDT 24
Peak memory 200436 kb
Host smart-9f5268d5-fe7f-4099-9196-b065edde8a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436745219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3436745219
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1379669178
Short name T72
Test name
Test status
Simulation time 8281962482 ps
CPU time 16.91 seconds
Started Jul 06 05:05:04 PM PDT 24
Finished Jul 06 05:05:21 PM PDT 24
Peak memory 217148 kb
Host smart-c65a84e5-0542-474d-993c-41e68df7d34b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379669178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1379669178
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1583424995
Short name T364
Test name
Test status
Simulation time 176083305 ps
CPU time 1.18 seconds
Started Jul 06 05:05:01 PM PDT 24
Finished Jul 06 05:05:03 PM PDT 24
Peak memory 200152 kb
Host smart-744e2724-4206-44aa-aec9-731435b23cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583424995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1583424995
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.4270237290
Short name T329
Test name
Test status
Simulation time 117034937 ps
CPU time 1.26 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:04:59 PM PDT 24
Peak memory 200320 kb
Host smart-1110535d-0b4c-41c0-b5af-1d43f8b97325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270237290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.4270237290
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3910920155
Short name T81
Test name
Test status
Simulation time 4918354173 ps
CPU time 19.05 seconds
Started Jul 06 05:05:05 PM PDT 24
Finished Jul 06 05:05:25 PM PDT 24
Peak memory 210452 kb
Host smart-ab4423e0-208b-4f28-b163-9b6c58164406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910920155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3910920155
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2778578750
Short name T88
Test name
Test status
Simulation time 380033908 ps
CPU time 2.31 seconds
Started Jul 06 05:05:00 PM PDT 24
Finished Jul 06 05:05:03 PM PDT 24
Peak memory 200160 kb
Host smart-5e580f4a-b21b-4f71-8f20-f6b4e7219102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778578750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2778578750
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2979129561
Short name T417
Test name
Test status
Simulation time 111488466 ps
CPU time 0.93 seconds
Started Jul 06 05:04:57 PM PDT 24
Finished Jul 06 05:04:58 PM PDT 24
Peak memory 200068 kb
Host smart-df3ef6be-bd6a-448f-a919-af465bd9dc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979129561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2979129561
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3802079602
Short name T155
Test name
Test status
Simulation time 77368555 ps
CPU time 0.78 seconds
Started Jul 06 05:06:11 PM PDT 24
Finished Jul 06 05:06:14 PM PDT 24
Peak memory 199864 kb
Host smart-864825c6-7b74-40d6-bc49-569cd5cedd8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802079602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3802079602
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.866645061
Short name T425
Test name
Test status
Simulation time 1902506115 ps
CPU time 8.19 seconds
Started Jul 06 05:06:13 PM PDT 24
Finished Jul 06 05:06:22 PM PDT 24
Peak memory 229884 kb
Host smart-4e2925e0-6839-43d9-abbf-01d63a610c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866645061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.866645061
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1643903459
Short name T496
Test name
Test status
Simulation time 244534139 ps
CPU time 1.19 seconds
Started Jul 06 05:06:09 PM PDT 24
Finished Jul 06 05:06:11 PM PDT 24
Peak memory 217552 kb
Host smart-5cbb712d-4c45-4de7-a5bf-23402839c742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643903459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1643903459
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2138019454
Short name T15
Test name
Test status
Simulation time 136750200 ps
CPU time 0.81 seconds
Started Jul 06 05:06:04 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 199964 kb
Host smart-26dd993b-c11a-4fa9-ba00-7f72b614bd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138019454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2138019454
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.394337617
Short name T397
Test name
Test status
Simulation time 1342621004 ps
CPU time 5.05 seconds
Started Jul 06 05:06:10 PM PDT 24
Finished Jul 06 05:06:16 PM PDT 24
Peak memory 200400 kb
Host smart-76125589-efcc-4101-8275-939f41112e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394337617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.394337617
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2766293648
Short name T237
Test name
Test status
Simulation time 106149399 ps
CPU time 1.07 seconds
Started Jul 06 05:06:11 PM PDT 24
Finished Jul 06 05:06:14 PM PDT 24
Peak memory 200140 kb
Host smart-41dd4f75-921a-4fdf-9f57-b4adc295da3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766293648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2766293648
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.167539466
Short name T238
Test name
Test status
Simulation time 119072177 ps
CPU time 1.29 seconds
Started Jul 06 05:06:08 PM PDT 24
Finished Jul 06 05:06:10 PM PDT 24
Peak memory 200368 kb
Host smart-adc90316-382e-4c75-9d46-fb2971d1512f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167539466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.167539466
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3404971603
Short name T469
Test name
Test status
Simulation time 12653166289 ps
CPU time 43.25 seconds
Started Jul 06 05:06:12 PM PDT 24
Finished Jul 06 05:06:57 PM PDT 24
Peak memory 208680 kb
Host smart-ef4d5675-64d9-423a-bc49-f028821f698b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404971603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3404971603
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.952624778
Short name T383
Test name
Test status
Simulation time 397734188 ps
CPU time 2.42 seconds
Started Jul 06 05:06:11 PM PDT 24
Finished Jul 06 05:06:13 PM PDT 24
Peak memory 200176 kb
Host smart-bd7c7f6c-6366-4437-9cd3-bc539d5c6052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952624778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.952624778
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1923905090
Short name T286
Test name
Test status
Simulation time 77024285 ps
CPU time 0.87 seconds
Started Jul 06 05:06:10 PM PDT 24
Finished Jul 06 05:06:11 PM PDT 24
Peak memory 200128 kb
Host smart-ae1df8a9-8ab0-401c-ab81-1319b1bcf095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923905090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1923905090
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2477823599
Short name T51
Test name
Test status
Simulation time 69063304 ps
CPU time 0.8 seconds
Started Jul 06 05:06:10 PM PDT 24
Finished Jul 06 05:06:11 PM PDT 24
Peak memory 199912 kb
Host smart-06baebfb-c5cc-42b0-bc88-16ce85d66b84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477823599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2477823599
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3759383376
Short name T29
Test name
Test status
Simulation time 2359628379 ps
CPU time 7.98 seconds
Started Jul 06 05:06:15 PM PDT 24
Finished Jul 06 05:06:24 PM PDT 24
Peak memory 221692 kb
Host smart-104ba884-0a76-412f-9a7c-e2a3278ab0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759383376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3759383376
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.875488566
Short name T489
Test name
Test status
Simulation time 245331122 ps
CPU time 1.04 seconds
Started Jul 06 05:06:14 PM PDT 24
Finished Jul 06 05:06:16 PM PDT 24
Peak memory 217520 kb
Host smart-0a79ef3c-9174-45bc-b152-a616ae9d511f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875488566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.875488566
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3729883124
Short name T511
Test name
Test status
Simulation time 210741513 ps
CPU time 0.97 seconds
Started Jul 06 05:06:12 PM PDT 24
Finished Jul 06 05:06:15 PM PDT 24
Peak memory 199964 kb
Host smart-42f35feb-86f4-457f-b01c-f3158ac3de46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729883124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3729883124
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2293358768
Short name T466
Test name
Test status
Simulation time 1499718764 ps
CPU time 6.28 seconds
Started Jul 06 05:06:12 PM PDT 24
Finished Jul 06 05:06:20 PM PDT 24
Peak memory 200380 kb
Host smart-aaa8f467-8da0-4397-9197-7895fbd41b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293358768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2293358768
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3096419274
Short name T149
Test name
Test status
Simulation time 108898499 ps
CPU time 1 seconds
Started Jul 06 05:06:10 PM PDT 24
Finished Jul 06 05:06:11 PM PDT 24
Peak memory 199988 kb
Host smart-e2d84493-8d03-48cc-97f5-7fba9043b052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096419274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3096419274
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3458824319
Short name T21
Test name
Test status
Simulation time 205916814 ps
CPU time 1.37 seconds
Started Jul 06 05:06:12 PM PDT 24
Finished Jul 06 05:06:15 PM PDT 24
Peak memory 200328 kb
Host smart-40397811-dfdc-4367-8a2b-83672ba7e00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458824319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3458824319
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.65130125
Short name T477
Test name
Test status
Simulation time 1172700569 ps
CPU time 5.45 seconds
Started Jul 06 05:06:12 PM PDT 24
Finished Jul 06 05:06:19 PM PDT 24
Peak memory 200400 kb
Host smart-76e20280-104f-4f93-83a8-94cdb58b7fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65130125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.65130125
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3189771286
Short name T371
Test name
Test status
Simulation time 313489971 ps
CPU time 2.08 seconds
Started Jul 06 05:06:17 PM PDT 24
Finished Jul 06 05:06:19 PM PDT 24
Peak memory 200152 kb
Host smart-b7deba27-dc3f-4353-ab3c-89b464300b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189771286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3189771286
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3870640915
Short name T84
Test name
Test status
Simulation time 160857762 ps
CPU time 1.2 seconds
Started Jul 06 05:06:11 PM PDT 24
Finished Jul 06 05:06:13 PM PDT 24
Peak memory 200320 kb
Host smart-74712f02-b259-485c-8d0d-e5df1ab1e7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870640915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3870640915
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3368863642
Short name T171
Test name
Test status
Simulation time 73694764 ps
CPU time 0.83 seconds
Started Jul 06 05:06:14 PM PDT 24
Finished Jul 06 05:06:15 PM PDT 24
Peak memory 199984 kb
Host smart-5f300966-5c15-493c-9891-0375c4a04617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368863642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3368863642
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.4258347867
Short name T378
Test name
Test status
Simulation time 2342763406 ps
CPU time 8 seconds
Started Jul 06 05:06:14 PM PDT 24
Finished Jul 06 05:06:23 PM PDT 24
Peak memory 217964 kb
Host smart-fa5e6db3-72ba-4f6d-ad0f-4d865f988f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258347867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.4258347867
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.567207171
Short name T278
Test name
Test status
Simulation time 243863811 ps
CPU time 1.06 seconds
Started Jul 06 05:06:11 PM PDT 24
Finished Jul 06 05:06:13 PM PDT 24
Peak memory 217552 kb
Host smart-443ee3aa-a3f7-4ddf-a4ce-07d7c14fbeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567207171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.567207171
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1768402158
Short name T256
Test name
Test status
Simulation time 94496738 ps
CPU time 0.77 seconds
Started Jul 06 05:06:13 PM PDT 24
Finished Jul 06 05:06:15 PM PDT 24
Peak memory 199924 kb
Host smart-9e458354-6435-4ad7-94a9-629a1b43c86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768402158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1768402158
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3686336147
Short name T111
Test name
Test status
Simulation time 1823340747 ps
CPU time 7.33 seconds
Started Jul 06 05:06:11 PM PDT 24
Finished Jul 06 05:06:18 PM PDT 24
Peak memory 200476 kb
Host smart-ad18ba64-8466-4a08-b4c8-9df77917fa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686336147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3686336147
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3258839886
Short name T136
Test name
Test status
Simulation time 145365045 ps
CPU time 1.21 seconds
Started Jul 06 05:06:13 PM PDT 24
Finished Jul 06 05:06:16 PM PDT 24
Peak memory 200152 kb
Host smart-70d48123-33bc-4c59-b37b-124ac3cae397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258839886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3258839886
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1030756665
Short name T332
Test name
Test status
Simulation time 207957580 ps
CPU time 1.5 seconds
Started Jul 06 05:06:10 PM PDT 24
Finished Jul 06 05:06:12 PM PDT 24
Peak memory 200284 kb
Host smart-217d49cf-60dc-46d5-8d78-c45189fe17f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030756665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1030756665
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2940571062
Short name T474
Test name
Test status
Simulation time 389319989 ps
CPU time 2.26 seconds
Started Jul 06 05:06:12 PM PDT 24
Finished Jul 06 05:06:16 PM PDT 24
Peak memory 208356 kb
Host smart-4648f8c7-111b-4f5c-96f9-90a813a91cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940571062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2940571062
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3599486245
Short name T277
Test name
Test status
Simulation time 295831390 ps
CPU time 1.68 seconds
Started Jul 06 05:06:10 PM PDT 24
Finished Jul 06 05:06:13 PM PDT 24
Peak memory 200240 kb
Host smart-2594f68a-55d8-4abf-b5e5-95ed42a27095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599486245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3599486245
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1066976266
Short name T164
Test name
Test status
Simulation time 76782415 ps
CPU time 0.9 seconds
Started Jul 06 05:06:16 PM PDT 24
Finished Jul 06 05:06:17 PM PDT 24
Peak memory 199952 kb
Host smart-c2d35e27-f09f-46da-aac5-c0df6fcf8946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066976266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1066976266
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2239242712
Short name T275
Test name
Test status
Simulation time 1230413869 ps
CPU time 5.5 seconds
Started Jul 06 05:07:42 PM PDT 24
Finished Jul 06 05:07:48 PM PDT 24
Peak memory 221728 kb
Host smart-df6b7bb7-7deb-4799-bba4-d0793d94797e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239242712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2239242712
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2945297545
Short name T200
Test name
Test status
Simulation time 243917168 ps
CPU time 1.09 seconds
Started Jul 06 05:06:18 PM PDT 24
Finished Jul 06 05:06:19 PM PDT 24
Peak memory 217456 kb
Host smart-207e09c2-d13a-4f59-a2c7-aca213569243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945297545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2945297545
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.540747288
Short name T159
Test name
Test status
Simulation time 207571870 ps
CPU time 0.91 seconds
Started Jul 06 05:06:16 PM PDT 24
Finished Jul 06 05:06:17 PM PDT 24
Peak memory 199912 kb
Host smart-693090d1-ee74-49e7-9298-147d51a7b4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540747288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.540747288
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2433656929
Short name T230
Test name
Test status
Simulation time 993204028 ps
CPU time 4.73 seconds
Started Jul 06 05:06:15 PM PDT 24
Finished Jul 06 05:06:20 PM PDT 24
Peak memory 200420 kb
Host smart-3e8d75fb-2106-4c73-85bb-263764e86989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433656929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2433656929
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3254934091
Short name T471
Test name
Test status
Simulation time 136985690 ps
CPU time 1.11 seconds
Started Jul 06 05:06:16 PM PDT 24
Finished Jul 06 05:06:17 PM PDT 24
Peak memory 200152 kb
Host smart-b5f6a48b-b16e-4cab-8340-b445cb3d9a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254934091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3254934091
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1933332955
Short name T538
Test name
Test status
Simulation time 199828677 ps
CPU time 1.36 seconds
Started Jul 06 05:06:18 PM PDT 24
Finished Jul 06 05:06:20 PM PDT 24
Peak memory 200368 kb
Host smart-1dcc87d3-4099-4a9a-b880-92c3d9a5af32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933332955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1933332955
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3257260394
Short name T330
Test name
Test status
Simulation time 5759032765 ps
CPU time 27.77 seconds
Started Jul 06 05:06:19 PM PDT 24
Finished Jul 06 05:06:47 PM PDT 24
Peak memory 208640 kb
Host smart-a14e044f-72f3-44a5-9d22-4b27f9a37e39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257260394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3257260394
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3558455441
Short name T483
Test name
Test status
Simulation time 360276865 ps
CPU time 2.23 seconds
Started Jul 06 05:06:16 PM PDT 24
Finished Jul 06 05:06:19 PM PDT 24
Peak memory 200140 kb
Host smart-306cad9d-2070-41c3-9428-53ff964b65dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558455441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3558455441
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1361484396
Short name T279
Test name
Test status
Simulation time 164856904 ps
CPU time 1.34 seconds
Started Jul 06 05:06:15 PM PDT 24
Finished Jul 06 05:06:16 PM PDT 24
Peak memory 200316 kb
Host smart-002dae73-020d-48db-8d44-4ab31d26dc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361484396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1361484396
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3757801134
Short name T139
Test name
Test status
Simulation time 70035022 ps
CPU time 0.82 seconds
Started Jul 06 05:06:16 PM PDT 24
Finished Jul 06 05:06:18 PM PDT 24
Peak memory 199880 kb
Host smart-6309a585-a94f-45ad-9343-e9c21222558c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757801134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3757801134
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3789919526
Short name T269
Test name
Test status
Simulation time 1887718302 ps
CPU time 7.71 seconds
Started Jul 06 05:06:16 PM PDT 24
Finished Jul 06 05:06:24 PM PDT 24
Peak memory 217780 kb
Host smart-5953c00e-22a7-4f06-83d3-4c9c396d67fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789919526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3789919526
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3178216592
Short name T463
Test name
Test status
Simulation time 243829807 ps
CPU time 1.15 seconds
Started Jul 06 05:06:17 PM PDT 24
Finished Jul 06 05:06:18 PM PDT 24
Peak memory 217536 kb
Host smart-10cb6de1-f07f-4774-b7c1-dde9880456d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178216592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3178216592
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.746788532
Short name T18
Test name
Test status
Simulation time 223697415 ps
CPU time 0.96 seconds
Started Jul 06 05:06:17 PM PDT 24
Finished Jul 06 05:06:18 PM PDT 24
Peak memory 199972 kb
Host smart-799d8c90-5c8a-4a7c-92c0-870107855d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746788532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.746788532
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.309414547
Short name T103
Test name
Test status
Simulation time 907669375 ps
CPU time 4.42 seconds
Started Jul 06 05:06:16 PM PDT 24
Finished Jul 06 05:06:21 PM PDT 24
Peak memory 200396 kb
Host smart-c5faa7ed-f946-49bb-8378-d710ef21f405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309414547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.309414547
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3876581756
Short name T293
Test name
Test status
Simulation time 151745150 ps
CPU time 1.15 seconds
Started Jul 06 05:06:18 PM PDT 24
Finished Jul 06 05:06:19 PM PDT 24
Peak memory 200064 kb
Host smart-863ebc47-1a45-4095-bcff-28c2f62e4259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876581756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3876581756
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3260384171
Short name T189
Test name
Test status
Simulation time 122444048 ps
CPU time 1.2 seconds
Started Jul 06 05:06:15 PM PDT 24
Finished Jul 06 05:06:17 PM PDT 24
Peak memory 200408 kb
Host smart-c06bb9a9-6e78-4261-a1fc-527b124a514f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260384171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3260384171
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3061462117
Short name T209
Test name
Test status
Simulation time 3067096206 ps
CPU time 10.77 seconds
Started Jul 06 05:06:16 PM PDT 24
Finished Jul 06 05:06:27 PM PDT 24
Peak memory 208608 kb
Host smart-4be1505c-4b7f-441a-919c-b35416866900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061462117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3061462117
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2391646241
Short name T233
Test name
Test status
Simulation time 372359371 ps
CPU time 2.03 seconds
Started Jul 06 05:06:15 PM PDT 24
Finished Jul 06 05:06:18 PM PDT 24
Peak memory 200136 kb
Host smart-84420271-0b7c-469f-8d88-ccdd1f5eb195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391646241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2391646241
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1028320028
Short name T242
Test name
Test status
Simulation time 209584097 ps
CPU time 1.26 seconds
Started Jul 06 05:06:16 PM PDT 24
Finished Jul 06 05:06:18 PM PDT 24
Peak memory 200072 kb
Host smart-1fd83b28-6322-49e1-a9ae-eeabdcbc7c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028320028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1028320028
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3627086338
Short name T193
Test name
Test status
Simulation time 78607366 ps
CPU time 0.84 seconds
Started Jul 06 05:06:20 PM PDT 24
Finished Jul 06 05:06:22 PM PDT 24
Peak memory 199924 kb
Host smart-9faa517c-5000-425c-a100-c0203f0126a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627086338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3627086338
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.366565757
Short name T318
Test name
Test status
Simulation time 1220297748 ps
CPU time 5.41 seconds
Started Jul 06 05:06:18 PM PDT 24
Finished Jul 06 05:06:24 PM PDT 24
Peak memory 221668 kb
Host smart-e120ef46-9c5c-49ce-a886-7af46be0a693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366565757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.366565757
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.490658537
Short name T312
Test name
Test status
Simulation time 243371026 ps
CPU time 1.18 seconds
Started Jul 06 05:06:21 PM PDT 24
Finished Jul 06 05:06:23 PM PDT 24
Peak memory 217512 kb
Host smart-900c0769-848c-40ab-b2ea-acafdcdb1fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490658537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.490658537
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1781977125
Short name T419
Test name
Test status
Simulation time 166033832 ps
CPU time 0.88 seconds
Started Jul 06 05:06:16 PM PDT 24
Finished Jul 06 05:06:18 PM PDT 24
Peak memory 199920 kb
Host smart-2598e82a-423a-436b-98bc-b6d84b1c2878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781977125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1781977125
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.929001692
Short name T24
Test name
Test status
Simulation time 1341718006 ps
CPU time 5.51 seconds
Started Jul 06 05:06:18 PM PDT 24
Finished Jul 06 05:06:24 PM PDT 24
Peak memory 200404 kb
Host smart-e905ff4b-592d-4ec4-a61f-49410226da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929001692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.929001692
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3559690603
Short name T335
Test name
Test status
Simulation time 165027145 ps
CPU time 1.26 seconds
Started Jul 06 05:06:21 PM PDT 24
Finished Jul 06 05:06:23 PM PDT 24
Peak memory 200124 kb
Host smart-669ac10d-8bd6-435e-8bf0-e8e53b226f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559690603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3559690603
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.413490088
Short name T450
Test name
Test status
Simulation time 109240947 ps
CPU time 1.22 seconds
Started Jul 06 05:06:16 PM PDT 24
Finished Jul 06 05:06:17 PM PDT 24
Peak memory 200396 kb
Host smart-9f6973ac-b78a-4d3c-84ed-37a9fa5eec0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413490088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.413490088
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.173100730
Short name T243
Test name
Test status
Simulation time 1046115028 ps
CPU time 4.93 seconds
Started Jul 06 05:06:21 PM PDT 24
Finished Jul 06 05:06:26 PM PDT 24
Peak memory 208620 kb
Host smart-149cd4dd-0310-45dd-a0aa-0c79d4b225b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173100730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.173100730
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3843643004
Short name T166
Test name
Test status
Simulation time 291024517 ps
CPU time 2.06 seconds
Started Jul 06 05:06:15 PM PDT 24
Finished Jul 06 05:06:18 PM PDT 24
Peak memory 208360 kb
Host smart-cdce8340-c15a-44e4-bb9a-73bc3d207348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843643004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3843643004
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.844091806
Short name T400
Test name
Test status
Simulation time 141650538 ps
CPU time 1.05 seconds
Started Jul 06 05:06:15 PM PDT 24
Finished Jul 06 05:06:17 PM PDT 24
Peak memory 200100 kb
Host smart-9d633420-6c8b-408d-a6f2-81fef2ec1fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844091806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.844091806
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3452479134
Short name T249
Test name
Test status
Simulation time 69207844 ps
CPU time 0.83 seconds
Started Jul 06 05:06:21 PM PDT 24
Finished Jul 06 05:06:22 PM PDT 24
Peak memory 199960 kb
Host smart-6f396342-7aa7-4de5-8203-0f9fa9c5578b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452479134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3452479134
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1037244042
Short name T48
Test name
Test status
Simulation time 1223702758 ps
CPU time 5.65 seconds
Started Jul 06 05:06:21 PM PDT 24
Finished Jul 06 05:06:27 PM PDT 24
Peak memory 217652 kb
Host smart-47d9fb0a-8c74-4345-8824-038a19026837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037244042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1037244042
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3494945268
Short name T156
Test name
Test status
Simulation time 244911482 ps
CPU time 1.15 seconds
Started Jul 06 05:06:23 PM PDT 24
Finished Jul 06 05:06:25 PM PDT 24
Peak memory 217448 kb
Host smart-c3e0004f-f01d-4aa0-b03b-d446e45ec65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494945268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3494945268
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.139603988
Short name T270
Test name
Test status
Simulation time 244493029 ps
CPU time 1 seconds
Started Jul 06 05:06:25 PM PDT 24
Finished Jul 06 05:06:26 PM PDT 24
Peak memory 199972 kb
Host smart-86536692-af6e-4f6b-be5b-0b22acb405da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139603988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.139603988
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3378841815
Short name T485
Test name
Test status
Simulation time 1192334025 ps
CPU time 5.2 seconds
Started Jul 06 05:06:20 PM PDT 24
Finished Jul 06 05:06:26 PM PDT 24
Peak memory 200312 kb
Host smart-18899a36-3490-4ee2-bc76-c15812cc97cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378841815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3378841815
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.4122133672
Short name T369
Test name
Test status
Simulation time 142409503 ps
CPU time 1.09 seconds
Started Jul 06 05:06:25 PM PDT 24
Finished Jul 06 05:06:26 PM PDT 24
Peak memory 200108 kb
Host smart-9e1cca6c-2036-4334-8a46-f650fd710d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122133672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.4122133672
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1070037453
Short name T229
Test name
Test status
Simulation time 192111708 ps
CPU time 1.4 seconds
Started Jul 06 05:06:20 PM PDT 24
Finished Jul 06 05:06:21 PM PDT 24
Peak memory 200296 kb
Host smart-533330cd-9e97-426c-905f-0cc85a86d26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070037453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1070037453
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3258245214
Short name T403
Test name
Test status
Simulation time 8399772170 ps
CPU time 32.73 seconds
Started Jul 06 05:06:23 PM PDT 24
Finished Jul 06 05:06:56 PM PDT 24
Peak memory 200464 kb
Host smart-9a5cc4f6-150b-4a01-8d59-7ad9edd65a59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258245214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3258245214
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.4080034456
Short name T459
Test name
Test status
Simulation time 131949766 ps
CPU time 1.71 seconds
Started Jul 06 05:06:20 PM PDT 24
Finished Jul 06 05:06:22 PM PDT 24
Peak memory 208360 kb
Host smart-24086581-77a7-4cd1-9212-0da88b7fa8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080034456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.4080034456
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.675861645
Short name T223
Test name
Test status
Simulation time 122449221 ps
CPU time 1.02 seconds
Started Jul 06 05:06:19 PM PDT 24
Finished Jul 06 05:06:20 PM PDT 24
Peak memory 200140 kb
Host smart-b4b04ea2-362d-402c-923d-a57ad9df8e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675861645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.675861645
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1763960434
Short name T150
Test name
Test status
Simulation time 65606374 ps
CPU time 0.73 seconds
Started Jul 06 05:06:30 PM PDT 24
Finished Jul 06 05:06:31 PM PDT 24
Peak memory 199964 kb
Host smart-0a0f94d4-04fe-4b73-a675-82f07942b6c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763960434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1763960434
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2372485489
Short name T508
Test name
Test status
Simulation time 247621618 ps
CPU time 1.06 seconds
Started Jul 06 05:06:25 PM PDT 24
Finished Jul 06 05:06:26 PM PDT 24
Peak memory 217512 kb
Host smart-8e207c75-9ae0-4234-abbb-a0b9842ccd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372485489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2372485489
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1101494375
Short name T292
Test name
Test status
Simulation time 154567382 ps
CPU time 0.93 seconds
Started Jul 06 05:06:24 PM PDT 24
Finished Jul 06 05:06:25 PM PDT 24
Peak memory 199660 kb
Host smart-74136c18-e0a7-4f99-b442-b6cf985377ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101494375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1101494375
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.4018909539
Short name T328
Test name
Test status
Simulation time 809319353 ps
CPU time 4.02 seconds
Started Jul 06 05:06:22 PM PDT 24
Finished Jul 06 05:06:26 PM PDT 24
Peak memory 200432 kb
Host smart-c25a9228-44eb-402e-80ba-38babe5cc05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018909539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4018909539
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.776156935
Short name T348
Test name
Test status
Simulation time 101202443 ps
CPU time 1.05 seconds
Started Jul 06 05:06:24 PM PDT 24
Finished Jul 06 05:06:25 PM PDT 24
Peak memory 199916 kb
Host smart-d92e5e0c-a57d-4884-8221-98f11a99165e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776156935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.776156935
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2482155308
Short name T518
Test name
Test status
Simulation time 116236122 ps
CPU time 1.19 seconds
Started Jul 06 05:06:30 PM PDT 24
Finished Jul 06 05:06:32 PM PDT 24
Peak memory 200372 kb
Host smart-f55744ab-9d23-4f0b-97fd-9feebc333a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482155308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2482155308
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.355878637
Short name T506
Test name
Test status
Simulation time 6756790591 ps
CPU time 30.68 seconds
Started Jul 06 05:06:23 PM PDT 24
Finished Jul 06 05:06:54 PM PDT 24
Peak memory 200392 kb
Host smart-7d716427-8ca6-4763-9812-889e1a174530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355878637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.355878637
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3803255589
Short name T405
Test name
Test status
Simulation time 122401891 ps
CPU time 1.66 seconds
Started Jul 06 05:06:21 PM PDT 24
Finished Jul 06 05:06:23 PM PDT 24
Peak memory 208332 kb
Host smart-9edaf05a-2080-4054-a46c-82c6516694a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803255589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3803255589
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2974885538
Short name T522
Test name
Test status
Simulation time 91784882 ps
CPU time 0.99 seconds
Started Jul 06 05:06:25 PM PDT 24
Finished Jul 06 05:06:26 PM PDT 24
Peak memory 200112 kb
Host smart-59fa125a-fb45-4014-8eeb-b428660c51b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974885538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2974885538
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2258219286
Short name T394
Test name
Test status
Simulation time 77818938 ps
CPU time 0.8 seconds
Started Jul 06 05:06:26 PM PDT 24
Finished Jul 06 05:06:27 PM PDT 24
Peak memory 199932 kb
Host smart-6a06918b-50e7-49cf-83e6-c0a2261c9628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258219286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2258219286
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2734441085
Short name T194
Test name
Test status
Simulation time 2156926522 ps
CPU time 8.01 seconds
Started Jul 06 05:06:28 PM PDT 24
Finished Jul 06 05:06:36 PM PDT 24
Peak memory 217648 kb
Host smart-3a5670ca-2b61-40ce-88b3-90e4370ffa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734441085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2734441085
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1232018692
Short name T236
Test name
Test status
Simulation time 244662625 ps
CPU time 1.07 seconds
Started Jul 06 05:06:26 PM PDT 24
Finished Jul 06 05:06:28 PM PDT 24
Peak memory 217528 kb
Host smart-7ece4a98-c185-4351-85da-aca967d451e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232018692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1232018692
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2726446272
Short name T531
Test name
Test status
Simulation time 228777602 ps
CPU time 0.94 seconds
Started Jul 06 05:06:25 PM PDT 24
Finished Jul 06 05:06:26 PM PDT 24
Peak memory 199948 kb
Host smart-b69f05d5-6905-473f-8857-d34ec672d63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726446272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2726446272
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.294097678
Short name T499
Test name
Test status
Simulation time 890541091 ps
CPU time 5.23 seconds
Started Jul 06 05:06:23 PM PDT 24
Finished Jul 06 05:06:28 PM PDT 24
Peak memory 200340 kb
Host smart-5dffbce6-27ae-4a24-9232-34ef5a939918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294097678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.294097678
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2445916078
Short name T216
Test name
Test status
Simulation time 182026885 ps
CPU time 1.21 seconds
Started Jul 06 05:06:23 PM PDT 24
Finished Jul 06 05:06:24 PM PDT 24
Peak memory 200064 kb
Host smart-049c6f56-689e-47c0-ac27-171418bdf09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445916078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2445916078
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.832601913
Short name T424
Test name
Test status
Simulation time 108771984 ps
CPU time 1.21 seconds
Started Jul 06 05:06:23 PM PDT 24
Finished Jul 06 05:06:24 PM PDT 24
Peak memory 200380 kb
Host smart-221cd361-a94f-48ec-8082-078dc2db8c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832601913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.832601913
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.4276248802
Short name T448
Test name
Test status
Simulation time 947869599 ps
CPU time 4.65 seconds
Started Jul 06 05:06:29 PM PDT 24
Finished Jul 06 05:06:34 PM PDT 24
Peak memory 200420 kb
Host smart-94449399-ba5b-4839-a8cd-7aee2eda1739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276248802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.4276248802
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2560958470
Short name T255
Test name
Test status
Simulation time 265401638 ps
CPU time 1.88 seconds
Started Jul 06 05:06:20 PM PDT 24
Finished Jul 06 05:06:23 PM PDT 24
Peak memory 200172 kb
Host smart-18c47b04-9b62-45fd-be9f-18c513b4a3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560958470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2560958470
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2484101176
Short name T460
Test name
Test status
Simulation time 150914129 ps
CPU time 1.2 seconds
Started Jul 06 05:06:21 PM PDT 24
Finished Jul 06 05:06:23 PM PDT 24
Peak memory 200152 kb
Host smart-b8550f95-caaa-4ab2-8215-fe35cbcadac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484101176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2484101176
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.4188831652
Short name T205
Test name
Test status
Simulation time 54980724 ps
CPU time 0.75 seconds
Started Jul 06 05:06:26 PM PDT 24
Finished Jul 06 05:06:28 PM PDT 24
Peak memory 199928 kb
Host smart-3ecbfdd6-50be-4f0a-b08f-81341c09ea02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188831652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4188831652
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2036307099
Short name T36
Test name
Test status
Simulation time 2367219322 ps
CPU time 9.97 seconds
Started Jul 06 05:06:27 PM PDT 24
Finished Jul 06 05:06:37 PM PDT 24
Peak memory 221712 kb
Host smart-e46e844e-60c6-486b-93bd-b4b36e2d9ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036307099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2036307099
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.395166492
Short name T533
Test name
Test status
Simulation time 244775577 ps
CPU time 1.01 seconds
Started Jul 06 05:06:24 PM PDT 24
Finished Jul 06 05:06:25 PM PDT 24
Peak memory 217432 kb
Host smart-7e219808-b821-47f9-8bcb-f26c2a7a5196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395166492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.395166492
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2543612482
Short name T381
Test name
Test status
Simulation time 125900237 ps
CPU time 0.9 seconds
Started Jul 06 05:06:26 PM PDT 24
Finished Jul 06 05:06:27 PM PDT 24
Peak memory 199972 kb
Host smart-d3f19a7b-3da2-454a-b10b-dc76d833c87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543612482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2543612482
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2975319521
Short name T475
Test name
Test status
Simulation time 1095880421 ps
CPU time 4.65 seconds
Started Jul 06 05:06:25 PM PDT 24
Finished Jul 06 05:06:30 PM PDT 24
Peak memory 200408 kb
Host smart-679fd56c-2955-4f6e-b37b-e184bbb2795c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975319521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2975319521
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.625120207
Short name T411
Test name
Test status
Simulation time 98957184 ps
CPU time 0.98 seconds
Started Jul 06 05:06:26 PM PDT 24
Finished Jul 06 05:06:27 PM PDT 24
Peak memory 200148 kb
Host smart-21c709db-e3f3-4e87-8fb2-e693f86354ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625120207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.625120207
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.134465853
Short name T334
Test name
Test status
Simulation time 121539712 ps
CPU time 1.24 seconds
Started Jul 06 05:06:25 PM PDT 24
Finished Jul 06 05:06:26 PM PDT 24
Peak memory 200328 kb
Host smart-4db781bc-2d40-4d02-a568-8387b8b0ac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134465853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.134465853
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2355510378
Short name T85
Test name
Test status
Simulation time 1930799497 ps
CPU time 8.77 seconds
Started Jul 06 05:06:27 PM PDT 24
Finished Jul 06 05:06:36 PM PDT 24
Peak memory 200468 kb
Host smart-23b58cc5-daca-4990-987b-e988cd371590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355510378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2355510378
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.4201237908
Short name T449
Test name
Test status
Simulation time 358868796 ps
CPU time 2.13 seconds
Started Jul 06 05:06:26 PM PDT 24
Finished Jul 06 05:06:29 PM PDT 24
Peak memory 200100 kb
Host smart-7ce16856-2956-49dd-9b3c-44d06cf9d602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201237908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.4201237908
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3890828189
Short name T310
Test name
Test status
Simulation time 86948716 ps
CPU time 0.84 seconds
Started Jul 06 05:06:34 PM PDT 24
Finished Jul 06 05:06:36 PM PDT 24
Peak memory 200128 kb
Host smart-9f38076a-a21c-4189-a9f3-926320bb8b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890828189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3890828189
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.4037206000
Short name T473
Test name
Test status
Simulation time 66107319 ps
CPU time 0.79 seconds
Started Jul 06 05:05:03 PM PDT 24
Finished Jul 06 05:05:05 PM PDT 24
Peak memory 199864 kb
Host smart-23d2e532-fa15-45c2-8340-d4d622cb90cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037206000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4037206000
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.904355967
Short name T295
Test name
Test status
Simulation time 245822160 ps
CPU time 1.09 seconds
Started Jul 06 05:05:03 PM PDT 24
Finished Jul 06 05:05:04 PM PDT 24
Peak memory 217532 kb
Host smart-467b3d2a-0edf-4a85-8233-859923994dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904355967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.904355967
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3446368422
Short name T299
Test name
Test status
Simulation time 142955666 ps
CPU time 0.85 seconds
Started Jul 06 05:05:02 PM PDT 24
Finished Jul 06 05:05:04 PM PDT 24
Peak memory 199852 kb
Host smart-f7ae54e4-20ea-4890-8c6f-74984b12c4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446368422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3446368422
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.65306428
Short name T391
Test name
Test status
Simulation time 662586954 ps
CPU time 3.99 seconds
Started Jul 06 05:05:06 PM PDT 24
Finished Jul 06 05:05:10 PM PDT 24
Peak memory 200456 kb
Host smart-daec4c12-e64c-4c43-91ed-6d4a2278ae7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65306428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.65306428
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3177281965
Short name T224
Test name
Test status
Simulation time 103528045 ps
CPU time 1.1 seconds
Started Jul 06 05:05:02 PM PDT 24
Finished Jul 06 05:05:04 PM PDT 24
Peak memory 200112 kb
Host smart-1c94f64f-5ff2-47fb-8668-67a1f69ac52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177281965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3177281965
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1259746889
Short name T404
Test name
Test status
Simulation time 198993742 ps
CPU time 1.42 seconds
Started Jul 06 05:05:01 PM PDT 24
Finished Jul 06 05:05:03 PM PDT 24
Peak memory 200280 kb
Host smart-00129ff8-f400-4bc6-a193-77ad1ae51dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259746889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1259746889
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.789689740
Short name T333
Test name
Test status
Simulation time 3246974172 ps
CPU time 14.55 seconds
Started Jul 06 05:05:03 PM PDT 24
Finished Jul 06 05:05:18 PM PDT 24
Peak memory 208588 kb
Host smart-dfb36613-c571-496b-88d8-9039cab0461d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789689740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.789689740
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.538333280
Short name T480
Test name
Test status
Simulation time 366995519 ps
CPU time 2.18 seconds
Started Jul 06 05:05:04 PM PDT 24
Finished Jul 06 05:05:06 PM PDT 24
Peak memory 200080 kb
Host smart-20771174-e64c-4adb-a94e-4a286a52f002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538333280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.538333280
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3104531393
Short name T244
Test name
Test status
Simulation time 111038353 ps
CPU time 0.93 seconds
Started Jul 06 05:05:06 PM PDT 24
Finished Jul 06 05:05:07 PM PDT 24
Peak memory 200024 kb
Host smart-21af0df4-e754-449b-9195-91570a3105a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104531393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3104531393
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3877239003
Short name T468
Test name
Test status
Simulation time 66279411 ps
CPU time 0.75 seconds
Started Jul 06 05:05:09 PM PDT 24
Finished Jul 06 05:05:10 PM PDT 24
Peak memory 199856 kb
Host smart-01ab12ae-18c3-40d9-a796-7ea6c3566517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877239003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3877239003
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1181655946
Short name T319
Test name
Test status
Simulation time 1219909022 ps
CPU time 5.73 seconds
Started Jul 06 05:05:04 PM PDT 24
Finished Jul 06 05:05:10 PM PDT 24
Peak memory 229944 kb
Host smart-6d0a5bf4-a83c-42ea-adf1-54615ef668c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181655946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1181655946
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3958369359
Short name T274
Test name
Test status
Simulation time 244738137 ps
CPU time 1.12 seconds
Started Jul 06 05:05:06 PM PDT 24
Finished Jul 06 05:05:07 PM PDT 24
Peak memory 217404 kb
Host smart-fb071b4c-1253-496a-8f52-a82a99812f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958369359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3958369359
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2438526453
Short name T380
Test name
Test status
Simulation time 189488013 ps
CPU time 1 seconds
Started Jul 06 05:05:06 PM PDT 24
Finished Jul 06 05:05:07 PM PDT 24
Peak memory 199832 kb
Host smart-8c875594-bd8a-446c-831f-aa637ca9b16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438526453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2438526453
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2245261004
Short name T326
Test name
Test status
Simulation time 2141418757 ps
CPU time 7.74 seconds
Started Jul 06 05:05:04 PM PDT 24
Finished Jul 06 05:05:12 PM PDT 24
Peak memory 200348 kb
Host smart-ac3cf324-0774-411f-bd03-265379f43ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245261004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2245261004
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.125755395
Short name T515
Test name
Test status
Simulation time 171788250 ps
CPU time 1.17 seconds
Started Jul 06 05:05:04 PM PDT 24
Finished Jul 06 05:05:05 PM PDT 24
Peak memory 200044 kb
Host smart-ebddeb2a-f637-43de-99bd-f588850311c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125755395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.125755395
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1425262065
Short name T365
Test name
Test status
Simulation time 194277218 ps
CPU time 1.49 seconds
Started Jul 06 05:05:03 PM PDT 24
Finished Jul 06 05:05:05 PM PDT 24
Peak memory 200284 kb
Host smart-0a5e5ddf-e9ed-418d-9a09-d08b6c1652d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425262065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1425262065
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.501161029
Short name T106
Test name
Test status
Simulation time 11045529226 ps
CPU time 36 seconds
Started Jul 06 05:05:10 PM PDT 24
Finished Jul 06 05:05:46 PM PDT 24
Peak memory 208676 kb
Host smart-e395d10a-debb-4086-a05d-ad335685b7b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501161029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.501161029
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2596493810
Short name T192
Test name
Test status
Simulation time 142290815 ps
CPU time 1.68 seconds
Started Jul 06 05:05:05 PM PDT 24
Finished Jul 06 05:05:08 PM PDT 24
Peak memory 200160 kb
Host smart-adc8bdc0-53b2-4b2b-bc0a-ac52815e986d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596493810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2596493810
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1936610381
Short name T157
Test name
Test status
Simulation time 231872220 ps
CPU time 1.54 seconds
Started Jul 06 05:05:01 PM PDT 24
Finished Jul 06 05:05:03 PM PDT 24
Peak memory 200356 kb
Host smart-b38ae0f7-f273-4f93-8572-82c537554b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936610381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1936610381
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3252879254
Short name T363
Test name
Test status
Simulation time 60582683 ps
CPU time 0.74 seconds
Started Jul 06 05:05:09 PM PDT 24
Finished Jul 06 05:05:10 PM PDT 24
Peak memory 199864 kb
Host smart-06dcd50f-0af2-46fa-af77-b2e17272499c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252879254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3252879254
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2349929793
Short name T43
Test name
Test status
Simulation time 1221328279 ps
CPU time 5.53 seconds
Started Jul 06 05:05:10 PM PDT 24
Finished Jul 06 05:05:16 PM PDT 24
Peak memory 217776 kb
Host smart-960092bb-8dd8-4890-836a-0661cc05035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349929793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2349929793
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1450084650
Short name T76
Test name
Test status
Simulation time 247192478 ps
CPU time 1.07 seconds
Started Jul 06 05:05:10 PM PDT 24
Finished Jul 06 05:05:12 PM PDT 24
Peak memory 218304 kb
Host smart-8a90a849-1661-4c5c-a28f-afd408cb8886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450084650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1450084650
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.966064320
Short name T368
Test name
Test status
Simulation time 79410694 ps
CPU time 0.78 seconds
Started Jul 06 05:05:12 PM PDT 24
Finished Jul 06 05:05:13 PM PDT 24
Peak memory 199876 kb
Host smart-a2d3acb1-2fed-46e9-aea8-6f611a76386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966064320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.966064320
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.383128854
Short name T507
Test name
Test status
Simulation time 775529845 ps
CPU time 3.92 seconds
Started Jul 06 05:05:09 PM PDT 24
Finished Jul 06 05:05:13 PM PDT 24
Peak memory 200396 kb
Host smart-cb8d5ee9-2b48-42cd-8015-3455016a4580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383128854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.383128854
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3705793415
Short name T487
Test name
Test status
Simulation time 153705625 ps
CPU time 1.16 seconds
Started Jul 06 05:05:08 PM PDT 24
Finished Jul 06 05:05:09 PM PDT 24
Peak memory 200076 kb
Host smart-09ed9e92-54e7-4a3a-902f-963554a9ed97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705793415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3705793415
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3366941254
Short name T541
Test name
Test status
Simulation time 107980847 ps
CPU time 1.2 seconds
Started Jul 06 05:05:09 PM PDT 24
Finished Jul 06 05:05:10 PM PDT 24
Peak memory 200356 kb
Host smart-faf56f76-e716-49cd-a54b-8426ecbc98fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366941254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3366941254
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2608271393
Short name T83
Test name
Test status
Simulation time 314657470 ps
CPU time 1.78 seconds
Started Jul 06 05:05:09 PM PDT 24
Finished Jul 06 05:05:11 PM PDT 24
Peak memory 200332 kb
Host smart-bf34ef6d-03ad-492a-a675-cde6b57bc81c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608271393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2608271393
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.4019792293
Short name T305
Test name
Test status
Simulation time 116403679 ps
CPU time 1.55 seconds
Started Jul 06 05:05:08 PM PDT 24
Finished Jul 06 05:05:10 PM PDT 24
Peak memory 200096 kb
Host smart-94f408d0-f021-48fa-9d51-0a2ffebd5eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019792293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.4019792293
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2143501343
Short name T208
Test name
Test status
Simulation time 163399824 ps
CPU time 1.26 seconds
Started Jul 06 05:05:11 PM PDT 24
Finished Jul 06 05:05:12 PM PDT 24
Peak memory 200080 kb
Host smart-bc9bc773-5ac5-4b47-99bf-ea66406d1d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143501343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2143501343
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.43936387
Short name T245
Test name
Test status
Simulation time 75321755 ps
CPU time 0.89 seconds
Started Jul 06 05:05:10 PM PDT 24
Finished Jul 06 05:05:11 PM PDT 24
Peak memory 199856 kb
Host smart-7527d8e3-fd9b-4c11-9400-32a5ecb3f8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43936387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.43936387
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.4150008016
Short name T32
Test name
Test status
Simulation time 1224369226 ps
CPU time 5.4 seconds
Started Jul 06 05:05:09 PM PDT 24
Finished Jul 06 05:05:15 PM PDT 24
Peak memory 217356 kb
Host smart-0eb2bea3-8093-47d6-94ac-a94a889a5f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150008016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4150008016
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3645314584
Short name T74
Test name
Test status
Simulation time 244069752 ps
CPU time 1.09 seconds
Started Jul 06 05:05:10 PM PDT 24
Finished Jul 06 05:05:11 PM PDT 24
Peak memory 217532 kb
Host smart-f2406b24-d08f-4501-a575-e5359ac40cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645314584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3645314584
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.180757727
Short name T488
Test name
Test status
Simulation time 212535134 ps
CPU time 0.95 seconds
Started Jul 06 05:05:15 PM PDT 24
Finished Jul 06 05:05:16 PM PDT 24
Peak memory 199876 kb
Host smart-e80a357b-34cf-47ce-8ab8-3eb655a3a224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180757727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.180757727
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1955359170
Short name T314
Test name
Test status
Simulation time 1107076993 ps
CPU time 4.68 seconds
Started Jul 06 05:05:09 PM PDT 24
Finished Jul 06 05:05:14 PM PDT 24
Peak memory 200476 kb
Host smart-1cb532e2-8c14-4cfd-ad9b-3e015a41dcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955359170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1955359170
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4230807848
Short name T432
Test name
Test status
Simulation time 150995343 ps
CPU time 1.1 seconds
Started Jul 06 05:05:09 PM PDT 24
Finished Jul 06 05:05:10 PM PDT 24
Peak memory 200140 kb
Host smart-f8f3c0a2-e4f0-4fc8-b844-81f52cbcc98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230807848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4230807848
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3701829884
Short name T253
Test name
Test status
Simulation time 196191436 ps
CPU time 1.32 seconds
Started Jul 06 05:05:08 PM PDT 24
Finished Jul 06 05:05:09 PM PDT 24
Peak memory 200364 kb
Host smart-f744fee2-16bc-4bc2-8fbc-918af06b6849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701829884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3701829884
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2924276331
Short name T497
Test name
Test status
Simulation time 399066933 ps
CPU time 2.03 seconds
Started Jul 06 05:05:10 PM PDT 24
Finished Jul 06 05:05:12 PM PDT 24
Peak memory 200316 kb
Host smart-65d861d6-2833-436f-b0af-ac680885cb3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924276331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2924276331
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.991750377
Short name T505
Test name
Test status
Simulation time 506153117 ps
CPU time 2.75 seconds
Started Jul 06 05:05:10 PM PDT 24
Finished Jul 06 05:05:13 PM PDT 24
Peak memory 200096 kb
Host smart-def7d395-33fe-41af-b660-b820f37a3a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991750377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.991750377
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2390436523
Short name T221
Test name
Test status
Simulation time 81997684 ps
CPU time 0.92 seconds
Started Jul 06 05:05:10 PM PDT 24
Finished Jul 06 05:05:11 PM PDT 24
Peak memory 199992 kb
Host smart-292b552b-dc01-47ac-9364-70a4857713d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390436523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2390436523
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1945978434
Short name T396
Test name
Test status
Simulation time 69396637 ps
CPU time 0.76 seconds
Started Jul 06 05:05:16 PM PDT 24
Finished Jul 06 05:05:17 PM PDT 24
Peak memory 199880 kb
Host smart-6c658e5a-dee1-47c0-be1e-7b13b7731ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945978434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1945978434
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1540675754
Short name T267
Test name
Test status
Simulation time 1883540021 ps
CPU time 7.51 seconds
Started Jul 06 05:05:18 PM PDT 24
Finished Jul 06 05:05:26 PM PDT 24
Peak memory 221308 kb
Host smart-fef9de50-abaf-466c-aa0d-c13833f1d918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540675754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1540675754
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2421762174
Short name T402
Test name
Test status
Simulation time 243703251 ps
CPU time 1.17 seconds
Started Jul 06 05:05:13 PM PDT 24
Finished Jul 06 05:05:15 PM PDT 24
Peak memory 217416 kb
Host smart-a26f6c6b-647e-4e20-9d1a-cbb6725726a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421762174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2421762174
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1248527129
Short name T148
Test name
Test status
Simulation time 150154635 ps
CPU time 0.84 seconds
Started Jul 06 05:05:08 PM PDT 24
Finished Jul 06 05:05:09 PM PDT 24
Peak memory 199972 kb
Host smart-9405761c-a5bd-4fb5-9ebf-1e64b2ba968e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248527129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1248527129
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3055504612
Short name T191
Test name
Test status
Simulation time 181278574 ps
CPU time 1.22 seconds
Started Jul 06 05:05:15 PM PDT 24
Finished Jul 06 05:05:17 PM PDT 24
Peak memory 200068 kb
Host smart-05dfe1c3-ba27-4319-8353-f2eea7d47591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055504612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3055504612
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4147826351
Short name T49
Test name
Test status
Simulation time 243333051 ps
CPU time 1.48 seconds
Started Jul 06 05:05:10 PM PDT 24
Finished Jul 06 05:05:12 PM PDT 24
Peak memory 200256 kb
Host smart-10a9002c-9c23-4a47-ad18-071f5cb0ea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147826351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4147826351
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2752576005
Short name T307
Test name
Test status
Simulation time 218912623 ps
CPU time 1.79 seconds
Started Jul 06 05:05:13 PM PDT 24
Finished Jul 06 05:05:15 PM PDT 24
Peak memory 200156 kb
Host smart-e2c46bfa-b1d2-4d02-b2ad-3651ef5a3b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752576005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2752576005
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.907540035
Short name T172
Test name
Test status
Simulation time 427442984 ps
CPU time 2.38 seconds
Started Jul 06 05:05:13 PM PDT 24
Finished Jul 06 05:05:16 PM PDT 24
Peak memory 200124 kb
Host smart-f226ac3f-65aa-411f-9750-dcdc22a87ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907540035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.907540035
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.786050218
Short name T366
Test name
Test status
Simulation time 253118474 ps
CPU time 1.5 seconds
Started Jul 06 05:05:12 PM PDT 24
Finished Jul 06 05:05:14 PM PDT 24
Peak memory 200128 kb
Host smart-039301b5-cf30-4abc-b9c2-6a112b351a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786050218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.786050218
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%