Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7914

1

T3

2

T6

18

T7

26

auto[1]

10793

1

T1

4

T3

12

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5799	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6340	1			T1	2		T2	1		T3	6
reset_info_cp[2]	2908	1			T1	1		T3	3		T4	1
reset_info_cp[4]	3738	1			T1	1		T3	3		T4	1
reset_info_cp[8]	108	1			T6	2		T7	1		T56	1
reset_info_cp[16]	120	1			T6	1		T9	1		T56	1
reset_info_cp[32]	108	1			T6	1		T7	1		T56	1
reset_info_cp[64]	114	1			T52	1		T54	2		T78	2
reset_info_cp[128]	92	1			T6	2		T59	1		T78	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3108	1			T3	2		T7	7		T9	12
reset_info_cp[1]	auto[1]	2612	1			T1	1		T3	3		T4	1
reset_info_cp[2]	auto[0]	926	1			T7	4		T9	4		T53	14
reset_info_cp[2]	auto[1]	1982	1			T1	1		T3	3		T4	1
reset_info_cp[4]	auto[0]	1280	1			T7	5		T9	10		T21	6
reset_info_cp[4]	auto[1]	2458	1			T1	1		T3	3		T4	1
reset_info_cp[8]	auto[0]	45	1			T6	2		T7	1		T53	2
reset_info_cp[8]	auto[1]	63	1			T56	1		T48	1		T34	1
reset_info_cp[16]	auto[0]	37	1			T6	1		T9	1		T77	1
reset_info_cp[16]	auto[1]	83	1			T56	1		T53	1		T41	1
reset_info_cp[32]	auto[0]	37	1			T6	1		T78	1		T128	1
reset_info_cp[32]	auto[1]	71	1			T7	1		T56	1		T54	1
reset_info_cp[64]	auto[0]	43	1			T52	1		T54	1		T78	1
reset_info_cp[64]	auto[1]	71	1			T54	1		T78	1		T79	2
reset_info_cp[128]	auto[0]	37	1			T6	1		T59	1		T79	1
reset_info_cp[128]	auto[1]	55	1			T6	1		T78	1		T33	1