Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T535 /workspace/coverage/default/15.rstmgr_sw_rst.4241850994 Jul 07 05:27:37 PM PDT 24 Jul 07 05:27:40 PM PDT 24 112902940 ps
T536 /workspace/coverage/default/30.rstmgr_por_stretcher.958022691 Jul 07 05:27:31 PM PDT 24 Jul 07 05:27:35 PM PDT 24 103066430 ps
T537 /workspace/coverage/default/38.rstmgr_sw_rst.1764680039 Jul 07 05:27:53 PM PDT 24 Jul 07 05:27:55 PM PDT 24 262241670 ps
T538 /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.111199176 Jul 07 05:28:02 PM PDT 24 Jul 07 05:28:03 PM PDT 24 244616159 ps
T539 /workspace/coverage/default/9.rstmgr_por_stretcher.1317776401 Jul 07 05:27:30 PM PDT 24 Jul 07 05:27:32 PM PDT 24 96284657 ps
T66 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1937035996 Jul 07 05:27:05 PM PDT 24 Jul 07 05:27:06 PM PDT 24 79902120 ps
T67 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2237026688 Jul 07 05:26:59 PM PDT 24 Jul 07 05:27:01 PM PDT 24 103237646 ps
T68 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1598223634 Jul 07 05:26:50 PM PDT 24 Jul 07 05:26:51 PM PDT 24 90774832 ps
T69 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1750388000 Jul 07 05:27:09 PM PDT 24 Jul 07 05:27:12 PM PDT 24 916738301 ps
T540 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1041001531 Jul 07 05:26:55 PM PDT 24 Jul 07 05:26:57 PM PDT 24 78790312 ps
T100 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3974528949 Jul 07 05:26:53 PM PDT 24 Jul 07 05:26:55 PM PDT 24 176525192 ps
T126 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2713025585 Jul 07 05:26:48 PM PDT 24 Jul 07 05:26:51 PM PDT 24 359745595 ps
T101 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1958919712 Jul 07 05:26:47 PM PDT 24 Jul 07 05:26:49 PM PDT 24 81731233 ps
T127 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1107242224 Jul 07 05:26:49 PM PDT 24 Jul 07 05:26:52 PM PDT 24 264492960 ps
T541 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2888346104 Jul 07 05:26:47 PM PDT 24 Jul 07 05:26:49 PM PDT 24 143855391 ps
T70 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.830577067 Jul 07 05:26:58 PM PDT 24 Jul 07 05:27:00 PM PDT 24 106284581 ps
T71 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1575614814 Jul 07 05:27:02 PM PDT 24 Jul 07 05:27:06 PM PDT 24 607409676 ps
T542 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.543241417 Jul 07 05:26:58 PM PDT 24 Jul 07 05:27:00 PM PDT 24 117111912 ps
T543 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.229493624 Jul 07 05:26:57 PM PDT 24 Jul 07 05:27:01 PM PDT 24 271649680 ps
T81 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1618144544 Jul 07 05:26:58 PM PDT 24 Jul 07 05:26:59 PM PDT 24 194403932 ps
T102 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.601750458 Jul 07 05:27:02 PM PDT 24 Jul 07 05:27:03 PM PDT 24 120822152 ps
T72 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.80119390 Jul 07 05:27:00 PM PDT 24 Jul 07 05:27:03 PM PDT 24 197907109 ps
T103 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1374765853 Jul 07 05:26:59 PM PDT 24 Jul 07 05:27:00 PM PDT 24 85441965 ps
T87 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2403344849 Jul 07 05:26:45 PM PDT 24 Jul 07 05:26:49 PM PDT 24 947489676 ps
T104 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3179749719 Jul 07 05:26:48 PM PDT 24 Jul 07 05:26:49 PM PDT 24 63623197 ps
T88 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.771069265 Jul 07 05:26:59 PM PDT 24 Jul 07 05:27:01 PM PDT 24 465317956 ps
T544 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2893000342 Jul 07 05:26:44 PM PDT 24 Jul 07 05:26:45 PM PDT 24 126656787 ps
T105 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2084736920 Jul 07 05:27:08 PM PDT 24 Jul 07 05:27:10 PM PDT 24 84943061 ps
T545 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3092867565 Jul 07 05:27:01 PM PDT 24 Jul 07 05:27:02 PM PDT 24 76819036 ps
T82 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1559698232 Jul 07 05:26:57 PM PDT 24 Jul 07 05:27:00 PM PDT 24 324367087 ps
T83 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3340023600 Jul 07 05:26:49 PM PDT 24 Jul 07 05:26:51 PM PDT 24 120995413 ps
T84 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2179601716 Jul 07 05:26:57 PM PDT 24 Jul 07 05:26:59 PM PDT 24 120607571 ps
T85 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1235832262 Jul 07 05:27:12 PM PDT 24 Jul 07 05:27:15 PM PDT 24 230204115 ps
T86 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1324946813 Jul 07 05:26:54 PM PDT 24 Jul 07 05:26:57 PM PDT 24 268362388 ps
T546 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1127579475 Jul 07 05:26:51 PM PDT 24 Jul 07 05:26:53 PM PDT 24 137482986 ps
T106 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.44550452 Jul 07 05:27:12 PM PDT 24 Jul 07 05:27:13 PM PDT 24 71162672 ps
T115 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3451584261 Jul 07 05:26:52 PM PDT 24 Jul 07 05:26:59 PM PDT 24 193152786 ps
T107 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3626532904 Jul 07 05:26:57 PM PDT 24 Jul 07 05:26:58 PM PDT 24 55535664 ps
T547 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4104858692 Jul 07 05:26:56 PM PDT 24 Jul 07 05:26:58 PM PDT 24 126787261 ps
T108 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1569463469 Jul 07 05:26:58 PM PDT 24 Jul 07 05:26:59 PM PDT 24 128374370 ps
T548 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.5636476 Jul 07 05:26:54 PM PDT 24 Jul 07 05:26:59 PM PDT 24 583414323 ps
T549 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.995059872 Jul 07 05:26:45 PM PDT 24 Jul 07 05:26:46 PM PDT 24 67989391 ps
T550 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1247845958 Jul 07 05:27:01 PM PDT 24 Jul 07 05:27:04 PM PDT 24 268786479 ps
T114 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1652441758 Jul 07 05:27:11 PM PDT 24 Jul 07 05:27:14 PM PDT 24 413529116 ps
T125 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3464717826 Jul 07 05:26:51 PM PDT 24 Jul 07 05:26:53 PM PDT 24 420369604 ps
T111 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1006859141 Jul 07 05:26:50 PM PDT 24 Jul 07 05:26:54 PM PDT 24 945334017 ps
T551 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.699358587 Jul 07 05:26:54 PM PDT 24 Jul 07 05:26:57 PM PDT 24 248904181 ps
T552 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2825815789 Jul 07 05:26:45 PM PDT 24 Jul 07 05:26:47 PM PDT 24 282530599 ps
T553 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3109795814 Jul 07 05:27:01 PM PDT 24 Jul 07 05:27:03 PM PDT 24 229458541 ps
T554 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1006863255 Jul 07 05:26:54 PM PDT 24 Jul 07 05:26:56 PM PDT 24 63241565 ps
T555 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2414287340 Jul 07 05:27:08 PM PDT 24 Jul 07 05:27:10 PM PDT 24 135874744 ps
T556 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3278762376 Jul 07 05:26:55 PM PDT 24 Jul 07 05:26:57 PM PDT 24 217531193 ps
T557 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.523797240 Jul 07 05:27:01 PM PDT 24 Jul 07 05:27:03 PM PDT 24 267277879 ps
T109 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3002744159 Jul 07 05:26:46 PM PDT 24 Jul 07 05:26:50 PM PDT 24 899951112 ps
T558 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1307432218 Jul 07 05:26:43 PM PDT 24 Jul 07 05:26:45 PM PDT 24 431029322 ps
T559 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.240592814 Jul 07 05:26:50 PM PDT 24 Jul 07 05:26:51 PM PDT 24 134901512 ps
T560 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2582291441 Jul 07 05:26:47 PM PDT 24 Jul 07 05:26:48 PM PDT 24 124951150 ps
T561 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.597231476 Jul 07 05:26:51 PM PDT 24 Jul 07 05:26:57 PM PDT 24 112989745 ps
T562 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1054384571 Jul 07 05:26:59 PM PDT 24 Jul 07 05:27:01 PM PDT 24 64530090 ps
T563 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1826101279 Jul 07 05:26:53 PM PDT 24 Jul 07 05:26:54 PM PDT 24 112832059 ps
T564 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.330721421 Jul 07 05:27:07 PM PDT 24 Jul 07 05:27:08 PM PDT 24 82271634 ps
T565 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3429343505 Jul 07 05:26:53 PM PDT 24 Jul 07 05:26:55 PM PDT 24 115121043 ps
T566 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1753541008 Jul 07 05:26:57 PM PDT 24 Jul 07 05:27:01 PM PDT 24 367782937 ps
T567 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.457128773 Jul 07 05:26:57 PM PDT 24 Jul 07 05:27:00 PM PDT 24 287290576 ps
T110 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2595767113 Jul 07 05:26:55 PM PDT 24 Jul 07 05:26:59 PM PDT 24 795585819 ps
T568 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1383147069 Jul 07 05:26:53 PM PDT 24 Jul 07 05:26:55 PM PDT 24 490877136 ps
T569 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3897449776 Jul 07 05:27:06 PM PDT 24 Jul 07 05:27:08 PM PDT 24 63777378 ps
T570 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.165069667 Jul 07 05:27:10 PM PDT 24 Jul 07 05:27:12 PM PDT 24 493567191 ps
T571 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3373316795 Jul 07 05:26:56 PM PDT 24 Jul 07 05:26:58 PM PDT 24 103580916 ps
T572 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2987224859 Jul 07 05:26:55 PM PDT 24 Jul 07 05:26:57 PM PDT 24 104653409 ps
T573 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2634872882 Jul 07 05:27:14 PM PDT 24 Jul 07 05:27:17 PM PDT 24 471750026 ps
T574 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2115386164 Jul 07 05:27:04 PM PDT 24 Jul 07 05:27:06 PM PDT 24 164362796 ps
T575 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2517677702 Jul 07 05:26:59 PM PDT 24 Jul 07 05:27:00 PM PDT 24 240321448 ps
T576 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3089185077 Jul 07 05:26:54 PM PDT 24 Jul 07 05:26:56 PM PDT 24 203319033 ps
T577 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3017855243 Jul 07 05:26:53 PM PDT 24 Jul 07 05:26:56 PM PDT 24 413909351 ps
T578 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3920403588 Jul 07 05:26:50 PM PDT 24 Jul 07 05:26:51 PM PDT 24 111563892 ps
T579 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2276800016 Jul 07 05:26:54 PM PDT 24 Jul 07 05:26:55 PM PDT 24 119236109 ps
T580 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3333411190 Jul 07 05:26:54 PM PDT 24 Jul 07 05:26:56 PM PDT 24 103998130 ps
T581 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1232736084 Jul 07 05:26:53 PM PDT 24 Jul 07 05:26:55 PM PDT 24 121282852 ps
T582 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.53146811 Jul 07 05:26:47 PM PDT 24 Jul 07 05:26:52 PM PDT 24 798459965 ps
T583 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2182396952 Jul 07 05:27:06 PM PDT 24 Jul 07 05:27:08 PM PDT 24 206359512 ps
T584 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3708303820 Jul 07 05:26:57 PM PDT 24 Jul 07 05:26:58 PM PDT 24 73984430 ps
T585 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2905674169 Jul 07 05:26:56 PM PDT 24 Jul 07 05:26:58 PM PDT 24 144356694 ps
T586 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3649299715 Jul 07 05:26:59 PM PDT 24 Jul 07 05:27:01 PM PDT 24 63522506 ps
T587 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4209960703 Jul 07 05:26:46 PM PDT 24 Jul 07 05:26:49 PM PDT 24 828457453 ps
T588 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2259561387 Jul 07 05:26:49 PM PDT 24 Jul 07 05:26:50 PM PDT 24 83813858 ps
T589 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.4041558922 Jul 07 05:27:00 PM PDT 24 Jul 07 05:27:04 PM PDT 24 1017379255 ps
T590 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1416343641 Jul 07 05:27:12 PM PDT 24 Jul 07 05:27:13 PM PDT 24 103953081 ps
T112 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1375539718 Jul 07 05:26:43 PM PDT 24 Jul 07 05:26:47 PM PDT 24 959077673 ps
T591 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.165988407 Jul 07 05:26:52 PM PDT 24 Jul 07 05:26:53 PM PDT 24 123411290 ps
T592 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1752910406 Jul 07 05:26:58 PM PDT 24 Jul 07 05:27:01 PM PDT 24 265195895 ps
T593 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1776355359 Jul 07 05:26:55 PM PDT 24 Jul 07 05:26:56 PM PDT 24 81697206 ps
T594 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3511678635 Jul 07 05:26:46 PM PDT 24 Jul 07 05:26:48 PM PDT 24 217865933 ps
T595 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3917571771 Jul 07 05:26:57 PM PDT 24 Jul 07 05:26:58 PM PDT 24 67121596 ps
T596 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1503207380 Jul 07 05:26:55 PM PDT 24 Jul 07 05:27:05 PM PDT 24 2290879292 ps
T597 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.505186179 Jul 07 05:27:08 PM PDT 24 Jul 07 05:27:10 PM PDT 24 72745006 ps
T598 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.627567423 Jul 07 05:26:49 PM PDT 24 Jul 07 05:26:52 PM PDT 24 330705697 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.435736029 Jul 07 05:26:54 PM PDT 24 Jul 07 05:26:56 PM PDT 24 68980912 ps
T600 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.59914144 Jul 07 05:26:56 PM PDT 24 Jul 07 05:26:58 PM PDT 24 97284856 ps
T601 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.832503974 Jul 07 05:26:57 PM PDT 24 Jul 07 05:26:59 PM PDT 24 116238386 ps
T602 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2693464231 Jul 07 05:27:10 PM PDT 24 Jul 07 05:27:11 PM PDT 24 75624583 ps
T603 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1953470221 Jul 07 05:26:55 PM PDT 24 Jul 07 05:26:56 PM PDT 24 65992964 ps
T604 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3859815576 Jul 07 05:26:50 PM PDT 24 Jul 07 05:26:51 PM PDT 24 83282213 ps
T605 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3222490598 Jul 07 05:26:57 PM PDT 24 Jul 07 05:26:59 PM PDT 24 514489999 ps
T606 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2182706339 Jul 07 05:27:03 PM PDT 24 Jul 07 05:27:05 PM PDT 24 431083539 ps
T607 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.4147763876 Jul 07 05:26:56 PM PDT 24 Jul 07 05:27:02 PM PDT 24 90414445 ps
T608 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3822420438 Jul 07 05:27:12 PM PDT 24 Jul 07 05:27:14 PM PDT 24 153788073 ps
T113 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1725545897 Jul 07 05:26:49 PM PDT 24 Jul 07 05:26:51 PM PDT 24 472857974 ps
T609 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3350680978 Jul 07 05:26:58 PM PDT 24 Jul 07 05:27:00 PM PDT 24 437275571 ps
T610 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1674775502 Jul 07 05:26:54 PM PDT 24 Jul 07 05:26:55 PM PDT 24 128651255 ps
T611 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1853804895 Jul 07 05:26:58 PM PDT 24 Jul 07 05:27:00 PM PDT 24 139958095 ps
T612 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1007018707 Jul 07 05:26:48 PM PDT 24 Jul 07 05:26:49 PM PDT 24 144036728 ps
T613 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1823159655 Jul 07 05:27:12 PM PDT 24 Jul 07 05:27:15 PM PDT 24 143243380 ps
T614 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1812114529 Jul 07 05:26:51 PM PDT 24 Jul 07 05:26:53 PM PDT 24 429323992 ps
T615 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1102948323 Jul 07 05:26:44 PM PDT 24 Jul 07 05:26:53 PM PDT 24 1544662199 ps
T616 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.305382298 Jul 07 05:26:52 PM PDT 24 Jul 07 05:26:54 PM PDT 24 125316901 ps
T617 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2471722304 Jul 07 05:27:15 PM PDT 24 Jul 07 05:27:17 PM PDT 24 136070775 ps
T618 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2417046933 Jul 07 05:26:56 PM PDT 24 Jul 07 05:26:58 PM PDT 24 184741629 ps
T619 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4018643981 Jul 07 05:26:55 PM PDT 24 Jul 07 05:26:57 PM PDT 24 116415577 ps
T620 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.804687957 Jul 07 05:26:58 PM PDT 24 Jul 07 05:27:01 PM PDT 24 159574709 ps

Test location /workspace/coverage/default/46.rstmgr_reset.2884687311
Short name T7
Test name
Test status
Simulation time 1270092273 ps
CPU time 5.38 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:30 PM PDT 24
Peak memory 200384 kb
Host smart-636f3c98-583c-440f-afd8-b72181515003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884687311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2884687311
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3427128502
Short name T20
Test name
Test status
Simulation time 533738941 ps
CPU time 2.65 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 200216 kb
Host smart-88c1e7d8-d642-4976-b6cb-844219364e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427128502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3427128502
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1750388000
Short name T69
Test name
Test status
Simulation time 916738301 ps
CPU time 3.08 seconds
Started Jul 07 05:27:09 PM PDT 24
Finished Jul 07 05:27:12 PM PDT 24
Peak memory 200412 kb
Host smart-8c374e84-0029-4bf0-befd-0adf02c1d10b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750388000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1750388000
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3143338576
Short name T51
Test name
Test status
Simulation time 8846809039 ps
CPU time 12.98 seconds
Started Jul 07 05:27:23 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 217260 kb
Host smart-c7de9acb-430d-404c-8f73-848d05fdfb66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143338576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3143338576
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2496826348
Short name T24
Test name
Test status
Simulation time 1900373556 ps
CPU time 7.44 seconds
Started Jul 07 05:27:49 PM PDT 24
Finished Jul 07 05:27:57 PM PDT 24
Peak memory 217788 kb
Host smart-d33cb203-cf8c-4842-9998-d5757e8ef1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496826348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2496826348
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.80119390
Short name T72
Test name
Test status
Simulation time 197907109 ps
CPU time 2.98 seconds
Started Jul 07 05:27:00 PM PDT 24
Finished Jul 07 05:27:03 PM PDT 24
Peak memory 208604 kb
Host smart-0d49bc47-3e4b-46fb-9125-a46b7103c992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80119390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.80119390
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3569079071
Short name T91
Test name
Test status
Simulation time 15831410363 ps
CPU time 58.03 seconds
Started Jul 07 05:28:01 PM PDT 24
Finished Jul 07 05:29:00 PM PDT 24
Peak memory 210752 kb
Host smart-9ced9da7-5bff-47d4-8a9f-174b389e235f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569079071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3569079071
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2435879523
Short name T129
Test name
Test status
Simulation time 89609877 ps
CPU time 0.8 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 199928 kb
Host smart-cfd66156-67cd-49f4-b682-e706b0ac7a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435879523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2435879523
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2291239826
Short name T47
Test name
Test status
Simulation time 113703657 ps
CPU time 1.02 seconds
Started Jul 07 05:27:36 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 200052 kb
Host smart-93b08ee6-1035-410a-bc7a-535a7b3a2a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291239826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2291239826
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3062768608
Short name T6
Test name
Test status
Simulation time 156443184 ps
CPU time 1.26 seconds
Started Jul 07 05:27:24 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 200400 kb
Host smart-dca36b3d-bd6a-4192-82c8-d8194a2f4342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062768608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3062768608
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2697795163
Short name T28
Test name
Test status
Simulation time 1888261590 ps
CPU time 7.29 seconds
Started Jul 07 05:28:16 PM PDT 24
Finished Jul 07 05:28:24 PM PDT 24
Peak memory 217428 kb
Host smart-8c2cce9b-cdd7-4fad-b0dc-8a92548b9201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697795163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2697795163
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1375539718
Short name T112
Test name
Test status
Simulation time 959077673 ps
CPU time 3.12 seconds
Started Jul 07 05:26:43 PM PDT 24
Finished Jul 07 05:26:47 PM PDT 24
Peak memory 200496 kb
Host smart-1b80d2b3-d248-4a37-be19-2c9dd0fc13d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375539718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1375539718
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1575614814
Short name T71
Test name
Test status
Simulation time 607409676 ps
CPU time 3.81 seconds
Started Jul 07 05:27:02 PM PDT 24
Finished Jul 07 05:27:06 PM PDT 24
Peak memory 208472 kb
Host smart-7fa31c12-0cd2-40d1-9df1-abf13e46ae7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575614814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1575614814
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2255536901
Short name T188
Test name
Test status
Simulation time 1220130258 ps
CPU time 5.75 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:38 PM PDT 24
Peak memory 217652 kb
Host smart-558491b9-0d99-4325-9414-96064c5a77ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255536901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2255536901
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3179749719
Short name T104
Test name
Test status
Simulation time 63623197 ps
CPU time 0.86 seconds
Started Jul 07 05:26:48 PM PDT 24
Finished Jul 07 05:26:49 PM PDT 24
Peak memory 200172 kb
Host smart-6e68abc2-b888-4d25-be2b-9244384b3a36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179749719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3179749719
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1231275201
Short name T12
Test name
Test status
Simulation time 178316299 ps
CPU time 0.86 seconds
Started Jul 07 05:27:04 PM PDT 24
Finished Jul 07 05:27:05 PM PDT 24
Peak memory 200012 kb
Host smart-47c1dfee-e32c-41a5-84a9-8bb9bee24bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231275201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1231275201
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1735733701
Short name T158
Test name
Test status
Simulation time 245123590 ps
CPU time 1.06 seconds
Started Jul 07 05:27:36 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 217448 kb
Host smart-0c825888-153d-4336-93fe-2edcaf5bc80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735733701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1735733701
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1652441758
Short name T114
Test name
Test status
Simulation time 413529116 ps
CPU time 1.86 seconds
Started Jul 07 05:27:11 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 200644 kb
Host smart-7d4785d3-5b94-4c89-9333-514a1d9c113c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652441758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1652441758
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.471725768
Short name T187
Test name
Test status
Simulation time 148319964 ps
CPU time 1.91 seconds
Started Jul 07 05:27:31 PM PDT 24
Finished Jul 07 05:27:35 PM PDT 24
Peak memory 200432 kb
Host smart-617183b3-e6d5-48ff-b866-038ad4ca68de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471725768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.471725768
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.543241417
Short name T542
Test name
Test status
Simulation time 117111912 ps
CPU time 1.38 seconds
Started Jul 07 05:26:58 PM PDT 24
Finished Jul 07 05:27:00 PM PDT 24
Peak memory 200372 kb
Host smart-da20b276-bb37-453b-a4d6-83188d824fd6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543241417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.543241417
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.229493624
Short name T543
Test name
Test status
Simulation time 271649680 ps
CPU time 3.31 seconds
Started Jul 07 05:26:57 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 200396 kb
Host smart-bf7fcd5d-4cb5-45cd-844e-87007d837aea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229493624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.229493624
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3859815576
Short name T604
Test name
Test status
Simulation time 83282213 ps
CPU time 0.81 seconds
Started Jul 07 05:26:50 PM PDT 24
Finished Jul 07 05:26:51 PM PDT 24
Peak memory 200120 kb
Host smart-d56d4474-d1ae-42d6-8bd7-ec860da403a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859815576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
859815576
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.240592814
Short name T559
Test name
Test status
Simulation time 134901512 ps
CPU time 1.08 seconds
Started Jul 07 05:26:50 PM PDT 24
Finished Jul 07 05:26:51 PM PDT 24
Peak memory 208964 kb
Host smart-028d57fc-4768-445f-99a0-e893768191d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240592814 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.240592814
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.435736029
Short name T599
Test name
Test status
Simulation time 68980912 ps
CPU time 0.83 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 200284 kb
Host smart-282300ad-4f7b-4af1-bb88-95713e8ed506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435736029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.435736029
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1674775502
Short name T610
Test name
Test status
Simulation time 128651255 ps
CPU time 1.15 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 200384 kb
Host smart-d9d909f2-eae4-440c-bae9-b40639f027e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674775502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1674775502
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1324946813
Short name T86
Test name
Test status
Simulation time 268362388 ps
CPU time 2.08 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:57 PM PDT 24
Peak memory 211336 kb
Host smart-df11c052-89d7-4d75-a8a7-562f7738050c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324946813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1324946813
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2115386164
Short name T574
Test name
Test status
Simulation time 164362796 ps
CPU time 2.02 seconds
Started Jul 07 05:27:04 PM PDT 24
Finished Jul 07 05:27:06 PM PDT 24
Peak memory 200444 kb
Host smart-59d83ca0-dfc0-4e0d-8f8b-5618e8d808c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115386164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
115386164
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1102948323
Short name T615
Test name
Test status
Simulation time 1544662199 ps
CPU time 8.7 seconds
Started Jul 07 05:26:44 PM PDT 24
Finished Jul 07 05:26:53 PM PDT 24
Peak memory 200436 kb
Host smart-ee8e1e33-f2a6-4f11-a373-bfbfab33dba0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102948323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
102948323
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2893000342
Short name T544
Test name
Test status
Simulation time 126656787 ps
CPU time 0.94 seconds
Started Jul 07 05:26:44 PM PDT 24
Finished Jul 07 05:26:45 PM PDT 24
Peak memory 200560 kb
Host smart-95bd1ff6-7048-4a92-8077-bcb6f16bd8e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893000342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
893000342
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2276800016
Short name T579
Test name
Test status
Simulation time 119236109 ps
CPU time 0.93 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 200340 kb
Host smart-383936cc-b110-4405-b1d7-bda37f21abb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276800016 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2276800016
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1041001531
Short name T540
Test name
Test status
Simulation time 78790312 ps
CPU time 0.93 seconds
Started Jul 07 05:26:55 PM PDT 24
Finished Jul 07 05:26:57 PM PDT 24
Peak memory 200292 kb
Host smart-587ced07-5686-4505-b578-9f1816f42c84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041001531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1041001531
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.4147763876
Short name T607
Test name
Test status
Simulation time 90414445 ps
CPU time 1.03 seconds
Started Jul 07 05:26:56 PM PDT 24
Finished Jul 07 05:27:02 PM PDT 24
Peak memory 200216 kb
Host smart-bbfa155b-d46f-4a6e-967c-fa258b58daa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147763876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.4147763876
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.804687957
Short name T620
Test name
Test status
Simulation time 159574709 ps
CPU time 2.24 seconds
Started Jul 07 05:26:58 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 208692 kb
Host smart-fe84dbe6-0abf-4252-a1ad-94cad97c1dcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804687957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.804687957
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1307432218
Short name T558
Test name
Test status
Simulation time 431029322 ps
CPU time 1.91 seconds
Started Jul 07 05:26:43 PM PDT 24
Finished Jul 07 05:26:45 PM PDT 24
Peak memory 200820 kb
Host smart-c3c0ef3a-6417-429c-b5fe-4cad082e8ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307432218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1307432218
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3429343505
Short name T565
Test name
Test status
Simulation time 115121043 ps
CPU time 0.96 seconds
Started Jul 07 05:26:53 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 200312 kb
Host smart-b44b2f84-1670-4ffe-ae11-0097e4235bbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429343505 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3429343505
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1853804895
Short name T611
Test name
Test status
Simulation time 139958095 ps
CPU time 1.37 seconds
Started Jul 07 05:26:58 PM PDT 24
Finished Jul 07 05:27:00 PM PDT 24
Peak memory 200480 kb
Host smart-c32de2de-8135-4d41-8457-eda484c393c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853804895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1853804895
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.5636476
Short name T548
Test name
Test status
Simulation time 583414323 ps
CPU time 4.11 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:59 PM PDT 24
Peak memory 208696 kb
Host smart-7fbda830-0ae8-45aa-820b-a294f5372d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5636476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.5636476
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1006859141
Short name T111
Test name
Test status
Simulation time 945334017 ps
CPU time 3.49 seconds
Started Jul 07 05:26:50 PM PDT 24
Finished Jul 07 05:26:54 PM PDT 24
Peak memory 200548 kb
Host smart-c1c59003-d1d3-441c-b115-5360884dca06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006859141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1006859141
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1232736084
Short name T581
Test name
Test status
Simulation time 121282852 ps
CPU time 1.28 seconds
Started Jul 07 05:26:53 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 213044 kb
Host smart-21f2a33f-aabb-468c-9aa0-244ae63bd2aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232736084 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1232736084
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3649299715
Short name T586
Test name
Test status
Simulation time 63522506 ps
CPU time 0.85 seconds
Started Jul 07 05:26:59 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 200180 kb
Host smart-22b089bb-fca0-4328-a339-64e4225465b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649299715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3649299715
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1937035996
Short name T66
Test name
Test status
Simulation time 79902120 ps
CPU time 1.06 seconds
Started Jul 07 05:27:05 PM PDT 24
Finished Jul 07 05:27:06 PM PDT 24
Peak memory 200348 kb
Host smart-e57bed76-501c-4bb9-8f2b-1df1df94544d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937035996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1937035996
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.305382298
Short name T616
Test name
Test status
Simulation time 125316901 ps
CPU time 1.63 seconds
Started Jul 07 05:26:52 PM PDT 24
Finished Jul 07 05:26:54 PM PDT 24
Peak memory 208616 kb
Host smart-d72b153a-7fd9-4b11-99f3-86fa2ce9a6b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305382298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.305382298
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2595767113
Short name T110
Test name
Test status
Simulation time 795585819 ps
CPU time 3.08 seconds
Started Jul 07 05:26:55 PM PDT 24
Finished Jul 07 05:26:59 PM PDT 24
Peak memory 200496 kb
Host smart-b8864638-1335-4a7a-9d7e-bf42015751a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595767113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2595767113
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1618144544
Short name T81
Test name
Test status
Simulation time 194403932 ps
CPU time 1.25 seconds
Started Jul 07 05:26:58 PM PDT 24
Finished Jul 07 05:26:59 PM PDT 24
Peak memory 200356 kb
Host smart-0cbb2eda-0386-49bd-855d-2f3476b7f2f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618144544 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1618144544
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1374765853
Short name T103
Test name
Test status
Simulation time 85441965 ps
CPU time 0.86 seconds
Started Jul 07 05:26:59 PM PDT 24
Finished Jul 07 05:27:00 PM PDT 24
Peak memory 200288 kb
Host smart-a4cc6263-d2ea-43e2-8d6b-9942881f1193
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374765853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1374765853
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3708303820
Short name T584
Test name
Test status
Simulation time 73984430 ps
CPU time 0.9 seconds
Started Jul 07 05:26:57 PM PDT 24
Finished Jul 07 05:26:58 PM PDT 24
Peak memory 200040 kb
Host smart-62395d04-a6b7-40fe-8419-4676bb59ee83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708303820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3708303820
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3333411190
Short name T580
Test name
Test status
Simulation time 103998130 ps
CPU time 1.45 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 208496 kb
Host smart-484503fb-9bb8-44b6-9b24-eb664859771e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333411190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3333411190
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4104858692
Short name T547
Test name
Test status
Simulation time 126787261 ps
CPU time 1.28 seconds
Started Jul 07 05:26:56 PM PDT 24
Finished Jul 07 05:26:58 PM PDT 24
Peak memory 208596 kb
Host smart-2e16f9b1-d35e-4d7d-8bf8-b568ae4bfd21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104858692 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4104858692
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1054384571
Short name T562
Test name
Test status
Simulation time 64530090 ps
CPU time 0.79 seconds
Started Jul 07 05:26:59 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 200184 kb
Host smart-b489fefb-5645-4266-a2be-9a4c5e55ff84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054384571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1054384571
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2084736920
Short name T105
Test name
Test status
Simulation time 84943061 ps
CPU time 0.96 seconds
Started Jul 07 05:27:08 PM PDT 24
Finished Jul 07 05:27:10 PM PDT 24
Peak memory 200348 kb
Host smart-e885497a-90ac-427a-9e81-acaad03f5299
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084736920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2084736920
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1247845958
Short name T550
Test name
Test status
Simulation time 268786479 ps
CPU time 2.15 seconds
Started Jul 07 05:27:01 PM PDT 24
Finished Jul 07 05:27:04 PM PDT 24
Peak memory 216768 kb
Host smart-fcce4809-d731-40e1-b5ae-b544f5f8663e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247845958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1247845958
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1383147069
Short name T568
Test name
Test status
Simulation time 490877136 ps
CPU time 1.81 seconds
Started Jul 07 05:26:53 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 200548 kb
Host smart-783a88aa-bab1-4df7-8448-7ba60ea348bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383147069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1383147069
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2237026688
Short name T67
Test name
Test status
Simulation time 103237646 ps
CPU time 1.05 seconds
Started Jul 07 05:26:59 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 200436 kb
Host smart-f0a650bd-5bb7-4311-8473-af9b3884f0d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237026688 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2237026688
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3092867565
Short name T545
Test name
Test status
Simulation time 76819036 ps
CPU time 0.82 seconds
Started Jul 07 05:27:01 PM PDT 24
Finished Jul 07 05:27:02 PM PDT 24
Peak memory 200192 kb
Host smart-a945e2a1-6426-42cd-9d96-31b2ef081ef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092867565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3092867565
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.457128773
Short name T567
Test name
Test status
Simulation time 287290576 ps
CPU time 1.79 seconds
Started Jul 07 05:26:57 PM PDT 24
Finished Jul 07 05:27:00 PM PDT 24
Peak memory 200488 kb
Host smart-32f083b4-b2d5-47d0-86fe-77d6dbe695ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457128773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.457128773
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1752910406
Short name T592
Test name
Test status
Simulation time 265195895 ps
CPU time 2.09 seconds
Started Jul 07 05:26:58 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 208496 kb
Host smart-481b60e3-932e-40c9-a77b-a7278fb951d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752910406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1752910406
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.771069265
Short name T88
Test name
Test status
Simulation time 465317956 ps
CPU time 2.04 seconds
Started Jul 07 05:26:59 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 200572 kb
Host smart-598d1b73-6ae9-40fb-85a6-02521d5c571d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771069265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.771069265
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.830577067
Short name T70
Test name
Test status
Simulation time 106284581 ps
CPU time 1.11 seconds
Started Jul 07 05:26:58 PM PDT 24
Finished Jul 07 05:27:00 PM PDT 24
Peak memory 208608 kb
Host smart-1264777c-cb4a-48b6-b3f2-d2d47f5f22a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830577067 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.830577067
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.330721421
Short name T564
Test name
Test status
Simulation time 82271634 ps
CPU time 0.86 seconds
Started Jul 07 05:27:07 PM PDT 24
Finished Jul 07 05:27:08 PM PDT 24
Peak memory 200288 kb
Host smart-0a06ba8d-d898-4975-b41e-42e098bf77b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330721421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.330721421
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.523797240
Short name T557
Test name
Test status
Simulation time 267277879 ps
CPU time 1.62 seconds
Started Jul 07 05:27:01 PM PDT 24
Finished Jul 07 05:27:03 PM PDT 24
Peak memory 200536 kb
Host smart-717c1474-5ddb-453c-8b76-7638b79516a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523797240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.523797240
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.832503974
Short name T601
Test name
Test status
Simulation time 116238386 ps
CPU time 1.89 seconds
Started Jul 07 05:26:57 PM PDT 24
Finished Jul 07 05:26:59 PM PDT 24
Peak memory 208564 kb
Host smart-aa51a5a6-5bf7-43d5-95fb-88b8440f72ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832503974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.832503974
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.165069667
Short name T570
Test name
Test status
Simulation time 493567191 ps
CPU time 1.94 seconds
Started Jul 07 05:27:10 PM PDT 24
Finished Jul 07 05:27:12 PM PDT 24
Peak memory 200512 kb
Host smart-911f0666-9ad4-4eb4-82b2-f1363c451bd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165069667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.165069667
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2182396952
Short name T583
Test name
Test status
Simulation time 206359512 ps
CPU time 1.3 seconds
Started Jul 07 05:27:06 PM PDT 24
Finished Jul 07 05:27:08 PM PDT 24
Peak memory 200424 kb
Host smart-be218571-daaa-442b-bcf4-afae21b9ee98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182396952 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2182396952
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3626532904
Short name T107
Test name
Test status
Simulation time 55535664 ps
CPU time 0.74 seconds
Started Jul 07 05:26:57 PM PDT 24
Finished Jul 07 05:26:58 PM PDT 24
Peak memory 200024 kb
Host smart-d5ee41b4-c680-4548-aa50-c63d7db790c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626532904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3626532904
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.601750458
Short name T102
Test name
Test status
Simulation time 120822152 ps
CPU time 1.16 seconds
Started Jul 07 05:27:02 PM PDT 24
Finished Jul 07 05:27:03 PM PDT 24
Peak memory 200356 kb
Host smart-c8f94809-fb91-4fc0-b69b-eabbe82efc1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601750458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.601750458
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3222490598
Short name T605
Test name
Test status
Simulation time 514489999 ps
CPU time 1.9 seconds
Started Jul 07 05:26:57 PM PDT 24
Finished Jul 07 05:26:59 PM PDT 24
Peak memory 200540 kb
Host smart-3e5aec3c-0a66-4b95-8b29-49a41529a5bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222490598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3222490598
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2179601716
Short name T84
Test name
Test status
Simulation time 120607571 ps
CPU time 1.01 seconds
Started Jul 07 05:26:57 PM PDT 24
Finished Jul 07 05:26:59 PM PDT 24
Peak memory 200328 kb
Host smart-3fdee11a-8113-4b14-b3ba-f35694052818
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179601716 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2179601716
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3897449776
Short name T569
Test name
Test status
Simulation time 63777378 ps
CPU time 0.8 seconds
Started Jul 07 05:27:06 PM PDT 24
Finished Jul 07 05:27:08 PM PDT 24
Peak memory 200176 kb
Host smart-37cd5bb4-03c1-457c-bbfe-58d2ef7619e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897449776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3897449776
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3109795814
Short name T553
Test name
Test status
Simulation time 229458541 ps
CPU time 1.9 seconds
Started Jul 07 05:27:01 PM PDT 24
Finished Jul 07 05:27:03 PM PDT 24
Peak memory 200384 kb
Host smart-81c74952-99f1-455b-bfaf-c178c1074e60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109795814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3109795814
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1235832262
Short name T85
Test name
Test status
Simulation time 230204115 ps
CPU time 1.87 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:15 PM PDT 24
Peak memory 211816 kb
Host smart-0b0d5955-0b87-4d9c-b08f-5e277affb5ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235832262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1235832262
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2634872882
Short name T573
Test name
Test status
Simulation time 471750026 ps
CPU time 1.89 seconds
Started Jul 07 05:27:14 PM PDT 24
Finished Jul 07 05:27:17 PM PDT 24
Peak memory 200492 kb
Host smart-f4a34559-7ec0-42e1-8f5c-ca501a03bc75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634872882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2634872882
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1823159655
Short name T613
Test name
Test status
Simulation time 143243380 ps
CPU time 1.35 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:15 PM PDT 24
Peak memory 200372 kb
Host smart-5c4ff16d-5a4a-45fe-8c0f-683037df5eec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823159655 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1823159655
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.505186179
Short name T597
Test name
Test status
Simulation time 72745006 ps
CPU time 0.84 seconds
Started Jul 07 05:27:08 PM PDT 24
Finished Jul 07 05:27:10 PM PDT 24
Peak memory 200288 kb
Host smart-f9807407-be6f-465d-9322-194246643fd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505186179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.505186179
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2414287340
Short name T555
Test name
Test status
Simulation time 135874744 ps
CPU time 1.23 seconds
Started Jul 07 05:27:08 PM PDT 24
Finished Jul 07 05:27:10 PM PDT 24
Peak memory 200344 kb
Host smart-18ff1d83-0ae9-4d89-b097-317246bb2ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414287340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2414287340
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3822420438
Short name T608
Test name
Test status
Simulation time 153788073 ps
CPU time 2.1 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 208520 kb
Host smart-e5cd408e-568f-429f-8b81-90b5bc5ce55b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822420438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3822420438
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2182706339
Short name T606
Test name
Test status
Simulation time 431083539 ps
CPU time 1.81 seconds
Started Jul 07 05:27:03 PM PDT 24
Finished Jul 07 05:27:05 PM PDT 24
Peak memory 200480 kb
Host smart-26e567bf-cb46-4bcc-aadb-e6322dd3a261
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182706339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2182706339
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1416343641
Short name T590
Test name
Test status
Simulation time 103953081 ps
CPU time 1.12 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:13 PM PDT 24
Peak memory 208580 kb
Host smart-336210e7-0601-49d3-93a4-b8ff6ad7c463
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416343641 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1416343641
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.44550452
Short name T106
Test name
Test status
Simulation time 71162672 ps
CPU time 0.81 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:13 PM PDT 24
Peak memory 200304 kb
Host smart-6a68c55d-9e9d-476a-b219-03248f4dbdbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44550452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.44550452
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2471722304
Short name T617
Test name
Test status
Simulation time 136070775 ps
CPU time 1.26 seconds
Started Jul 07 05:27:15 PM PDT 24
Finished Jul 07 05:27:17 PM PDT 24
Peak memory 208740 kb
Host smart-26fc399c-363c-4841-ae9e-fd6d8f3f09b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471722304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2471722304
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4018643981
Short name T619
Test name
Test status
Simulation time 116415577 ps
CPU time 1.37 seconds
Started Jul 07 05:26:55 PM PDT 24
Finished Jul 07 05:26:57 PM PDT 24
Peak memory 200440 kb
Host smart-3452ed23-6f5e-4b0e-b028-c1d8b4a3ded2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018643981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.4
018643981
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1503207380
Short name T596
Test name
Test status
Simulation time 2290879292 ps
CPU time 9.92 seconds
Started Jul 07 05:26:55 PM PDT 24
Finished Jul 07 05:27:05 PM PDT 24
Peak memory 200568 kb
Host smart-9b0b9548-538c-4773-8067-4cb9dc72823c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503207380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
503207380
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1007018707
Short name T612
Test name
Test status
Simulation time 144036728 ps
CPU time 0.95 seconds
Started Jul 07 05:26:48 PM PDT 24
Finished Jul 07 05:26:49 PM PDT 24
Peak memory 200272 kb
Host smart-7eb829ed-c398-4cb6-820f-439ade114fd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007018707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
007018707
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.165988407
Short name T591
Test name
Test status
Simulation time 123411290 ps
CPU time 1.39 seconds
Started Jul 07 05:26:52 PM PDT 24
Finished Jul 07 05:26:53 PM PDT 24
Peak memory 208612 kb
Host smart-2d800004-dbea-40c0-962e-56252f9a2370
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165988407 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.165988407
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1953470221
Short name T603
Test name
Test status
Simulation time 65992964 ps
CPU time 0.83 seconds
Started Jul 07 05:26:55 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 200292 kb
Host smart-beba93b6-74b5-4e45-b418-12abb6274668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953470221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1953470221
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2987224859
Short name T572
Test name
Test status
Simulation time 104653409 ps
CPU time 1.28 seconds
Started Jul 07 05:26:55 PM PDT 24
Finished Jul 07 05:26:57 PM PDT 24
Peak memory 200540 kb
Host smart-c549c6d5-a372-4906-9f0b-c6efc609c9b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987224859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2987224859
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3511678635
Short name T594
Test name
Test status
Simulation time 217865933 ps
CPU time 1.87 seconds
Started Jul 07 05:26:46 PM PDT 24
Finished Jul 07 05:26:48 PM PDT 24
Peak memory 211492 kb
Host smart-a2ec22d3-bf4b-4870-8f52-48e2da153d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511678635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3511678635
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3350680978
Short name T609
Test name
Test status
Simulation time 437275571 ps
CPU time 1.74 seconds
Started Jul 07 05:26:58 PM PDT 24
Finished Jul 07 05:27:00 PM PDT 24
Peak memory 200504 kb
Host smart-77b27cfc-0c3b-4a06-bbd4-d0b73a8aa9f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350680978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3350680978
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.597231476
Short name T561
Test name
Test status
Simulation time 112989745 ps
CPU time 1.33 seconds
Started Jul 07 05:26:51 PM PDT 24
Finished Jul 07 05:26:57 PM PDT 24
Peak memory 200344 kb
Host smart-8b3ff0ed-cc15-4be2-9b83-0499fb1c48de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597231476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.597231476
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1107242224
Short name T127
Test name
Test status
Simulation time 264492960 ps
CPU time 3.28 seconds
Started Jul 07 05:26:49 PM PDT 24
Finished Jul 07 05:26:52 PM PDT 24
Peak memory 200344 kb
Host smart-5c6df78b-f586-44a1-ad5a-6df30efa69fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107242224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
107242224
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2582291441
Short name T560
Test name
Test status
Simulation time 124951150 ps
CPU time 0.91 seconds
Started Jul 07 05:26:47 PM PDT 24
Finished Jul 07 05:26:48 PM PDT 24
Peak memory 200308 kb
Host smart-94df3ee9-76d2-4fc8-8485-6c912cc08f42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582291441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
582291441
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3278762376
Short name T556
Test name
Test status
Simulation time 217531193 ps
CPU time 1.59 seconds
Started Jul 07 05:26:55 PM PDT 24
Finished Jul 07 05:26:57 PM PDT 24
Peak memory 208604 kb
Host smart-cb9f693c-c264-4045-8a84-75fffd7e2798
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278762376 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3278762376
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1958919712
Short name T101
Test name
Test status
Simulation time 81731233 ps
CPU time 0.89 seconds
Started Jul 07 05:26:47 PM PDT 24
Finished Jul 07 05:26:49 PM PDT 24
Peak memory 200308 kb
Host smart-58214499-308c-435c-9ef8-b998fbabe057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958919712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1958919712
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2417046933
Short name T618
Test name
Test status
Simulation time 184741629 ps
CPU time 1.42 seconds
Started Jul 07 05:26:56 PM PDT 24
Finished Jul 07 05:26:58 PM PDT 24
Peak memory 200548 kb
Host smart-f07374ea-5a74-4e28-9ecd-31d54af3ca84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417046933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2417046933
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3017855243
Short name T577
Test name
Test status
Simulation time 413909351 ps
CPU time 3.04 seconds
Started Jul 07 05:26:53 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 216536 kb
Host smart-903581ab-3ee8-4761-9d8e-38c87b85b7e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017855243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3017855243
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3002744159
Short name T109
Test name
Test status
Simulation time 899951112 ps
CPU time 3.02 seconds
Started Jul 07 05:26:46 PM PDT 24
Finished Jul 07 05:26:50 PM PDT 24
Peak memory 200388 kb
Host smart-59b0171e-558d-42dd-ab4f-c30d2658d1fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002744159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3002744159
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2713025585
Short name T126
Test name
Test status
Simulation time 359745595 ps
CPU time 2.49 seconds
Started Jul 07 05:26:48 PM PDT 24
Finished Jul 07 05:26:51 PM PDT 24
Peak memory 200316 kb
Host smart-34e38644-c29b-4061-9a92-d2bd4ed367d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713025585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
713025585
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.53146811
Short name T582
Test name
Test status
Simulation time 798459965 ps
CPU time 4.84 seconds
Started Jul 07 05:26:47 PM PDT 24
Finished Jul 07 05:26:52 PM PDT 24
Peak memory 200436 kb
Host smart-99c6c406-6e11-465e-b2b7-3cb2beb3c179
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53146811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.53146811
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2888346104
Short name T541
Test name
Test status
Simulation time 143855391 ps
CPU time 0.95 seconds
Started Jul 07 05:26:47 PM PDT 24
Finished Jul 07 05:26:49 PM PDT 24
Peak memory 200296 kb
Host smart-6128d7ca-ece5-41e7-a5a2-7f36b1d74c80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888346104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
888346104
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3373316795
Short name T571
Test name
Test status
Simulation time 103580916 ps
CPU time 0.96 seconds
Started Jul 07 05:26:56 PM PDT 24
Finished Jul 07 05:26:58 PM PDT 24
Peak memory 200312 kb
Host smart-84f9793e-62fe-493f-a506-5c66a65b6302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373316795 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3373316795
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.995059872
Short name T549
Test name
Test status
Simulation time 67989391 ps
CPU time 0.81 seconds
Started Jul 07 05:26:45 PM PDT 24
Finished Jul 07 05:26:46 PM PDT 24
Peak memory 200020 kb
Host smart-f3aa5d6d-f75a-46ed-ab92-9d43e7b30828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995059872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.995059872
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3974528949
Short name T100
Test name
Test status
Simulation time 176525192 ps
CPU time 1.4 seconds
Started Jul 07 05:26:53 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 200492 kb
Host smart-8f2e471c-e818-458e-8e10-40dc6d04be8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974528949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3974528949
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3340023600
Short name T83
Test name
Test status
Simulation time 120995413 ps
CPU time 1.7 seconds
Started Jul 07 05:26:49 PM PDT 24
Finished Jul 07 05:26:51 PM PDT 24
Peak memory 208504 kb
Host smart-940d2356-b36f-466b-a5dc-202308fee6f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340023600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3340023600
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2403344849
Short name T87
Test name
Test status
Simulation time 947489676 ps
CPU time 3.32 seconds
Started Jul 07 05:26:45 PM PDT 24
Finished Jul 07 05:26:49 PM PDT 24
Peak memory 200564 kb
Host smart-00b7f683-a841-4e4d-a867-756bea3d178c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403344849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2403344849
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3089185077
Short name T576
Test name
Test status
Simulation time 203319033 ps
CPU time 1.32 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 208616 kb
Host smart-54ab73c7-fd6e-4e6a-b922-8f634dda209c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089185077 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3089185077
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2259561387
Short name T588
Test name
Test status
Simulation time 83813858 ps
CPU time 0.87 seconds
Started Jul 07 05:26:49 PM PDT 24
Finished Jul 07 05:26:50 PM PDT 24
Peak memory 200244 kb
Host smart-32007de0-8a31-4f23-a34b-5487638b08e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259561387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2259561387
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.59914144
Short name T600
Test name
Test status
Simulation time 97284856 ps
CPU time 1.23 seconds
Started Jul 07 05:26:56 PM PDT 24
Finished Jul 07 05:26:58 PM PDT 24
Peak memory 200472 kb
Host smart-fc1209dd-c56a-403a-9763-c5b230e72649
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59914144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same
_csr_outstanding.59914144
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.627567423
Short name T598
Test name
Test status
Simulation time 330705697 ps
CPU time 2.11 seconds
Started Jul 07 05:26:49 PM PDT 24
Finished Jul 07 05:26:52 PM PDT 24
Peak memory 208624 kb
Host smart-0d9dea9c-1d54-4b9a-bd45-eb62e1a49e64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627567423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.627567423
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4209960703
Short name T587
Test name
Test status
Simulation time 828457453 ps
CPU time 2.72 seconds
Started Jul 07 05:26:46 PM PDT 24
Finished Jul 07 05:26:49 PM PDT 24
Peak memory 200504 kb
Host smart-29b3eac9-233a-4a0d-ae83-2c92a8baae75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209960703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.4209960703
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3451584261
Short name T115
Test name
Test status
Simulation time 193152786 ps
CPU time 2 seconds
Started Jul 07 05:26:52 PM PDT 24
Finished Jul 07 05:26:59 PM PDT 24
Peak memory 208824 kb
Host smart-8542d2bd-701f-432a-80a9-3dc19b722bb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451584261 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3451584261
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1006863255
Short name T554
Test name
Test status
Simulation time 63241565 ps
CPU time 0.82 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 200196 kb
Host smart-51e26f0a-97d1-4159-b231-7537475027a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006863255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1006863255
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3920403588
Short name T578
Test name
Test status
Simulation time 111563892 ps
CPU time 1.27 seconds
Started Jul 07 05:26:50 PM PDT 24
Finished Jul 07 05:26:51 PM PDT 24
Peak memory 200520 kb
Host smart-55675f8b-f0e3-4915-a4a6-8a8655e5c1ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920403588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3920403588
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2825815789
Short name T552
Test name
Test status
Simulation time 282530599 ps
CPU time 2.12 seconds
Started Jul 07 05:26:45 PM PDT 24
Finished Jul 07 05:26:47 PM PDT 24
Peak memory 208548 kb
Host smart-13958d47-2f21-49d0-be17-f1db6a904ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825815789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2825815789
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3464717826
Short name T125
Test name
Test status
Simulation time 420369604 ps
CPU time 1.84 seconds
Started Jul 07 05:26:51 PM PDT 24
Finished Jul 07 05:26:53 PM PDT 24
Peak memory 200404 kb
Host smart-058ce6fa-8c97-41b6-b775-f97c34e38b83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464717826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3464717826
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1127579475
Short name T546
Test name
Test status
Simulation time 137482986 ps
CPU time 1.16 seconds
Started Jul 07 05:26:51 PM PDT 24
Finished Jul 07 05:26:53 PM PDT 24
Peak memory 210832 kb
Host smart-45f9e568-507f-4cfb-a0b4-445abfe62a62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127579475 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1127579475
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2693464231
Short name T602
Test name
Test status
Simulation time 75624583 ps
CPU time 0.79 seconds
Started Jul 07 05:27:10 PM PDT 24
Finished Jul 07 05:27:11 PM PDT 24
Peak memory 200184 kb
Host smart-bfdf52cc-9671-4bc9-9ff6-1886675eb233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693464231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2693464231
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1569463469
Short name T108
Test name
Test status
Simulation time 128374370 ps
CPU time 1.04 seconds
Started Jul 07 05:26:58 PM PDT 24
Finished Jul 07 05:26:59 PM PDT 24
Peak memory 200284 kb
Host smart-b0fec47c-96a9-45fb-8eb4-29e49080065c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569463469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1569463469
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1559698232
Short name T82
Test name
Test status
Simulation time 324367087 ps
CPU time 2.45 seconds
Started Jul 07 05:26:57 PM PDT 24
Finished Jul 07 05:27:00 PM PDT 24
Peak memory 216744 kb
Host smart-9879e5dc-7e79-49ea-94d6-314027d4a722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559698232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1559698232
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.4041558922
Short name T589
Test name
Test status
Simulation time 1017379255 ps
CPU time 3.37 seconds
Started Jul 07 05:27:00 PM PDT 24
Finished Jul 07 05:27:04 PM PDT 24
Peak memory 200352 kb
Host smart-093171ee-8bd2-4eab-81e6-0a3e5c6cccd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041558922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.4041558922
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2905674169
Short name T585
Test name
Test status
Simulation time 144356694 ps
CPU time 1.09 seconds
Started Jul 07 05:26:56 PM PDT 24
Finished Jul 07 05:26:58 PM PDT 24
Peak memory 208608 kb
Host smart-1b8d0aec-e138-442f-ae9d-f79f7fcf90bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905674169 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2905674169
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3917571771
Short name T595
Test name
Test status
Simulation time 67121596 ps
CPU time 0.76 seconds
Started Jul 07 05:26:57 PM PDT 24
Finished Jul 07 05:26:58 PM PDT 24
Peak memory 199948 kb
Host smart-6ef3c415-8cd3-4f7b-aa1c-ad6a6526a552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917571771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3917571771
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2517677702
Short name T575
Test name
Test status
Simulation time 240321448 ps
CPU time 1.54 seconds
Started Jul 07 05:26:59 PM PDT 24
Finished Jul 07 05:27:00 PM PDT 24
Peak memory 200472 kb
Host smart-32eb2c3b-8c7f-4fd7-afb4-ecfe7d044b30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517677702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2517677702
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1753541008
Short name T566
Test name
Test status
Simulation time 367782937 ps
CPU time 2.51 seconds
Started Jul 07 05:26:57 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 208636 kb
Host smart-cb75bba1-21dc-4e9a-a7ff-1004d8e7d9a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753541008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1753541008
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1725545897
Short name T113
Test name
Test status
Simulation time 472857974 ps
CPU time 1.98 seconds
Started Jul 07 05:26:49 PM PDT 24
Finished Jul 07 05:26:51 PM PDT 24
Peak memory 200520 kb
Host smart-8180af56-2bb1-4f27-be53-d9de58900b16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725545897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1725545897
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1826101279
Short name T563
Test name
Test status
Simulation time 112832059 ps
CPU time 0.96 seconds
Started Jul 07 05:26:53 PM PDT 24
Finished Jul 07 05:26:54 PM PDT 24
Peak memory 200424 kb
Host smart-ef490ef4-9c11-426d-9e11-225628ae7321
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826101279 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1826101279
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1598223634
Short name T68
Test name
Test status
Simulation time 90774832 ps
CPU time 0.9 seconds
Started Jul 07 05:26:50 PM PDT 24
Finished Jul 07 05:26:51 PM PDT 24
Peak memory 200256 kb
Host smart-dd34dea7-1690-421b-9359-18b847f979a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598223634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1598223634
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1776355359
Short name T593
Test name
Test status
Simulation time 81697206 ps
CPU time 0.97 seconds
Started Jul 07 05:26:55 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 200352 kb
Host smart-0c8047ad-20dd-4710-90b5-42f2d5e9db65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776355359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1776355359
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.699358587
Short name T551
Test name
Test status
Simulation time 248904181 ps
CPU time 1.92 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:57 PM PDT 24
Peak memory 208580 kb
Host smart-acb5276f-2b90-4f85-886e-a05b915e7d4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699358587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.699358587
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1812114529
Short name T614
Test name
Test status
Simulation time 429323992 ps
CPU time 1.8 seconds
Started Jul 07 05:26:51 PM PDT 24
Finished Jul 07 05:26:53 PM PDT 24
Peak memory 200484 kb
Host smart-8d1615ce-6591-45c3-861f-09b583def756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812114529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1812114529
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2222139452
Short name T504
Test name
Test status
Simulation time 60690201 ps
CPU time 0.76 seconds
Started Jul 07 05:27:08 PM PDT 24
Finished Jul 07 05:27:09 PM PDT 24
Peak memory 199944 kb
Host smart-57609d9e-21eb-4fb0-9616-4ead1edc8a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222139452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2222139452
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.4059054024
Short name T228
Test name
Test status
Simulation time 1895177330 ps
CPU time 7.38 seconds
Started Jul 07 05:27:05 PM PDT 24
Finished Jul 07 05:27:13 PM PDT 24
Peak memory 217628 kb
Host smart-8a8f06c9-3459-468e-ba8a-be91c0477059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059054024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.4059054024
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3957710177
Short name T322
Test name
Test status
Simulation time 244236460 ps
CPU time 1.08 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 217492 kb
Host smart-af57dcbf-78c5-447b-b3d8-9b88c45ced69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957710177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3957710177
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3609829801
Short name T462
Test name
Test status
Simulation time 1541534737 ps
CPU time 5.73 seconds
Started Jul 07 05:27:13 PM PDT 24
Finished Jul 07 05:27:20 PM PDT 24
Peak memory 200388 kb
Host smart-de82bf3c-aad7-431a-92b0-411ca7945cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609829801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3609829801
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2513390888
Short name T73
Test name
Test status
Simulation time 16530210902 ps
CPU time 30.97 seconds
Started Jul 07 05:27:13 PM PDT 24
Finished Jul 07 05:27:45 PM PDT 24
Peak memory 217204 kb
Host smart-2fb967a8-9327-4169-b349-0f8f41f924e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513390888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2513390888
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3866404166
Short name T366
Test name
Test status
Simulation time 155117662 ps
CPU time 1.13 seconds
Started Jul 07 05:27:11 PM PDT 24
Finished Jul 07 05:27:13 PM PDT 24
Peak memory 200156 kb
Host smart-3cacb7e2-1c72-4a03-92c7-6b521308ae61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866404166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3866404166
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2252747078
Short name T441
Test name
Test status
Simulation time 191949721 ps
CPU time 1.32 seconds
Started Jul 07 05:27:10 PM PDT 24
Finished Jul 07 05:27:12 PM PDT 24
Peak memory 200372 kb
Host smart-e393110e-ab84-496d-aea1-45b7bf99ef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252747078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2252747078
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.403653375
Short name T469
Test name
Test status
Simulation time 13436311276 ps
CPU time 43.63 seconds
Started Jul 07 05:27:15 PM PDT 24
Finished Jul 07 05:27:59 PM PDT 24
Peak memory 208684 kb
Host smart-56a3c4a6-da70-40b8-b89d-0c15481d179e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403653375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.403653375
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2552020786
Short name T471
Test name
Test status
Simulation time 115150355 ps
CPU time 1.45 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 200144 kb
Host smart-a3e561fd-4c06-4108-866d-1220bce456d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552020786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2552020786
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.190111772
Short name T400
Test name
Test status
Simulation time 217483506 ps
CPU time 1.35 seconds
Started Jul 07 05:26:59 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 200128 kb
Host smart-69ac42b2-a21a-4be2-aaff-3c83f77012ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190111772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.190111772
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3175496293
Short name T429
Test name
Test status
Simulation time 77415809 ps
CPU time 0.83 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 199876 kb
Host smart-8a77c9a7-c835-4f06-b1d4-2391ff4ec844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175496293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3175496293
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1880952421
Short name T405
Test name
Test status
Simulation time 1899711342 ps
CPU time 6.8 seconds
Started Jul 07 05:27:21 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 217812 kb
Host smart-6a928041-f3a4-497c-b79c-52a8dd1b86a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880952421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1880952421
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.4140446259
Short name T442
Test name
Test status
Simulation time 249816452 ps
CPU time 1.07 seconds
Started Jul 07 05:27:07 PM PDT 24
Finished Jul 07 05:27:09 PM PDT 24
Peak memory 217400 kb
Host smart-d4cd6fd0-c98f-4e14-96b8-ce054ed75fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140446259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.4140446259
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1930058976
Short name T418
Test name
Test status
Simulation time 218821130 ps
CPU time 1 seconds
Started Jul 07 05:27:11 PM PDT 24
Finished Jul 07 05:27:12 PM PDT 24
Peak memory 199976 kb
Host smart-579c7c1f-dd3a-41a3-ad39-e70cdd7c5aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930058976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1930058976
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.577253523
Short name T395
Test name
Test status
Simulation time 1074631570 ps
CPU time 5.64 seconds
Started Jul 07 05:27:13 PM PDT 24
Finished Jul 07 05:27:19 PM PDT 24
Peak memory 200356 kb
Host smart-3857bb74-04b1-4576-89d3-0c3584dc566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577253523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.577253523
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1053879192
Short name T75
Test name
Test status
Simulation time 9306562233 ps
CPU time 14.27 seconds
Started Jul 07 05:27:10 PM PDT 24
Finished Jul 07 05:27:25 PM PDT 24
Peak memory 217076 kb
Host smart-91c38746-9e57-46e9-ba8a-52eadc301752
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053879192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1053879192
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3957440413
Short name T404
Test name
Test status
Simulation time 102916598 ps
CPU time 1.09 seconds
Started Jul 07 05:27:01 PM PDT 24
Finished Jul 07 05:27:02 PM PDT 24
Peak memory 200080 kb
Host smart-0503cc6d-360e-4508-8a7b-b564ac0702b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957440413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3957440413
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1524298596
Short name T124
Test name
Test status
Simulation time 192818602 ps
CPU time 1.45 seconds
Started Jul 07 05:27:02 PM PDT 24
Finished Jul 07 05:27:03 PM PDT 24
Peak memory 200332 kb
Host smart-daabe234-7e97-454a-8065-d337a1504887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524298596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1524298596
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3559790224
Short name T238
Test name
Test status
Simulation time 15068654349 ps
CPU time 51.25 seconds
Started Jul 07 05:27:10 PM PDT 24
Finished Jul 07 05:28:02 PM PDT 24
Peak memory 208680 kb
Host smart-693a4a80-dc46-4d05-a54c-ba8a3cba6fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559790224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3559790224
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2969690437
Short name T451
Test name
Test status
Simulation time 314400396 ps
CPU time 2.03 seconds
Started Jul 07 05:27:10 PM PDT 24
Finished Jul 07 05:27:13 PM PDT 24
Peak memory 208320 kb
Host smart-eb376080-8251-415c-ab6f-cd01c52fbaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969690437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2969690437
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3283605970
Short name T143
Test name
Test status
Simulation time 120499934 ps
CPU time 1.01 seconds
Started Jul 07 05:27:07 PM PDT 24
Finished Jul 07 05:27:09 PM PDT 24
Peak memory 200136 kb
Host smart-fbaa2de1-79cb-46bf-9707-940e397bbb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283605970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3283605970
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.733965316
Short name T383
Test name
Test status
Simulation time 63065576 ps
CPU time 0.72 seconds
Started Jul 07 05:27:23 PM PDT 24
Finished Jul 07 05:27:25 PM PDT 24
Peak memory 199948 kb
Host smart-00c91caa-6cf3-470f-b1a5-2dc56f5090fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733965316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.733965316
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.236150639
Short name T494
Test name
Test status
Simulation time 1902544491 ps
CPU time 6.97 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:44 PM PDT 24
Peak memory 221752 kb
Host smart-109e5f08-42f6-4f63-bd66-c5b38f883249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236150639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.236150639
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1705299583
Short name T292
Test name
Test status
Simulation time 244071203 ps
CPU time 1.01 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:31 PM PDT 24
Peak memory 217536 kb
Host smart-cef5c30d-320a-4442-b8c1-89f90e05239a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705299583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1705299583
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2811382196
Short name T303
Test name
Test status
Simulation time 128406400 ps
CPU time 0.83 seconds
Started Jul 07 05:27:21 PM PDT 24
Finished Jul 07 05:27:23 PM PDT 24
Peak memory 199924 kb
Host smart-edbde22f-f108-4253-a105-78299109fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811382196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2811382196
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.415849779
Short name T298
Test name
Test status
Simulation time 1381876571 ps
CPU time 5.9 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:38 PM PDT 24
Peak memory 200448 kb
Host smart-4bef2796-abd6-4f4a-afaf-dedfdbf3f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415849779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.415849779
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.622090640
Short name T459
Test name
Test status
Simulation time 150161724 ps
CPU time 1.1 seconds
Started Jul 07 05:27:37 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 200092 kb
Host smart-f4927e7c-6a17-47a2-b3ae-0f30a683718c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622090640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.622090640
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1365985033
Short name T166
Test name
Test status
Simulation time 254196811 ps
CPU time 1.47 seconds
Started Jul 07 05:27:25 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 200276 kb
Host smart-223d85c7-efb2-4998-97b3-6eacfe272e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365985033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1365985033
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3603342591
Short name T300
Test name
Test status
Simulation time 6362206632 ps
CPU time 21.54 seconds
Started Jul 07 05:27:32 PM PDT 24
Finished Jul 07 05:27:56 PM PDT 24
Peak memory 208672 kb
Host smart-13736b44-e4e0-4094-a837-ccf71b613b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603342591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3603342591
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2177734952
Short name T77
Test name
Test status
Simulation time 77566135 ps
CPU time 0.85 seconds
Started Jul 07 05:27:36 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 200084 kb
Host smart-61eb4f5f-03ce-4f5b-bd9b-bb53a59d7ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177734952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2177734952
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1251229834
Short name T218
Test name
Test status
Simulation time 73695406 ps
CPU time 0.8 seconds
Started Jul 07 05:27:26 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 199944 kb
Host smart-2ed73f63-413a-4de6-b3b3-05d73b009d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251229834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1251229834
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.929862834
Short name T346
Test name
Test status
Simulation time 2165308095 ps
CPU time 7.58 seconds
Started Jul 07 05:27:39 PM PDT 24
Finished Jul 07 05:27:47 PM PDT 24
Peak memory 221780 kb
Host smart-97407a13-93fd-4845-96f6-c379b12f6048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929862834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.929862834
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.154035026
Short name T353
Test name
Test status
Simulation time 244983946 ps
CPU time 1.06 seconds
Started Jul 07 05:27:25 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 217524 kb
Host smart-bae58ace-824b-448c-9d6b-7294bf59bf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154035026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.154035026
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1828348909
Short name T368
Test name
Test status
Simulation time 169496438 ps
CPU time 0.88 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 199896 kb
Host smart-d41df0b0-5be1-4212-a113-1d6be19f298e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828348909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1828348909
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.641113289
Short name T390
Test name
Test status
Simulation time 842750216 ps
CPU time 4.1 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:34 PM PDT 24
Peak memory 200404 kb
Host smart-6920c409-da66-415c-ac36-53d46948a03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641113289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.641113289
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1285176687
Short name T212
Test name
Test status
Simulation time 143538894 ps
CPU time 1.1 seconds
Started Jul 07 05:27:24 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 200152 kb
Host smart-c6fa4fa6-75a0-42a7-a12e-ac997f70722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285176687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1285176687
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.501711199
Short name T452
Test name
Test status
Simulation time 195655905 ps
CPU time 1.41 seconds
Started Jul 07 05:27:26 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 200304 kb
Host smart-e9b0d9e6-c2b9-4ae7-9368-1409bfea9251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501711199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.501711199
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3941212447
Short name T161
Test name
Test status
Simulation time 2004510951 ps
CPU time 7.71 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:31 PM PDT 24
Peak memory 200392 kb
Host smart-11bc0d01-2640-4655-a6b3-72b66eea94b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941212447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3941212447
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.644277331
Short name T235
Test name
Test status
Simulation time 391736515 ps
CPU time 2.64 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:38 PM PDT 24
Peak memory 208348 kb
Host smart-8b348f28-1c2a-479d-a524-6895ee533b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644277331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.644277331
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1046723169
Short name T59
Test name
Test status
Simulation time 194583374 ps
CPU time 1.23 seconds
Started Jul 07 05:27:23 PM PDT 24
Finished Jul 07 05:27:25 PM PDT 24
Peak memory 200152 kb
Host smart-6807faa9-e95b-4dd7-b3ae-0d75b9ddcc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046723169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1046723169
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1741381576
Short name T215
Test name
Test status
Simulation time 74369087 ps
CPU time 0.75 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:30 PM PDT 24
Peak memory 199936 kb
Host smart-b7b0d413-8789-4814-8875-fff9295fd8d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741381576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1741381576
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.394570098
Short name T431
Test name
Test status
Simulation time 244459345 ps
CPU time 1 seconds
Started Jul 07 05:27:24 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 217492 kb
Host smart-4401e0f8-0b50-46e0-ab39-60f00fa8c44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394570098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.394570098
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2588006345
Short name T13
Test name
Test status
Simulation time 193365264 ps
CPU time 0.89 seconds
Started Jul 07 05:27:25 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 199728 kb
Host smart-7f818721-581b-4f63-aa22-392008725cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588006345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2588006345
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.350001154
Short name T526
Test name
Test status
Simulation time 1503253774 ps
CPU time 5.31 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:37 PM PDT 24
Peak memory 200404 kb
Host smart-98dfefba-ea3d-4d2c-89c5-aacdaf2c15ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350001154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.350001154
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2503433469
Short name T239
Test name
Test status
Simulation time 104729997 ps
CPU time 0.94 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 200148 kb
Host smart-7b22b641-1c8b-45a6-8e2c-6239b387645c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503433469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2503433469
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.326987751
Short name T370
Test name
Test status
Simulation time 254533473 ps
CPU time 1.7 seconds
Started Jul 07 05:28:02 PM PDT 24
Finished Jul 07 05:28:05 PM PDT 24
Peak memory 200292 kb
Host smart-0ada4406-dbf5-417e-aa43-12b5504d68fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326987751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.326987751
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1530888719
Short name T497
Test name
Test status
Simulation time 1781288685 ps
CPU time 8.16 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:31 PM PDT 24
Peak memory 200364 kb
Host smart-5fc9d7eb-89e4-4ec5-8b66-7f4a2e659e7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530888719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1530888719
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1778501454
Short name T236
Test name
Test status
Simulation time 307491405 ps
CPU time 2.01 seconds
Started Jul 07 05:27:31 PM PDT 24
Finished Jul 07 05:27:35 PM PDT 24
Peak memory 208272 kb
Host smart-2d86663b-7034-4338-820a-fb1f1f8c7e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778501454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1778501454
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1623562480
Short name T254
Test name
Test status
Simulation time 62398641 ps
CPU time 0.74 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 200148 kb
Host smart-153f743c-cb53-40da-8b4b-d4270b8bacdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623562480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1623562480
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3293156461
Short name T221
Test name
Test status
Simulation time 92035021 ps
CPU time 0.82 seconds
Started Jul 07 05:27:25 PM PDT 24
Finished Jul 07 05:27:27 PM PDT 24
Peak memory 199956 kb
Host smart-0ce2aa83-3601-4a3c-a92c-b214fb55a621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293156461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3293156461
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2196672126
Short name T32
Test name
Test status
Simulation time 1231040755 ps
CPU time 5.62 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 217788 kb
Host smart-00ba310c-bda1-4159-a5b9-61fd443233b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196672126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2196672126
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1520070827
Short name T313
Test name
Test status
Simulation time 244111711 ps
CPU time 1.13 seconds
Started Jul 07 05:27:21 PM PDT 24
Finished Jul 07 05:27:23 PM PDT 24
Peak memory 217540 kb
Host smart-fd6f673f-0bc3-49fb-9650-c51b835ebc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520070827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1520070827
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2679541648
Short name T18
Test name
Test status
Simulation time 113028070 ps
CPU time 0.76 seconds
Started Jul 07 05:27:37 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 199896 kb
Host smart-3feb55ab-22cd-43c6-8014-cff6ec73b104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679541648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2679541648
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.213949216
Short name T9
Test name
Test status
Simulation time 1139863630 ps
CPU time 5.41 seconds
Started Jul 07 05:27:26 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200340 kb
Host smart-5e3523f6-2dac-4d84-89fa-cc47d278bde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213949216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.213949216
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2097398785
Short name T437
Test name
Test status
Simulation time 99202169 ps
CPU time 1 seconds
Started Jul 07 05:27:23 PM PDT 24
Finished Jul 07 05:27:25 PM PDT 24
Peak memory 200000 kb
Host smart-872a27b6-c27f-4866-a94a-e678348ba4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097398785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2097398785
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3494723996
Short name T255
Test name
Test status
Simulation time 199329804 ps
CPU time 1.42 seconds
Started Jul 07 05:27:26 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 200272 kb
Host smart-66d1ff02-8539-461e-b5bd-1d2e1852cbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494723996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3494723996
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1133102805
Short name T279
Test name
Test status
Simulation time 7670759801 ps
CPU time 26.71 seconds
Started Jul 07 05:27:25 PM PDT 24
Finished Jul 07 05:27:53 PM PDT 24
Peak memory 208724 kb
Host smart-d7b431ad-d96c-47ea-bf33-d92939426fbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133102805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1133102805
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.362591646
Short name T486
Test name
Test status
Simulation time 276663705 ps
CPU time 1.95 seconds
Started Jul 07 05:27:24 PM PDT 24
Finished Jul 07 05:27:27 PM PDT 24
Peak memory 200080 kb
Host smart-655ee507-ab84-4c4b-9884-b5193a1db154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362591646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.362591646
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1788653923
Short name T263
Test name
Test status
Simulation time 83651577 ps
CPU time 0.84 seconds
Started Jul 07 05:27:26 PM PDT 24
Finished Jul 07 05:27:27 PM PDT 24
Peak memory 200156 kb
Host smart-8dd2d8a2-f34c-4928-893f-9355db7a103d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788653923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1788653923
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.465734703
Short name T309
Test name
Test status
Simulation time 66452775 ps
CPU time 0.78 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:30 PM PDT 24
Peak memory 199944 kb
Host smart-ab020e07-5af9-4978-b37c-682e2d1b79f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465734703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.465734703
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.695413904
Short name T41
Test name
Test status
Simulation time 1964082874 ps
CPU time 6.55 seconds
Started Jul 07 05:27:52 PM PDT 24
Finished Jul 07 05:27:59 PM PDT 24
Peak memory 217380 kb
Host smart-9643286a-eb89-48b4-ac48-5b44eaf17054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695413904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.695413904
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3895366275
Short name T190
Test name
Test status
Simulation time 179273710 ps
CPU time 0.91 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 199964 kb
Host smart-5e37e841-6fed-4e62-8e02-7567d10c335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895366275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3895366275
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3556331058
Short name T268
Test name
Test status
Simulation time 967831312 ps
CPU time 4.71 seconds
Started Jul 07 05:27:34 PM PDT 24
Finished Jul 07 05:27:41 PM PDT 24
Peak memory 200408 kb
Host smart-f50f0766-8a0f-466d-b8e0-78b5804c9774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556331058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3556331058
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3834293395
Short name T261
Test name
Test status
Simulation time 171940804 ps
CPU time 1.17 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200080 kb
Host smart-9aab4938-ea78-4937-839c-5f0fa9dab0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834293395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3834293395
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4046099715
Short name T285
Test name
Test status
Simulation time 189448853 ps
CPU time 1.37 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 200340 kb
Host smart-ca94850a-fb8f-4db2-9b72-e8bd63d860ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046099715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4046099715
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2558361324
Short name T286
Test name
Test status
Simulation time 5518206200 ps
CPU time 21.05 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:50 PM PDT 24
Peak memory 208652 kb
Host smart-f3cdc487-9146-4520-bf25-1f8b7d64e26b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558361324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2558361324
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.4206450265
Short name T46
Test name
Test status
Simulation time 124371061 ps
CPU time 1.58 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:30 PM PDT 24
Peak memory 200140 kb
Host smart-5f65021b-7f29-4559-875f-86be745c2ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206450265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.4206450265
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2983131313
Short name T290
Test name
Test status
Simulation time 145655547 ps
CPU time 1.22 seconds
Started Jul 07 05:27:25 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 200176 kb
Host smart-319195d1-3e1a-471a-92d2-c6860c07eb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983131313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2983131313
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3238635525
Short name T358
Test name
Test status
Simulation time 81151269 ps
CPU time 0.81 seconds
Started Jul 07 05:27:31 PM PDT 24
Finished Jul 07 05:27:35 PM PDT 24
Peak memory 199944 kb
Host smart-e3536599-9164-4338-b88e-fb82a98aa175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238635525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3238635525
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.954344774
Short name T27
Test name
Test status
Simulation time 1897218265 ps
CPU time 7.9 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:46 PM PDT 24
Peak memory 217612 kb
Host smart-b45febc1-94eb-4187-b96e-c6f2629615df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954344774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.954344774
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2032458511
Short name T226
Test name
Test status
Simulation time 244077602 ps
CPU time 1.1 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 217452 kb
Host smart-ab429eca-cc7f-4ae0-9366-35eef0d25a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032458511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2032458511
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2197669570
Short name T388
Test name
Test status
Simulation time 140774076 ps
CPU time 0.86 seconds
Started Jul 07 05:27:37 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 199964 kb
Host smart-1fba777a-260b-4256-81c3-bca48a351cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197669570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2197669570
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2604436417
Short name T89
Test name
Test status
Simulation time 780367315 ps
CPU time 3.91 seconds
Started Jul 07 05:27:23 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 200404 kb
Host smart-ca049a88-819f-49ba-bb65-5fb683c04aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604436417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2604436417
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3497685289
Short name T189
Test name
Test status
Simulation time 113159378 ps
CPU time 0.96 seconds
Started Jul 07 05:27:23 PM PDT 24
Finished Jul 07 05:27:24 PM PDT 24
Peak memory 200120 kb
Host smart-545c2960-1cd3-49b6-8c04-99654940a2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497685289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3497685289
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.884265303
Short name T10
Test name
Test status
Simulation time 236367775 ps
CPU time 1.54 seconds
Started Jul 07 05:27:19 PM PDT 24
Finished Jul 07 05:27:21 PM PDT 24
Peak memory 200352 kb
Host smart-301522ee-50ee-430f-a8d7-c1c7c0ad51da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884265303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.884265303
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.111030185
Short name T324
Test name
Test status
Simulation time 3791645666 ps
CPU time 13.26 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:44 PM PDT 24
Peak memory 200516 kb
Host smart-8a5f3afc-29f8-49c3-a24a-f1f55f5d7703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111030185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.111030185
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.4241850994
Short name T535
Test name
Test status
Simulation time 112902940 ps
CPU time 1.47 seconds
Started Jul 07 05:27:37 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 200108 kb
Host smart-3b66664a-2e3b-4a11-9300-ec9fc39653b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241850994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.4241850994
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2086780890
Short name T503
Test name
Test status
Simulation time 162732025 ps
CPU time 1.09 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:31 PM PDT 24
Peak memory 200088 kb
Host smart-556268ef-42eb-4e7a-a910-9da98251fe5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086780890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2086780890
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.4064780392
Short name T31
Test name
Test status
Simulation time 2171051302 ps
CPU time 8.55 seconds
Started Jul 07 05:27:21 PM PDT 24
Finished Jul 07 05:27:30 PM PDT 24
Peak memory 217860 kb
Host smart-ae6c1222-9130-4709-8d38-05b4f0ea1931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064780392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.4064780392
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.4047785725
Short name T271
Test name
Test status
Simulation time 243581512 ps
CPU time 1.05 seconds
Started Jul 07 05:27:38 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 217436 kb
Host smart-892ed95d-0f2f-45ca-9565-e65396b13c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047785725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.4047785725
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2862597607
Short name T341
Test name
Test status
Simulation time 179817629 ps
CPU time 0.86 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 199816 kb
Host smart-3f6b3360-8351-402d-91a5-520e9f52b709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862597607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2862597607
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3289128221
Short name T386
Test name
Test status
Simulation time 1070446153 ps
CPU time 4.72 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:37 PM PDT 24
Peak memory 200452 kb
Host smart-d2180f62-7827-46f3-89fb-9e8974be72cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289128221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3289128221
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2237005543
Short name T464
Test name
Test status
Simulation time 110315724 ps
CPU time 1 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 200008 kb
Host smart-5da82d55-0ecd-4b7a-a0f1-b7b9bfc855fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237005543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2237005543
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1311676565
Short name T209
Test name
Test status
Simulation time 197499156 ps
CPU time 1.46 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 200340 kb
Host smart-0b44187d-bfab-4e16-bf1f-08b5991fda6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311676565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1311676565
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1988803748
Short name T79
Test name
Test status
Simulation time 2025387729 ps
CPU time 7.57 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:43 PM PDT 24
Peak memory 200408 kb
Host smart-c6d21f8a-b45d-47ae-a31d-88553e35a843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988803748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1988803748
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.4107904730
Short name T444
Test name
Test status
Simulation time 424163526 ps
CPU time 2.44 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 208272 kb
Host smart-4cd3d64d-9fb2-4a04-b8f8-d4763c4c8fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107904730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4107904730
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1641551218
Short name T148
Test name
Test status
Simulation time 164317991 ps
CPU time 1.17 seconds
Started Jul 07 05:27:32 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 200156 kb
Host smart-12ee4660-9753-4dbb-a1e2-c88eb6d940da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641551218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1641551218
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4234070259
Short name T434
Test name
Test status
Simulation time 85397850 ps
CPU time 0.81 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:30 PM PDT 24
Peak memory 199908 kb
Host smart-104b2546-5d2d-4215-bf27-a9acb2493cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234070259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4234070259
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3230600456
Short name T407
Test name
Test status
Simulation time 1223841392 ps
CPU time 5.66 seconds
Started Jul 07 05:27:38 PM PDT 24
Finished Jul 07 05:27:45 PM PDT 24
Peak memory 221756 kb
Host smart-940cdca2-1038-4cbb-a87d-30430e7bfddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230600456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3230600456
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3423177679
Short name T217
Test name
Test status
Simulation time 245076403 ps
CPU time 1.04 seconds
Started Jul 07 05:27:52 PM PDT 24
Finished Jul 07 05:27:54 PM PDT 24
Peak memory 217508 kb
Host smart-5d0915e0-7150-4677-a88c-5f2c2ef045d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423177679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3423177679
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2598277878
Short name T19
Test name
Test status
Simulation time 114489593 ps
CPU time 0.77 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:38 PM PDT 24
Peak memory 199812 kb
Host smart-2ce6ee58-c7c7-475e-9a92-f2ac6ecc1870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598277878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2598277878
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.355979485
Short name T252
Test name
Test status
Simulation time 1357128510 ps
CPU time 5.18 seconds
Started Jul 07 05:27:34 PM PDT 24
Finished Jul 07 05:27:42 PM PDT 24
Peak memory 200232 kb
Host smart-6755dc98-6cbb-49f4-8be1-48aadbbc250b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355979485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.355979485
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.372768574
Short name T402
Test name
Test status
Simulation time 156859851 ps
CPU time 1.16 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:31 PM PDT 24
Peak memory 200140 kb
Host smart-83ba1f01-0ccf-4133-82f9-52e5d9504b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372768574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.372768574
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.4154848641
Short name T533
Test name
Test status
Simulation time 192416492 ps
CPU time 1.3 seconds
Started Jul 07 05:27:26 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 200116 kb
Host smart-bbb7a667-6e0c-45e4-ae11-864a194d0be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154848641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.4154848641
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1209789881
Short name T528
Test name
Test status
Simulation time 10943533919 ps
CPU time 40.74 seconds
Started Jul 07 05:27:24 PM PDT 24
Finished Jul 07 05:28:06 PM PDT 24
Peak memory 200480 kb
Host smart-d1416173-9bb9-4b6d-82c2-fa65b689a771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209789881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1209789881
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2318437586
Short name T214
Test name
Test status
Simulation time 313372250 ps
CPU time 2.14 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200128 kb
Host smart-228c32b3-292c-4b44-a8b8-70ea817036e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318437586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2318437586
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1900330969
Short name T204
Test name
Test status
Simulation time 73952484 ps
CPU time 0.84 seconds
Started Jul 07 05:27:31 PM PDT 24
Finished Jul 07 05:27:34 PM PDT 24
Peak memory 200156 kb
Host smart-b4b0ef1d-8612-4743-8080-1680c8598864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900330969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1900330969
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.128018137
Short name T394
Test name
Test status
Simulation time 60868484 ps
CPU time 0.72 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:38 PM PDT 24
Peak memory 199800 kb
Host smart-eafc41f9-2f41-43ba-8df5-3e72496a8849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128018137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.128018137
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2747452912
Short name T502
Test name
Test status
Simulation time 1219584165 ps
CPU time 5.17 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:37 PM PDT 24
Peak memory 221620 kb
Host smart-f1f11d25-c5b7-4175-a324-dbdc3242d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747452912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2747452912
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.657327532
Short name T385
Test name
Test status
Simulation time 245779004 ps
CPU time 1.04 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 217508 kb
Host smart-936e5505-6320-44dc-b9b6-7789c33777e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657327532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.657327532
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.120889195
Short name T157
Test name
Test status
Simulation time 95108102 ps
CPU time 0.76 seconds
Started Jul 07 05:27:31 PM PDT 24
Finished Jul 07 05:27:35 PM PDT 24
Peak memory 199892 kb
Host smart-8b689741-d7bc-4cb0-ad6d-0d07ffda4a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120889195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.120889195
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3261683571
Short name T489
Test name
Test status
Simulation time 1670925697 ps
CPU time 6.37 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:42 PM PDT 24
Peak memory 200404 kb
Host smart-cd43011c-5505-4610-ac34-22676bdc1799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261683571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3261683571
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.271593854
Short name T184
Test name
Test status
Simulation time 181522626 ps
CPU time 1.3 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200164 kb
Host smart-ab610dc9-e224-400e-9216-5d3ec61f8627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271593854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.271593854
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3915350628
Short name T293
Test name
Test status
Simulation time 113691109 ps
CPU time 1.15 seconds
Started Jul 07 05:27:23 PM PDT 24
Finished Jul 07 05:27:25 PM PDT 24
Peak memory 200288 kb
Host smart-809c9e48-6b97-49ee-8641-e80d100d0b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915350628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3915350628
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2995751704
Short name T339
Test name
Test status
Simulation time 8184383575 ps
CPU time 29.27 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:59 PM PDT 24
Peak memory 200468 kb
Host smart-cc7cf7bd-8a9c-41b2-a3e6-6cf736830a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995751704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2995751704
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1506689592
Short name T207
Test name
Test status
Simulation time 116914620 ps
CPU time 1.57 seconds
Started Jul 07 05:27:37 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 200136 kb
Host smart-34350e4f-2b20-4604-b84f-30962baa46e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506689592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1506689592
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.571221586
Short name T410
Test name
Test status
Simulation time 184750517 ps
CPU time 1.22 seconds
Started Jul 07 05:27:36 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 200072 kb
Host smart-82809aed-fc9e-4798-98ce-de70e7f6d349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571221586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.571221586
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3019757483
Short name T525
Test name
Test status
Simulation time 75694883 ps
CPU time 0.77 seconds
Started Jul 07 05:27:31 PM PDT 24
Finished Jul 07 05:27:34 PM PDT 24
Peak memory 199928 kb
Host smart-62ae6e7b-7a2f-4509-a689-68118030d239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019757483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3019757483
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2753111339
Short name T58
Test name
Test status
Simulation time 2356514720 ps
CPU time 8.97 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:45 PM PDT 24
Peak memory 221812 kb
Host smart-9d5be50a-ad97-4016-979c-127d3c19c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753111339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2753111339
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4040527539
Short name T232
Test name
Test status
Simulation time 245247744 ps
CPU time 1.03 seconds
Started Jul 07 05:27:46 PM PDT 24
Finished Jul 07 05:27:47 PM PDT 24
Peak memory 217400 kb
Host smart-15055c99-44f5-4813-9d0c-4a753924918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040527539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4040527539
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.443918050
Short name T466
Test name
Test status
Simulation time 166280714 ps
CPU time 0.91 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 199960 kb
Host smart-792dc0d1-c18c-4261-96b9-8a210e8600fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443918050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.443918050
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.4245216151
Short name T517
Test name
Test status
Simulation time 872321330 ps
CPU time 4.18 seconds
Started Jul 07 05:27:40 PM PDT 24
Finished Jul 07 05:27:45 PM PDT 24
Peak memory 200336 kb
Host smart-2fb73a73-b362-4596-811f-8bf75155b84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245216151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.4245216151
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1314558202
Short name T132
Test name
Test status
Simulation time 194444824 ps
CPU time 1.35 seconds
Started Jul 07 05:27:24 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 200192 kb
Host smart-38a7935d-e948-4cb6-835a-fba863f3148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314558202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1314558202
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1840490079
Short name T522
Test name
Test status
Simulation time 10068686611 ps
CPU time 33.17 seconds
Started Jul 07 05:27:24 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 208632 kb
Host smart-85d5995e-ba78-4e6e-918a-52262aac7b6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840490079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1840490079
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4075115374
Short name T439
Test name
Test status
Simulation time 490075846 ps
CPU time 2.45 seconds
Started Jul 07 05:27:31 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 200188 kb
Host smart-7be04020-e3dd-455b-8942-53627277b5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075115374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4075115374
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2895850833
Short name T485
Test name
Test status
Simulation time 110941372 ps
CPU time 1.02 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200124 kb
Host smart-272c7049-80ad-46f1-871a-2a7ba8bfb78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895850833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2895850833
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3289131853
Short name T227
Test name
Test status
Simulation time 76163522 ps
CPU time 0.83 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 199852 kb
Host smart-a09b2071-3333-4938-b831-ed41d8ae951b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289131853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3289131853
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.324281239
Short name T296
Test name
Test status
Simulation time 2342878246 ps
CPU time 8.93 seconds
Started Jul 07 05:27:23 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 221644 kb
Host smart-c45f5361-3b70-42c9-9a7a-46d671d6b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324281239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.324281239
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2308895814
Short name T411
Test name
Test status
Simulation time 243567015 ps
CPU time 1.16 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 217444 kb
Host smart-5cf53a6e-1b73-4894-8444-40c782a80732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308895814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2308895814
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3369594222
Short name T512
Test name
Test status
Simulation time 227625896 ps
CPU time 1.03 seconds
Started Jul 07 05:27:19 PM PDT 24
Finished Jul 07 05:27:20 PM PDT 24
Peak memory 199968 kb
Host smart-cfe0b415-a9fa-4dc3-aecd-d9e80842ac97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369594222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3369594222
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2696918795
Short name T282
Test name
Test status
Simulation time 858873453 ps
CPU time 4.17 seconds
Started Jul 07 05:27:19 PM PDT 24
Finished Jul 07 05:27:23 PM PDT 24
Peak memory 200488 kb
Host smart-939b768c-e72c-4edd-af4f-42a3a85df50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696918795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2696918795
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.378935737
Short name T37
Test name
Test status
Simulation time 8290352512 ps
CPU time 13.6 seconds
Started Jul 07 05:27:10 PM PDT 24
Finished Jul 07 05:27:24 PM PDT 24
Peak memory 217224 kb
Host smart-3ba764f5-26c2-4179-833a-ef08bd5d3fc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378935737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.378935737
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2811289863
Short name T397
Test name
Test status
Simulation time 94527224 ps
CPU time 1.05 seconds
Started Jul 07 05:27:13 PM PDT 24
Finished Jul 07 05:27:15 PM PDT 24
Peak memory 200156 kb
Host smart-b9dcdfde-04fa-4db5-81af-0f31d11546e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811289863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2811289863
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.807655644
Short name T374
Test name
Test status
Simulation time 117082419 ps
CPU time 1.2 seconds
Started Jul 07 05:27:11 PM PDT 24
Finished Jul 07 05:27:13 PM PDT 24
Peak memory 200368 kb
Host smart-11fc1f1a-c81f-45d1-9345-e7b3ee044c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807655644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.807655644
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3097645327
Short name T237
Test name
Test status
Simulation time 2056883231 ps
CPU time 8.32 seconds
Started Jul 07 05:27:17 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 200508 kb
Host smart-d01724b3-c52b-483c-9244-92308ed59440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097645327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3097645327
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1153165500
Short name T334
Test name
Test status
Simulation time 129867652 ps
CPU time 1.68 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:24 PM PDT 24
Peak memory 200152 kb
Host smart-4557de0b-65ba-45b1-878d-3cc53a6150e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153165500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1153165500
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.880741551
Short name T230
Test name
Test status
Simulation time 85731024 ps
CPU time 0.86 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:23 PM PDT 24
Peak memory 200152 kb
Host smart-1c84223f-57b0-4eb0-9ce2-ab2f28fd5ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880741551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.880741551
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2889627979
Short name T191
Test name
Test status
Simulation time 72319689 ps
CPU time 0.74 seconds
Started Jul 07 05:27:32 PM PDT 24
Finished Jul 07 05:27:35 PM PDT 24
Peak memory 199860 kb
Host smart-f68a9ae5-9ac4-4134-953c-1186208d7dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889627979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2889627979
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1098967437
Short name T216
Test name
Test status
Simulation time 2172930485 ps
CPU time 7.57 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:35 PM PDT 24
Peak memory 217648 kb
Host smart-909b9ecc-5c42-44aa-915a-39140019ae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098967437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1098967437
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3814233708
Short name T156
Test name
Test status
Simulation time 245039368 ps
CPU time 1.03 seconds
Started Jul 07 05:27:38 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 217392 kb
Host smart-cf5f0716-777f-435f-8e87-5f9828bc96d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814233708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3814233708
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.697476703
Short name T167
Test name
Test status
Simulation time 234834027 ps
CPU time 0.93 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 199952 kb
Host smart-c9f93c07-4aed-4032-8528-3cfb07bfa577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697476703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.697476703
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.279462955
Short name T220
Test name
Test status
Simulation time 963957040 ps
CPU time 4.74 seconds
Started Jul 07 05:27:43 PM PDT 24
Finished Jul 07 05:27:48 PM PDT 24
Peak memory 200352 kb
Host smart-fd7a62e6-ac2a-44ca-960b-cbfa7964ef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279462955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.279462955
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.867775284
Short name T289
Test name
Test status
Simulation time 97397905 ps
CPU time 1.06 seconds
Started Jul 07 05:27:32 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 200156 kb
Host smart-9ee60e45-a076-4b44-9039-d6d33df750ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867775284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.867775284
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1054356168
Short name T248
Test name
Test status
Simulation time 117031462 ps
CPU time 1.12 seconds
Started Jul 07 05:27:50 PM PDT 24
Finished Jul 07 05:27:51 PM PDT 24
Peak memory 200248 kb
Host smart-b567b083-1676-41a8-8563-7a7454d3c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054356168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1054356168
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.710744013
Short name T117
Test name
Test status
Simulation time 8227339479 ps
CPU time 31.69 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:28:03 PM PDT 24
Peak memory 200576 kb
Host smart-bd18b900-f76e-4edc-a9dd-124a485ef946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710744013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.710744013
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.345575082
Short name T321
Test name
Test status
Simulation time 349275728 ps
CPU time 2.34 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 200196 kb
Host smart-c62ed751-3270-4c01-9c59-38900f50fc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345575082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.345575082
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.4285959064
Short name T470
Test name
Test status
Simulation time 247069509 ps
CPU time 1.34 seconds
Started Jul 07 05:27:34 PM PDT 24
Finished Jul 07 05:27:37 PM PDT 24
Peak memory 200152 kb
Host smart-bf17b7f1-2dd0-420c-8927-d91d8220a591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285959064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.4285959064
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3095054919
Short name T223
Test name
Test status
Simulation time 102120359 ps
CPU time 0.82 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 199952 kb
Host smart-838fa579-ebd8-46fc-83fa-abfa2f0636ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095054919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3095054919
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1436621748
Short name T251
Test name
Test status
Simulation time 1222038672 ps
CPU time 5.76 seconds
Started Jul 07 05:27:40 PM PDT 24
Finished Jul 07 05:27:46 PM PDT 24
Peak memory 217744 kb
Host smart-2e572825-9930-42f4-87c0-fb6ff01b8e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436621748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1436621748
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3958558065
Short name T174
Test name
Test status
Simulation time 246118395 ps
CPU time 1.07 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 217440 kb
Host smart-fdf9def9-e44c-4200-9c61-4ae93826f0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958558065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3958558065
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1515861941
Short name T347
Test name
Test status
Simulation time 83901126 ps
CPU time 0.76 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:38 PM PDT 24
Peak memory 199900 kb
Host smart-ebbf2f0d-396a-49c6-9552-9ac38ce82f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515861941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1515861941
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3615788028
Short name T493
Test name
Test status
Simulation time 745587176 ps
CPU time 3.86 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 200436 kb
Host smart-f01aa731-e24b-42ed-8c08-e55f6c1c93f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615788028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3615788028
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2941556277
Short name T310
Test name
Test status
Simulation time 110411115 ps
CPU time 1.03 seconds
Started Jul 07 05:27:36 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 200128 kb
Host smart-3e24a545-d3f9-4c16-8db2-32a426010ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941556277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2941556277
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1524990851
Short name T380
Test name
Test status
Simulation time 224237916 ps
CPU time 1.44 seconds
Started Jul 07 05:27:31 PM PDT 24
Finished Jul 07 05:27:35 PM PDT 24
Peak memory 200340 kb
Host smart-503a4a26-20a2-4912-a991-2104d4d80558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524990851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1524990851
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.4185210920
Short name T258
Test name
Test status
Simulation time 5626331383 ps
CPU time 20.08 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:49 PM PDT 24
Peak memory 200520 kb
Host smart-dfab15e0-0c63-451a-9d6b-54d927873543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185210920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.4185210920
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3560972969
Short name T315
Test name
Test status
Simulation time 130870546 ps
CPU time 1.65 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:37 PM PDT 24
Peak memory 200128 kb
Host smart-a0d81029-6036-4bae-9161-641553f38f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560972969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3560972969
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2645709413
Short name T128
Test name
Test status
Simulation time 128400203 ps
CPU time 1.06 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 199992 kb
Host smart-ffdf473e-6500-4693-ae4b-aa65650d640d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645709413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2645709413
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3733566308
Short name T50
Test name
Test status
Simulation time 71287809 ps
CPU time 0.77 seconds
Started Jul 07 05:27:38 PM PDT 24
Finished Jul 07 05:27:41 PM PDT 24
Peak memory 199764 kb
Host smart-c26700ea-3b49-4347-9a50-38b2649d6a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733566308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3733566308
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3959429150
Short name T30
Test name
Test status
Simulation time 1887376905 ps
CPU time 6.86 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 217620 kb
Host smart-757ad265-c3f0-4aa3-b80d-606a9622377c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959429150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3959429150
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1052532104
Short name T173
Test name
Test status
Simulation time 244161324 ps
CPU time 1.07 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 217536 kb
Host smart-a1361c75-cab4-412e-904b-11717730c3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052532104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1052532104
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.706681177
Short name T8
Test name
Test status
Simulation time 87866887 ps
CPU time 0.73 seconds
Started Jul 07 05:27:34 PM PDT 24
Finished Jul 07 05:27:37 PM PDT 24
Peak memory 199940 kb
Host smart-f53ac014-d8de-4919-954b-74024df1f26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706681177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.706681177
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.500727906
Short name T432
Test name
Test status
Simulation time 1406380678 ps
CPU time 5.66 seconds
Started Jul 07 05:27:34 PM PDT 24
Finished Jul 07 05:27:43 PM PDT 24
Peak memory 200368 kb
Host smart-8d1b6f4f-2dd7-4714-9a0b-b3af4a13590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500727906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.500727906
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3485535167
Short name T422
Test name
Test status
Simulation time 113149830 ps
CPU time 1.04 seconds
Started Jul 07 05:27:39 PM PDT 24
Finished Jul 07 05:27:41 PM PDT 24
Peak memory 200116 kb
Host smart-4008a121-f136-42c0-b450-3e7e3f69b2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485535167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3485535167
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2335219936
Short name T312
Test name
Test status
Simulation time 204199770 ps
CPU time 1.51 seconds
Started Jul 07 05:27:36 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 200344 kb
Host smart-728178d4-e01c-4d82-8126-05f28d316694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335219936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2335219936
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3711001087
Short name T78
Test name
Test status
Simulation time 8804984166 ps
CPU time 29.67 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:28:05 PM PDT 24
Peak memory 200576 kb
Host smart-02d01416-8e13-4843-a14a-b04e4406758d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711001087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3711001087
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2336273203
Short name T259
Test name
Test status
Simulation time 131822428 ps
CPU time 1.61 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 200148 kb
Host smart-d979a9d4-2bf3-42f5-b9c5-e5bc2a70d0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336273203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2336273203
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3635909727
Short name T275
Test name
Test status
Simulation time 171947366 ps
CPU time 1.44 seconds
Started Jul 07 05:27:23 PM PDT 24
Finished Jul 07 05:27:25 PM PDT 24
Peak memory 200688 kb
Host smart-7b499cb9-1d62-4ea6-8d01-01ff106365bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635909727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3635909727
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3965793791
Short name T131
Test name
Test status
Simulation time 93499206 ps
CPU time 0.85 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 199952 kb
Host smart-49a37628-ed9c-403c-bfe6-693efab8456b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965793791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3965793791
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2486254132
Short name T299
Test name
Test status
Simulation time 1216667776 ps
CPU time 5.55 seconds
Started Jul 07 05:27:37 PM PDT 24
Finished Jul 07 05:27:44 PM PDT 24
Peak memory 217708 kb
Host smart-5bb0f94a-05e4-4738-b284-83fb75073b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486254132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2486254132
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3462854376
Short name T253
Test name
Test status
Simulation time 244861271 ps
CPU time 1.03 seconds
Started Jul 07 05:27:31 PM PDT 24
Finished Jul 07 05:27:34 PM PDT 24
Peak memory 217512 kb
Host smart-3b916bf6-22c1-4d1d-b0bf-cd6d2668650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462854376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3462854376
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1666655719
Short name T463
Test name
Test status
Simulation time 73485888 ps
CPU time 0.69 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 199960 kb
Host smart-fbfbbe88-e885-4e29-a0a6-8952a61849b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666655719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1666655719
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2160781588
Short name T97
Test name
Test status
Simulation time 2071874372 ps
CPU time 7.27 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:45 PM PDT 24
Peak memory 200384 kb
Host smart-bb278aca-59bd-44cf-a35e-7b42614ca604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160781588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2160781588
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3481395471
Short name T355
Test name
Test status
Simulation time 170857565 ps
CPU time 1.13 seconds
Started Jul 07 05:27:43 PM PDT 24
Finished Jul 07 05:27:45 PM PDT 24
Peak memory 200132 kb
Host smart-7985eaef-c61a-40ae-816c-d01fb244a6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481395471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3481395471
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1759055808
Short name T399
Test name
Test status
Simulation time 109122744 ps
CPU time 1.17 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 200624 kb
Host smart-c2a16c52-629a-419f-a68f-4ac06b39cb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759055808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1759055808
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.4199648489
Short name T95
Test name
Test status
Simulation time 5689736527 ps
CPU time 26.48 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:59 PM PDT 24
Peak memory 208664 kb
Host smart-1f5ad684-2d28-4a66-83aa-d507ce80bf8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199648489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.4199648489
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.253379416
Short name T478
Test name
Test status
Simulation time 106910582 ps
CPU time 0.97 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:30 PM PDT 24
Peak memory 200160 kb
Host smart-860385d3-5d77-4d1a-bf4b-bbf73205e459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253379416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.253379416
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.346943778
Short name T449
Test name
Test status
Simulation time 72994897 ps
CPU time 0.82 seconds
Started Jul 07 05:27:36 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 199904 kb
Host smart-8ae18d12-feae-4fc0-a19e-528a156591c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346943778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.346943778
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2032786001
Short name T273
Test name
Test status
Simulation time 1220876190 ps
CPU time 5.5 seconds
Started Jul 07 05:27:44 PM PDT 24
Finished Jul 07 05:27:50 PM PDT 24
Peak memory 217756 kb
Host smart-478c9f08-e5fb-41b9-a93f-2a40716b0c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032786001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2032786001
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.381968016
Short name T224
Test name
Test status
Simulation time 244745566 ps
CPU time 1.05 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 217512 kb
Host smart-dcb3a7dc-299a-4c09-9315-fe1d10b68cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381968016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.381968016
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1272757720
Short name T391
Test name
Test status
Simulation time 97280818 ps
CPU time 0.8 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 199964 kb
Host smart-c0f79608-7e3c-4132-8ad9-8d28707c2c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272757720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1272757720
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3163329270
Short name T93
Test name
Test status
Simulation time 811834294 ps
CPU time 3.76 seconds
Started Jul 07 05:27:34 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 200416 kb
Host smart-52a4b28f-4cd4-40a9-b2e3-2d19f350b56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163329270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3163329270
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1965639020
Short name T139
Test name
Test status
Simulation time 177533406 ps
CPU time 1.29 seconds
Started Jul 07 05:27:34 PM PDT 24
Finished Jul 07 05:27:38 PM PDT 24
Peak memory 200168 kb
Host smart-4020847c-78e5-44a5-a259-cb3d37fbfa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965639020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1965639020
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2007088062
Short name T63
Test name
Test status
Simulation time 205455575 ps
CPU time 1.32 seconds
Started Jul 07 05:27:32 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 200360 kb
Host smart-46a6109d-bb9e-4f95-a3a9-9fb010c28985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007088062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2007088062
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.330612649
Short name T118
Test name
Test status
Simulation time 9640906276 ps
CPU time 31.46 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:28:03 PM PDT 24
Peak memory 200396 kb
Host smart-93f61fdc-9a2a-47af-83ce-0e327bb258ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330612649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.330612649
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2394070512
Short name T257
Test name
Test status
Simulation time 148522587 ps
CPU time 1.85 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:37 PM PDT 24
Peak memory 200156 kb
Host smart-f191ad82-0159-4035-8bbb-306205c091c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394070512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2394070512
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2179199148
Short name T330
Test name
Test status
Simulation time 73492045 ps
CPU time 0.83 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 199872 kb
Host smart-ea30b9a8-af96-4435-b766-0589dc1c58b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179199148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2179199148
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1024235503
Short name T389
Test name
Test status
Simulation time 1897288348 ps
CPU time 7.48 seconds
Started Jul 07 05:27:48 PM PDT 24
Finished Jul 07 05:27:56 PM PDT 24
Peak memory 221776 kb
Host smart-5844c3ad-049f-4780-a091-e697bdadbeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024235503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1024235503
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3951695753
Short name T130
Test name
Test status
Simulation time 243858512 ps
CPU time 1.1 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 217460 kb
Host smart-08144f5e-ddbc-4ab4-a81b-717bf0f6129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951695753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3951695753
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1175942518
Short name T168
Test name
Test status
Simulation time 125022524 ps
CPU time 0.82 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:38 PM PDT 24
Peak memory 199896 kb
Host smart-640558ed-155d-46fa-bab4-7fb31c0ea103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175942518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1175942518
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.355281416
Short name T480
Test name
Test status
Simulation time 1359258362 ps
CPU time 5.03 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 200356 kb
Host smart-35402a64-4be3-4e95-beff-e654c12a625e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355281416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.355281416
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3018899014
Short name T534
Test name
Test status
Simulation time 100401684 ps
CPU time 1 seconds
Started Jul 07 05:27:44 PM PDT 24
Finished Jul 07 05:27:46 PM PDT 24
Peak memory 200168 kb
Host smart-b5874f99-c7ec-45a9-a914-5a4ac5c413b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018899014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3018899014
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3178069295
Short name T446
Test name
Test status
Simulation time 129032112 ps
CPU time 1.16 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 200272 kb
Host smart-eea66969-5483-47de-a437-59a5789b39ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178069295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3178069295
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3110780808
Short name T98
Test name
Test status
Simulation time 2814347067 ps
CPU time 13.29 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:51 PM PDT 24
Peak memory 209656 kb
Host smart-0b0df904-8aaa-4922-804a-f9d0469d2497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110780808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3110780808
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2869113879
Short name T80
Test name
Test status
Simulation time 151650594 ps
CPU time 1.81 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200140 kb
Host smart-0862f40b-e70a-4b4b-bcde-8daee82ee94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869113879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2869113879
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.196837468
Short name T501
Test name
Test status
Simulation time 130738570 ps
CPU time 1.01 seconds
Started Jul 07 05:27:32 PM PDT 24
Finished Jul 07 05:27:35 PM PDT 24
Peak memory 200144 kb
Host smart-f781d387-8cb6-45f6-acd7-8767b74c6085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196837468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.196837468
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.760401831
Short name T247
Test name
Test status
Simulation time 77820973 ps
CPU time 0.81 seconds
Started Jul 07 05:27:34 PM PDT 24
Finished Jul 07 05:27:37 PM PDT 24
Peak memory 199924 kb
Host smart-348222ff-5153-4da4-87ed-841552a488b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760401831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.760401831
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1154315356
Short name T506
Test name
Test status
Simulation time 1893620502 ps
CPU time 6.73 seconds
Started Jul 07 05:27:46 PM PDT 24
Finished Jul 07 05:27:54 PM PDT 24
Peak memory 217408 kb
Host smart-26ec91ba-aebc-4a3a-9853-7aad777e5e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154315356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1154315356
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1978159335
Short name T179
Test name
Test status
Simulation time 243863435 ps
CPU time 1.05 seconds
Started Jul 07 05:27:32 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 217520 kb
Host smart-e6ff8ac1-ea7e-4d92-b9c5-bf6515348da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978159335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1978159335
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2854865957
Short name T176
Test name
Test status
Simulation time 159153737 ps
CPU time 0.84 seconds
Started Jul 07 05:27:40 PM PDT 24
Finished Jul 07 05:27:41 PM PDT 24
Peak memory 199984 kb
Host smart-dfb21332-4c98-4e08-9aeb-690e6d13d9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854865957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2854865957
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1760260288
Short name T281
Test name
Test status
Simulation time 1601286753 ps
CPU time 6.46 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:44 PM PDT 24
Peak memory 200352 kb
Host smart-1d191553-aa53-4085-8701-2132230c7fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760260288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1760260288
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3311490852
Short name T340
Test name
Test status
Simulation time 99486188 ps
CPU time 1.04 seconds
Started Jul 07 05:27:31 PM PDT 24
Finished Jul 07 05:27:34 PM PDT 24
Peak memory 200152 kb
Host smart-99c7eb0d-401a-472d-bbbb-a16ed38ff25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311490852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3311490852
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3989857531
Short name T170
Test name
Test status
Simulation time 240662405 ps
CPU time 1.51 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200352 kb
Host smart-a7577ec3-03be-449c-b089-23c5522f0d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989857531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3989857531
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2019937338
Short name T381
Test name
Test status
Simulation time 132576046 ps
CPU time 1.07 seconds
Started Jul 07 05:27:39 PM PDT 24
Finished Jul 07 05:27:41 PM PDT 24
Peak memory 199940 kb
Host smart-96f66d23-de82-430d-9db0-73d2ef813722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019937338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2019937338
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2723558891
Short name T277
Test name
Test status
Simulation time 308901657 ps
CPU time 1.92 seconds
Started Jul 07 05:27:37 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 208404 kb
Host smart-85848bb3-3b76-4c52-b22d-3db8bed207cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723558891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2723558891
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.253223866
Short name T468
Test name
Test status
Simulation time 157779689 ps
CPU time 1.25 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200368 kb
Host smart-01f8e4d1-d4c7-4fb6-ae5f-69119b0bc1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253223866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.253223866
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1019480699
Short name T201
Test name
Test status
Simulation time 60608206 ps
CPU time 0.73 seconds
Started Jul 07 05:27:34 PM PDT 24
Finished Jul 07 05:27:37 PM PDT 24
Peak memory 199948 kb
Host smart-6a64fd6d-b2a7-4366-b8b1-6f51d0bead06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019480699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1019480699
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1587519981
Short name T350
Test name
Test status
Simulation time 1229587290 ps
CPU time 5.24 seconds
Started Jul 07 05:27:45 PM PDT 24
Finished Jul 07 05:27:51 PM PDT 24
Peak memory 217536 kb
Host smart-b4c159db-d248-446f-ae79-40c17f52dc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587519981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1587519981
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.4029984504
Short name T43
Test name
Test status
Simulation time 243815807 ps
CPU time 1.1 seconds
Started Jul 07 05:27:45 PM PDT 24
Finished Jul 07 05:27:47 PM PDT 24
Peak memory 217440 kb
Host smart-58fa24f2-b125-4eab-971e-77792785b3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029984504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.4029984504
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.4187233107
Short name T448
Test name
Test status
Simulation time 231333524 ps
CPU time 0.91 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 199972 kb
Host smart-3fdbfd90-2920-4489-80c1-e13d1c17b4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187233107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.4187233107
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2974586979
Short name T222
Test name
Test status
Simulation time 902950991 ps
CPU time 4.46 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 200400 kb
Host smart-4ced6ab5-b12a-43e4-80d7-9a316f8a7ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974586979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2974586979
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3704704425
Short name T363
Test name
Test status
Simulation time 147071772 ps
CPU time 1.12 seconds
Started Jul 07 05:27:37 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 200156 kb
Host smart-a27ae3e5-3bd5-4d58-96b5-de7f7a8b9f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704704425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3704704425
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.4289565252
Short name T62
Test name
Test status
Simulation time 234700856 ps
CPU time 1.44 seconds
Started Jul 07 05:27:47 PM PDT 24
Finished Jul 07 05:27:49 PM PDT 24
Peak memory 200340 kb
Host smart-31893e81-4351-4775-a09b-68a1950a1b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289565252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.4289565252
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.326549602
Short name T509
Test name
Test status
Simulation time 8432224962 ps
CPU time 30.94 seconds
Started Jul 07 05:27:47 PM PDT 24
Finished Jul 07 05:28:19 PM PDT 24
Peak memory 208664 kb
Host smart-38e9c89a-b83e-4ae2-9798-1dac8d189f41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326549602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.326549602
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3071766412
Short name T45
Test name
Test status
Simulation time 516573769 ps
CPU time 2.9 seconds
Started Jul 07 05:27:41 PM PDT 24
Finished Jul 07 05:27:44 PM PDT 24
Peak memory 200032 kb
Host smart-342db519-9390-426a-82e9-fdece8022bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071766412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3071766412
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1300002915
Short name T403
Test name
Test status
Simulation time 182992406 ps
CPU time 1.15 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 200160 kb
Host smart-e5727c30-0a33-4cc7-a5d6-a2dc150e7999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300002915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1300002915
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3415183560
Short name T288
Test name
Test status
Simulation time 66358802 ps
CPU time 0.81 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:27:38 PM PDT 24
Peak memory 199716 kb
Host smart-699abee3-6993-4d92-9148-ee3412ded6d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415183560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3415183560
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.942955490
Short name T371
Test name
Test status
Simulation time 243905992 ps
CPU time 1.04 seconds
Started Jul 07 05:27:38 PM PDT 24
Finished Jul 07 05:27:44 PM PDT 24
Peak memory 217484 kb
Host smart-feceb2d5-41b0-4068-a5b4-8d89f0d024dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942955490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.942955490
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1508281350
Short name T333
Test name
Test status
Simulation time 121995937 ps
CPU time 0.81 seconds
Started Jul 07 05:27:49 PM PDT 24
Finished Jul 07 05:27:50 PM PDT 24
Peak memory 199964 kb
Host smart-2a1247ad-825e-463f-8862-ecb42f57df00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508281350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1508281350
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3397733521
Short name T332
Test name
Test status
Simulation time 1172541494 ps
CPU time 5.17 seconds
Started Jul 07 05:27:40 PM PDT 24
Finished Jul 07 05:27:46 PM PDT 24
Peak memory 200340 kb
Host smart-3f8cc826-e9e9-41ee-bec3-dc123a1a1be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397733521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3397733521
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3998587586
Short name T4
Test name
Test status
Simulation time 111740847 ps
CPU time 1.01 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200120 kb
Host smart-106148ea-6364-4787-bf4f-6538608fbe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998587586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3998587586
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.735089903
Short name T398
Test name
Test status
Simulation time 258454938 ps
CPU time 1.63 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 200352 kb
Host smart-0fec8af7-c86e-424a-81b9-428eda61924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735089903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.735089903
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3911138812
Short name T94
Test name
Test status
Simulation time 3071921850 ps
CPU time 15.28 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:48 PM PDT 24
Peak memory 209980 kb
Host smart-dca74d70-092e-4aba-a78d-d79d2f8e54cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911138812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3911138812
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1426992364
Short name T382
Test name
Test status
Simulation time 313537287 ps
CPU time 2.08 seconds
Started Jul 07 05:27:45 PM PDT 24
Finished Jul 07 05:27:47 PM PDT 24
Peak memory 208096 kb
Host smart-2c7493c0-702f-49fe-a8bb-8802c92b9320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426992364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1426992364
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3278394370
Short name T211
Test name
Test status
Simulation time 228692728 ps
CPU time 1.38 seconds
Started Jul 07 05:27:45 PM PDT 24
Finished Jul 07 05:27:47 PM PDT 24
Peak memory 200120 kb
Host smart-002f4672-ba13-4e5d-87c6-a445d1e16061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278394370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3278394370
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1209545347
Short name T482
Test name
Test status
Simulation time 61444703 ps
CPU time 0.71 seconds
Started Jul 07 05:27:38 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 199952 kb
Host smart-e004a4cf-9c0d-4b90-a003-ae8f2b3c887b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209545347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1209545347
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3862043083
Short name T492
Test name
Test status
Simulation time 1896176732 ps
CPU time 6.95 seconds
Started Jul 07 05:27:34 PM PDT 24
Finished Jul 07 05:27:44 PM PDT 24
Peak memory 217812 kb
Host smart-e0f5d859-21a3-4dd6-9db3-1df4e7f3bd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862043083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3862043083
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2514985527
Short name T2
Test name
Test status
Simulation time 243694495 ps
CPU time 1.05 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 217544 kb
Host smart-64679cbd-9385-4486-8f77-227d919348c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514985527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2514985527
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1137904551
Short name T178
Test name
Test status
Simulation time 137455458 ps
CPU time 0.84 seconds
Started Jul 07 05:27:46 PM PDT 24
Finished Jul 07 05:27:47 PM PDT 24
Peak memory 199976 kb
Host smart-f84c8be6-cd23-49b8-9efc-ff30d3543b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137904551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1137904551
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3688781846
Short name T265
Test name
Test status
Simulation time 1807505235 ps
CPU time 6.76 seconds
Started Jul 07 05:27:34 PM PDT 24
Finished Jul 07 05:27:44 PM PDT 24
Peak memory 200416 kb
Host smart-79a5e287-b7c1-4fc7-b4b5-df063c6912b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688781846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3688781846
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4030387485
Short name T276
Test name
Test status
Simulation time 164236097 ps
CPU time 1.12 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:34 PM PDT 24
Peak memory 200192 kb
Host smart-438b438f-543a-4834-b66a-dadb030a43fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030387485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4030387485
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2035514738
Short name T329
Test name
Test status
Simulation time 264276445 ps
CPU time 1.6 seconds
Started Jul 07 05:27:44 PM PDT 24
Finished Jul 07 05:27:46 PM PDT 24
Peak memory 200340 kb
Host smart-fd906096-e5b1-4f50-887b-2ceb53d2e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035514738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2035514738
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3436258366
Short name T496
Test name
Test status
Simulation time 7025754535 ps
CPU time 23.84 seconds
Started Jul 07 05:27:32 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 208720 kb
Host smart-a530845e-78a5-4697-9bc8-e9af38e0d220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436258366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3436258366
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2365227447
Short name T297
Test name
Test status
Simulation time 345491078 ps
CPU time 2.25 seconds
Started Jul 07 05:27:38 PM PDT 24
Finished Jul 07 05:27:42 PM PDT 24
Peak memory 200216 kb
Host smart-8af1296f-3157-4303-8dfe-fc741236c988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365227447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2365227447
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2720171511
Short name T287
Test name
Test status
Simulation time 246832485 ps
CPU time 1.53 seconds
Started Jul 07 05:27:42 PM PDT 24
Finished Jul 07 05:27:44 PM PDT 24
Peak memory 200416 kb
Host smart-0fa1903d-5d8a-4bea-8fc4-41934279830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720171511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2720171511
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.4108684028
Short name T74
Test name
Test status
Simulation time 68529082 ps
CPU time 0.81 seconds
Started Jul 07 05:27:19 PM PDT 24
Finished Jul 07 05:27:21 PM PDT 24
Peak memory 199908 kb
Host smart-8e9422f7-30aa-42dc-bbaf-5b38505f9ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108684028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.4108684028
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3885402372
Short name T42
Test name
Test status
Simulation time 1904872952 ps
CPU time 7.03 seconds
Started Jul 07 05:27:06 PM PDT 24
Finished Jul 07 05:27:13 PM PDT 24
Peak memory 217748 kb
Host smart-ddb806e1-c517-4dce-b548-1814eace0311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885402372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3885402372
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.507703985
Short name T474
Test name
Test status
Simulation time 244531329 ps
CPU time 1.09 seconds
Started Jul 07 05:27:11 PM PDT 24
Finished Jul 07 05:27:13 PM PDT 24
Peak memory 217544 kb
Host smart-61956d48-7147-4e11-a6e4-8fe616fa4d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507703985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.507703985
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2983919590
Short name T171
Test name
Test status
Simulation time 163953745 ps
CPU time 0.88 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:24 PM PDT 24
Peak memory 199948 kb
Host smart-f89ec7a7-dda8-45ef-af52-08e9c30b48ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983919590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2983919590
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3917251333
Short name T373
Test name
Test status
Simulation time 1126333201 ps
CPU time 4.6 seconds
Started Jul 07 05:27:17 PM PDT 24
Finished Jul 07 05:27:22 PM PDT 24
Peak memory 200404 kb
Host smart-86eb73f6-a521-4d6d-ac16-0cf16d4b65c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917251333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3917251333
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2031541008
Short name T181
Test name
Test status
Simulation time 147536374 ps
CPU time 1.19 seconds
Started Jul 07 05:27:14 PM PDT 24
Finished Jul 07 05:27:16 PM PDT 24
Peak memory 200152 kb
Host smart-141f4902-3660-4bf8-9a53-a73be09861b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031541008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2031541008
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2475823153
Short name T306
Test name
Test status
Simulation time 115571621 ps
CPU time 1.22 seconds
Started Jul 07 05:27:07 PM PDT 24
Finished Jul 07 05:27:09 PM PDT 24
Peak memory 200284 kb
Host smart-ce1900e9-22eb-471c-a06d-0387c590121b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475823153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2475823153
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2861291142
Short name T99
Test name
Test status
Simulation time 1734618998 ps
CPU time 8.75 seconds
Started Jul 07 05:27:07 PM PDT 24
Finished Jul 07 05:27:16 PM PDT 24
Peak memory 200308 kb
Host smart-01a45411-cc22-492b-ba3f-e4cbb9635ef2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861291142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2861291142
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.108797795
Short name T49
Test name
Test status
Simulation time 347243073 ps
CPU time 2.22 seconds
Started Jul 07 05:27:19 PM PDT 24
Finished Jul 07 05:27:22 PM PDT 24
Peak memory 199972 kb
Host smart-6d54e7b1-39f5-45a5-9806-f340c8add7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108797795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.108797795
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3658943516
Short name T508
Test name
Test status
Simulation time 243332670 ps
CPU time 1.53 seconds
Started Jul 07 05:27:15 PM PDT 24
Finished Jul 07 05:27:17 PM PDT 24
Peak memory 200352 kb
Host smart-10afb072-8d51-48e8-abd0-9f2384d6ae2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658943516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3658943516
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3731976844
Short name T145
Test name
Test status
Simulation time 54286691 ps
CPU time 0.71 seconds
Started Jul 07 05:27:53 PM PDT 24
Finished Jul 07 05:27:54 PM PDT 24
Peak memory 199952 kb
Host smart-e668e861-f0cd-49b1-be19-6642a15401ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731976844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3731976844
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2859836961
Short name T250
Test name
Test status
Simulation time 1217417962 ps
CPU time 6.12 seconds
Started Jul 07 05:27:45 PM PDT 24
Finished Jul 07 05:27:52 PM PDT 24
Peak memory 217584 kb
Host smart-e6c327c2-aa16-444b-b72d-0136b0e05394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859836961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2859836961
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3447450166
Short name T387
Test name
Test status
Simulation time 243653011 ps
CPU time 1.09 seconds
Started Jul 07 05:27:54 PM PDT 24
Finished Jul 07 05:27:55 PM PDT 24
Peak memory 217552 kb
Host smart-b16e5c1e-2716-4329-99ed-7e9d8a70b2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447450166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3447450166
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.958022691
Short name T536
Test name
Test status
Simulation time 103066430 ps
CPU time 0.76 seconds
Started Jul 07 05:27:31 PM PDT 24
Finished Jul 07 05:27:35 PM PDT 24
Peak memory 199960 kb
Host smart-01f69c88-2024-43cd-b914-dbc2b531ccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958022691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.958022691
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2995027588
Short name T307
Test name
Test status
Simulation time 1605252606 ps
CPU time 6.36 seconds
Started Jul 07 05:27:39 PM PDT 24
Finished Jul 07 05:27:47 PM PDT 24
Peak memory 200384 kb
Host smart-a7d4809b-a74a-4409-9cb3-8d587737d2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995027588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2995027588
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3783765177
Short name T491
Test name
Test status
Simulation time 146041107 ps
CPU time 1.09 seconds
Started Jul 07 05:27:43 PM PDT 24
Finished Jul 07 05:27:44 PM PDT 24
Peak memory 200140 kb
Host smart-75360c8e-9176-4858-b1e8-af11ed3b2d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783765177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3783765177
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3504899247
Short name T351
Test name
Test status
Simulation time 112616694 ps
CPU time 1.17 seconds
Started Jul 07 05:27:42 PM PDT 24
Finished Jul 07 05:27:43 PM PDT 24
Peak memory 200340 kb
Host smart-f7e45996-7bfb-4509-9144-50d9d72f5513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504899247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3504899247
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2049444315
Short name T242
Test name
Test status
Simulation time 364690821 ps
CPU time 1.95 seconds
Started Jul 07 05:27:56 PM PDT 24
Finished Jul 07 05:27:59 PM PDT 24
Peak memory 200400 kb
Host smart-dccee029-672d-4f26-9d59-f33e0aa864cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049444315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2049444315
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3159895548
Short name T460
Test name
Test status
Simulation time 253193728 ps
CPU time 1.76 seconds
Started Jul 07 05:27:49 PM PDT 24
Finished Jul 07 05:27:51 PM PDT 24
Peak memory 200164 kb
Host smart-c8387004-36e8-40d5-bf0a-26df9b753397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159895548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3159895548
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1172945199
Short name T36
Test name
Test status
Simulation time 132189075 ps
CPU time 1.01 seconds
Started Jul 07 05:27:37 PM PDT 24
Finished Jul 07 05:27:43 PM PDT 24
Peak memory 200156 kb
Host smart-ca303859-8706-418b-bb7c-bf50fca6fabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172945199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1172945199
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3026580621
Short name T467
Test name
Test status
Simulation time 77985921 ps
CPU time 0.76 seconds
Started Jul 07 05:27:54 PM PDT 24
Finished Jul 07 05:27:55 PM PDT 24
Peak memory 199936 kb
Host smart-8c7f4661-ac38-4bef-8bdc-1fda83ce189d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026580621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3026580621
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3166186275
Short name T274
Test name
Test status
Simulation time 1867256757 ps
CPU time 7.15 seconds
Started Jul 07 05:27:50 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 217792 kb
Host smart-7c556a28-fc6c-4a93-ac24-31df0fcb0f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166186275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3166186275
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.989524540
Short name T266
Test name
Test status
Simulation time 245160636 ps
CPU time 1.13 seconds
Started Jul 07 05:27:47 PM PDT 24
Finished Jul 07 05:27:49 PM PDT 24
Peak memory 218288 kb
Host smart-f874bae6-bf12-48b0-88a0-75bc09248cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989524540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.989524540
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2925518261
Short name T169
Test name
Test status
Simulation time 181943998 ps
CPU time 0.94 seconds
Started Jul 07 05:27:55 PM PDT 24
Finished Jul 07 05:27:56 PM PDT 24
Peak memory 199972 kb
Host smart-9322620d-8bcf-4a6e-bd89-6c7877f293ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925518261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2925518261
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.594644764
Short name T510
Test name
Test status
Simulation time 1667497360 ps
CPU time 5.9 seconds
Started Jul 07 05:27:44 PM PDT 24
Finished Jul 07 05:27:51 PM PDT 24
Peak memory 200320 kb
Host smart-d0810c02-2c0b-44d6-a3c2-9e4cd9a3f64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594644764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.594644764
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.136697795
Short name T233
Test name
Test status
Simulation time 173745198 ps
CPU time 1.24 seconds
Started Jul 07 05:27:47 PM PDT 24
Finished Jul 07 05:27:49 PM PDT 24
Peak memory 200048 kb
Host smart-c8e2b489-b2be-4c60-8d77-49d38b581e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136697795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.136697795
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.921030014
Short name T262
Test name
Test status
Simulation time 245995378 ps
CPU time 1.44 seconds
Started Jul 07 05:27:45 PM PDT 24
Finished Jul 07 05:27:47 PM PDT 24
Peak memory 200356 kb
Host smart-2c7cc414-b53d-4591-a009-2ee077dcff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921030014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.921030014
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3772666602
Short name T401
Test name
Test status
Simulation time 7594791832 ps
CPU time 28.37 seconds
Started Jul 07 05:28:03 PM PDT 24
Finished Jul 07 05:28:32 PM PDT 24
Peak memory 200468 kb
Host smart-f90aecb4-93af-492d-a93c-7343b764a3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772666602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3772666602
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.344461611
Short name T424
Test name
Test status
Simulation time 144148775 ps
CPU time 1.82 seconds
Started Jul 07 05:27:38 PM PDT 24
Finished Jul 07 05:27:41 PM PDT 24
Peak memory 200148 kb
Host smart-eefd009c-2777-46a2-89e9-c166e0613342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344461611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.344461611
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3122512089
Short name T38
Test name
Test status
Simulation time 102480737 ps
CPU time 0.93 seconds
Started Jul 07 05:27:54 PM PDT 24
Finished Jul 07 05:27:55 PM PDT 24
Peak memory 200168 kb
Host smart-27269421-aa8f-476a-a0d5-9dc9b12cb103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122512089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3122512089
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1783938466
Short name T200
Test name
Test status
Simulation time 72365359 ps
CPU time 0.78 seconds
Started Jul 07 05:27:42 PM PDT 24
Finished Jul 07 05:27:43 PM PDT 24
Peak memory 199956 kb
Host smart-0765d2d0-d4c0-4aa1-b925-b0e9cb160193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783938466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1783938466
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.812819378
Short name T29
Test name
Test status
Simulation time 1901262601 ps
CPU time 6.53 seconds
Started Jul 07 05:27:54 PM PDT 24
Finished Jul 07 05:28:01 PM PDT 24
Peak memory 217392 kb
Host smart-25237c10-85d7-4e6f-a213-92ce6df36b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812819378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.812819378
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1938082711
Short name T142
Test name
Test status
Simulation time 243906695 ps
CPU time 1.05 seconds
Started Jul 07 05:27:48 PM PDT 24
Finished Jul 07 05:27:50 PM PDT 24
Peak memory 217536 kb
Host smart-1918ed5c-9901-421e-add8-40eb98f7d02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938082711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1938082711
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2356339055
Short name T15
Test name
Test status
Simulation time 129618748 ps
CPU time 0.77 seconds
Started Jul 07 05:27:48 PM PDT 24
Finished Jul 07 05:27:49 PM PDT 24
Peak memory 199976 kb
Host smart-14989a1c-5551-4bf4-9472-90b049c2dcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356339055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2356339055
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3885691405
Short name T314
Test name
Test status
Simulation time 1404425329 ps
CPU time 6.18 seconds
Started Jul 07 05:27:55 PM PDT 24
Finished Jul 07 05:28:02 PM PDT 24
Peak memory 200312 kb
Host smart-d3dde60a-ea94-4087-8bba-e8559ce99a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885691405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3885691405
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2299572815
Short name T280
Test name
Test status
Simulation time 150905041 ps
CPU time 1.14 seconds
Started Jul 07 05:28:02 PM PDT 24
Finished Jul 07 05:28:03 PM PDT 24
Peak memory 200120 kb
Host smart-796f70b7-91cf-48c9-8c45-74f982233cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299572815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2299572815
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2696648942
Short name T195
Test name
Test status
Simulation time 195320832 ps
CPU time 1.39 seconds
Started Jul 07 05:27:36 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 200328 kb
Host smart-793885db-aac6-448b-bd35-9ebad833d346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696648942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2696648942
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.936437026
Short name T304
Test name
Test status
Simulation time 2013172732 ps
CPU time 8.53 seconds
Started Jul 07 05:27:46 PM PDT 24
Finished Jul 07 05:27:55 PM PDT 24
Peak memory 210560 kb
Host smart-d993153c-5d22-402e-b5b2-5dccf047b4cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936437026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.936437026
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3986105349
Short name T133
Test name
Test status
Simulation time 369909873 ps
CPU time 2.22 seconds
Started Jul 07 05:27:53 PM PDT 24
Finished Jul 07 05:27:56 PM PDT 24
Peak memory 200008 kb
Host smart-046f8e45-5a3a-4558-833a-24b0c2bde9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986105349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3986105349
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.483037526
Short name T483
Test name
Test status
Simulation time 209154038 ps
CPU time 1.37 seconds
Started Jul 07 05:27:38 PM PDT 24
Finished Jul 07 05:27:41 PM PDT 24
Peak memory 199948 kb
Host smart-69c4cc82-affa-411f-be9d-eb7ffa41f52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483037526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.483037526
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1010740291
Short name T301
Test name
Test status
Simulation time 74897997 ps
CPU time 0.83 seconds
Started Jul 07 05:27:46 PM PDT 24
Finished Jul 07 05:27:47 PM PDT 24
Peak memory 200004 kb
Host smart-e5fdf6ab-2ae7-40c9-9b98-6a5b4b24af9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010740291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1010740291
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3784513254
Short name T244
Test name
Test status
Simulation time 1904295739 ps
CPU time 7.21 seconds
Started Jul 07 05:27:44 PM PDT 24
Finished Jul 07 05:27:52 PM PDT 24
Peak memory 221768 kb
Host smart-c7b9d184-1927-4253-a441-f3c07259cf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784513254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3784513254
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3780251479
Short name T513
Test name
Test status
Simulation time 244993042 ps
CPU time 1.02 seconds
Started Jul 07 05:27:46 PM PDT 24
Finished Jul 07 05:27:48 PM PDT 24
Peak memory 217520 kb
Host smart-7819f7d7-4b7a-493c-bacc-79e07049c8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780251479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3780251479
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3676361711
Short name T194
Test name
Test status
Simulation time 138154513 ps
CPU time 0.81 seconds
Started Jul 07 05:27:47 PM PDT 24
Finished Jul 07 05:27:48 PM PDT 24
Peak memory 199984 kb
Host smart-a262a829-9bf1-4848-b739-4f3ca3220d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676361711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3676361711
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3862156328
Short name T461
Test name
Test status
Simulation time 1499087867 ps
CPU time 5.38 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 200412 kb
Host smart-2cfe16be-9b76-4fc1-b3db-04fe3047a320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862156328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3862156328
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2298822785
Short name T246
Test name
Test status
Simulation time 101869780 ps
CPU time 1.03 seconds
Started Jul 07 05:27:46 PM PDT 24
Finished Jul 07 05:27:48 PM PDT 24
Peak memory 200092 kb
Host smart-300e7242-c87f-461f-8ec7-e4729ac2616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298822785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2298822785
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2593910798
Short name T349
Test name
Test status
Simulation time 114190149 ps
CPU time 1.22 seconds
Started Jul 07 05:28:02 PM PDT 24
Finished Jul 07 05:28:04 PM PDT 24
Peak memory 200280 kb
Host smart-cf7714b6-d9e3-4fe3-a38d-06ea8c0b9b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593910798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2593910798
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.4103851634
Short name T527
Test name
Test status
Simulation time 3363397713 ps
CPU time 12.06 seconds
Started Jul 07 05:27:52 PM PDT 24
Finished Jul 07 05:28:04 PM PDT 24
Peak memory 200400 kb
Host smart-944450fa-c621-4ab6-92e5-87d064ac6947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103851634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.4103851634
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3611093578
Short name T427
Test name
Test status
Simulation time 130451125 ps
CPU time 1.56 seconds
Started Jul 07 05:27:47 PM PDT 24
Finished Jul 07 05:27:49 PM PDT 24
Peak memory 208324 kb
Host smart-012f231f-f607-49d8-a8f2-82a4e35a58f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611093578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3611093578
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3290490168
Short name T518
Test name
Test status
Simulation time 91621767 ps
CPU time 0.84 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:37 PM PDT 24
Peak memory 200156 kb
Host smart-c6f5ef03-4faa-44f5-8f68-ff4be3ebe467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290490168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3290490168
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.4260542606
Short name T392
Test name
Test status
Simulation time 82037670 ps
CPU time 0.77 seconds
Started Jul 07 05:27:52 PM PDT 24
Finished Jul 07 05:27:53 PM PDT 24
Peak memory 199876 kb
Host smart-cea7ce58-7987-4e74-8169-41f1af232bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260542606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.4260542606
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1781632022
Short name T325
Test name
Test status
Simulation time 1223042640 ps
CPU time 5.59 seconds
Started Jul 07 05:27:50 PM PDT 24
Finished Jul 07 05:27:56 PM PDT 24
Peak memory 217732 kb
Host smart-6e8c7589-340a-44c4-8e05-027b9d9fbde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781632022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1781632022
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3029485281
Short name T360
Test name
Test status
Simulation time 245493199 ps
CPU time 1.03 seconds
Started Jul 07 05:27:32 PM PDT 24
Finished Jul 07 05:27:35 PM PDT 24
Peak memory 217240 kb
Host smart-06ce87cc-02cb-4a23-a0b6-15a3bf5d1054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029485281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3029485281
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2546180418
Short name T147
Test name
Test status
Simulation time 204573472 ps
CPU time 0.93 seconds
Started Jul 07 05:27:51 PM PDT 24
Finished Jul 07 05:27:52 PM PDT 24
Peak memory 199976 kb
Host smart-3e53ff19-d2d0-4571-a89f-6fbed999660b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546180418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2546180418
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1904137817
Short name T119
Test name
Test status
Simulation time 1624251699 ps
CPU time 5.87 seconds
Started Jul 07 05:27:48 PM PDT 24
Finished Jul 07 05:27:54 PM PDT 24
Peak memory 200464 kb
Host smart-2b2629c8-3aa6-461b-bd09-2afaddc7c57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904137817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1904137817
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3705095601
Short name T172
Test name
Test status
Simulation time 93819093 ps
CPU time 0.95 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:42 PM PDT 24
Peak memory 200144 kb
Host smart-88400ec0-f88c-41ae-a979-ad30b68ad264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705095601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3705095601
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.326275239
Short name T295
Test name
Test status
Simulation time 124822591 ps
CPU time 1.24 seconds
Started Jul 07 05:27:33 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 200396 kb
Host smart-e51239b5-f5b4-4e5a-b179-a7273f0d4183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326275239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.326275239
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3461988628
Short name T384
Test name
Test status
Simulation time 2253706687 ps
CPU time 9.3 seconds
Started Jul 07 05:27:53 PM PDT 24
Finished Jul 07 05:28:03 PM PDT 24
Peak memory 200400 kb
Host smart-7bf55463-e3c2-4caf-90a4-8aec84228038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461988628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3461988628
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1532285735
Short name T378
Test name
Test status
Simulation time 126646835 ps
CPU time 1.55 seconds
Started Jul 07 05:27:53 PM PDT 24
Finished Jul 07 05:27:55 PM PDT 24
Peak memory 208392 kb
Host smart-0a31162c-9316-48c0-853f-efadc1b9133d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532285735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1532285735
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1763975088
Short name T52
Test name
Test status
Simulation time 187035080 ps
CPU time 1.34 seconds
Started Jul 07 05:27:50 PM PDT 24
Finished Jul 07 05:27:52 PM PDT 24
Peak memory 200088 kb
Host smart-8f4154e5-d608-4c2b-a8bf-ee72632c5bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763975088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1763975088
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.146139785
Short name T472
Test name
Test status
Simulation time 67568772 ps
CPU time 0.77 seconds
Started Jul 07 05:27:48 PM PDT 24
Finished Jul 07 05:27:49 PM PDT 24
Peak memory 199876 kb
Host smart-d6318aa4-1d68-490e-9176-770ad2291875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146139785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.146139785
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2209259251
Short name T499
Test name
Test status
Simulation time 1901715783 ps
CPU time 7.66 seconds
Started Jul 07 05:27:42 PM PDT 24
Finished Jul 07 05:27:49 PM PDT 24
Peak memory 221716 kb
Host smart-dd2c0114-fa5d-42b4-bc78-c7f72ba26fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209259251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2209259251
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3403860540
Short name T421
Test name
Test status
Simulation time 244081874 ps
CPU time 1.27 seconds
Started Jul 07 05:27:59 PM PDT 24
Finished Jul 07 05:28:01 PM PDT 24
Peak memory 217452 kb
Host smart-865904a1-844a-4ae3-b066-7f5f5f78d741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403860540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3403860540
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.306557972
Short name T198
Test name
Test status
Simulation time 95572013 ps
CPU time 0.78 seconds
Started Jul 07 05:27:57 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 200240 kb
Host smart-5ce6c322-6116-4d33-8cab-9c383fb4237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306557972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.306557972
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3577685612
Short name T408
Test name
Test status
Simulation time 1917052904 ps
CPU time 6.63 seconds
Started Jul 07 05:27:50 PM PDT 24
Finished Jul 07 05:27:57 PM PDT 24
Peak memory 200396 kb
Host smart-70cba698-694b-4468-af0d-1d5e1f3aa298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577685612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3577685612
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3890700755
Short name T152
Test name
Test status
Simulation time 100535923 ps
CPU time 1.05 seconds
Started Jul 07 05:28:01 PM PDT 24
Finished Jul 07 05:28:02 PM PDT 24
Peak memory 200148 kb
Host smart-b1996683-e389-4974-9b0d-53c716a33ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890700755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3890700755
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1541019200
Short name T453
Test name
Test status
Simulation time 197417319 ps
CPU time 1.48 seconds
Started Jul 07 05:27:48 PM PDT 24
Finished Jul 07 05:27:50 PM PDT 24
Peak memory 200644 kb
Host smart-9695af1c-7efc-43ef-9a2f-cc609d377f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541019200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1541019200
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3299819657
Short name T3
Test name
Test status
Simulation time 573695013 ps
CPU time 2.32 seconds
Started Jul 07 05:27:36 PM PDT 24
Finished Jul 07 05:27:40 PM PDT 24
Peak memory 200356 kb
Host smart-d21e8610-2ca4-419f-b794-bb3b8d202a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299819657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3299819657
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.391843643
Short name T433
Test name
Test status
Simulation time 289830449 ps
CPU time 2.01 seconds
Started Jul 07 05:27:58 PM PDT 24
Finished Jul 07 05:28:01 PM PDT 24
Peak memory 208308 kb
Host smart-3f8870c8-f1a9-408d-befb-44a9a3ad4b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391843643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.391843643
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2561773726
Short name T519
Test name
Test status
Simulation time 178863610 ps
CPU time 1.19 seconds
Started Jul 07 05:27:45 PM PDT 24
Finished Jul 07 05:27:46 PM PDT 24
Peak memory 200136 kb
Host smart-65d13672-3c19-4902-9625-d18c1d5fa9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561773726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2561773726
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.412392337
Short name T249
Test name
Test status
Simulation time 61565130 ps
CPU time 0.73 seconds
Started Jul 07 05:27:49 PM PDT 24
Finished Jul 07 05:27:50 PM PDT 24
Peak memory 199940 kb
Host smart-3baa2bf9-bb72-4ff1-81c2-0afeba6aa790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412392337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.412392337
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1987977847
Short name T57
Test name
Test status
Simulation time 1903456476 ps
CPU time 8.05 seconds
Started Jul 07 05:27:53 PM PDT 24
Finished Jul 07 05:28:01 PM PDT 24
Peak memory 221796 kb
Host smart-ee8e038f-89dc-4bd9-8cfa-d4c0a023e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987977847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1987977847
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1505101918
Short name T283
Test name
Test status
Simulation time 244235707 ps
CPU time 1.25 seconds
Started Jul 07 05:27:58 PM PDT 24
Finished Jul 07 05:28:00 PM PDT 24
Peak memory 217532 kb
Host smart-15600c09-f101-4586-ae89-d676db369f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505101918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1505101918
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3292754552
Short name T375
Test name
Test status
Simulation time 249624541 ps
CPU time 0.94 seconds
Started Jul 07 05:27:58 PM PDT 24
Finished Jul 07 05:28:00 PM PDT 24
Peak memory 199964 kb
Host smart-e9fb9b5e-79eb-4330-8354-223d92cd9868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292754552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3292754552
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3768653961
Short name T343
Test name
Test status
Simulation time 957570301 ps
CPU time 4.72 seconds
Started Jul 07 05:27:47 PM PDT 24
Finished Jul 07 05:27:52 PM PDT 24
Peak memory 200400 kb
Host smart-b018de4b-5b8a-4988-8e81-a60eddbdecff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768653961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3768653961
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2379127239
Short name T523
Test name
Test status
Simulation time 104689492 ps
CPU time 1.07 seconds
Started Jul 07 05:27:57 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 200072 kb
Host smart-4b32d239-46f8-48bc-a95f-0ccafb60069f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379127239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2379127239
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.243375789
Short name T234
Test name
Test status
Simulation time 120992367 ps
CPU time 1.24 seconds
Started Jul 07 05:27:53 PM PDT 24
Finished Jul 07 05:27:54 PM PDT 24
Peak memory 200268 kb
Host smart-20e6531e-9a4a-42f9-a5cc-85510ccb44eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243375789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.243375789
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3568999551
Short name T284
Test name
Test status
Simulation time 12445134026 ps
CPU time 42.2 seconds
Started Jul 07 05:27:44 PM PDT 24
Finished Jul 07 05:28:27 PM PDT 24
Peak memory 200476 kb
Host smart-850bd80f-3a98-41b0-acb7-e52844fabec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568999551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3568999551
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3602147538
Short name T302
Test name
Test status
Simulation time 115454785 ps
CPU time 1.5 seconds
Started Jul 07 05:28:01 PM PDT 24
Finished Jul 07 05:28:03 PM PDT 24
Peak memory 200156 kb
Host smart-5612cb0c-e453-4f17-97a9-b77f66d4badd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602147538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3602147538
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1136982609
Short name T240
Test name
Test status
Simulation time 156361403 ps
CPU time 1.32 seconds
Started Jul 07 05:27:50 PM PDT 24
Finished Jul 07 05:27:52 PM PDT 24
Peak memory 200352 kb
Host smart-602865a8-b768-44b8-9575-9cd2ba8669ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136982609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1136982609
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2459542548
Short name T495
Test name
Test status
Simulation time 73452082 ps
CPU time 0.85 seconds
Started Jul 07 05:27:58 PM PDT 24
Finished Jul 07 05:28:00 PM PDT 24
Peak memory 199876 kb
Host smart-6f3d4fbf-09e1-45ff-b546-b70f9bda8d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459542548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2459542548
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1893991505
Short name T26
Test name
Test status
Simulation time 1908804447 ps
CPU time 7.25 seconds
Started Jul 07 05:28:04 PM PDT 24
Finished Jul 07 05:28:12 PM PDT 24
Peak memory 221764 kb
Host smart-d0c80b2a-ae1b-4d12-9691-2807eadfb5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893991505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1893991505
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.47230231
Short name T367
Test name
Test status
Simulation time 244274363 ps
CPU time 1.08 seconds
Started Jul 07 05:27:54 PM PDT 24
Finished Jul 07 05:27:55 PM PDT 24
Peak memory 217496 kb
Host smart-06ccc028-0377-4b4a-94b1-ec0e5bfe6ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47230231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.47230231
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.216995419
Short name T267
Test name
Test status
Simulation time 193114271 ps
CPU time 0.86 seconds
Started Jul 07 05:27:56 PM PDT 24
Finished Jul 07 05:27:57 PM PDT 24
Peak memory 199960 kb
Host smart-9c67e3a8-2b23-43ae-9311-eeb6939fc460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216995419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.216995419
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1001378062
Short name T150
Test name
Test status
Simulation time 832739415 ps
CPU time 4 seconds
Started Jul 07 05:27:55 PM PDT 24
Finished Jul 07 05:27:59 PM PDT 24
Peak memory 200416 kb
Host smart-0ba2e8c8-d056-4ab0-8c2d-09512c4fd423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001378062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1001378062
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2789314815
Short name T185
Test name
Test status
Simulation time 172082114 ps
CPU time 1.19 seconds
Started Jul 07 05:27:55 PM PDT 24
Finished Jul 07 05:27:57 PM PDT 24
Peak memory 200156 kb
Host smart-fe1d24a3-20ba-4088-9772-b9ebbbd7ce65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789314815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2789314815
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2597313127
Short name T192
Test name
Test status
Simulation time 254947894 ps
CPU time 1.55 seconds
Started Jul 07 05:27:56 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 200300 kb
Host smart-6e58dcec-387e-4a84-80e4-e92dfb49c10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597313127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2597313127
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1865648686
Short name T177
Test name
Test status
Simulation time 2787251454 ps
CPU time 13.8 seconds
Started Jul 07 05:28:00 PM PDT 24
Finished Jul 07 05:28:15 PM PDT 24
Peak memory 208596 kb
Host smart-f07f1933-2d0c-4ee6-af76-8bf757457aac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865648686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1865648686
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1556097491
Short name T121
Test name
Test status
Simulation time 392654203 ps
CPU time 2.31 seconds
Started Jul 07 05:27:54 PM PDT 24
Finished Jul 07 05:27:57 PM PDT 24
Peak memory 208384 kb
Host smart-ac4fe479-a6f9-497d-9f6a-b08f747cc614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556097491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1556097491
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2869704612
Short name T338
Test name
Test status
Simulation time 254622097 ps
CPU time 1.41 seconds
Started Jul 07 05:27:56 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 200204 kb
Host smart-3787b804-476d-4554-989b-7abab7bd4587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869704612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2869704612
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2111518412
Short name T376
Test name
Test status
Simulation time 78318584 ps
CPU time 0.81 seconds
Started Jul 07 05:27:54 PM PDT 24
Finished Jul 07 05:27:55 PM PDT 24
Peak memory 199860 kb
Host smart-6007b2b6-cd3f-43d5-8c52-7aa905f2a888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111518412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2111518412
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3088959557
Short name T327
Test name
Test status
Simulation time 1222911660 ps
CPU time 5.73 seconds
Started Jul 07 05:27:56 PM PDT 24
Finished Jul 07 05:28:02 PM PDT 24
Peak memory 216948 kb
Host smart-69b61c39-513b-4fd9-a21b-6014806c54e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088959557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3088959557
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.143719378
Short name T379
Test name
Test status
Simulation time 247152068 ps
CPU time 1.1 seconds
Started Jul 07 05:28:00 PM PDT 24
Finished Jul 07 05:28:02 PM PDT 24
Peak memory 217488 kb
Host smart-cd0a2ba0-961f-43e9-8b27-8e0d6f524009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143719378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.143719378
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2042723302
Short name T16
Test name
Test status
Simulation time 173038265 ps
CPU time 0.85 seconds
Started Jul 07 05:27:50 PM PDT 24
Finished Jul 07 05:27:51 PM PDT 24
Peak memory 199924 kb
Host smart-287e64b8-476e-40ba-b840-6f1ab54e70c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042723302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2042723302
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2268013455
Short name T48
Test name
Test status
Simulation time 1451004462 ps
CPU time 5.62 seconds
Started Jul 07 05:27:54 PM PDT 24
Finished Jul 07 05:28:00 PM PDT 24
Peak memory 200408 kb
Host smart-f50f1446-0bba-4ad8-8c60-9dbd756132f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268013455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2268013455
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.4011044857
Short name T475
Test name
Test status
Simulation time 112541513 ps
CPU time 1.02 seconds
Started Jul 07 05:27:57 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 200100 kb
Host smart-7fcc405a-de64-470e-96fa-d4a408760766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011044857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.4011044857
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.676759419
Short name T337
Test name
Test status
Simulation time 116441441 ps
CPU time 1.25 seconds
Started Jul 07 05:28:00 PM PDT 24
Finished Jul 07 05:28:02 PM PDT 24
Peak memory 200348 kb
Host smart-8a5a1e1a-7b3e-4f74-8ed0-c90d0d9e977c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676759419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.676759419
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.4271262254
Short name T225
Test name
Test status
Simulation time 1435786891 ps
CPU time 7.57 seconds
Started Jul 07 05:27:52 PM PDT 24
Finished Jul 07 05:28:00 PM PDT 24
Peak memory 200412 kb
Host smart-729d0380-4e16-409f-a4bd-8a01802a25a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271262254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.4271262254
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1764680039
Short name T537
Test name
Test status
Simulation time 262241670 ps
CPU time 1.83 seconds
Started Jul 07 05:27:53 PM PDT 24
Finished Jul 07 05:27:55 PM PDT 24
Peak memory 200076 kb
Host smart-34a2d5c4-4cd9-4b05-b405-bbd36e8719fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764680039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1764680039
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3395113219
Short name T141
Test name
Test status
Simulation time 126868948 ps
CPU time 1.07 seconds
Started Jul 07 05:27:53 PM PDT 24
Finished Jul 07 05:27:55 PM PDT 24
Peak memory 200096 kb
Host smart-9f5a6c6a-f674-4d0b-91a6-4ffdc737b4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395113219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3395113219
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.93944296
Short name T415
Test name
Test status
Simulation time 66651129 ps
CPU time 0.81 seconds
Started Jul 07 05:27:59 PM PDT 24
Finished Jul 07 05:28:01 PM PDT 24
Peak memory 199876 kb
Host smart-922b7da4-684e-4ac1-b9d5-675a04c116c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93944296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.93944296
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.188388665
Short name T33
Test name
Test status
Simulation time 1886087800 ps
CPU time 7.54 seconds
Started Jul 07 05:27:52 PM PDT 24
Finished Jul 07 05:28:00 PM PDT 24
Peak memory 221712 kb
Host smart-66776eb4-e309-45fd-a1b8-0100113bd816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188388665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.188388665
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3796591136
Short name T39
Test name
Test status
Simulation time 243776450 ps
CPU time 1.12 seconds
Started Jul 07 05:27:57 PM PDT 24
Finished Jul 07 05:27:59 PM PDT 24
Peak memory 217488 kb
Host smart-72ed1ab2-2da6-49fc-869a-d30fb400c4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796591136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3796591136
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3226705893
Short name T160
Test name
Test status
Simulation time 144123383 ps
CPU time 0.86 seconds
Started Jul 07 05:27:56 PM PDT 24
Finished Jul 07 05:27:57 PM PDT 24
Peak memory 199892 kb
Host smart-3bac74c7-5257-4232-8448-f97b57cd54bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226705893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3226705893
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1679114830
Short name T92
Test name
Test status
Simulation time 1029293244 ps
CPU time 5.33 seconds
Started Jul 07 05:28:00 PM PDT 24
Finished Jul 07 05:28:06 PM PDT 24
Peak memory 200376 kb
Host smart-2ad4a7dd-dc0e-41b1-86eb-fe8ef14109e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679114830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1679114830
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1234057095
Short name T498
Test name
Test status
Simulation time 97113268 ps
CPU time 0.93 seconds
Started Jul 07 05:27:54 PM PDT 24
Finished Jul 07 05:27:56 PM PDT 24
Peak memory 200000 kb
Host smart-7a90fb16-2d5f-46f3-8098-35d1882c0415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234057095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1234057095
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.270806108
Short name T135
Test name
Test status
Simulation time 195164218 ps
CPU time 1.45 seconds
Started Jul 07 05:27:57 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 200284 kb
Host smart-7fa356c4-5da3-4817-8950-948672a83f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270806108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.270806108
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1894809887
Short name T96
Test name
Test status
Simulation time 8028433399 ps
CPU time 28.14 seconds
Started Jul 07 05:28:00 PM PDT 24
Finished Jul 07 05:28:29 PM PDT 24
Peak memory 208524 kb
Host smart-c8cc585f-83f2-40b6-9339-e9ce8632a8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894809887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1894809887
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2574339912
Short name T364
Test name
Test status
Simulation time 489483419 ps
CPU time 2.71 seconds
Started Jul 07 05:28:05 PM PDT 24
Finished Jul 07 05:28:08 PM PDT 24
Peak memory 200092 kb
Host smart-5e487bf3-b5f9-4aab-87b4-f2cbd68cd571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574339912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2574339912
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3880139052
Short name T440
Test name
Test status
Simulation time 216453895 ps
CPU time 1.28 seconds
Started Jul 07 05:27:53 PM PDT 24
Finished Jul 07 05:27:54 PM PDT 24
Peak memory 200164 kb
Host smart-26701232-cb02-4ba3-8af8-83d5344e507f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880139052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3880139052
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3908093861
Short name T175
Test name
Test status
Simulation time 70150247 ps
CPU time 0.79 seconds
Started Jul 07 05:27:13 PM PDT 24
Finished Jul 07 05:27:15 PM PDT 24
Peak memory 199916 kb
Host smart-cc0194bf-3b6b-43c1-8489-52a5ad48295e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908093861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3908093861
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2105211722
Short name T532
Test name
Test status
Simulation time 1890955703 ps
CPU time 6.99 seconds
Started Jul 07 05:27:21 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 217576 kb
Host smart-315f7dfe-f7b7-4d5f-9c48-844ddb525135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105211722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2105211722
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1926465932
Short name T155
Test name
Test status
Simulation time 246277761 ps
CPU time 1.09 seconds
Started Jul 07 05:27:08 PM PDT 24
Finished Jul 07 05:27:09 PM PDT 24
Peak memory 217524 kb
Host smart-8e414c5a-bff2-46df-9fe7-84bdff7c9dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926465932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1926465932
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1916096130
Short name T409
Test name
Test status
Simulation time 203909085 ps
CPU time 0.89 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:24 PM PDT 24
Peak memory 199888 kb
Host smart-1029eba6-6141-4347-9e70-5c4b8a23709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916096130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1916096130
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2988244008
Short name T229
Test name
Test status
Simulation time 1525133951 ps
CPU time 6.06 seconds
Started Jul 07 05:27:13 PM PDT 24
Finished Jul 07 05:27:20 PM PDT 24
Peak memory 200256 kb
Host smart-a7b37709-20bd-4a56-873b-76efb4157eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988244008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2988244008
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1593087269
Short name T76
Test name
Test status
Simulation time 8284933070 ps
CPU time 15.31 seconds
Started Jul 07 05:27:17 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 217244 kb
Host smart-061d4a96-cc93-41c1-ae28-009a7c71ac39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593087269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1593087269
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2662318540
Short name T455
Test name
Test status
Simulation time 150538610 ps
CPU time 1.1 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 200164 kb
Host smart-660bb60f-1546-4549-a1f2-487dfc8c774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662318540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2662318540
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1623414543
Short name T149
Test name
Test status
Simulation time 122656327 ps
CPU time 1.22 seconds
Started Jul 07 05:27:16 PM PDT 24
Finished Jul 07 05:27:17 PM PDT 24
Peak memory 200308 kb
Host smart-a39f11f9-332c-40f6-8386-644f4a814f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623414543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1623414543
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3411468440
Short name T231
Test name
Test status
Simulation time 3730070467 ps
CPU time 16.31 seconds
Started Jul 07 05:27:19 PM PDT 24
Finished Jul 07 05:27:36 PM PDT 24
Peak memory 208632 kb
Host smart-33b41fe2-69ab-46b3-a7cb-1ff1616d7fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411468440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3411468440
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1496339742
Short name T359
Test name
Test status
Simulation time 141945708 ps
CPU time 1.66 seconds
Started Jul 07 05:27:24 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 200132 kb
Host smart-c80f59a0-b1a1-4923-b2e3-bb88625c8c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496339742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1496339742
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2215690421
Short name T219
Test name
Test status
Simulation time 81402657 ps
CPU time 0.84 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 200148 kb
Host smart-82a4d7ed-f2de-4ee5-9d11-edfbeb783934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215690421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2215690421
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3403190350
Short name T428
Test name
Test status
Simulation time 66747947 ps
CPU time 0.84 seconds
Started Jul 07 05:28:07 PM PDT 24
Finished Jul 07 05:28:08 PM PDT 24
Peak memory 199952 kb
Host smart-84b32b76-0fdc-4bb8-9437-ac0950369b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403190350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3403190350
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1590886627
Short name T420
Test name
Test status
Simulation time 1881416139 ps
CPU time 7.46 seconds
Started Jul 07 05:28:03 PM PDT 24
Finished Jul 07 05:28:11 PM PDT 24
Peak memory 217504 kb
Host smart-d1448d67-e41b-4273-b995-5ea3513c454f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590886627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1590886627
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1064503063
Short name T507
Test name
Test status
Simulation time 244916646 ps
CPU time 1.05 seconds
Started Jul 07 05:28:07 PM PDT 24
Finished Jul 07 05:28:08 PM PDT 24
Peak memory 217508 kb
Host smart-2c4472b0-bbcd-4f3f-89a8-b1017e11f56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064503063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1064503063
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3805545974
Short name T270
Test name
Test status
Simulation time 201900699 ps
CPU time 0.95 seconds
Started Jul 07 05:27:58 PM PDT 24
Finished Jul 07 05:28:00 PM PDT 24
Peak memory 199964 kb
Host smart-46fe8476-0d41-40e8-8e26-1b9314dfb91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805545974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3805545974
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3917192325
Short name T413
Test name
Test status
Simulation time 823959470 ps
CPU time 4.26 seconds
Started Jul 07 05:27:55 PM PDT 24
Finished Jul 07 05:28:00 PM PDT 24
Peak memory 200404 kb
Host smart-58b40d6f-13cd-48dc-b435-9eea520a787a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917192325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3917192325
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3328134558
Short name T206
Test name
Test status
Simulation time 154366585 ps
CPU time 1.12 seconds
Started Jul 07 05:27:59 PM PDT 24
Finished Jul 07 05:28:01 PM PDT 24
Peak memory 200116 kb
Host smart-4b504b05-6a8f-42c6-bcc2-7b82a33dbb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328134558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3328134558
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.4276997081
Short name T414
Test name
Test status
Simulation time 117609611 ps
CPU time 1.23 seconds
Started Jul 07 05:27:56 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 200408 kb
Host smart-2fca9f32-d42f-4e50-a9a3-30dee8a64e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276997081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.4276997081
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2753855831
Short name T423
Test name
Test status
Simulation time 2960054414 ps
CPU time 13.9 seconds
Started Jul 07 05:28:04 PM PDT 24
Finished Jul 07 05:28:18 PM PDT 24
Peak memory 208668 kb
Host smart-ecf5dbaf-08f3-42b7-a65e-a7ab48f54a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753855831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2753855831
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1448196386
Short name T436
Test name
Test status
Simulation time 151364199 ps
CPU time 1.78 seconds
Started Jul 07 05:27:59 PM PDT 24
Finished Jul 07 05:28:01 PM PDT 24
Peak memory 200140 kb
Host smart-7eea921d-cb9a-4730-ae3a-81b98af362aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448196386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1448196386
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.991257654
Short name T294
Test name
Test status
Simulation time 133581342 ps
CPU time 1.07 seconds
Started Jul 07 05:27:56 PM PDT 24
Finished Jul 07 05:27:57 PM PDT 24
Peak memory 200144 kb
Host smart-f7cc0156-88c9-4af1-aa97-2eb8b6d06beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991257654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.991257654
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2798449169
Short name T369
Test name
Test status
Simulation time 78150279 ps
CPU time 0.8 seconds
Started Jul 07 05:28:09 PM PDT 24
Finished Jul 07 05:28:10 PM PDT 24
Peak memory 199960 kb
Host smart-18261b83-6766-4e9c-a819-dbf2ef631a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798449169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2798449169
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2853048962
Short name T23
Test name
Test status
Simulation time 2170057240 ps
CPU time 7.73 seconds
Started Jul 07 05:28:02 PM PDT 24
Finished Jul 07 05:28:11 PM PDT 24
Peak memory 217196 kb
Host smart-7dc131ad-cb25-4cfe-839a-e68e96a4d635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853048962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2853048962
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3909710638
Short name T320
Test name
Test status
Simulation time 245033381 ps
CPU time 1.1 seconds
Started Jul 07 05:28:09 PM PDT 24
Finished Jul 07 05:28:11 PM PDT 24
Peak memory 217536 kb
Host smart-561e4887-0719-411d-b9d3-5261fce9b163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909710638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3909710638
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4127236894
Short name T213
Test name
Test status
Simulation time 108190651 ps
CPU time 0.85 seconds
Started Jul 07 05:28:11 PM PDT 24
Finished Jul 07 05:28:12 PM PDT 24
Peak memory 199976 kb
Host smart-478380b3-53df-43e8-b7b2-7cfdbd709f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127236894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4127236894
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1213043169
Short name T417
Test name
Test status
Simulation time 1424575194 ps
CPU time 5.83 seconds
Started Jul 07 05:28:03 PM PDT 24
Finished Jul 07 05:28:10 PM PDT 24
Peak memory 200200 kb
Host smart-5ba2dab6-c21c-42e7-adeb-fc5f194ceb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213043169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1213043169
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.406094333
Short name T316
Test name
Test status
Simulation time 156790556 ps
CPU time 1.18 seconds
Started Jul 07 05:28:02 PM PDT 24
Finished Jul 07 05:28:04 PM PDT 24
Peak memory 200156 kb
Host smart-df9ab795-f45d-4f88-85b6-a58ebe19dfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406094333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.406094333
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2197163948
Short name T269
Test name
Test status
Simulation time 198826273 ps
CPU time 1.46 seconds
Started Jul 07 05:28:02 PM PDT 24
Finished Jul 07 05:28:04 PM PDT 24
Peak memory 200344 kb
Host smart-2ad91bdc-ed9c-4829-a33f-ed126911c852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197163948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2197163948
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2322178442
Short name T123
Test name
Test status
Simulation time 1501627800 ps
CPU time 5.63 seconds
Started Jul 07 05:28:07 PM PDT 24
Finished Jul 07 05:28:13 PM PDT 24
Peak memory 200376 kb
Host smart-c7397960-5b4a-4bbb-8530-076d4e91a876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322178442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2322178442
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.4219936868
Short name T335
Test name
Test status
Simulation time 480075731 ps
CPU time 2.6 seconds
Started Jul 07 05:28:09 PM PDT 24
Finished Jul 07 05:28:12 PM PDT 24
Peak memory 200188 kb
Host smart-92664920-ba8c-4c02-91b0-55f1987d7f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219936868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.4219936868
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3145996198
Short name T22
Test name
Test status
Simulation time 70403182 ps
CPU time 0.78 seconds
Started Jul 07 05:27:59 PM PDT 24
Finished Jul 07 05:28:00 PM PDT 24
Peak memory 200104 kb
Host smart-158d3e27-4d2d-4022-8464-048f5100f412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145996198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3145996198
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3464811276
Short name T481
Test name
Test status
Simulation time 76036652 ps
CPU time 0.85 seconds
Started Jul 07 05:27:55 PM PDT 24
Finished Jul 07 05:27:56 PM PDT 24
Peak memory 200000 kb
Host smart-e717e813-c4cc-43fa-9e2d-98e80fe4b421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464811276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3464811276
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3784121785
Short name T55
Test name
Test status
Simulation time 1901542499 ps
CPU time 8.08 seconds
Started Jul 07 05:28:11 PM PDT 24
Finished Jul 07 05:28:19 PM PDT 24
Peak memory 217812 kb
Host smart-0fba26ff-1609-43aa-a1bf-8613ba157d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784121785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3784121785
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3266370514
Short name T326
Test name
Test status
Simulation time 245414761 ps
CPU time 1.03 seconds
Started Jul 07 05:28:08 PM PDT 24
Finished Jul 07 05:28:09 PM PDT 24
Peak memory 217528 kb
Host smart-19fd17da-66f6-4451-8c7e-92be01b3d892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266370514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3266370514
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1914155009
Short name T372
Test name
Test status
Simulation time 186485784 ps
CPU time 0.9 seconds
Started Jul 07 05:28:06 PM PDT 24
Finished Jul 07 05:28:07 PM PDT 24
Peak memory 200004 kb
Host smart-df16168b-be76-4a3c-a820-cbea3b30ee88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914155009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1914155009
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2701283508
Short name T331
Test name
Test status
Simulation time 1755128004 ps
CPU time 7.15 seconds
Started Jul 07 05:27:59 PM PDT 24
Finished Jul 07 05:28:07 PM PDT 24
Peak memory 200404 kb
Host smart-b5309ab0-0a78-4b39-af3c-b4066d4ec61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701283508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2701283508
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1039157513
Short name T264
Test name
Test status
Simulation time 95908200 ps
CPU time 1.03 seconds
Started Jul 07 05:28:06 PM PDT 24
Finished Jul 07 05:28:07 PM PDT 24
Peak memory 200168 kb
Host smart-a2679371-beba-4ed7-adac-d6df89b442dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039157513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1039157513
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3337632784
Short name T159
Test name
Test status
Simulation time 116994727 ps
CPU time 1.29 seconds
Started Jul 07 05:28:04 PM PDT 24
Finished Jul 07 05:28:06 PM PDT 24
Peak memory 200224 kb
Host smart-e14dd670-97e0-412b-860e-1c93b143e017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337632784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3337632784
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1227409010
Short name T122
Test name
Test status
Simulation time 491786866 ps
CPU time 2.79 seconds
Started Jul 07 05:27:59 PM PDT 24
Finished Jul 07 05:28:02 PM PDT 24
Peak memory 200192 kb
Host smart-c8113375-8675-4fc1-ad5b-64436ad53d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227409010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1227409010
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1258591331
Short name T134
Test name
Test status
Simulation time 88158653 ps
CPU time 0.93 seconds
Started Jul 07 05:28:02 PM PDT 24
Finished Jul 07 05:28:04 PM PDT 24
Peak memory 200124 kb
Host smart-04c19955-5318-4852-ad30-06ad88a92b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258591331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1258591331
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.4193640598
Short name T450
Test name
Test status
Simulation time 63866527 ps
CPU time 0.83 seconds
Started Jul 07 05:28:05 PM PDT 24
Finished Jul 07 05:28:06 PM PDT 24
Peak memory 199948 kb
Host smart-32576d9a-fd6e-4df5-a034-73c1f7274dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193640598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.4193640598
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2120495487
Short name T500
Test name
Test status
Simulation time 1228706189 ps
CPU time 5.76 seconds
Started Jul 07 05:27:59 PM PDT 24
Finished Jul 07 05:28:06 PM PDT 24
Peak memory 221488 kb
Host smart-9e44454f-63da-4a9f-8663-b82abc4296a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120495487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2120495487
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.111199176
Short name T538
Test name
Test status
Simulation time 244616159 ps
CPU time 1.03 seconds
Started Jul 07 05:28:02 PM PDT 24
Finished Jul 07 05:28:03 PM PDT 24
Peak memory 217496 kb
Host smart-cbcb160c-e846-4755-9ee3-e01d7f19d774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111199176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.111199176
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3281669198
Short name T396
Test name
Test status
Simulation time 154117995 ps
CPU time 0.82 seconds
Started Jul 07 05:28:06 PM PDT 24
Finished Jul 07 05:28:07 PM PDT 24
Peak memory 199904 kb
Host smart-9a6e92f8-a567-4e62-b9b7-3096c9fa3ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281669198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3281669198
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.108307056
Short name T406
Test name
Test status
Simulation time 1047212653 ps
CPU time 4.92 seconds
Started Jul 07 05:28:10 PM PDT 24
Finished Jul 07 05:28:15 PM PDT 24
Peak memory 200396 kb
Host smart-c3608823-2601-4d2f-b034-b8b34b9203d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108307056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.108307056
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1338259320
Short name T64
Test name
Test status
Simulation time 115823495 ps
CPU time 1.02 seconds
Started Jul 07 05:27:59 PM PDT 24
Finished Jul 07 05:28:00 PM PDT 24
Peak memory 200160 kb
Host smart-643e7ac5-e4fc-4d12-b0c7-5fc23be53d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338259320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1338259320
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3380882450
Short name T356
Test name
Test status
Simulation time 246950757 ps
CPU time 1.49 seconds
Started Jul 07 05:28:00 PM PDT 24
Finished Jul 07 05:28:03 PM PDT 24
Peak memory 200340 kb
Host smart-50ad2326-5360-41b5-859f-50c022e51e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380882450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3380882450
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.533811009
Short name T278
Test name
Test status
Simulation time 13243268693 ps
CPU time 49.6 seconds
Started Jul 07 05:28:03 PM PDT 24
Finished Jul 07 05:28:53 PM PDT 24
Peak memory 208668 kb
Host smart-ae6734ea-2310-4f71-b23b-a380e18966e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533811009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.533811009
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.4048667801
Short name T193
Test name
Test status
Simulation time 370942037 ps
CPU time 2.67 seconds
Started Jul 07 05:28:02 PM PDT 24
Finished Jul 07 05:28:05 PM PDT 24
Peak memory 200144 kb
Host smart-f16ef59f-26d3-4901-a453-407ef2916389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048667801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4048667801
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.957288118
Short name T136
Test name
Test status
Simulation time 71822107 ps
CPU time 0.82 seconds
Started Jul 07 05:28:08 PM PDT 24
Finished Jul 07 05:28:09 PM PDT 24
Peak memory 200152 kb
Host smart-910991a0-13ea-4793-a867-9599905798a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957288118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.957288118
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2187551947
Short name T183
Test name
Test status
Simulation time 73241556 ps
CPU time 0.84 seconds
Started Jul 07 05:28:06 PM PDT 24
Finished Jul 07 05:28:07 PM PDT 24
Peak memory 199888 kb
Host smart-80289920-6e0c-4c62-bc0d-f56e8ba72e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187551947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2187551947
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1477905077
Short name T476
Test name
Test status
Simulation time 1229749073 ps
CPU time 5.75 seconds
Started Jul 07 05:28:07 PM PDT 24
Finished Jul 07 05:28:13 PM PDT 24
Peak memory 217628 kb
Host smart-09de5445-8911-4246-9013-630ef875a938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477905077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1477905077
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.901234799
Short name T318
Test name
Test status
Simulation time 243986485 ps
CPU time 1.08 seconds
Started Jul 07 05:28:12 PM PDT 24
Finished Jul 07 05:28:14 PM PDT 24
Peak memory 217560 kb
Host smart-5d90dc62-e3de-4bb4-bf37-fc59b6aa88e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901234799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.901234799
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2293270623
Short name T14
Test name
Test status
Simulation time 199409989 ps
CPU time 0.95 seconds
Started Jul 07 05:28:03 PM PDT 24
Finished Jul 07 05:28:04 PM PDT 24
Peak memory 200004 kb
Host smart-9e1b755b-7651-4b35-8a66-7185a5cc769c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293270623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2293270623
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2438223861
Short name T457
Test name
Test status
Simulation time 1599420400 ps
CPU time 6.12 seconds
Started Jul 07 05:28:07 PM PDT 24
Finished Jul 07 05:28:13 PM PDT 24
Peak memory 200404 kb
Host smart-3acf6de4-4d81-41d2-b3e0-967974ac613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438223861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2438223861
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2521994100
Short name T61
Test name
Test status
Simulation time 152606265 ps
CPU time 1.13 seconds
Started Jul 07 05:28:06 PM PDT 24
Finished Jul 07 05:28:08 PM PDT 24
Peak memory 200092 kb
Host smart-da53c108-c2f0-4d29-a4a2-aaa3fb4beb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521994100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2521994100
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2119239727
Short name T473
Test name
Test status
Simulation time 195624793 ps
CPU time 1.37 seconds
Started Jul 07 05:28:04 PM PDT 24
Finished Jul 07 05:28:06 PM PDT 24
Peak memory 200340 kb
Host smart-f5fe2753-d273-4913-9fc0-54dc6dd150ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119239727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2119239727
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1361740308
Short name T54
Test name
Test status
Simulation time 2034412358 ps
CPU time 8.03 seconds
Started Jul 07 05:28:03 PM PDT 24
Finished Jul 07 05:28:12 PM PDT 24
Peak memory 200404 kb
Host smart-1486f0c1-be78-48b8-9d25-f97632e7d4fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361740308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1361740308
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1804287622
Short name T241
Test name
Test status
Simulation time 392002252 ps
CPU time 2.18 seconds
Started Jul 07 05:28:00 PM PDT 24
Finished Jul 07 05:28:03 PM PDT 24
Peak memory 200052 kb
Host smart-d445141e-baed-47d5-86fe-22b23d12d9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804287622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1804287622
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1012716276
Short name T362
Test name
Test status
Simulation time 95998299 ps
CPU time 0.88 seconds
Started Jul 07 05:27:57 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 200160 kb
Host smart-e56164cd-3bd9-47c6-8214-e8d55a32bfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012716276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1012716276
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1772589104
Short name T144
Test name
Test status
Simulation time 63823300 ps
CPU time 0.74 seconds
Started Jul 07 05:28:23 PM PDT 24
Finished Jul 07 05:28:25 PM PDT 24
Peak memory 199924 kb
Host smart-869b62a6-f157-4941-a065-ed0be1412159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772589104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1772589104
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2822451272
Short name T438
Test name
Test status
Simulation time 1236800415 ps
CPU time 5.79 seconds
Started Jul 07 05:28:04 PM PDT 24
Finished Jul 07 05:28:11 PM PDT 24
Peak memory 217480 kb
Host smart-9ae5b811-c679-4808-b9e6-5bfa85ffb8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822451272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2822451272
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3276380410
Short name T477
Test name
Test status
Simulation time 244527433 ps
CPU time 1.08 seconds
Started Jul 07 05:28:29 PM PDT 24
Finished Jul 07 05:28:31 PM PDT 24
Peak memory 217440 kb
Host smart-ad7df5c1-2dfe-42e6-aa79-38a1da14720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276380410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3276380410
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2303361245
Short name T521
Test name
Test status
Simulation time 88910380 ps
CPU time 0.81 seconds
Started Jul 07 05:28:06 PM PDT 24
Finished Jul 07 05:28:07 PM PDT 24
Peak memory 200004 kb
Host smart-96e39f5e-eda6-41e9-8fd3-263ed9054337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303361245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2303361245
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1634955766
Short name T345
Test name
Test status
Simulation time 2098256209 ps
CPU time 8.22 seconds
Started Jul 07 05:28:00 PM PDT 24
Finished Jul 07 05:28:09 PM PDT 24
Peak memory 200452 kb
Host smart-8c793ee1-35b0-4c1c-9c39-4c3a11c3dc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634955766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1634955766
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3177519864
Short name T412
Test name
Test status
Simulation time 110036734 ps
CPU time 1.07 seconds
Started Jul 07 05:28:12 PM PDT 24
Finished Jul 07 05:28:14 PM PDT 24
Peak memory 200152 kb
Host smart-72008630-baa3-4d25-a399-5822c37e7912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177519864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3177519864
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2359554115
Short name T511
Test name
Test status
Simulation time 112611891 ps
CPU time 1.29 seconds
Started Jul 07 05:28:04 PM PDT 24
Finished Jul 07 05:28:06 PM PDT 24
Peak memory 200328 kb
Host smart-9de9da95-ca15-4b7a-b37a-0555155eb5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359554115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2359554115
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2033805747
Short name T116
Test name
Test status
Simulation time 1618299123 ps
CPU time 6.58 seconds
Started Jul 07 05:28:23 PM PDT 24
Finished Jul 07 05:28:30 PM PDT 24
Peak memory 200384 kb
Host smart-8e4662cd-38ad-4bdd-887a-427cd9f70baf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033805747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2033805747
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.407363147
Short name T138
Test name
Test status
Simulation time 147615800 ps
CPU time 1.89 seconds
Started Jul 07 05:28:03 PM PDT 24
Finished Jul 07 05:28:06 PM PDT 24
Peak memory 200116 kb
Host smart-fc79f6e2-8eee-4a98-964e-b4698df0d99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407363147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.407363147
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3570288343
Short name T336
Test name
Test status
Simulation time 120951244 ps
CPU time 0.98 seconds
Started Jul 07 05:28:03 PM PDT 24
Finished Jul 07 05:28:05 PM PDT 24
Peak memory 200000 kb
Host smart-951de703-8973-445b-bcb8-1c5136a9cea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570288343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3570288343
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.736947358
Short name T40
Test name
Test status
Simulation time 67786071 ps
CPU time 0.76 seconds
Started Jul 07 05:28:16 PM PDT 24
Finished Jul 07 05:28:17 PM PDT 24
Peak memory 199960 kb
Host smart-ad47fa3c-42e1-44f6-93d3-a43592d882b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736947358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.736947358
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3479121748
Short name T319
Test name
Test status
Simulation time 1874801139 ps
CPU time 7.22 seconds
Started Jul 07 05:28:23 PM PDT 24
Finished Jul 07 05:28:31 PM PDT 24
Peak memory 217684 kb
Host smart-341ebe64-1fc0-4750-b298-421145f2b8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479121748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3479121748
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.171624627
Short name T199
Test name
Test status
Simulation time 245079707 ps
CPU time 1.05 seconds
Started Jul 07 05:28:27 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 217548 kb
Host smart-ad57944b-c122-4d7f-82fe-1f73c2e676cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171624627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.171624627
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3825242005
Short name T514
Test name
Test status
Simulation time 189956040 ps
CPU time 0.9 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:25 PM PDT 24
Peak memory 200012 kb
Host smart-2c1103c9-04db-4216-805d-57a6ee0d86b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825242005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3825242005
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3993042243
Short name T505
Test name
Test status
Simulation time 146487668 ps
CPU time 1.1 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 200432 kb
Host smart-65ec5dfb-6c2e-49fa-8fb6-ba01ae2b6442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993042243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3993042243
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1786189897
Short name T342
Test name
Test status
Simulation time 194992015 ps
CPU time 1.36 seconds
Started Jul 07 05:28:26 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 200340 kb
Host smart-6ab66905-8fe6-481c-ba98-4c97811d450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786189897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1786189897
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3413589602
Short name T260
Test name
Test status
Simulation time 4528528065 ps
CPU time 20.84 seconds
Started Jul 07 05:28:26 PM PDT 24
Finished Jul 07 05:28:47 PM PDT 24
Peak memory 208712 kb
Host smart-48c8f035-20e1-431b-9d98-31dd016dd868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413589602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3413589602
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1016750913
Short name T120
Test name
Test status
Simulation time 491283111 ps
CPU time 2.53 seconds
Started Jul 07 05:28:15 PM PDT 24
Finished Jul 07 05:28:18 PM PDT 24
Peak memory 200072 kb
Host smart-a1ec70dc-000b-48d3-a971-658cba1ad709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016750913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1016750913
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.259415870
Short name T182
Test name
Test status
Simulation time 73570293 ps
CPU time 0.8 seconds
Started Jul 07 05:28:17 PM PDT 24
Finished Jul 07 05:28:18 PM PDT 24
Peak memory 200192 kb
Host smart-8a5b7c5f-3201-4843-b808-fb72478901bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259415870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.259415870
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3393407977
Short name T154
Test name
Test status
Simulation time 65707133 ps
CPU time 0.74 seconds
Started Jul 07 05:28:30 PM PDT 24
Finished Jul 07 05:28:31 PM PDT 24
Peak memory 199924 kb
Host smart-5ee0177e-1fda-443b-89df-f8cd9c041039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393407977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3393407977
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.390317408
Short name T445
Test name
Test status
Simulation time 244792076 ps
CPU time 1.1 seconds
Started Jul 07 05:28:14 PM PDT 24
Finished Jul 07 05:28:15 PM PDT 24
Peak memory 217480 kb
Host smart-aa553035-c2b6-4b82-a8f5-51906d43455b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390317408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.390317408
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.4022030741
Short name T153
Test name
Test status
Simulation time 177166522 ps
CPU time 0.88 seconds
Started Jul 07 05:28:22 PM PDT 24
Finished Jul 07 05:28:23 PM PDT 24
Peak memory 199976 kb
Host smart-80aadfa8-2eab-4edf-8d5b-05e2b0b7984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022030741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4022030741
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1713117628
Short name T458
Test name
Test status
Simulation time 1063711971 ps
CPU time 5.09 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:32 PM PDT 24
Peak memory 200752 kb
Host smart-4ff06589-8cbf-47c1-8304-4b92e6b9f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713117628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1713117628
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2864414641
Short name T530
Test name
Test status
Simulation time 156289116 ps
CPU time 1.21 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 200128 kb
Host smart-3a589e68-935f-4650-ab6b-05dbdbceae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864414641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2864414641
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.768645252
Short name T180
Test name
Test status
Simulation time 248489360 ps
CPU time 1.56 seconds
Started Jul 07 05:28:26 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 200400 kb
Host smart-f04e1481-8a90-41f4-9889-6ab6d89e5b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768645252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.768645252
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3886825626
Short name T243
Test name
Test status
Simulation time 4626027821 ps
CPU time 20.66 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:47 PM PDT 24
Peak memory 200772 kb
Host smart-5f08d443-9857-4841-bd56-0ba5d4fff998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886825626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3886825626
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1053907804
Short name T531
Test name
Test status
Simulation time 126942142 ps
CPU time 1.7 seconds
Started Jul 07 05:28:26 PM PDT 24
Finished Jul 07 05:28:29 PM PDT 24
Peak memory 200164 kb
Host smart-a0384f9c-82c0-4c79-a121-5cbe050a3a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053907804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1053907804
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3987865009
Short name T488
Test name
Test status
Simulation time 109653341 ps
CPU time 1 seconds
Started Jul 07 05:28:16 PM PDT 24
Finished Jul 07 05:28:17 PM PDT 24
Peak memory 200156 kb
Host smart-08a88c9f-a1d1-4fb4-a40b-7a8953a2cc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987865009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3987865009
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3651770325
Short name T416
Test name
Test status
Simulation time 69646676 ps
CPU time 0.81 seconds
Started Jul 07 05:28:22 PM PDT 24
Finished Jul 07 05:28:23 PM PDT 24
Peak memory 199932 kb
Host smart-7904b387-4ad7-48d1-858f-97047d7e5c63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651770325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3651770325
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2111128823
Short name T348
Test name
Test status
Simulation time 2352627564 ps
CPU time 8.53 seconds
Started Jul 07 05:28:30 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 221772 kb
Host smart-34a932cd-c3eb-42da-8360-f6068a98fb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111128823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2111128823
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1720767330
Short name T479
Test name
Test status
Simulation time 245072463 ps
CPU time 1.09 seconds
Started Jul 07 05:28:16 PM PDT 24
Finished Jul 07 05:28:17 PM PDT 24
Peak memory 217480 kb
Host smart-7722cf8e-1f5f-4be2-a036-818cf29c039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720767330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1720767330
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.4115945817
Short name T291
Test name
Test status
Simulation time 223985490 ps
CPU time 0.86 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:26 PM PDT 24
Peak memory 199968 kb
Host smart-97986c14-e04c-4de3-81b6-0997b27d0f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115945817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.4115945817
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3020434130
Short name T90
Test name
Test status
Simulation time 1394534029 ps
CPU time 5.95 seconds
Started Jul 07 05:28:27 PM PDT 24
Finished Jul 07 05:28:33 PM PDT 24
Peak memory 200404 kb
Host smart-6af659ba-b796-4906-b280-cae8359019cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020434130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3020434130
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1791079766
Short name T308
Test name
Test status
Simulation time 175947096 ps
CPU time 1.19 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:27 PM PDT 24
Peak memory 200172 kb
Host smart-8a50514a-4538-44c5-ad97-7576cd774ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791079766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1791079766
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2100190062
Short name T164
Test name
Test status
Simulation time 197159848 ps
CPU time 1.42 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:27 PM PDT 24
Peak memory 200344 kb
Host smart-5bcb02d6-f9cd-4baa-a761-1470ec32d265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100190062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2100190062
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3466811389
Short name T208
Test name
Test status
Simulation time 4717743421 ps
CPU time 21.52 seconds
Started Jul 07 05:28:29 PM PDT 24
Finished Jul 07 05:28:51 PM PDT 24
Peak memory 208664 kb
Host smart-7dbbd069-9cb2-46d5-9b82-0c4b2d77b6af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466811389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3466811389
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.4003438890
Short name T197
Test name
Test status
Simulation time 128658447 ps
CPU time 1.66 seconds
Started Jul 07 05:28:13 PM PDT 24
Finished Jul 07 05:28:16 PM PDT 24
Peak memory 208332 kb
Host smart-41d851bf-c696-4e97-add8-fff5710d0fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003438890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.4003438890
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3734839396
Short name T393
Test name
Test status
Simulation time 137371410 ps
CPU time 1.05 seconds
Started Jul 07 05:28:27 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 200164 kb
Host smart-c91d8b4e-c728-413a-b716-0f63db4ad3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734839396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3734839396
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1742292968
Short name T245
Test name
Test status
Simulation time 84440229 ps
CPU time 0.83 seconds
Started Jul 07 05:28:16 PM PDT 24
Finished Jul 07 05:28:17 PM PDT 24
Peak memory 199872 kb
Host smart-e8bde28b-ec86-4f30-8765-4b7c0690a559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742292968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1742292968
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2913567305
Short name T435
Test name
Test status
Simulation time 2183847493 ps
CPU time 7.24 seconds
Started Jul 07 05:28:28 PM PDT 24
Finished Jul 07 05:28:36 PM PDT 24
Peak memory 221820 kb
Host smart-9bccc037-83ce-4658-9e5b-35dbec32c5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913567305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2913567305
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1640015917
Short name T305
Test name
Test status
Simulation time 244778803 ps
CPU time 1.14 seconds
Started Jul 07 05:28:23 PM PDT 24
Finished Jul 07 05:28:25 PM PDT 24
Peak memory 217524 kb
Host smart-72c42eb1-b1c2-4422-9b52-4d3f4455994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640015917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1640015917
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.4198764987
Short name T317
Test name
Test status
Simulation time 163666118 ps
CPU time 0.81 seconds
Started Jul 07 05:28:31 PM PDT 24
Finished Jul 07 05:28:32 PM PDT 24
Peak memory 199980 kb
Host smart-e98e6073-d0c1-4f26-a325-7f2bc4227149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198764987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.4198764987
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.459619240
Short name T443
Test name
Test status
Simulation time 1299582118 ps
CPU time 5.23 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:37 PM PDT 24
Peak memory 200444 kb
Host smart-7cabcfe2-4796-41e3-abab-5e334b2a3335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459619240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.459619240
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.780533788
Short name T425
Test name
Test status
Simulation time 189704805 ps
CPU time 1.17 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:26 PM PDT 24
Peak memory 200124 kb
Host smart-d9ac6385-36ab-4eda-85d8-417134104a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780533788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.780533788
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3779447217
Short name T365
Test name
Test status
Simulation time 246949694 ps
CPU time 1.45 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:26 PM PDT 24
Peak memory 200352 kb
Host smart-2c530482-afc2-4932-95e7-edcc68939fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779447217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3779447217
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.146077065
Short name T377
Test name
Test status
Simulation time 2264920535 ps
CPU time 8.39 seconds
Started Jul 07 05:28:29 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 200512 kb
Host smart-87203a13-82ca-4dd7-a75d-697c761145af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146077065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.146077065
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2128532983
Short name T151
Test name
Test status
Simulation time 140981049 ps
CPU time 1.81 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:34 PM PDT 24
Peak memory 200156 kb
Host smart-258f6bdc-cfc4-4c76-b050-2c9477041c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128532983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2128532983
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2496762109
Short name T484
Test name
Test status
Simulation time 208857818 ps
CPU time 1.19 seconds
Started Jul 07 05:28:33 PM PDT 24
Finished Jul 07 05:28:35 PM PDT 24
Peak memory 200140 kb
Host smart-62cc9e59-d50e-4aa7-bc95-9648d1896eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496762109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2496762109
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1174512240
Short name T146
Test name
Test status
Simulation time 88862167 ps
CPU time 0.78 seconds
Started Jul 07 05:27:13 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 199892 kb
Host smart-bb50299c-e740-4980-ad7c-324297a2fee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174512240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1174512240
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3904346646
Short name T25
Test name
Test status
Simulation time 1226954375 ps
CPU time 5.16 seconds
Started Jul 07 05:27:13 PM PDT 24
Finished Jul 07 05:27:19 PM PDT 24
Peak memory 216860 kb
Host smart-21357e27-0f6d-4e8c-8d01-4dfe671c2449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904346646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3904346646
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1319387118
Short name T165
Test name
Test status
Simulation time 245662050 ps
CPU time 1.05 seconds
Started Jul 07 05:27:14 PM PDT 24
Finished Jul 07 05:27:16 PM PDT 24
Peak memory 217516 kb
Host smart-38698c19-3d6f-479e-9791-b9b4c931e807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319387118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1319387118
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.867250720
Short name T426
Test name
Test status
Simulation time 164246890 ps
CPU time 0.89 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 199972 kb
Host smart-b3af9955-4ab0-4e68-a8d5-a46e08385b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867250720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.867250720
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3124118380
Short name T447
Test name
Test status
Simulation time 1663377552 ps
CPU time 6.38 seconds
Started Jul 07 05:27:25 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200432 kb
Host smart-f4692046-c045-4505-990b-65edc3d13919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124118380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3124118380
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2997164370
Short name T35
Test name
Test status
Simulation time 95319292 ps
CPU time 1.03 seconds
Started Jul 07 05:27:11 PM PDT 24
Finished Jul 07 05:27:12 PM PDT 24
Peak memory 200152 kb
Host smart-5f06c4d3-faa6-44ae-b1f9-d757cad5d184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997164370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2997164370
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2970639880
Short name T256
Test name
Test status
Simulation time 118283996 ps
CPU time 1.14 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 200396 kb
Host smart-016d94c1-50b1-4352-8084-a700e87d171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970639880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2970639880
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1781598747
Short name T140
Test name
Test status
Simulation time 1864454151 ps
CPU time 7.22 seconds
Started Jul 07 05:27:26 PM PDT 24
Finished Jul 07 05:27:34 PM PDT 24
Peak memory 200700 kb
Host smart-48336bcc-1ab0-4819-9bcb-be02650bcda1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781598747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1781598747
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.4182631940
Short name T490
Test name
Test status
Simulation time 386443330 ps
CPU time 2.05 seconds
Started Jul 07 05:27:21 PM PDT 24
Finished Jul 07 05:27:23 PM PDT 24
Peak memory 200144 kb
Host smart-1e33604c-9e83-406d-b54c-607111a5cd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182631940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.4182631940
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1362216782
Short name T515
Test name
Test status
Simulation time 108115647 ps
CPU time 0.87 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:13 PM PDT 24
Peak memory 200000 kb
Host smart-0bbbbf29-03bc-429f-8fb2-a7e220cbf315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362216782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1362216782
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2567453404
Short name T162
Test name
Test status
Simulation time 79832585 ps
CPU time 0.81 seconds
Started Jul 07 05:27:14 PM PDT 24
Finished Jul 07 05:27:15 PM PDT 24
Peak memory 199924 kb
Host smart-98f97695-a88a-4425-8ff1-b7247a7a8515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567453404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2567453404
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3445708307
Short name T56
Test name
Test status
Simulation time 1223534570 ps
CPU time 5.67 seconds
Started Jul 07 05:27:18 PM PDT 24
Finished Jul 07 05:27:24 PM PDT 24
Peak memory 216900 kb
Host smart-02e2eda3-d524-4fbd-9ffb-a993b6362260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445708307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3445708307
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1653695451
Short name T465
Test name
Test status
Simulation time 243370517 ps
CPU time 1.11 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:24 PM PDT 24
Peak memory 217528 kb
Host smart-d7ec5d80-42a7-4f16-b82a-099d4d96d2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653695451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1653695451
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.698175959
Short name T5
Test name
Test status
Simulation time 87022527 ps
CPU time 0.73 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 199944 kb
Host smart-07a8e845-bcf9-4cb2-ac4d-81ec3a3ac37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698175959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.698175959
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3670918087
Short name T34
Test name
Test status
Simulation time 1455910978 ps
CPU time 5.55 seconds
Started Jul 07 05:27:26 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200336 kb
Host smart-580e8f87-40f8-4ba2-8998-6cdca9b1b5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670918087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3670918087
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.380362175
Short name T1
Test name
Test status
Simulation time 164658412 ps
CPU time 1.17 seconds
Started Jul 07 05:27:25 PM PDT 24
Finished Jul 07 05:27:27 PM PDT 24
Peak memory 200096 kb
Host smart-fd9354a9-3e69-4bb2-86b4-234747016109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380362175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.380362175
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1377684899
Short name T419
Test name
Test status
Simulation time 256289710 ps
CPU time 1.48 seconds
Started Jul 07 05:27:14 PM PDT 24
Finished Jul 07 05:27:16 PM PDT 24
Peak memory 200328 kb
Host smart-33d84741-9dad-4dcc-a29c-2f223a389121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377684899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1377684899
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.39031344
Short name T361
Test name
Test status
Simulation time 5035905669 ps
CPU time 19.93 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:49 PM PDT 24
Peak memory 208944 kb
Host smart-1aa1dd4e-fe7c-460a-8b20-0f761de4d82a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39031344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.39031344
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1677732887
Short name T137
Test name
Test status
Simulation time 133026394 ps
CPU time 1.66 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:34 PM PDT 24
Peak memory 200096 kb
Host smart-d6bd3a41-ec6e-4879-aed0-0aec232d1cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677732887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1677732887
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1240346354
Short name T529
Test name
Test status
Simulation time 129451234 ps
CPU time 1.03 seconds
Started Jul 07 05:27:18 PM PDT 24
Finished Jul 07 05:27:19 PM PDT 24
Peak memory 200076 kb
Host smart-462155e6-a841-41c4-be72-559222becd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240346354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1240346354
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2179463126
Short name T210
Test name
Test status
Simulation time 70373874 ps
CPU time 0.73 seconds
Started Jul 07 05:27:19 PM PDT 24
Finished Jul 07 05:27:20 PM PDT 24
Peak memory 199876 kb
Host smart-f141218a-4c9d-4024-9dcd-926733acfc66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179463126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2179463126
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.4017862874
Short name T344
Test name
Test status
Simulation time 1903509375 ps
CPU time 7.34 seconds
Started Jul 07 05:27:24 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 217468 kb
Host smart-7591874c-5905-4f80-8f4f-1343799b0e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017862874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.4017862874
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1354282168
Short name T430
Test name
Test status
Simulation time 244916522 ps
CPU time 1.09 seconds
Started Jul 07 05:27:23 PM PDT 24
Finished Jul 07 05:27:25 PM PDT 24
Peak memory 217444 kb
Host smart-4c22c636-66ce-49cf-ac73-f683ed02eb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354282168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1354282168
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1273069905
Short name T17
Test name
Test status
Simulation time 163400760 ps
CPU time 0.83 seconds
Started Jul 07 05:27:21 PM PDT 24
Finished Jul 07 05:27:22 PM PDT 24
Peak memory 199980 kb
Host smart-ab4f0fee-910f-4c3c-8c31-cfe955a889fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273069905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1273069905
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.474746022
Short name T516
Test name
Test status
Simulation time 1011827046 ps
CPU time 4.75 seconds
Started Jul 07 05:27:14 PM PDT 24
Finished Jul 07 05:27:20 PM PDT 24
Peak memory 200436 kb
Host smart-944f2d83-67df-4de4-a281-6d40204c2397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474746022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.474746022
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2591244134
Short name T203
Test name
Test status
Simulation time 152022582 ps
CPU time 1.11 seconds
Started Jul 07 05:27:12 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 200092 kb
Host smart-5a151af7-3e74-4adf-b1ca-25e9e7eed6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591244134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2591244134
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3893062765
Short name T352
Test name
Test status
Simulation time 112192862 ps
CPU time 1.21 seconds
Started Jul 07 05:27:26 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 200300 kb
Host smart-6ab7b858-890e-4c04-8cae-8d96754804d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893062765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3893062765
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3664758073
Short name T354
Test name
Test status
Simulation time 10090649615 ps
CPU time 37.28 seconds
Started Jul 07 05:27:29 PM PDT 24
Finished Jul 07 05:28:08 PM PDT 24
Peak memory 208656 kb
Host smart-34f51446-bc66-4ed4-abec-ad28c6108732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664758073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3664758073
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2265882884
Short name T65
Test name
Test status
Simulation time 354834950 ps
CPU time 2.51 seconds
Started Jul 07 05:27:25 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 200032 kb
Host smart-790126b8-c13f-4595-84c2-14f7baeb0248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265882884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2265882884
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2322847028
Short name T487
Test name
Test status
Simulation time 65315075 ps
CPU time 0.81 seconds
Started Jul 07 05:27:13 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 200116 kb
Host smart-a9cfaa90-9066-408c-ad51-2aeb4e5ef596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322847028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2322847028
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.228304907
Short name T357
Test name
Test status
Simulation time 80783749 ps
CPU time 0.82 seconds
Started Jul 07 05:27:27 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 200232 kb
Host smart-4889fa22-8a90-450f-bc6c-00119cd9b8b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228304907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.228304907
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2573026986
Short name T202
Test name
Test status
Simulation time 2348600176 ps
CPU time 7.68 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:30 PM PDT 24
Peak memory 217900 kb
Host smart-56a3d015-bf34-4a87-a34c-70d964baa1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573026986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2573026986
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.409774912
Short name T205
Test name
Test status
Simulation time 244291255 ps
CPU time 1.02 seconds
Started Jul 07 05:27:39 PM PDT 24
Finished Jul 07 05:27:41 PM PDT 24
Peak memory 217448 kb
Host smart-c11ded94-30b9-44ff-a0e6-4b86b1bd7508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409774912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.409774912
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2709880588
Short name T520
Test name
Test status
Simulation time 163454307 ps
CPU time 0.94 seconds
Started Jul 07 05:27:26 PM PDT 24
Finished Jul 07 05:27:27 PM PDT 24
Peak memory 199972 kb
Host smart-b33b1371-ab66-488f-8bf8-e9f664eb3ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709880588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2709880588
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.676644762
Short name T21
Test name
Test status
Simulation time 1442500371 ps
CPU time 5.34 seconds
Started Jul 07 05:27:20 PM PDT 24
Finished Jul 07 05:27:25 PM PDT 24
Peak memory 200480 kb
Host smart-1acaa6e8-4085-4daf-a906-05e226da481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676644762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.676644762
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4282273446
Short name T11
Test name
Test status
Simulation time 98826168 ps
CPU time 1 seconds
Started Jul 07 05:27:20 PM PDT 24
Finished Jul 07 05:27:21 PM PDT 24
Peak memory 200408 kb
Host smart-ef22c773-35f6-4086-8d12-265ee75ecd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282273446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4282273446
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2687678998
Short name T60
Test name
Test status
Simulation time 243662553 ps
CPU time 1.45 seconds
Started Jul 07 05:27:24 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 200348 kb
Host smart-40ed1b93-b0c6-4f8e-8d8a-e8898f3ec654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687678998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2687678998
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2598275393
Short name T53
Test name
Test status
Simulation time 3195431531 ps
CPU time 14.02 seconds
Started Jul 07 05:27:15 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 208596 kb
Host smart-d51609ad-da7d-4590-9309-e8947f0716fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598275393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2598275393
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3291957546
Short name T323
Test name
Test status
Simulation time 338791512 ps
CPU time 1.88 seconds
Started Jul 07 05:27:21 PM PDT 24
Finished Jul 07 05:27:24 PM PDT 24
Peak memory 200144 kb
Host smart-7d9fd8b8-0201-44ef-b1bb-67aba4a14329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291957546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3291957546
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1983761801
Short name T454
Test name
Test status
Simulation time 229782838 ps
CPU time 1.33 seconds
Started Jul 07 05:27:23 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 200160 kb
Host smart-d9d221d5-064d-4364-8d01-7daaf48f809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983761801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1983761801
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.982935490
Short name T524
Test name
Test status
Simulation time 61244695 ps
CPU time 0.74 seconds
Started Jul 07 05:27:26 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 199952 kb
Host smart-33c469a0-46d8-446b-b3f2-dedd7b2b0baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982935490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.982935490
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4049440115
Short name T196
Test name
Test status
Simulation time 2352351143 ps
CPU time 8.06 seconds
Started Jul 07 05:27:19 PM PDT 24
Finished Jul 07 05:27:28 PM PDT 24
Peak memory 217780 kb
Host smart-3289d5bc-743e-4e98-9411-e82ece1619b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049440115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4049440115
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2865069402
Short name T328
Test name
Test status
Simulation time 244111614 ps
CPU time 1.07 seconds
Started Jul 07 05:27:22 PM PDT 24
Finished Jul 07 05:27:24 PM PDT 24
Peak memory 217528 kb
Host smart-f37c1d11-184c-4e16-8679-ea41524b7e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865069402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2865069402
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1317776401
Short name T539
Test name
Test status
Simulation time 96284657 ps
CPU time 0.78 seconds
Started Jul 07 05:27:30 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 200228 kb
Host smart-ffec140c-6185-4e46-abbb-12429258bfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317776401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1317776401
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.686955259
Short name T456
Test name
Test status
Simulation time 1745205457 ps
CPU time 6.95 seconds
Started Jul 07 05:27:13 PM PDT 24
Finished Jul 07 05:27:21 PM PDT 24
Peak memory 200724 kb
Host smart-73bd17ad-9356-458a-818f-f01f8421d360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686955259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.686955259
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2104719952
Short name T163
Test name
Test status
Simulation time 113734669 ps
CPU time 0.98 seconds
Started Jul 07 05:27:15 PM PDT 24
Finished Jul 07 05:27:17 PM PDT 24
Peak memory 200152 kb
Host smart-69917edf-85f3-47ec-855c-1e23dc6d1b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104719952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2104719952
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2126193881
Short name T272
Test name
Test status
Simulation time 191980737 ps
CPU time 1.39 seconds
Started Jul 07 05:27:21 PM PDT 24
Finished Jul 07 05:27:23 PM PDT 24
Peak memory 200340 kb
Host smart-436128b9-a738-48ae-8bfb-3d43bc32f16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126193881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2126193881
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.4197555186
Short name T311
Test name
Test status
Simulation time 7077500386 ps
CPU time 23.83 seconds
Started Jul 07 05:27:32 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 200416 kb
Host smart-f4583558-c07e-4a6d-b754-392f962ab237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197555186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.4197555186
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3559060537
Short name T44
Test name
Test status
Simulation time 149240304 ps
CPU time 1.92 seconds
Started Jul 07 05:27:28 PM PDT 24
Finished Jul 07 05:27:31 PM PDT 24
Peak memory 200144 kb
Host smart-1a0aa504-3c2f-4b85-88d2-bacd6222684a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559060537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3559060537
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3721215588
Short name T186
Test name
Test status
Simulation time 269190564 ps
CPU time 1.52 seconds
Started Jul 07 05:27:35 PM PDT 24
Finished Jul 07 05:27:39 PM PDT 24
Peak memory 200296 kb
Host smart-e68c64ed-e193-4d0f-861e-274283341cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721215588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3721215588
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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