Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8155

1

T2

15

T4

7

T7

20

auto[1]

10970

1

T2

86

T4

1

T6

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5898	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6488	1			T1	1		T2	27		T3	1
reset_info_cp[2]	2977	1			T2	17		T6	1		T7	14
reset_info_cp[4]	3823	1			T2	19		T6	1		T7	17
reset_info_cp[8]	115	1			T7	1		T11	2		T12	1
reset_info_cp[16]	119	1			T2	2		T6	1		T9	2
reset_info_cp[32]	107	1			T2	1		T7	1		T15	1
reset_info_cp[64]	111	1			T7	3		T9	1		T11	1
reset_info_cp[128]	106	1			T11	1		T12	2		T13	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3110	1			T2	15		T7	20		T9	20
reset_info_cp[1]	auto[1]	2759	1			T2	11		T6	1		T7	6
reset_info_cp[2]	auto[0]	924	1			T13	7		T15	21		T73	4
reset_info_cp[2]	auto[1]	2053	1			T2	17		T6	1		T7	14
reset_info_cp[4]	auto[0]	1434	1			T13	4		T15	48		T73	6
reset_info_cp[4]	auto[1]	2389	1			T2	19		T6	1		T7	17
reset_info_cp[8]	auto[0]	41	1			T11	2		T12	1		T14	1
reset_info_cp[8]	auto[1]	74	1			T7	1		T76	1		T91	1
reset_info_cp[16]	auto[0]	43	1			T12	2		T13	1		T14	1
reset_info_cp[16]	auto[1]	76	1			T2	2		T6	1		T9	2
reset_info_cp[32]	auto[0]	44	1			T15	1		T55	1		T28	1
reset_info_cp[32]	auto[1]	63	1			T2	1		T7	1		T74	1
reset_info_cp[64]	auto[0]	42	1			T11	1		T12	1		T13	1
reset_info_cp[64]	auto[1]	69	1			T7	3		T9	1		T26	1
reset_info_cp[128]	auto[0]	38	1			T11	1		T12	2		T13	1
reset_info_cp[128]	auto[1]	68	1			T26	1		T32	1		T44	1