Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 619
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T536 /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4273064980 Jul 09 05:42:34 PM PDT 24 Jul 09 05:42:42 PM PDT 24 1227952979 ps
T537 /workspace/coverage/default/44.rstmgr_sw_rst.1155557132 Jul 09 05:43:38 PM PDT 24 Jul 09 05:43:42 PM PDT 24 254245896 ps
T538 /workspace/coverage/default/43.rstmgr_alert_test.2434936751 Jul 09 05:43:32 PM PDT 24 Jul 09 05:43:35 PM PDT 24 66820754 ps
T539 /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1249012530 Jul 09 05:43:11 PM PDT 24 Jul 09 05:43:13 PM PDT 24 112486214 ps
T62 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3114300649 Jul 09 05:42:08 PM PDT 24 Jul 09 05:42:11 PM PDT 24 360490656 ps
T63 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2341715798 Jul 09 05:42:23 PM PDT 24 Jul 09 05:42:26 PM PDT 24 179622313 ps
T66 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2464227099 Jul 09 05:42:34 PM PDT 24 Jul 09 05:42:38 PM PDT 24 295153502 ps
T64 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2050173264 Jul 09 05:42:26 PM PDT 24 Jul 09 05:42:28 PM PDT 24 67983809 ps
T67 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4111533633 Jul 09 05:42:27 PM PDT 24 Jul 09 05:42:31 PM PDT 24 429484357 ps
T65 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2915183946 Jul 09 05:42:28 PM PDT 24 Jul 09 05:42:32 PM PDT 24 1098580935 ps
T69 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3657660159 Jul 09 05:42:31 PM PDT 24 Jul 09 05:42:33 PM PDT 24 156572599 ps
T84 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1911710481 Jul 09 05:42:22 PM PDT 24 Jul 09 05:42:24 PM PDT 24 481211213 ps
T85 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.432367377 Jul 09 05:42:21 PM PDT 24 Jul 09 05:42:23 PM PDT 24 128855368 ps
T97 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1401966912 Jul 09 05:42:31 PM PDT 24 Jul 09 05:42:33 PM PDT 24 82605867 ps
T86 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3321062808 Jul 09 05:42:26 PM PDT 24 Jul 09 05:42:29 PM PDT 24 955413988 ps
T87 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2337225471 Jul 09 05:42:27 PM PDT 24 Jul 09 05:42:29 PM PDT 24 181236857 ps
T98 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1199110178 Jul 09 05:42:19 PM PDT 24 Jul 09 05:42:21 PM PDT 24 58274260 ps
T99 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1933230743 Jul 09 05:42:17 PM PDT 24 Jul 09 05:42:19 PM PDT 24 76908217 ps
T115 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.336560919 Jul 09 05:42:19 PM PDT 24 Jul 09 05:42:23 PM PDT 24 811371688 ps
T100 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.545322179 Jul 09 05:42:26 PM PDT 24 Jul 09 05:42:27 PM PDT 24 70897326 ps
T540 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1549660284 Jul 09 05:42:20 PM PDT 24 Jul 09 05:42:22 PM PDT 24 86358017 ps
T541 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2253325254 Jul 09 05:42:12 PM PDT 24 Jul 09 05:42:16 PM PDT 24 357953443 ps
T101 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.998862941 Jul 09 05:42:28 PM PDT 24 Jul 09 05:42:30 PM PDT 24 135816189 ps
T88 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2328254317 Jul 09 05:42:21 PM PDT 24 Jul 09 05:42:23 PM PDT 24 192499689 ps
T89 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1658982759 Jul 09 05:42:12 PM PDT 24 Jul 09 05:42:15 PM PDT 24 179624931 ps
T90 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2891847449 Jul 09 05:42:27 PM PDT 24 Jul 09 05:42:31 PM PDT 24 969695406 ps
T542 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1272110126 Jul 09 05:42:12 PM PDT 24 Jul 09 05:42:22 PM PDT 24 2309136202 ps
T110 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.738941021 Jul 09 05:42:21 PM PDT 24 Jul 09 05:42:25 PM PDT 24 940292121 ps
T543 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.311669771 Jul 09 05:42:16 PM PDT 24 Jul 09 05:42:18 PM PDT 24 217273166 ps
T544 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4110891645 Jul 09 05:42:13 PM PDT 24 Jul 09 05:42:15 PM PDT 24 92399512 ps
T545 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3478571290 Jul 09 05:42:23 PM PDT 24 Jul 09 05:42:24 PM PDT 24 76161110 ps
T546 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.930849298 Jul 09 05:42:08 PM PDT 24 Jul 09 05:42:12 PM PDT 24 946124201 ps
T547 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1358685471 Jul 09 05:42:21 PM PDT 24 Jul 09 05:42:23 PM PDT 24 123734129 ps
T548 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.360792889 Jul 09 05:42:12 PM PDT 24 Jul 09 05:42:23 PM PDT 24 2282798277 ps
T102 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2512563542 Jul 09 05:42:08 PM PDT 24 Jul 09 05:42:09 PM PDT 24 93036119 ps
T549 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3206378444 Jul 09 05:42:15 PM PDT 24 Jul 09 05:42:16 PM PDT 24 66114768 ps
T106 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3371938306 Jul 09 05:42:17 PM PDT 24 Jul 09 05:42:19 PM PDT 24 199240513 ps
T550 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1533505622 Jul 09 05:42:26 PM PDT 24 Jul 09 05:42:28 PM PDT 24 67371286 ps
T551 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.501627274 Jul 09 05:42:19 PM PDT 24 Jul 09 05:42:21 PM PDT 24 123953511 ps
T108 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.827212577 Jul 09 05:42:15 PM PDT 24 Jul 09 05:42:19 PM PDT 24 912330588 ps
T103 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.219338302 Jul 09 05:42:25 PM PDT 24 Jul 09 05:42:26 PM PDT 24 63623572 ps
T104 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1601133039 Jul 09 05:42:28 PM PDT 24 Jul 09 05:42:30 PM PDT 24 209453838 ps
T113 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.584469514 Jul 09 05:42:17 PM PDT 24 Jul 09 05:42:20 PM PDT 24 353001523 ps
T105 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2332376553 Jul 09 05:42:27 PM PDT 24 Jul 09 05:42:29 PM PDT 24 151445830 ps
T552 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1967164000 Jul 09 05:42:10 PM PDT 24 Jul 09 05:42:12 PM PDT 24 74323640 ps
T553 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.496979467 Jul 09 05:42:31 PM PDT 24 Jul 09 05:42:33 PM PDT 24 59066038 ps
T554 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2252600030 Jul 09 05:42:34 PM PDT 24 Jul 09 05:42:37 PM PDT 24 194329829 ps
T555 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2201644640 Jul 09 05:42:09 PM PDT 24 Jul 09 05:42:11 PM PDT 24 117152646 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2855140348 Jul 09 05:42:10 PM PDT 24 Jul 09 05:42:13 PM PDT 24 217981301 ps
T114 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.684607425 Jul 09 05:42:14 PM PDT 24 Jul 09 05:42:16 PM PDT 24 99040972 ps
T557 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.636208485 Jul 09 05:42:24 PM PDT 24 Jul 09 05:42:27 PM PDT 24 190071830 ps
T558 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4194942293 Jul 09 05:42:34 PM PDT 24 Jul 09 05:42:36 PM PDT 24 73702533 ps
T559 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2014875790 Jul 09 05:42:09 PM PDT 24 Jul 09 05:42:11 PM PDT 24 86533810 ps
T560 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.723513906 Jul 09 05:42:35 PM PDT 24 Jul 09 05:42:38 PM PDT 24 225203016 ps
T561 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.914012271 Jul 09 05:42:09 PM PDT 24 Jul 09 05:42:12 PM PDT 24 420203730 ps
T122 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3151433370 Jul 09 05:42:13 PM PDT 24 Jul 09 05:42:18 PM PDT 24 935589678 ps
T562 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.339270708 Jul 09 05:42:05 PM PDT 24 Jul 09 05:42:06 PM PDT 24 100864027 ps
T563 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1515191910 Jul 09 05:42:25 PM PDT 24 Jul 09 05:42:26 PM PDT 24 154832164 ps
T564 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3960967320 Jul 09 05:42:23 PM PDT 24 Jul 09 05:42:25 PM PDT 24 118822412 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3002832904 Jul 09 05:42:13 PM PDT 24 Jul 09 05:42:16 PM PDT 24 361453448 ps
T566 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1190411477 Jul 09 05:42:20 PM PDT 24 Jul 09 05:42:23 PM PDT 24 458991696 ps
T567 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3927492120 Jul 09 05:45:12 PM PDT 24 Jul 09 05:45:16 PM PDT 24 304443234 ps
T568 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.963797961 Jul 09 05:42:09 PM PDT 24 Jul 09 05:42:12 PM PDT 24 152158029 ps
T569 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1929673411 Jul 09 05:42:21 PM PDT 24 Jul 09 05:42:23 PM PDT 24 124481470 ps
T570 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3123552929 Jul 09 05:42:09 PM PDT 24 Jul 09 05:42:14 PM PDT 24 1033626916 ps
T571 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3914563677 Jul 09 05:42:08 PM PDT 24 Jul 09 05:42:10 PM PDT 24 143201780 ps
T572 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.978617195 Jul 09 05:42:19 PM PDT 24 Jul 09 05:42:22 PM PDT 24 196450168 ps
T109 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2336148628 Jul 09 05:42:27 PM PDT 24 Jul 09 05:42:29 PM PDT 24 480038964 ps
T573 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2109723336 Jul 09 05:42:18 PM PDT 24 Jul 09 05:42:19 PM PDT 24 68780495 ps
T574 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4030647895 Jul 09 05:42:17 PM PDT 24 Jul 09 05:42:18 PM PDT 24 178151575 ps
T575 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.675024608 Jul 09 05:42:20 PM PDT 24 Jul 09 05:42:24 PM PDT 24 456539288 ps
T576 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1179549259 Jul 09 05:42:16 PM PDT 24 Jul 09 05:42:18 PM PDT 24 105166284 ps
T577 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.855386069 Jul 09 05:42:33 PM PDT 24 Jul 09 05:42:38 PM PDT 24 434081298 ps
T578 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1487404364 Jul 09 05:42:11 PM PDT 24 Jul 09 05:42:13 PM PDT 24 138579513 ps
T579 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.799699166 Jul 09 05:42:23 PM PDT 24 Jul 09 05:42:25 PM PDT 24 228529362 ps
T580 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3275715146 Jul 09 05:42:14 PM PDT 24 Jul 09 05:42:17 PM PDT 24 168160557 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4282877662 Jul 09 05:42:20 PM PDT 24 Jul 09 05:42:23 PM PDT 24 282414062 ps
T582 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1569321683 Jul 09 05:42:11 PM PDT 24 Jul 09 05:42:13 PM PDT 24 77065280 ps
T583 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3575557836 Jul 09 05:42:16 PM PDT 24 Jul 09 05:42:18 PM PDT 24 65038193 ps
T584 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1243901440 Jul 09 05:42:21 PM PDT 24 Jul 09 05:42:24 PM PDT 24 111118356 ps
T111 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.856154572 Jul 09 05:42:09 PM PDT 24 Jul 09 05:42:13 PM PDT 24 934575658 ps
T585 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.370028766 Jul 09 05:42:25 PM PDT 24 Jul 09 05:42:27 PM PDT 24 127450600 ps
T586 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.275449701 Jul 09 05:42:09 PM PDT 24 Jul 09 05:42:14 PM PDT 24 802779101 ps
T587 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.395753541 Jul 09 05:42:15 PM PDT 24 Jul 09 05:42:16 PM PDT 24 75813072 ps
T112 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4215952367 Jul 09 05:42:18 PM PDT 24 Jul 09 05:42:22 PM PDT 24 888587934 ps
T588 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1902307411 Jul 09 05:42:20 PM PDT 24 Jul 09 05:42:23 PM PDT 24 245023891 ps
T589 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.626700163 Jul 09 05:42:13 PM PDT 24 Jul 09 05:42:15 PM PDT 24 81899502 ps
T590 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3528497128 Jul 09 05:42:15 PM PDT 24 Jul 09 05:42:17 PM PDT 24 80773696 ps
T591 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3159283248 Jul 09 05:42:18 PM PDT 24 Jul 09 05:42:21 PM PDT 24 486952104 ps
T592 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.983238989 Jul 09 05:42:18 PM PDT 24 Jul 09 05:42:19 PM PDT 24 133204585 ps
T593 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2028075469 Jul 09 05:42:19 PM PDT 24 Jul 09 05:42:21 PM PDT 24 174665056 ps
T594 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3506272192 Jul 09 05:42:20 PM PDT 24 Jul 09 05:42:23 PM PDT 24 498908383 ps
T595 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2729609656 Jul 09 05:42:28 PM PDT 24 Jul 09 05:42:30 PM PDT 24 207372543 ps
T596 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2004200029 Jul 09 05:42:18 PM PDT 24 Jul 09 05:42:22 PM PDT 24 935836328 ps
T597 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1744763976 Jul 09 05:42:18 PM PDT 24 Jul 09 05:42:20 PM PDT 24 115565915 ps
T598 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2763960589 Jul 09 05:42:17 PM PDT 24 Jul 09 05:42:19 PM PDT 24 103942894 ps
T599 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1567688252 Jul 09 05:42:09 PM PDT 24 Jul 09 05:42:11 PM PDT 24 139190774 ps
T600 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1519057708 Jul 09 05:42:17 PM PDT 24 Jul 09 05:42:19 PM PDT 24 242954422 ps
T601 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4264528708 Jul 09 05:42:30 PM PDT 24 Jul 09 05:42:32 PM PDT 24 127993631 ps
T602 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3914220324 Jul 09 05:42:07 PM PDT 24 Jul 09 05:42:08 PM PDT 24 63277686 ps
T603 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.477410517 Jul 09 05:42:07 PM PDT 24 Jul 09 05:42:09 PM PDT 24 188608511 ps
T604 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2239913546 Jul 09 05:42:19 PM PDT 24 Jul 09 05:42:21 PM PDT 24 64035528 ps
T605 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1082099748 Jul 09 05:42:17 PM PDT 24 Jul 09 05:42:20 PM PDT 24 470832267 ps
T606 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1493803379 Jul 09 05:42:05 PM PDT 24 Jul 09 05:42:08 PM PDT 24 463747729 ps
T607 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2827741325 Jul 09 05:42:16 PM PDT 24 Jul 09 05:42:18 PM PDT 24 88665710 ps
T608 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2426209073 Jul 09 05:42:24 PM PDT 24 Jul 09 05:42:26 PM PDT 24 199780874 ps
T609 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2386189375 Jul 09 05:42:20 PM PDT 24 Jul 09 05:42:24 PM PDT 24 435497169 ps
T610 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2560052035 Jul 09 05:42:16 PM PDT 24 Jul 09 05:42:18 PM PDT 24 86069591 ps
T611 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1420109551 Jul 09 05:42:09 PM PDT 24 Jul 09 05:42:12 PM PDT 24 219493330 ps
T123 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4077439942 Jul 09 05:42:15 PM PDT 24 Jul 09 05:42:19 PM PDT 24 922996259 ps
T612 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.446312416 Jul 09 05:42:26 PM PDT 24 Jul 09 05:42:29 PM PDT 24 387402203 ps
T613 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1996560948 Jul 09 05:42:05 PM PDT 24 Jul 09 05:42:07 PM PDT 24 268038560 ps
T614 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.378001286 Jul 09 05:42:09 PM PDT 24 Jul 09 05:42:14 PM PDT 24 811878908 ps
T615 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.240791398 Jul 09 05:42:22 PM PDT 24 Jul 09 05:42:23 PM PDT 24 68238651 ps
T107 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1684036381 Jul 09 05:42:27 PM PDT 24 Jul 09 05:42:30 PM PDT 24 427750106 ps
T616 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2468911266 Jul 09 05:42:31 PM PDT 24 Jul 09 05:42:33 PM PDT 24 95286867 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1937782294 Jul 09 05:42:12 PM PDT 24 Jul 09 05:42:14 PM PDT 24 205733228 ps
T618 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3175246242 Jul 09 05:42:17 PM PDT 24 Jul 09 05:42:19 PM PDT 24 215865110 ps
T619 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.721806717 Jul 09 05:42:31 PM PDT 24 Jul 09 05:42:34 PM PDT 24 208203870 ps

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1569389618
Short name T7
Test name
Test status
Simulation time 1895837750 ps
CPU time 7.39 seconds
Started Jul 09 05:42:46 PM PDT 24
Finished Jul 09 05:42:55 PM PDT 24
Peak memory 221660 kb
Host smart-7b01711b-6d15-4cf2-9b29-fd4bf70fdf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569389618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1569389618
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.501431675
Short name T15
Test name
Test status
Simulation time 10437146401 ps
CPU time 34.89 seconds
Started Jul 09 05:43:26 PM PDT 24
Finished Jul 09 05:44:02 PM PDT 24
Peak memory 200444 kb
Host smart-40021abb-6c54-43f9-96ef-7e7b707aef48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501431675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.501431675
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1381955484
Short name T30
Test name
Test status
Simulation time 138200809 ps
CPU time 1.73 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 200208 kb
Host smart-0fb2d9d6-8c29-4f4c-943d-5dde4c5e26d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381955484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1381955484
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2341715798
Short name T63
Test name
Test status
Simulation time 179622313 ps
CPU time 1.85 seconds
Started Jul 09 05:42:23 PM PDT 24
Finished Jul 09 05:42:26 PM PDT 24
Peak memory 216924 kb
Host smart-5cf54587-37e6-4f4b-870a-0f195dc5fe35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341715798 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2341715798
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3673647861
Short name T31
Test name
Test status
Simulation time 8409691327 ps
CPU time 13.02 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:42:44 PM PDT 24
Peak memory 217192 kb
Host smart-84721531-ecc9-4241-a72a-69885ea0ebb2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673647861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3673647861
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2891847449
Short name T90
Test name
Test status
Simulation time 969695406 ps
CPU time 3.23 seconds
Started Jul 09 05:42:27 PM PDT 24
Finished Jul 09 05:42:31 PM PDT 24
Peak memory 200760 kb
Host smart-79807beb-ccc3-458b-8f2f-3670d31c8567
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891847449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2891847449
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1267700067
Short name T53
Test name
Test status
Simulation time 71246564 ps
CPU time 0.81 seconds
Started Jul 09 05:42:44 PM PDT 24
Finished Jul 09 05:42:46 PM PDT 24
Peak memory 199984 kb
Host smart-751d838b-12b2-4e72-9f03-7b0021df77c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267700067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1267700067
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3617755389
Short name T33
Test name
Test status
Simulation time 1212834688 ps
CPU time 5.56 seconds
Started Jul 09 05:42:51 PM PDT 24
Finished Jul 09 05:42:59 PM PDT 24
Peak memory 221768 kb
Host smart-bfec6fd0-a1ca-45c1-9e4e-dc86478c652f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617755389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3617755389
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3149302908
Short name T56
Test name
Test status
Simulation time 156540628 ps
CPU time 1.12 seconds
Started Jul 09 05:42:35 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 200180 kb
Host smart-131864e7-4c87-47d1-ae59-dac91a79ec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149302908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3149302908
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2219784102
Short name T80
Test name
Test status
Simulation time 9747116762 ps
CPU time 36 seconds
Started Jul 09 05:42:51 PM PDT 24
Finished Jul 09 05:43:30 PM PDT 24
Peak memory 208660 kb
Host smart-2ad66f78-aac6-4073-9ed2-0b792152cce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219784102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2219784102
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2336148628
Short name T109
Test name
Test status
Simulation time 480038964 ps
CPU time 1.93 seconds
Started Jul 09 05:42:27 PM PDT 24
Finished Jul 09 05:42:29 PM PDT 24
Peak memory 200392 kb
Host smart-7b458389-c4ab-4ebc-b643-3d7d3f47af09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336148628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2336148628
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.938402191
Short name T55
Test name
Test status
Simulation time 250280920 ps
CPU time 1.48 seconds
Started Jul 09 05:42:48 PM PDT 24
Finished Jul 09 05:42:52 PM PDT 24
Peak memory 200080 kb
Host smart-64ed7a0f-4b3f-40f6-906d-d970fffc34ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938402191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.938402191
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.4204430630
Short name T35
Test name
Test status
Simulation time 2384625287 ps
CPU time 8.1 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:44 PM PDT 24
Peak memory 217912 kb
Host smart-fc52ab04-5fb3-4840-9148-d78dc5bec62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204430630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.4204430630
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2464227099
Short name T66
Test name
Test status
Simulation time 295153502 ps
CPU time 2.33 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 212272 kb
Host smart-688deb7f-b1ef-4184-8b86-2912b73c5f12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464227099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2464227099
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2512563542
Short name T102
Test name
Test status
Simulation time 93036119 ps
CPU time 0.88 seconds
Started Jul 09 05:42:08 PM PDT 24
Finished Jul 09 05:42:09 PM PDT 24
Peak memory 200260 kb
Host smart-39f26f41-c34f-4f4f-bee6-6d1f9c2cdb4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512563542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2512563542
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.914364107
Short name T16
Test name
Test status
Simulation time 124787700 ps
CPU time 0.8 seconds
Started Jul 09 05:42:46 PM PDT 24
Finished Jul 09 05:42:49 PM PDT 24
Peak memory 199956 kb
Host smart-89c0e622-ccf3-4fd1-9e07-eef2ef2130f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914364107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.914364107
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2077655912
Short name T5
Test name
Test status
Simulation time 245611362 ps
CPU time 1.03 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:36 PM PDT 24
Peak memory 217548 kb
Host smart-292b621d-7f5f-470f-8fb7-a3b9a5145909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077655912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2077655912
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1493803379
Short name T606
Test name
Test status
Simulation time 463747729 ps
CPU time 1.91 seconds
Started Jul 09 05:42:05 PM PDT 24
Finished Jul 09 05:42:08 PM PDT 24
Peak memory 208688 kb
Host smart-f1a61d83-6a21-4bb9-b285-222623c32fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493803379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1493803379
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1684036381
Short name T107
Test name
Test status
Simulation time 427750106 ps
CPU time 1.89 seconds
Started Jul 09 05:42:27 PM PDT 24
Finished Jul 09 05:42:30 PM PDT 24
Peak memory 200364 kb
Host smart-3536756c-970f-4d5b-b990-358b7600e35e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684036381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1684036381
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2253325254
Short name T541
Test name
Test status
Simulation time 357953443 ps
CPU time 2.52 seconds
Started Jul 09 05:42:12 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 200472 kb
Host smart-7c9be9f1-6cc4-464c-a20a-5cf81b109e31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253325254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
253325254
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.378001286
Short name T614
Test name
Test status
Simulation time 811878908 ps
CPU time 4.45 seconds
Started Jul 09 05:42:09 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 200432 kb
Host smart-a196d862-13a6-44eb-94f3-c4eee4e3eb6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378001286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.378001286
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.339270708
Short name T562
Test name
Test status
Simulation time 100864027 ps
CPU time 0.83 seconds
Started Jul 09 05:42:05 PM PDT 24
Finished Jul 09 05:42:06 PM PDT 24
Peak memory 200296 kb
Host smart-89033bfd-749d-4666-b352-ba9de79df1c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339270708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.339270708
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2201644640
Short name T555
Test name
Test status
Simulation time 117152646 ps
CPU time 1.03 seconds
Started Jul 09 05:42:09 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 200440 kb
Host smart-cd1ada1f-c16e-4a32-bc2e-637167e31d5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201644640 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2201644640
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2014875790
Short name T559
Test name
Test status
Simulation time 86533810 ps
CPU time 1.05 seconds
Started Jul 09 05:42:09 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 200252 kb
Host smart-aac3044b-724b-42c0-a6e9-314a781572f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014875790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2014875790
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1996560948
Short name T613
Test name
Test status
Simulation time 268038560 ps
CPU time 1.94 seconds
Started Jul 09 05:42:05 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 210744 kb
Host smart-0f58b6d5-fb92-497f-8d14-c307594d6430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996560948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1996560948
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2855140348
Short name T556
Test name
Test status
Simulation time 217981301 ps
CPU time 1.57 seconds
Started Jul 09 05:42:10 PM PDT 24
Finished Jul 09 05:42:13 PM PDT 24
Peak memory 200432 kb
Host smart-af6cf4b5-40f5-4531-9ca8-358ab50d3bef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855140348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
855140348
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3123552929
Short name T570
Test name
Test status
Simulation time 1033626916 ps
CPU time 4.93 seconds
Started Jul 09 05:42:09 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 216756 kb
Host smart-0606049f-0c7c-4938-8189-f263eb9fe54a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123552929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
123552929
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1567688252
Short name T599
Test name
Test status
Simulation time 139190774 ps
CPU time 0.92 seconds
Started Jul 09 05:42:09 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 200272 kb
Host smart-7c0d0e15-4dcc-4f0a-b546-b5d6e67cee08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567688252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
567688252
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.477410517
Short name T603
Test name
Test status
Simulation time 188608511 ps
CPU time 1.68 seconds
Started Jul 09 05:42:07 PM PDT 24
Finished Jul 09 05:42:09 PM PDT 24
Peak memory 208840 kb
Host smart-c6b1605b-899d-471d-9d1f-2a7647022327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477410517 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.477410517
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3914220324
Short name T602
Test name
Test status
Simulation time 63277686 ps
CPU time 0.8 seconds
Started Jul 09 05:42:07 PM PDT 24
Finished Jul 09 05:42:08 PM PDT 24
Peak memory 200280 kb
Host smart-7c75b865-dc43-4743-8a48-0c24ee91a32a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914220324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3914220324
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1420109551
Short name T611
Test name
Test status
Simulation time 219493330 ps
CPU time 1.53 seconds
Started Jul 09 05:42:09 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 200416 kb
Host smart-39507108-d552-4ced-9e9f-a414b672a9e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420109551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1420109551
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.914012271
Short name T561
Test name
Test status
Simulation time 420203730 ps
CPU time 3.05 seconds
Started Jul 09 05:42:09 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 216768 kb
Host smart-c5677f4a-0ad1-4588-9677-5ab6e44bf6db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914012271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.914012271
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.856154572
Short name T111
Test name
Test status
Simulation time 934575658 ps
CPU time 3.46 seconds
Started Jul 09 05:42:09 PM PDT 24
Finished Jul 09 05:42:13 PM PDT 24
Peak memory 200556 kb
Host smart-d5788c8e-f014-4b17-8797-eb0d55330bff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856154572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
856154572
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.501627274
Short name T551
Test name
Test status
Simulation time 123953511 ps
CPU time 1.2 seconds
Started Jul 09 05:42:19 PM PDT 24
Finished Jul 09 05:42:21 PM PDT 24
Peak memory 208572 kb
Host smart-daf63d9a-033e-4697-a8b1-5eec5ae82cd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501627274 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.501627274
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1933230743
Short name T99
Test name
Test status
Simulation time 76908217 ps
CPU time 0.81 seconds
Started Jul 09 05:42:17 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 200268 kb
Host smart-3fdd5188-6509-40a1-83f0-089f82e43a45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933230743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1933230743
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1902307411
Short name T588
Test name
Test status
Simulation time 245023891 ps
CPU time 1.51 seconds
Started Jul 09 05:42:20 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 216864 kb
Host smart-739f7139-e8af-46fb-ad08-f2d1fb16e738
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902307411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1902307411
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2386189375
Short name T609
Test name
Test status
Simulation time 435497169 ps
CPU time 3.38 seconds
Started Jul 09 05:42:20 PM PDT 24
Finished Jul 09 05:42:24 PM PDT 24
Peak memory 208644 kb
Host smart-7942d71e-aa3b-42c1-9b0a-0d91c784da4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386189375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2386189375
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1190411477
Short name T566
Test name
Test status
Simulation time 458991696 ps
CPU time 1.78 seconds
Started Jul 09 05:42:20 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 200512 kb
Host smart-517fa298-46db-4b60-b02e-cb11499cd79c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190411477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1190411477
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2328254317
Short name T88
Test name
Test status
Simulation time 192499689 ps
CPU time 1.28 seconds
Started Jul 09 05:42:21 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 208628 kb
Host smart-f1ef325c-00ca-4399-a5cb-cf70607946bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328254317 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2328254317
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.545322179
Short name T100
Test name
Test status
Simulation time 70897326 ps
CPU time 0.81 seconds
Started Jul 09 05:42:26 PM PDT 24
Finished Jul 09 05:42:27 PM PDT 24
Peak memory 200268 kb
Host smart-38c34f97-c01f-4854-92eb-e602692bd41d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545322179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.545322179
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1929673411
Short name T569
Test name
Test status
Simulation time 124481470 ps
CPU time 1.08 seconds
Started Jul 09 05:42:21 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 200312 kb
Host smart-f66315c6-c485-41cc-8c0c-37228f0a3c2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929673411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1929673411
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.675024608
Short name T575
Test name
Test status
Simulation time 456539288 ps
CPU time 2.92 seconds
Started Jul 09 05:42:20 PM PDT 24
Finished Jul 09 05:42:24 PM PDT 24
Peak memory 208652 kb
Host smart-25419f02-6450-4908-809e-33efed502deb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675024608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.675024608
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3159283248
Short name T591
Test name
Test status
Simulation time 486952104 ps
CPU time 1.98 seconds
Started Jul 09 05:42:18 PM PDT 24
Finished Jul 09 05:42:21 PM PDT 24
Peak memory 200508 kb
Host smart-2c818805-c13e-4bc7-ac41-fb2353504305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159283248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3159283248
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.432367377
Short name T85
Test name
Test status
Simulation time 128855368 ps
CPU time 1.43 seconds
Started Jul 09 05:42:21 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 208564 kb
Host smart-084df4d9-b97e-444f-9c32-e7a0aa3bf8cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432367377 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.432367377
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1549660284
Short name T540
Test name
Test status
Simulation time 86358017 ps
CPU time 0.85 seconds
Started Jul 09 05:42:20 PM PDT 24
Finished Jul 09 05:42:22 PM PDT 24
Peak memory 200252 kb
Host smart-2abadd3c-c2a8-46ef-95d7-a00e4c04fe4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549660284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1549660284
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.799699166
Short name T579
Test name
Test status
Simulation time 228529362 ps
CPU time 1.47 seconds
Started Jul 09 05:42:23 PM PDT 24
Finished Jul 09 05:42:25 PM PDT 24
Peak memory 200572 kb
Host smart-fcd1b0b4-d501-45bd-b570-0def8cae734a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799699166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.799699166
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1243901440
Short name T584
Test name
Test status
Simulation time 111118356 ps
CPU time 1.75 seconds
Started Jul 09 05:42:21 PM PDT 24
Finished Jul 09 05:42:24 PM PDT 24
Peak memory 208620 kb
Host smart-534c811a-1689-4378-9a1c-0a42a098a54d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243901440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1243901440
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3506272192
Short name T594
Test name
Test status
Simulation time 498908383 ps
CPU time 1.97 seconds
Started Jul 09 05:42:20 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 200364 kb
Host smart-a17e7e3a-2a57-49bd-ac26-02f19a1a6693
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506272192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3506272192
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2426209073
Short name T608
Test name
Test status
Simulation time 199780874 ps
CPU time 2.14 seconds
Started Jul 09 05:42:24 PM PDT 24
Finished Jul 09 05:42:26 PM PDT 24
Peak memory 208828 kb
Host smart-15dc77a3-19ef-4beb-85a9-3ee67997109e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426209073 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2426209073
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3478571290
Short name T545
Test name
Test status
Simulation time 76161110 ps
CPU time 0.84 seconds
Started Jul 09 05:42:23 PM PDT 24
Finished Jul 09 05:42:24 PM PDT 24
Peak memory 200240 kb
Host smart-c82b90db-4133-4c46-ab20-46aabe4227db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478571290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3478571290
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2332376553
Short name T105
Test name
Test status
Simulation time 151445830 ps
CPU time 1.08 seconds
Started Jul 09 05:42:27 PM PDT 24
Finished Jul 09 05:42:29 PM PDT 24
Peak memory 200328 kb
Host smart-262e96a0-189a-4438-9837-a18a1aedaf89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332376553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2332376553
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3960967320
Short name T564
Test name
Test status
Simulation time 118822412 ps
CPU time 1.55 seconds
Started Jul 09 05:42:23 PM PDT 24
Finished Jul 09 05:42:25 PM PDT 24
Peak memory 208580 kb
Host smart-0bf9d4bb-951e-4ee2-b70d-c1cec7fff103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960967320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3960967320
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.738941021
Short name T110
Test name
Test status
Simulation time 940292121 ps
CPU time 3.37 seconds
Started Jul 09 05:42:21 PM PDT 24
Finished Jul 09 05:42:25 PM PDT 24
Peak memory 200464 kb
Host smart-d16921f7-6fb8-4b0d-818c-d95f55f08e0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738941021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.738941021
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.219338302
Short name T103
Test name
Test status
Simulation time 63623572 ps
CPU time 0.86 seconds
Started Jul 09 05:42:25 PM PDT 24
Finished Jul 09 05:42:26 PM PDT 24
Peak memory 200244 kb
Host smart-08a33ee7-064a-40aa-91f0-2472d23c48b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219338302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.219338302
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1515191910
Short name T563
Test name
Test status
Simulation time 154832164 ps
CPU time 1.22 seconds
Started Jul 09 05:42:25 PM PDT 24
Finished Jul 09 05:42:26 PM PDT 24
Peak memory 200380 kb
Host smart-eca82983-e678-4f9f-8857-a0f1cff643ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515191910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1515191910
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4111533633
Short name T67
Test name
Test status
Simulation time 429484357 ps
CPU time 3.25 seconds
Started Jul 09 05:42:27 PM PDT 24
Finished Jul 09 05:42:31 PM PDT 24
Peak memory 208668 kb
Host smart-99dcb8f1-88f7-44a0-a9a9-26fda255d5e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111533633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4111533633
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1911710481
Short name T84
Test name
Test status
Simulation time 481211213 ps
CPU time 1.89 seconds
Started Jul 09 05:42:22 PM PDT 24
Finished Jul 09 05:42:24 PM PDT 24
Peak memory 200448 kb
Host smart-4c7cd622-0d95-4f30-af02-2165060db8d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911710481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1911710481
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2252600030
Short name T554
Test name
Test status
Simulation time 194329829 ps
CPU time 1.25 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:37 PM PDT 24
Peak memory 208628 kb
Host smart-598d79ac-260d-4066-827b-fe23f57b432b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252600030 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2252600030
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.240791398
Short name T615
Test name
Test status
Simulation time 68238651 ps
CPU time 0.82 seconds
Started Jul 09 05:42:22 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 200296 kb
Host smart-1eeda017-dc40-4c9c-88a7-91f9cf425dbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240791398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.240791398
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.723513906
Short name T560
Test name
Test status
Simulation time 225203016 ps
CPU time 1.48 seconds
Started Jul 09 05:42:35 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 200488 kb
Host smart-dff88e21-c977-4d2f-b154-4380a3e3c4e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723513906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.723513906
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.636208485
Short name T557
Test name
Test status
Simulation time 190071830 ps
CPU time 2.79 seconds
Started Jul 09 05:42:24 PM PDT 24
Finished Jul 09 05:42:27 PM PDT 24
Peak memory 216820 kb
Host smart-dbb37963-81a2-480f-9556-e4de11a4dc4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636208485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.636208485
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3321062808
Short name T86
Test name
Test status
Simulation time 955413988 ps
CPU time 3.4 seconds
Started Jul 09 05:42:26 PM PDT 24
Finished Jul 09 05:42:29 PM PDT 24
Peak memory 200536 kb
Host smart-970af5fc-00f3-4d11-a07b-200545431386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321062808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3321062808
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2337225471
Short name T87
Test name
Test status
Simulation time 181236857 ps
CPU time 1.85 seconds
Started Jul 09 05:42:27 PM PDT 24
Finished Jul 09 05:42:29 PM PDT 24
Peak memory 208832 kb
Host smart-ddfecd53-b9f9-4291-87b7-6d98bba25c3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337225471 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2337225471
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2050173264
Short name T64
Test name
Test status
Simulation time 67983809 ps
CPU time 0.83 seconds
Started Jul 09 05:42:26 PM PDT 24
Finished Jul 09 05:42:28 PM PDT 24
Peak memory 200284 kb
Host smart-ffa43896-4324-4e56-9be2-d10fe3307b16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050173264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2050173264
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.998862941
Short name T101
Test name
Test status
Simulation time 135816189 ps
CPU time 1.4 seconds
Started Jul 09 05:42:28 PM PDT 24
Finished Jul 09 05:42:30 PM PDT 24
Peak memory 200456 kb
Host smart-91fdc643-bdc9-452a-a694-09388c80ba4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998862941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.998862941
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.855386069
Short name T577
Test name
Test status
Simulation time 434081298 ps
CPU time 3.16 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 216700 kb
Host smart-95b428de-e8ff-4972-8732-a76771001046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855386069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.855386069
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2915183946
Short name T65
Test name
Test status
Simulation time 1098580935 ps
CPU time 3.15 seconds
Started Jul 09 05:42:28 PM PDT 24
Finished Jul 09 05:42:32 PM PDT 24
Peak memory 200456 kb
Host smart-3113671b-e079-4a60-86bd-487fbba21244
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915183946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2915183946
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.370028766
Short name T585
Test name
Test status
Simulation time 127450600 ps
CPU time 1.22 seconds
Started Jul 09 05:42:25 PM PDT 24
Finished Jul 09 05:42:27 PM PDT 24
Peak memory 208564 kb
Host smart-3aef87a9-ea1a-4b6a-ad46-7f744aa64195
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370028766 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.370028766
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1401966912
Short name T97
Test name
Test status
Simulation time 82605867 ps
CPU time 0.92 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:42:33 PM PDT 24
Peak memory 200284 kb
Host smart-42429336-b391-4509-825d-0fa11cf6c769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401966912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1401966912
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2729609656
Short name T595
Test name
Test status
Simulation time 207372543 ps
CPU time 1.44 seconds
Started Jul 09 05:42:28 PM PDT 24
Finished Jul 09 05:42:30 PM PDT 24
Peak memory 200420 kb
Host smart-ff83b151-6c77-411e-8f48-040d74c3c7f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729609656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2729609656
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3657660159
Short name T69
Test name
Test status
Simulation time 156572599 ps
CPU time 1.6 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:42:33 PM PDT 24
Peak memory 208792 kb
Host smart-1f6c982d-7a8a-44c5-864c-0a98b3195e5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657660159 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3657660159
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.496979467
Short name T553
Test name
Test status
Simulation time 59066038 ps
CPU time 0.81 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:42:33 PM PDT 24
Peak memory 200284 kb
Host smart-ecc503b4-2dcf-4fb9-b4fb-267bbb3eb35f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496979467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.496979467
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2468911266
Short name T616
Test name
Test status
Simulation time 95286867 ps
CPU time 1.32 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:42:33 PM PDT 24
Peak memory 200536 kb
Host smart-bc942091-5cf5-440a-a5eb-3ad124421309
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468911266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2468911266
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3927492120
Short name T567
Test name
Test status
Simulation time 304443234 ps
CPU time 2.23 seconds
Started Jul 09 05:45:12 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 208724 kb
Host smart-d1c5d87d-dee7-4b3a-a3c5-c48f63ada9cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927492120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3927492120
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4264528708
Short name T601
Test name
Test status
Simulation time 127993631 ps
CPU time 1.4 seconds
Started Jul 09 05:42:30 PM PDT 24
Finished Jul 09 05:42:32 PM PDT 24
Peak memory 208524 kb
Host smart-69d4ad8a-ad27-4f08-8726-6aa03da0c495
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264528708 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4264528708
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4194942293
Short name T558
Test name
Test status
Simulation time 73702533 ps
CPU time 0.86 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:36 PM PDT 24
Peak memory 200208 kb
Host smart-809c5bcf-d0f8-4b96-990c-179bb1945fc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194942293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.4194942293
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1601133039
Short name T104
Test name
Test status
Simulation time 209453838 ps
CPU time 1.54 seconds
Started Jul 09 05:42:28 PM PDT 24
Finished Jul 09 05:42:30 PM PDT 24
Peak memory 200480 kb
Host smart-7d41627b-44af-450e-a440-6737cc6113ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601133039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1601133039
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.721806717
Short name T619
Test name
Test status
Simulation time 208203870 ps
CPU time 1.76 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:42:34 PM PDT 24
Peak memory 200440 kb
Host smart-a0096dfe-bdc5-42b3-9627-244fa37ddb59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721806717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.721806717
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3114300649
Short name T62
Test name
Test status
Simulation time 360490656 ps
CPU time 2.41 seconds
Started Jul 09 05:42:08 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 200480 kb
Host smart-f21b173c-09bc-421f-b49e-b82bae9cddad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114300649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
114300649
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.275449701
Short name T586
Test name
Test status
Simulation time 802779101 ps
CPU time 4.56 seconds
Started Jul 09 05:42:09 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 216072 kb
Host smart-7d740bf0-3ec9-4324-8531-ea17f11f5494
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275449701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.275449701
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3914563677
Short name T571
Test name
Test status
Simulation time 143201780 ps
CPU time 1 seconds
Started Jul 09 05:42:08 PM PDT 24
Finished Jul 09 05:42:10 PM PDT 24
Peak memory 200328 kb
Host smart-6c916038-b490-4387-a46e-659aca246317
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914563677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
914563677
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1658982759
Short name T89
Test name
Test status
Simulation time 179624931 ps
CPU time 1.62 seconds
Started Jul 09 05:42:12 PM PDT 24
Finished Jul 09 05:42:15 PM PDT 24
Peak memory 208664 kb
Host smart-1d0cd49a-262f-45d4-a6d0-715889328835
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658982759 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1658982759
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1967164000
Short name T552
Test name
Test status
Simulation time 74323640 ps
CPU time 0.92 seconds
Started Jul 09 05:42:10 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 200232 kb
Host smart-d51849bb-e2fd-4e76-b073-83c3dcb63b46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967164000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1967164000
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3528497128
Short name T590
Test name
Test status
Simulation time 80773696 ps
CPU time 1.03 seconds
Started Jul 09 05:42:15 PM PDT 24
Finished Jul 09 05:42:17 PM PDT 24
Peak memory 200340 kb
Host smart-827eba53-61b3-4b5a-b071-a1425a72653c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528497128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3528497128
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.963797961
Short name T568
Test name
Test status
Simulation time 152158029 ps
CPU time 2.23 seconds
Started Jul 09 05:42:09 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 212200 kb
Host smart-a46f044a-5fb7-44b6-b11a-14b5d90c8191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963797961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.963797961
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.930849298
Short name T546
Test name
Test status
Simulation time 946124201 ps
CPU time 3.56 seconds
Started Jul 09 05:42:08 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 200472 kb
Host smart-7610418c-90a8-44a2-9b9d-35f7d139304f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930849298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
930849298
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.311669771
Short name T543
Test name
Test status
Simulation time 217273166 ps
CPU time 1.61 seconds
Started Jul 09 05:42:16 PM PDT 24
Finished Jul 09 05:42:18 PM PDT 24
Peak memory 200296 kb
Host smart-c1b84f47-81da-4b11-96d4-099b4f2f244e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311669771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.311669771
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1272110126
Short name T542
Test name
Test status
Simulation time 2309136202 ps
CPU time 9.68 seconds
Started Jul 09 05:42:12 PM PDT 24
Finished Jul 09 05:42:22 PM PDT 24
Peak memory 200388 kb
Host smart-803af64b-e00e-4e1e-82d1-fa132ab352a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272110126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
272110126
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1487404364
Short name T578
Test name
Test status
Simulation time 138579513 ps
CPU time 0.94 seconds
Started Jul 09 05:42:11 PM PDT 24
Finished Jul 09 05:42:13 PM PDT 24
Peak memory 200208 kb
Host smart-d050825e-914a-4920-abf4-e7a95e18f7b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487404364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
487404364
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1937782294
Short name T617
Test name
Test status
Simulation time 205733228 ps
CPU time 1.31 seconds
Started Jul 09 05:42:12 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 208628 kb
Host smart-49f2f470-ff6b-4b5e-b7ff-b31bc256f06d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937782294 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1937782294
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3206378444
Short name T549
Test name
Test status
Simulation time 66114768 ps
CPU time 0.75 seconds
Started Jul 09 05:42:15 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 200316 kb
Host smart-1720a327-1737-43ed-bec5-596b7ecb2be7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206378444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3206378444
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1569321683
Short name T582
Test name
Test status
Simulation time 77065280 ps
CPU time 1.04 seconds
Started Jul 09 05:42:11 PM PDT 24
Finished Jul 09 05:42:13 PM PDT 24
Peak memory 200304 kb
Host smart-6ec4765d-8fad-4f9d-a3f4-291192529709
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569321683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1569321683
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3002832904
Short name T565
Test name
Test status
Simulation time 361453448 ps
CPU time 2.54 seconds
Started Jul 09 05:42:13 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 208652 kb
Host smart-edb2a17d-deda-4e02-b597-f8f45248a010
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002832904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3002832904
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4077439942
Short name T123
Test name
Test status
Simulation time 922996259 ps
CPU time 3.21 seconds
Started Jul 09 05:42:15 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 208656 kb
Host smart-57bf7d00-e69e-4e35-a26d-1f0d3d461134
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077439942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.4077439942
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1179549259
Short name T576
Test name
Test status
Simulation time 105166284 ps
CPU time 1.46 seconds
Started Jul 09 05:42:16 PM PDT 24
Finished Jul 09 05:42:18 PM PDT 24
Peak memory 200424 kb
Host smart-0c3e8398-d602-44af-b7c0-12b661e30508
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179549259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
179549259
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.360792889
Short name T548
Test name
Test status
Simulation time 2282798277 ps
CPU time 9.69 seconds
Started Jul 09 05:42:12 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 200452 kb
Host smart-54807710-30e7-4f19-a391-48b6e43cd122
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360792889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.360792889
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4110891645
Short name T544
Test name
Test status
Simulation time 92399512 ps
CPU time 0.87 seconds
Started Jul 09 05:42:13 PM PDT 24
Finished Jul 09 05:42:15 PM PDT 24
Peak memory 200252 kb
Host smart-41e6f323-1d80-422e-975e-ee127b6801ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110891645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.4
110891645
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3371938306
Short name T106
Test name
Test status
Simulation time 199240513 ps
CPU time 1.36 seconds
Started Jul 09 05:42:17 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 208748 kb
Host smart-caa7697a-9cf4-4bef-b240-90d5a9af4bfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371938306 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3371938306
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.626700163
Short name T589
Test name
Test status
Simulation time 81899502 ps
CPU time 0.86 seconds
Started Jul 09 05:42:13 PM PDT 24
Finished Jul 09 05:42:15 PM PDT 24
Peak memory 200300 kb
Host smart-112f4e34-501f-4dd6-a2ea-10ab9d3f4d3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626700163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.626700163
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.395753541
Short name T587
Test name
Test status
Simulation time 75813072 ps
CPU time 0.99 seconds
Started Jul 09 05:42:15 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 200380 kb
Host smart-3fe63716-fa7a-4c97-b97b-4f48523298be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395753541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.395753541
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.684607425
Short name T114
Test name
Test status
Simulation time 99040972 ps
CPU time 1.34 seconds
Started Jul 09 05:42:14 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 208632 kb
Host smart-0db94c95-c82b-4afa-b723-da942fc8ae6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684607425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.684607425
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3151433370
Short name T122
Test name
Test status
Simulation time 935589678 ps
CPU time 3.43 seconds
Started Jul 09 05:42:13 PM PDT 24
Finished Jul 09 05:42:18 PM PDT 24
Peak memory 200540 kb
Host smart-721b408f-815c-4315-aec5-5c21eb097512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151433370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3151433370
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2763960589
Short name T598
Test name
Test status
Simulation time 103942894 ps
CPU time 0.95 seconds
Started Jul 09 05:42:17 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 200336 kb
Host smart-1027fbd3-e6db-4fb2-9f5a-3896e7c7e1ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763960589 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2763960589
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3575557836
Short name T583
Test name
Test status
Simulation time 65038193 ps
CPU time 0.82 seconds
Started Jul 09 05:42:16 PM PDT 24
Finished Jul 09 05:42:18 PM PDT 24
Peak memory 200296 kb
Host smart-b7fab798-857c-4e0d-99fe-de8c57c03e51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575557836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3575557836
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2560052035
Short name T610
Test name
Test status
Simulation time 86069591 ps
CPU time 1.04 seconds
Started Jul 09 05:42:16 PM PDT 24
Finished Jul 09 05:42:18 PM PDT 24
Peak memory 200296 kb
Host smart-e09073cd-6dd4-4444-9edf-860ab8cba736
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560052035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2560052035
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.584469514
Short name T113
Test name
Test status
Simulation time 353001523 ps
CPU time 2.81 seconds
Started Jul 09 05:42:17 PM PDT 24
Finished Jul 09 05:42:20 PM PDT 24
Peak memory 208584 kb
Host smart-173914e0-86f8-48e1-bf5a-040457043131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584469514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.584469514
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.827212577
Short name T108
Test name
Test status
Simulation time 912330588 ps
CPU time 3.27 seconds
Started Jul 09 05:42:15 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 200500 kb
Host smart-e1407a3c-dbef-4eb0-a9a2-5765f5b6b7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827212577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
827212577
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.978617195
Short name T572
Test name
Test status
Simulation time 196450168 ps
CPU time 1.95 seconds
Started Jul 09 05:42:19 PM PDT 24
Finished Jul 09 05:42:22 PM PDT 24
Peak memory 208848 kb
Host smart-0ce82896-8fcf-4b06-a6a9-1ce0aa7fe041
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978617195 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.978617195
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2239913546
Short name T604
Test name
Test status
Simulation time 64035528 ps
CPU time 0.86 seconds
Started Jul 09 05:42:19 PM PDT 24
Finished Jul 09 05:42:21 PM PDT 24
Peak memory 200324 kb
Host smart-1d4fe4fa-0382-4730-bda6-ca20af0b295b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239913546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2239913546
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.983238989
Short name T592
Test name
Test status
Simulation time 133204585 ps
CPU time 1.08 seconds
Started Jul 09 05:42:18 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 200312 kb
Host smart-9546ce75-280b-4f9c-86e5-ca9aad7c461e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983238989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.983238989
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3275715146
Short name T580
Test name
Test status
Simulation time 168160557 ps
CPU time 2.49 seconds
Started Jul 09 05:42:14 PM PDT 24
Finished Jul 09 05:42:17 PM PDT 24
Peak memory 208640 kb
Host smart-d1450a31-b9c5-416f-bf7f-ce6853b155c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275715146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3275715146
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1082099748
Short name T605
Test name
Test status
Simulation time 470832267 ps
CPU time 1.86 seconds
Started Jul 09 05:42:17 PM PDT 24
Finished Jul 09 05:42:20 PM PDT 24
Peak memory 200500 kb
Host smart-8f483137-603e-4497-b395-9b9723d34683
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082099748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1082099748
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4030647895
Short name T574
Test name
Test status
Simulation time 178151575 ps
CPU time 1.23 seconds
Started Jul 09 05:42:17 PM PDT 24
Finished Jul 09 05:42:18 PM PDT 24
Peak memory 208520 kb
Host smart-584888db-45ab-4155-9db7-5f6343321b5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030647895 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.4030647895
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2109723336
Short name T573
Test name
Test status
Simulation time 68780495 ps
CPU time 0.79 seconds
Started Jul 09 05:42:18 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 200300 kb
Host smart-dc73da4b-1684-42be-bab1-e4d33692cf8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109723336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2109723336
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2827741325
Short name T607
Test name
Test status
Simulation time 88665710 ps
CPU time 1.09 seconds
Started Jul 09 05:42:16 PM PDT 24
Finished Jul 09 05:42:18 PM PDT 24
Peak memory 200492 kb
Host smart-ed516066-2e67-4cb8-bfcb-b361d86155d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827741325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2827741325
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1519057708
Short name T600
Test name
Test status
Simulation time 242954422 ps
CPU time 1.63 seconds
Started Jul 09 05:42:17 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 200344 kb
Host smart-4f02db15-76dd-4b9f-8105-9cd895bb6b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519057708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1519057708
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.336560919
Short name T115
Test name
Test status
Simulation time 811371688 ps
CPU time 2.75 seconds
Started Jul 09 05:42:19 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 200504 kb
Host smart-cd56d5aa-aefb-47c5-bb04-13ac59edd61f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336560919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
336560919
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1358685471
Short name T547
Test name
Test status
Simulation time 123734129 ps
CPU time 1.05 seconds
Started Jul 09 05:42:21 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 208556 kb
Host smart-dc022839-2d36-45b8-8fdd-f15301a6facc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358685471 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1358685471
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1199110178
Short name T98
Test name
Test status
Simulation time 58274260 ps
CPU time 0.74 seconds
Started Jul 09 05:42:19 PM PDT 24
Finished Jul 09 05:42:21 PM PDT 24
Peak memory 200284 kb
Host smart-d4a360b8-1441-47e9-a259-72790cd8a436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199110178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1199110178
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1744763976
Short name T597
Test name
Test status
Simulation time 115565915 ps
CPU time 1 seconds
Started Jul 09 05:42:18 PM PDT 24
Finished Jul 09 05:42:20 PM PDT 24
Peak memory 200360 kb
Host smart-ac5c00aa-ca37-4f65-910a-702a44abb93d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744763976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1744763976
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3175246242
Short name T618
Test name
Test status
Simulation time 215865110 ps
CPU time 1.51 seconds
Started Jul 09 05:42:17 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 200332 kb
Host smart-19e70b66-0950-467e-97a5-a163a01acad6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175246242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3175246242
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4215952367
Short name T112
Test name
Test status
Simulation time 888587934 ps
CPU time 3.25 seconds
Started Jul 09 05:42:18 PM PDT 24
Finished Jul 09 05:42:22 PM PDT 24
Peak memory 200440 kb
Host smart-d83761d8-23af-41d0-8f68-80e62e9599c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215952367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.4215952367
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2028075469
Short name T593
Test name
Test status
Simulation time 174665056 ps
CPU time 1.2 seconds
Started Jul 09 05:42:19 PM PDT 24
Finished Jul 09 05:42:21 PM PDT 24
Peak memory 208576 kb
Host smart-c04bd8e4-0a60-4cf3-999c-0534c463d28d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028075469 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2028075469
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1533505622
Short name T550
Test name
Test status
Simulation time 67371286 ps
CPU time 0.78 seconds
Started Jul 09 05:42:26 PM PDT 24
Finished Jul 09 05:42:28 PM PDT 24
Peak memory 200264 kb
Host smart-16202423-9359-460c-b093-b14687252797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533505622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1533505622
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4282877662
Short name T581
Test name
Test status
Simulation time 282414062 ps
CPU time 1.63 seconds
Started Jul 09 05:42:20 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 200456 kb
Host smart-414e1c8c-c5f3-413e-b049-a38b410f41b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282877662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.4282877662
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.446312416
Short name T612
Test name
Test status
Simulation time 387402203 ps
CPU time 2.64 seconds
Started Jul 09 05:42:26 PM PDT 24
Finished Jul 09 05:42:29 PM PDT 24
Peak memory 208580 kb
Host smart-b61e719f-e092-463e-add4-9c4afb553dc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446312416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.446312416
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2004200029
Short name T596
Test name
Test status
Simulation time 935836328 ps
CPU time 3 seconds
Started Jul 09 05:42:18 PM PDT 24
Finished Jul 09 05:42:22 PM PDT 24
Peak memory 200548 kb
Host smart-1a1fe78d-c3ec-4e89-afca-c2c6759fde40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004200029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2004200029
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1459209847
Short name T437
Test name
Test status
Simulation time 61540921 ps
CPU time 0.76 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:35 PM PDT 24
Peak memory 199872 kb
Host smart-f8637c38-649b-4df7-905f-55667a8ad111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459209847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1459209847
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3908815669
Short name T528
Test name
Test status
Simulation time 135115567 ps
CPU time 0.84 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:37 PM PDT 24
Peak memory 199992 kb
Host smart-55725236-8bba-4c16-9938-4b37db534581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908815669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3908815669
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2728124772
Short name T486
Test name
Test status
Simulation time 787281298 ps
CPU time 3.72 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:39 PM PDT 24
Peak memory 200432 kb
Host smart-f909c42a-35a1-4fd1-8949-b2db37d8f827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728124772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2728124772
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3780364417
Short name T68
Test name
Test status
Simulation time 8429891621 ps
CPU time 12.43 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:47 PM PDT 24
Peak memory 217212 kb
Host smart-fe2d18fa-cc9e-4e72-ab40-0d98baf0891c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780364417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3780364417
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2002734234
Short name T281
Test name
Test status
Simulation time 121438697 ps
CPU time 1.27 seconds
Started Jul 09 05:42:29 PM PDT 24
Finished Jul 09 05:42:31 PM PDT 24
Peak memory 200372 kb
Host smart-0c05261a-2613-4352-acb9-697c420255f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002734234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2002734234
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.586140029
Short name T414
Test name
Test status
Simulation time 271907991 ps
CPU time 1.49 seconds
Started Jul 09 05:42:29 PM PDT 24
Finished Jul 09 05:42:31 PM PDT 24
Peak memory 199912 kb
Host smart-602bb816-5cbc-4518-a4b9-aa03277a8e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586140029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.586140029
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2166092314
Short name T432
Test name
Test status
Simulation time 341792728 ps
CPU time 2.37 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:42:34 PM PDT 24
Peak memory 208380 kb
Host smart-453a9abb-75d3-4193-b520-ef927947fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166092314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2166092314
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.212513737
Short name T490
Test name
Test status
Simulation time 152492717 ps
CPU time 1.25 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:36 PM PDT 24
Peak memory 200268 kb
Host smart-315317a6-329f-4cb5-827a-731356128988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212513737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.212513737
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2329354792
Short name T370
Test name
Test status
Simulation time 54826152 ps
CPU time 0.74 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:35 PM PDT 24
Peak memory 199880 kb
Host smart-22162390-4fb0-4fa8-ba77-9a8920ed92b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329354792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2329354792
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.4020241285
Short name T2
Test name
Test status
Simulation time 1229708845 ps
CPU time 5.23 seconds
Started Jul 09 05:42:30 PM PDT 24
Finished Jul 09 05:42:36 PM PDT 24
Peak memory 221716 kb
Host smart-ce72ec7a-caab-4fe3-80e2-b6041e7f9c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020241285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.4020241285
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3497203654
Short name T199
Test name
Test status
Simulation time 245317842 ps
CPU time 1.1 seconds
Started Jul 09 05:42:32 PM PDT 24
Finished Jul 09 05:42:34 PM PDT 24
Peak memory 217496 kb
Host smart-884b10ac-4eb6-498b-a68e-6b9f6867f5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497203654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3497203654
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3784004924
Short name T165
Test name
Test status
Simulation time 82700934 ps
CPU time 0.76 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:35 PM PDT 24
Peak memory 199992 kb
Host smart-57439cbd-f253-4181-83ab-143758c6fbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784004924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3784004924
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1112262521
Short name T450
Test name
Test status
Simulation time 1532751056 ps
CPU time 6.04 seconds
Started Jul 09 05:42:32 PM PDT 24
Finished Jul 09 05:42:39 PM PDT 24
Peak memory 200432 kb
Host smart-8c5d3a28-d9af-4142-a850-a75b2ac9f9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112262521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1112262521
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.894431210
Short name T182
Test name
Test status
Simulation time 114204306 ps
CPU time 0.98 seconds
Started Jul 09 05:42:30 PM PDT 24
Finished Jul 09 05:42:32 PM PDT 24
Peak memory 200088 kb
Host smart-9ce62c27-dbdf-43a6-a062-cac320a88ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894431210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.894431210
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1926976202
Short name T397
Test name
Test status
Simulation time 129956635 ps
CPU time 1.27 seconds
Started Jul 09 05:42:37 PM PDT 24
Finished Jul 09 05:42:39 PM PDT 24
Peak memory 200252 kb
Host smart-7dd92676-7a9f-4c8e-b43f-3f0b8aa00936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926976202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1926976202
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2663854170
Short name T410
Test name
Test status
Simulation time 14676695081 ps
CPU time 57.4 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:43:29 PM PDT 24
Peak memory 208708 kb
Host smart-c7b1d014-7137-4cf0-9805-2b168e2d9439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663854170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2663854170
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1656611852
Short name T476
Test name
Test status
Simulation time 267072588 ps
CPU time 1.87 seconds
Started Jul 09 05:42:32 PM PDT 24
Finished Jul 09 05:42:34 PM PDT 24
Peak memory 200168 kb
Host smart-adb83e54-74b2-47a6-beb9-c265445b6f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656611852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1656611852
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1753207657
Short name T488
Test name
Test status
Simulation time 87241793 ps
CPU time 0.93 seconds
Started Jul 09 05:42:35 PM PDT 24
Finished Jul 09 05:42:37 PM PDT 24
Peak memory 200144 kb
Host smart-7e4e61f8-5031-45bb-8d7a-e13f2080fb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753207657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1753207657
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2092170356
Short name T497
Test name
Test status
Simulation time 71041136 ps
CPU time 0.77 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 199872 kb
Host smart-3d0e2770-1823-4b8b-bb6f-978acf43f0dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092170356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2092170356
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.805724791
Short name T125
Test name
Test status
Simulation time 244489733 ps
CPU time 1.06 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:47 PM PDT 24
Peak memory 217520 kb
Host smart-bd24a2e1-be09-4a8f-ba44-450ff3bd0852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805724791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.805724791
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2338983055
Short name T441
Test name
Test status
Simulation time 219540466 ps
CPU time 0.91 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:48 PM PDT 24
Peak memory 199940 kb
Host smart-269c3fc8-df28-42a8-9e90-0bd216b3ff9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338983055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2338983055
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2696380751
Short name T320
Test name
Test status
Simulation time 1168670332 ps
CPU time 5.29 seconds
Started Jul 09 05:42:44 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 200480 kb
Host smart-cde1247a-c908-4a9f-9aea-6ee93a3fcd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696380751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2696380751
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2647443885
Short name T72
Test name
Test status
Simulation time 103291292 ps
CPU time 1.09 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:48 PM PDT 24
Peak memory 200060 kb
Host smart-683d159d-c5a9-45e7-9c7e-189a8b6c5b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647443885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2647443885
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1480903642
Short name T210
Test name
Test status
Simulation time 248250432 ps
CPU time 1.56 seconds
Started Jul 09 05:42:42 PM PDT 24
Finished Jul 09 05:42:44 PM PDT 24
Peak memory 200380 kb
Host smart-a639313e-826f-434b-adf9-7666f662bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480903642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1480903642
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1262195650
Short name T44
Test name
Test status
Simulation time 5985920064 ps
CPU time 25.98 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:43:13 PM PDT 24
Peak memory 208680 kb
Host smart-613f2fba-c160-4309-ac22-61eeb6ff0687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262195650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1262195650
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.671759852
Short name T396
Test name
Test status
Simulation time 126033582 ps
CPU time 1.48 seconds
Started Jul 09 05:42:48 PM PDT 24
Finished Jul 09 05:42:52 PM PDT 24
Peak memory 200180 kb
Host smart-6339c2b8-81b4-4725-9022-2cf59ccf20ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671759852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.671759852
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1520125934
Short name T258
Test name
Test status
Simulation time 137991533 ps
CPU time 0.99 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:47 PM PDT 24
Peak memory 200112 kb
Host smart-0be94da7-c97d-409e-9bf2-51c4025a5f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520125934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1520125934
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2147151272
Short name T32
Test name
Test status
Simulation time 1870585871 ps
CPU time 7.25 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 221776 kb
Host smart-e69f0b9e-011c-45bd-bb63-9a7d6e37b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147151272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2147151272
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1172304189
Short name T314
Test name
Test status
Simulation time 245039277 ps
CPU time 1.08 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:51 PM PDT 24
Peak memory 217488 kb
Host smart-f01d3a96-5609-46e5-9a54-f5699dd4a7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172304189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1172304189
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.5852692
Short name T325
Test name
Test status
Simulation time 187869896 ps
CPU time 0.9 seconds
Started Jul 09 05:42:49 PM PDT 24
Finished Jul 09 05:42:53 PM PDT 24
Peak memory 199964 kb
Host smart-0ee25abc-a194-4c97-a064-d75d85edbb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5852692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.5852692
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2074551997
Short name T350
Test name
Test status
Simulation time 1134871335 ps
CPU time 5.37 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 200320 kb
Host smart-4f80a24f-8d27-43ba-94a4-6ea985644b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074551997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2074551997
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3529965378
Short name T129
Test name
Test status
Simulation time 98166238 ps
CPU time 0.98 seconds
Started Jul 09 05:42:48 PM PDT 24
Finished Jul 09 05:42:51 PM PDT 24
Peak memory 200128 kb
Host smart-62e63e93-0d4c-4378-92d0-be8f012b6ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529965378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3529965378
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2930381812
Short name T194
Test name
Test status
Simulation time 127122060 ps
CPU time 1.21 seconds
Started Jul 09 05:42:43 PM PDT 24
Finished Jul 09 05:42:45 PM PDT 24
Peak memory 200316 kb
Host smart-14e94295-9fa0-493e-a77a-1e82a4a8afc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930381812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2930381812
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2489540179
Short name T372
Test name
Test status
Simulation time 12448621647 ps
CPU time 42.53 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:43:32 PM PDT 24
Peak memory 208668 kb
Host smart-99646ba6-2550-43ad-ba5d-f79ed0fb8a0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489540179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2489540179
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2485331379
Short name T144
Test name
Test status
Simulation time 140367873 ps
CPU time 1.66 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:48 PM PDT 24
Peak memory 200012 kb
Host smart-4f747063-1710-4a5d-b003-951863f31b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485331379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2485331379
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2477995826
Short name T347
Test name
Test status
Simulation time 94368763 ps
CPU time 0.83 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:51 PM PDT 24
Peak memory 199932 kb
Host smart-51b06643-0991-41b0-b723-ddb412dfd6b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477995826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2477995826
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1898138049
Short name T445
Test name
Test status
Simulation time 1223120456 ps
CPU time 5.46 seconds
Started Jul 09 05:42:46 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 217780 kb
Host smart-81507b76-f4ee-49f6-b36b-dce5c2ed2778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898138049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1898138049
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1046837088
Short name T342
Test name
Test status
Simulation time 244621304 ps
CPU time 1.13 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 217544 kb
Host smart-d46f8529-97e7-4cbb-9acc-f894467ec31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046837088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1046837088
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1291224156
Short name T243
Test name
Test status
Simulation time 111231095 ps
CPU time 0.77 seconds
Started Jul 09 05:42:49 PM PDT 24
Finished Jul 09 05:42:52 PM PDT 24
Peak memory 199996 kb
Host smart-effdc4f0-315a-43cf-be05-7dfd5da66cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291224156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1291224156
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2407065328
Short name T135
Test name
Test status
Simulation time 898621720 ps
CPU time 4.46 seconds
Started Jul 09 05:42:46 PM PDT 24
Finished Jul 09 05:42:52 PM PDT 24
Peak memory 200440 kb
Host smart-630da907-57f3-4077-809a-d90d943a3f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407065328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2407065328
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3274111304
Short name T228
Test name
Test status
Simulation time 113606720 ps
CPU time 1.03 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 200164 kb
Host smart-8ee45fde-2eb9-43b6-b732-ae4e05f165d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274111304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3274111304
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1506363477
Short name T272
Test name
Test status
Simulation time 188734193 ps
CPU time 1.47 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:51 PM PDT 24
Peak memory 200316 kb
Host smart-0e01870a-1d08-467e-96cb-5e04676e5cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506363477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1506363477
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3930807351
Short name T249
Test name
Test status
Simulation time 6864419058 ps
CPU time 28.64 seconds
Started Jul 09 05:42:49 PM PDT 24
Finished Jul 09 05:43:20 PM PDT 24
Peak memory 208688 kb
Host smart-89c03be6-52ab-420a-bac7-bed608adf35c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930807351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3930807351
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3566842178
Short name T212
Test name
Test status
Simulation time 520785680 ps
CPU time 2.73 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:52 PM PDT 24
Peak memory 200156 kb
Host smart-d26fa92b-040b-414f-a720-0be6aea0b949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566842178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3566842178
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2736726653
Short name T283
Test name
Test status
Simulation time 79374082 ps
CPU time 0.87 seconds
Started Jul 09 05:42:51 PM PDT 24
Finished Jul 09 05:42:55 PM PDT 24
Peak memory 200152 kb
Host smart-08214faf-6267-4566-97f7-11e71bf82dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736726653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2736726653
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3771037432
Short name T382
Test name
Test status
Simulation time 81449065 ps
CPU time 0.82 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 199936 kb
Host smart-80c8f5eb-1b65-4987-a061-f3f1403cc965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771037432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3771037432
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2465768047
Short name T327
Test name
Test status
Simulation time 1215668804 ps
CPU time 5.85 seconds
Started Jul 09 05:42:49 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 217788 kb
Host smart-748c5cf4-d3f0-4950-afc1-33bac4368c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465768047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2465768047
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1226200805
Short name T261
Test name
Test status
Simulation time 244117319 ps
CPU time 1.11 seconds
Started Jul 09 05:42:49 PM PDT 24
Finished Jul 09 05:42:53 PM PDT 24
Peak memory 217556 kb
Host smart-e7d2443d-c3b1-4ab4-917b-d94f3cf1f94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226200805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1226200805
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.820594959
Short name T253
Test name
Test status
Simulation time 103231318 ps
CPU time 0.77 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 199868 kb
Host smart-fbd46238-727c-4b94-8566-4c717bbffbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820594959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.820594959
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2493200856
Short name T465
Test name
Test status
Simulation time 851905932 ps
CPU time 4.49 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 200420 kb
Host smart-d43ed4d0-b3ac-42d1-a170-ad1171ded684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493200856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2493200856
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1625540241
Short name T402
Test name
Test status
Simulation time 148442963 ps
CPU time 1.06 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 200132 kb
Host smart-7ef395ad-40a8-4a0c-89c7-c83ba2340562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625540241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1625540241
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3494904932
Short name T348
Test name
Test status
Simulation time 122241100 ps
CPU time 1.19 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 200352 kb
Host smart-90aa93e9-c5c3-4bda-845a-2295b3682017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494904932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3494904932
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3494748477
Short name T452
Test name
Test status
Simulation time 9191933540 ps
CPU time 34.35 seconds
Started Jul 09 05:42:48 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 216248 kb
Host smart-d982dbc3-e9cf-4d0f-90d5-796cc03fed55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494748477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3494748477
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2120067417
Short name T200
Test name
Test status
Simulation time 134739780 ps
CPU time 1.6 seconds
Started Jul 09 05:42:46 PM PDT 24
Finished Jul 09 05:42:49 PM PDT 24
Peak memory 208372 kb
Host smart-84f6fcb9-64f8-415a-8cb0-03f9c2b29728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120067417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2120067417
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1390648563
Short name T78
Test name
Test status
Simulation time 113702915 ps
CPU time 0.93 seconds
Started Jul 09 05:42:48 PM PDT 24
Finished Jul 09 05:42:51 PM PDT 24
Peak memory 200160 kb
Host smart-62a5ca8f-d197-4bf8-8a84-6e1d3466f450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390648563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1390648563
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.390897973
Short name T149
Test name
Test status
Simulation time 96200143 ps
CPU time 0.81 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 199980 kb
Host smart-6b0f8917-cacc-4a69-bc02-792b3f60c7b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390897973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.390897973
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2433409139
Short name T255
Test name
Test status
Simulation time 2349673133 ps
CPU time 8.82 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:58 PM PDT 24
Peak memory 217828 kb
Host smart-145653de-009d-4cd2-a28b-e6b1d1389a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433409139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2433409139
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1296578127
Short name T316
Test name
Test status
Simulation time 243912791 ps
CPU time 1.15 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 217552 kb
Host smart-71b169ce-6c37-4387-821f-a87a30a5ce04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296578127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1296578127
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1034629893
Short name T216
Test name
Test status
Simulation time 92610566 ps
CPU time 0.76 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 199952 kb
Host smart-ed807000-6df1-49f3-9f9c-6c9909b20cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034629893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1034629893
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3987641276
Short name T471
Test name
Test status
Simulation time 1453957849 ps
CPU time 5.81 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:53 PM PDT 24
Peak memory 200404 kb
Host smart-11bb64d1-1f2c-40da-9768-013646fba7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987641276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3987641276
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3072925420
Short name T217
Test name
Test status
Simulation time 174241222 ps
CPU time 1.19 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 200164 kb
Host smart-0e538796-6c81-4be4-b48c-7720e0cca1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072925420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3072925420
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2900448498
Short name T197
Test name
Test status
Simulation time 185494054 ps
CPU time 1.31 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:51 PM PDT 24
Peak memory 200348 kb
Host smart-ad3056a7-521a-4608-b019-d7d51385d3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900448498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2900448498
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3807465700
Short name T218
Test name
Test status
Simulation time 566246169 ps
CPU time 3.01 seconds
Started Jul 09 05:42:48 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 200372 kb
Host smart-5091aa41-4199-470e-b739-348b095bbf6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807465700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3807465700
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.242716840
Short name T289
Test name
Test status
Simulation time 294365007 ps
CPU time 1.94 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 208336 kb
Host smart-f317baa5-014e-45e7-a2dc-caf224014675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242716840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.242716840
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2545639715
Short name T334
Test name
Test status
Simulation time 138030359 ps
CPU time 1.09 seconds
Started Jul 09 05:42:47 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 200180 kb
Host smart-3444023e-26d9-4876-9d30-be3c79a22b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545639715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2545639715
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1405576865
Short name T381
Test name
Test status
Simulation time 62521947 ps
CPU time 0.74 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 199960 kb
Host smart-aec540a0-aafc-49d8-abf4-cf136b0a4451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405576865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1405576865
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2376763290
Short name T58
Test name
Test status
Simulation time 2167963947 ps
CPU time 7.55 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 217840 kb
Host smart-c5067fa2-7905-47d1-8ce4-87ca044386b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376763290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2376763290
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.46159104
Short name T366
Test name
Test status
Simulation time 245541154 ps
CPU time 1 seconds
Started Jul 09 05:42:49 PM PDT 24
Finished Jul 09 05:42:53 PM PDT 24
Peak memory 217484 kb
Host smart-05cea004-d6c0-40d1-87cc-78f372d4acfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46159104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.46159104
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2822117425
Short name T235
Test name
Test status
Simulation time 1577926114 ps
CPU time 6.14 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 200380 kb
Host smart-063cb570-9172-4046-9946-f1d38f927cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822117425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2822117425
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3568743272
Short name T75
Test name
Test status
Simulation time 175446513 ps
CPU time 1.28 seconds
Started Jul 09 05:42:50 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 200180 kb
Host smart-28b13990-8a76-4326-8c51-06a788e0a015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568743272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3568743272
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3217593776
Short name T401
Test name
Test status
Simulation time 114996804 ps
CPU time 1.19 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 200380 kb
Host smart-2d43ccdf-108a-4cef-9455-b16ba9ef6966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217593776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3217593776
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2844001485
Short name T454
Test name
Test status
Simulation time 1797798679 ps
CPU time 6.7 seconds
Started Jul 09 05:42:50 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 200440 kb
Host smart-ad2bf328-201b-40b1-bd2f-6048231fb17b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844001485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2844001485
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2423834754
Short name T79
Test name
Test status
Simulation time 331162703 ps
CPU time 2.14 seconds
Started Jul 09 05:42:51 PM PDT 24
Finished Jul 09 05:42:56 PM PDT 24
Peak memory 208336 kb
Host smart-485287ba-61cf-40fa-93fd-5ba30b6919fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423834754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2423834754
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.453401501
Short name T271
Test name
Test status
Simulation time 167206441 ps
CPU time 1.29 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 200352 kb
Host smart-58402613-53f4-4f99-9897-9c4d4f2f6793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453401501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.453401501
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2758636495
Short name T59
Test name
Test status
Simulation time 64910360 ps
CPU time 0.71 seconds
Started Jul 09 05:42:51 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 199968 kb
Host smart-68b64983-377e-46b8-a501-e9f7dee18d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758636495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2758636495
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2615676520
Short name T459
Test name
Test status
Simulation time 243735622 ps
CPU time 1.15 seconds
Started Jul 09 05:42:50 PM PDT 24
Finished Jul 09 05:42:53 PM PDT 24
Peak memory 217520 kb
Host smart-ee894856-27cc-421d-ba60-4dd99302192c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615676520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2615676520
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3801106821
Short name T338
Test name
Test status
Simulation time 155606333 ps
CPU time 0.85 seconds
Started Jul 09 05:42:51 PM PDT 24
Finished Jul 09 05:42:55 PM PDT 24
Peak memory 199920 kb
Host smart-4c7af9e2-520f-414a-b2e8-059fedab470b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801106821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3801106821
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2593038912
Short name T207
Test name
Test status
Simulation time 1280587255 ps
CPU time 5.01 seconds
Started Jul 09 05:42:51 PM PDT 24
Finished Jul 09 05:42:59 PM PDT 24
Peak memory 200440 kb
Host smart-a4e5e2b7-38e6-49a0-a622-4ad8ddc2302e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593038912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2593038912
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2408188292
Short name T274
Test name
Test status
Simulation time 180744754 ps
CPU time 1.23 seconds
Started Jul 09 05:42:50 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 200108 kb
Host smart-876d288e-931d-4dcf-b55f-ef312ba8aaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408188292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2408188292
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2393869364
Short name T451
Test name
Test status
Simulation time 235245600 ps
CPU time 1.58 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 200352 kb
Host smart-a3ac7aee-dd86-4399-a9c5-95e11d1a539c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393869364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2393869364
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3538276101
Short name T278
Test name
Test status
Simulation time 1765666032 ps
CPU time 6.2 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 200444 kb
Host smart-1d5bdc5e-3af5-4af8-93fb-4c8b8db9755c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538276101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3538276101
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2855256236
Short name T523
Test name
Test status
Simulation time 538158973 ps
CPU time 2.75 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:42:59 PM PDT 24
Peak memory 200184 kb
Host smart-a3f745ba-f2c8-488e-98fc-9f9ce9d1c1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855256236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2855256236
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.4255622673
Short name T300
Test name
Test status
Simulation time 89865267 ps
CPU time 0.91 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:56 PM PDT 24
Peak memory 200152 kb
Host smart-c3b084d8-5d6e-4c3c-8b06-9f1c94ce57ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255622673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.4255622673
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1818356496
Short name T141
Test name
Test status
Simulation time 70983295 ps
CPU time 0.77 seconds
Started Jul 09 05:42:49 PM PDT 24
Finished Jul 09 05:42:52 PM PDT 24
Peak memory 199932 kb
Host smart-07ecdfbf-84a0-4e35-9f2f-0cf9a2fc1de4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818356496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1818356496
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2459769405
Short name T225
Test name
Test status
Simulation time 1229412492 ps
CPU time 5.56 seconds
Started Jul 09 05:42:48 PM PDT 24
Finished Jul 09 05:42:56 PM PDT 24
Peak memory 217664 kb
Host smart-f45754ff-6c33-4e12-b685-ba58d3b8b914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459769405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2459769405
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1555404303
Short name T162
Test name
Test status
Simulation time 244164566 ps
CPU time 1.09 seconds
Started Jul 09 05:42:48 PM PDT 24
Finished Jul 09 05:42:52 PM PDT 24
Peak memory 217508 kb
Host smart-4d6c92a8-4062-42bc-b2a8-8963778fc82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555404303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1555404303
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.248716373
Short name T426
Test name
Test status
Simulation time 149365373 ps
CPU time 0.82 seconds
Started Jul 09 05:42:50 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 199972 kb
Host smart-6f5702f8-9b9a-476d-bfde-562b9f3319a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248716373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.248716373
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1725669884
Short name T408
Test name
Test status
Simulation time 1500547057 ps
CPU time 6.93 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 200416 kb
Host smart-38d83587-d923-40fe-b1f4-80604098181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725669884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1725669884
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1414717448
Short name T412
Test name
Test status
Simulation time 144984837 ps
CPU time 1.15 seconds
Started Jul 09 05:42:50 PM PDT 24
Finished Jul 09 05:42:55 PM PDT 24
Peak memory 200156 kb
Host smart-cbe0592f-8965-475a-b7ea-b1fe5ad93154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414717448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1414717448
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3552083278
Short name T242
Test name
Test status
Simulation time 232997797 ps
CPU time 1.54 seconds
Started Jul 09 05:42:58 PM PDT 24
Finished Jul 09 05:43:01 PM PDT 24
Peak memory 200188 kb
Host smart-56c08100-7313-401e-87bb-7016622d25b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552083278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3552083278
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1682042163
Short name T506
Test name
Test status
Simulation time 321623976 ps
CPU time 2.23 seconds
Started Jul 09 05:42:54 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 200184 kb
Host smart-86129b80-e5e4-4547-bdfb-6563fd78725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682042163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1682042163
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.518393102
Short name T521
Test name
Test status
Simulation time 77198561 ps
CPU time 0.88 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:56 PM PDT 24
Peak memory 200140 kb
Host smart-e55e18dc-9ff0-433f-a049-51000998c382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518393102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.518393102
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.932790379
Short name T3
Test name
Test status
Simulation time 80569544 ps
CPU time 0.77 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:56 PM PDT 24
Peak memory 199956 kb
Host smart-b937fef1-4be7-45fb-a298-4b5017f76bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932790379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.932790379
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3778249445
Short name T57
Test name
Test status
Simulation time 2348213610 ps
CPU time 7.81 seconds
Started Jul 09 05:42:50 PM PDT 24
Finished Jul 09 05:43:01 PM PDT 24
Peak memory 217976 kb
Host smart-78adea04-15ca-48f5-bfb5-ab431ddbba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778249445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3778249445
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3430801279
Short name T319
Test name
Test status
Simulation time 244622404 ps
CPU time 1.11 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:56 PM PDT 24
Peak memory 217480 kb
Host smart-8649f870-8667-4d68-97d4-7ff027621fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430801279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3430801279
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.84342555
Short name T474
Test name
Test status
Simulation time 236542258 ps
CPU time 0.94 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:56 PM PDT 24
Peak memory 199980 kb
Host smart-77ee54f5-e495-4eca-a9fa-f09b848aba52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84342555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.84342555
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3485828032
Short name T92
Test name
Test status
Simulation time 1856540969 ps
CPU time 7.13 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 200488 kb
Host smart-0394df0b-051a-40fe-9e7e-b0ecc4e79282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485828032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3485828032
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.4198167709
Short name T168
Test name
Test status
Simulation time 114066935 ps
CPU time 1.02 seconds
Started Jul 09 05:42:50 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 200076 kb
Host smart-b54d02c1-da82-4d45-9dca-424787c8cea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198167709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.4198167709
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.921497651
Short name T151
Test name
Test status
Simulation time 125316407 ps
CPU time 1.22 seconds
Started Jul 09 05:42:50 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 200316 kb
Host smart-539d06a8-8748-4545-9b66-0b0dabc5fff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921497651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.921497651
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.986210406
Short name T513
Test name
Test status
Simulation time 7156456846 ps
CPU time 25.45 seconds
Started Jul 09 05:42:50 PM PDT 24
Finished Jul 09 05:43:19 PM PDT 24
Peak memory 200448 kb
Host smart-6f84d018-009a-4c9a-8367-b5328aa09f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986210406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.986210406
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3827551636
Short name T205
Test name
Test status
Simulation time 134537258 ps
CPU time 1.69 seconds
Started Jul 09 05:42:51 PM PDT 24
Finished Jul 09 05:42:55 PM PDT 24
Peak memory 200180 kb
Host smart-77b17934-0ea7-43ec-80dc-fcb1d27e0e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827551636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3827551636
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.513988953
Short name T250
Test name
Test status
Simulation time 255034017 ps
CPU time 1.49 seconds
Started Jul 09 05:42:50 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 200128 kb
Host smart-fa13a007-d0ac-4d68-8c58-222405626b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513988953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.513988953
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1285360356
Short name T178
Test name
Test status
Simulation time 69188490 ps
CPU time 0.78 seconds
Started Jul 09 05:42:54 PM PDT 24
Finished Jul 09 05:42:58 PM PDT 24
Peak memory 199920 kb
Host smart-a62679ac-368e-4ca3-a4d4-b052e8b10da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285360356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1285360356
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.4055535874
Short name T51
Test name
Test status
Simulation time 1876965356 ps
CPU time 6.85 seconds
Started Jul 09 05:42:54 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 217764 kb
Host smart-5315c1e9-fe19-4f76-8b98-e76ffa369792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055535874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.4055535874
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.66270891
Short name T285
Test name
Test status
Simulation time 245149877 ps
CPU time 1.14 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:42:58 PM PDT 24
Peak memory 217420 kb
Host smart-0a568855-a102-4529-9bca-ced5ef4c91b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66270891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.66270891
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3081176537
Short name T19
Test name
Test status
Simulation time 145781821 ps
CPU time 0.9 seconds
Started Jul 09 05:42:49 PM PDT 24
Finished Jul 09 05:42:53 PM PDT 24
Peak memory 199920 kb
Host smart-61f28a9d-4653-4009-8d7e-7812db11de37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081176537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3081176537
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2699540042
Short name T176
Test name
Test status
Simulation time 726865402 ps
CPU time 3.64 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 200440 kb
Host smart-cc4e8324-1977-4014-a56e-342e0858d519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699540042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2699540042
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1684127082
Short name T189
Test name
Test status
Simulation time 177449833 ps
CPU time 1.23 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 200184 kb
Host smart-4a44479c-4861-4ada-8ad9-4383a52dcc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684127082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1684127082
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1413946819
Short name T392
Test name
Test status
Simulation time 111457349 ps
CPU time 1.18 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:42:58 PM PDT 24
Peak memory 200256 kb
Host smart-b7929b76-04eb-4c81-bf23-f488c927826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413946819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1413946819
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1583132080
Short name T443
Test name
Test status
Simulation time 681613088 ps
CPU time 3.07 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:42:59 PM PDT 24
Peak memory 200352 kb
Host smart-2fcc63c3-878a-43c4-84a3-7c6d8f478bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583132080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1583132080
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2784399813
Short name T145
Test name
Test status
Simulation time 324195166 ps
CPU time 2.51 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 200124 kb
Host smart-53d1f909-7b49-4f3d-b5a9-4ea498419606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784399813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2784399813
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4113503422
Short name T54
Test name
Test status
Simulation time 134372373 ps
CPU time 1.16 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:42:58 PM PDT 24
Peak memory 200168 kb
Host smart-2a0a7fc4-6f3e-4dc5-9213-e4dc894ac60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113503422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4113503422
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.118137685
Short name T126
Test name
Test status
Simulation time 73314599 ps
CPU time 0.75 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:36 PM PDT 24
Peak memory 199964 kb
Host smart-9e46a510-052b-4ae8-a98e-cf81004f17c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118137685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.118137685
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2589778780
Short name T39
Test name
Test status
Simulation time 1222045155 ps
CPU time 5.58 seconds
Started Jul 09 05:42:32 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 221716 kb
Host smart-3eb792f4-99ae-4b0b-8db1-7268d89e037f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589778780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2589778780
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3010720731
Short name T354
Test name
Test status
Simulation time 244451055 ps
CPU time 1.06 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:42:33 PM PDT 24
Peak memory 217452 kb
Host smart-bb132b62-4e8e-4adb-a4d6-15c7676e9b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010720731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3010720731
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.790537592
Short name T21
Test name
Test status
Simulation time 99541062 ps
CPU time 0.75 seconds
Started Jul 09 05:42:30 PM PDT 24
Finished Jul 09 05:42:31 PM PDT 24
Peak memory 199996 kb
Host smart-30f57fed-0786-4f0f-b972-6b9c64b8cdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790537592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.790537592
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2846797453
Short name T214
Test name
Test status
Simulation time 776375262 ps
CPU time 4.14 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:37 PM PDT 24
Peak memory 200340 kb
Host smart-bc3ae787-7a58-4e01-980c-ce2c6aa9c6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846797453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2846797453
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1379821941
Short name T10
Test name
Test status
Simulation time 8274755932 ps
CPU time 15.4 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:51 PM PDT 24
Peak memory 217472 kb
Host smart-a0fa8f9a-5f39-4e11-bd70-b1f6bb93f49d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379821941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1379821941
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1049700725
Short name T498
Test name
Test status
Simulation time 167534880 ps
CPU time 1.15 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:35 PM PDT 24
Peak memory 200164 kb
Host smart-8a88ff9c-4fd8-420b-a919-69e0876b4905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049700725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1049700725
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1651079272
Short name T120
Test name
Test status
Simulation time 219618598 ps
CPU time 1.46 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:35 PM PDT 24
Peak memory 200352 kb
Host smart-4f077255-b5fe-443a-9f44-fa8a5b56d9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651079272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1651079272
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3577118931
Short name T95
Test name
Test status
Simulation time 5234401991 ps
CPU time 24.36 seconds
Started Jul 09 05:42:29 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 200436 kb
Host smart-970cbaf5-e698-469b-922d-6e59072bc613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577118931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3577118931
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2672448330
Short name T475
Test name
Test status
Simulation time 402696777 ps
CPU time 2.15 seconds
Started Jul 09 05:42:32 PM PDT 24
Finished Jul 09 05:42:35 PM PDT 24
Peak memory 208316 kb
Host smart-5fa55e25-57f6-4797-8299-98e6703b78a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672448330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2672448330
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2422531168
Short name T487
Test name
Test status
Simulation time 202944073 ps
CPU time 1.25 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:42:33 PM PDT 24
Peak memory 200180 kb
Host smart-4a7667e5-6825-4855-92c1-1b635469632b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422531168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2422531168
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.464131089
Short name T290
Test name
Test status
Simulation time 60692169 ps
CPU time 0.7 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:56 PM PDT 24
Peak memory 199972 kb
Host smart-9a4f9571-9989-4401-96d2-75da75d37d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464131089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.464131089
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.630646747
Short name T431
Test name
Test status
Simulation time 1216586437 ps
CPU time 5.67 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 217720 kb
Host smart-7e2ef58d-da5e-4141-ba93-4720d27bf07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630646747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.630646747
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2534398049
Short name T532
Test name
Test status
Simulation time 244151314 ps
CPU time 1.04 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 217540 kb
Host smart-d62c3f44-1587-42c9-8928-7557e6ea84c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534398049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2534398049
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2102767435
Short name T363
Test name
Test status
Simulation time 255822941 ps
CPU time 1.03 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 199968 kb
Host smart-3b72387c-8405-41ad-abb9-5467d25a7a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102767435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2102767435
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2051012348
Short name T74
Test name
Test status
Simulation time 723044089 ps
CPU time 4.07 seconds
Started Jul 09 05:42:57 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 200440 kb
Host smart-60031ba2-5990-4e9c-9fa1-7457fd979125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051012348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2051012348
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1713067499
Short name T298
Test name
Test status
Simulation time 100538096 ps
CPU time 0.97 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 200164 kb
Host smart-92c1d52a-acd2-45b7-8deb-b0c7c1be6079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713067499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1713067499
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.266805521
Short name T341
Test name
Test status
Simulation time 244659477 ps
CPU time 1.45 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 200360 kb
Host smart-c948c7e1-3346-4866-9259-e1835c78ec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266805521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.266805521
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2447326756
Short name T499
Test name
Test status
Simulation time 4131194916 ps
CPU time 19.01 seconds
Started Jul 09 05:43:02 PM PDT 24
Finished Jul 09 05:43:22 PM PDT 24
Peak memory 208636 kb
Host smart-8165918e-4e7b-4d49-8f78-13de6143d2c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447326756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2447326756
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2514686170
Short name T185
Test name
Test status
Simulation time 135864548 ps
CPU time 1.63 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:05 PM PDT 24
Peak memory 200100 kb
Host smart-cc46f4e0-1135-4f6b-b567-bfe97de426ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514686170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2514686170
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2493162014
Short name T229
Test name
Test status
Simulation time 72781929 ps
CPU time 0.77 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:42:59 PM PDT 24
Peak memory 200120 kb
Host smart-67d51d66-e2fe-4d78-be86-f0d4d00b42b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493162014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2493162014
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1477959988
Short name T93
Test name
Test status
Simulation time 86229876 ps
CPU time 0.83 seconds
Started Jul 09 05:42:54 PM PDT 24
Finished Jul 09 05:42:58 PM PDT 24
Peak memory 199924 kb
Host smart-28a6b30f-a449-4846-a7fe-374ec09287d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477959988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1477959988
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3979429008
Short name T453
Test name
Test status
Simulation time 2160968565 ps
CPU time 7.89 seconds
Started Jul 09 05:42:54 PM PDT 24
Finished Jul 09 05:43:05 PM PDT 24
Peak memory 221668 kb
Host smart-45895c8b-c9ee-41b8-921b-a2fafc52a5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979429008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3979429008
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2271210333
Short name T375
Test name
Test status
Simulation time 245240929 ps
CPU time 1.03 seconds
Started Jul 09 05:42:51 PM PDT 24
Finished Jul 09 05:42:55 PM PDT 24
Peak memory 217536 kb
Host smart-47adfc46-38ac-4f83-b923-92ab70795fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271210333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2271210333
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1416511532
Short name T22
Test name
Test status
Simulation time 199738777 ps
CPU time 0.91 seconds
Started Jul 09 05:42:54 PM PDT 24
Finished Jul 09 05:42:58 PM PDT 24
Peak memory 199960 kb
Host smart-4f189db2-34d1-4740-93eb-c1307dec9441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416511532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1416511532
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1726661259
Short name T77
Test name
Test status
Simulation time 1374245647 ps
CPU time 5.83 seconds
Started Jul 09 05:42:58 PM PDT 24
Finished Jul 09 05:43:05 PM PDT 24
Peak memory 200436 kb
Host smart-90c55543-1b05-4297-8ec2-f4b8953a969c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726661259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1726661259
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3375965314
Short name T518
Test name
Test status
Simulation time 96830645 ps
CPU time 1.01 seconds
Started Jul 09 05:42:58 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 200184 kb
Host smart-6358af26-4ec0-4373-ab6c-cd265e15fde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375965314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3375965314
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1773616488
Short name T481
Test name
Test status
Simulation time 256915254 ps
CPU time 1.48 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 200308 kb
Host smart-7a09687b-4804-4045-b970-4d51286b4076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773616488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1773616488
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1170187647
Short name T83
Test name
Test status
Simulation time 2155207459 ps
CPU time 11.16 seconds
Started Jul 09 05:42:55 PM PDT 24
Finished Jul 09 05:43:09 PM PDT 24
Peak memory 209012 kb
Host smart-bb3c1ea2-f12b-452e-932d-1488a50e58da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170187647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1170187647
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3291226331
Short name T268
Test name
Test status
Simulation time 422904329 ps
CPU time 2.45 seconds
Started Jul 09 05:42:58 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 208176 kb
Host smart-b97f36e8-6945-41cd-a410-77401f109d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291226331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3291226331
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3360308754
Short name T307
Test name
Test status
Simulation time 56655232 ps
CPU time 0.76 seconds
Started Jul 09 05:42:52 PM PDT 24
Finished Jul 09 05:42:56 PM PDT 24
Peak memory 200144 kb
Host smart-4b10dd57-dd22-49c3-85cf-b003d55cdd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360308754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3360308754
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3707800644
Short name T181
Test name
Test status
Simulation time 58730013 ps
CPU time 0.71 seconds
Started Jul 09 05:43:00 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 199968 kb
Host smart-4c5ff35d-5919-4420-835e-8e81f13480e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707800644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3707800644
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1118112969
Short name T328
Test name
Test status
Simulation time 1890536104 ps
CPU time 6.87 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 217780 kb
Host smart-9ae902c8-62a7-48f4-8293-a6c0033773d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118112969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1118112969
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2649730275
Short name T252
Test name
Test status
Simulation time 245165615 ps
CPU time 1.08 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:42:57 PM PDT 24
Peak memory 217540 kb
Host smart-644fdf0a-a76e-4fd9-9380-5d64dae2359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649730275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2649730275
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3411711917
Short name T535
Test name
Test status
Simulation time 88659670 ps
CPU time 0.81 seconds
Started Jul 09 05:42:54 PM PDT 24
Finished Jul 09 05:42:58 PM PDT 24
Peak memory 199972 kb
Host smart-7cd38d4a-a71c-4fa9-9a7b-d356e0da5179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411711917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3411711917
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1502542730
Short name T131
Test name
Test status
Simulation time 967909068 ps
CPU time 4.98 seconds
Started Jul 09 05:42:57 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 200436 kb
Host smart-091bfd64-965f-4054-9615-4bb80d729446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502542730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1502542730
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2805373022
Short name T390
Test name
Test status
Simulation time 148416170 ps
CPU time 1.18 seconds
Started Jul 09 05:42:53 PM PDT 24
Finished Jul 09 05:42:58 PM PDT 24
Peak memory 200060 kb
Host smart-28bfcc38-8c99-4683-aa85-d06c5d357cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805373022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2805373022
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3967825318
Short name T361
Test name
Test status
Simulation time 119649440 ps
CPU time 1.16 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 200304 kb
Host smart-5699b61b-b2df-49c2-97c5-0ba249ca04af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967825318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3967825318
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.778855978
Short name T464
Test name
Test status
Simulation time 125151083 ps
CPU time 1 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 199904 kb
Host smart-5cd6a0da-dd24-4948-a012-6d6ad32c2b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778855978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.778855978
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1250274190
Short name T458
Test name
Test status
Simulation time 122289387 ps
CPU time 1.47 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 200112 kb
Host smart-e3ffe12c-ff60-499a-bc2c-8185a3d3dc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250274190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1250274190
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3926650416
Short name T482
Test name
Test status
Simulation time 135071499 ps
CPU time 0.99 seconds
Started Jul 09 05:42:54 PM PDT 24
Finished Jul 09 05:42:58 PM PDT 24
Peak memory 200076 kb
Host smart-0e0dab40-393e-42ea-921a-9f3c78b45164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926650416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3926650416
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2189462604
Short name T238
Test name
Test status
Simulation time 72490639 ps
CPU time 0.74 seconds
Started Jul 09 05:42:55 PM PDT 24
Finished Jul 09 05:42:58 PM PDT 24
Peak memory 199916 kb
Host smart-8987d01d-9ea4-4186-9264-31b92b4c26a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189462604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2189462604
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2913360468
Short name T36
Test name
Test status
Simulation time 1902305804 ps
CPU time 7.63 seconds
Started Jul 09 05:42:57 PM PDT 24
Finished Jul 09 05:43:06 PM PDT 24
Peak memory 221568 kb
Host smart-34dc438c-9215-4f2e-9787-eaa40d2b69b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913360468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2913360468
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3364146626
Short name T376
Test name
Test status
Simulation time 243867993 ps
CPU time 1.08 seconds
Started Jul 09 05:42:58 PM PDT 24
Finished Jul 09 05:43:01 PM PDT 24
Peak memory 217480 kb
Host smart-655588f4-f071-4cc6-b74c-adf5cc21f415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364146626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3364146626
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2094396639
Short name T23
Test name
Test status
Simulation time 177648984 ps
CPU time 0.86 seconds
Started Jul 09 05:42:57 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 199920 kb
Host smart-e468b624-d62f-437f-ae3a-f4d629971c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094396639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2094396639
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.353159928
Short name T485
Test name
Test status
Simulation time 1156462816 ps
CPU time 4.52 seconds
Started Jul 09 05:42:58 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 200396 kb
Host smart-5d0b6d5c-a08a-4063-a891-2aac1aaa9813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353159928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.353159928
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2436447567
Short name T400
Test name
Test status
Simulation time 171115093 ps
CPU time 1.25 seconds
Started Jul 09 05:43:05 PM PDT 24
Finished Jul 09 05:43:07 PM PDT 24
Peak memory 200172 kb
Host smart-509af267-04e4-4d50-9f83-7aa000847b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436447567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2436447567
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.121612004
Short name T173
Test name
Test status
Simulation time 192203755 ps
CPU time 1.38 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 200356 kb
Host smart-0e8a12a6-2bd7-45e1-99aa-c60810af3924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121612004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.121612004
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2756912375
Short name T201
Test name
Test status
Simulation time 2538174477 ps
CPU time 10.6 seconds
Started Jul 09 05:42:59 PM PDT 24
Finished Jul 09 05:43:11 PM PDT 24
Peak memory 200468 kb
Host smart-61a38801-ba46-49e8-bf98-51f5e67628c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756912375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2756912375
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.895527
Short name T227
Test name
Test status
Simulation time 320251562 ps
CPU time 2.13 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 200224 kb
Host smart-07c1b350-560d-416b-a10f-774aedf0ee8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.895527
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2012671614
Short name T399
Test name
Test status
Simulation time 217624182 ps
CPU time 1.39 seconds
Started Jul 09 05:43:00 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 200180 kb
Host smart-b2bdb145-7a17-4c1c-b387-4ece8d33a9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012671614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2012671614
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3294110057
Short name T444
Test name
Test status
Simulation time 69992178 ps
CPU time 0.78 seconds
Started Jul 09 05:42:57 PM PDT 24
Finished Jul 09 05:42:59 PM PDT 24
Peak memory 199952 kb
Host smart-bc6f4f84-f426-4c7c-bdb1-000c404d9b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294110057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3294110057
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1110860789
Short name T47
Test name
Test status
Simulation time 1880884030 ps
CPU time 7.46 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:43:06 PM PDT 24
Peak memory 229892 kb
Host smart-c32285d6-bc25-4ac0-8b7d-6890f1ef4e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110860789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1110860789
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.982136546
Short name T1
Test name
Test status
Simulation time 245491664 ps
CPU time 1.03 seconds
Started Jul 09 05:43:02 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 217520 kb
Host smart-415f4480-6fd6-4966-b971-b8ce86453d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982136546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.982136546
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2162341316
Short name T279
Test name
Test status
Simulation time 186323091 ps
CPU time 0.87 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 199932 kb
Host smart-4c2bd5a4-0592-4e5b-a2eb-d62c5c107082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162341316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2162341316
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.769498286
Short name T326
Test name
Test status
Simulation time 895998379 ps
CPU time 4.71 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 200400 kb
Host smart-0513c9ca-cc1e-49d8-b3d1-73118ed46148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769498286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.769498286
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.195199009
Short name T146
Test name
Test status
Simulation time 146530007 ps
CPU time 1.11 seconds
Started Jul 09 05:42:58 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 200156 kb
Host smart-340726cf-a9d8-4495-897f-fe5c9b637bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195199009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.195199009
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.4248307167
Short name T358
Test name
Test status
Simulation time 128029975 ps
CPU time 1.27 seconds
Started Jul 09 05:42:59 PM PDT 24
Finished Jul 09 05:43:01 PM PDT 24
Peak memory 200376 kb
Host smart-16c2d681-d495-46dd-bdf9-fc6937570659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248307167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4248307167
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.4161771220
Short name T161
Test name
Test status
Simulation time 5102326794 ps
CPU time 25.1 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:28 PM PDT 24
Peak memory 208676 kb
Host smart-7e1e2211-d4c1-4ddb-ba48-12a14686d556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161771220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4161771220
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2379556790
Short name T440
Test name
Test status
Simulation time 111747342 ps
CPU time 1.41 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 200156 kb
Host smart-118b61e1-88bd-46fe-a21b-84e7c287e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379556790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2379556790
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2217407060
Short name T463
Test name
Test status
Simulation time 89536836 ps
CPU time 0.87 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:42:59 PM PDT 24
Peak memory 200092 kb
Host smart-1fc1c30f-72b6-441a-aa18-b75b0776a0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217407060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2217407060
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2931442973
Short name T152
Test name
Test status
Simulation time 68439812 ps
CPU time 0.78 seconds
Started Jul 09 05:43:02 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 199936 kb
Host smart-3580e068-79af-4d32-b65c-68f2032169d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931442973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2931442973
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3646910080
Short name T345
Test name
Test status
Simulation time 2352336598 ps
CPU time 8.07 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:43:06 PM PDT 24
Peak memory 217924 kb
Host smart-c9cac292-fe5a-4b83-8860-1f080699b543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646910080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3646910080
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3327903276
Short name T45
Test name
Test status
Simulation time 243903843 ps
CPU time 1.16 seconds
Started Jul 09 05:42:59 PM PDT 24
Finished Jul 09 05:43:01 PM PDT 24
Peak memory 217508 kb
Host smart-5a353841-d854-494a-8887-323c87340e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327903276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3327903276
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2322763239
Short name T352
Test name
Test status
Simulation time 121956380 ps
CPU time 0.86 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:42:59 PM PDT 24
Peak memory 199944 kb
Host smart-11b5c723-b0f2-4594-aef0-5a0ef82c3e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322763239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2322763239
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3732693407
Short name T479
Test name
Test status
Simulation time 1075950632 ps
CPU time 5.34 seconds
Started Jul 09 05:42:58 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 200360 kb
Host smart-937bbab7-813e-4beb-886e-2ef2d24b6894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732693407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3732693407
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1599990465
Short name T335
Test name
Test status
Simulation time 105731268 ps
CPU time 1.1 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 200160 kb
Host smart-b5cc7f05-0e38-4d4f-b1fc-de3aba577468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599990465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1599990465
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2486114501
Short name T260
Test name
Test status
Simulation time 119567009 ps
CPU time 1.23 seconds
Started Jul 09 05:42:55 PM PDT 24
Finished Jul 09 05:42:59 PM PDT 24
Peak memory 200380 kb
Host smart-5bc0dacb-8a1e-4c08-ab84-d39e11734ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486114501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2486114501
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.46413903
Short name T517
Test name
Test status
Simulation time 1607542738 ps
CPU time 7.33 seconds
Started Jul 09 05:43:03 PM PDT 24
Finished Jul 09 05:43:11 PM PDT 24
Peak memory 208624 kb
Host smart-61ed9110-1fd9-40db-9604-ebc7d7c6d670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46413903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.46413903
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3106566293
Short name T163
Test name
Test status
Simulation time 127733154 ps
CPU time 1.61 seconds
Started Jul 09 05:42:59 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 208384 kb
Host smart-5d74f4b1-934d-4b7b-8142-503b481f14c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106566293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3106566293
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3087704407
Short name T158
Test name
Test status
Simulation time 131909569 ps
CPU time 1.17 seconds
Started Jul 09 05:42:56 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 200160 kb
Host smart-b8176646-2961-4ab0-9860-03b5b4209c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087704407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3087704407
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3538197347
Short name T369
Test name
Test status
Simulation time 71496399 ps
CPU time 0.81 seconds
Started Jul 09 05:42:59 PM PDT 24
Finished Jul 09 05:43:01 PM PDT 24
Peak memory 199980 kb
Host smart-589edd3f-d1c8-40c7-a3d6-8686322caf9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538197347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3538197347
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.4212644782
Short name T43
Test name
Test status
Simulation time 1894748580 ps
CPU time 8.24 seconds
Started Jul 09 05:43:00 PM PDT 24
Finished Jul 09 05:43:09 PM PDT 24
Peak memory 217796 kb
Host smart-7a8409ad-2494-4357-9152-494458076c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212644782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.4212644782
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3099150526
Short name T385
Test name
Test status
Simulation time 244750079 ps
CPU time 1.13 seconds
Started Jul 09 05:43:04 PM PDT 24
Finished Jul 09 05:43:05 PM PDT 24
Peak memory 217556 kb
Host smart-2db71a1e-a2cb-402a-8a72-1c1eaf6c8edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099150526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3099150526
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2167558002
Short name T415
Test name
Test status
Simulation time 132583442 ps
CPU time 0.84 seconds
Started Jul 09 05:43:07 PM PDT 24
Finished Jul 09 05:43:09 PM PDT 24
Peak memory 199992 kb
Host smart-bf524e17-a12b-43f5-88f7-e3cf50fcdb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167558002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2167558002
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3424556126
Short name T297
Test name
Test status
Simulation time 1285168855 ps
CPU time 5.01 seconds
Started Jul 09 05:42:59 PM PDT 24
Finished Jul 09 05:43:05 PM PDT 24
Peak memory 200428 kb
Host smart-c43162b2-842d-4e0c-add5-5c51c9f92e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424556126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3424556126
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.797635865
Short name T525
Test name
Test status
Simulation time 145022489 ps
CPU time 1.24 seconds
Started Jul 09 05:43:00 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 200144 kb
Host smart-c92ab137-4aef-45e9-9b22-9054b9c193c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797635865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.797635865
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3163640539
Short name T282
Test name
Test status
Simulation time 205738922 ps
CPU time 1.43 seconds
Started Jul 09 05:42:59 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 200372 kb
Host smart-011df886-cb39-4748-bc8e-5963a0372e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163640539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3163640539
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1787597623
Short name T470
Test name
Test status
Simulation time 4940436762 ps
CPU time 16.84 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:18 PM PDT 24
Peak memory 208648 kb
Host smart-3a290aa1-18ad-43ee-86cc-5986bc0a5f5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787597623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1787597623
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.726736409
Short name T304
Test name
Test status
Simulation time 381210377 ps
CPU time 2.37 seconds
Started Jul 09 05:43:13 PM PDT 24
Finished Jul 09 05:43:17 PM PDT 24
Peak memory 200172 kb
Host smart-afc0c743-4f02-4f4b-9116-a76631e30f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726736409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.726736409
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1452996458
Short name T171
Test name
Test status
Simulation time 193818192 ps
CPU time 1.24 seconds
Started Jul 09 05:43:02 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 200104 kb
Host smart-8aa7bf4f-d8cf-469c-9f2e-ec1d8edb32bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452996458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1452996458
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2738460958
Short name T359
Test name
Test status
Simulation time 70408946 ps
CPU time 0.75 seconds
Started Jul 09 05:43:02 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 199892 kb
Host smart-91e95d07-d2bf-4b97-ae94-14f76100e7ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738460958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2738460958
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3325574958
Short name T311
Test name
Test status
Simulation time 1908466371 ps
CPU time 7.35 seconds
Started Jul 09 05:43:03 PM PDT 24
Finished Jul 09 05:43:11 PM PDT 24
Peak memory 217832 kb
Host smart-abf1c131-5d21-4ee6-81b7-c14f607dabeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325574958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3325574958
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3510584996
Short name T368
Test name
Test status
Simulation time 244367855 ps
CPU time 1.06 seconds
Started Jul 09 05:43:03 PM PDT 24
Finished Jul 09 05:43:05 PM PDT 24
Peak memory 217536 kb
Host smart-e770e823-6bdc-4c2a-aae0-200caef77d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510584996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3510584996
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2394756153
Short name T420
Test name
Test status
Simulation time 177200209 ps
CPU time 0.85 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 199928 kb
Host smart-c32c6cf7-8a5e-426c-b521-ac314302484d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394756153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2394756153
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1532905855
Short name T137
Test name
Test status
Simulation time 776459172 ps
CPU time 3.93 seconds
Started Jul 09 05:42:59 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 200432 kb
Host smart-b3ad0741-8f78-4b7f-b058-9971908184be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532905855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1532905855
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3044955008
Short name T473
Test name
Test status
Simulation time 108316948 ps
CPU time 1.03 seconds
Started Jul 09 05:43:03 PM PDT 24
Finished Jul 09 05:43:05 PM PDT 24
Peak memory 200188 kb
Host smart-c97a061d-6646-494f-a876-0596e39b7cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044955008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3044955008
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.545279751
Short name T226
Test name
Test status
Simulation time 126648984 ps
CPU time 1.21 seconds
Started Jul 09 05:43:05 PM PDT 24
Finished Jul 09 05:43:07 PM PDT 24
Peak memory 200380 kb
Host smart-e703c464-dd5b-4c6d-8da6-bd69e3a7924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545279751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.545279751
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3367150687
Short name T299
Test name
Test status
Simulation time 6612754134 ps
CPU time 31.58 seconds
Started Jul 09 05:43:13 PM PDT 24
Finished Jul 09 05:43:46 PM PDT 24
Peak memory 208676 kb
Host smart-b37412bf-afe0-4906-a4cb-92a0540d0225
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367150687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3367150687
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.406189170
Short name T505
Test name
Test status
Simulation time 145697685 ps
CPU time 1.82 seconds
Started Jul 09 05:43:01 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 200128 kb
Host smart-0bf97698-e65f-460b-8f6a-55f1944536e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406189170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.406189170
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3836315184
Short name T405
Test name
Test status
Simulation time 101525462 ps
CPU time 1.03 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:34 PM PDT 24
Peak memory 200132 kb
Host smart-3b712495-cf03-4f2e-81aa-2671167665e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836315184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3836315184
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2011576483
Short name T167
Test name
Test status
Simulation time 65690320 ps
CPU time 0.74 seconds
Started Jul 09 05:43:05 PM PDT 24
Finished Jul 09 05:43:07 PM PDT 24
Peak memory 199972 kb
Host smart-c55050a4-6332-4d3d-b1b8-2b5ac94d41de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011576483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2011576483
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3244166227
Short name T433
Test name
Test status
Simulation time 2164129011 ps
CPU time 8.71 seconds
Started Jul 09 05:43:13 PM PDT 24
Finished Jul 09 05:43:23 PM PDT 24
Peak memory 217564 kb
Host smart-f8fc747d-aef7-4397-b7b6-cb76e0547c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244166227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3244166227
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.27294199
Short name T169
Test name
Test status
Simulation time 244404467 ps
CPU time 1.09 seconds
Started Jul 09 05:43:09 PM PDT 24
Finished Jul 09 05:43:11 PM PDT 24
Peak memory 217540 kb
Host smart-d7a40496-24a2-47bf-959b-b98345073efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27294199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.27294199
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2234704975
Short name T509
Test name
Test status
Simulation time 164954766 ps
CPU time 0.92 seconds
Started Jul 09 05:43:05 PM PDT 24
Finished Jul 09 05:43:07 PM PDT 24
Peak memory 199948 kb
Host smart-96d47e0f-b487-4f35-9dc0-e7c27730ed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234704975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2234704975
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1172301115
Short name T186
Test name
Test status
Simulation time 1017161440 ps
CPU time 4.82 seconds
Started Jul 09 05:43:05 PM PDT 24
Finished Jul 09 05:43:10 PM PDT 24
Peak memory 200436 kb
Host smart-b8ebcb27-ca6d-4841-817e-5010b621298c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172301115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1172301115
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2292031212
Short name T355
Test name
Test status
Simulation time 105036877 ps
CPU time 1 seconds
Started Jul 09 05:43:06 PM PDT 24
Finished Jul 09 05:43:07 PM PDT 24
Peak memory 200172 kb
Host smart-452003be-b3ad-4f1d-9e2d-8c65d5a528e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292031212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2292031212
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1997319896
Short name T266
Test name
Test status
Simulation time 123865561 ps
CPU time 1.3 seconds
Started Jul 09 05:43:05 PM PDT 24
Finished Jul 09 05:43:07 PM PDT 24
Peak memory 200380 kb
Host smart-b705ce70-7306-495c-bbce-d369054693d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997319896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1997319896
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2291924564
Short name T156
Test name
Test status
Simulation time 5487029738 ps
CPU time 26.16 seconds
Started Jul 09 05:43:15 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 208676 kb
Host smart-26aa8161-b163-4ab5-8c8a-e6b149575c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291924564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2291924564
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3269767538
Short name T60
Test name
Test status
Simulation time 481752407 ps
CPU time 2.76 seconds
Started Jul 09 05:43:03 PM PDT 24
Finished Jul 09 05:43:07 PM PDT 24
Peak memory 200120 kb
Host smart-439327ed-13c0-474d-a77a-bffb09ccdc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269767538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3269767538
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1891927788
Short name T11
Test name
Test status
Simulation time 237690043 ps
CPU time 1.41 seconds
Started Jul 09 05:43:04 PM PDT 24
Finished Jul 09 05:43:06 PM PDT 24
Peak memory 200384 kb
Host smart-376bf9f1-f2b3-4f6f-b413-2fc8ed0abb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891927788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1891927788
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.317871965
Short name T208
Test name
Test status
Simulation time 251948010 ps
CPU time 1.15 seconds
Started Jul 09 05:43:11 PM PDT 24
Finished Jul 09 05:43:13 PM PDT 24
Peak memory 199896 kb
Host smart-73c9e4ea-88e6-47e2-b562-5a9b284ee6c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317871965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.317871965
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.810538556
Short name T529
Test name
Test status
Simulation time 1221963537 ps
CPU time 6.14 seconds
Started Jul 09 05:43:15 PM PDT 24
Finished Jul 09 05:43:22 PM PDT 24
Peak memory 221812 kb
Host smart-d71c392b-756f-4b8d-9964-4a7fdb936f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810538556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.810538556
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2279699615
Short name T394
Test name
Test status
Simulation time 244250801 ps
CPU time 1.1 seconds
Started Jul 09 05:43:17 PM PDT 24
Finished Jul 09 05:43:20 PM PDT 24
Peak memory 217532 kb
Host smart-266ed446-199e-445e-b9fd-97cbf05912db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279699615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2279699615
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1129917327
Short name T170
Test name
Test status
Simulation time 132455663 ps
CPU time 0.78 seconds
Started Jul 09 05:43:11 PM PDT 24
Finished Jul 09 05:43:13 PM PDT 24
Peak memory 199984 kb
Host smart-56ac75a7-f1ae-4312-b9c9-95124212b0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129917327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1129917327
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1264438387
Short name T522
Test name
Test status
Simulation time 1251876010 ps
CPU time 4.77 seconds
Started Jul 09 05:43:19 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 200440 kb
Host smart-dfe82ede-5a57-43a3-9f9a-162216383afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264438387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1264438387
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1249012530
Short name T539
Test name
Test status
Simulation time 112486214 ps
CPU time 1 seconds
Started Jul 09 05:43:11 PM PDT 24
Finished Jul 09 05:43:13 PM PDT 24
Peak memory 200176 kb
Host smart-a37dbdad-d584-47ad-957f-1fefb5176356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249012530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1249012530
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1749449865
Short name T292
Test name
Test status
Simulation time 256860970 ps
CPU time 1.57 seconds
Started Jul 09 05:43:05 PM PDT 24
Finished Jul 09 05:43:07 PM PDT 24
Peak memory 200336 kb
Host smart-dfa9f5cb-143f-4800-b135-785a0b1c7aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749449865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1749449865
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3317021493
Short name T425
Test name
Test status
Simulation time 204485954 ps
CPU time 1.34 seconds
Started Jul 09 05:43:05 PM PDT 24
Finished Jul 09 05:43:07 PM PDT 24
Peak memory 199944 kb
Host smart-e9611cfd-c450-4c89-a6bd-ef9c265a49bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317021493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3317021493
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.601186999
Short name T246
Test name
Test status
Simulation time 424361832 ps
CPU time 2.5 seconds
Started Jul 09 05:43:11 PM PDT 24
Finished Jul 09 05:43:14 PM PDT 24
Peak memory 208372 kb
Host smart-ed3a9e2d-240f-4278-a3d9-feffca52aa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601186999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.601186999
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3559545498
Short name T223
Test name
Test status
Simulation time 127273884 ps
CPU time 1.13 seconds
Started Jul 09 05:43:07 PM PDT 24
Finished Jul 09 05:43:09 PM PDT 24
Peak memory 200160 kb
Host smart-271f5343-25bc-453d-ab4a-bd79df9558f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559545498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3559545498
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.150438885
Short name T429
Test name
Test status
Simulation time 56397555 ps
CPU time 0.82 seconds
Started Jul 09 05:42:38 PM PDT 24
Finished Jul 09 05:42:40 PM PDT 24
Peak memory 199868 kb
Host smart-b60022ff-b5ab-4f8f-8332-48ef36a13697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150438885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.150438885
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3742308659
Short name T49
Test name
Test status
Simulation time 2367599971 ps
CPU time 7.62 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:42:39 PM PDT 24
Peak memory 221796 kb
Host smart-bdfbf246-d2c1-4b24-afc4-665f2c8bba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742308659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3742308659
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1933569972
Short name T351
Test name
Test status
Simulation time 244079961 ps
CPU time 1.13 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:37 PM PDT 24
Peak memory 217512 kb
Host smart-41635718-2930-4c3c-83d8-af38edb76d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933569972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1933569972
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3530783647
Short name T466
Test name
Test status
Simulation time 198152522 ps
CPU time 0.89 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:34 PM PDT 24
Peak memory 199900 kb
Host smart-249c0f5d-8598-4757-9c93-474a706bae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530783647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3530783647
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.443301221
Short name T26
Test name
Test status
Simulation time 1060498334 ps
CPU time 5.29 seconds
Started Jul 09 05:42:35 PM PDT 24
Finished Jul 09 05:42:42 PM PDT 24
Peak memory 200404 kb
Host smart-2dac8fd7-81cc-4d12-97d7-e66a273e6ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443301221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.443301221
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2943387722
Short name T70
Test name
Test status
Simulation time 16906577823 ps
CPU time 25.99 seconds
Started Jul 09 05:42:40 PM PDT 24
Finished Jul 09 05:43:06 PM PDT 24
Peak memory 217268 kb
Host smart-26372a5d-b169-4657-92d4-5023e44638f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943387722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2943387722
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.42241921
Short name T6
Test name
Test status
Simulation time 111497688 ps
CPU time 1.09 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:37 PM PDT 24
Peak memory 200048 kb
Host smart-f40c5521-33d7-4772-b379-44a331d78b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42241921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.42241921
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2979317824
Short name T530
Test name
Test status
Simulation time 198873844 ps
CPU time 1.35 seconds
Started Jul 09 05:42:31 PM PDT 24
Finished Jul 09 05:42:33 PM PDT 24
Peak memory 200392 kb
Host smart-b96a66d6-cea8-4abc-9024-8279bf8f4f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979317824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2979317824
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2266304400
Short name T428
Test name
Test status
Simulation time 2829102172 ps
CPU time 10.98 seconds
Started Jul 09 05:42:36 PM PDT 24
Finished Jul 09 05:42:48 PM PDT 24
Peak memory 208620 kb
Host smart-d8499b3d-c69f-4098-8f83-2c26b543aa50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266304400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2266304400
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.739648608
Short name T150
Test name
Test status
Simulation time 121484068 ps
CPU time 1.72 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:35 PM PDT 24
Peak memory 208304 kb
Host smart-a3c1a42e-ce6e-41d4-b70a-3ac1fb0e722b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739648608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.739648608
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2424439616
Short name T190
Test name
Test status
Simulation time 146945254 ps
CPU time 1.12 seconds
Started Jul 09 05:42:32 PM PDT 24
Finished Jul 09 05:42:34 PM PDT 24
Peak memory 200112 kb
Host smart-8957c124-dfe6-48b3-80c0-900f8f93a2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424439616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2424439616
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.336194036
Short name T172
Test name
Test status
Simulation time 80815439 ps
CPU time 0.83 seconds
Started Jul 09 05:43:15 PM PDT 24
Finished Jul 09 05:43:16 PM PDT 24
Peak memory 199920 kb
Host smart-48070f35-173c-40fa-a08b-0ac1e9d73fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336194036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.336194036
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3797276729
Short name T48
Test name
Test status
Simulation time 2356838932 ps
CPU time 7.92 seconds
Started Jul 09 05:43:12 PM PDT 24
Finished Jul 09 05:43:21 PM PDT 24
Peak memory 217940 kb
Host smart-f6664374-29d6-48ba-aed5-24c605106a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797276729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3797276729
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2996084323
Short name T264
Test name
Test status
Simulation time 244318056 ps
CPU time 1.16 seconds
Started Jul 09 05:43:13 PM PDT 24
Finished Jul 09 05:43:15 PM PDT 24
Peak memory 217496 kb
Host smart-913b96cf-158d-411a-9102-502f6c6037c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996084323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2996084323
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3344100160
Short name T337
Test name
Test status
Simulation time 219660679 ps
CPU time 1.05 seconds
Started Jul 09 05:43:14 PM PDT 24
Finished Jul 09 05:43:16 PM PDT 24
Peak memory 199924 kb
Host smart-2fcf3e32-e76c-44ee-b111-daae172a32a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344100160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3344100160
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.4172900320
Short name T323
Test name
Test status
Simulation time 1345748433 ps
CPU time 4.87 seconds
Started Jul 09 05:43:14 PM PDT 24
Finished Jul 09 05:43:20 PM PDT 24
Peak memory 200372 kb
Host smart-2a1f9784-50f2-49e9-88ec-808b23360e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172900320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4172900320
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.20553081
Short name T76
Test name
Test status
Simulation time 173823368 ps
CPU time 1.26 seconds
Started Jul 09 05:43:14 PM PDT 24
Finished Jul 09 05:43:16 PM PDT 24
Peak memory 200196 kb
Host smart-91aa4690-cc2c-4ca2-8469-3029932550ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20553081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.20553081
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.16589444
Short name T511
Test name
Test status
Simulation time 196357751 ps
CPU time 1.39 seconds
Started Jul 09 05:43:08 PM PDT 24
Finished Jul 09 05:43:10 PM PDT 24
Peak memory 200340 kb
Host smart-9d159cd4-8483-45f6-b60b-fc1665a5cd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16589444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.16589444
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2727502396
Short name T118
Test name
Test status
Simulation time 10227944654 ps
CPU time 38.91 seconds
Started Jul 09 05:43:18 PM PDT 24
Finished Jul 09 05:43:58 PM PDT 24
Peak memory 208684 kb
Host smart-09d451af-d9cc-4b4c-acee-21ce44ff1642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727502396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2727502396
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.15285857
Short name T389
Test name
Test status
Simulation time 326069547 ps
CPU time 2.29 seconds
Started Jul 09 05:43:16 PM PDT 24
Finished Jul 09 05:43:18 PM PDT 24
Peak memory 200200 kb
Host smart-4ce4a3e4-a0ec-446f-a794-5f3aa4bd5d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15285857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.15285857
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1829415754
Short name T318
Test name
Test status
Simulation time 221241829 ps
CPU time 1.28 seconds
Started Jul 09 05:43:15 PM PDT 24
Finished Jul 09 05:43:17 PM PDT 24
Peak memory 200192 kb
Host smart-d787d582-e8a8-4d95-8890-489898cb4b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829415754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1829415754
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.4177162331
Short name T302
Test name
Test status
Simulation time 95789763 ps
CPU time 0.85 seconds
Started Jul 09 05:43:10 PM PDT 24
Finished Jul 09 05:43:12 PM PDT 24
Peak memory 199864 kb
Host smart-c6425994-cb2e-493c-903e-298cfd5f9952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177162331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.4177162331
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.645290421
Short name T516
Test name
Test status
Simulation time 1231323759 ps
CPU time 5.36 seconds
Started Jul 09 05:43:08 PM PDT 24
Finished Jul 09 05:43:14 PM PDT 24
Peak memory 216840 kb
Host smart-856d073d-d5ab-410a-9f64-f60671a04c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645290421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.645290421
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.369388805
Short name T421
Test name
Test status
Simulation time 247281719 ps
CPU time 1.08 seconds
Started Jul 09 05:43:18 PM PDT 24
Finished Jul 09 05:43:20 PM PDT 24
Peak memory 217548 kb
Host smart-b56c3ef0-5650-4178-a8f8-b4c0f5db4384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369388805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.369388805
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1670460052
Short name T435
Test name
Test status
Simulation time 185373603 ps
CPU time 0.84 seconds
Started Jul 09 05:43:14 PM PDT 24
Finished Jul 09 05:43:16 PM PDT 24
Peak memory 199980 kb
Host smart-59697197-3308-44cd-ba1c-23d2283e4c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670460052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1670460052
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1897874379
Short name T94
Test name
Test status
Simulation time 1484503606 ps
CPU time 5.74 seconds
Started Jul 09 05:43:18 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 200444 kb
Host smart-33d67962-e02b-444a-8ef0-0f0efd1f7d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897874379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1897874379
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2651431419
Short name T398
Test name
Test status
Simulation time 106409704 ps
CPU time 1 seconds
Started Jul 09 05:43:18 PM PDT 24
Finished Jul 09 05:43:20 PM PDT 24
Peak memory 200184 kb
Host smart-abeaec5f-346a-46de-8699-9ca830c0146a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651431419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2651431419
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1691272214
Short name T61
Test name
Test status
Simulation time 248907870 ps
CPU time 1.42 seconds
Started Jul 09 05:43:14 PM PDT 24
Finished Jul 09 05:43:16 PM PDT 24
Peak memory 200304 kb
Host smart-df0252e9-23ff-439a-83ac-b8376bb1c8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691272214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1691272214
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.95746511
Short name T154
Test name
Test status
Simulation time 11284034181 ps
CPU time 40.06 seconds
Started Jul 09 05:43:13 PM PDT 24
Finished Jul 09 05:43:54 PM PDT 24
Peak memory 208588 kb
Host smart-1f07bfe9-ff44-466c-9055-f678668c8f9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95746511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.95746511
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1598693050
Short name T411
Test name
Test status
Simulation time 414651772 ps
CPU time 2.3 seconds
Started Jul 09 05:43:13 PM PDT 24
Finished Jul 09 05:43:16 PM PDT 24
Peak memory 208308 kb
Host smart-0f0ac4e3-1feb-4116-b262-9d9901935098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598693050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1598693050
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2071465536
Short name T502
Test name
Test status
Simulation time 80401601 ps
CPU time 0.86 seconds
Started Jul 09 05:43:11 PM PDT 24
Finished Jul 09 05:43:13 PM PDT 24
Peak memory 200152 kb
Host smart-86f8d7d7-5ddb-4149-af2a-880731fd12fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071465536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2071465536
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2722850171
Short name T296
Test name
Test status
Simulation time 69531712 ps
CPU time 0.77 seconds
Started Jul 09 05:43:23 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 199976 kb
Host smart-55d3e6df-2c61-4df6-a49e-45265218b23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722850171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2722850171
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.391683494
Short name T439
Test name
Test status
Simulation time 1891794632 ps
CPU time 7.3 seconds
Started Jul 09 05:43:17 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 217720 kb
Host smart-3452dc59-7946-4ef7-a5f1-55eb54a1e237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391683494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.391683494
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1015256639
Short name T491
Test name
Test status
Simulation time 244321998 ps
CPU time 1.08 seconds
Started Jul 09 05:43:16 PM PDT 24
Finished Jul 09 05:43:18 PM PDT 24
Peak memory 217508 kb
Host smart-3b34fda3-b094-4792-a9a7-4471478679b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015256639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1015256639
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.592302754
Short name T357
Test name
Test status
Simulation time 183157962 ps
CPU time 0.92 seconds
Started Jul 09 05:43:14 PM PDT 24
Finished Jul 09 05:43:16 PM PDT 24
Peak memory 200000 kb
Host smart-230b4c38-5f02-4c8d-821a-f6045ae79991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592302754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.592302754
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2311796606
Short name T460
Test name
Test status
Simulation time 1914248068 ps
CPU time 7.54 seconds
Started Jul 09 05:43:10 PM PDT 24
Finished Jul 09 05:43:18 PM PDT 24
Peak memory 200332 kb
Host smart-fd7867e9-5389-46c2-ab92-e6e38c0d73a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311796606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2311796606
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3699470878
Short name T417
Test name
Test status
Simulation time 107332222 ps
CPU time 0.99 seconds
Started Jul 09 05:43:26 PM PDT 24
Finished Jul 09 05:43:27 PM PDT 24
Peak memory 200148 kb
Host smart-e23bf02b-1c23-4eb3-8b5b-440bfb96f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699470878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3699470878
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1779828801
Short name T531
Test name
Test status
Simulation time 116150123 ps
CPU time 1.13 seconds
Started Jul 09 05:43:13 PM PDT 24
Finished Jul 09 05:43:15 PM PDT 24
Peak memory 200368 kb
Host smart-386dcc1e-151c-4920-8a5f-84ff0af32e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779828801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1779828801
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1326373226
Short name T378
Test name
Test status
Simulation time 3214355167 ps
CPU time 11.39 seconds
Started Jul 09 05:43:35 PM PDT 24
Finished Jul 09 05:43:49 PM PDT 24
Peak memory 200512 kb
Host smart-91b56467-7df4-4084-8c5b-62844375ad0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326373226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1326373226
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3199479247
Short name T234
Test name
Test status
Simulation time 275152892 ps
CPU time 1.94 seconds
Started Jul 09 05:43:14 PM PDT 24
Finished Jul 09 05:43:17 PM PDT 24
Peak memory 200124 kb
Host smart-a72536f9-e7f5-4fa1-bb36-48c3ab37da47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199479247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3199479247
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1593598927
Short name T303
Test name
Test status
Simulation time 216065750 ps
CPU time 1.36 seconds
Started Jul 09 05:43:17 PM PDT 24
Finished Jul 09 05:43:19 PM PDT 24
Peak memory 200176 kb
Host smart-76618e57-ddf5-4090-89d4-4efd411a908c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593598927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1593598927
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1021011708
Short name T287
Test name
Test status
Simulation time 66870442 ps
CPU time 0.74 seconds
Started Jul 09 05:43:19 PM PDT 24
Finished Jul 09 05:43:21 PM PDT 24
Peak memory 199984 kb
Host smart-af026ee5-7287-4861-af51-8221a1cc086d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021011708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1021011708
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.272495663
Short name T483
Test name
Test status
Simulation time 2145924467 ps
CPU time 8.59 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:47 PM PDT 24
Peak memory 217768 kb
Host smart-c418ea8e-55e9-463f-941a-36159205d1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272495663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.272495663
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2196277004
Short name T241
Test name
Test status
Simulation time 243705404 ps
CPU time 1.12 seconds
Started Jul 09 05:43:47 PM PDT 24
Finished Jul 09 05:43:49 PM PDT 24
Peak memory 217480 kb
Host smart-d659c199-8fba-4684-bd45-6be57ace0662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196277004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2196277004
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2533168895
Short name T340
Test name
Test status
Simulation time 187912442 ps
CPU time 0.86 seconds
Started Jul 09 05:43:17 PM PDT 24
Finished Jul 09 05:43:18 PM PDT 24
Peak memory 199980 kb
Host smart-903d8a11-1f5a-42f5-b009-349fef2e18bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533168895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2533168895
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.435311710
Short name T222
Test name
Test status
Simulation time 980159178 ps
CPU time 4.54 seconds
Started Jul 09 05:43:23 PM PDT 24
Finished Jul 09 05:43:29 PM PDT 24
Peak memory 200400 kb
Host smart-938f0041-95a8-46d4-951b-b0b63570dfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435311710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.435311710
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2775442399
Short name T132
Test name
Test status
Simulation time 179781525 ps
CPU time 1.24 seconds
Started Jul 09 05:43:11 PM PDT 24
Finished Jul 09 05:43:13 PM PDT 24
Peak memory 200180 kb
Host smart-8a068478-70fc-4b50-b1f0-3d6af995b215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775442399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2775442399
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3155951821
Short name T308
Test name
Test status
Simulation time 124696606 ps
CPU time 1.17 seconds
Started Jul 09 05:43:21 PM PDT 24
Finished Jul 09 05:43:23 PM PDT 24
Peak memory 200324 kb
Host smart-0f226de5-d4f3-4a6a-86cd-9526ea423b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155951821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3155951821
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.937557637
Short name T213
Test name
Test status
Simulation time 1041029465 ps
CPU time 4.51 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:37 PM PDT 24
Peak memory 200444 kb
Host smart-8ca0129e-50c0-47c1-b7a3-f8047d50b26b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937557637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.937557637
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2132587241
Short name T195
Test name
Test status
Simulation time 270569518 ps
CPU time 1.75 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:34 PM PDT 24
Peak memory 200176 kb
Host smart-7553a581-e5df-4da5-a1ce-4952adb3d05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132587241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2132587241
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1257921000
Short name T12
Test name
Test status
Simulation time 251452978 ps
CPU time 1.58 seconds
Started Jul 09 05:43:12 PM PDT 24
Finished Jul 09 05:43:14 PM PDT 24
Peak memory 200376 kb
Host smart-6c26afea-0bff-4430-a289-ce2829774db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257921000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1257921000
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2294154551
Short name T438
Test name
Test status
Simulation time 64773322 ps
CPU time 0.75 seconds
Started Jul 09 05:43:22 PM PDT 24
Finished Jul 09 05:43:23 PM PDT 24
Peak memory 199972 kb
Host smart-997895bf-8b69-420a-98ce-c61df6f4c291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294154551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2294154551
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1451306275
Short name T37
Test name
Test status
Simulation time 1225746902 ps
CPU time 5.48 seconds
Started Jul 09 05:43:23 PM PDT 24
Finished Jul 09 05:43:29 PM PDT 24
Peak memory 217676 kb
Host smart-8d456d19-0de6-4abf-b3fa-bd50c8625849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451306275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1451306275
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1355011763
Short name T322
Test name
Test status
Simulation time 244706777 ps
CPU time 1.14 seconds
Started Jul 09 05:43:28 PM PDT 24
Finished Jul 09 05:43:30 PM PDT 24
Peak memory 217680 kb
Host smart-e0b7d0ca-e7ab-4e45-a682-9b863f58756f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355011763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1355011763
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3473227176
Short name T18
Test name
Test status
Simulation time 113373439 ps
CPU time 0.78 seconds
Started Jul 09 05:43:23 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 199960 kb
Host smart-35a88443-0c3d-42c6-9e1b-bfb8e87b32b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473227176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3473227176
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.989433465
Short name T133
Test name
Test status
Simulation time 1253658662 ps
CPU time 4.83 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:46 PM PDT 24
Peak memory 200444 kb
Host smart-fa51fdb8-c494-430b-bf61-228b94ef970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989433465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.989433465
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2749881469
Short name T256
Test name
Test status
Simulation time 100401010 ps
CPU time 1 seconds
Started Jul 09 05:43:22 PM PDT 24
Finished Jul 09 05:43:24 PM PDT 24
Peak memory 200084 kb
Host smart-d24f37a5-9692-480c-94af-6dea06fd4390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749881469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2749881469
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3486599889
Short name T276
Test name
Test status
Simulation time 117993413 ps
CPU time 1.25 seconds
Started Jul 09 05:43:24 PM PDT 24
Finished Jul 09 05:43:26 PM PDT 24
Peak memory 200368 kb
Host smart-76d75a92-6245-4682-aacf-8cb8f00fcaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486599889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3486599889
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1842231447
Short name T82
Test name
Test status
Simulation time 2315668723 ps
CPU time 8.45 seconds
Started Jul 09 05:43:19 PM PDT 24
Finished Jul 09 05:43:28 PM PDT 24
Peak memory 208696 kb
Host smart-c28bfcdb-6b20-461f-a79b-38ed4a48cd16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842231447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1842231447
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.4039440756
Short name T209
Test name
Test status
Simulation time 284615928 ps
CPU time 2.06 seconds
Started Jul 09 05:43:15 PM PDT 24
Finished Jul 09 05:43:18 PM PDT 24
Peak memory 200080 kb
Host smart-edbe0e50-bcb4-4d2b-a3b5-c695df7412e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039440756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4039440756
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1043061773
Short name T46
Test name
Test status
Simulation time 198817045 ps
CPU time 1.27 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:35 PM PDT 24
Peak memory 200172 kb
Host smart-8ca9f5ca-98b4-490f-9f77-8e9a1df9f747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043061773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1043061773
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.29613453
Short name T244
Test name
Test status
Simulation time 67867234 ps
CPU time 0.75 seconds
Started Jul 09 05:43:30 PM PDT 24
Finished Jul 09 05:43:32 PM PDT 24
Peak memory 199936 kb
Host smart-266ee7a8-e631-4a05-b0bf-d5f2fea14967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29613453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.29613453
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1581434788
Short name T301
Test name
Test status
Simulation time 1234834445 ps
CPU time 5.31 seconds
Started Jul 09 05:43:27 PM PDT 24
Finished Jul 09 05:43:33 PM PDT 24
Peak memory 217812 kb
Host smart-0b82a82d-c709-450d-950a-c2d565056774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581434788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1581434788
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.456998385
Short name T153
Test name
Test status
Simulation time 243821067 ps
CPU time 1.1 seconds
Started Jul 09 05:43:23 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 217492 kb
Host smart-0303900e-6fad-468c-9342-3bc69ce7b4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456998385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.456998385
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2552660132
Short name T386
Test name
Test status
Simulation time 181657921 ps
CPU time 0.88 seconds
Started Jul 09 05:43:30 PM PDT 24
Finished Jul 09 05:43:32 PM PDT 24
Peak memory 199984 kb
Host smart-862a660f-0095-4643-986c-ddae036e8bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552660132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2552660132
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1490768284
Short name T116
Test name
Test status
Simulation time 1792212826 ps
CPU time 6.21 seconds
Started Jul 09 05:43:23 PM PDT 24
Finished Jul 09 05:43:31 PM PDT 24
Peak memory 200364 kb
Host smart-6c184f66-f0dc-4908-bf97-1f2bb5ffdd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490768284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1490768284
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3425922950
Short name T449
Test name
Test status
Simulation time 99695304 ps
CPU time 0.97 seconds
Started Jul 09 05:43:22 PM PDT 24
Finished Jul 09 05:43:23 PM PDT 24
Peak memory 200152 kb
Host smart-ac2c74f7-1b95-476c-856f-df5469f047f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425922950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3425922950
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1090685275
Short name T374
Test name
Test status
Simulation time 202778638 ps
CPU time 1.37 seconds
Started Jul 09 05:43:18 PM PDT 24
Finished Jul 09 05:43:21 PM PDT 24
Peak memory 200364 kb
Host smart-730a96fe-45e7-40ed-a1de-bf475ba1c5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090685275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1090685275
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2342895417
Short name T508
Test name
Test status
Simulation time 7382040640 ps
CPU time 27.21 seconds
Started Jul 09 05:43:28 PM PDT 24
Finished Jul 09 05:43:56 PM PDT 24
Peak memory 208676 kb
Host smart-6686470d-a25d-4129-8b0c-512454c4cd46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342895417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2342895417
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1514570762
Short name T494
Test name
Test status
Simulation time 144613297 ps
CPU time 1.84 seconds
Started Jul 09 05:43:35 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 200184 kb
Host smart-94197194-ab02-4be3-a5e2-b8829e9efa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514570762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1514570762
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1254909932
Short name T4
Test name
Test status
Simulation time 129032360 ps
CPU time 1.06 seconds
Started Jul 09 05:43:24 PM PDT 24
Finished Jul 09 05:43:26 PM PDT 24
Peak memory 200188 kb
Host smart-b8e5ed16-1821-4926-862f-f9797b9fbc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254909932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1254909932
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.912594930
Short name T379
Test name
Test status
Simulation time 73441927 ps
CPU time 0.85 seconds
Started Jul 09 05:43:25 PM PDT 24
Finished Jul 09 05:43:27 PM PDT 24
Peak memory 199952 kb
Host smart-325a39d6-f1b3-41b5-a54e-372ef8a934a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912594930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.912594930
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.670264663
Short name T496
Test name
Test status
Simulation time 1889495046 ps
CPU time 6.97 seconds
Started Jul 09 05:43:20 PM PDT 24
Finished Jul 09 05:43:28 PM PDT 24
Peak memory 216928 kb
Host smart-80bbcc34-8907-4abe-b9fe-1735f5c37426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670264663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.670264663
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.580289893
Short name T377
Test name
Test status
Simulation time 245109909 ps
CPU time 1.07 seconds
Started Jul 09 05:43:23 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 217452 kb
Host smart-a59f65c5-4075-4ef2-895f-cae163e17a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580289893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.580289893
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.19904681
Short name T510
Test name
Test status
Simulation time 123123056 ps
CPU time 0.84 seconds
Started Jul 09 05:43:23 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 199920 kb
Host smart-ab772b16-7f63-4342-835a-1bef19a8fc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19904681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.19904681
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1183613940
Short name T196
Test name
Test status
Simulation time 1414756687 ps
CPU time 5.27 seconds
Started Jul 09 05:43:30 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 200436 kb
Host smart-e9d6b6bf-474c-4b03-ad5e-1f66fc6f8e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183613940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1183613940
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2781565832
Short name T245
Test name
Test status
Simulation time 171158225 ps
CPU time 1.19 seconds
Started Jul 09 05:43:27 PM PDT 24
Finished Jul 09 05:43:29 PM PDT 24
Peak memory 200132 kb
Host smart-ae7c25b5-0b88-45f1-941a-d761e41c8477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781565832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2781565832
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3159339701
Short name T192
Test name
Test status
Simulation time 119240082 ps
CPU time 1.21 seconds
Started Jul 09 05:43:25 PM PDT 24
Finished Jul 09 05:43:27 PM PDT 24
Peak memory 200364 kb
Host smart-702be315-3ae6-42b8-9d1e-a7643e3de770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159339701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3159339701
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2104156234
Short name T395
Test name
Test status
Simulation time 8409185904 ps
CPU time 28.77 seconds
Started Jul 09 05:43:21 PM PDT 24
Finished Jul 09 05:43:50 PM PDT 24
Peak memory 200508 kb
Host smart-c64c564f-37e7-468d-994d-ddcf831f01bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104156234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2104156234
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2050642028
Short name T247
Test name
Test status
Simulation time 142198918 ps
CPU time 1.81 seconds
Started Jul 09 05:43:21 PM PDT 24
Finished Jul 09 05:43:23 PM PDT 24
Peak memory 200080 kb
Host smart-b1942953-c8ea-4aa9-bf8c-ad4758bba122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050642028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2050642028
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.116241776
Short name T147
Test name
Test status
Simulation time 208197444 ps
CPU time 1.29 seconds
Started Jul 09 05:43:21 PM PDT 24
Finished Jul 09 05:43:23 PM PDT 24
Peak memory 200152 kb
Host smart-ec6c0f97-8823-41df-8622-bcf7a4f9f4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116241776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.116241776
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3905258
Short name T155
Test name
Test status
Simulation time 56331821 ps
CPU time 0.74 seconds
Started Jul 09 05:43:22 PM PDT 24
Finished Jul 09 05:43:23 PM PDT 24
Peak memory 199936 kb
Host smart-2b091193-8bc8-43a2-bbc5-76315c898e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3905258
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3037647040
Short name T364
Test name
Test status
Simulation time 1219248157 ps
CPU time 5.36 seconds
Started Jul 09 05:43:27 PM PDT 24
Finished Jul 09 05:43:33 PM PDT 24
Peak memory 217352 kb
Host smart-35544d10-a905-4829-857c-dc2737bc2c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037647040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3037647040
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.984763742
Short name T527
Test name
Test status
Simulation time 244574511 ps
CPU time 1.06 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:34 PM PDT 24
Peak memory 217520 kb
Host smart-8b4332c1-e6b3-43d0-9143-5b927c7a4ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984763742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.984763742
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2899327938
Short name T183
Test name
Test status
Simulation time 207959081 ps
CPU time 1.05 seconds
Started Jul 09 05:43:26 PM PDT 24
Finished Jul 09 05:43:28 PM PDT 24
Peak memory 199940 kb
Host smart-c80d547b-c2ed-4d2c-8fb4-dcb890d88c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899327938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2899327938
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3374956445
Short name T237
Test name
Test status
Simulation time 1762288929 ps
CPU time 6.38 seconds
Started Jul 09 05:43:26 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 200364 kb
Host smart-ac41bdca-b207-4292-97f7-4b85ac1524ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374956445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3374956445
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.4282511427
Short name T333
Test name
Test status
Simulation time 153113184 ps
CPU time 1.12 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:41 PM PDT 24
Peak memory 200188 kb
Host smart-e7f4e3fc-b0e4-49e3-b227-f9a9170a9e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282511427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.4282511427
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2530898347
Short name T436
Test name
Test status
Simulation time 113774599 ps
CPU time 1.2 seconds
Started Jul 09 05:43:29 PM PDT 24
Finished Jul 09 05:43:31 PM PDT 24
Peak memory 200332 kb
Host smart-3da9bc76-68a3-49b5-9612-2c1ee154a3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530898347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2530898347
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1622984404
Short name T239
Test name
Test status
Simulation time 2011254362 ps
CPU time 8.38 seconds
Started Jul 09 05:43:25 PM PDT 24
Finished Jul 09 05:43:34 PM PDT 24
Peak memory 200368 kb
Host smart-71ea02b6-d6b9-469a-869b-ccf967415065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622984404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1622984404
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3672713906
Short name T8
Test name
Test status
Simulation time 114319407 ps
CPU time 1.45 seconds
Started Jul 09 05:43:29 PM PDT 24
Finished Jul 09 05:43:31 PM PDT 24
Peak memory 200184 kb
Host smart-6713fc53-51b5-47c9-9bfb-84caf49fc75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672713906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3672713906
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3463265480
Short name T313
Test name
Test status
Simulation time 93237218 ps
CPU time 0.84 seconds
Started Jul 09 05:43:22 PM PDT 24
Finished Jul 09 05:43:23 PM PDT 24
Peak memory 200184 kb
Host smart-e4a53e65-c378-4f1c-a19b-fbbecf23f55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463265480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3463265480
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2369976631
Short name T230
Test name
Test status
Simulation time 60279428 ps
CPU time 0.75 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:34 PM PDT 24
Peak memory 199944 kb
Host smart-d2607da8-857a-4353-b81e-bd17c1ab97ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369976631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2369976631
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2375748721
Short name T519
Test name
Test status
Simulation time 1224369210 ps
CPU time 5.71 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 217804 kb
Host smart-447d6a35-322e-494c-a0d0-dc9c215b68a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375748721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2375748721
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.149018972
Short name T514
Test name
Test status
Simulation time 244816674 ps
CPU time 1.06 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 217552 kb
Host smart-952ce18c-e1f3-48cf-aba5-f7f109a5e1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149018972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.149018972
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2819741658
Short name T191
Test name
Test status
Simulation time 102159137 ps
CPU time 0.82 seconds
Started Jul 09 05:43:22 PM PDT 24
Finished Jul 09 05:43:24 PM PDT 24
Peak memory 199980 kb
Host smart-4ba3d688-e1ba-47b4-b4ca-61e231e39b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819741658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2819741658
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.579237465
Short name T119
Test name
Test status
Simulation time 1595331682 ps
CPU time 6.76 seconds
Started Jul 09 05:43:23 PM PDT 24
Finished Jul 09 05:43:31 PM PDT 24
Peak memory 200380 kb
Host smart-09fe7b9a-2c51-43b9-9fa7-49b96917d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579237465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.579237465
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2574597584
Short name T419
Test name
Test status
Simulation time 182997782 ps
CPU time 1.16 seconds
Started Jul 09 05:43:23 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 200148 kb
Host smart-1090faa4-f459-4d42-9c11-189f262b3158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574597584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2574597584
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.589917548
Short name T507
Test name
Test status
Simulation time 120040078 ps
CPU time 1.19 seconds
Started Jul 09 05:43:25 PM PDT 24
Finished Jul 09 05:43:27 PM PDT 24
Peak memory 200388 kb
Host smart-466c5d6a-c55b-4568-84bb-e1e3b3f24a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589917548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.589917548
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3988092044
Short name T329
Test name
Test status
Simulation time 248326118 ps
CPU time 1.71 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:35 PM PDT 24
Peak memory 200380 kb
Host smart-8b24a730-be91-497b-a3f3-d0c7e2b4b4a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988092044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3988092044
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2188907220
Short name T504
Test name
Test status
Simulation time 125233856 ps
CPU time 1.47 seconds
Started Jul 09 05:43:30 PM PDT 24
Finished Jul 09 05:43:32 PM PDT 24
Peak memory 200156 kb
Host smart-9c8b6ba7-f0a8-47c2-a5b2-c65cbf47db24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188907220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2188907220
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2500304863
Short name T424
Test name
Test status
Simulation time 268624231 ps
CPU time 1.43 seconds
Started Jul 09 05:43:24 PM PDT 24
Finished Jul 09 05:43:27 PM PDT 24
Peak memory 200340 kb
Host smart-e1ae8cba-c8ca-4e9c-b6d8-bf5bd111f4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500304863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2500304863
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1721368218
Short name T321
Test name
Test status
Simulation time 82942839 ps
CPU time 0.86 seconds
Started Jul 09 05:43:24 PM PDT 24
Finished Jul 09 05:43:26 PM PDT 24
Peak memory 199976 kb
Host smart-70280aaa-a09e-41d6-8ddd-cd25d248fb46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721368218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1721368218
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3345053352
Short name T50
Test name
Test status
Simulation time 2357376539 ps
CPU time 8.08 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 217876 kb
Host smart-a4827ca1-120a-4eb7-8996-a7874865d66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345053352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3345053352
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3214263038
Short name T310
Test name
Test status
Simulation time 245361438 ps
CPU time 1.05 seconds
Started Jul 09 05:43:21 PM PDT 24
Finished Jul 09 05:43:23 PM PDT 24
Peak memory 217488 kb
Host smart-27bc25f1-72e6-45a4-a34c-7b2c0fb971cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214263038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3214263038
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1423244970
Short name T305
Test name
Test status
Simulation time 84370523 ps
CPU time 0.75 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:32 PM PDT 24
Peak memory 199944 kb
Host smart-59161402-0e7e-4d1b-8640-b746595da67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423244970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1423244970
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.476643540
Short name T284
Test name
Test status
Simulation time 2010704118 ps
CPU time 7.77 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:50 PM PDT 24
Peak memory 200380 kb
Host smart-f30a6820-582f-415a-b9ca-cb5fea425647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476643540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.476643540
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2803829867
Short name T128
Test name
Test status
Simulation time 170483173 ps
CPU time 1.23 seconds
Started Jul 09 05:43:25 PM PDT 24
Finished Jul 09 05:43:27 PM PDT 24
Peak memory 200080 kb
Host smart-3a442f31-ba2d-49f0-9a65-0a29ca0d3625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803829867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2803829867
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3478006273
Short name T204
Test name
Test status
Simulation time 192362602 ps
CPU time 1.3 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 200268 kb
Host smart-6cfd82b5-96fc-4682-9903-91889cddd235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478006273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3478006273
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.258722091
Short name T403
Test name
Test status
Simulation time 7362753094 ps
CPU time 28.77 seconds
Started Jul 09 05:43:26 PM PDT 24
Finished Jul 09 05:43:55 PM PDT 24
Peak memory 200432 kb
Host smart-14cd90f7-9e20-43e2-a55f-a559c87908a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258722091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.258722091
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1427158560
Short name T291
Test name
Test status
Simulation time 430242757 ps
CPU time 2.42 seconds
Started Jul 09 05:43:35 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 200200 kb
Host smart-1211723a-7f6e-40cb-9bde-081ead748d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427158560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1427158560
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2930494829
Short name T324
Test name
Test status
Simulation time 117954198 ps
CPU time 0.93 seconds
Started Jul 09 05:43:30 PM PDT 24
Finished Jul 09 05:43:32 PM PDT 24
Peak memory 200136 kb
Host smart-defaa605-3a7e-48c6-a5b0-31af6c5f07e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930494829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2930494829
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1209402453
Short name T206
Test name
Test status
Simulation time 66564479 ps
CPU time 0.8 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:36 PM PDT 24
Peak memory 199880 kb
Host smart-32d025bd-7aa8-4476-ab96-2da523001bdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209402453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1209402453
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4273064980
Short name T536
Test name
Test status
Simulation time 1227952979 ps
CPU time 5.85 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:42 PM PDT 24
Peak memory 217544 kb
Host smart-5befb98e-d58a-43ab-a4d6-eb2f094ccd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273064980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4273064980
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3465793249
Short name T203
Test name
Test status
Simulation time 244657945 ps
CPU time 1.16 seconds
Started Jul 09 05:42:38 PM PDT 24
Finished Jul 09 05:42:39 PM PDT 24
Peak memory 217460 kb
Host smart-ffd23593-797a-49c2-81e1-da441f985a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465793249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3465793249
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.637152432
Short name T404
Test name
Test status
Simulation time 173703322 ps
CPU time 0.87 seconds
Started Jul 09 05:42:35 PM PDT 24
Finished Jul 09 05:42:37 PM PDT 24
Peak memory 199872 kb
Host smart-34cb75e4-3ce2-4814-b60c-84416b70a9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637152432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.637152432
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1969121119
Short name T312
Test name
Test status
Simulation time 1879554531 ps
CPU time 6.36 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:42 PM PDT 24
Peak memory 200432 kb
Host smart-32524bfd-99a1-43aa-96cf-9232939f56fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969121119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1969121119
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3756130132
Short name T71
Test name
Test status
Simulation time 18181340454 ps
CPU time 26.94 seconds
Started Jul 09 05:42:35 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 218216 kb
Host smart-de6d4a50-68ef-4e08-8707-c09c7d68d308
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756130132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3756130132
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.72735135
Short name T462
Test name
Test status
Simulation time 102203663 ps
CPU time 1.02 seconds
Started Jul 09 05:42:36 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 200116 kb
Host smart-2d685254-7133-4a3c-93d5-258c84707251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72735135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.72735135
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2585885086
Short name T331
Test name
Test status
Simulation time 116942849 ps
CPU time 1.18 seconds
Started Jul 09 05:42:35 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 200400 kb
Host smart-386afa48-03ba-4405-85c0-9cb3c311f315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585885086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2585885086
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1476493036
Short name T187
Test name
Test status
Simulation time 5901946059 ps
CPU time 26.95 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 200452 kb
Host smart-f249dda4-ea38-402c-b330-e432aa3a1614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476493036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1476493036
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.458521754
Short name T277
Test name
Test status
Simulation time 389244045 ps
CPU time 2.62 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 200188 kb
Host smart-d6e073bb-a87a-406f-acba-132ebdf0777b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458521754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.458521754
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.707028357
Short name T330
Test name
Test status
Simulation time 102539503 ps
CPU time 0.95 seconds
Started Jul 09 05:42:37 PM PDT 24
Finished Jul 09 05:42:39 PM PDT 24
Peak memory 200164 kb
Host smart-14abcba9-51ba-4978-9450-5dc259041983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707028357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.707028357
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.4042313222
Short name T127
Test name
Test status
Simulation time 74540747 ps
CPU time 0.86 seconds
Started Jul 09 05:43:23 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 199956 kb
Host smart-fd0cd980-5d23-4904-a93d-86d6f6c884e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042313222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.4042313222
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3682479433
Short name T248
Test name
Test status
Simulation time 244818309 ps
CPU time 1.03 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:35 PM PDT 24
Peak memory 217568 kb
Host smart-e61d008f-dc31-49fa-ac35-c21a47f7c585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682479433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3682479433
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2731827198
Short name T262
Test name
Test status
Simulation time 201078710 ps
CPU time 0.89 seconds
Started Jul 09 05:43:25 PM PDT 24
Finished Jul 09 05:43:27 PM PDT 24
Peak memory 199940 kb
Host smart-205a1fbb-ec33-40bb-855a-1c1819a0f84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731827198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2731827198
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.459599022
Short name T96
Test name
Test status
Simulation time 1922381674 ps
CPU time 7.14 seconds
Started Jul 09 05:43:35 PM PDT 24
Finished Jul 09 05:43:44 PM PDT 24
Peak memory 200384 kb
Host smart-2aa5c97d-065c-4de8-925c-6c74beee2f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459599022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.459599022
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1854865439
Short name T524
Test name
Test status
Simulation time 154374741 ps
CPU time 1.09 seconds
Started Jul 09 05:43:26 PM PDT 24
Finished Jul 09 05:43:28 PM PDT 24
Peak memory 200156 kb
Host smart-96fb7223-e1d9-4405-83f5-857bbbf12401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854865439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1854865439
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3876271552
Short name T423
Test name
Test status
Simulation time 126995693 ps
CPU time 1.21 seconds
Started Jul 09 05:43:27 PM PDT 24
Finished Jul 09 05:43:29 PM PDT 24
Peak memory 200268 kb
Host smart-ef0a8401-cc97-4d49-a203-012d767b2cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876271552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3876271552
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.961296350
Short name T81
Test name
Test status
Simulation time 5621027719 ps
CPU time 25.46 seconds
Started Jul 09 05:43:39 PM PDT 24
Finished Jul 09 05:44:07 PM PDT 24
Peak memory 208728 kb
Host smart-5b473473-9a40-44d0-abc0-40fd21266bbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961296350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.961296350
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1260595036
Short name T138
Test name
Test status
Simulation time 137691477 ps
CPU time 0.98 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:41 PM PDT 24
Peak memory 200160 kb
Host smart-1eac6cb9-7625-47be-9179-e89649150c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260595036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1260595036
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3429312027
Short name T480
Test name
Test status
Simulation time 76707641 ps
CPU time 0.79 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 199968 kb
Host smart-5751050a-0265-4447-806c-e03d3f2310bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429312027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3429312027
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.915970645
Short name T343
Test name
Test status
Simulation time 1216954953 ps
CPU time 5.54 seconds
Started Jul 09 05:43:59 PM PDT 24
Finished Jul 09 05:44:06 PM PDT 24
Peak memory 221716 kb
Host smart-c084d359-28a4-4a38-aa23-d5ad1c11809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915970645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.915970645
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3094486181
Short name T134
Test name
Test status
Simulation time 244066365 ps
CPU time 1.03 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 217504 kb
Host smart-1c2d6eeb-bbbd-4585-8331-68a58e69a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094486181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3094486181
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3770282119
Short name T257
Test name
Test status
Simulation time 90325429 ps
CPU time 0.75 seconds
Started Jul 09 05:43:34 PM PDT 24
Finished Jul 09 05:43:37 PM PDT 24
Peak memory 199992 kb
Host smart-186ac7e1-e961-4551-8686-558867175a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770282119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3770282119
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.653868007
Short name T332
Test name
Test status
Simulation time 937837407 ps
CPU time 4.43 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:45 PM PDT 24
Peak memory 200424 kb
Host smart-a582d4b6-4270-4c01-824a-229b6d121566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653868007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.653868007
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3298095104
Short name T349
Test name
Test status
Simulation time 106784592 ps
CPU time 0.95 seconds
Started Jul 09 05:43:35 PM PDT 24
Finished Jul 09 05:43:38 PM PDT 24
Peak memory 200124 kb
Host smart-f66272ee-58f6-4268-9e22-14f7df72785f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298095104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3298095104
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2765118044
Short name T306
Test name
Test status
Simulation time 120276585 ps
CPU time 1.19 seconds
Started Jul 09 05:43:39 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 200336 kb
Host smart-f6fa5904-57cc-446e-b4a4-9604f17c54a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765118044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2765118044
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3126441180
Short name T288
Test name
Test status
Simulation time 509451462 ps
CPU time 2.69 seconds
Started Jul 09 05:43:22 PM PDT 24
Finished Jul 09 05:43:26 PM PDT 24
Peak memory 200172 kb
Host smart-2fe7a702-2a42-4d5d-b833-01dcae6f936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126441180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3126441180
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.4113843006
Short name T472
Test name
Test status
Simulation time 149816674 ps
CPU time 1.15 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:34 PM PDT 24
Peak memory 200132 kb
Host smart-5cb34352-3e62-46ab-b34d-cb86d5ab228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113843006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.4113843006
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.714975255
Short name T164
Test name
Test status
Simulation time 79033015 ps
CPU time 0.8 seconds
Started Jul 09 05:43:22 PM PDT 24
Finished Jul 09 05:43:24 PM PDT 24
Peak memory 199808 kb
Host smart-3c045ccb-3204-470c-966d-42e9fef32d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714975255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.714975255
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1846284969
Short name T495
Test name
Test status
Simulation time 1882382744 ps
CPU time 7.16 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 217772 kb
Host smart-2c7194b6-72d8-44eb-8ce2-afba65df5e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846284969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1846284969
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1118556259
Short name T477
Test name
Test status
Simulation time 243958723 ps
CPU time 1.07 seconds
Started Jul 09 05:43:35 PM PDT 24
Finished Jul 09 05:43:38 PM PDT 24
Peak memory 217584 kb
Host smart-acbe30d2-222e-4f33-aa14-631b5a194765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118556259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1118556259
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2543338632
Short name T25
Test name
Test status
Simulation time 187528099 ps
CPU time 1.04 seconds
Started Jul 09 05:43:22 PM PDT 24
Finished Jul 09 05:43:24 PM PDT 24
Peak memory 199980 kb
Host smart-6375f1fe-1b88-4626-b69b-5b86d546ae2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543338632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2543338632
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1987064854
Short name T73
Test name
Test status
Simulation time 1068756284 ps
CPU time 4.91 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:45 PM PDT 24
Peak memory 200476 kb
Host smart-bc371b2a-d12e-46b1-9090-c7bc579c86be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987064854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1987064854
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3545328772
Short name T492
Test name
Test status
Simulation time 143192221 ps
CPU time 1.11 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:35 PM PDT 24
Peak memory 200144 kb
Host smart-2d34d674-29dd-4a2a-8622-0e2002ee1e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545328772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3545328772
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1336983817
Short name T166
Test name
Test status
Simulation time 124825920 ps
CPU time 1.18 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:37 PM PDT 24
Peak memory 200392 kb
Host smart-67d53885-9bf7-4a67-87a3-a936b7876a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336983817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1336983817
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1290692197
Short name T317
Test name
Test status
Simulation time 234106496 ps
CPU time 1.31 seconds
Started Jul 09 05:43:55 PM PDT 24
Finished Jul 09 05:43:57 PM PDT 24
Peak memory 200052 kb
Host smart-a844cc4d-f839-4fea-91d5-0e107c3cfc1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290692197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1290692197
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1431230913
Short name T121
Test name
Test status
Simulation time 377784733 ps
CPU time 2.21 seconds
Started Jul 09 05:43:24 PM PDT 24
Finished Jul 09 05:43:28 PM PDT 24
Peak memory 200008 kb
Host smart-aaba1543-6e01-4aaa-9d0a-e9a0c0274d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431230913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1431230913
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1523983367
Short name T468
Test name
Test status
Simulation time 147824893 ps
CPU time 1.17 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:41 PM PDT 24
Peak memory 200368 kb
Host smart-21c0e9ff-24a7-4daa-ab03-05de0095eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523983367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1523983367
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2434936751
Short name T538
Test name
Test status
Simulation time 66820754 ps
CPU time 0.75 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:35 PM PDT 24
Peak memory 199952 kb
Host smart-044cf61c-02bc-4198-848b-d41652d35cbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434936751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2434936751
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.407165753
Short name T29
Test name
Test status
Simulation time 2348011034 ps
CPU time 8.63 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:41 PM PDT 24
Peak memory 217924 kb
Host smart-747a7b12-86f8-483d-9635-cd86a5a7deda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407165753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.407165753
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3987835968
Short name T391
Test name
Test status
Simulation time 244944017 ps
CPU time 1.03 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:33 PM PDT 24
Peak memory 217504 kb
Host smart-663e45b7-38d0-4edf-ad64-d1c46a5dd41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987835968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3987835968
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1993750859
Short name T17
Test name
Test status
Simulation time 158789635 ps
CPU time 0.9 seconds
Started Jul 09 05:43:29 PM PDT 24
Finished Jul 09 05:43:31 PM PDT 24
Peak memory 199832 kb
Host smart-eb5d3d03-b2da-45ae-8cea-0a68e8f06694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993750859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1993750859
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2331781201
Short name T27
Test name
Test status
Simulation time 1571718597 ps
CPU time 5.72 seconds
Started Jul 09 05:43:42 PM PDT 24
Finished Jul 09 05:43:49 PM PDT 24
Peak memory 200320 kb
Host smart-c954db05-cc46-4f4b-aad5-d8eb1c5ef2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331781201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2331781201
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1743211014
Short name T232
Test name
Test status
Simulation time 181039098 ps
CPU time 1.2 seconds
Started Jul 09 05:43:24 PM PDT 24
Finished Jul 09 05:43:27 PM PDT 24
Peak memory 200168 kb
Host smart-78bdb201-21b8-4cd9-b5b4-e026bb0c0ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743211014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1743211014
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.889149323
Short name T456
Test name
Test status
Simulation time 196408836 ps
CPU time 1.31 seconds
Started Jul 09 05:43:25 PM PDT 24
Finished Jul 09 05:43:27 PM PDT 24
Peak memory 200356 kb
Host smart-4cc89442-4a6e-4679-bfaa-00691e8383a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889149323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.889149323
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.170326702
Short name T446
Test name
Test status
Simulation time 8631215472 ps
CPU time 29.65 seconds
Started Jul 09 05:43:27 PM PDT 24
Finished Jul 09 05:43:57 PM PDT 24
Peak memory 208576 kb
Host smart-841d98ff-c99a-4730-b829-539c21c4623b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170326702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.170326702
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3407862941
Short name T383
Test name
Test status
Simulation time 324832057 ps
CPU time 1.94 seconds
Started Jul 09 05:43:45 PM PDT 24
Finished Jul 09 05:43:53 PM PDT 24
Peak memory 200152 kb
Host smart-f46b7397-1228-4319-8fdd-4df6cfc6ea06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407862941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3407862941
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.978613440
Short name T240
Test name
Test status
Simulation time 67032761 ps
CPU time 0.75 seconds
Started Jul 09 05:43:24 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 200160 kb
Host smart-ac8dbd47-eb36-4d98-a95c-85b3739cc64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978613440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.978613440
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1910770441
Short name T422
Test name
Test status
Simulation time 79164757 ps
CPU time 0.77 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:34 PM PDT 24
Peak memory 199812 kb
Host smart-05790b6d-d221-4f5c-913a-ff5595238f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910770441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1910770441
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3378670952
Short name T434
Test name
Test status
Simulation time 2369391059 ps
CPU time 7.96 seconds
Started Jul 09 05:44:00 PM PDT 24
Finished Jul 09 05:44:09 PM PDT 24
Peak memory 221884 kb
Host smart-78449b54-a19f-4307-94ec-5cb425ea44a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378670952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3378670952
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1470644960
Short name T211
Test name
Test status
Simulation time 243616419 ps
CPU time 1.06 seconds
Started Jul 09 05:43:30 PM PDT 24
Finished Jul 09 05:43:31 PM PDT 24
Peak memory 217448 kb
Host smart-0d47ea99-137b-44bf-aa77-476c5ef5ceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470644960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1470644960
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.737608519
Short name T20
Test name
Test status
Simulation time 187074764 ps
CPU time 0.93 seconds
Started Jul 09 05:43:27 PM PDT 24
Finished Jul 09 05:43:29 PM PDT 24
Peak memory 199972 kb
Host smart-4dfd2db1-a657-4c55-8673-40caf623e986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737608519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.737608519
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.703171197
Short name T418
Test name
Test status
Simulation time 808996142 ps
CPU time 4.07 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:44 PM PDT 24
Peak memory 200488 kb
Host smart-cf5994bf-ee33-423c-8487-15afb0be0608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703171197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.703171197
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1485189639
Short name T139
Test name
Test status
Simulation time 142523042 ps
CPU time 1.09 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 200360 kb
Host smart-5fd09527-4f71-4459-9977-e21f08479e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485189639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1485189639
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3678047583
Short name T484
Test name
Test status
Simulation time 116067394 ps
CPU time 1.27 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 200300 kb
Host smart-28bb8076-0d7e-4a4b-96ff-3497d12e63bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678047583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3678047583
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3845527569
Short name T295
Test name
Test status
Simulation time 14683365988 ps
CPU time 51.36 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:44:32 PM PDT 24
Peak memory 216268 kb
Host smart-a3058b66-7811-461b-9704-292501606615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845527569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3845527569
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1155557132
Short name T537
Test name
Test status
Simulation time 254245896 ps
CPU time 1.68 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 200132 kb
Host smart-3414e81a-9109-4108-b162-b44d7549168d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155557132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1155557132
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2459494058
Short name T174
Test name
Test status
Simulation time 55410818 ps
CPU time 0.76 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 200116 kb
Host smart-ee3ca4da-9ef6-459f-8d77-a9e2d8815948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459494058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2459494058
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3452212839
Short name T406
Test name
Test status
Simulation time 76444534 ps
CPU time 0.77 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 199976 kb
Host smart-2d9e6a14-d1ef-4eb7-a9f6-6db0e258b724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452212839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3452212839
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.4025657089
Short name T269
Test name
Test status
Simulation time 1884327604 ps
CPU time 7.5 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:48 PM PDT 24
Peak memory 229900 kb
Host smart-eed30f60-40af-45c9-ad26-3c1022957717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025657089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.4025657089
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1016847925
Short name T251
Test name
Test status
Simulation time 244609774 ps
CPU time 1.15 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 217564 kb
Host smart-2a91d302-3349-4e22-a083-8e4ddb90474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016847925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1016847925
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2684956665
Short name T336
Test name
Test status
Simulation time 80571011 ps
CPU time 0.74 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 199756 kb
Host smart-30b0eb81-fdab-4882-bd07-2e256a587f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684956665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2684956665
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.379974757
Short name T219
Test name
Test status
Simulation time 881834433 ps
CPU time 4.96 seconds
Started Jul 09 05:43:35 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 200424 kb
Host smart-8a19f570-6001-481c-81a5-29223f98d471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379974757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.379974757
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2253593206
Short name T457
Test name
Test status
Simulation time 186083424 ps
CPU time 1.23 seconds
Started Jul 09 05:43:26 PM PDT 24
Finished Jul 09 05:43:28 PM PDT 24
Peak memory 200084 kb
Host smart-e4f3e68f-d3ca-4168-a225-d8694f962840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253593206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2253593206
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.294813191
Short name T259
Test name
Test status
Simulation time 125360450 ps
CPU time 1.2 seconds
Started Jul 09 05:43:39 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 200404 kb
Host smart-cdc4107f-ae2d-466c-957b-c86cebd4fb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294813191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.294813191
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1830665343
Short name T315
Test name
Test status
Simulation time 2607225318 ps
CPU time 11.06 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 208660 kb
Host smart-79d4452f-7c8c-4f2b-9b7d-25346d6c97d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830665343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1830665343
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2031934061
Short name T455
Test name
Test status
Simulation time 149196975 ps
CPU time 1.86 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:41 PM PDT 24
Peak memory 200064 kb
Host smart-5f901c49-7ce8-46a7-a56a-d974453ca8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031934061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2031934061
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1735943832
Short name T236
Test name
Test status
Simulation time 113193352 ps
CPU time 0.9 seconds
Started Jul 09 05:43:39 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 200132 kb
Host smart-216b33f1-4d7d-475a-bf1c-1f06eba03580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735943832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1735943832
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3992461849
Short name T124
Test name
Test status
Simulation time 53275832 ps
CPU time 0.75 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:33 PM PDT 24
Peak memory 199976 kb
Host smart-cd712807-839c-49c4-8db3-04fdc4815a92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992461849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3992461849
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1473718756
Short name T41
Test name
Test status
Simulation time 1885347007 ps
CPU time 7.2 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:41 PM PDT 24
Peak memory 217744 kb
Host smart-337b79f3-f3ed-4df5-bee7-34e55851f1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473718756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1473718756
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3638730504
Short name T362
Test name
Test status
Simulation time 244525342 ps
CPU time 1.21 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 217508 kb
Host smart-d7f171d2-c38e-4842-b15b-40a13d2d0a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638730504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3638730504
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3587381207
Short name T286
Test name
Test status
Simulation time 132700020 ps
CPU time 0.78 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:33 PM PDT 24
Peak memory 199960 kb
Host smart-6bde5cda-d3d4-465d-b95a-cf37ce4056ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587381207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3587381207
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3667396088
Short name T413
Test name
Test status
Simulation time 794161019 ps
CPU time 4.24 seconds
Started Jul 09 05:43:34 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 200420 kb
Host smart-7f57d0a5-e94c-48ff-8a40-2be7a3559b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667396088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3667396088
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.443665051
Short name T175
Test name
Test status
Simulation time 170242352 ps
CPU time 1.2 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 200180 kb
Host smart-e2703b58-4773-423a-b58d-6dc21c491f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443665051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.443665051
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3499248330
Short name T534
Test name
Test status
Simulation time 203733043 ps
CPU time 1.36 seconds
Started Jul 09 05:43:34 PM PDT 24
Finished Jul 09 05:43:38 PM PDT 24
Peak memory 200324 kb
Host smart-97d5c856-a5ce-4067-a1b7-37fa785e3869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499248330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3499248330
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2332282338
Short name T221
Test name
Test status
Simulation time 10544026990 ps
CPU time 40.66 seconds
Started Jul 09 05:43:40 PM PDT 24
Finished Jul 09 05:44:23 PM PDT 24
Peak memory 216168 kb
Host smart-b20f6a97-a974-4dde-8a19-42d2e93e4ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332282338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2332282338
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.48995549
Short name T309
Test name
Test status
Simulation time 376490420 ps
CPU time 2.24 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:44 PM PDT 24
Peak memory 208380 kb
Host smart-18609edb-82a8-442d-bb4c-31b5a51b459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48995549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.48995549
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1572798087
Short name T14
Test name
Test status
Simulation time 139359216 ps
CPU time 1.16 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:32 PM PDT 24
Peak memory 200192 kb
Host smart-2ecb9ab1-dc21-4f3b-97a2-23586fe4d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572798087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1572798087
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1200892657
Short name T489
Test name
Test status
Simulation time 69576404 ps
CPU time 0.76 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:35 PM PDT 24
Peak memory 199932 kb
Host smart-a9baca92-b6ef-4848-b9fc-6e0e6a3534b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200892657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1200892657
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1737432554
Short name T365
Test name
Test status
Simulation time 1230078754 ps
CPU time 5.55 seconds
Started Jul 09 05:43:44 PM PDT 24
Finished Jul 09 05:43:50 PM PDT 24
Peak memory 216972 kb
Host smart-2a2513e2-2b8d-4493-a3c4-6cc787898113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737432554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1737432554
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4055294561
Short name T275
Test name
Test status
Simulation time 244109454 ps
CPU time 1.07 seconds
Started Jul 09 05:43:30 PM PDT 24
Finished Jul 09 05:43:38 PM PDT 24
Peak memory 217568 kb
Host smart-cf7b6c1f-abd9-4d97-a6ee-955a22c12430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055294561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4055294561
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1185632321
Short name T24
Test name
Test status
Simulation time 97028009 ps
CPU time 0.77 seconds
Started Jul 09 05:43:35 PM PDT 24
Finished Jul 09 05:43:37 PM PDT 24
Peak memory 199884 kb
Host smart-474b5eb7-a1cd-490f-a1d8-f3282f3e0cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185632321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1185632321
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1417291356
Short name T503
Test name
Test status
Simulation time 987589771 ps
CPU time 4.82 seconds
Started Jul 09 05:43:51 PM PDT 24
Finished Jul 09 05:43:56 PM PDT 24
Peak memory 200416 kb
Host smart-26008b9f-607e-411b-9ddb-b0f7853769e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417291356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1417291356
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2456223994
Short name T360
Test name
Test status
Simulation time 177486120 ps
CPU time 1.15 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 200188 kb
Host smart-ad90051d-3098-4086-a39e-11e0e1787579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456223994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2456223994
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.387182297
Short name T143
Test name
Test status
Simulation time 122076032 ps
CPU time 1.15 seconds
Started Jul 09 05:43:59 PM PDT 24
Finished Jul 09 05:44:01 PM PDT 24
Peak memory 200424 kb
Host smart-81cb9be0-617d-4214-a31b-81ec2ccb14bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387182297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.387182297
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3392278093
Short name T160
Test name
Test status
Simulation time 2272468801 ps
CPU time 9.79 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:51 PM PDT 24
Peak memory 208708 kb
Host smart-c193cb6a-2ce3-4d4b-a5b3-778b1b4c4127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392278093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3392278093
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2839739407
Short name T515
Test name
Test status
Simulation time 347195431 ps
CPU time 2.05 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:37 PM PDT 24
Peak memory 200384 kb
Host smart-16e26a9c-c4aa-40e8-97e0-e8f7eaa735ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839739407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2839739407
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1342286897
Short name T294
Test name
Test status
Simulation time 171064090 ps
CPU time 1.13 seconds
Started Jul 09 05:43:49 PM PDT 24
Finished Jul 09 05:43:51 PM PDT 24
Peak memory 200188 kb
Host smart-305a70e3-f027-4510-b18d-387f29c67058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342286897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1342286897
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3105781874
Short name T500
Test name
Test status
Simulation time 76905681 ps
CPU time 0.8 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:33 PM PDT 24
Peak memory 199944 kb
Host smart-ecd5a7f6-7422-4aa2-873f-b762c7c698c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105781874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3105781874
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1838027426
Short name T9
Test name
Test status
Simulation time 1222666357 ps
CPU time 5.79 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:38 PM PDT 24
Peak memory 217332 kb
Host smart-3a1e9e99-1983-408f-a147-d9afebeda72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838027426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1838027426
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3713805635
Short name T188
Test name
Test status
Simulation time 246409493 ps
CPU time 1.07 seconds
Started Jul 09 05:43:45 PM PDT 24
Finished Jul 09 05:43:46 PM PDT 24
Peak memory 217600 kb
Host smart-4116a631-e23c-4fab-b71f-291ccfbf2e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713805635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3713805635
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.4058453918
Short name T442
Test name
Test status
Simulation time 83165448 ps
CPU time 0.76 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 199920 kb
Host smart-aba974f0-682e-4d1f-bcea-6c84a326fdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058453918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.4058453918
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3663243061
Short name T409
Test name
Test status
Simulation time 926325171 ps
CPU time 5.09 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:41 PM PDT 24
Peak memory 200408 kb
Host smart-9510fbfe-cc78-44a6-b1c2-cb7d4640ae64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663243061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3663243061
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.303575170
Short name T280
Test name
Test status
Simulation time 97730437 ps
CPU time 0.96 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 200196 kb
Host smart-da099214-4ecc-4276-8158-372c31a46a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303575170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.303575170
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1140791451
Short name T198
Test name
Test status
Simulation time 259408239 ps
CPU time 1.55 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:37 PM PDT 24
Peak memory 200376 kb
Host smart-ac9303e9-ba8c-4289-af88-11c8955a130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140791451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1140791451
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3764349008
Short name T339
Test name
Test status
Simulation time 12066383564 ps
CPU time 42.91 seconds
Started Jul 09 05:43:40 PM PDT 24
Finished Jul 09 05:44:25 PM PDT 24
Peak memory 200432 kb
Host smart-16111012-b766-4713-88aa-95b0a5ee3e20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764349008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3764349008
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.4127504364
Short name T224
Test name
Test status
Simulation time 431952153 ps
CPU time 2.5 seconds
Started Jul 09 05:43:54 PM PDT 24
Finished Jul 09 05:43:57 PM PDT 24
Peak memory 200104 kb
Host smart-7ef8a147-e26d-44eb-8e14-9bc270176203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127504364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.4127504364
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2426265608
Short name T184
Test name
Test status
Simulation time 67064083 ps
CPU time 0.85 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 200120 kb
Host smart-e0f7d8ac-52d1-4bc4-9630-31cd92e2df2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426265608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2426265608
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.93580941
Short name T42
Test name
Test status
Simulation time 60862455 ps
CPU time 0.73 seconds
Started Jul 09 05:43:34 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 199964 kb
Host smart-10b58be8-c20e-4bbd-8069-cbf249ecf5ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93580941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.93580941
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1450196984
Short name T34
Test name
Test status
Simulation time 1228590450 ps
CPU time 5.38 seconds
Started Jul 09 05:44:00 PM PDT 24
Finished Jul 09 05:44:07 PM PDT 24
Peak memory 217728 kb
Host smart-f782a9d8-6420-4511-87d2-6ba797725c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450196984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1450196984
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3715909464
Short name T388
Test name
Test status
Simulation time 245067509 ps
CPU time 1.04 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 217548 kb
Host smart-decd4c23-b17c-46d8-989c-be61e89c6997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715909464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3715909464
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3465687078
Short name T263
Test name
Test status
Simulation time 95530052 ps
CPU time 0.78 seconds
Started Jul 09 05:43:53 PM PDT 24
Finished Jul 09 05:43:55 PM PDT 24
Peak memory 199880 kb
Host smart-fb43215c-b78a-4f59-8700-e7e963b2744f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465687078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3465687078
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2348995654
Short name T202
Test name
Test status
Simulation time 912199680 ps
CPU time 4.32 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:46 PM PDT 24
Peak memory 200364 kb
Host smart-18d3824f-2c9a-4f8c-9e91-51f762da7bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348995654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2348995654
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3322831221
Short name T461
Test name
Test status
Simulation time 141942569 ps
CPU time 1.23 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 200192 kb
Host smart-c35ed49d-7b71-453c-887b-08826e9c4539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322831221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3322831221
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2417321838
Short name T231
Test name
Test status
Simulation time 202958169 ps
CPU time 1.37 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 200356 kb
Host smart-4d8922c6-1ce7-4efd-87b3-de3aa50634db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417321838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2417321838
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2564754955
Short name T371
Test name
Test status
Simulation time 12388583038 ps
CPU time 47.56 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:44:26 PM PDT 24
Peak memory 210520 kb
Host smart-44b512db-d280-46ce-b801-dbdbca27b03f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564754955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2564754955
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.348307150
Short name T501
Test name
Test status
Simulation time 137652111 ps
CPU time 1.79 seconds
Started Jul 09 05:43:53 PM PDT 24
Finished Jul 09 05:43:56 PM PDT 24
Peak memory 200064 kb
Host smart-c09d9bf6-bc8d-414d-bcef-cdc4e92b249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348307150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.348307150
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.592762247
Short name T267
Test name
Test status
Simulation time 177821688 ps
CPU time 1.1 seconds
Started Jul 09 05:43:35 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 200192 kb
Host smart-6cb344a2-9ab7-43e1-8124-525ee030a0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592762247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.592762247
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3551851178
Short name T478
Test name
Test status
Simulation time 66993137 ps
CPU time 0.76 seconds
Started Jul 09 05:42:42 PM PDT 24
Finished Jul 09 05:42:43 PM PDT 24
Peak memory 199956 kb
Host smart-251a18cb-7bc0-40fe-a919-2d7ce161f9ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551851178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3551851178
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.151633032
Short name T52
Test name
Test status
Simulation time 1903458215 ps
CPU time 7.84 seconds
Started Jul 09 05:42:39 PM PDT 24
Finished Jul 09 05:42:47 PM PDT 24
Peak memory 217608 kb
Host smart-7ae54840-98bf-4754-97de-54b1533e611c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151633032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.151633032
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3168859455
Short name T387
Test name
Test status
Simulation time 244863063 ps
CPU time 1.06 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:35 PM PDT 24
Peak memory 217612 kb
Host smart-5181e6b6-2c19-4a5f-8712-ab04479dbeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168859455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3168859455
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3222305152
Short name T265
Test name
Test status
Simulation time 153371153 ps
CPU time 0.92 seconds
Started Jul 09 05:42:36 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 199952 kb
Host smart-ee6ef05a-42cb-4493-99e0-0c74021708a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222305152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3222305152
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1820645906
Short name T346
Test name
Test status
Simulation time 1572215661 ps
CPU time 5.46 seconds
Started Jul 09 05:42:34 PM PDT 24
Finished Jul 09 05:42:41 PM PDT 24
Peak memory 200208 kb
Host smart-3058f7ab-ef2f-49db-a540-586599a63368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820645906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1820645906
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2817982813
Short name T533
Test name
Test status
Simulation time 107525064 ps
CPU time 0.96 seconds
Started Jul 09 05:42:33 PM PDT 24
Finished Jul 09 05:42:35 PM PDT 24
Peak memory 200156 kb
Host smart-c3fac4be-4384-4659-8fbb-f8613cc65be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817982813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2817982813
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1770149768
Short name T273
Test name
Test status
Simulation time 114912275 ps
CPU time 1.13 seconds
Started Jul 09 05:42:35 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 200328 kb
Host smart-551042fb-59e0-444d-a9e2-0d8522fce16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770149768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1770149768
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2664749865
Short name T13
Test name
Test status
Simulation time 1355461919 ps
CPU time 5.34 seconds
Started Jul 09 05:42:35 PM PDT 24
Finished Jul 09 05:42:42 PM PDT 24
Peak memory 200452 kb
Host smart-bd2879cc-e244-4329-a737-bfec28e42a68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664749865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2664749865
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3807465364
Short name T416
Test name
Test status
Simulation time 263457501 ps
CPU time 1.84 seconds
Started Jul 09 05:42:36 PM PDT 24
Finished Jul 09 05:42:39 PM PDT 24
Peak memory 200140 kb
Host smart-74f9b5c3-72b5-41e8-a939-c71fd8896dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807465364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3807465364
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1144693495
Short name T159
Test name
Test status
Simulation time 238233755 ps
CPU time 1.38 seconds
Started Jul 09 05:42:36 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 200104 kb
Host smart-88310f13-897a-45e4-8f70-d7c5fae90645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144693495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1144693495
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3444552894
Short name T384
Test name
Test status
Simulation time 66315702 ps
CPU time 0.79 seconds
Started Jul 09 05:42:42 PM PDT 24
Finished Jul 09 05:42:43 PM PDT 24
Peak memory 199980 kb
Host smart-eb3bc9a3-4364-4dd6-aaca-b9cd0c284b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444552894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3444552894
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.620180551
Short name T40
Test name
Test status
Simulation time 1229252539 ps
CPU time 6.04 seconds
Started Jul 09 05:42:41 PM PDT 24
Finished Jul 09 05:42:47 PM PDT 24
Peak memory 221780 kb
Host smart-4254e582-5a7f-41bf-ad5b-a151bc04edf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620180551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.620180551
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1714212800
Short name T493
Test name
Test status
Simulation time 244331586 ps
CPU time 1.08 seconds
Started Jul 09 05:42:43 PM PDT 24
Finished Jul 09 05:42:44 PM PDT 24
Peak memory 217500 kb
Host smart-b85ae8ab-8024-4e76-aa6c-8f06c2b35fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714212800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1714212800
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2022538637
Short name T469
Test name
Test status
Simulation time 211831843 ps
CPU time 0.85 seconds
Started Jul 09 05:42:42 PM PDT 24
Finished Jul 09 05:42:44 PM PDT 24
Peak memory 199992 kb
Host smart-d615bf90-9c3c-49b5-8cee-3fa0bbc41fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022538637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2022538637
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.636017128
Short name T140
Test name
Test status
Simulation time 919081911 ps
CPU time 5.09 seconds
Started Jul 09 05:42:44 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 200448 kb
Host smart-a0d9e551-7834-40cb-a01c-cd8fa4f75f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636017128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.636017128
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3434271734
Short name T520
Test name
Test status
Simulation time 149901400 ps
CPU time 1.2 seconds
Started Jul 09 05:42:38 PM PDT 24
Finished Jul 09 05:42:40 PM PDT 24
Peak memory 200132 kb
Host smart-9d003e03-f5a2-4e68-8c80-ef9738f5c21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434271734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3434271734
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2293730120
Short name T177
Test name
Test status
Simulation time 252526089 ps
CPU time 1.54 seconds
Started Jul 09 05:42:41 PM PDT 24
Finished Jul 09 05:42:43 PM PDT 24
Peak memory 200316 kb
Host smart-93dae9b1-77ac-470c-a006-a58ee53a5f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293730120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2293730120
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3133767881
Short name T117
Test name
Test status
Simulation time 1860421478 ps
CPU time 7.46 seconds
Started Jul 09 05:42:40 PM PDT 24
Finished Jul 09 05:42:48 PM PDT 24
Peak memory 208616 kb
Host smart-45ae5188-ebca-481c-9594-69359af7d3fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133767881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3133767881
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1027242356
Short name T467
Test name
Test status
Simulation time 143040754 ps
CPU time 1.78 seconds
Started Jul 09 05:42:40 PM PDT 24
Finished Jul 09 05:42:42 PM PDT 24
Peak memory 200064 kb
Host smart-6b2438b6-afc1-4c15-bbd4-833938cb5525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027242356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1027242356
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.816651148
Short name T373
Test name
Test status
Simulation time 77232791 ps
CPU time 0.83 seconds
Started Jul 09 05:42:37 PM PDT 24
Finished Jul 09 05:42:38 PM PDT 24
Peak memory 200144 kb
Host smart-ff1a5424-9f80-4c52-af85-29781a9bdc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816651148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.816651148
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.249252133
Short name T180
Test name
Test status
Simulation time 61691304 ps
CPU time 0.71 seconds
Started Jul 09 05:43:06 PM PDT 24
Finished Jul 09 05:43:08 PM PDT 24
Peak memory 199940 kb
Host smart-9f4c9151-99b2-4eee-b3e2-0a5cd584311d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249252133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.249252133
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.601224050
Short name T38
Test name
Test status
Simulation time 1890254522 ps
CPU time 7.45 seconds
Started Jul 09 05:42:42 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 229848 kb
Host smart-e91859da-f7e6-41fa-b5cb-1adff9b5006c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601224050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.601224050
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3181268451
Short name T293
Test name
Test status
Simulation time 244456474 ps
CPU time 1.02 seconds
Started Jul 09 05:42:41 PM PDT 24
Finished Jul 09 05:42:43 PM PDT 24
Peak memory 217524 kb
Host smart-37d927b1-d0dd-4ba1-9a6f-5369d7e92e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181268451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3181268451
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1632927677
Short name T233
Test name
Test status
Simulation time 129820358 ps
CPU time 0.79 seconds
Started Jul 09 05:42:41 PM PDT 24
Finished Jul 09 05:42:42 PM PDT 24
Peak memory 199996 kb
Host smart-6ee5d0ba-c2f5-4b64-bb8d-eaaa061f9789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632927677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1632927677
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3007099859
Short name T254
Test name
Test status
Simulation time 1911344119 ps
CPU time 6.83 seconds
Started Jul 09 05:42:41 PM PDT 24
Finished Jul 09 05:42:48 PM PDT 24
Peak memory 200440 kb
Host smart-05b0a603-62a3-4c6a-80ad-36c92a2efe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007099859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3007099859
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.843712888
Short name T353
Test name
Test status
Simulation time 157278368 ps
CPU time 1.23 seconds
Started Jul 09 05:42:44 PM PDT 24
Finished Jul 09 05:42:46 PM PDT 24
Peak memory 200180 kb
Host smart-f1b6aab2-e818-46af-8025-cd26be5fb5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843712888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.843712888
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.28760321
Short name T270
Test name
Test status
Simulation time 115980350 ps
CPU time 1.2 seconds
Started Jul 09 05:42:41 PM PDT 24
Finished Jul 09 05:42:43 PM PDT 24
Peak memory 200380 kb
Host smart-2f33511d-4040-4c86-939f-5732faf71acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28760321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.28760321
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.247880206
Short name T91
Test name
Test status
Simulation time 1689719867 ps
CPU time 6.52 seconds
Started Jul 09 05:42:40 PM PDT 24
Finished Jul 09 05:42:47 PM PDT 24
Peak memory 200404 kb
Host smart-e077160b-579c-4275-a90c-60afbe3671eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247880206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.247880206
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2164256840
Short name T148
Test name
Test status
Simulation time 136898169 ps
CPU time 1.57 seconds
Started Jul 09 05:42:42 PM PDT 24
Finished Jul 09 05:42:44 PM PDT 24
Peak memory 208416 kb
Host smart-8cb501d0-a4ff-46e0-847f-60ebd330c263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164256840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2164256840
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3530813715
Short name T448
Test name
Test status
Simulation time 154238018 ps
CPU time 1.15 seconds
Started Jul 09 05:42:40 PM PDT 24
Finished Jul 09 05:42:41 PM PDT 24
Peak memory 200168 kb
Host smart-6b0b63a8-7f92-4249-a5f6-523c744a162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530813715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3530813715
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1950128208
Short name T512
Test name
Test status
Simulation time 80730362 ps
CPU time 0.83 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:46 PM PDT 24
Peak memory 199984 kb
Host smart-7deb3eb2-c582-4d29-884d-4cb367d9400a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950128208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1950128208
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3683209123
Short name T220
Test name
Test status
Simulation time 1225923707 ps
CPU time 5.96 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:52 PM PDT 24
Peak memory 217436 kb
Host smart-e88dda9a-2d11-40c2-a6ce-181ac5fbac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683209123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3683209123
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1958549494
Short name T427
Test name
Test status
Simulation time 243538574 ps
CPU time 1.14 seconds
Started Jul 09 05:42:43 PM PDT 24
Finished Jul 09 05:42:45 PM PDT 24
Peak memory 217596 kb
Host smart-abcfaac0-7719-41e7-aaca-9bc4a69a35c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958549494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1958549494
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3330531343
Short name T393
Test name
Test status
Simulation time 112150676 ps
CPU time 0.81 seconds
Started Jul 09 05:42:44 PM PDT 24
Finished Jul 09 05:42:45 PM PDT 24
Peak memory 199960 kb
Host smart-ccc316cf-2d75-474c-aa8b-4ea4b0c7eb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330531343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3330531343
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3001452196
Short name T215
Test name
Test status
Simulation time 1143956320 ps
CPU time 5.11 seconds
Started Jul 09 05:42:46 PM PDT 24
Finished Jul 09 05:42:52 PM PDT 24
Peak memory 200436 kb
Host smart-65e3a973-7914-4510-9339-114c07f455b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001452196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3001452196
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.507866680
Short name T136
Test name
Test status
Simulation time 113408899 ps
CPU time 1.04 seconds
Started Jul 09 05:42:43 PM PDT 24
Finished Jul 09 05:42:45 PM PDT 24
Peak memory 200128 kb
Host smart-bb101ba2-551f-4da0-97f1-f50f809a6e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507866680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.507866680
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2969805306
Short name T142
Test name
Test status
Simulation time 185621626 ps
CPU time 1.42 seconds
Started Jul 09 05:42:46 PM PDT 24
Finished Jul 09 05:42:49 PM PDT 24
Peak memory 200352 kb
Host smart-02449719-2f7f-40bd-8dbf-5d8e283768bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969805306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2969805306
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2031601168
Short name T526
Test name
Test status
Simulation time 9188017976 ps
CPU time 31.92 seconds
Started Jul 09 05:42:43 PM PDT 24
Finished Jul 09 05:43:16 PM PDT 24
Peak memory 208700 kb
Host smart-dd830280-a6bc-4998-b233-3e6b21dcb493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031601168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2031601168
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2493080717
Short name T356
Test name
Test status
Simulation time 152403218 ps
CPU time 1.94 seconds
Started Jul 09 05:42:48 PM PDT 24
Finished Jul 09 05:42:53 PM PDT 24
Peak memory 200136 kb
Host smart-d17a6401-d4f3-4e35-8c17-22fc53de510d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493080717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2493080717
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3805451025
Short name T130
Test name
Test status
Simulation time 169332919 ps
CPU time 1.18 seconds
Started Jul 09 05:42:46 PM PDT 24
Finished Jul 09 05:42:49 PM PDT 24
Peak memory 200376 kb
Host smart-f0789bcc-b421-4a7a-8a46-ecd8a275ea49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805451025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3805451025
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2337896341
Short name T367
Test name
Test status
Simulation time 70692113 ps
CPU time 0.76 seconds
Started Jul 09 05:42:46 PM PDT 24
Finished Jul 09 05:42:48 PM PDT 24
Peak memory 199880 kb
Host smart-5139313a-c6da-4ca0-8ed8-7a823d6f42d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337896341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2337896341
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4291641247
Short name T447
Test name
Test status
Simulation time 1887462431 ps
CPU time 6.86 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:53 PM PDT 24
Peak memory 221444 kb
Host smart-dc673a21-3af6-472f-8f85-a05af1474fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291641247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4291641247
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.646930250
Short name T407
Test name
Test status
Simulation time 244869872 ps
CPU time 1.14 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:48 PM PDT 24
Peak memory 217536 kb
Host smart-f387720a-f316-418f-90de-8a3d1381936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646930250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.646930250
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.366703009
Short name T430
Test name
Test status
Simulation time 146858110 ps
CPU time 0.82 seconds
Started Jul 09 05:42:44 PM PDT 24
Finished Jul 09 05:42:46 PM PDT 24
Peak memory 199996 kb
Host smart-17931c47-420b-4f1a-828a-9fd1bbbc8df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366703009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.366703009
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2735851479
Short name T157
Test name
Test status
Simulation time 737035654 ps
CPU time 3.65 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 200404 kb
Host smart-0451db36-6df3-4261-8dc2-55e2dc56a699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735851479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2735851479
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2791540347
Short name T344
Test name
Test status
Simulation time 138237866 ps
CPU time 1.11 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:47 PM PDT 24
Peak memory 200116 kb
Host smart-6033ecc0-cf01-42cc-8511-3aefb8304e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791540347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2791540347
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1925361033
Short name T179
Test name
Test status
Simulation time 125244938 ps
CPU time 1.18 seconds
Started Jul 09 05:42:43 PM PDT 24
Finished Jul 09 05:42:45 PM PDT 24
Peak memory 200344 kb
Host smart-58b83cde-899c-413e-bcd7-a59943d05089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925361033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1925361033
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3664581655
Short name T28
Test name
Test status
Simulation time 2353721751 ps
CPU time 8.08 seconds
Started Jul 09 05:42:45 PM PDT 24
Finished Jul 09 05:42:55 PM PDT 24
Peak memory 208660 kb
Host smart-b68e2261-970e-458a-865b-fde1a2e9a4f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664581655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3664581655
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.797787572
Short name T380
Test name
Test status
Simulation time 496164286 ps
CPU time 2.48 seconds
Started Jul 09 05:42:46 PM PDT 24
Finished Jul 09 05:42:50 PM PDT 24
Peak memory 200228 kb
Host smart-d24e7686-fe10-43e9-8609-2137c9611f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797787572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.797787572
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3155466546
Short name T193
Test name
Test status
Simulation time 199826592 ps
CPU time 1.25 seconds
Started Jul 09 05:42:44 PM PDT 24
Finished Jul 09 05:42:46 PM PDT 24
Peak memory 200168 kb
Host smart-95b4111a-4053-469d-9cd9-d32510828905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155466546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3155466546
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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