Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8309

1

T2

32

T6

5

T7

16

auto[1]

11340

1

T1

4

T2

32

T3

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6071	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6581	1			T1	2		T2	15		T3	2
reset_info_cp[2]	3068	1			T1	1		T2	10		T3	1
reset_info_cp[4]	3987	1			T1	1		T2	21		T3	1
reset_info_cp[8]	104	1			T7	2		T51	1		T53	1
reset_info_cp[16]	112	1			T9	1		T53	2		T50	2
reset_info_cp[32]	117	1			T2	1		T6	1		T53	1
reset_info_cp[64]	106	1			T6	1		T7	2		T51	1
reset_info_cp[128]	123	1			T2	1		T7	1		T51	3

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3164	1			T2	6		T9	19		T51	36
reset_info_cp[1]	auto[1]	2797	1			T1	1		T2	8		T3	1
reset_info_cp[2]	auto[0]	999	1			T2	7		T51	16		T53	14
reset_info_cp[2]	auto[1]	2069	1			T1	1		T2	3		T3	1
reset_info_cp[4]	auto[0]	1435	1			T2	10		T51	32		T53	26
reset_info_cp[4]	auto[1]	2552	1			T1	1		T2	11		T3	1
reset_info_cp[8]	auto[0]	50	1			T7	2		T51	1		T50	1
reset_info_cp[8]	auto[1]	54	1			T53	1		T42	2		T50	1
reset_info_cp[16]	auto[0]	41	1			T130	1		T95	1		T77	1
reset_info_cp[16]	auto[1]	71	1			T9	1		T53	2		T50	2
reset_info_cp[32]	auto[0]	43	1			T2	1		T53	1		T62	1
reset_info_cp[32]	auto[1]	74	1			T6	1		T50	2		T62	1
reset_info_cp[64]	auto[0]	44	1			T6	1		T7	2		T51	1
reset_info_cp[64]	auto[1]	62	1			T53	3		T42	1		T50	1
reset_info_cp[128]	auto[0]	47	1			T7	1		T53	1		T62	2
reset_info_cp[128]	auto[1]	76	1			T2	1		T51	3		T53	3