Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T535 /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.159253118 Jul 10 07:19:44 PM PDT 24 Jul 10 07:19:50 PM PDT 24 97605488 ps
T536 /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3612087466 Jul 10 07:19:58 PM PDT 24 Jul 10 07:20:01 PM PDT 24 245081564 ps
T537 /workspace/coverage/default/0.rstmgr_alert_test.3774044694 Jul 10 07:19:45 PM PDT 24 Jul 10 07:19:50 PM PDT 24 86954059 ps
T538 /workspace/coverage/default/44.rstmgr_por_stretcher.2421441660 Jul 10 07:21:26 PM PDT 24 Jul 10 07:21:30 PM PDT 24 206066268 ps
T539 /workspace/coverage/default/10.rstmgr_alert_test.3555892297 Jul 10 07:20:19 PM PDT 24 Jul 10 07:20:23 PM PDT 24 68325820 ps
T63 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3980960141 Jul 10 05:40:39 PM PDT 24 Jul 10 05:40:42 PM PDT 24 891278542 ps
T64 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4037932868 Jul 10 05:40:52 PM PDT 24 Jul 10 05:40:54 PM PDT 24 67527632 ps
T67 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3956956765 Jul 10 05:40:45 PM PDT 24 Jul 10 05:40:48 PM PDT 24 316819896 ps
T65 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1550839575 Jul 10 05:40:57 PM PDT 24 Jul 10 05:41:02 PM PDT 24 791287963 ps
T66 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2668918262 Jul 10 05:40:34 PM PDT 24 Jul 10 05:40:38 PM PDT 24 866420340 ps
T68 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2265122274 Jul 10 05:40:50 PM PDT 24 Jul 10 05:40:53 PM PDT 24 198403816 ps
T102 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2061318295 Jul 10 05:40:50 PM PDT 24 Jul 10 05:40:52 PM PDT 24 94907462 ps
T69 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1228199197 Jul 10 05:40:46 PM PDT 24 Jul 10 05:40:48 PM PDT 24 114820075 ps
T88 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3697332095 Jul 10 05:40:57 PM PDT 24 Jul 10 05:41:01 PM PDT 24 416774891 ps
T540 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.956425280 Jul 10 05:40:33 PM PDT 24 Jul 10 05:40:41 PM PDT 24 487865637 ps
T89 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.783996135 Jul 10 05:40:47 PM PDT 24 Jul 10 05:40:50 PM PDT 24 208991589 ps
T90 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4083191393 Jul 10 05:41:02 PM PDT 24 Jul 10 05:41:05 PM PDT 24 421705773 ps
T91 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3364182082 Jul 10 05:40:58 PM PDT 24 Jul 10 05:41:02 PM PDT 24 793916405 ps
T103 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4123515799 Jul 10 05:41:01 PM PDT 24 Jul 10 05:41:02 PM PDT 24 74574238 ps
T541 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1136876535 Jul 10 05:40:40 PM PDT 24 Jul 10 05:40:42 PM PDT 24 90538731 ps
T92 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.204127624 Jul 10 05:40:57 PM PDT 24 Jul 10 05:41:00 PM PDT 24 117416344 ps
T93 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1576656383 Jul 10 05:41:03 PM PDT 24 Jul 10 05:41:06 PM PDT 24 167331721 ps
T104 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.140293973 Jul 10 05:40:51 PM PDT 24 Jul 10 05:40:54 PM PDT 24 82873639 ps
T542 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2079162366 Jul 10 05:40:57 PM PDT 24 Jul 10 05:40:58 PM PDT 24 75107327 ps
T105 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.978520846 Jul 10 05:41:01 PM PDT 24 Jul 10 05:41:03 PM PDT 24 77943516 ps
T106 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.742683315 Jul 10 05:40:58 PM PDT 24 Jul 10 05:41:00 PM PDT 24 86119950 ps
T94 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2160439249 Jul 10 05:40:51 PM PDT 24 Jul 10 05:40:55 PM PDT 24 149231746 ps
T117 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.645627030 Jul 10 05:40:57 PM PDT 24 Jul 10 05:41:00 PM PDT 24 426122488 ps
T107 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3394963158 Jul 10 05:40:45 PM PDT 24 Jul 10 05:40:46 PM PDT 24 60695048 ps
T543 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1194861291 Jul 10 05:40:40 PM PDT 24 Jul 10 05:40:42 PM PDT 24 138117236 ps
T113 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3775977723 Jul 10 05:40:45 PM PDT 24 Jul 10 05:40:48 PM PDT 24 113902210 ps
T108 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2059036633 Jul 10 05:41:02 PM PDT 24 Jul 10 05:41:05 PM PDT 24 66577508 ps
T109 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2182931754 Jul 10 05:40:46 PM PDT 24 Jul 10 05:40:48 PM PDT 24 74193132 ps
T110 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4171677975 Jul 10 05:40:48 PM PDT 24 Jul 10 05:40:50 PM PDT 24 84036042 ps
T111 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3425934854 Jul 10 05:40:40 PM PDT 24 Jul 10 05:40:42 PM PDT 24 213402893 ps
T544 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3450745279 Jul 10 05:40:57 PM PDT 24 Jul 10 05:40:58 PM PDT 24 76410590 ps
T545 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3885651055 Jul 10 05:40:45 PM PDT 24 Jul 10 05:40:48 PM PDT 24 258446048 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3428222214 Jul 10 05:40:42 PM PDT 24 Jul 10 05:40:43 PM PDT 24 63272478 ps
T547 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3153194883 Jul 10 05:40:52 PM PDT 24 Jul 10 05:40:54 PM PDT 24 64700261 ps
T118 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3826022531 Jul 10 05:40:48 PM PDT 24 Jul 10 05:40:51 PM PDT 24 299495319 ps
T112 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2777484571 Jul 10 05:40:58 PM PDT 24 Jul 10 05:41:01 PM PDT 24 161147508 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.317398448 Jul 10 05:40:40 PM PDT 24 Jul 10 05:40:46 PM PDT 24 1172120085 ps
T549 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1165307573 Jul 10 05:41:02 PM PDT 24 Jul 10 05:41:07 PM PDT 24 433710407 ps
T550 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3594672576 Jul 10 05:40:34 PM PDT 24 Jul 10 05:40:37 PM PDT 24 113897972 ps
T128 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1767257714 Jul 10 05:40:38 PM PDT 24 Jul 10 05:40:40 PM PDT 24 429111777 ps
T551 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1290420645 Jul 10 05:40:46 PM PDT 24 Jul 10 05:40:48 PM PDT 24 137369369 ps
T552 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.176109956 Jul 10 05:40:47 PM PDT 24 Jul 10 05:40:49 PM PDT 24 64617780 ps
T553 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2814813181 Jul 10 05:41:03 PM PDT 24 Jul 10 05:41:06 PM PDT 24 171739575 ps
T554 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1044637010 Jul 10 05:40:56 PM PDT 24 Jul 10 05:40:58 PM PDT 24 242607226 ps
T555 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.857855575 Jul 10 05:40:53 PM PDT 24 Jul 10 05:40:55 PM PDT 24 115038880 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3426631204 Jul 10 05:40:35 PM PDT 24 Jul 10 05:40:37 PM PDT 24 94868605 ps
T557 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.241944906 Jul 10 05:40:51 PM PDT 24 Jul 10 05:40:54 PM PDT 24 402411350 ps
T119 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1450984692 Jul 10 05:40:54 PM PDT 24 Jul 10 05:40:57 PM PDT 24 467080304 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3671382838 Jul 10 05:40:42 PM PDT 24 Jul 10 05:40:44 PM PDT 24 80615416 ps
T559 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1140065414 Jul 10 05:40:36 PM PDT 24 Jul 10 05:40:40 PM PDT 24 380034452 ps
T129 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1254253655 Jul 10 05:40:57 PM PDT 24 Jul 10 05:41:00 PM PDT 24 465866488 ps
T560 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2483699579 Jul 10 05:40:48 PM PDT 24 Jul 10 05:40:50 PM PDT 24 90439884 ps
T561 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.938544695 Jul 10 05:40:45 PM PDT 24 Jul 10 05:40:48 PM PDT 24 489737964 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.551114808 Jul 10 05:40:35 PM PDT 24 Jul 10 05:40:37 PM PDT 24 106372402 ps
T563 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.64836097 Jul 10 05:40:56 PM PDT 24 Jul 10 05:40:58 PM PDT 24 75743059 ps
T564 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1160516616 Jul 10 05:41:04 PM PDT 24 Jul 10 05:41:06 PM PDT 24 98773800 ps
T565 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3373078262 Jul 10 05:40:33 PM PDT 24 Jul 10 05:40:36 PM PDT 24 238744246 ps
T566 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1982782446 Jul 10 05:41:03 PM PDT 24 Jul 10 05:41:06 PM PDT 24 234481919 ps
T567 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1197742658 Jul 10 05:40:33 PM PDT 24 Jul 10 05:40:36 PM PDT 24 176323631 ps
T568 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1851108605 Jul 10 05:40:53 PM PDT 24 Jul 10 05:40:56 PM PDT 24 187579173 ps
T569 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2903337956 Jul 10 05:41:03 PM PDT 24 Jul 10 05:41:06 PM PDT 24 176989291 ps
T570 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.635075738 Jul 10 05:40:46 PM PDT 24 Jul 10 05:40:48 PM PDT 24 67573656 ps
T571 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1872628786 Jul 10 05:40:57 PM PDT 24 Jul 10 05:40:59 PM PDT 24 100618118 ps
T572 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4168193852 Jul 10 05:40:41 PM PDT 24 Jul 10 05:40:44 PM PDT 24 355995265 ps
T573 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2999615257 Jul 10 05:40:49 PM PDT 24 Jul 10 05:40:53 PM PDT 24 455415785 ps
T574 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.388002360 Jul 10 05:40:53 PM PDT 24 Jul 10 05:40:55 PM PDT 24 103355284 ps
T575 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2756927298 Jul 10 05:40:42 PM PDT 24 Jul 10 05:40:44 PM PDT 24 101358395 ps
T576 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4182358515 Jul 10 05:40:50 PM PDT 24 Jul 10 05:40:55 PM PDT 24 389570069 ps
T577 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.974801491 Jul 10 05:40:34 PM PDT 24 Jul 10 05:40:36 PM PDT 24 116031040 ps
T578 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3893186762 Jul 10 05:40:35 PM PDT 24 Jul 10 05:40:37 PM PDT 24 144236240 ps
T579 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2576176236 Jul 10 05:40:50 PM PDT 24 Jul 10 05:40:52 PM PDT 24 126154343 ps
T580 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2400610997 Jul 10 05:41:00 PM PDT 24 Jul 10 05:41:02 PM PDT 24 106027207 ps
T581 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1008450802 Jul 10 05:41:01 PM PDT 24 Jul 10 05:41:04 PM PDT 24 131703184 ps
T582 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2573968998 Jul 10 05:40:47 PM PDT 24 Jul 10 05:40:50 PM PDT 24 425734600 ps
T583 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1789424733 Jul 10 05:41:01 PM PDT 24 Jul 10 05:41:03 PM PDT 24 217413014 ps
T584 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1365269699 Jul 10 05:41:03 PM PDT 24 Jul 10 05:41:06 PM PDT 24 59491320 ps
T585 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.449282462 Jul 10 05:40:57 PM PDT 24 Jul 10 05:41:00 PM PDT 24 169151149 ps
T586 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2713884364 Jul 10 05:43:08 PM PDT 24 Jul 10 05:43:11 PM PDT 24 190614123 ps
T114 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1115107683 Jul 10 05:41:01 PM PDT 24 Jul 10 05:41:04 PM PDT 24 429322775 ps
T115 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.843275527 Jul 10 05:41:01 PM PDT 24 Jul 10 05:41:04 PM PDT 24 517736142 ps
T587 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1752528439 Jul 10 05:40:57 PM PDT 24 Jul 10 05:41:01 PM PDT 24 155235720 ps
T588 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2507564545 Jul 10 05:40:47 PM PDT 24 Jul 10 05:40:50 PM PDT 24 155147530 ps
T589 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1691279810 Jul 10 05:40:51 PM PDT 24 Jul 10 05:40:53 PM PDT 24 84863873 ps
T590 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2782888878 Jul 10 05:40:44 PM PDT 24 Jul 10 05:40:46 PM PDT 24 223122350 ps
T591 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4208290608 Jul 10 05:40:53 PM PDT 24 Jul 10 05:40:56 PM PDT 24 507626021 ps
T592 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3452689646 Jul 10 05:40:57 PM PDT 24 Jul 10 05:40:59 PM PDT 24 63533582 ps
T593 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.64634884 Jul 10 05:40:45 PM PDT 24 Jul 10 05:40:49 PM PDT 24 913912375 ps
T594 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1230070483 Jul 10 05:40:50 PM PDT 24 Jul 10 05:40:53 PM PDT 24 175244914 ps
T595 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1598583947 Jul 10 05:40:34 PM PDT 24 Jul 10 05:40:37 PM PDT 24 233986340 ps
T596 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1878899015 Jul 10 05:40:46 PM PDT 24 Jul 10 05:40:51 PM PDT 24 268370720 ps
T597 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1368922081 Jul 10 05:41:03 PM PDT 24 Jul 10 05:41:05 PM PDT 24 70205223 ps
T598 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2350400057 Jul 10 05:40:40 PM PDT 24 Jul 10 05:40:49 PM PDT 24 1980168616 ps
T599 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.387873646 Jul 10 05:40:51 PM PDT 24 Jul 10 05:40:53 PM PDT 24 119541074 ps
T600 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3990156996 Jul 10 05:41:01 PM PDT 24 Jul 10 05:41:03 PM PDT 24 160786800 ps
T601 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.734425053 Jul 10 05:40:34 PM PDT 24 Jul 10 05:40:39 PM PDT 24 894332219 ps
T602 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2868089749 Jul 10 05:40:47 PM PDT 24 Jul 10 05:40:50 PM PDT 24 429163953 ps
T603 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1844220026 Jul 10 05:40:45 PM PDT 24 Jul 10 05:40:48 PM PDT 24 110995414 ps
T604 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.104057786 Jul 10 05:41:02 PM PDT 24 Jul 10 05:41:05 PM PDT 24 278659329 ps
T605 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2083669008 Jul 10 05:41:02 PM PDT 24 Jul 10 05:41:05 PM PDT 24 187189291 ps
T606 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1533044882 Jul 10 05:40:46 PM PDT 24 Jul 10 05:40:50 PM PDT 24 503114528 ps
T607 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2822470089 Jul 10 05:40:50 PM PDT 24 Jul 10 05:40:53 PM PDT 24 81863127 ps
T608 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2288575606 Jul 10 05:40:40 PM PDT 24 Jul 10 05:40:44 PM PDT 24 319735163 ps
T609 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1700886011 Jul 10 05:40:45 PM PDT 24 Jul 10 05:40:47 PM PDT 24 154991375 ps
T610 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4131626274 Jul 10 05:40:52 PM PDT 24 Jul 10 05:40:54 PM PDT 24 58152747 ps
T611 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2892070948 Jul 10 05:41:02 PM PDT 24 Jul 10 05:41:04 PM PDT 24 178203632 ps
T612 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3655385955 Jul 10 05:40:56 PM PDT 24 Jul 10 05:40:59 PM PDT 24 123613018 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2021656988 Jul 10 05:40:44 PM PDT 24 Jul 10 05:40:47 PM PDT 24 195121248 ps
T614 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.278423039 Jul 10 05:40:57 PM PDT 24 Jul 10 05:40:59 PM PDT 24 103025579 ps
T116 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1474308158 Jul 10 05:40:51 PM PDT 24 Jul 10 05:40:56 PM PDT 24 915920829 ps
T615 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2285391313 Jul 10 05:40:33 PM PDT 24 Jul 10 05:40:35 PM PDT 24 70248834 ps
T616 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.296301512 Jul 10 05:41:01 PM PDT 24 Jul 10 05:41:04 PM PDT 24 91285444 ps
T617 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3443196134 Jul 10 05:40:34 PM PDT 24 Jul 10 05:40:37 PM PDT 24 245318402 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1593804695 Jul 10 05:40:31 PM PDT 24 Jul 10 05:40:34 PM PDT 24 174365769 ps
T619 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2245757459 Jul 10 05:41:01 PM PDT 24 Jul 10 05:41:06 PM PDT 24 785157785 ps
T620 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3134647970 Jul 10 05:40:33 PM PDT 24 Jul 10 05:40:40 PM PDT 24 484954593 ps

Test location /workspace/coverage/default/13.rstmgr_smoke.2254973917
Short name T1
Test name
Test status
Simulation time 120324897 ps
CPU time 1.17 seconds
Started Jul 10 07:20:15 PM PDT 24
Finished Jul 10 07:20:20 PM PDT 24
Peak memory 200360 kb
Host smart-e1c954b0-0e22-4f03-8a3c-28c79056f4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254973917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2254973917
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.4114474050
Short name T53
Test name
Test status
Simulation time 5467871885 ps
CPU time 24.03 seconds
Started Jul 10 07:20:51 PM PDT 24
Finished Jul 10 07:21:18 PM PDT 24
Peak memory 209824 kb
Host smart-e1afb720-7679-42bf-9ac6-7eff3c0bf2bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114474050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.4114474050
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.783996135
Short name T89
Test name
Test status
Simulation time 208991589 ps
CPU time 1.34 seconds
Started Jul 10 05:40:47 PM PDT 24
Finished Jul 10 05:40:50 PM PDT 24
Peak memory 211236 kb
Host smart-082ec698-a7c7-4ce0-8f9b-1b67e340c969
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783996135 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.783996135
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3199281433
Short name T70
Test name
Test status
Simulation time 16922916110 ps
CPU time 25.37 seconds
Started Jul 10 07:19:42 PM PDT 24
Finished Jul 10 07:20:12 PM PDT 24
Peak memory 217696 kb
Host smart-08bea366-9c71-48c6-9060-1cb29a5364c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199281433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3199281433
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1980326965
Short name T42
Test name
Test status
Simulation time 1218293810 ps
CPU time 5.94 seconds
Started Jul 10 07:20:19 PM PDT 24
Finished Jul 10 07:20:28 PM PDT 24
Peak memory 221756 kb
Host smart-4aa8e7ec-14e4-4452-99c8-33aa3efb42f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980326965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1980326965
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1234714485
Short name T10
Test name
Test status
Simulation time 249747397 ps
CPU time 1.55 seconds
Started Jul 10 07:21:00 PM PDT 24
Finished Jul 10 07:21:03 PM PDT 24
Peak memory 200328 kb
Host smart-47709877-fff3-4ab2-9230-0ca9506fb539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234714485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1234714485
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2668918262
Short name T66
Test name
Test status
Simulation time 866420340 ps
CPU time 2.91 seconds
Started Jul 10 05:40:34 PM PDT 24
Finished Jul 10 05:40:38 PM PDT 24
Peak memory 200420 kb
Host smart-6e0e5c0f-fa55-41e0-866d-73f729f84f30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668918262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2668918262
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.4215060935
Short name T38
Test name
Test status
Simulation time 335660678 ps
CPU time 2.15 seconds
Started Jul 10 07:20:31 PM PDT 24
Finished Jul 10 07:20:35 PM PDT 24
Peak memory 208348 kb
Host smart-99ea3800-5988-4660-8eaa-2065b1719cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215060935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.4215060935
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1791860217
Short name T54
Test name
Test status
Simulation time 79566175 ps
CPU time 0.82 seconds
Started Jul 10 07:20:19 PM PDT 24
Finished Jul 10 07:20:23 PM PDT 24
Peak memory 199952 kb
Host smart-c9ad7479-b391-4e59-83bd-da8489b3e0fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791860217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1791860217
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3299569782
Short name T50
Test name
Test status
Simulation time 16234499373 ps
CPU time 52.4 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:21:45 PM PDT 24
Peak memory 200496 kb
Host smart-1bab3bf8-10ee-4757-8204-bc33f38301b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299569782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3299569782
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2160439249
Short name T94
Test name
Test status
Simulation time 149231746 ps
CPU time 2.17 seconds
Started Jul 10 05:40:51 PM PDT 24
Finished Jul 10 05:40:55 PM PDT 24
Peak memory 208548 kb
Host smart-4b9f1f98-0821-4d0c-a0c9-4006c99d6fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160439249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2160439249
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2148507861
Short name T188
Test name
Test status
Simulation time 185944050 ps
CPU time 1.29 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:19:48 PM PDT 24
Peak memory 200236 kb
Host smart-d8dd8e3b-7071-43f4-a3ad-df166eae8f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148507861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2148507861
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.143400476
Short name T27
Test name
Test status
Simulation time 1225114643 ps
CPU time 6.44 seconds
Started Jul 10 07:20:49 PM PDT 24
Finished Jul 10 07:20:56 PM PDT 24
Peak memory 221760 kb
Host smart-5027feff-48b8-4699-945a-8ab51bfab665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143400476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.143400476
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2833597385
Short name T153
Test name
Test status
Simulation time 96291415 ps
CPU time 0.93 seconds
Started Jul 10 07:20:13 PM PDT 24
Finished Jul 10 07:20:16 PM PDT 24
Peak memory 200160 kb
Host smart-66a858b3-2524-4d0a-b100-f53e3ee16bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833597385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2833597385
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.843275527
Short name T115
Test name
Test status
Simulation time 517736142 ps
CPU time 2.04 seconds
Started Jul 10 05:41:01 PM PDT 24
Finished Jul 10 05:41:04 PM PDT 24
Peak memory 200552 kb
Host smart-898281df-420f-4ed0-b910-9539910b6228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843275527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.843275527
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1550839575
Short name T65
Test name
Test status
Simulation time 791287963 ps
CPU time 2.73 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:41:02 PM PDT 24
Peak memory 200432 kb
Host smart-4b6929fb-2f5e-4edd-ba77-2ba8010d0c44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550839575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1550839575
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.897976080
Short name T43
Test name
Test status
Simulation time 1225924458 ps
CPU time 6.13 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:18 PM PDT 24
Peak memory 217824 kb
Host smart-98f9271d-b81b-4399-81a6-dec7832ecb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897976080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.897976080
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.742683315
Short name T106
Test name
Test status
Simulation time 86119950 ps
CPU time 1 seconds
Started Jul 10 05:40:58 PM PDT 24
Finished Jul 10 05:41:00 PM PDT 24
Peak memory 200296 kb
Host smart-69bcfd83-9607-40dd-9fbe-3c2f8d381058
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742683315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.742683315
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.59972741
Short name T13
Test name
Test status
Simulation time 209039719 ps
CPU time 0.89 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:19:48 PM PDT 24
Peak memory 199948 kb
Host smart-c9d73054-b4f9-48e6-9a68-ced20bf3f90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59972741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.59972741
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2713884364
Short name T586
Test name
Test status
Simulation time 190614123 ps
CPU time 1.96 seconds
Started Jul 10 05:43:08 PM PDT 24
Finished Jul 10 05:43:11 PM PDT 24
Peak memory 208760 kb
Host smart-130d499f-4f8c-44d7-a545-1da3452a7cc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713884364 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2713884364
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3443196134
Short name T617
Test name
Test status
Simulation time 245318402 ps
CPU time 1.7 seconds
Started Jul 10 05:40:34 PM PDT 24
Finished Jul 10 05:40:37 PM PDT 24
Peak memory 200384 kb
Host smart-5ea2a336-0da9-460a-93c7-39a7922a0ad9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443196134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
443196134
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.956425280
Short name T540
Test name
Test status
Simulation time 487865637 ps
CPU time 6.19 seconds
Started Jul 10 05:40:33 PM PDT 24
Finished Jul 10 05:40:41 PM PDT 24
Peak memory 200336 kb
Host smart-6ce9639a-f1de-4a72-9946-fcfe5015156e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956425280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.956425280
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.974801491
Short name T577
Test name
Test status
Simulation time 116031040 ps
CPU time 0.92 seconds
Started Jul 10 05:40:34 PM PDT 24
Finished Jul 10 05:40:36 PM PDT 24
Peak memory 200152 kb
Host smart-1c61813f-b250-4aaf-a95a-db83559dbd01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974801491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.974801491
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2285391313
Short name T615
Test name
Test status
Simulation time 70248834 ps
CPU time 0.85 seconds
Started Jul 10 05:40:33 PM PDT 24
Finished Jul 10 05:40:35 PM PDT 24
Peak memory 200236 kb
Host smart-5989961f-dea3-4ea8-b59d-f470df5dd52a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285391313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2285391313
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3373078262
Short name T565
Test name
Test status
Simulation time 238744246 ps
CPU time 1.45 seconds
Started Jul 10 05:40:33 PM PDT 24
Finished Jul 10 05:40:36 PM PDT 24
Peak memory 200428 kb
Host smart-92413b1c-c301-44cb-9400-cfc98cb1b2d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373078262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3373078262
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1140065414
Short name T559
Test name
Test status
Simulation time 380034452 ps
CPU time 3.24 seconds
Started Jul 10 05:40:36 PM PDT 24
Finished Jul 10 05:40:40 PM PDT 24
Peak memory 208544 kb
Host smart-0b22c466-5d6b-4c39-a512-dfa600786b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140065414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1140065414
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.551114808
Short name T562
Test name
Test status
Simulation time 106372402 ps
CPU time 1.38 seconds
Started Jul 10 05:40:35 PM PDT 24
Finished Jul 10 05:40:37 PM PDT 24
Peak memory 200304 kb
Host smart-3f819d35-6280-4dfc-80b3-925d9b88e702
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551114808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.551114808
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3134647970
Short name T620
Test name
Test status
Simulation time 484954593 ps
CPU time 5.94 seconds
Started Jul 10 05:40:33 PM PDT 24
Finished Jul 10 05:40:40 PM PDT 24
Peak memory 200432 kb
Host smart-980b9e9e-cf38-43bd-8303-1a5d739d8ed5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134647970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
134647970
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3893186762
Short name T578
Test name
Test status
Simulation time 144236240 ps
CPU time 0.99 seconds
Started Jul 10 05:40:35 PM PDT 24
Finished Jul 10 05:40:37 PM PDT 24
Peak memory 200244 kb
Host smart-85be3552-c699-4271-a4e9-965ccc5d9fd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893186762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
893186762
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1197742658
Short name T567
Test name
Test status
Simulation time 176323631 ps
CPU time 1.18 seconds
Started Jul 10 05:40:33 PM PDT 24
Finished Jul 10 05:40:36 PM PDT 24
Peak memory 200360 kb
Host smart-f31c0ffd-642b-4503-b528-41dba5d8989c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197742658 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1197742658
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3426631204
Short name T556
Test name
Test status
Simulation time 94868605 ps
CPU time 0.91 seconds
Started Jul 10 05:40:35 PM PDT 24
Finished Jul 10 05:40:37 PM PDT 24
Peak memory 200236 kb
Host smart-09182572-0106-4d7e-9e1d-19319b093e43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426631204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3426631204
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3594672576
Short name T550
Test name
Test status
Simulation time 113897972 ps
CPU time 1.07 seconds
Started Jul 10 05:40:34 PM PDT 24
Finished Jul 10 05:40:37 PM PDT 24
Peak memory 200300 kb
Host smart-cfbdad6d-5f2d-4855-9070-989f8afc4ff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594672576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3594672576
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1593804695
Short name T618
Test name
Test status
Simulation time 174365769 ps
CPU time 2.28 seconds
Started Jul 10 05:40:31 PM PDT 24
Finished Jul 10 05:40:34 PM PDT 24
Peak memory 208596 kb
Host smart-d8713596-4187-4e1b-920d-bdf77b15a97a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593804695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1593804695
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.734425053
Short name T601
Test name
Test status
Simulation time 894332219 ps
CPU time 3.22 seconds
Started Jul 10 05:40:34 PM PDT 24
Finished Jul 10 05:40:39 PM PDT 24
Peak memory 200552 kb
Host smart-cef97df0-a3dc-4c53-979f-a12fc34f145b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734425053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
734425053
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.387873646
Short name T599
Test name
Test status
Simulation time 119541074 ps
CPU time 1.31 seconds
Started Jul 10 05:40:51 PM PDT 24
Finished Jul 10 05:40:53 PM PDT 24
Peak memory 208556 kb
Host smart-7226b8a7-28d8-499f-bdc1-d6eb616cfe89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387873646 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.387873646
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4037932868
Short name T64
Test name
Test status
Simulation time 67527632 ps
CPU time 0.78 seconds
Started Jul 10 05:40:52 PM PDT 24
Finished Jul 10 05:40:54 PM PDT 24
Peak memory 200228 kb
Host smart-9868bb51-ef9c-48eb-b4c7-e7bc4469bea6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037932868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4037932868
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.388002360
Short name T574
Test name
Test status
Simulation time 103355284 ps
CPU time 1.27 seconds
Started Jul 10 05:40:53 PM PDT 24
Finished Jul 10 05:40:55 PM PDT 24
Peak memory 200324 kb
Host smart-959f7ce6-aa6a-4cdd-a635-e27d62d32dd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388002360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.388002360
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1851108605
Short name T568
Test name
Test status
Simulation time 187579173 ps
CPU time 1.69 seconds
Started Jul 10 05:40:53 PM PDT 24
Finished Jul 10 05:40:56 PM PDT 24
Peak memory 210896 kb
Host smart-785b5352-e68b-4f6f-b316-1913d526bd94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851108605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1851108605
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.241944906
Short name T557
Test name
Test status
Simulation time 402411350 ps
CPU time 1.74 seconds
Started Jul 10 05:40:51 PM PDT 24
Finished Jul 10 05:40:54 PM PDT 24
Peak memory 200444 kb
Host smart-db01140f-4e28-4b0a-8000-f6364d141ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241944906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.241944906
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3655385955
Short name T612
Test name
Test status
Simulation time 123613018 ps
CPU time 1.32 seconds
Started Jul 10 05:40:56 PM PDT 24
Finished Jul 10 05:40:59 PM PDT 24
Peak memory 208476 kb
Host smart-8f44da3d-2135-45b4-a464-68d60809f63d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655385955 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3655385955
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4131626274
Short name T610
Test name
Test status
Simulation time 58152747 ps
CPU time 0.8 seconds
Started Jul 10 05:40:52 PM PDT 24
Finished Jul 10 05:40:54 PM PDT 24
Peak memory 200224 kb
Host smart-48b0ad68-d74f-4407-afad-67c2e85c195b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131626274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4131626274
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1230070483
Short name T594
Test name
Test status
Simulation time 175244914 ps
CPU time 1.43 seconds
Started Jul 10 05:40:50 PM PDT 24
Finished Jul 10 05:40:53 PM PDT 24
Peak memory 200480 kb
Host smart-2e7ee784-5824-4186-926d-125eea4ac61a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230070483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1230070483
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2999615257
Short name T573
Test name
Test status
Simulation time 455415785 ps
CPU time 2.94 seconds
Started Jul 10 05:40:49 PM PDT 24
Finished Jul 10 05:40:53 PM PDT 24
Peak memory 200260 kb
Host smart-b430c56e-e50c-4820-9976-f785cc683621
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999615257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2999615257
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1450984692
Short name T119
Test name
Test status
Simulation time 467080304 ps
CPU time 1.98 seconds
Started Jul 10 05:40:54 PM PDT 24
Finished Jul 10 05:40:57 PM PDT 24
Peak memory 200396 kb
Host smart-e3868e61-e912-4018-8f22-c105017583c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450984692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1450984692
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.278423039
Short name T614
Test name
Test status
Simulation time 103025579 ps
CPU time 1.09 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:40:59 PM PDT 24
Peak memory 208768 kb
Host smart-caf0b201-99da-4653-ae95-a6c37fd5941a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278423039 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.278423039
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3452689646
Short name T592
Test name
Test status
Simulation time 63533582 ps
CPU time 0.84 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:40:59 PM PDT 24
Peak memory 200144 kb
Host smart-bfdbd28c-90ee-4c6c-b6d9-0c144c643ca2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452689646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3452689646
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1872628786
Short name T571
Test name
Test status
Simulation time 100618118 ps
CPU time 1.33 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:40:59 PM PDT 24
Peak memory 200408 kb
Host smart-ce3caf28-10df-4017-87f6-4393eddd72dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872628786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1872628786
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3697332095
Short name T88
Test name
Test status
Simulation time 416774891 ps
CPU time 2.79 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:41:01 PM PDT 24
Peak memory 212324 kb
Host smart-b1ad1d06-56db-4b91-8546-8318ff881f3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697332095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3697332095
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.204127624
Short name T92
Test name
Test status
Simulation time 117416344 ps
CPU time 1.2 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:41:00 PM PDT 24
Peak memory 208560 kb
Host smart-027efb27-39d9-4ea2-9e26-0fd7a96854ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204127624 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.204127624
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2079162366
Short name T542
Test name
Test status
Simulation time 75107327 ps
CPU time 0.85 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:40:58 PM PDT 24
Peak memory 200144 kb
Host smart-18f10311-8082-4e6c-9e01-0d111610e663
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079162366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2079162366
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1752528439
Short name T587
Test name
Test status
Simulation time 155235720 ps
CPU time 2.2 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:41:01 PM PDT 24
Peak memory 211868 kb
Host smart-f3fae5b7-cdd6-49e4-9822-b7bf897c386d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752528439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1752528439
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3364182082
Short name T91
Test name
Test status
Simulation time 793916405 ps
CPU time 2.94 seconds
Started Jul 10 05:40:58 PM PDT 24
Finished Jul 10 05:41:02 PM PDT 24
Peak memory 200504 kb
Host smart-a8166a56-8b75-4f36-a025-7a6cd5ae910a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364182082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3364182082
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.449282462
Short name T585
Test name
Test status
Simulation time 169151149 ps
CPU time 1.12 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:41:00 PM PDT 24
Peak memory 208548 kb
Host smart-db095b8c-714c-432e-b5bf-178a7480264b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449282462 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.449282462
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3450745279
Short name T544
Test name
Test status
Simulation time 76410590 ps
CPU time 0.76 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:40:58 PM PDT 24
Peak memory 200236 kb
Host smart-7ba53b8a-011b-4c5a-b469-fe6f045c99c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450745279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3450745279
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1789424733
Short name T583
Test name
Test status
Simulation time 217413014 ps
CPU time 1.6 seconds
Started Jul 10 05:41:01 PM PDT 24
Finished Jul 10 05:41:03 PM PDT 24
Peak memory 200500 kb
Host smart-017a51d1-b210-44e6-9390-f45b1f970404
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789424733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1789424733
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3990156996
Short name T600
Test name
Test status
Simulation time 160786800 ps
CPU time 1.35 seconds
Started Jul 10 05:41:01 PM PDT 24
Finished Jul 10 05:41:03 PM PDT 24
Peak memory 200232 kb
Host smart-80b671bd-c7bd-422f-8e09-b50d04c022a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990156996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3990156996
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.645627030
Short name T117
Test name
Test status
Simulation time 426122488 ps
CPU time 1.71 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:41:00 PM PDT 24
Peak memory 200444 kb
Host smart-d41325e9-3d91-4deb-a01b-63f201fa578e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645627030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.645627030
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2400610997
Short name T580
Test name
Test status
Simulation time 106027207 ps
CPU time 0.93 seconds
Started Jul 10 05:41:00 PM PDT 24
Finished Jul 10 05:41:02 PM PDT 24
Peak memory 200304 kb
Host smart-10bc850a-905c-4e93-b3ce-9885b04ea7e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400610997 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2400610997
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.64836097
Short name T563
Test name
Test status
Simulation time 75743059 ps
CPU time 0.85 seconds
Started Jul 10 05:40:56 PM PDT 24
Finished Jul 10 05:40:58 PM PDT 24
Peak memory 200156 kb
Host smart-ff978000-d36e-44ff-827f-cdbd9dc13fb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64836097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.64836097
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1044637010
Short name T554
Test name
Test status
Simulation time 242607226 ps
CPU time 1.63 seconds
Started Jul 10 05:40:56 PM PDT 24
Finished Jul 10 05:40:58 PM PDT 24
Peak memory 200428 kb
Host smart-9e9fe927-fe3b-451c-9ed3-51e10c817bf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044637010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1044637010
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2777484571
Short name T112
Test name
Test status
Simulation time 161147508 ps
CPU time 2.21 seconds
Started Jul 10 05:40:58 PM PDT 24
Finished Jul 10 05:41:01 PM PDT 24
Peak memory 208584 kb
Host smart-f1bcfb80-875a-4751-bd23-678b452ada8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777484571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2777484571
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1254253655
Short name T129
Test name
Test status
Simulation time 465866488 ps
CPU time 2.11 seconds
Started Jul 10 05:40:57 PM PDT 24
Finished Jul 10 05:41:00 PM PDT 24
Peak memory 200440 kb
Host smart-f6c1ad5f-78d2-467e-bc53-2701dd65c1fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254253655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1254253655
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2892070948
Short name T611
Test name
Test status
Simulation time 178203632 ps
CPU time 1.22 seconds
Started Jul 10 05:41:02 PM PDT 24
Finished Jul 10 05:41:04 PM PDT 24
Peak memory 208412 kb
Host smart-463596d0-1ed1-4c76-b425-79c035030fcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892070948 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2892070948
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2059036633
Short name T108
Test name
Test status
Simulation time 66577508 ps
CPU time 0.8 seconds
Started Jul 10 05:41:02 PM PDT 24
Finished Jul 10 05:41:05 PM PDT 24
Peak memory 200252 kb
Host smart-e19bf82d-f552-41e5-9aeb-af5f0d0e23c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059036633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2059036633
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.104057786
Short name T604
Test name
Test status
Simulation time 278659329 ps
CPU time 1.68 seconds
Started Jul 10 05:41:02 PM PDT 24
Finished Jul 10 05:41:05 PM PDT 24
Peak memory 200432 kb
Host smart-52d9c343-c513-46e1-b19b-1edb26fa0fa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104057786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.104057786
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2903337956
Short name T569
Test name
Test status
Simulation time 176989291 ps
CPU time 1.47 seconds
Started Jul 10 05:41:03 PM PDT 24
Finished Jul 10 05:41:06 PM PDT 24
Peak memory 216564 kb
Host smart-150ad899-9c99-4340-aa69-ba2dc084db46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903337956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2903337956
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2245757459
Short name T619
Test name
Test status
Simulation time 785157785 ps
CPU time 3.22 seconds
Started Jul 10 05:41:01 PM PDT 24
Finished Jul 10 05:41:06 PM PDT 24
Peak memory 200440 kb
Host smart-b582d104-0c21-4145-b180-5bff20c8f57a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245757459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2245757459
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1576656383
Short name T93
Test name
Test status
Simulation time 167331721 ps
CPU time 1.21 seconds
Started Jul 10 05:41:03 PM PDT 24
Finished Jul 10 05:41:06 PM PDT 24
Peak memory 208560 kb
Host smart-7c447341-6923-4a77-aae4-e64607440359
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576656383 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1576656383
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1365269699
Short name T584
Test name
Test status
Simulation time 59491320 ps
CPU time 0.78 seconds
Started Jul 10 05:41:03 PM PDT 24
Finished Jul 10 05:41:06 PM PDT 24
Peak memory 200252 kb
Host smart-d3fd5229-5fb1-4472-9ae3-26771428c8c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365269699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1365269699
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1982782446
Short name T566
Test name
Test status
Simulation time 234481919 ps
CPU time 1.48 seconds
Started Jul 10 05:41:03 PM PDT 24
Finished Jul 10 05:41:06 PM PDT 24
Peak memory 200472 kb
Host smart-8376fe2e-cd34-4311-a740-550ea68ece66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982782446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1982782446
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.296301512
Short name T616
Test name
Test status
Simulation time 91285444 ps
CPU time 1.55 seconds
Started Jul 10 05:41:01 PM PDT 24
Finished Jul 10 05:41:04 PM PDT 24
Peak memory 200380 kb
Host smart-dae2c1e8-1b61-478f-a6c2-4d8475149c91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296301512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.296301512
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4083191393
Short name T90
Test name
Test status
Simulation time 421705773 ps
CPU time 1.81 seconds
Started Jul 10 05:41:02 PM PDT 24
Finished Jul 10 05:41:05 PM PDT 24
Peak memory 200420 kb
Host smart-4a02feb6-2e6d-42c5-adfc-2bc8866cac88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083191393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.4083191393
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2083669008
Short name T605
Test name
Test status
Simulation time 187189291 ps
CPU time 1.18 seconds
Started Jul 10 05:41:02 PM PDT 24
Finished Jul 10 05:41:05 PM PDT 24
Peak memory 209976 kb
Host smart-41227117-821c-444c-8f57-c232afd93021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083669008 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2083669008
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4123515799
Short name T103
Test name
Test status
Simulation time 74574238 ps
CPU time 0.89 seconds
Started Jul 10 05:41:01 PM PDT 24
Finished Jul 10 05:41:02 PM PDT 24
Peak memory 200236 kb
Host smart-073da921-cac9-487a-a901-d29c3da46017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123515799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4123515799
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.978520846
Short name T105
Test name
Test status
Simulation time 77943516 ps
CPU time 1.07 seconds
Started Jul 10 05:41:01 PM PDT 24
Finished Jul 10 05:41:03 PM PDT 24
Peak memory 200276 kb
Host smart-a8db0bb8-ca95-40fb-b137-eb7d1b88e014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978520846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.978520846
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1160516616
Short name T564
Test name
Test status
Simulation time 98773800 ps
CPU time 1.42 seconds
Started Jul 10 05:41:04 PM PDT 24
Finished Jul 10 05:41:06 PM PDT 24
Peak memory 208468 kb
Host smart-17e9502b-444c-4513-91a3-644b99fd29d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160516616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1160516616
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1115107683
Short name T114
Test name
Test status
Simulation time 429322775 ps
CPU time 1.97 seconds
Started Jul 10 05:41:01 PM PDT 24
Finished Jul 10 05:41:04 PM PDT 24
Peak memory 200452 kb
Host smart-b27b42b7-43a6-4edc-90c0-314ade4816df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115107683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1115107683
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2814813181
Short name T553
Test name
Test status
Simulation time 171739575 ps
CPU time 1.24 seconds
Started Jul 10 05:41:03 PM PDT 24
Finished Jul 10 05:41:06 PM PDT 24
Peak memory 208504 kb
Host smart-3cd0f609-9b7d-4044-8742-a4961c8fa3a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814813181 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2814813181
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1368922081
Short name T597
Test name
Test status
Simulation time 70205223 ps
CPU time 0.81 seconds
Started Jul 10 05:41:03 PM PDT 24
Finished Jul 10 05:41:05 PM PDT 24
Peak memory 200120 kb
Host smart-b762d22e-1abb-4e56-9494-89fe74c72f59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368922081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1368922081
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1008450802
Short name T581
Test name
Test status
Simulation time 131703184 ps
CPU time 1.11 seconds
Started Jul 10 05:41:01 PM PDT 24
Finished Jul 10 05:41:04 PM PDT 24
Peak memory 200296 kb
Host smart-528a263e-eb3f-4911-b9b6-19cc73f79e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008450802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1008450802
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1165307573
Short name T549
Test name
Test status
Simulation time 433710407 ps
CPU time 2.89 seconds
Started Jul 10 05:41:02 PM PDT 24
Finished Jul 10 05:41:07 PM PDT 24
Peak memory 208580 kb
Host smart-bb07a57c-8d6d-41f1-be66-8c911c9ad8d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165307573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1165307573
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4168193852
Short name T572
Test name
Test status
Simulation time 355995265 ps
CPU time 2.49 seconds
Started Jul 10 05:40:41 PM PDT 24
Finished Jul 10 05:40:44 PM PDT 24
Peak memory 200232 kb
Host smart-f65a8d9e-3112-4c84-b016-768a29f01473
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168193852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.4
168193852
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.317398448
Short name T548
Test name
Test status
Simulation time 1172120085 ps
CPU time 5.93 seconds
Started Jul 10 05:40:40 PM PDT 24
Finished Jul 10 05:40:46 PM PDT 24
Peak memory 200396 kb
Host smart-4e2b5728-b413-4654-88ca-1c724afba813
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317398448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.317398448
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1136876535
Short name T541
Test name
Test status
Simulation time 90538731 ps
CPU time 0.83 seconds
Started Jul 10 05:40:40 PM PDT 24
Finished Jul 10 05:40:42 PM PDT 24
Peak memory 200292 kb
Host smart-fc8f8ac7-c6fe-474c-abe0-ea3bf3419aec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136876535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
136876535
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2756927298
Short name T575
Test name
Test status
Simulation time 101358395 ps
CPU time 0.9 seconds
Started Jul 10 05:40:42 PM PDT 24
Finished Jul 10 05:40:44 PM PDT 24
Peak memory 200360 kb
Host smart-b5fbe692-f822-4ac1-847a-c95def105613
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756927298 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2756927298
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3671382838
Short name T558
Test name
Test status
Simulation time 80615416 ps
CPU time 0.81 seconds
Started Jul 10 05:40:42 PM PDT 24
Finished Jul 10 05:40:44 PM PDT 24
Peak memory 200236 kb
Host smart-0719754e-d249-4e83-8713-67a227a52b96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671382838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3671382838
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3425934854
Short name T111
Test name
Test status
Simulation time 213402893 ps
CPU time 1.54 seconds
Started Jul 10 05:40:40 PM PDT 24
Finished Jul 10 05:40:42 PM PDT 24
Peak memory 200400 kb
Host smart-2aa068b7-7551-4c62-ad16-b35d9e1bf392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425934854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3425934854
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1598583947
Short name T595
Test name
Test status
Simulation time 233986340 ps
CPU time 2.01 seconds
Started Jul 10 05:40:34 PM PDT 24
Finished Jul 10 05:40:37 PM PDT 24
Peak memory 208636 kb
Host smart-472ed700-13cd-4076-a44f-592e0c7391aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598583947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1598583947
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1767257714
Short name T128
Test name
Test status
Simulation time 429111777 ps
CPU time 1.97 seconds
Started Jul 10 05:40:38 PM PDT 24
Finished Jul 10 05:40:40 PM PDT 24
Peak memory 200444 kb
Host smart-dde1c9ff-cc5e-45f1-a4c3-ea9d848139b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767257714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1767257714
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3885651055
Short name T545
Test name
Test status
Simulation time 258446048 ps
CPU time 1.65 seconds
Started Jul 10 05:40:45 PM PDT 24
Finished Jul 10 05:40:48 PM PDT 24
Peak memory 200396 kb
Host smart-1c736b22-2735-44cf-ae74-537eebaa607f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885651055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
885651055
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2350400057
Short name T598
Test name
Test status
Simulation time 1980168616 ps
CPU time 9.12 seconds
Started Jul 10 05:40:40 PM PDT 24
Finished Jul 10 05:40:49 PM PDT 24
Peak memory 200380 kb
Host smart-84c92880-09a5-4714-99e0-129eae0157e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350400057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
350400057
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1194861291
Short name T543
Test name
Test status
Simulation time 138117236 ps
CPU time 0.93 seconds
Started Jul 10 05:40:40 PM PDT 24
Finished Jul 10 05:40:42 PM PDT 24
Peak memory 200152 kb
Host smart-92fc51cc-c153-47c9-8ead-fe021bd913e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194861291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
194861291
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1228199197
Short name T69
Test name
Test status
Simulation time 114820075 ps
CPU time 0.98 seconds
Started Jul 10 05:40:46 PM PDT 24
Finished Jul 10 05:40:48 PM PDT 24
Peak memory 200260 kb
Host smart-061c7b51-b453-4c20-9766-edc3146333c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228199197 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1228199197
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3428222214
Short name T546
Test name
Test status
Simulation time 63272478 ps
CPU time 0.8 seconds
Started Jul 10 05:40:42 PM PDT 24
Finished Jul 10 05:40:43 PM PDT 24
Peak memory 200168 kb
Host smart-73809688-ba26-4254-b140-4ae0b03b5360
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428222214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3428222214
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4171677975
Short name T110
Test name
Test status
Simulation time 84036042 ps
CPU time 0.91 seconds
Started Jul 10 05:40:48 PM PDT 24
Finished Jul 10 05:40:50 PM PDT 24
Peak memory 200544 kb
Host smart-caabda9e-8f5f-4b0e-9c42-cfc973f61b18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171677975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4171677975
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2288575606
Short name T608
Test name
Test status
Simulation time 319735163 ps
CPU time 2.48 seconds
Started Jul 10 05:40:40 PM PDT 24
Finished Jul 10 05:40:44 PM PDT 24
Peak memory 208552 kb
Host smart-5dbdd3fb-e1c7-4a6f-b312-411a6d4950fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288575606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2288575606
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3980960141
Short name T63
Test name
Test status
Simulation time 891278542 ps
CPU time 2.93 seconds
Started Jul 10 05:40:39 PM PDT 24
Finished Jul 10 05:40:42 PM PDT 24
Peak memory 200692 kb
Host smart-3de7fcf4-1419-412c-80ff-fe352f703eea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980960141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3980960141
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2507564545
Short name T588
Test name
Test status
Simulation time 155147530 ps
CPU time 2.04 seconds
Started Jul 10 05:40:47 PM PDT 24
Finished Jul 10 05:40:50 PM PDT 24
Peak memory 200308 kb
Host smart-2a21f6dd-39a2-4f64-9cda-4ecbad4305e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507564545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
507564545
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1878899015
Short name T596
Test name
Test status
Simulation time 268370720 ps
CPU time 3.37 seconds
Started Jul 10 05:40:46 PM PDT 24
Finished Jul 10 05:40:51 PM PDT 24
Peak memory 200432 kb
Host smart-2f4b5c47-3d45-458c-8939-343e8f230a13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878899015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
878899015
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2483699579
Short name T560
Test name
Test status
Simulation time 90439884 ps
CPU time 0.79 seconds
Started Jul 10 05:40:48 PM PDT 24
Finished Jul 10 05:40:50 PM PDT 24
Peak memory 200164 kb
Host smart-4a3db66f-26d6-449e-a9a5-08616ed05c28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483699579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
483699579
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2021656988
Short name T613
Test name
Test status
Simulation time 195121248 ps
CPU time 2.06 seconds
Started Jul 10 05:40:44 PM PDT 24
Finished Jul 10 05:40:47 PM PDT 24
Peak memory 208604 kb
Host smart-e4846c9d-c6b9-45fb-b4b2-2313a67e0e1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021656988 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2021656988
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3394963158
Short name T107
Test name
Test status
Simulation time 60695048 ps
CPU time 0.81 seconds
Started Jul 10 05:40:45 PM PDT 24
Finished Jul 10 05:40:46 PM PDT 24
Peak memory 200236 kb
Host smart-1d32570d-4af9-4f27-897a-2f8225d1b592
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394963158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3394963158
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1290420645
Short name T551
Test name
Test status
Simulation time 137369369 ps
CPU time 1.14 seconds
Started Jul 10 05:40:46 PM PDT 24
Finished Jul 10 05:40:48 PM PDT 24
Peak memory 200296 kb
Host smart-eff80ecf-8290-4e28-bb09-eb6ea8d3b2cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290420645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1290420645
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3826022531
Short name T118
Test name
Test status
Simulation time 299495319 ps
CPU time 2.34 seconds
Started Jul 10 05:40:48 PM PDT 24
Finished Jul 10 05:40:51 PM PDT 24
Peak memory 216540 kb
Host smart-39c17d84-671b-479c-a4ad-e81e1e2f9f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826022531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3826022531
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2573968998
Short name T582
Test name
Test status
Simulation time 425734600 ps
CPU time 1.92 seconds
Started Jul 10 05:40:47 PM PDT 24
Finished Jul 10 05:40:50 PM PDT 24
Peak memory 200452 kb
Host smart-aa0cb66f-bd33-4ea2-9003-8b2dcc29851a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573968998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2573968998
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2182931754
Short name T109
Test name
Test status
Simulation time 74193132 ps
CPU time 0.84 seconds
Started Jul 10 05:40:46 PM PDT 24
Finished Jul 10 05:40:48 PM PDT 24
Peak memory 200144 kb
Host smart-0ca3fabf-f3d3-4837-9cb5-afe6d3be4a38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182931754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2182931754
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2782888878
Short name T590
Test name
Test status
Simulation time 223122350 ps
CPU time 1.45 seconds
Started Jul 10 05:40:44 PM PDT 24
Finished Jul 10 05:40:46 PM PDT 24
Peak memory 200420 kb
Host smart-c470f05b-1795-4c7d-a1dd-2d33a5097fdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782888878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2782888878
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1533044882
Short name T606
Test name
Test status
Simulation time 503114528 ps
CPU time 3.34 seconds
Started Jul 10 05:40:46 PM PDT 24
Finished Jul 10 05:40:50 PM PDT 24
Peak memory 216588 kb
Host smart-63e73ddd-f957-4506-9140-0d3598fa71a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533044882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1533044882
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.64634884
Short name T593
Test name
Test status
Simulation time 913912375 ps
CPU time 3.19 seconds
Started Jul 10 05:40:45 PM PDT 24
Finished Jul 10 05:40:49 PM PDT 24
Peak memory 200528 kb
Host smart-9e4c3880-4ada-437e-84cb-2e5f76c35328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64634884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.64634884
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3775977723
Short name T113
Test name
Test status
Simulation time 113902210 ps
CPU time 1.3 seconds
Started Jul 10 05:40:45 PM PDT 24
Finished Jul 10 05:40:48 PM PDT 24
Peak memory 208460 kb
Host smart-6d06bb7a-97e1-4918-91bb-c67df2f16848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775977723 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3775977723
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.635075738
Short name T570
Test name
Test status
Simulation time 67573656 ps
CPU time 0.79 seconds
Started Jul 10 05:40:46 PM PDT 24
Finished Jul 10 05:40:48 PM PDT 24
Peak memory 200232 kb
Host smart-0eca0351-31a0-4b55-ba08-ae43b7e95b39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635075738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.635075738
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1844220026
Short name T603
Test name
Test status
Simulation time 110995414 ps
CPU time 1.36 seconds
Started Jul 10 05:40:45 PM PDT 24
Finished Jul 10 05:40:48 PM PDT 24
Peak memory 200428 kb
Host smart-eac4d48a-3ddb-4781-a8a4-63cdc6f55a71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844220026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1844220026
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1700886011
Short name T609
Test name
Test status
Simulation time 154991375 ps
CPU time 1.3 seconds
Started Jul 10 05:40:45 PM PDT 24
Finished Jul 10 05:40:47 PM PDT 24
Peak memory 208428 kb
Host smart-ca2e45fc-de9e-4bfb-8540-3ec5fb2e7f81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700886011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1700886011
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.938544695
Short name T561
Test name
Test status
Simulation time 489737964 ps
CPU time 1.9 seconds
Started Jul 10 05:40:45 PM PDT 24
Finished Jul 10 05:40:48 PM PDT 24
Peak memory 200412 kb
Host smart-862d6581-3a81-4c6f-b612-bf6d2d721797
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938544695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
938544695
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2265122274
Short name T68
Test name
Test status
Simulation time 198403816 ps
CPU time 1.38 seconds
Started Jul 10 05:40:50 PM PDT 24
Finished Jul 10 05:40:53 PM PDT 24
Peak memory 208576 kb
Host smart-7f1ef383-0e3f-45d3-a413-04489f068575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265122274 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2265122274
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.176109956
Short name T552
Test name
Test status
Simulation time 64617780 ps
CPU time 0.78 seconds
Started Jul 10 05:40:47 PM PDT 24
Finished Jul 10 05:40:49 PM PDT 24
Peak memory 200072 kb
Host smart-7b154bd9-77ab-48af-bd35-dc48ed885511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176109956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.176109956
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2822470089
Short name T607
Test name
Test status
Simulation time 81863127 ps
CPU time 0.95 seconds
Started Jul 10 05:40:50 PM PDT 24
Finished Jul 10 05:40:53 PM PDT 24
Peak memory 200296 kb
Host smart-f0a228a6-d95d-4a26-abeb-b555f3bdde5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822470089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2822470089
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3956956765
Short name T67
Test name
Test status
Simulation time 316819896 ps
CPU time 2.29 seconds
Started Jul 10 05:40:45 PM PDT 24
Finished Jul 10 05:40:48 PM PDT 24
Peak memory 208620 kb
Host smart-453fbfda-74f5-4e6e-bc41-fdfd213543c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956956765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3956956765
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2868089749
Short name T602
Test name
Test status
Simulation time 429163953 ps
CPU time 1.75 seconds
Started Jul 10 05:40:47 PM PDT 24
Finished Jul 10 05:40:50 PM PDT 24
Peak memory 200352 kb
Host smart-4104894d-4107-4941-a382-199a50ede1df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868089749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2868089749
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2576176236
Short name T579
Test name
Test status
Simulation time 126154343 ps
CPU time 1.03 seconds
Started Jul 10 05:40:50 PM PDT 24
Finished Jul 10 05:40:52 PM PDT 24
Peak memory 200384 kb
Host smart-a6bc1061-8517-48da-b3d7-3aaea545c332
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576176236 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2576176236
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3153194883
Short name T547
Test name
Test status
Simulation time 64700261 ps
CPU time 0.78 seconds
Started Jul 10 05:40:52 PM PDT 24
Finished Jul 10 05:40:54 PM PDT 24
Peak memory 200140 kb
Host smart-36a706d2-e28c-469a-a2c8-0156502fa4d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153194883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3153194883
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2061318295
Short name T102
Test name
Test status
Simulation time 94907462 ps
CPU time 1.35 seconds
Started Jul 10 05:40:50 PM PDT 24
Finished Jul 10 05:40:52 PM PDT 24
Peak memory 200448 kb
Host smart-dc8a0e49-25f3-4e5e-9971-68ecc056009e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061318295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2061318295
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1474308158
Short name T116
Test name
Test status
Simulation time 915920829 ps
CPU time 3.26 seconds
Started Jul 10 05:40:51 PM PDT 24
Finished Jul 10 05:40:56 PM PDT 24
Peak memory 200364 kb
Host smart-fb9c1493-5919-4369-9b6e-689d2baa4796
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474308158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1474308158
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.857855575
Short name T555
Test name
Test status
Simulation time 115038880 ps
CPU time 0.98 seconds
Started Jul 10 05:40:53 PM PDT 24
Finished Jul 10 05:40:55 PM PDT 24
Peak memory 200372 kb
Host smart-6f2adb09-8286-4dd3-9fdc-d81ce06c65b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857855575 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.857855575
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1691279810
Short name T589
Test name
Test status
Simulation time 84863873 ps
CPU time 0.83 seconds
Started Jul 10 05:40:51 PM PDT 24
Finished Jul 10 05:40:53 PM PDT 24
Peak memory 200220 kb
Host smart-78a1a582-647a-4cf6-8c16-ec4dad77d549
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691279810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1691279810
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.140293973
Short name T104
Test name
Test status
Simulation time 82873639 ps
CPU time 1 seconds
Started Jul 10 05:40:51 PM PDT 24
Finished Jul 10 05:40:54 PM PDT 24
Peak memory 200544 kb
Host smart-b26be75c-1712-4d0b-a79f-2cd5732df339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140293973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.140293973
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4182358515
Short name T576
Test name
Test status
Simulation time 389570069 ps
CPU time 2.88 seconds
Started Jul 10 05:40:50 PM PDT 24
Finished Jul 10 05:40:55 PM PDT 24
Peak memory 208544 kb
Host smart-ba6edb5a-2ab8-4a3f-8ef3-809419212103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182358515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4182358515
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4208290608
Short name T591
Test name
Test status
Simulation time 507626021 ps
CPU time 2.13 seconds
Started Jul 10 05:40:53 PM PDT 24
Finished Jul 10 05:40:56 PM PDT 24
Peak memory 200468 kb
Host smart-98c7e1f8-ac7f-40b6-ac1b-d01f918c5d53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208290608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.4208290608
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3774044694
Short name T537
Test name
Test status
Simulation time 86954059 ps
CPU time 0.85 seconds
Started Jul 10 07:19:45 PM PDT 24
Finished Jul 10 07:19:50 PM PDT 24
Peak memory 199952 kb
Host smart-9ce56ec9-4ffc-4df4-88b5-0ff22e5caff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774044694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3774044694
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3534342515
Short name T29
Test name
Test status
Simulation time 1222323601 ps
CPU time 6 seconds
Started Jul 10 07:19:40 PM PDT 24
Finished Jul 10 07:19:48 PM PDT 24
Peak memory 221644 kb
Host smart-e4c9f97f-f690-4471-9cae-d36e3726e296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534342515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3534342515
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2852542657
Short name T410
Test name
Test status
Simulation time 243780759 ps
CPU time 1.12 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:19:49 PM PDT 24
Peak memory 216976 kb
Host smart-277f9756-56e7-4f90-8119-61186b6791de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852542657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2852542657
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.474395799
Short name T121
Test name
Test status
Simulation time 2058887545 ps
CPU time 8.29 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:19:56 PM PDT 24
Peak memory 200432 kb
Host smart-7b0990bb-e6e9-47d8-9f3b-8637c9a50a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474395799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.474395799
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3057671530
Short name T255
Test name
Test status
Simulation time 238945403 ps
CPU time 1.49 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:19:48 PM PDT 24
Peak memory 200348 kb
Host smart-cbb5abd1-82aa-48d4-8c86-f9e640008fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057671530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3057671530
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1889950620
Short name T465
Test name
Test status
Simulation time 10319032984 ps
CPU time 33.45 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:20:20 PM PDT 24
Peak memory 200512 kb
Host smart-3530ea02-c0f3-4f9b-b145-1c61c51b7ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889950620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1889950620
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3849521357
Short name T433
Test name
Test status
Simulation time 351415187 ps
CPU time 2.37 seconds
Started Jul 10 07:19:44 PM PDT 24
Finished Jul 10 07:19:51 PM PDT 24
Peak memory 200188 kb
Host smart-ad51cfa5-0026-4a42-9f52-c401632d0fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849521357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3849521357
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3973670334
Short name T263
Test name
Test status
Simulation time 66814836 ps
CPU time 0.84 seconds
Started Jul 10 07:19:41 PM PDT 24
Finished Jul 10 07:19:43 PM PDT 24
Peak memory 200156 kb
Host smart-3a2c4e62-da37-4314-b240-a65b43b96010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973670334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3973670334
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1370857790
Short name T290
Test name
Test status
Simulation time 63372941 ps
CPU time 0.74 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:19:48 PM PDT 24
Peak memory 199964 kb
Host smart-e2770d2a-fc4e-41de-a13c-d967477054fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370857790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1370857790
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3567819520
Short name T519
Test name
Test status
Simulation time 2352215168 ps
CPU time 8.27 seconds
Started Jul 10 07:19:45 PM PDT 24
Finished Jul 10 07:19:58 PM PDT 24
Peak memory 217964 kb
Host smart-45606854-a817-4413-b48a-daa26afc9b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567819520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3567819520
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.272518911
Short name T384
Test name
Test status
Simulation time 244575057 ps
CPU time 1.09 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:19:49 PM PDT 24
Peak memory 217072 kb
Host smart-826c6dfc-4e69-4a08-a5ba-d073cd33f9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272518911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.272518911
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3242606198
Short name T182
Test name
Test status
Simulation time 227943765 ps
CPU time 0.93 seconds
Started Jul 10 07:19:42 PM PDT 24
Finished Jul 10 07:19:47 PM PDT 24
Peak memory 199980 kb
Host smart-8e42242a-8413-427e-9de3-593be417fd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242606198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3242606198
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.949781087
Short name T364
Test name
Test status
Simulation time 1376880463 ps
CPU time 5.52 seconds
Started Jul 10 07:19:44 PM PDT 24
Finished Jul 10 07:19:54 PM PDT 24
Peak memory 200488 kb
Host smart-1658ae6c-9fe0-48fe-990d-fe3dccea04b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949781087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.949781087
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2420473384
Short name T72
Test name
Test status
Simulation time 20758165047 ps
CPU time 32.44 seconds
Started Jul 10 07:19:44 PM PDT 24
Finished Jul 10 07:20:22 PM PDT 24
Peak memory 217672 kb
Host smart-68575d80-54f9-4b6c-99ab-1798dfb4c8ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420473384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2420473384
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.445787782
Short name T474
Test name
Test status
Simulation time 173499127 ps
CPU time 1.19 seconds
Started Jul 10 07:19:42 PM PDT 24
Finished Jul 10 07:19:46 PM PDT 24
Peak memory 200172 kb
Host smart-9ab2f785-c827-4bef-97cb-cb754a7a37f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445787782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.445787782
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1414393364
Short name T406
Test name
Test status
Simulation time 121942681 ps
CPU time 1.27 seconds
Started Jul 10 07:19:44 PM PDT 24
Finished Jul 10 07:19:50 PM PDT 24
Peak memory 200368 kb
Host smart-86293ca2-bc62-40dc-8a78-9050b865d7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414393364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1414393364
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2434905060
Short name T62
Test name
Test status
Simulation time 11372372788 ps
CPU time 40.95 seconds
Started Jul 10 07:19:45 PM PDT 24
Finished Jul 10 07:20:31 PM PDT 24
Peak memory 208672 kb
Host smart-1388d420-4997-4a18-82e0-c71d09c96e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434905060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2434905060
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3433794042
Short name T279
Test name
Test status
Simulation time 528776813 ps
CPU time 3.02 seconds
Started Jul 10 07:19:45 PM PDT 24
Finished Jul 10 07:19:52 PM PDT 24
Peak memory 200360 kb
Host smart-d79f3f82-20b7-4b7f-bc2b-3054f2d421ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433794042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3433794042
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.159253118
Short name T535
Test name
Test status
Simulation time 97605488 ps
CPU time 0.88 seconds
Started Jul 10 07:19:44 PM PDT 24
Finished Jul 10 07:19:50 PM PDT 24
Peak memory 200176 kb
Host smart-cf5833a7-dad0-4a66-b693-6f256dd5c7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159253118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.159253118
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3555892297
Short name T539
Test name
Test status
Simulation time 68325820 ps
CPU time 0.81 seconds
Started Jul 10 07:20:19 PM PDT 24
Finished Jul 10 07:20:23 PM PDT 24
Peak memory 199952 kb
Host smart-59311d4b-1806-45a0-bf3a-c20511f20354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555892297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3555892297
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2320806498
Short name T218
Test name
Test status
Simulation time 2177501107 ps
CPU time 7.63 seconds
Started Jul 10 07:20:13 PM PDT 24
Finished Jul 10 07:20:22 PM PDT 24
Peak memory 217924 kb
Host smart-b940824a-d91f-4f0b-a5a9-a04d769afa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320806498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2320806498
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.447003515
Short name T425
Test name
Test status
Simulation time 245317662 ps
CPU time 1.07 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:20 PM PDT 24
Peak memory 217468 kb
Host smart-c6a0521d-ce9a-449e-9fe2-a596e6b8f88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447003515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.447003515
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3032814151
Short name T152
Test name
Test status
Simulation time 223913269 ps
CPU time 0.94 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:20 PM PDT 24
Peak memory 199972 kb
Host smart-62c69351-251a-4850-8c7b-995fd8579791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032814151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3032814151
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3358862172
Short name T154
Test name
Test status
Simulation time 1511427061 ps
CPU time 5.82 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:25 PM PDT 24
Peak memory 200532 kb
Host smart-45e95360-dd20-418b-be0d-dc95b214f8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358862172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3358862172
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2668644718
Short name T216
Test name
Test status
Simulation time 145772749 ps
CPU time 1.14 seconds
Started Jul 10 07:20:14 PM PDT 24
Finished Jul 10 07:20:17 PM PDT 24
Peak memory 200160 kb
Host smart-53e3e38e-ecce-4f49-9858-c7bd68f19d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668644718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2668644718
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.656550382
Short name T378
Test name
Test status
Simulation time 192666713 ps
CPU time 1.4 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:21 PM PDT 24
Peak memory 200348 kb
Host smart-e9d723be-3ed0-4e05-8e88-629472f61146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656550382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.656550382
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3300111305
Short name T252
Test name
Test status
Simulation time 966992635 ps
CPU time 3.98 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:23 PM PDT 24
Peak memory 200348 kb
Host smart-cad96553-fe6f-4dcf-937d-79e47548e4c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300111305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3300111305
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1744143747
Short name T329
Test name
Test status
Simulation time 271161086 ps
CPU time 1.91 seconds
Started Jul 10 07:20:13 PM PDT 24
Finished Jul 10 07:20:17 PM PDT 24
Peak memory 200152 kb
Host smart-f73745c1-0b91-41cb-9c8c-ae4c532133fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744143747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1744143747
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2255036423
Short name T533
Test name
Test status
Simulation time 121523284 ps
CPU time 1.1 seconds
Started Jul 10 07:20:14 PM PDT 24
Finished Jul 10 07:20:17 PM PDT 24
Peak memory 200156 kb
Host smart-45c64948-16a6-4386-afd1-4a96126a91e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255036423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2255036423
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2466948615
Short name T517
Test name
Test status
Simulation time 74483624 ps
CPU time 0.81 seconds
Started Jul 10 07:20:14 PM PDT 24
Finished Jul 10 07:20:17 PM PDT 24
Peak memory 199952 kb
Host smart-ec1ccae5-4c1e-4fd9-8ff3-626fa0e04332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466948615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2466948615
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2095576758
Short name T57
Test name
Test status
Simulation time 2351055358 ps
CPU time 8.21 seconds
Started Jul 10 07:20:14 PM PDT 24
Finished Jul 10 07:20:25 PM PDT 24
Peak memory 217952 kb
Host smart-10c55856-c161-4012-a1b6-e44d9e77c731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095576758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2095576758
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3095909408
Short name T502
Test name
Test status
Simulation time 243619964 ps
CPU time 1.15 seconds
Started Jul 10 07:20:15 PM PDT 24
Finished Jul 10 07:20:19 PM PDT 24
Peak memory 217540 kb
Host smart-c289ed69-889e-4d3d-9628-f03fbe4c525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095909408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3095909408
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1582896182
Short name T259
Test name
Test status
Simulation time 158290626 ps
CPU time 0.9 seconds
Started Jul 10 07:20:14 PM PDT 24
Finished Jul 10 07:20:17 PM PDT 24
Peak memory 199984 kb
Host smart-fdb36d9e-dc55-49bf-bd18-e7f5aa57a52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582896182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1582896182
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2629159746
Short name T155
Test name
Test status
Simulation time 1571075651 ps
CPU time 6.62 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:27 PM PDT 24
Peak memory 200532 kb
Host smart-a2b8f7ed-4a84-432a-b469-9c04a5635808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629159746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2629159746
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1076987624
Short name T327
Test name
Test status
Simulation time 184622859 ps
CPU time 1.31 seconds
Started Jul 10 07:20:15 PM PDT 24
Finished Jul 10 07:20:19 PM PDT 24
Peak memory 200164 kb
Host smart-6474d9a8-5afa-47e8-a89c-ed24c16fa971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076987624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1076987624
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1412736048
Short name T36
Test name
Test status
Simulation time 114199894 ps
CPU time 1.2 seconds
Started Jul 10 07:20:19 PM PDT 24
Finished Jul 10 07:20:23 PM PDT 24
Peak memory 199580 kb
Host smart-eeb433d1-693d-4e51-9927-b3d51eb48509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412736048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1412736048
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2173031519
Short name T76
Test name
Test status
Simulation time 4405988501 ps
CPU time 19.78 seconds
Started Jul 10 07:20:14 PM PDT 24
Finished Jul 10 07:20:36 PM PDT 24
Peak memory 208652 kb
Host smart-9cfa474a-930e-4cca-b769-851ce0cd3e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173031519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2173031519
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2755626389
Short name T181
Test name
Test status
Simulation time 304079354 ps
CPU time 2.14 seconds
Started Jul 10 07:20:13 PM PDT 24
Finished Jul 10 07:20:17 PM PDT 24
Peak memory 208348 kb
Host smart-d1f8510a-07e4-40e6-9f86-01dbe7b30289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755626389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2755626389
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3600940847
Short name T349
Test name
Test status
Simulation time 107743147 ps
CPU time 0.92 seconds
Started Jul 10 07:20:12 PM PDT 24
Finished Jul 10 07:20:14 PM PDT 24
Peak memory 200188 kb
Host smart-7c4d214b-6165-46b3-90a2-abd791983a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600940847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3600940847
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3053381438
Short name T396
Test name
Test status
Simulation time 66063335 ps
CPU time 0.76 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:20 PM PDT 24
Peak memory 199952 kb
Host smart-f5e7542d-7621-47d2-8683-b3de2977943c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053381438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3053381438
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3682554451
Short name T478
Test name
Test status
Simulation time 2349012824 ps
CPU time 9.08 seconds
Started Jul 10 07:20:13 PM PDT 24
Finished Jul 10 07:20:23 PM PDT 24
Peak memory 218032 kb
Host smart-ea7f6697-f65a-4f86-a2ce-d7fe24980af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682554451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3682554451
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.563059890
Short name T83
Test name
Test status
Simulation time 244780510 ps
CPU time 1.13 seconds
Started Jul 10 07:20:13 PM PDT 24
Finished Jul 10 07:20:17 PM PDT 24
Peak memory 217528 kb
Host smart-da06b3fd-73fc-4cd8-9ea0-8ee7d252884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563059890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.563059890
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3611981695
Short name T369
Test name
Test status
Simulation time 200655981 ps
CPU time 0.93 seconds
Started Jul 10 07:20:14 PM PDT 24
Finished Jul 10 07:20:16 PM PDT 24
Peak memory 200040 kb
Host smart-718debd2-c463-41ce-94f9-6223100866a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611981695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3611981695
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.532779489
Short name T195
Test name
Test status
Simulation time 701751296 ps
CPU time 4.07 seconds
Started Jul 10 07:20:15 PM PDT 24
Finished Jul 10 07:20:23 PM PDT 24
Peak memory 200412 kb
Host smart-e4011080-fcab-48ce-99f8-36769665fb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532779489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.532779489
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1939770630
Short name T243
Test name
Test status
Simulation time 145744920 ps
CPU time 1.22 seconds
Started Jul 10 07:20:19 PM PDT 24
Finished Jul 10 07:20:23 PM PDT 24
Peak memory 200160 kb
Host smart-5d85c5c4-b2cf-4556-88f5-53a87da31674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939770630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1939770630
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2199907272
Short name T219
Test name
Test status
Simulation time 265399242 ps
CPU time 1.6 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:21 PM PDT 24
Peak memory 200348 kb
Host smart-1a82e39e-5830-4ab0-b033-668229c3ee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199907272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2199907272
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.61268112
Short name T282
Test name
Test status
Simulation time 7840793673 ps
CPU time 27.99 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:48 PM PDT 24
Peak memory 208684 kb
Host smart-a9f617ce-6b50-42ef-9a12-eacd898e4b02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61268112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.61268112
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1341080833
Short name T184
Test name
Test status
Simulation time 137954610 ps
CPU time 1.74 seconds
Started Jul 10 07:20:13 PM PDT 24
Finished Jul 10 07:20:16 PM PDT 24
Peak memory 200168 kb
Host smart-c66866aa-afbd-407f-b597-903818e57547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341080833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1341080833
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.311449568
Short name T387
Test name
Test status
Simulation time 297112276 ps
CPU time 1.65 seconds
Started Jul 10 07:20:15 PM PDT 24
Finished Jul 10 07:20:19 PM PDT 24
Peak memory 200320 kb
Host smart-118842f7-1da7-46ed-af3a-d59cd87a2527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311449568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.311449568
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3155752308
Short name T59
Test name
Test status
Simulation time 1233116098 ps
CPU time 5.94 seconds
Started Jul 10 07:20:19 PM PDT 24
Finished Jul 10 07:20:28 PM PDT 24
Peak memory 217656 kb
Host smart-6036ebe9-1804-4090-8c12-cc3256452cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155752308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3155752308
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2135799538
Short name T170
Test name
Test status
Simulation time 243981950 ps
CPU time 1.08 seconds
Started Jul 10 07:20:15 PM PDT 24
Finished Jul 10 07:20:19 PM PDT 24
Peak memory 217500 kb
Host smart-8ca185d0-ab94-430f-910f-de900143e09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135799538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2135799538
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2661040821
Short name T189
Test name
Test status
Simulation time 87527413 ps
CPU time 0.8 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:20 PM PDT 24
Peak memory 199972 kb
Host smart-008f77a4-b0ee-43e1-9db7-4de4d1e3225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661040821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2661040821
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3343093276
Short name T312
Test name
Test status
Simulation time 1648637167 ps
CPU time 6.29 seconds
Started Jul 10 07:20:13 PM PDT 24
Finished Jul 10 07:20:21 PM PDT 24
Peak memory 200464 kb
Host smart-c2fbae0d-aa3d-4910-b052-0062a715fec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343093276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3343093276
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.150208215
Short name T194
Test name
Test status
Simulation time 178857413 ps
CPU time 1.21 seconds
Started Jul 10 07:20:14 PM PDT 24
Finished Jul 10 07:20:18 PM PDT 24
Peak memory 200096 kb
Host smart-66ef054d-fc8c-464f-92b7-5bb801ff4b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150208215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.150208215
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3965464504
Short name T381
Test name
Test status
Simulation time 4346069962 ps
CPU time 16 seconds
Started Jul 10 07:20:15 PM PDT 24
Finished Jul 10 07:20:34 PM PDT 24
Peak memory 200524 kb
Host smart-1e2cf447-b1eb-416e-af29-9e9d302f0701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965464504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3965464504
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2322069739
Short name T306
Test name
Test status
Simulation time 392742175 ps
CPU time 2.6 seconds
Started Jul 10 07:20:13 PM PDT 24
Finished Jul 10 07:20:18 PM PDT 24
Peak memory 200164 kb
Host smart-88044889-16fd-4deb-a6a9-55cdc3261741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322069739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2322069739
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3198178346
Short name T162
Test name
Test status
Simulation time 83987878 ps
CPU time 0.9 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:37 PM PDT 24
Peak memory 199952 kb
Host smart-1f8b3e1b-6368-487d-b18c-8a14395b9d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198178346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3198178346
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.204537547
Short name T332
Test name
Test status
Simulation time 2368375707 ps
CPU time 8.54 seconds
Started Jul 10 07:20:30 PM PDT 24
Finished Jul 10 07:20:40 PM PDT 24
Peak memory 217876 kb
Host smart-f2668208-499a-4c61-958a-a738852aa875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204537547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.204537547
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3949059037
Short name T416
Test name
Test status
Simulation time 244041686 ps
CPU time 1.04 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:35 PM PDT 24
Peak memory 217532 kb
Host smart-9b59ba58-1296-4929-9a9f-d3e4e3c6cac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949059037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3949059037
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3623765220
Short name T513
Test name
Test status
Simulation time 111238180 ps
CPU time 0.77 seconds
Started Jul 10 07:20:31 PM PDT 24
Finished Jul 10 07:20:33 PM PDT 24
Peak memory 199972 kb
Host smart-04d23ce6-da95-412b-b4e1-5d2e2d54e674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623765220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3623765220
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.4238891797
Short name T509
Test name
Test status
Simulation time 697622372 ps
CPU time 3.79 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:38 PM PDT 24
Peak memory 200400 kb
Host smart-040a029b-08cf-4a46-971b-8acf1043e0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238891797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4238891797
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2392677651
Short name T161
Test name
Test status
Simulation time 106648196 ps
CPU time 1.02 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:37 PM PDT 24
Peak memory 200168 kb
Host smart-948b94c8-6596-4dbb-a62f-3bcabe368778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392677651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2392677651
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3849956911
Short name T458
Test name
Test status
Simulation time 197946329 ps
CPU time 1.39 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:35 PM PDT 24
Peak memory 200348 kb
Host smart-b1b0b0ad-16f1-4068-a7ca-26adb4356677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849956911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3849956911
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3942830133
Short name T100
Test name
Test status
Simulation time 6229409339 ps
CPU time 20.57 seconds
Started Jul 10 07:20:29 PM PDT 24
Finished Jul 10 07:20:51 PM PDT 24
Peak memory 200428 kb
Host smart-f0c1955e-1053-40d5-911e-6ea0f29801c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942830133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3942830133
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3658138210
Short name T435
Test name
Test status
Simulation time 138109168 ps
CPU time 1.79 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:38 PM PDT 24
Peak memory 200160 kb
Host smart-abf5f9ba-df61-45fe-922b-2b28b156f3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658138210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3658138210
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1059149939
Short name T430
Test name
Test status
Simulation time 67287209 ps
CPU time 0.81 seconds
Started Jul 10 07:20:34 PM PDT 24
Finished Jul 10 07:20:38 PM PDT 24
Peak memory 200144 kb
Host smart-aa7f6610-f721-425e-a09a-53d3f2ad4e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059149939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1059149939
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2009238572
Short name T158
Test name
Test status
Simulation time 80233898 ps
CPU time 0.8 seconds
Started Jul 10 07:20:30 PM PDT 24
Finished Jul 10 07:20:32 PM PDT 24
Peak memory 199976 kb
Host smart-f6eb4cd9-163d-453b-93c4-1c19ad0be9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009238572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2009238572
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3209405814
Short name T330
Test name
Test status
Simulation time 2353349617 ps
CPU time 8.74 seconds
Started Jul 10 07:20:34 PM PDT 24
Finished Jul 10 07:20:45 PM PDT 24
Peak memory 217224 kb
Host smart-929f35ef-c556-458d-b5a4-84ba5257f614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209405814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3209405814
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3312973033
Short name T178
Test name
Test status
Simulation time 244074750 ps
CPU time 1.09 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:37 PM PDT 24
Peak memory 217512 kb
Host smart-2fbe783a-a747-4641-aa76-8b7422bcbc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312973033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3312973033
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.325842955
Short name T20
Test name
Test status
Simulation time 74371048 ps
CPU time 0.76 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:36 PM PDT 24
Peak memory 199968 kb
Host smart-5fa4b522-8ade-4ee9-9db4-267e85bd14cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325842955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.325842955
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3389446319
Short name T336
Test name
Test status
Simulation time 770994233 ps
CPU time 3.99 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:41 PM PDT 24
Peak memory 200412 kb
Host smart-4d9de088-26b2-43da-9634-4efe4ebc991d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389446319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3389446319
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2889285572
Short name T503
Test name
Test status
Simulation time 182608219 ps
CPU time 1.21 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:36 PM PDT 24
Peak memory 200232 kb
Host smart-91715a19-214c-4224-baa6-35a818695532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889285572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2889285572
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.999809385
Short name T322
Test name
Test status
Simulation time 255202665 ps
CPU time 1.8 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:36 PM PDT 24
Peak memory 200340 kb
Host smart-9862fce9-7127-4061-8d5a-a7008cd371e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999809385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.999809385
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.185495179
Short name T167
Test name
Test status
Simulation time 2243007282 ps
CPU time 12.3 seconds
Started Jul 10 07:20:31 PM PDT 24
Finished Jul 10 07:20:45 PM PDT 24
Peak memory 208668 kb
Host smart-4a58d024-655d-4c8a-bb32-3b71dc7e05d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185495179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.185495179
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2129272401
Short name T207
Test name
Test status
Simulation time 87121051 ps
CPU time 0.85 seconds
Started Jul 10 07:20:29 PM PDT 24
Finished Jul 10 07:20:31 PM PDT 24
Peak memory 200148 kb
Host smart-7638d598-f966-4cc0-8a8f-c697656b1e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129272401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2129272401
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3168579847
Short name T358
Test name
Test status
Simulation time 83492937 ps
CPU time 0.82 seconds
Started Jul 10 07:20:30 PM PDT 24
Finished Jul 10 07:20:33 PM PDT 24
Peak memory 199952 kb
Host smart-e58efc1e-ad69-4ae6-ad44-6945a66503b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168579847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3168579847
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.559385670
Short name T375
Test name
Test status
Simulation time 1235447493 ps
CPU time 5.91 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:42 PM PDT 24
Peak memory 217572 kb
Host smart-f52a982f-b8b0-43aa-9703-f560d65fa3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559385670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.559385670
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2610929620
Short name T180
Test name
Test status
Simulation time 244869981 ps
CPU time 1.03 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:35 PM PDT 24
Peak memory 217512 kb
Host smart-cdef5009-b524-4553-ba69-e5b8c584810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610929620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2610929620
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2275058620
Short name T135
Test name
Test status
Simulation time 210830911 ps
CPU time 0.92 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:35 PM PDT 24
Peak memory 199984 kb
Host smart-2a6c8339-691b-452a-a735-189a09114af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275058620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2275058620
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4248756105
Short name T272
Test name
Test status
Simulation time 1483829284 ps
CPU time 5.77 seconds
Started Jul 10 07:20:30 PM PDT 24
Finished Jul 10 07:20:38 PM PDT 24
Peak memory 200428 kb
Host smart-8e0b7bb1-7973-4b0b-81b4-98e1eafd5247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248756105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4248756105
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3329369071
Short name T318
Test name
Test status
Simulation time 156693161 ps
CPU time 1.13 seconds
Started Jul 10 07:20:30 PM PDT 24
Finished Jul 10 07:20:33 PM PDT 24
Peak memory 200224 kb
Host smart-39cad184-95bf-4ced-b7c2-ed657036ef5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329369071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3329369071
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.148964903
Short name T481
Test name
Test status
Simulation time 200481456 ps
CPU time 1.39 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:36 PM PDT 24
Peak memory 200348 kb
Host smart-ae49055d-9bd5-42e3-b792-9247b99a12db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148964903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.148964903
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1585121093
Short name T51
Test name
Test status
Simulation time 3947060354 ps
CPU time 19.71 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:55 PM PDT 24
Peak memory 208720 kb
Host smart-f7e64fc1-be93-4a11-ad9f-db38dd6bdeb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585121093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1585121093
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3581002947
Short name T251
Test name
Test status
Simulation time 146158355 ps
CPU time 1.83 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:36 PM PDT 24
Peak memory 200228 kb
Host smart-7f1bc1f3-b880-4eec-b5e5-9b3ce5e42ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581002947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3581002947
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2859107276
Short name T134
Test name
Test status
Simulation time 215818680 ps
CPU time 1.29 seconds
Started Jul 10 07:20:34 PM PDT 24
Finished Jul 10 07:20:38 PM PDT 24
Peak memory 200144 kb
Host smart-6ab0a2ce-0cbb-43c8-af7b-2255a1d0b3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859107276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2859107276
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1281922885
Short name T39
Test name
Test status
Simulation time 69525906 ps
CPU time 0.81 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:36 PM PDT 24
Peak memory 199928 kb
Host smart-a299b450-8ced-4e03-bd33-d0a90db1c260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281922885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1281922885
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3212178059
Short name T408
Test name
Test status
Simulation time 1899079263 ps
CPU time 7.44 seconds
Started Jul 10 07:20:36 PM PDT 24
Finished Jul 10 07:20:45 PM PDT 24
Peak memory 217964 kb
Host smart-87b99201-2050-4bc7-ba27-a5726d45ef17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212178059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3212178059
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2554652871
Short name T47
Test name
Test status
Simulation time 245167235 ps
CPU time 1.12 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:35 PM PDT 24
Peak memory 217208 kb
Host smart-82f3ed97-c9b7-4b51-ae0b-fdbf1f55c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554652871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2554652871
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3072401578
Short name T455
Test name
Test status
Simulation time 135497252 ps
CPU time 0.83 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:36 PM PDT 24
Peak memory 199972 kb
Host smart-1a73214a-6c63-4f28-a2ff-6d5614f1aa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072401578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3072401578
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.4078042183
Short name T2
Test name
Test status
Simulation time 1501123408 ps
CPU time 6.84 seconds
Started Jul 10 07:20:34 PM PDT 24
Finished Jul 10 07:20:44 PM PDT 24
Peak memory 200412 kb
Host smart-1dc8b4b1-98e2-41db-b2b5-8f882796674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078042183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.4078042183
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2074802229
Short name T402
Test name
Test status
Simulation time 180080179 ps
CPU time 1.2 seconds
Started Jul 10 07:20:30 PM PDT 24
Finished Jul 10 07:20:33 PM PDT 24
Peak memory 200148 kb
Host smart-e8e80c99-ecca-4e92-8f82-a1f8a9f49ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074802229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2074802229
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2596209819
Short name T269
Test name
Test status
Simulation time 252661470 ps
CPU time 1.55 seconds
Started Jul 10 07:20:31 PM PDT 24
Finished Jul 10 07:20:35 PM PDT 24
Peak memory 200348 kb
Host smart-4c5e34e2-8d7d-4f6e-b938-8826292fc18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596209819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2596209819
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.666043601
Short name T343
Test name
Test status
Simulation time 1939053192 ps
CPU time 9.23 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:44 PM PDT 24
Peak memory 208652 kb
Host smart-57ad2ee5-5e2b-40cc-b000-9cf65e7c30e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666043601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.666043601
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2083184397
Short name T418
Test name
Test status
Simulation time 395079536 ps
CPU time 2.23 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:36 PM PDT 24
Peak memory 200160 kb
Host smart-65b5bf41-4e42-43c5-a73b-3fc1561abc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083184397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2083184397
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3325244901
Short name T310
Test name
Test status
Simulation time 134289051 ps
CPU time 1.2 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:37 PM PDT 24
Peak memory 200164 kb
Host smart-02fc4bf0-8488-48e0-a442-8c05aacebfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325244901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3325244901
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2650539423
Short name T145
Test name
Test status
Simulation time 72314686 ps
CPU time 0.76 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:35 PM PDT 24
Peak memory 199960 kb
Host smart-5b7b0967-e118-435d-80b3-0c8e9430b4da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650539423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2650539423
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3189655879
Short name T309
Test name
Test status
Simulation time 2358390909 ps
CPU time 8.7 seconds
Started Jul 10 07:20:35 PM PDT 24
Finished Jul 10 07:20:46 PM PDT 24
Peak memory 221860 kb
Host smart-5c185e24-50c6-47ff-8a61-51336e4e3fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189655879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3189655879
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3937276766
Short name T524
Test name
Test status
Simulation time 244150121 ps
CPU time 1.12 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:35 PM PDT 24
Peak memory 217364 kb
Host smart-950af085-3fd9-48e3-bef8-9a90c1f91c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937276766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3937276766
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2747131256
Short name T453
Test name
Test status
Simulation time 255201715 ps
CPU time 0.99 seconds
Started Jul 10 07:20:30 PM PDT 24
Finished Jul 10 07:20:33 PM PDT 24
Peak memory 199984 kb
Host smart-e4637787-3636-4b3d-ace4-48d49d976699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747131256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2747131256
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.856264320
Short name T225
Test name
Test status
Simulation time 614777204 ps
CPU time 3.69 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:39 PM PDT 24
Peak memory 200424 kb
Host smart-07ba4154-cc42-423a-b40f-de9ca2ecd33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856264320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.856264320
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2289890175
Short name T235
Test name
Test status
Simulation time 146525507 ps
CPU time 1.14 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:37 PM PDT 24
Peak memory 200156 kb
Host smart-713d6579-041d-43e2-8d9f-cfaa1a2ae481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289890175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2289890175
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2031988270
Short name T397
Test name
Test status
Simulation time 125031956 ps
CPU time 1.24 seconds
Started Jul 10 07:20:30 PM PDT 24
Finished Jul 10 07:20:33 PM PDT 24
Peak memory 200344 kb
Host smart-527f081c-902e-4c4a-9c9b-0ffb387a6a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031988270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2031988270
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.830265336
Short name T356
Test name
Test status
Simulation time 5540951800 ps
CPU time 21.62 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:57 PM PDT 24
Peak memory 208672 kb
Host smart-46a97f23-09da-4900-9203-ac81e7558054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830265336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.830265336
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2538497524
Short name T494
Test name
Test status
Simulation time 471749334 ps
CPU time 2.73 seconds
Started Jul 10 07:20:37 PM PDT 24
Finished Jul 10 07:20:41 PM PDT 24
Peak memory 200352 kb
Host smart-0871bb51-cfbc-46a3-9ab6-81790a21df9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538497524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2538497524
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3300808025
Short name T440
Test name
Test status
Simulation time 113864175 ps
CPU time 0.99 seconds
Started Jul 10 07:20:31 PM PDT 24
Finished Jul 10 07:20:34 PM PDT 24
Peak memory 200140 kb
Host smart-1d165d0b-32df-44ac-b5fc-0e196c7078b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300808025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3300808025
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1995425595
Short name T280
Test name
Test status
Simulation time 67831230 ps
CPU time 0.83 seconds
Started Jul 10 07:20:40 PM PDT 24
Finished Jul 10 07:20:42 PM PDT 24
Peak memory 199948 kb
Host smart-8260e49b-9979-47ff-ade5-062935ad303b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995425595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1995425595
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.435188563
Short name T468
Test name
Test status
Simulation time 1231287199 ps
CPU time 6.17 seconds
Started Jul 10 07:20:40 PM PDT 24
Finished Jul 10 07:20:48 PM PDT 24
Peak memory 221420 kb
Host smart-a161ab8e-3122-40b7-a26a-b2842686f877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435188563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.435188563
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.630516861
Short name T196
Test name
Test status
Simulation time 244452979 ps
CPU time 1.07 seconds
Started Jul 10 07:20:39 PM PDT 24
Finished Jul 10 07:20:41 PM PDT 24
Peak memory 217540 kb
Host smart-a3ef3d2a-5b4e-4b48-b50e-fd9f8ea3912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630516861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.630516861
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1560196050
Short name T352
Test name
Test status
Simulation time 102950824 ps
CPU time 0.78 seconds
Started Jul 10 07:20:31 PM PDT 24
Finished Jul 10 07:20:34 PM PDT 24
Peak memory 199984 kb
Host smart-95055d44-3a62-491a-8d3c-f70a1aa03904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560196050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1560196050
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1423494437
Short name T78
Test name
Test status
Simulation time 760463017 ps
CPU time 3.96 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:38 PM PDT 24
Peak memory 200412 kb
Host smart-8f527f3d-e776-4473-b00f-cf71149bda5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423494437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1423494437
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.920224578
Short name T404
Test name
Test status
Simulation time 176480646 ps
CPU time 1.25 seconds
Started Jul 10 07:20:35 PM PDT 24
Finished Jul 10 07:20:39 PM PDT 24
Peak memory 200180 kb
Host smart-99e84b35-199c-4a1f-bb61-d5565c77a685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920224578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.920224578
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.4238357957
Short name T141
Test name
Test status
Simulation time 199285596 ps
CPU time 1.35 seconds
Started Jul 10 07:20:33 PM PDT 24
Finished Jul 10 07:20:37 PM PDT 24
Peak memory 200420 kb
Host smart-323e4593-ab6e-4844-906c-b7eda0d8ff48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238357957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.4238357957
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1055928060
Short name T98
Test name
Test status
Simulation time 5611210238 ps
CPU time 19.29 seconds
Started Jul 10 07:20:40 PM PDT 24
Finished Jul 10 07:21:00 PM PDT 24
Peak memory 208692 kb
Host smart-2a043a84-5fb5-414a-994d-6178397c9105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055928060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1055928060
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4033117831
Short name T504
Test name
Test status
Simulation time 467070141 ps
CPU time 2.69 seconds
Started Jul 10 07:20:35 PM PDT 24
Finished Jul 10 07:20:40 PM PDT 24
Peak memory 200168 kb
Host smart-02d27739-fc9e-4270-b36e-5d1521476703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033117831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4033117831
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1862558739
Short name T337
Test name
Test status
Simulation time 88113571 ps
CPU time 0.91 seconds
Started Jul 10 07:20:32 PM PDT 24
Finished Jul 10 07:20:35 PM PDT 24
Peak memory 200176 kb
Host smart-b72263be-de78-4200-afd8-69ff0d609a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862558739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1862558739
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3771832026
Short name T126
Test name
Test status
Simulation time 74771851 ps
CPU time 0.79 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:01 PM PDT 24
Peak memory 199948 kb
Host smart-d0d27449-3914-43fb-98c5-1b81c0366a07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771832026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3771832026
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2053412647
Short name T60
Test name
Test status
Simulation time 1884251050 ps
CPU time 7.17 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:19:55 PM PDT 24
Peak memory 217552 kb
Host smart-c0f5aa6b-6b2e-4453-b06f-f5bc6ac30d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053412647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2053412647
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2259981648
Short name T305
Test name
Test status
Simulation time 244954038 ps
CPU time 1.06 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:19:49 PM PDT 24
Peak memory 217440 kb
Host smart-06ba756f-d9b9-48c7-8a80-00c08940fed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259981648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2259981648
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2325913286
Short name T150
Test name
Test status
Simulation time 224360268 ps
CPU time 0.94 seconds
Started Jul 10 07:19:45 PM PDT 24
Finished Jul 10 07:19:51 PM PDT 24
Peak memory 199968 kb
Host smart-322a186d-9402-4dbc-8fdb-a4203a9dd90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325913286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2325913286
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1683618555
Short name T166
Test name
Test status
Simulation time 1142924083 ps
CPU time 4.73 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:19:53 PM PDT 24
Peak memory 200420 kb
Host smart-83a07588-89b1-434a-9a35-b21484c1c3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683618555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1683618555
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2614896488
Short name T73
Test name
Test status
Simulation time 16636488552 ps
CPU time 25.22 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:20:24 PM PDT 24
Peak memory 218340 kb
Host smart-fb1c91d6-cd37-4a6c-ba90-d57c5b6a9f4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614896488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2614896488
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.315245723
Short name T472
Test name
Test status
Simulation time 106497181 ps
CPU time 1.01 seconds
Started Jul 10 07:19:46 PM PDT 24
Finished Jul 10 07:19:51 PM PDT 24
Peak memory 199964 kb
Host smart-5fceb6d5-ab87-4683-b4b1-25fd7194dea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315245723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.315245723
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.877273292
Short name T448
Test name
Test status
Simulation time 120107580 ps
CPU time 1.24 seconds
Started Jul 10 07:19:46 PM PDT 24
Finished Jul 10 07:19:52 PM PDT 24
Peak memory 200092 kb
Host smart-8978b432-7396-4716-a817-5a4dafeb14a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877273292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.877273292
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3366686079
Short name T467
Test name
Test status
Simulation time 13403600397 ps
CPU time 52.6 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:52 PM PDT 24
Peak memory 200476 kb
Host smart-6af62ee7-71ab-4fb0-8caa-f667fa34ca9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366686079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3366686079
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1986666734
Short name T457
Test name
Test status
Simulation time 131404846 ps
CPU time 1.82 seconds
Started Jul 10 07:19:43 PM PDT 24
Finished Jul 10 07:19:49 PM PDT 24
Peak memory 208348 kb
Host smart-04c1c29c-a773-426a-aa94-eb61f14c9af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986666734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1986666734
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.946332636
Short name T294
Test name
Test status
Simulation time 222164214 ps
CPU time 1.23 seconds
Started Jul 10 07:19:42 PM PDT 24
Finished Jul 10 07:19:46 PM PDT 24
Peak memory 200160 kb
Host smart-1326b522-cdd7-4a21-a439-e57f9dca1833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946332636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.946332636
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3958147746
Short name T449
Test name
Test status
Simulation time 70996340 ps
CPU time 0.81 seconds
Started Jul 10 07:20:41 PM PDT 24
Finished Jul 10 07:20:43 PM PDT 24
Peak memory 200152 kb
Host smart-06d895a6-3aad-4029-9778-26aab559c2d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958147746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3958147746
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1122305745
Short name T55
Test name
Test status
Simulation time 1227834407 ps
CPU time 5.72 seconds
Started Jul 10 07:20:45 PM PDT 24
Finished Jul 10 07:20:52 PM PDT 24
Peak memory 217016 kb
Host smart-3932e7d9-35e6-4517-b486-1c56e640a2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122305745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1122305745
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.851034518
Short name T413
Test name
Test status
Simulation time 245065919 ps
CPU time 1.1 seconds
Started Jul 10 07:20:39 PM PDT 24
Finished Jul 10 07:20:42 PM PDT 24
Peak memory 217552 kb
Host smart-5403f4d1-77fe-4da7-b833-9676110b19f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851034518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.851034518
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1614153142
Short name T233
Test name
Test status
Simulation time 143158272 ps
CPU time 0.81 seconds
Started Jul 10 07:20:39 PM PDT 24
Finished Jul 10 07:20:40 PM PDT 24
Peak memory 199984 kb
Host smart-d98191cd-e5f3-4e8f-ba28-18b9b9fd7f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614153142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1614153142
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1499040326
Short name T125
Test name
Test status
Simulation time 1606786782 ps
CPU time 6.42 seconds
Started Jul 10 07:20:41 PM PDT 24
Finished Jul 10 07:20:49 PM PDT 24
Peak memory 200392 kb
Host smart-c25b1be8-11a9-44c3-8f79-973f7190e619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499040326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1499040326
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1604717822
Short name T493
Test name
Test status
Simulation time 179825566 ps
CPU time 1.22 seconds
Started Jul 10 07:20:38 PM PDT 24
Finished Jul 10 07:20:40 PM PDT 24
Peak memory 200148 kb
Host smart-01add621-ab6a-4c5c-8ead-a830e1e9337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604717822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1604717822
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1952850564
Short name T374
Test name
Test status
Simulation time 116523276 ps
CPU time 1.23 seconds
Started Jul 10 07:20:46 PM PDT 24
Finished Jul 10 07:20:48 PM PDT 24
Peak memory 200372 kb
Host smart-34cf7852-7af3-471f-bd63-f3f098143782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952850564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1952850564
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1035620311
Short name T142
Test name
Test status
Simulation time 221122640 ps
CPU time 1.29 seconds
Started Jul 10 07:20:40 PM PDT 24
Finished Jul 10 07:20:43 PM PDT 24
Peak memory 200220 kb
Host smart-3b62fc08-3f0e-4758-a2fa-7970ee706a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035620311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1035620311
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.815954641
Short name T240
Test name
Test status
Simulation time 145699097 ps
CPU time 1.79 seconds
Started Jul 10 07:20:39 PM PDT 24
Finished Jul 10 07:20:41 PM PDT 24
Peak memory 200156 kb
Host smart-181b34dc-5848-4b6e-953a-76488feade5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815954641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.815954641
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2716992419
Short name T427
Test name
Test status
Simulation time 170614954 ps
CPU time 1.33 seconds
Started Jul 10 07:20:41 PM PDT 24
Finished Jul 10 07:20:43 PM PDT 24
Peak memory 200392 kb
Host smart-c30f6c7d-cdf3-49b5-9b42-038e9fdd19bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716992419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2716992419
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.437980816
Short name T37
Test name
Test status
Simulation time 65415962 ps
CPU time 0.76 seconds
Started Jul 10 07:20:39 PM PDT 24
Finished Jul 10 07:20:41 PM PDT 24
Peak memory 199932 kb
Host smart-3065e57f-01bf-428a-8e0d-4c1e1316a34e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437980816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.437980816
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3720652817
Short name T437
Test name
Test status
Simulation time 1224454457 ps
CPU time 5.73 seconds
Started Jul 10 07:20:40 PM PDT 24
Finished Jul 10 07:20:48 PM PDT 24
Peak memory 217784 kb
Host smart-8de035ca-f314-443b-a6aa-d077290abe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720652817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3720652817
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.104640884
Short name T434
Test name
Test status
Simulation time 244574590 ps
CPU time 1.06 seconds
Started Jul 10 07:20:47 PM PDT 24
Finished Jul 10 07:20:48 PM PDT 24
Peak memory 217500 kb
Host smart-70c62119-ab9e-4853-8bdd-0efc027aec3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104640884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.104640884
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1646091679
Short name T267
Test name
Test status
Simulation time 155535808 ps
CPU time 0.88 seconds
Started Jul 10 07:20:45 PM PDT 24
Finished Jul 10 07:20:47 PM PDT 24
Peak memory 199972 kb
Host smart-903ff1e9-4c4d-4a40-a83e-cb4aa1eacf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646091679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1646091679
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.713901009
Short name T367
Test name
Test status
Simulation time 1424327947 ps
CPU time 5.88 seconds
Started Jul 10 07:20:42 PM PDT 24
Finished Jul 10 07:20:49 PM PDT 24
Peak memory 200412 kb
Host smart-9ff95608-49ba-48b3-a71c-efbcd944a16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713901009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.713901009
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1867493856
Short name T275
Test name
Test status
Simulation time 113489214 ps
CPU time 1.02 seconds
Started Jul 10 07:20:44 PM PDT 24
Finished Jul 10 07:20:46 PM PDT 24
Peak memory 200180 kb
Host smart-d364dbc1-7b3d-4231-abc3-e98201a63427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867493856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1867493856
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3581262884
Short name T487
Test name
Test status
Simulation time 126198674 ps
CPU time 1.14 seconds
Started Jul 10 07:20:45 PM PDT 24
Finished Jul 10 07:20:47 PM PDT 24
Peak memory 200332 kb
Host smart-502c03ea-f9ba-40fa-b9ff-788be945c42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581262884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3581262884
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3089567228
Short name T287
Test name
Test status
Simulation time 6351869506 ps
CPU time 24.22 seconds
Started Jul 10 07:20:41 PM PDT 24
Finished Jul 10 07:21:06 PM PDT 24
Peak memory 210524 kb
Host smart-0949e639-1100-4362-8ba7-2a11fd673606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089567228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3089567228
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1354982193
Short name T304
Test name
Test status
Simulation time 144948664 ps
CPU time 1.73 seconds
Started Jul 10 07:20:45 PM PDT 24
Finished Jul 10 07:20:47 PM PDT 24
Peak memory 208380 kb
Host smart-e05f7bde-1cb2-4cc4-9402-fd6d4fb0d31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354982193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1354982193
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2649624859
Short name T307
Test name
Test status
Simulation time 84993549 ps
CPU time 0.9 seconds
Started Jul 10 07:20:42 PM PDT 24
Finished Jul 10 07:20:44 PM PDT 24
Peak memory 200364 kb
Host smart-a0083109-1f2c-4b3a-afb9-1d7eb6648a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649624859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2649624859
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1316363277
Short name T316
Test name
Test status
Simulation time 79869717 ps
CPU time 0.8 seconds
Started Jul 10 07:20:41 PM PDT 24
Finished Jul 10 07:20:43 PM PDT 24
Peak memory 199932 kb
Host smart-e54a0831-6290-454e-be39-60232d32d21b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316363277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1316363277
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3151200792
Short name T25
Test name
Test status
Simulation time 2181415284 ps
CPU time 7.84 seconds
Started Jul 10 07:20:41 PM PDT 24
Finished Jul 10 07:20:50 PM PDT 24
Peak memory 217916 kb
Host smart-4dc95ab1-7f21-4756-9e98-54c9c781b00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151200792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3151200792
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2916355293
Short name T232
Test name
Test status
Simulation time 244777327 ps
CPU time 1.1 seconds
Started Jul 10 07:20:43 PM PDT 24
Finished Jul 10 07:20:45 PM PDT 24
Peak memory 217576 kb
Host smart-4590cd8f-c8fe-4899-a926-a8e1db926873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916355293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2916355293
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2907799890
Short name T438
Test name
Test status
Simulation time 169579133 ps
CPU time 0.88 seconds
Started Jul 10 07:20:51 PM PDT 24
Finished Jul 10 07:20:55 PM PDT 24
Peak memory 199972 kb
Host smart-75934e36-eb13-4575-93f7-8f9ab4c0a35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907799890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2907799890
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.272672084
Short name T173
Test name
Test status
Simulation time 1493371730 ps
CPU time 5.78 seconds
Started Jul 10 07:20:44 PM PDT 24
Finished Jul 10 07:20:51 PM PDT 24
Peak memory 200436 kb
Host smart-c04895fb-1ae8-4bbc-a6ec-049b7955d861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272672084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.272672084
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2173864557
Short name T292
Test name
Test status
Simulation time 102694779 ps
CPU time 1.01 seconds
Started Jul 10 07:20:41 PM PDT 24
Finished Jul 10 07:20:44 PM PDT 24
Peak memory 200108 kb
Host smart-8c874856-e995-4fad-89a6-3c4eca092275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173864557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2173864557
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1406732752
Short name T85
Test name
Test status
Simulation time 116913151 ps
CPU time 1.2 seconds
Started Jul 10 07:20:41 PM PDT 24
Finished Jul 10 07:20:43 PM PDT 24
Peak memory 200368 kb
Host smart-017295f8-7170-465b-afba-3da438b11eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406732752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1406732752
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3507237968
Short name T526
Test name
Test status
Simulation time 1576885834 ps
CPU time 7.07 seconds
Started Jul 10 07:20:45 PM PDT 24
Finished Jul 10 07:20:53 PM PDT 24
Peak memory 208608 kb
Host smart-56689f36-3909-4dc7-a97b-cb2dd905fa08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507237968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3507237968
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1893448999
Short name T193
Test name
Test status
Simulation time 151456498 ps
CPU time 1.92 seconds
Started Jul 10 07:20:43 PM PDT 24
Finished Jul 10 07:20:46 PM PDT 24
Peak memory 200148 kb
Host smart-68ca15fc-529a-44d7-92d0-3d0f93690ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893448999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1893448999
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3172714955
Short name T476
Test name
Test status
Simulation time 77872415 ps
CPU time 0.87 seconds
Started Jul 10 07:20:45 PM PDT 24
Finished Jul 10 07:20:47 PM PDT 24
Peak memory 200164 kb
Host smart-c9a9ee8b-51eb-41fe-bc88-7df3f3daddec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172714955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3172714955
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3955960032
Short name T424
Test name
Test status
Simulation time 82703940 ps
CPU time 0.74 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:20:55 PM PDT 24
Peak memory 199996 kb
Host smart-d42b29ba-8dc0-4565-b861-f30e1bda3cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955960032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3955960032
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2577130949
Short name T257
Test name
Test status
Simulation time 1880546625 ps
CPU time 7.06 seconds
Started Jul 10 07:20:51 PM PDT 24
Finished Jul 10 07:21:01 PM PDT 24
Peak memory 221740 kb
Host smart-544383f1-0a28-491d-90c6-783db6d02015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577130949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2577130949
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4225712960
Short name T392
Test name
Test status
Simulation time 244081810 ps
CPU time 1.21 seconds
Started Jul 10 07:20:46 PM PDT 24
Finished Jul 10 07:20:48 PM PDT 24
Peak memory 217500 kb
Host smart-916fc676-5872-4b8b-9654-dad76b99ccf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225712960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4225712960
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2410847513
Short name T446
Test name
Test status
Simulation time 95151808 ps
CPU time 0.76 seconds
Started Jul 10 07:20:39 PM PDT 24
Finished Jul 10 07:20:41 PM PDT 24
Peak memory 199984 kb
Host smart-988fc42b-8a0b-4473-977e-63890adc72b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410847513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2410847513
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1902909467
Short name T363
Test name
Test status
Simulation time 1698795062 ps
CPU time 7.19 seconds
Started Jul 10 07:20:46 PM PDT 24
Finished Jul 10 07:20:54 PM PDT 24
Peak memory 200396 kb
Host smart-deeced5c-fa00-4233-9d78-a12a19706bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902909467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1902909467
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.310360072
Short name T515
Test name
Test status
Simulation time 105202739 ps
CPU time 1.03 seconds
Started Jul 10 07:20:47 PM PDT 24
Finished Jul 10 07:20:49 PM PDT 24
Peak memory 200148 kb
Host smart-bfaeefd7-153f-4137-a790-98f1fbb69fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310360072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.310360072
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1397640353
Short name T447
Test name
Test status
Simulation time 202739605 ps
CPU time 1.53 seconds
Started Jul 10 07:20:43 PM PDT 24
Finished Jul 10 07:20:46 PM PDT 24
Peak memory 200344 kb
Host smart-04de003e-6138-4dd3-84e6-5bdcc0f39d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397640353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1397640353
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1192361582
Short name T124
Test name
Test status
Simulation time 10611068879 ps
CPU time 36.9 seconds
Started Jul 10 07:20:41 PM PDT 24
Finished Jul 10 07:21:19 PM PDT 24
Peak memory 208656 kb
Host smart-8265de5a-0b42-4cfd-9b8c-c0090c6a430b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192361582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1192361582
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.337353612
Short name T159
Test name
Test status
Simulation time 279455234 ps
CPU time 2.02 seconds
Started Jul 10 07:20:40 PM PDT 24
Finished Jul 10 07:20:43 PM PDT 24
Peak memory 200224 kb
Host smart-71e074ab-20dd-4429-9264-89667e04205e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337353612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.337353612
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.242880136
Short name T518
Test name
Test status
Simulation time 123282324 ps
CPU time 1.11 seconds
Started Jul 10 07:20:51 PM PDT 24
Finished Jul 10 07:20:55 PM PDT 24
Peak memory 200168 kb
Host smart-0eabe736-57a5-48a5-9ea7-27fec7f55f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242880136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.242880136
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2559096871
Short name T379
Test name
Test status
Simulation time 79736434 ps
CPU time 0.83 seconds
Started Jul 10 07:20:54 PM PDT 24
Finished Jul 10 07:20:57 PM PDT 24
Peak memory 199952 kb
Host smart-0cb55f4e-ed25-4985-a24e-d0bb45385ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559096871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2559096871
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.605822315
Short name T254
Test name
Test status
Simulation time 1900962540 ps
CPU time 8.32 seconds
Started Jul 10 07:20:54 PM PDT 24
Finished Jul 10 07:21:05 PM PDT 24
Peak memory 217588 kb
Host smart-a9da50b1-6cf8-4629-85cf-2f9a55fd6443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605822315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.605822315
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4277783554
Short name T499
Test name
Test status
Simulation time 245118986 ps
CPU time 1.06 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:20:53 PM PDT 24
Peak memory 217496 kb
Host smart-dd099fe6-27c9-44ea-b49a-8c6877d36b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277783554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4277783554
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1091596100
Short name T247
Test name
Test status
Simulation time 177329500 ps
CPU time 0.85 seconds
Started Jul 10 07:20:39 PM PDT 24
Finished Jul 10 07:20:41 PM PDT 24
Peak memory 199984 kb
Host smart-2689722b-a41a-4dfe-9b2e-c8b15b778585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091596100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1091596100
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.201946537
Short name T344
Test name
Test status
Simulation time 784823418 ps
CPU time 4.04 seconds
Started Jul 10 07:20:45 PM PDT 24
Finished Jul 10 07:20:51 PM PDT 24
Peak memory 200396 kb
Host smart-092c20bc-f78f-4d41-ad64-b09013bedefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201946537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.201946537
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1447048348
Short name T163
Test name
Test status
Simulation time 170564528 ps
CPU time 1.23 seconds
Started Jul 10 07:20:41 PM PDT 24
Finished Jul 10 07:20:44 PM PDT 24
Peak memory 200108 kb
Host smart-808ab3b5-43f2-432b-befd-5df97bd577a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447048348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1447048348
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2450238225
Short name T190
Test name
Test status
Simulation time 192914220 ps
CPU time 1.27 seconds
Started Jul 10 07:20:51 PM PDT 24
Finished Jul 10 07:20:55 PM PDT 24
Peak memory 200388 kb
Host smart-4b5954c3-5c8b-48fb-aec4-cfc60fac102a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450238225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2450238225
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.652149213
Short name T265
Test name
Test status
Simulation time 8061387818 ps
CPU time 35.14 seconds
Started Jul 10 07:20:48 PM PDT 24
Finished Jul 10 07:21:24 PM PDT 24
Peak memory 216388 kb
Host smart-b1a115b0-2610-48df-8e65-6118a1ee6d44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652149213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.652149213
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3407164610
Short name T49
Test name
Test status
Simulation time 262152080 ps
CPU time 1.68 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:20:54 PM PDT 24
Peak memory 200184 kb
Host smart-443133c2-9c52-4663-8853-285d9ba9b74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407164610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3407164610
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3087105602
Short name T175
Test name
Test status
Simulation time 204273860 ps
CPU time 1.46 seconds
Started Jul 10 07:20:43 PM PDT 24
Finished Jul 10 07:20:45 PM PDT 24
Peak memory 200164 kb
Host smart-22bfea93-673a-404e-911b-184590c02d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087105602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3087105602
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3016551741
Short name T532
Test name
Test status
Simulation time 55408116 ps
CPU time 0.78 seconds
Started Jul 10 07:20:59 PM PDT 24
Finished Jul 10 07:21:01 PM PDT 24
Peak memory 199940 kb
Host smart-31e0cf4b-0ecd-4804-830c-bb8994183b4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016551741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3016551741
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3378868632
Short name T201
Test name
Test status
Simulation time 244163862 ps
CPU time 1.15 seconds
Started Jul 10 07:20:54 PM PDT 24
Finished Jul 10 07:20:57 PM PDT 24
Peak memory 217540 kb
Host smart-2289f6e3-c665-4b75-b030-86f0e9b4c039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378868632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3378868632
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1871614416
Short name T15
Test name
Test status
Simulation time 202739084 ps
CPU time 1 seconds
Started Jul 10 07:20:48 PM PDT 24
Finished Jul 10 07:20:50 PM PDT 24
Peak memory 199940 kb
Host smart-1d6f046a-3190-4e87-a34c-70ba21e5d49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871614416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1871614416
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2417905838
Short name T122
Test name
Test status
Simulation time 2043339522 ps
CPU time 7.25 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:20:59 PM PDT 24
Peak memory 200344 kb
Host smart-7885e73c-197f-4774-95b1-4a440c7d8d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417905838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2417905838
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2484848357
Short name T22
Test name
Test status
Simulation time 110455257 ps
CPU time 1.18 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:20:53 PM PDT 24
Peak memory 200156 kb
Host smart-230b2182-2f27-445e-99d6-1a189b4ce913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484848357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2484848357
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3414593769
Short name T3
Test name
Test status
Simulation time 123284276 ps
CPU time 1.29 seconds
Started Jul 10 07:20:49 PM PDT 24
Finished Jul 10 07:20:52 PM PDT 24
Peak memory 200408 kb
Host smart-3534c7bc-57fe-4070-b7da-ec6d079617a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414593769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3414593769
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2110351397
Short name T241
Test name
Test status
Simulation time 367623819 ps
CPU time 2.13 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:20:54 PM PDT 24
Peak memory 200084 kb
Host smart-c1c7fe1a-f8a9-48b2-8a97-93b8894a0e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110351397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2110351397
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3961856187
Short name T6
Test name
Test status
Simulation time 92409409 ps
CPU time 0.99 seconds
Started Jul 10 07:20:48 PM PDT 24
Finished Jul 10 07:20:50 PM PDT 24
Peak memory 200160 kb
Host smart-4cd93ceb-793e-4757-ac73-5b94820dc09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961856187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3961856187
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1540790980
Short name T462
Test name
Test status
Simulation time 75984038 ps
CPU time 0.9 seconds
Started Jul 10 07:20:59 PM PDT 24
Finished Jul 10 07:21:02 PM PDT 24
Peak memory 199940 kb
Host smart-3d5012a6-8679-49ef-bbb2-c6ad6a05dcdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540790980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1540790980
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3537837183
Short name T61
Test name
Test status
Simulation time 1882300474 ps
CPU time 7.12 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:20:59 PM PDT 24
Peak memory 217716 kb
Host smart-0d9bdaf0-acdf-483f-993e-904ec384c39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537837183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3537837183
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3072788942
Short name T149
Test name
Test status
Simulation time 244273875 ps
CPU time 1.23 seconds
Started Jul 10 07:20:47 PM PDT 24
Finished Jul 10 07:20:50 PM PDT 24
Peak memory 217520 kb
Host smart-8aaf5a94-de0f-45e1-b943-319759c04470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072788942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3072788942
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.805329399
Short name T529
Test name
Test status
Simulation time 76316046 ps
CPU time 0.73 seconds
Started Jul 10 07:20:48 PM PDT 24
Finished Jul 10 07:20:50 PM PDT 24
Peak memory 199964 kb
Host smart-c0f3ea64-d959-4b49-a1b7-e5133850cf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805329399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.805329399
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3337479087
Short name T338
Test name
Test status
Simulation time 896284441 ps
CPU time 4.72 seconds
Started Jul 10 07:20:46 PM PDT 24
Finished Jul 10 07:20:52 PM PDT 24
Peak memory 200412 kb
Host smart-4c2e7060-3d15-42b4-b6a1-2ae00bc662dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337479087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3337479087
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1846268592
Short name T298
Test name
Test status
Simulation time 104983025 ps
CPU time 1.1 seconds
Started Jul 10 07:21:00 PM PDT 24
Finished Jul 10 07:21:03 PM PDT 24
Peak memory 200144 kb
Host smart-c93e81c3-de21-4adf-a6fb-e8dcf6c6cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846268592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1846268592
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2245383686
Short name T429
Test name
Test status
Simulation time 196736042 ps
CPU time 1.45 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:20:56 PM PDT 24
Peak memory 200348 kb
Host smart-75a5fd91-dde2-47f5-9a42-474ec913de9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245383686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2245383686
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1213437014
Short name T423
Test name
Test status
Simulation time 391326204 ps
CPU time 2.06 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:20:56 PM PDT 24
Peak memory 200340 kb
Host smart-26517ac0-1107-4f6d-89d5-94e3d608a562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213437014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1213437014
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2543106648
Short name T82
Test name
Test status
Simulation time 151326859 ps
CPU time 2.02 seconds
Started Jul 10 07:20:49 PM PDT 24
Finished Jul 10 07:20:53 PM PDT 24
Peak memory 200168 kb
Host smart-5082a282-e00b-48bb-b936-aa127f6328b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543106648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2543106648
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2036947218
Short name T136
Test name
Test status
Simulation time 173410656 ps
CPU time 1.2 seconds
Started Jul 10 07:20:49 PM PDT 24
Finished Jul 10 07:20:52 PM PDT 24
Peak memory 200164 kb
Host smart-eafbc671-953d-4202-b05a-28e73607ac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036947218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2036947218
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2126534557
Short name T473
Test name
Test status
Simulation time 72818588 ps
CPU time 0.8 seconds
Started Jul 10 07:20:48 PM PDT 24
Finished Jul 10 07:20:50 PM PDT 24
Peak memory 199928 kb
Host smart-8f3fc0fd-0c34-4e80-9474-06139a99ec7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126534557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2126534557
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3632816923
Short name T32
Test name
Test status
Simulation time 2352884625 ps
CPU time 8.62 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:21:01 PM PDT 24
Peak memory 217360 kb
Host smart-03f5853f-6fce-4c2e-b47b-cb7ad662f19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632816923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3632816923
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.35442143
Short name T414
Test name
Test status
Simulation time 244750634 ps
CPU time 1.05 seconds
Started Jul 10 07:20:47 PM PDT 24
Finished Jul 10 07:20:49 PM PDT 24
Peak memory 217488 kb
Host smart-fa2d1a90-a31a-4b0c-97f3-5a68cd9fcf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35442143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.35442143
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1372345504
Short name T258
Test name
Test status
Simulation time 141109321 ps
CPU time 0.82 seconds
Started Jul 10 07:20:59 PM PDT 24
Finished Jul 10 07:21:01 PM PDT 24
Peak memory 199960 kb
Host smart-f95ee513-79bf-480c-99f4-3100780c3420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372345504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1372345504
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3140411565
Short name T224
Test name
Test status
Simulation time 2068926976 ps
CPU time 7.22 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:20:59 PM PDT 24
Peak memory 200424 kb
Host smart-69258f8d-bd6d-4d4e-aa8b-d918fa83d731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140411565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3140411565
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3403178049
Short name T46
Test name
Test status
Simulation time 94772758 ps
CPU time 0.98 seconds
Started Jul 10 07:20:49 PM PDT 24
Finished Jul 10 07:20:52 PM PDT 24
Peak memory 200132 kb
Host smart-eb8ab78c-56fc-4279-be8a-741a38a477f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403178049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3403178049
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.263212464
Short name T501
Test name
Test status
Simulation time 125694685 ps
CPU time 1.27 seconds
Started Jul 10 07:20:59 PM PDT 24
Finished Jul 10 07:21:02 PM PDT 24
Peak memory 200376 kb
Host smart-4e6786bb-d6ba-496a-9c6c-570998a1331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263212464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.263212464
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2254711236
Short name T389
Test name
Test status
Simulation time 8053267740 ps
CPU time 26.15 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:21:20 PM PDT 24
Peak memory 208668 kb
Host smart-98317a97-1d50-4ec3-9617-991658aa90f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254711236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2254711236
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1911342479
Short name T75
Test name
Test status
Simulation time 265917398 ps
CPU time 1.75 seconds
Started Jul 10 07:20:49 PM PDT 24
Finished Jul 10 07:20:52 PM PDT 24
Peak memory 200152 kb
Host smart-bc3ba27e-0161-444e-b8b1-152bf4d59ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911342479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1911342479
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.4229406292
Short name T412
Test name
Test status
Simulation time 277981899 ps
CPU time 1.7 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:20:54 PM PDT 24
Peak memory 200364 kb
Host smart-34d7e422-39d4-4306-9e31-82d51d941ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229406292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.4229406292
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3819594692
Short name T133
Test name
Test status
Simulation time 70078425 ps
CPU time 0.78 seconds
Started Jul 10 07:20:49 PM PDT 24
Finished Jul 10 07:20:51 PM PDT 24
Peak memory 200028 kb
Host smart-0c405ab8-eee4-44ce-a291-7c988503641c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819594692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3819594692
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.4078116346
Short name T58
Test name
Test status
Simulation time 1897883287 ps
CPU time 7.37 seconds
Started Jul 10 07:20:49 PM PDT 24
Finished Jul 10 07:20:58 PM PDT 24
Peak memory 229964 kb
Host smart-40b33bd7-8e2d-4f04-bbb4-90ffb63298f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078116346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.4078116346
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.69255924
Short name T197
Test name
Test status
Simulation time 244232675 ps
CPU time 1.12 seconds
Started Jul 10 07:20:51 PM PDT 24
Finished Jul 10 07:20:55 PM PDT 24
Peak memory 217532 kb
Host smart-e83dbcda-c709-4303-923f-88e8ef4885bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69255924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.69255924
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4155911424
Short name T11
Test name
Test status
Simulation time 209078900 ps
CPU time 0.99 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:20:53 PM PDT 24
Peak memory 199984 kb
Host smart-b9950417-84c9-434c-9ac9-07da42137f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155911424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4155911424
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.407948202
Short name T97
Test name
Test status
Simulation time 1684798009 ps
CPU time 5.73 seconds
Started Jul 10 07:20:50 PM PDT 24
Finished Jul 10 07:20:58 PM PDT 24
Peak memory 200412 kb
Host smart-1d8e42f7-903e-4284-900e-f2272057ae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407948202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.407948202
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1051494494
Short name T516
Test name
Test status
Simulation time 99706706 ps
CPU time 1.04 seconds
Started Jul 10 07:20:53 PM PDT 24
Finished Jul 10 07:20:57 PM PDT 24
Peak memory 200160 kb
Host smart-a2293744-24de-45d3-986b-3f26b298de51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051494494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1051494494
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.4255927496
Short name T246
Test name
Test status
Simulation time 229080170 ps
CPU time 1.41 seconds
Started Jul 10 07:20:53 PM PDT 24
Finished Jul 10 07:20:57 PM PDT 24
Peak memory 200348 kb
Host smart-0b40ac73-1282-485f-8b69-55800624d6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255927496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.4255927496
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3518246402
Short name T253
Test name
Test status
Simulation time 7601094270 ps
CPU time 28.64 seconds
Started Jul 10 07:20:51 PM PDT 24
Finished Jul 10 07:21:22 PM PDT 24
Peak memory 208696 kb
Host smart-6058a444-24f7-4e8c-973d-8eb4a5609e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518246402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3518246402
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2803479021
Short name T415
Test name
Test status
Simulation time 150408301 ps
CPU time 1.84 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:20:56 PM PDT 24
Peak memory 200188 kb
Host smart-7113b34d-35a4-4030-b34d-a1274ed4c4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803479021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2803479021
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1003608172
Short name T132
Test name
Test status
Simulation time 234125236 ps
CPU time 1.43 seconds
Started Jul 10 07:20:51 PM PDT 24
Finished Jul 10 07:20:56 PM PDT 24
Peak memory 200300 kb
Host smart-d4669062-6ceb-4a04-ace0-c8d355b3cec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003608172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1003608172
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2399313296
Short name T286
Test name
Test status
Simulation time 68275386 ps
CPU time 0.82 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:20:55 PM PDT 24
Peak memory 199964 kb
Host smart-f81f6928-db4c-497d-9362-58f738be2645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399313296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2399313296
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1971862373
Short name T213
Test name
Test status
Simulation time 2379514901 ps
CPU time 8.01 seconds
Started Jul 10 07:20:51 PM PDT 24
Finished Jul 10 07:21:02 PM PDT 24
Peak memory 217256 kb
Host smart-1af04ee4-dec3-4cf8-8661-a1c790176c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971862373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1971862373
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1023389304
Short name T436
Test name
Test status
Simulation time 247818879 ps
CPU time 1.09 seconds
Started Jul 10 07:20:47 PM PDT 24
Finished Jul 10 07:20:50 PM PDT 24
Peak memory 217532 kb
Host smart-9dc26fb5-c8cf-457a-b6b3-80d716fe1cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023389304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1023389304
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3151461273
Short name T350
Test name
Test status
Simulation time 91284999 ps
CPU time 0.77 seconds
Started Jul 10 07:20:48 PM PDT 24
Finished Jul 10 07:20:50 PM PDT 24
Peak memory 200044 kb
Host smart-f181ee1a-9177-4b28-bac1-c7ac5b94c09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151461273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3151461273
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1533144469
Short name T383
Test name
Test status
Simulation time 894547142 ps
CPU time 4.44 seconds
Started Jul 10 07:20:54 PM PDT 24
Finished Jul 10 07:21:01 PM PDT 24
Peak memory 200412 kb
Host smart-7f44c115-f3b9-40b3-b7f1-97c510263059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533144469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1533144469
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3672957404
Short name T399
Test name
Test status
Simulation time 145404403 ps
CPU time 1.09 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:20:55 PM PDT 24
Peak memory 200168 kb
Host smart-79a19d3f-1125-4d81-b55f-8999b2350a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672957404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3672957404
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1198069706
Short name T498
Test name
Test status
Simulation time 113704352 ps
CPU time 1.18 seconds
Started Jul 10 07:20:49 PM PDT 24
Finished Jul 10 07:20:51 PM PDT 24
Peak memory 200344 kb
Host smart-57fbecb1-4240-4682-be57-302bc4c57c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198069706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1198069706
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1350960487
Short name T210
Test name
Test status
Simulation time 13430307830 ps
CPU time 50.51 seconds
Started Jul 10 07:20:49 PM PDT 24
Finished Jul 10 07:21:42 PM PDT 24
Peak memory 210596 kb
Host smart-d58cfb01-ca87-49ff-bc64-1445058f6672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350960487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1350960487
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3433391444
Short name T355
Test name
Test status
Simulation time 131610347 ps
CPU time 1.56 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:20:56 PM PDT 24
Peak memory 208324 kb
Host smart-0e34823a-54b3-460c-bd52-361171660dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433391444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3433391444
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1581916298
Short name T441
Test name
Test status
Simulation time 181330293 ps
CPU time 1.25 seconds
Started Jul 10 07:20:51 PM PDT 24
Finished Jul 10 07:20:55 PM PDT 24
Peak memory 200176 kb
Host smart-72b50e67-b40b-4f86-9178-7e39ce7a8354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581916298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1581916298
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3596100863
Short name T266
Test name
Test status
Simulation time 66779167 ps
CPU time 0.73 seconds
Started Jul 10 07:20:07 PM PDT 24
Finished Jul 10 07:20:09 PM PDT 24
Peak memory 199952 kb
Host smart-501e7127-9e1f-4cdf-9366-2311c667fc17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596100863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3596100863
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2872122673
Short name T479
Test name
Test status
Simulation time 1230248184 ps
CPU time 5.7 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:05 PM PDT 24
Peak memory 221708 kb
Host smart-0a5674ad-00b9-4c71-bff8-a605ee13f3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872122673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2872122673
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2863613548
Short name T463
Test name
Test status
Simulation time 244455367 ps
CPU time 1.12 seconds
Started Jul 10 07:20:01 PM PDT 24
Finished Jul 10 07:20:04 PM PDT 24
Peak memory 217516 kb
Host smart-0f4712f5-d9d8-4171-b74b-b7e5e1144e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863613548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2863613548
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.718527883
Short name T386
Test name
Test status
Simulation time 126659545 ps
CPU time 0.86 seconds
Started Jul 10 07:19:59 PM PDT 24
Finished Jul 10 07:20:02 PM PDT 24
Peak memory 199968 kb
Host smart-ddaee070-3141-4b47-94ea-63191770d5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718527883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.718527883
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3948232109
Short name T520
Test name
Test status
Simulation time 912293491 ps
CPU time 4.66 seconds
Started Jul 10 07:20:02 PM PDT 24
Finished Jul 10 07:20:09 PM PDT 24
Peak memory 200424 kb
Host smart-f1490d94-1f24-4a2c-a0f9-ebe9ce97d79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948232109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3948232109
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.526993015
Short name T74
Test name
Test status
Simulation time 8298144171 ps
CPU time 15.34 seconds
Started Jul 10 07:19:56 PM PDT 24
Finished Jul 10 07:20:12 PM PDT 24
Peak memory 217272 kb
Host smart-46c334d7-0825-40da-9c65-76d0700403b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526993015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.526993015
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.965731333
Short name T506
Test name
Test status
Simulation time 187116790 ps
CPU time 1.29 seconds
Started Jul 10 07:20:01 PM PDT 24
Finished Jul 10 07:20:05 PM PDT 24
Peak memory 200096 kb
Host smart-6c3f239c-409a-4f19-8c8d-ad5fa3a000e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965731333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.965731333
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.674158620
Short name T470
Test name
Test status
Simulation time 195458774 ps
CPU time 1.33 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:02 PM PDT 24
Peak memory 200436 kb
Host smart-5d907dce-2db6-4614-a3af-97fa1d878be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674158620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.674158620
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2939373905
Short name T303
Test name
Test status
Simulation time 1527785931 ps
CPU time 5.6 seconds
Started Jul 10 07:20:08 PM PDT 24
Finished Jul 10 07:20:15 PM PDT 24
Peak memory 200412 kb
Host smart-78081433-a089-4813-bfd0-409937fc1740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939373905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2939373905
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.446966713
Short name T204
Test name
Test status
Simulation time 464950312 ps
CPU time 2.55 seconds
Started Jul 10 07:20:08 PM PDT 24
Finished Jul 10 07:20:12 PM PDT 24
Peak memory 208352 kb
Host smart-67226392-1155-4b4b-93bf-c7e465fca9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446966713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.446966713
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3895226018
Short name T400
Test name
Test status
Simulation time 82200576 ps
CPU time 0.94 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:02 PM PDT 24
Peak memory 200108 kb
Host smart-c8d83487-2647-40f1-b7ba-1330ca044a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895226018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3895226018
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1756915630
Short name T511
Test name
Test status
Simulation time 62867204 ps
CPU time 0.76 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:20:56 PM PDT 24
Peak memory 199944 kb
Host smart-ada920c2-4b2e-49fd-8c47-964383345c62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756915630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1756915630
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.827176430
Short name T525
Test name
Test status
Simulation time 2352129763 ps
CPU time 8.6 seconds
Started Jul 10 07:21:00 PM PDT 24
Finished Jul 10 07:21:10 PM PDT 24
Peak memory 229952 kb
Host smart-c9ff727a-38aa-4067-87de-4dc1c4270f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827176430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.827176430
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1750058715
Short name T179
Test name
Test status
Simulation time 244693815 ps
CPU time 1.06 seconds
Started Jul 10 07:20:56 PM PDT 24
Finished Jul 10 07:20:59 PM PDT 24
Peak memory 217524 kb
Host smart-0285da1d-a527-40cc-b3df-e79552344065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750058715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1750058715
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1938709516
Short name T164
Test name
Test status
Simulation time 197070200 ps
CPU time 0.91 seconds
Started Jul 10 07:20:56 PM PDT 24
Finished Jul 10 07:20:58 PM PDT 24
Peak memory 199984 kb
Host smart-8f098dcd-6a89-4bdc-886a-1da0ec97ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938709516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1938709516
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3784098559
Short name T377
Test name
Test status
Simulation time 829614694 ps
CPU time 4.32 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:20:58 PM PDT 24
Peak memory 200412 kb
Host smart-58e41982-c154-40e7-81ea-ca694a4a592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784098559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3784098559
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2588924660
Short name T442
Test name
Test status
Simulation time 186993267 ps
CPU time 1.29 seconds
Started Jul 10 07:20:56 PM PDT 24
Finished Jul 10 07:20:59 PM PDT 24
Peak memory 200168 kb
Host smart-13e8f083-25c8-4120-a2f8-3503efff8ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588924660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2588924660
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2513395655
Short name T285
Test name
Test status
Simulation time 114155999 ps
CPU time 1.26 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:20:57 PM PDT 24
Peak memory 200392 kb
Host smart-58b61336-9858-41e9-a156-b1dc2b93afb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513395655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2513395655
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4020473588
Short name T362
Test name
Test status
Simulation time 450447666 ps
CPU time 2.71 seconds
Started Jul 10 07:20:59 PM PDT 24
Finished Jul 10 07:21:03 PM PDT 24
Peak memory 200136 kb
Host smart-60e5f16c-04eb-4082-8005-02cb1dec9714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020473588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4020473588
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1293148740
Short name T512
Test name
Test status
Simulation time 95106198 ps
CPU time 0.91 seconds
Started Jul 10 07:20:52 PM PDT 24
Finished Jul 10 07:20:56 PM PDT 24
Peak memory 200156 kb
Host smart-825a2a7b-2b29-4279-8da5-c01d1eae81b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293148740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1293148740
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.393375155
Short name T531
Test name
Test status
Simulation time 63078874 ps
CPU time 0.75 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:14 PM PDT 24
Peak memory 199948 kb
Host smart-e0aa6cef-2108-4c38-9dc3-29fa8f4a5438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393375155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.393375155
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1005027422
Short name T398
Test name
Test status
Simulation time 1231155774 ps
CPU time 5.35 seconds
Started Jul 10 07:21:14 PM PDT 24
Finished Jul 10 07:21:21 PM PDT 24
Peak memory 217728 kb
Host smart-709e099c-3403-47d9-a94c-7b9931dd4f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005027422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1005027422
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1825978273
Short name T365
Test name
Test status
Simulation time 245357188 ps
CPU time 1.03 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:11 PM PDT 24
Peak memory 217504 kb
Host smart-e880c13f-3c13-4f71-8643-fd14b7d18265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825978273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1825978273
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1342123405
Short name T160
Test name
Test status
Simulation time 100246227 ps
CPU time 0.78 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:14 PM PDT 24
Peak memory 199972 kb
Host smart-1587bdd1-4b05-42e9-bce9-b3b1600b8e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342123405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1342123405
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3267060291
Short name T264
Test name
Test status
Simulation time 851670604 ps
CPU time 4.21 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:17 PM PDT 24
Peak memory 200420 kb
Host smart-ddf074cc-fd0f-4f2d-9d76-681e8a3a56d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267060291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3267060291
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2812776729
Short name T300
Test name
Test status
Simulation time 176279589 ps
CPU time 1.22 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:10 PM PDT 24
Peak memory 200156 kb
Host smart-06662266-dd2e-40e5-b53f-80a7f298ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812776729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2812776729
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2869440736
Short name T99
Test name
Test status
Simulation time 4271944330 ps
CPU time 22 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:36 PM PDT 24
Peak memory 208672 kb
Host smart-fd3b31b9-f8a9-4e09-a396-2ff9f02cc3a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869440736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2869440736
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1684364972
Short name T35
Test name
Test status
Simulation time 291574270 ps
CPU time 1.95 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:12 PM PDT 24
Peak memory 200144 kb
Host smart-e71fe1bd-ebe8-4b72-943f-aa50c04310f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684364972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1684364972
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1155843538
Short name T371
Test name
Test status
Simulation time 148276340 ps
CPU time 1.13 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:13 PM PDT 24
Peak memory 200180 kb
Host smart-8a074eb9-9081-4742-8db4-8fb4b49b7f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155843538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1155843538
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2694793792
Short name T21
Test name
Test status
Simulation time 68123222 ps
CPU time 0.79 seconds
Started Jul 10 07:21:11 PM PDT 24
Finished Jul 10 07:21:16 PM PDT 24
Peak memory 199968 kb
Host smart-fd4b21c8-ce1b-412d-9dfc-930ed75e1209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694793792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2694793792
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2636833282
Short name T33
Test name
Test status
Simulation time 2358679787 ps
CPU time 8.75 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:23 PM PDT 24
Peak memory 217920 kb
Host smart-0bce6eba-5432-44a7-a7b6-ce5f854dc502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636833282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2636833282
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.270829481
Short name T228
Test name
Test status
Simulation time 243734638 ps
CPU time 1.12 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:11 PM PDT 24
Peak memory 217512 kb
Host smart-fdba6ce8-e930-4851-98e3-f8b3b5dd20af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270829481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.270829481
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.4284736102
Short name T14
Test name
Test status
Simulation time 106736508 ps
CPU time 0.77 seconds
Started Jul 10 07:21:07 PM PDT 24
Finished Jul 10 07:21:09 PM PDT 24
Peak memory 199972 kb
Host smart-b350f367-d136-4864-b897-c8af98b13b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284736102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.4284736102
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.590061162
Short name T464
Test name
Test status
Simulation time 984122742 ps
CPU time 5.13 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:19 PM PDT 24
Peak memory 200388 kb
Host smart-7b21d218-b71f-4bdd-8e64-0aaa46d48d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590061162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.590061162
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2235199311
Short name T409
Test name
Test status
Simulation time 112863005 ps
CPU time 1.04 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:12 PM PDT 24
Peak memory 200228 kb
Host smart-3af00e92-b8e1-4be8-aadf-e3062587d99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235199311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2235199311
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1324279595
Short name T321
Test name
Test status
Simulation time 124073180 ps
CPU time 1.15 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:13 PM PDT 24
Peak memory 200344 kb
Host smart-35d8fac0-d6e8-49d0-8327-9331e3804dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324279595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1324279595
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2399605895
Short name T217
Test name
Test status
Simulation time 16793033693 ps
CPU time 58.76 seconds
Started Jul 10 07:21:13 PM PDT 24
Finished Jul 10 07:22:14 PM PDT 24
Peak memory 200488 kb
Host smart-fe094967-2832-4ec4-a6b0-2fdab36ef7a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399605895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2399605895
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4233010650
Short name T422
Test name
Test status
Simulation time 366244773 ps
CPU time 1.98 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:16 PM PDT 24
Peak memory 200136 kb
Host smart-d174c9d4-c71e-4ca1-8eb6-1ba1dfa2bb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233010650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4233010650
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1897422167
Short name T130
Test name
Test status
Simulation time 190147632 ps
CPU time 1.35 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:11 PM PDT 24
Peak memory 200164 kb
Host smart-01a41aff-d1c5-4d80-818d-f2e201e33b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897422167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1897422167
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2708019425
Short name T139
Test name
Test status
Simulation time 69938090 ps
CPU time 0.76 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:15 PM PDT 24
Peak memory 200028 kb
Host smart-ae505653-14c7-4956-b4ac-e5048ff3e822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708019425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2708019425
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.440900752
Short name T461
Test name
Test status
Simulation time 1223622985 ps
CPU time 5.66 seconds
Started Jul 10 07:21:11 PM PDT 24
Finished Jul 10 07:21:20 PM PDT 24
Peak memory 221752 kb
Host smart-b6b027c9-4073-4221-a2d6-f74b45e92ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440900752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.440900752
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2343029962
Short name T214
Test name
Test status
Simulation time 244736119 ps
CPU time 1.09 seconds
Started Jul 10 07:21:12 PM PDT 24
Finished Jul 10 07:21:16 PM PDT 24
Peak memory 217708 kb
Host smart-2404708d-00ca-4ffd-838a-f9ff1c4ff5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343029962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2343029962
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.4233043944
Short name T19
Test name
Test status
Simulation time 90699277 ps
CPU time 0.77 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:14 PM PDT 24
Peak memory 199928 kb
Host smart-b230bdc7-ac5d-441b-bdbf-49985c68c22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233043944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.4233043944
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3353197215
Short name T288
Test name
Test status
Simulation time 1129238927 ps
CPU time 4.84 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:19 PM PDT 24
Peak memory 200392 kb
Host smart-477289de-5c50-465e-b1e8-e6863c213d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353197215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3353197215
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.103157108
Short name T390
Test name
Test status
Simulation time 176529770 ps
CPU time 1.25 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:14 PM PDT 24
Peak memory 200232 kb
Host smart-fa8a380e-9377-4233-96d6-b2ba911802f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103157108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.103157108
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.645370507
Short name T351
Test name
Test status
Simulation time 193705463 ps
CPU time 1.29 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:14 PM PDT 24
Peak memory 200324 kb
Host smart-a8fa60bf-4cb4-446d-9631-adc77bacde45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645370507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.645370507
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.4036326934
Short name T488
Test name
Test status
Simulation time 3805815669 ps
CPU time 18.63 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:32 PM PDT 24
Peak memory 208796 kb
Host smart-7ea3a302-9c3c-4b1c-9332-bee16fa27aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036326934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.4036326934
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2505457867
Short name T328
Test name
Test status
Simulation time 332665595 ps
CPU time 2.45 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:17 PM PDT 24
Peak memory 208344 kb
Host smart-87698948-8e8b-449e-8925-0817878ba2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505457867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2505457867
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3034749917
Short name T314
Test name
Test status
Simulation time 134832819 ps
CPU time 1.22 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:11 PM PDT 24
Peak memory 200176 kb
Host smart-bdb57eb3-ac3e-4ebb-8069-c620e701db84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034749917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3034749917
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.419808329
Short name T244
Test name
Test status
Simulation time 65249449 ps
CPU time 0.82 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:13 PM PDT 24
Peak memory 199968 kb
Host smart-38f9d8e6-f88f-4a6e-82ab-076267f48bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419808329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.419808329
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2689892573
Short name T490
Test name
Test status
Simulation time 2367666736 ps
CPU time 9.74 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:24 PM PDT 24
Peak memory 221836 kb
Host smart-e91faffb-2583-4d85-b031-b3f4cdfbb507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689892573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2689892573
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1164706100
Short name T299
Test name
Test status
Simulation time 243661970 ps
CPU time 1.13 seconds
Started Jul 10 07:21:11 PM PDT 24
Finished Jul 10 07:21:16 PM PDT 24
Peak memory 217524 kb
Host smart-6bbf2b1d-5e62-4114-a955-2447d740c2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164706100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1164706100
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3466141627
Short name T147
Test name
Test status
Simulation time 117440676 ps
CPU time 0.82 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:15 PM PDT 24
Peak memory 199624 kb
Host smart-9305f2f6-0e34-4524-b36c-da7cf646f6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466141627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3466141627
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3709868719
Short name T237
Test name
Test status
Simulation time 1562800910 ps
CPU time 6.59 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:21 PM PDT 24
Peak memory 200300 kb
Host smart-6f3a8915-7d8c-4b24-a16d-02876a8458cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709868719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3709868719
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1974469416
Short name T203
Test name
Test status
Simulation time 140819002 ps
CPU time 1.17 seconds
Started Jul 10 07:21:07 PM PDT 24
Finished Jul 10 07:21:09 PM PDT 24
Peak memory 200156 kb
Host smart-15759d30-5f75-49d8-8921-08b40597c690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974469416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1974469416
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.261885039
Short name T393
Test name
Test status
Simulation time 247578403 ps
CPU time 1.69 seconds
Started Jul 10 07:21:07 PM PDT 24
Finished Jul 10 07:21:10 PM PDT 24
Peak memory 200348 kb
Host smart-a44eb49f-e34b-47ea-a930-43c028d36fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261885039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.261885039
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2071701110
Short name T187
Test name
Test status
Simulation time 4588529878 ps
CPU time 21.14 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:31 PM PDT 24
Peak memory 200488 kb
Host smart-051ead89-065a-4152-900a-cf27f5c629fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071701110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2071701110
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.837041188
Short name T439
Test name
Test status
Simulation time 431612449 ps
CPU time 2.27 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:16 PM PDT 24
Peak memory 208396 kb
Host smart-913f45e8-34fa-4214-8d6c-94d50acf094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837041188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.837041188
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2653809296
Short name T456
Test name
Test status
Simulation time 87236914 ps
CPU time 0.89 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:12 PM PDT 24
Peak memory 200156 kb
Host smart-a94ed2f5-1779-4d0d-89c6-85c28794fd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653809296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2653809296
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.839568102
Short name T345
Test name
Test status
Simulation time 90743075 ps
CPU time 0.88 seconds
Started Jul 10 07:21:13 PM PDT 24
Finished Jul 10 07:21:16 PM PDT 24
Peak memory 199960 kb
Host smart-7f839223-84c7-4ea9-b89a-934901374ffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839568102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.839568102
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2721041852
Short name T206
Test name
Test status
Simulation time 244281358 ps
CPU time 1.18 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:14 PM PDT 24
Peak memory 217480 kb
Host smart-0fca9b26-b326-499a-a6bc-f56e1d4ba129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721041852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2721041852
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.842640951
Short name T81
Test name
Test status
Simulation time 102951413 ps
CPU time 0.81 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:12 PM PDT 24
Peak memory 199984 kb
Host smart-974dc988-df94-489b-9b60-fb835ba6fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842640951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.842640951
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1665806300
Short name T220
Test name
Test status
Simulation time 1805090468 ps
CPU time 7.66 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:17 PM PDT 24
Peak memory 200396 kb
Host smart-ed28496f-fc13-4761-9f96-c0f63c642b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665806300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1665806300
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4249480521
Short name T222
Test name
Test status
Simulation time 165490192 ps
CPU time 1.2 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:13 PM PDT 24
Peak memory 200172 kb
Host smart-9882c987-7dc1-4339-94c7-49f5a7d134a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249480521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4249480521
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1501290342
Short name T174
Test name
Test status
Simulation time 119401497 ps
CPU time 1.21 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:14 PM PDT 24
Peak memory 200392 kb
Host smart-b73fed4f-853a-4056-8702-dc52e8a2a47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501290342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1501290342
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1728764358
Short name T443
Test name
Test status
Simulation time 7034623498 ps
CPU time 27.28 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:41 PM PDT 24
Peak memory 208696 kb
Host smart-516bef18-70fb-45d5-a5b3-30eb78dd15aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728764358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1728764358
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.328677162
Short name T486
Test name
Test status
Simulation time 276363518 ps
CPU time 2.01 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:14 PM PDT 24
Peak memory 200168 kb
Host smart-74b30410-6bb9-4a45-977b-d39447da94f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328677162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.328677162
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.106563950
Short name T528
Test name
Test status
Simulation time 155320675 ps
CPU time 1.3 seconds
Started Jul 10 07:21:06 PM PDT 24
Finished Jul 10 07:21:09 PM PDT 24
Peak memory 200364 kb
Host smart-6777411f-3b0b-4723-9a7c-f82fa9eba2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106563950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.106563950
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1353478599
Short name T348
Test name
Test status
Simulation time 79609669 ps
CPU time 0.87 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:15 PM PDT 24
Peak memory 199956 kb
Host smart-8e1bd102-4310-4ceb-84f7-1f4fc928346b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353478599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1353478599
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2011960520
Short name T205
Test name
Test status
Simulation time 1892299486 ps
CPU time 7.27 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:20 PM PDT 24
Peak memory 217764 kb
Host smart-5fffb8e3-2625-4900-b9a9-c6715330b1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011960520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2011960520
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2500647198
Short name T353
Test name
Test status
Simulation time 244158029 ps
CPU time 1.1 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:15 PM PDT 24
Peak memory 217532 kb
Host smart-3f5044cd-0b8c-4fd1-9c03-9915f8f99d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500647198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2500647198
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3766588801
Short name T271
Test name
Test status
Simulation time 186491106 ps
CPU time 0.89 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:15 PM PDT 24
Peak memory 199968 kb
Host smart-ba9d39f6-eb86-4096-84c6-e66224037ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766588801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3766588801
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.675334275
Short name T347
Test name
Test status
Simulation time 1493421569 ps
CPU time 6.42 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:19 PM PDT 24
Peak memory 200476 kb
Host smart-b8d84c0a-84d0-49c0-98a9-7a199196e047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675334275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.675334275
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1614580007
Short name T185
Test name
Test status
Simulation time 111078915 ps
CPU time 1.01 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:13 PM PDT 24
Peak memory 200172 kb
Host smart-95c899a5-ab0e-41b0-956d-5cb303d41c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614580007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1614580007
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.124051736
Short name T359
Test name
Test status
Simulation time 200194080 ps
CPU time 1.43 seconds
Started Jul 10 07:21:08 PM PDT 24
Finished Jul 10 07:21:11 PM PDT 24
Peak memory 200360 kb
Host smart-e1039d99-7eab-45fa-be98-afd95d0aef2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124051736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.124051736
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2848516816
Short name T527
Test name
Test status
Simulation time 6422663079 ps
CPU time 26.98 seconds
Started Jul 10 07:21:12 PM PDT 24
Finished Jul 10 07:21:42 PM PDT 24
Peak memory 200688 kb
Host smart-d2b924ef-6f20-4b06-bbfb-ead202fbeaba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848516816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2848516816
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2982363599
Short name T324
Test name
Test status
Simulation time 124326524 ps
CPU time 1.57 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:15 PM PDT 24
Peak memory 200196 kb
Host smart-64daee96-8375-4825-8d38-01968cfb2b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982363599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2982363599
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.4132043217
Short name T521
Test name
Test status
Simulation time 122953841 ps
CPU time 1.02 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:14 PM PDT 24
Peak memory 200232 kb
Host smart-8aa0b354-69c9-44ce-861b-8d71db63340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132043217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.4132043217
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1325751683
Short name T186
Test name
Test status
Simulation time 67367161 ps
CPU time 0.81 seconds
Started Jul 10 07:21:19 PM PDT 24
Finished Jul 10 07:21:22 PM PDT 24
Peak memory 199964 kb
Host smart-ad941e1a-c6c4-4574-b024-ed7749ad792e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325751683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1325751683
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2389859081
Short name T471
Test name
Test status
Simulation time 2363958594 ps
CPU time 8.11 seconds
Started Jul 10 07:21:11 PM PDT 24
Finished Jul 10 07:21:23 PM PDT 24
Peak memory 221784 kb
Host smart-ce1e1a89-8020-4eb7-8e83-9afaed6828c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389859081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2389859081
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3291420921
Short name T500
Test name
Test status
Simulation time 244279398 ps
CPU time 1.13 seconds
Started Jul 10 07:21:11 PM PDT 24
Finished Jul 10 07:21:16 PM PDT 24
Peak memory 217512 kb
Host smart-b4b2cb2c-af78-4fbe-949a-4bfad5324a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291420921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3291420921
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1978595153
Short name T221
Test name
Test status
Simulation time 101564435 ps
CPU time 0.8 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:15 PM PDT 24
Peak memory 199952 kb
Host smart-d4b002c6-e8cc-4418-8f71-3c61ee0a1859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978595153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1978595153
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3889233156
Short name T514
Test name
Test status
Simulation time 739695037 ps
CPU time 3.85 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:17 PM PDT 24
Peak memory 200412 kb
Host smart-86bd1a5c-d985-48f2-823b-3a7c4b7c3402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889233156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3889233156
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3033396911
Short name T191
Test name
Test status
Simulation time 108901637 ps
CPU time 1.05 seconds
Started Jul 10 07:21:13 PM PDT 24
Finished Jul 10 07:21:17 PM PDT 24
Peak memory 199980 kb
Host smart-a4c40126-0233-4c94-9ff9-464804cbcaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033396911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3033396911
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1329394959
Short name T276
Test name
Test status
Simulation time 122538182 ps
CPU time 1.23 seconds
Started Jul 10 07:21:09 PM PDT 24
Finished Jul 10 07:21:13 PM PDT 24
Peak memory 200356 kb
Host smart-b041ea5b-f132-4d68-a1b4-b68964429248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329394959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1329394959
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1519541180
Short name T277
Test name
Test status
Simulation time 1606329657 ps
CPU time 6.21 seconds
Started Jul 10 07:21:13 PM PDT 24
Finished Jul 10 07:21:22 PM PDT 24
Peak memory 208496 kb
Host smart-3d1fe6ea-f7cc-41c3-8893-8647eb040cd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519541180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1519541180
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3642473549
Short name T291
Test name
Test status
Simulation time 129330346 ps
CPU time 1.75 seconds
Started Jul 10 07:21:10 PM PDT 24
Finished Jul 10 07:21:16 PM PDT 24
Peak memory 208328 kb
Host smart-0173990b-2834-4439-aedb-adc9797e4f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642473549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3642473549
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3451557712
Short name T40
Test name
Test status
Simulation time 155402339 ps
CPU time 1.16 seconds
Started Jul 10 07:21:14 PM PDT 24
Finished Jul 10 07:21:17 PM PDT 24
Peak memory 200084 kb
Host smart-1366f062-a26a-405a-937b-7bc50ccca147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451557712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3451557712
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3795331080
Short name T262
Test name
Test status
Simulation time 65615505 ps
CPU time 0.8 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:27 PM PDT 24
Peak memory 199916 kb
Host smart-c6fbe6ed-a203-469b-ae0c-1076db0a879d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795331080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3795331080
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3990937020
Short name T31
Test name
Test status
Simulation time 1217573692 ps
CPU time 6.2 seconds
Started Jul 10 07:21:16 PM PDT 24
Finished Jul 10 07:21:24 PM PDT 24
Peak memory 221696 kb
Host smart-ed276791-dfd9-4bd4-bfdc-a7702c5efded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990937020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3990937020
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3068027611
Short name T52
Test name
Test status
Simulation time 244916570 ps
CPU time 1.16 seconds
Started Jul 10 07:21:20 PM PDT 24
Finished Jul 10 07:21:23 PM PDT 24
Peak memory 217516 kb
Host smart-72a3ba0b-53b7-4398-8710-7406e08aca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068027611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3068027611
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1793856584
Short name T326
Test name
Test status
Simulation time 231038990 ps
CPU time 0.9 seconds
Started Jul 10 07:21:18 PM PDT 24
Finished Jul 10 07:21:21 PM PDT 24
Peak memory 199988 kb
Host smart-b9ecabc8-b8cc-4b1a-8575-9e06aed8c8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793856584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1793856584
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2970271548
Short name T376
Test name
Test status
Simulation time 1511837604 ps
CPU time 6.25 seconds
Started Jul 10 07:21:17 PM PDT 24
Finished Jul 10 07:21:25 PM PDT 24
Peak memory 200424 kb
Host smart-1e6ce776-8450-4a29-9bd3-bfe1ff6b023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970271548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2970271548
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.4097051961
Short name T273
Test name
Test status
Simulation time 148248438 ps
CPU time 1.08 seconds
Started Jul 10 07:21:22 PM PDT 24
Finished Jul 10 07:21:24 PM PDT 24
Peak memory 200168 kb
Host smart-7473749d-f081-433a-aacf-81fff6392673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097051961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.4097051961
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2086951098
Short name T454
Test name
Test status
Simulation time 117320035 ps
CPU time 1.21 seconds
Started Jul 10 07:21:22 PM PDT 24
Finished Jul 10 07:21:25 PM PDT 24
Peak memory 200360 kb
Host smart-fd06c12a-ed65-4227-a1b8-21cbb7ca5da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086951098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2086951098
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3958750035
Short name T361
Test name
Test status
Simulation time 2568209819 ps
CPU time 10.22 seconds
Started Jul 10 07:21:17 PM PDT 24
Finished Jul 10 07:21:30 PM PDT 24
Peak memory 216816 kb
Host smart-1dd720e0-8258-461c-9610-149d594fa4ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958750035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3958750035
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2108860317
Short name T274
Test name
Test status
Simulation time 149658753 ps
CPU time 1.84 seconds
Started Jul 10 07:21:16 PM PDT 24
Finished Jul 10 07:21:19 PM PDT 24
Peak memory 200152 kb
Host smart-60411e0f-ee63-436e-a164-bc6c60643c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108860317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2108860317
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3917572846
Short name T80
Test name
Test status
Simulation time 140111432 ps
CPU time 1.01 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:27 PM PDT 24
Peak memory 200164 kb
Host smart-b3dd12ed-dc22-4750-a617-fed6e8acf5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917572846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3917572846
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.467177162
Short name T131
Test name
Test status
Simulation time 69564456 ps
CPU time 0.79 seconds
Started Jul 10 07:21:16 PM PDT 24
Finished Jul 10 07:21:18 PM PDT 24
Peak memory 199932 kb
Host smart-0e882722-ea09-4ced-a00b-b4cc805a13d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467177162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.467177162
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.321667855
Short name T296
Test name
Test status
Simulation time 2167848934 ps
CPU time 7.39 seconds
Started Jul 10 07:21:18 PM PDT 24
Finished Jul 10 07:21:27 PM PDT 24
Peak memory 217120 kb
Host smart-74a168e9-b680-4d72-9232-7bdac66ed711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321667855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.321667855
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1218738737
Short name T250
Test name
Test status
Simulation time 244412986 ps
CPU time 1.13 seconds
Started Jul 10 07:21:18 PM PDT 24
Finished Jul 10 07:21:21 PM PDT 24
Peak memory 217536 kb
Host smart-9e5926bd-478c-4799-8b5b-efb4a14bd529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218738737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1218738737
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.874856982
Short name T16
Test name
Test status
Simulation time 193288639 ps
CPU time 0.93 seconds
Started Jul 10 07:21:19 PM PDT 24
Finished Jul 10 07:21:23 PM PDT 24
Peak memory 199980 kb
Host smart-30138cde-bf74-4d05-aa10-e17faec95449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874856982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.874856982
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.4036799317
Short name T366
Test name
Test status
Simulation time 1044618647 ps
CPU time 5.38 seconds
Started Jul 10 07:21:16 PM PDT 24
Finished Jul 10 07:21:23 PM PDT 24
Peak memory 200388 kb
Host smart-a9c0c55c-a860-4b6a-a18e-df5972b28a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036799317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.4036799317
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.646602778
Short name T248
Test name
Test status
Simulation time 178620476 ps
CPU time 1.13 seconds
Started Jul 10 07:21:18 PM PDT 24
Finished Jul 10 07:21:21 PM PDT 24
Peak memory 200164 kb
Host smart-d545d3ad-e68d-415c-8dc1-8cb9321b9f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646602778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.646602778
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1825058936
Short name T281
Test name
Test status
Simulation time 189288735 ps
CPU time 1.36 seconds
Started Jul 10 07:21:18 PM PDT 24
Finished Jul 10 07:21:21 PM PDT 24
Peak memory 200348 kb
Host smart-1261b413-7c19-4969-af4f-1713ec4b5426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825058936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1825058936
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.186423071
Short name T388
Test name
Test status
Simulation time 7201036952 ps
CPU time 23.88 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:50 PM PDT 24
Peak memory 200476 kb
Host smart-545ba043-9fcd-46c9-8491-e14a88919ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186423071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.186423071
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4265764340
Short name T417
Test name
Test status
Simulation time 131695678 ps
CPU time 1.69 seconds
Started Jul 10 07:21:20 PM PDT 24
Finished Jul 10 07:21:24 PM PDT 24
Peak memory 200152 kb
Host smart-73ce46fb-0df4-4971-b22d-0447874b643b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265764340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4265764340
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.490839283
Short name T261
Test name
Test status
Simulation time 78692908 ps
CPU time 0.83 seconds
Started Jul 10 07:21:19 PM PDT 24
Finished Jul 10 07:21:22 PM PDT 24
Peak memory 200180 kb
Host smart-cd12eb32-8740-4822-b0bb-ac77e8400afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490839283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.490839283
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3146024212
Short name T346
Test name
Test status
Simulation time 68610226 ps
CPU time 0.86 seconds
Started Jul 10 07:20:00 PM PDT 24
Finished Jul 10 07:20:03 PM PDT 24
Peak memory 199952 kb
Host smart-4bd2b0c7-bc74-4c1d-a250-e4cc64e1f331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146024212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3146024212
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1115709847
Short name T333
Test name
Test status
Simulation time 1224003704 ps
CPU time 5.74 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:20:04 PM PDT 24
Peak memory 217804 kb
Host smart-e0acbdc2-e80e-474f-8622-4784b194b898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115709847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1115709847
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3612087466
Short name T536
Test name
Test status
Simulation time 245081564 ps
CPU time 1.07 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:01 PM PDT 24
Peak memory 217524 kb
Host smart-24064be5-3f69-4dff-bafc-c74d83e97f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612087466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3612087466
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1115733511
Short name T495
Test name
Test status
Simulation time 197944903 ps
CPU time 0.89 seconds
Started Jul 10 07:20:07 PM PDT 24
Finished Jul 10 07:20:09 PM PDT 24
Peak memory 199972 kb
Host smart-0a0d31c9-de28-4e27-b89c-7483ee0cc823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115733511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1115733511
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1192535415
Short name T444
Test name
Test status
Simulation time 1406995414 ps
CPU time 5.2 seconds
Started Jul 10 07:20:03 PM PDT 24
Finished Jul 10 07:20:11 PM PDT 24
Peak memory 200408 kb
Host smart-8c99b6a0-1b0a-4c31-ab68-d87811883c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192535415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1192535415
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1619466677
Short name T71
Test name
Test status
Simulation time 8304854525 ps
CPU time 13.79 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:20:11 PM PDT 24
Peak memory 217220 kb
Host smart-c2e36091-50b5-4510-a41e-fcf848c103db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619466677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1619466677
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.134834596
Short name T295
Test name
Test status
Simulation time 137278279 ps
CPU time 1.1 seconds
Started Jul 10 07:20:00 PM PDT 24
Finished Jul 10 07:20:04 PM PDT 24
Peak memory 200096 kb
Host smart-0f7e17e0-3b7c-4b25-ae30-fccc9d9ccfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134834596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.134834596
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3290504711
Short name T176
Test name
Test status
Simulation time 110038778 ps
CPU time 1.18 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:01 PM PDT 24
Peak memory 200328 kb
Host smart-ab655f79-af06-471f-9ea7-64e79e05df6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290504711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3290504711
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.946653890
Short name T354
Test name
Test status
Simulation time 7469129433 ps
CPU time 27.37 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:20:27 PM PDT 24
Peak memory 210388 kb
Host smart-d828f11b-fe1c-4ede-8ab0-83d05a3f5f4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946653890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.946653890
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1292592132
Short name T331
Test name
Test status
Simulation time 138945053 ps
CPU time 1.76 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:19:59 PM PDT 24
Peak memory 208356 kb
Host smart-217f3827-bc43-4706-b953-76840423358b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292592132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1292592132
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.225070549
Short name T223
Test name
Test status
Simulation time 100164536 ps
CPU time 0.91 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:00 PM PDT 24
Peak memory 200164 kb
Host smart-f92225d4-1535-42ca-aef8-83dbfe692c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225070549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.225070549
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2488212152
Short name T8
Test name
Test status
Simulation time 52831127 ps
CPU time 0.74 seconds
Started Jul 10 07:21:20 PM PDT 24
Finished Jul 10 07:21:23 PM PDT 24
Peak memory 199948 kb
Host smart-885ba3bc-a379-493e-a455-ae4e06b10558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488212152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2488212152
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2959615184
Short name T56
Test name
Test status
Simulation time 1898260003 ps
CPU time 7.16 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:33 PM PDT 24
Peak memory 217804 kb
Host smart-c7319ce8-880f-48b6-a89f-328d77948f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959615184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2959615184
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.159388746
Short name T485
Test name
Test status
Simulation time 244742621 ps
CPU time 1.03 seconds
Started Jul 10 07:21:17 PM PDT 24
Finished Jul 10 07:21:20 PM PDT 24
Peak memory 217492 kb
Host smart-ad17f8cf-d80c-4a9f-bb2c-8a5d5ed60f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159388746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.159388746
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2437858106
Short name T342
Test name
Test status
Simulation time 152160556 ps
CPU time 0.83 seconds
Started Jul 10 07:21:17 PM PDT 24
Finished Jul 10 07:21:20 PM PDT 24
Peak memory 199984 kb
Host smart-1cb42fea-2e6f-4967-a6a8-34b0d81cbcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437858106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2437858106
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.356931546
Short name T148
Test name
Test status
Simulation time 1313123115 ps
CPU time 5.14 seconds
Started Jul 10 07:21:17 PM PDT 24
Finished Jul 10 07:21:24 PM PDT 24
Peak memory 200412 kb
Host smart-c4f7cdf3-1e52-47e7-bd4c-07c58f9acd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356931546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.356931546
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.888628205
Short name T340
Test name
Test status
Simulation time 151368497 ps
CPU time 1.23 seconds
Started Jul 10 07:21:26 PM PDT 24
Finished Jul 10 07:21:31 PM PDT 24
Peak memory 200164 kb
Host smart-4d9cbbad-dca7-4827-bb0c-4ace36061163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888628205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.888628205
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2107071053
Short name T452
Test name
Test status
Simulation time 225534627 ps
CPU time 1.51 seconds
Started Jul 10 07:21:16 PM PDT 24
Finished Jul 10 07:21:18 PM PDT 24
Peak memory 200348 kb
Host smart-be328c41-90fa-4596-93e4-c851793805bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107071053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2107071053
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2208140849
Short name T256
Test name
Test status
Simulation time 141083192 ps
CPU time 1.05 seconds
Started Jul 10 07:21:20 PM PDT 24
Finished Jul 10 07:21:23 PM PDT 24
Peak memory 200124 kb
Host smart-151c6c98-c82b-44b0-854b-461b63c24227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208140849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2208140849
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.351791835
Short name T239
Test name
Test status
Simulation time 272236232 ps
CPU time 1.84 seconds
Started Jul 10 07:21:26 PM PDT 24
Finished Jul 10 07:21:31 PM PDT 24
Peak memory 200140 kb
Host smart-ae3cf3bc-4623-45e3-a125-8846827843e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351791835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.351791835
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.4138118648
Short name T302
Test name
Test status
Simulation time 187082200 ps
CPU time 1.26 seconds
Started Jul 10 07:21:22 PM PDT 24
Finished Jul 10 07:21:25 PM PDT 24
Peak memory 200176 kb
Host smart-b40c4dfa-c346-491c-a0d0-9f7298ee6c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138118648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.4138118648
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2306553783
Short name T227
Test name
Test status
Simulation time 85410835 ps
CPU time 0.87 seconds
Started Jul 10 07:21:16 PM PDT 24
Finished Jul 10 07:21:19 PM PDT 24
Peak memory 199952 kb
Host smart-55b2ea09-1f8f-4a81-8d22-20ca4bb032d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306553783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2306553783
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2489249645
Short name T41
Test name
Test status
Simulation time 1900999063 ps
CPU time 8.09 seconds
Started Jul 10 07:21:20 PM PDT 24
Finished Jul 10 07:21:30 PM PDT 24
Peak memory 217480 kb
Host smart-cecd8f34-df76-4b8c-82f2-b854560353a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489249645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2489249645
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.204858083
Short name T157
Test name
Test status
Simulation time 244610012 ps
CPU time 1.14 seconds
Started Jul 10 07:21:19 PM PDT 24
Finished Jul 10 07:21:23 PM PDT 24
Peak memory 217592 kb
Host smart-a99deef1-ca82-44c7-8a05-9449079b3b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204858083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.204858083
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2225169452
Short name T18
Test name
Test status
Simulation time 120912629 ps
CPU time 0.81 seconds
Started Jul 10 07:21:20 PM PDT 24
Finished Jul 10 07:21:23 PM PDT 24
Peak memory 199984 kb
Host smart-326b45df-4dce-4763-936c-faffbd5a6d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225169452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2225169452
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3528714447
Short name T212
Test name
Test status
Simulation time 816535368 ps
CPU time 4.05 seconds
Started Jul 10 07:21:16 PM PDT 24
Finished Jul 10 07:21:22 PM PDT 24
Peak memory 200456 kb
Host smart-4034c2cf-0e8c-4fca-9f59-79337c97c712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528714447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3528714447
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3924201024
Short name T380
Test name
Test status
Simulation time 169996348 ps
CPU time 1.16 seconds
Started Jul 10 07:21:25 PM PDT 24
Finished Jul 10 07:21:30 PM PDT 24
Peak memory 200124 kb
Host smart-c8081459-91f4-4c8d-a5f3-7773d5f062d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924201024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3924201024
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2362651571
Short name T198
Test name
Test status
Simulation time 189610112 ps
CPU time 1.43 seconds
Started Jul 10 07:21:18 PM PDT 24
Finished Jul 10 07:21:21 PM PDT 24
Peak memory 200348 kb
Host smart-9463cd62-8091-43f2-8e69-938f3e2c0d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362651571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2362651571
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1255467604
Short name T339
Test name
Test status
Simulation time 316362726 ps
CPU time 1.72 seconds
Started Jul 10 07:21:20 PM PDT 24
Finished Jul 10 07:21:24 PM PDT 24
Peak memory 200464 kb
Host smart-11c0561d-d4ce-4461-b0e1-aaf3e419041c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255467604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1255467604
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1265060125
Short name T138
Test name
Test status
Simulation time 369027309 ps
CPU time 2.37 seconds
Started Jul 10 07:21:20 PM PDT 24
Finished Jul 10 07:21:25 PM PDT 24
Peak memory 200224 kb
Host smart-a33d738e-954f-4bd8-a98e-8355797d3a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265060125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1265060125
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1630934524
Short name T335
Test name
Test status
Simulation time 128193890 ps
CPU time 1.12 seconds
Started Jul 10 07:21:17 PM PDT 24
Finished Jul 10 07:21:19 PM PDT 24
Peak memory 200140 kb
Host smart-f5348f52-9897-4803-824d-f81e6ada87bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630934524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1630934524
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.678672108
Short name T323
Test name
Test status
Simulation time 70695421 ps
CPU time 0.79 seconds
Started Jul 10 07:21:21 PM PDT 24
Finished Jul 10 07:21:24 PM PDT 24
Peak memory 199960 kb
Host smart-7c114725-f63d-43a1-9332-54e8d9cf99f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678672108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.678672108
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.4263833958
Short name T242
Test name
Test status
Simulation time 1900050156 ps
CPU time 7.81 seconds
Started Jul 10 07:21:20 PM PDT 24
Finished Jul 10 07:21:30 PM PDT 24
Peak memory 221696 kb
Host smart-fbc81d93-3e88-4e30-9913-60b1a3c3ff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263833958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.4263833958
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1696236719
Short name T492
Test name
Test status
Simulation time 244491088 ps
CPU time 1.09 seconds
Started Jul 10 07:21:18 PM PDT 24
Finished Jul 10 07:21:21 PM PDT 24
Peak memory 217520 kb
Host smart-8df8deeb-3a52-4fb8-a501-92b0fa0e0135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696236719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1696236719
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3455931771
Short name T297
Test name
Test status
Simulation time 120485113 ps
CPU time 0.84 seconds
Started Jul 10 07:21:18 PM PDT 24
Finished Jul 10 07:21:21 PM PDT 24
Peak memory 200040 kb
Host smart-8a36534d-c7b2-4301-bef0-1c948d5bbc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455931771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3455931771
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.316596128
Short name T171
Test name
Test status
Simulation time 1591242061 ps
CPU time 6.14 seconds
Started Jul 10 07:21:17 PM PDT 24
Finished Jul 10 07:21:25 PM PDT 24
Peak memory 200480 kb
Host smart-832596ec-964e-4b7d-808b-07f769fc5863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316596128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.316596128
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3365885381
Short name T48
Test name
Test status
Simulation time 99193916 ps
CPU time 0.98 seconds
Started Jul 10 07:21:17 PM PDT 24
Finished Jul 10 07:21:20 PM PDT 24
Peak memory 200168 kb
Host smart-0661f42c-7d31-4c16-bbbc-5393c7a2c807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365885381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3365885381
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.4143830954
Short name T341
Test name
Test status
Simulation time 123569676 ps
CPU time 1.21 seconds
Started Jul 10 07:21:25 PM PDT 24
Finished Jul 10 07:21:30 PM PDT 24
Peak memory 200368 kb
Host smart-51d99244-869b-43b8-a15b-8ca226df6f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143830954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.4143830954
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.756018330
Short name T120
Test name
Test status
Simulation time 10730791604 ps
CPU time 35.52 seconds
Started Jul 10 07:21:19 PM PDT 24
Finished Jul 10 07:21:57 PM PDT 24
Peak memory 200476 kb
Host smart-af62b072-8ae7-40ed-81b7-21dfc420a53f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756018330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.756018330
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2730865303
Short name T278
Test name
Test status
Simulation time 314249323 ps
CPU time 2.05 seconds
Started Jul 10 07:21:17 PM PDT 24
Finished Jul 10 07:21:21 PM PDT 24
Peak memory 200144 kb
Host smart-5ba86907-a5b7-40e2-848e-f6b6abe08a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730865303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2730865303
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1116403102
Short name T320
Test name
Test status
Simulation time 172996503 ps
CPU time 1.27 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:28 PM PDT 24
Peak memory 200132 kb
Host smart-c8769b31-1f7c-476d-85ad-d130ca775a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116403102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1116403102
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.4279523061
Short name T522
Test name
Test status
Simulation time 67151911 ps
CPU time 0.77 seconds
Started Jul 10 07:21:37 PM PDT 24
Finished Jul 10 07:21:40 PM PDT 24
Peak memory 200164 kb
Host smart-7bf767d6-1b1c-42e0-9639-ae30ab199f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279523061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.4279523061
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3313080423
Short name T293
Test name
Test status
Simulation time 1227047460 ps
CPU time 5.87 seconds
Started Jul 10 07:21:25 PM PDT 24
Finished Jul 10 07:21:34 PM PDT 24
Peak memory 221756 kb
Host smart-ce2a6ef1-68f4-46d8-8650-135c17033e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313080423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3313080423
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3052764852
Short name T172
Test name
Test status
Simulation time 246039951 ps
CPU time 1.04 seconds
Started Jul 10 07:21:31 PM PDT 24
Finished Jul 10 07:21:34 PM PDT 24
Peak memory 217544 kb
Host smart-fbde3d16-9200-4285-bb7e-3e1473434514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052764852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3052764852
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2085005823
Short name T419
Test name
Test status
Simulation time 209778698 ps
CPU time 0.94 seconds
Started Jul 10 07:21:16 PM PDT 24
Finished Jul 10 07:21:18 PM PDT 24
Peak memory 199984 kb
Host smart-106c0b2b-7137-4a0f-a6f1-a8fa6ae0a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085005823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2085005823
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1931425024
Short name T123
Test name
Test status
Simulation time 1932595093 ps
CPU time 8.03 seconds
Started Jul 10 07:21:21 PM PDT 24
Finished Jul 10 07:21:31 PM PDT 24
Peak memory 200408 kb
Host smart-649d06ae-7a64-4063-8ce5-bccfe67ca55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931425024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1931425024
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2898194877
Short name T140
Test name
Test status
Simulation time 105567421 ps
CPU time 1.01 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:27 PM PDT 24
Peak memory 200156 kb
Host smart-bf73c0a2-ad34-46ec-ac2d-3c3227609527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898194877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2898194877
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3414592867
Short name T385
Test name
Test status
Simulation time 128451423 ps
CPU time 1.2 seconds
Started Jul 10 07:21:17 PM PDT 24
Finished Jul 10 07:21:20 PM PDT 24
Peak memory 200388 kb
Host smart-237f2200-55d0-442c-8610-81e0844226fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414592867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3414592867
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3024064963
Short name T460
Test name
Test status
Simulation time 3851060907 ps
CPU time 18.37 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:45 PM PDT 24
Peak memory 200464 kb
Host smart-b9574be7-5a2e-4f8a-a3c8-4d668fd144b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024064963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3024064963
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2232707016
Short name T370
Test name
Test status
Simulation time 148314860 ps
CPU time 1.99 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:27 PM PDT 24
Peak memory 200136 kb
Host smart-793a9773-c008-4afa-a73b-f340d8f24bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232707016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2232707016
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3856617868
Short name T420
Test name
Test status
Simulation time 155661924 ps
CPU time 1.29 seconds
Started Jul 10 07:21:28 PM PDT 24
Finished Jul 10 07:21:32 PM PDT 24
Peak memory 200360 kb
Host smart-904f48b0-bdd4-47fd-af7f-ac1b2630c42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856617868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3856617868
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.4277561870
Short name T325
Test name
Test status
Simulation time 59871703 ps
CPU time 0.74 seconds
Started Jul 10 07:21:25 PM PDT 24
Finished Jul 10 07:21:29 PM PDT 24
Peak memory 199964 kb
Host smart-dd9e682d-4292-424a-9fea-1e0d84d35607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277561870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4277561870
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1375123884
Short name T28
Test name
Test status
Simulation time 2164972883 ps
CPU time 8.86 seconds
Started Jul 10 07:21:24 PM PDT 24
Finished Jul 10 07:21:36 PM PDT 24
Peak memory 217752 kb
Host smart-1cc6799b-b30f-43ed-ad74-d15afb2c70c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375123884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1375123884
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.750371061
Short name T231
Test name
Test status
Simulation time 248832781 ps
CPU time 1.1 seconds
Started Jul 10 07:21:33 PM PDT 24
Finished Jul 10 07:21:36 PM PDT 24
Peak memory 217524 kb
Host smart-d242fc43-cb63-48ee-909d-6585f965c0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750371061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.750371061
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2421441660
Short name T538
Test name
Test status
Simulation time 206066268 ps
CPU time 0.88 seconds
Started Jul 10 07:21:26 PM PDT 24
Finished Jul 10 07:21:30 PM PDT 24
Peak memory 199924 kb
Host smart-0f6fddb4-00bd-4fc6-919d-b0c3dd1b14cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421441660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2421441660
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3225482264
Short name T459
Test name
Test status
Simulation time 880534982 ps
CPU time 4.5 seconds
Started Jul 10 07:21:33 PM PDT 24
Finished Jul 10 07:21:39 PM PDT 24
Peak memory 200472 kb
Host smart-519dd778-5115-436e-a749-69163846a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225482264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3225482264
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3181472180
Short name T183
Test name
Test status
Simulation time 104783965 ps
CPU time 0.99 seconds
Started Jul 10 07:21:24 PM PDT 24
Finished Jul 10 07:21:28 PM PDT 24
Peak memory 200180 kb
Host smart-7c88af72-110c-4100-a763-ea5f1ee28033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181472180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3181472180
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3455410055
Short name T12
Test name
Test status
Simulation time 243322048 ps
CPU time 1.64 seconds
Started Jul 10 07:21:38 PM PDT 24
Finished Jul 10 07:21:43 PM PDT 24
Peak memory 200480 kb
Host smart-a9d0978e-035b-4d15-b2ab-6ed58ceb63ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455410055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3455410055
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3176503641
Short name T199
Test name
Test status
Simulation time 1407998403 ps
CPU time 5.82 seconds
Started Jul 10 07:21:26 PM PDT 24
Finished Jul 10 07:21:35 PM PDT 24
Peak memory 200468 kb
Host smart-c77d5802-7db3-4d60-8ebd-f12251c57660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176503641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3176503641
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3023881609
Short name T87
Test name
Test status
Simulation time 147819147 ps
CPU time 1.81 seconds
Started Jul 10 07:21:26 PM PDT 24
Finished Jul 10 07:21:31 PM PDT 24
Peak memory 200164 kb
Host smart-c32b80e6-928f-4834-9dd4-835b40ec736e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023881609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3023881609
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1926403201
Short name T127
Test name
Test status
Simulation time 91617551 ps
CPU time 0.86 seconds
Started Jul 10 07:21:27 PM PDT 24
Finished Jul 10 07:21:31 PM PDT 24
Peak memory 200144 kb
Host smart-5d94779b-bb23-48bf-9a0a-42993c471d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926403201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1926403201
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3669094196
Short name T249
Test name
Test status
Simulation time 81205987 ps
CPU time 0.81 seconds
Started Jul 10 07:21:24 PM PDT 24
Finished Jul 10 07:21:28 PM PDT 24
Peak memory 199964 kb
Host smart-9befa48f-3ed9-45ef-b152-255f5f4c12ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669094196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3669094196
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.4159913209
Short name T192
Test name
Test status
Simulation time 2347057265 ps
CPU time 8.16 seconds
Started Jul 10 07:21:26 PM PDT 24
Finished Jul 10 07:21:37 PM PDT 24
Peak memory 217964 kb
Host smart-3b4e1bef-d36f-40e5-8671-f834bc6f3973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159913209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.4159913209
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1313231939
Short name T151
Test name
Test status
Simulation time 244695070 ps
CPU time 1.14 seconds
Started Jul 10 07:21:27 PM PDT 24
Finished Jul 10 07:21:31 PM PDT 24
Peak memory 217540 kb
Host smart-0c08a74b-0a03-4d65-a078-823b93fad282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313231939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1313231939
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.61898288
Short name T4
Test name
Test status
Simulation time 189706706 ps
CPU time 0.93 seconds
Started Jul 10 07:21:25 PM PDT 24
Finished Jul 10 07:21:29 PM PDT 24
Peak memory 200048 kb
Host smart-c70960ec-867c-4a29-a8c1-56bcc9d54a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61898288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.61898288
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.625431733
Short name T317
Test name
Test status
Simulation time 877782871 ps
CPU time 4.62 seconds
Started Jul 10 07:21:22 PM PDT 24
Finished Jul 10 07:21:29 PM PDT 24
Peak memory 200408 kb
Host smart-40e1cccb-3fe4-4d1e-9e79-ff5427d5fae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625431733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.625431733
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3757576402
Short name T270
Test name
Test status
Simulation time 159997942 ps
CPU time 1.13 seconds
Started Jul 10 07:21:37 PM PDT 24
Finished Jul 10 07:21:41 PM PDT 24
Peak memory 200332 kb
Host smart-1242df53-a29a-42a7-804d-283f6c6513ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757576402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3757576402
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3087336575
Short name T523
Test name
Test status
Simulation time 114034872 ps
CPU time 1.22 seconds
Started Jul 10 07:21:28 PM PDT 24
Finished Jul 10 07:21:32 PM PDT 24
Peak memory 200552 kb
Host smart-5d4a40b1-80b8-4396-a4e2-013d8b87be7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087336575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3087336575
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3536195367
Short name T238
Test name
Test status
Simulation time 4477532561 ps
CPU time 16.5 seconds
Started Jul 10 07:21:34 PM PDT 24
Finished Jul 10 07:21:52 PM PDT 24
Peak memory 208688 kb
Host smart-90ad96ff-0065-4b00-8775-749a98a1bfd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536195367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3536195367
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1109151132
Short name T450
Test name
Test status
Simulation time 469696666 ps
CPU time 2.74 seconds
Started Jul 10 07:21:27 PM PDT 24
Finished Jul 10 07:21:32 PM PDT 24
Peak memory 200152 kb
Host smart-02707584-77f5-4b49-9a5e-e711f7adc641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109151132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1109151132
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.4093470944
Short name T84
Test name
Test status
Simulation time 116609537 ps
CPU time 1.07 seconds
Started Jul 10 07:21:25 PM PDT 24
Finished Jul 10 07:21:29 PM PDT 24
Peak memory 200156 kb
Host smart-4694f7ae-2b83-454c-a00b-3e0f6f9c5143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093470944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.4093470944
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2297191245
Short name T368
Test name
Test status
Simulation time 61041222 ps
CPU time 0.75 seconds
Started Jul 10 07:21:24 PM PDT 24
Finished Jul 10 07:21:28 PM PDT 24
Peak memory 199940 kb
Host smart-3deca136-9e75-4c96-ab17-c32f503b4629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297191245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2297191245
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3896069938
Short name T428
Test name
Test status
Simulation time 1896248121 ps
CPU time 7.53 seconds
Started Jul 10 07:21:33 PM PDT 24
Finished Jul 10 07:21:42 PM PDT 24
Peak memory 217796 kb
Host smart-53603e2a-0627-4829-b83e-07c0dfeccd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896069938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3896069938
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2738692726
Short name T79
Test name
Test status
Simulation time 244316849 ps
CPU time 1.09 seconds
Started Jul 10 07:21:25 PM PDT 24
Finished Jul 10 07:21:29 PM PDT 24
Peak memory 217500 kb
Host smart-31236d81-630e-4bf7-892b-986baa8a14f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738692726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2738692726
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3868769316
Short name T229
Test name
Test status
Simulation time 255236806 ps
CPU time 1.02 seconds
Started Jul 10 07:21:34 PM PDT 24
Finished Jul 10 07:21:36 PM PDT 24
Peak memory 199988 kb
Host smart-d644be15-0a87-422a-bf83-a4dcb8008fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868769316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3868769316
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1229116907
Short name T497
Test name
Test status
Simulation time 1384666265 ps
CPU time 5.67 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:32 PM PDT 24
Peak memory 200476 kb
Host smart-24e72034-a82b-476c-ad0a-9d67457fe2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229116907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1229116907
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1387077237
Short name T426
Test name
Test status
Simulation time 102325518 ps
CPU time 1 seconds
Started Jul 10 07:21:29 PM PDT 24
Finished Jul 10 07:21:32 PM PDT 24
Peak memory 200356 kb
Host smart-3f70f8bf-5b81-4247-bb49-6286772c449d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387077237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1387077237
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3407495569
Short name T508
Test name
Test status
Simulation time 253536896 ps
CPU time 1.5 seconds
Started Jul 10 07:21:37 PM PDT 24
Finished Jul 10 07:21:41 PM PDT 24
Peak memory 200564 kb
Host smart-22307079-43d6-48b0-8f98-d677a6328226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407495569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3407495569
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3256380817
Short name T407
Test name
Test status
Simulation time 8883192617 ps
CPU time 42.09 seconds
Started Jul 10 07:21:28 PM PDT 24
Finished Jul 10 07:22:13 PM PDT 24
Peak memory 200492 kb
Host smart-6362d797-64d3-4eef-a2cc-5dfb2a6a30a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256380817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3256380817
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3255510842
Short name T421
Test name
Test status
Simulation time 121901157 ps
CPU time 1.46 seconds
Started Jul 10 07:21:22 PM PDT 24
Finished Jul 10 07:21:26 PM PDT 24
Peak memory 200192 kb
Host smart-76aac348-72a4-4985-a621-886698994b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255510842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3255510842
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2057224455
Short name T395
Test name
Test status
Simulation time 166246698 ps
CPU time 1.24 seconds
Started Jul 10 07:21:26 PM PDT 24
Finished Jul 10 07:21:31 PM PDT 24
Peak memory 200144 kb
Host smart-f0770704-ff3d-46ee-9048-fb784c31f0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057224455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2057224455
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1345988355
Short name T308
Test name
Test status
Simulation time 56771969 ps
CPU time 0.73 seconds
Started Jul 10 07:21:38 PM PDT 24
Finished Jul 10 07:21:42 PM PDT 24
Peak memory 199988 kb
Host smart-91e560ef-d63b-47af-893a-ec0ad5c26628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345988355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1345988355
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3439845657
Short name T26
Test name
Test status
Simulation time 2165539427 ps
CPU time 7.98 seconds
Started Jul 10 07:21:33 PM PDT 24
Finished Jul 10 07:21:42 PM PDT 24
Peak memory 217876 kb
Host smart-8253660e-710e-4f35-97ef-805f431b3939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439845657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3439845657
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.547490539
Short name T466
Test name
Test status
Simulation time 244775261 ps
CPU time 1.15 seconds
Started Jul 10 07:21:37 PM PDT 24
Finished Jul 10 07:21:42 PM PDT 24
Peak memory 217720 kb
Host smart-f277f0e2-cbf8-48ea-87a9-f57a8dd274b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547490539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.547490539
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2257839482
Short name T209
Test name
Test status
Simulation time 76403931 ps
CPU time 0.73 seconds
Started Jul 10 07:21:33 PM PDT 24
Finished Jul 10 07:21:36 PM PDT 24
Peak memory 199964 kb
Host smart-b60371c2-bf1f-41d0-b68e-c42d1d17a064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257839482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2257839482
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1870888287
Short name T95
Test name
Test status
Simulation time 752250454 ps
CPU time 4.16 seconds
Started Jul 10 07:21:29 PM PDT 24
Finished Jul 10 07:21:35 PM PDT 24
Peak memory 200616 kb
Host smart-b3167b3c-ed83-4e23-8d50-da74b1b3600e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870888287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1870888287
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.999023723
Short name T334
Test name
Test status
Simulation time 158487402 ps
CPU time 1.18 seconds
Started Jul 10 07:21:24 PM PDT 24
Finished Jul 10 07:21:28 PM PDT 24
Peak memory 200176 kb
Host smart-da4513e0-8f62-4afe-9a07-1aabe33e24f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999023723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.999023723
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3503124120
Short name T86
Test name
Test status
Simulation time 195663198 ps
CPU time 1.32 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:28 PM PDT 24
Peak memory 200360 kb
Host smart-a432a657-df1e-48bd-acfe-9b29d4c1b86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503124120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3503124120
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2896997513
Short name T211
Test name
Test status
Simulation time 5351413786 ps
CPU time 18.48 seconds
Started Jul 10 07:21:24 PM PDT 24
Finished Jul 10 07:21:46 PM PDT 24
Peak memory 200468 kb
Host smart-b7a029c2-5f6e-4814-bbd0-581dca95b1c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896997513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2896997513
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2662355551
Short name T45
Test name
Test status
Simulation time 351206323 ps
CPU time 2.32 seconds
Started Jul 10 07:21:25 PM PDT 24
Finished Jul 10 07:21:30 PM PDT 24
Peak memory 200164 kb
Host smart-98f5a9c5-4df1-45d6-9010-01db32c2ceaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662355551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2662355551
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.835684697
Short name T283
Test name
Test status
Simulation time 138533922 ps
CPU time 1.11 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:27 PM PDT 24
Peak memory 200148 kb
Host smart-fbb49f5a-9472-4502-9f90-061f3fd51736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835684697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.835684697
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.18280871
Short name T34
Test name
Test status
Simulation time 68360159 ps
CPU time 0.79 seconds
Started Jul 10 07:21:26 PM PDT 24
Finished Jul 10 07:21:30 PM PDT 24
Peak memory 199896 kb
Host smart-8be34ade-ec4c-48cd-8339-cdfef4ba52c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18280871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.18280871
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1558740446
Short name T30
Test name
Test status
Simulation time 1217992887 ps
CPU time 5.77 seconds
Started Jul 10 07:21:37 PM PDT 24
Finished Jul 10 07:21:45 PM PDT 24
Peak memory 217968 kb
Host smart-bcbb8968-e415-4ca2-a1ad-5a6d3f48739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558740446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1558740446
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.105606034
Short name T177
Test name
Test status
Simulation time 244568652 ps
CPU time 1.05 seconds
Started Jul 10 07:21:36 PM PDT 24
Finished Jul 10 07:21:39 PM PDT 24
Peak memory 217720 kb
Host smart-2185e608-53e9-48ef-9957-401a946acea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105606034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.105606034
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3321849491
Short name T372
Test name
Test status
Simulation time 149148845 ps
CPU time 0.88 seconds
Started Jul 10 07:21:22 PM PDT 24
Finished Jul 10 07:21:25 PM PDT 24
Peak memory 199984 kb
Host smart-9c2daa85-18bc-46c9-8b7c-ccc0de2f9328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321849491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3321849491
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3579153894
Short name T431
Test name
Test status
Simulation time 1753415695 ps
CPU time 6.45 seconds
Started Jul 10 07:21:25 PM PDT 24
Finished Jul 10 07:21:34 PM PDT 24
Peak memory 200424 kb
Host smart-213fe076-7785-4308-8968-14fa1ace1a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579153894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3579153894
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1943982662
Short name T477
Test name
Test status
Simulation time 180198559 ps
CPU time 1.21 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:26 PM PDT 24
Peak memory 200156 kb
Host smart-0338ee13-a871-4514-849b-970d4431654b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943982662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1943982662
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3363614629
Short name T146
Test name
Test status
Simulation time 124357918 ps
CPU time 1.24 seconds
Started Jul 10 07:21:28 PM PDT 24
Finished Jul 10 07:21:32 PM PDT 24
Peak memory 200356 kb
Host smart-58910136-39e1-4733-a73a-5f47e4b2329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363614629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3363614629
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3401245484
Short name T289
Test name
Test status
Simulation time 5641905129 ps
CPU time 24.35 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:50 PM PDT 24
Peak memory 208672 kb
Host smart-41168770-f831-479b-b773-9b29d4c06bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401245484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3401245484
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3452481157
Short name T432
Test name
Test status
Simulation time 128322933 ps
CPU time 1.6 seconds
Started Jul 10 07:21:23 PM PDT 24
Finished Jul 10 07:21:27 PM PDT 24
Peak memory 208392 kb
Host smart-f107bea9-f576-47f2-8fdd-b0b6a6c3802c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452481157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3452481157
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1045277499
Short name T510
Test name
Test status
Simulation time 281906228 ps
CPU time 1.48 seconds
Started Jul 10 07:21:28 PM PDT 24
Finished Jul 10 07:21:32 PM PDT 24
Peak memory 200136 kb
Host smart-5688bcf9-6183-4f4a-afc1-c25a18d4fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045277499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1045277499
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2669500564
Short name T382
Test name
Test status
Simulation time 79582278 ps
CPU time 0.82 seconds
Started Jul 10 07:21:44 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 199932 kb
Host smart-22382db8-71d2-4c2c-ad3b-ec87f801b312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669500564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2669500564
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2038159079
Short name T44
Test name
Test status
Simulation time 1891385513 ps
CPU time 7.62 seconds
Started Jul 10 07:21:41 PM PDT 24
Finished Jul 10 07:21:52 PM PDT 24
Peak memory 216872 kb
Host smart-f528c140-4f1e-4330-852c-872c7de2feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038159079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2038159079
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.4125693345
Short name T451
Test name
Test status
Simulation time 244817823 ps
CPU time 1.06 seconds
Started Jul 10 07:21:39 PM PDT 24
Finished Jul 10 07:21:44 PM PDT 24
Peak memory 217612 kb
Host smart-ce5cd4db-9189-4b89-8f10-d362b05d90b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125693345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.4125693345
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2183192537
Short name T505
Test name
Test status
Simulation time 189397451 ps
CPU time 0.93 seconds
Started Jul 10 07:21:39 PM PDT 24
Finished Jul 10 07:21:43 PM PDT 24
Peak memory 199988 kb
Host smart-70d06626-c72f-48c0-b09a-a46923023f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183192537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2183192537
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3831616922
Short name T77
Test name
Test status
Simulation time 965253666 ps
CPU time 4.58 seconds
Started Jul 10 07:21:39 PM PDT 24
Finished Jul 10 07:21:48 PM PDT 24
Peak memory 200420 kb
Host smart-b9acf196-e255-49e7-8a28-9c7dd83e562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831616922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3831616922
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.36096395
Short name T202
Test name
Test status
Simulation time 170158714 ps
CPU time 1.2 seconds
Started Jul 10 07:21:39 PM PDT 24
Finished Jul 10 07:21:44 PM PDT 24
Peak memory 200164 kb
Host smart-05abf599-8933-4e9f-8e99-21821351a86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36096395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.36096395
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1234358449
Short name T391
Test name
Test status
Simulation time 111863934 ps
CPU time 1.27 seconds
Started Jul 10 07:21:38 PM PDT 24
Finished Jul 10 07:21:42 PM PDT 24
Peak memory 200360 kb
Host smart-30841eb7-4e85-42ed-b92f-e7c5c20dc61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234358449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1234358449
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2851756736
Short name T482
Test name
Test status
Simulation time 5310956607 ps
CPU time 19.12 seconds
Started Jul 10 07:21:43 PM PDT 24
Finished Jul 10 07:22:06 PM PDT 24
Peak memory 210484 kb
Host smart-2badbe9d-77f3-4ea7-b42e-aa66160690c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851756736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2851756736
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1527171850
Short name T215
Test name
Test status
Simulation time 111606849 ps
CPU time 1.51 seconds
Started Jul 10 07:21:44 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 200152 kb
Host smart-50267d0d-cace-4ed2-8560-0a779b77d725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527171850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1527171850
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1696819157
Short name T23
Test name
Test status
Simulation time 127483546 ps
CPU time 1.05 seconds
Started Jul 10 07:21:43 PM PDT 24
Finished Jul 10 07:21:48 PM PDT 24
Peak memory 200164 kb
Host smart-5cbf11ca-fe13-4213-8621-d846dfb09ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696819157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1696819157
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.969080309
Short name T144
Test name
Test status
Simulation time 81873149 ps
CPU time 0.83 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:20:00 PM PDT 24
Peak memory 199932 kb
Host smart-e1437184-dbcb-47b7-b55d-f1a2137ad9b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969080309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.969080309
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2372545969
Short name T507
Test name
Test status
Simulation time 1889093626 ps
CPU time 7.61 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:20:06 PM PDT 24
Peak memory 217780 kb
Host smart-8b4b2a3b-84fa-443c-9588-172c3c0d3741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372545969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2372545969
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2101077642
Short name T200
Test name
Test status
Simulation time 244361614 ps
CPU time 1.17 seconds
Started Jul 10 07:20:02 PM PDT 24
Finished Jul 10 07:20:06 PM PDT 24
Peak memory 217532 kb
Host smart-24852001-201b-4040-a59b-c9c18e47cd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101077642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2101077642
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1799788185
Short name T17
Test name
Test status
Simulation time 192654068 ps
CPU time 0.99 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:01 PM PDT 24
Peak memory 199948 kb
Host smart-d88c0170-b674-4f38-9b9d-3e53cdabe132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799788185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1799788185
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.4209197268
Short name T403
Test name
Test status
Simulation time 1438329926 ps
CPU time 5.88 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:20:04 PM PDT 24
Peak memory 200408 kb
Host smart-0ec4ec12-f2ce-448c-b490-8b1825fc57a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209197268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.4209197268
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1292343025
Short name T373
Test name
Test status
Simulation time 185327042 ps
CPU time 1.22 seconds
Started Jul 10 07:19:59 PM PDT 24
Finished Jul 10 07:20:03 PM PDT 24
Peak memory 200112 kb
Host smart-b36b2806-46a6-498a-9e08-cce94dc3ba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292343025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1292343025
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3594057882
Short name T319
Test name
Test status
Simulation time 234998747 ps
CPU time 1.49 seconds
Started Jul 10 07:19:59 PM PDT 24
Finished Jul 10 07:20:02 PM PDT 24
Peak memory 200416 kb
Host smart-3a623a27-28d3-4f70-a5db-0529e9b6a9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594057882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3594057882
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1723946447
Short name T480
Test name
Test status
Simulation time 5604412086 ps
CPU time 19.37 seconds
Started Jul 10 07:20:02 PM PDT 24
Finished Jul 10 07:20:23 PM PDT 24
Peak memory 216136 kb
Host smart-9ce2adfd-70df-4e38-8db5-457f8dc6cb9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723946447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1723946447
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.411350815
Short name T284
Test name
Test status
Simulation time 276665421 ps
CPU time 1.9 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:20:01 PM PDT 24
Peak memory 200180 kb
Host smart-8026d119-fe95-4a52-9898-6d0a9493f4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411350815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.411350815
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.4091509061
Short name T469
Test name
Test status
Simulation time 143828419 ps
CPU time 1.06 seconds
Started Jul 10 07:20:00 PM PDT 24
Finished Jul 10 07:20:04 PM PDT 24
Peak memory 200168 kb
Host smart-39fc5f53-517c-47fc-8f79-63ada1ca2cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091509061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.4091509061
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3136863751
Short name T401
Test name
Test status
Simulation time 69939109 ps
CPU time 0.74 seconds
Started Jul 10 07:20:06 PM PDT 24
Finished Jul 10 07:20:07 PM PDT 24
Peak memory 199964 kb
Host smart-f15b5c2b-52bc-43be-8cc2-5b3c6c2240af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136863751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3136863751
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3578765874
Short name T24
Test name
Test status
Simulation time 2349974404 ps
CPU time 8.22 seconds
Started Jul 10 07:19:59 PM PDT 24
Finished Jul 10 07:20:09 PM PDT 24
Peak memory 217936 kb
Host smart-ffbeb654-ca01-4cd3-b260-773fe1ed9f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578765874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3578765874
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.664980835
Short name T534
Test name
Test status
Simulation time 243412171 ps
CPU time 1.13 seconds
Started Jul 10 07:20:01 PM PDT 24
Finished Jul 10 07:20:05 PM PDT 24
Peak memory 217516 kb
Host smart-45287ee0-19c6-4072-883b-620fbfef03df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664980835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.664980835
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2321266693
Short name T489
Test name
Test status
Simulation time 73368167 ps
CPU time 0.74 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:01 PM PDT 24
Peak memory 200040 kb
Host smart-f2baf432-02f9-4f9d-8710-d6b546535b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321266693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2321266693
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3319282480
Short name T311
Test name
Test status
Simulation time 733748301 ps
CPU time 4.24 seconds
Started Jul 10 07:20:02 PM PDT 24
Finished Jul 10 07:20:08 PM PDT 24
Peak memory 200412 kb
Host smart-242cea06-584c-4a0b-af1d-918e1b7235fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319282480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3319282480
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1581440996
Short name T491
Test name
Test status
Simulation time 114859897 ps
CPU time 1.04 seconds
Started Jul 10 07:20:02 PM PDT 24
Finished Jul 10 07:20:05 PM PDT 24
Peak memory 200172 kb
Host smart-3b83e6ba-037c-4f15-a343-375657d71efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581440996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1581440996
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3233309747
Short name T137
Test name
Test status
Simulation time 118739425 ps
CPU time 1.25 seconds
Started Jul 10 07:20:08 PM PDT 24
Finished Jul 10 07:20:10 PM PDT 24
Peak memory 200348 kb
Host smart-b0bf9b89-d4d4-4bff-9b01-639481232ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233309747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3233309747
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1388213955
Short name T315
Test name
Test status
Simulation time 2874105430 ps
CPU time 13.07 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:20:11 PM PDT 24
Peak memory 208716 kb
Host smart-a28d1e31-2fc5-4565-922b-8a1c65c3c3dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388213955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1388213955
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2253139673
Short name T230
Test name
Test status
Simulation time 524197597 ps
CPU time 2.87 seconds
Started Jul 10 07:20:00 PM PDT 24
Finished Jul 10 07:20:05 PM PDT 24
Peak memory 200152 kb
Host smart-e1c40e2c-d7f1-4e95-9364-65807a54be5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253139673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2253139673
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4233660376
Short name T445
Test name
Test status
Simulation time 130873103 ps
CPU time 1.07 seconds
Started Jul 10 07:20:01 PM PDT 24
Finished Jul 10 07:20:05 PM PDT 24
Peak memory 200156 kb
Host smart-b0a73945-2972-4716-a4f8-6d8f7d6b7324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233660376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4233660376
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.518397458
Short name T313
Test name
Test status
Simulation time 84574376 ps
CPU time 0.84 seconds
Started Jul 10 07:20:08 PM PDT 24
Finished Jul 10 07:20:10 PM PDT 24
Peak memory 199948 kb
Host smart-8e991b20-bca3-4850-85b0-5a576e856a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518397458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.518397458
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.245631872
Short name T9
Test name
Test status
Simulation time 1894914395 ps
CPU time 7.71 seconds
Started Jul 10 07:19:59 PM PDT 24
Finished Jul 10 07:20:09 PM PDT 24
Peak memory 229968 kb
Host smart-bde6a8e8-5025-4e37-a336-cc803f693677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245631872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.245631872
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.719243511
Short name T260
Test name
Test status
Simulation time 244830000 ps
CPU time 1.03 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:20:00 PM PDT 24
Peak memory 217516 kb
Host smart-c3315c1a-147b-4fba-a2ea-c08142fc11be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719243511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.719243511
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2672013042
Short name T411
Test name
Test status
Simulation time 165898858 ps
CPU time 0.94 seconds
Started Jul 10 07:20:02 PM PDT 24
Finished Jul 10 07:20:05 PM PDT 24
Peak memory 199972 kb
Host smart-7ba8f00e-1fc8-4d63-9b1f-0d4f7e887916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672013042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2672013042
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.686453906
Short name T496
Test name
Test status
Simulation time 835293841 ps
CPU time 4.75 seconds
Started Jul 10 07:20:05 PM PDT 24
Finished Jul 10 07:20:11 PM PDT 24
Peak memory 200444 kb
Host smart-a8ab6790-ede6-4fda-8117-e5796d59b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686453906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.686453906
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.826305285
Short name T483
Test name
Test status
Simulation time 140862361 ps
CPU time 1.15 seconds
Started Jul 10 07:20:01 PM PDT 24
Finished Jul 10 07:20:05 PM PDT 24
Peak memory 200176 kb
Host smart-25901b72-e7e7-4501-823b-7fbef8d05d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826305285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.826305285
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.881233129
Short name T143
Test name
Test status
Simulation time 109489510 ps
CPU time 1.14 seconds
Started Jul 10 07:20:00 PM PDT 24
Finished Jul 10 07:20:04 PM PDT 24
Peak memory 200296 kb
Host smart-c5590771-581e-4d32-8b8b-790582452d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881233129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.881233129
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2566316016
Short name T360
Test name
Test status
Simulation time 7520219523 ps
CPU time 27.74 seconds
Started Jul 10 07:19:57 PM PDT 24
Finished Jul 10 07:20:26 PM PDT 24
Peak memory 210596 kb
Host smart-1449f299-14ad-4eb9-b4a0-d46e5d7ff5cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566316016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2566316016
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.310008929
Short name T156
Test name
Test status
Simulation time 119066355 ps
CPU time 1.47 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:02 PM PDT 24
Peak memory 200152 kb
Host smart-830345f3-14c8-4d09-9229-7ddbab80c0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310008929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.310008929
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3457375598
Short name T7
Test name
Test status
Simulation time 206356107 ps
CPU time 1.33 seconds
Started Jul 10 07:20:01 PM PDT 24
Finished Jul 10 07:20:05 PM PDT 24
Peak memory 200148 kb
Host smart-522f3054-e54d-4f60-ab9f-ddf21db6d6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457375598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3457375598
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2166941144
Short name T165
Test name
Test status
Simulation time 72357101 ps
CPU time 0.79 seconds
Started Jul 10 07:20:05 PM PDT 24
Finished Jul 10 07:20:07 PM PDT 24
Peak memory 199960 kb
Host smart-9699ae9a-06d4-4053-8b9b-225d3c7af43f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166941144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2166941144
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.364341840
Short name T245
Test name
Test status
Simulation time 1908206337 ps
CPU time 7.63 seconds
Started Jul 10 07:20:08 PM PDT 24
Finished Jul 10 07:20:17 PM PDT 24
Peak memory 221696 kb
Host smart-c26a9ab3-ca16-47e2-b72d-0ac03b7a447e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364341840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.364341840
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.4087397928
Short name T5
Test name
Test status
Simulation time 244026121 ps
CPU time 1.14 seconds
Started Jul 10 07:20:01 PM PDT 24
Finished Jul 10 07:20:04 PM PDT 24
Peak memory 217520 kb
Host smart-9160096f-f152-4da9-a40e-f8e20aa4cac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087397928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.4087397928
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3505300753
Short name T268
Test name
Test status
Simulation time 127286953 ps
CPU time 0.85 seconds
Started Jul 10 07:20:06 PM PDT 24
Finished Jul 10 07:20:08 PM PDT 24
Peak memory 199984 kb
Host smart-552e7683-2e6c-4d25-b1a1-f47a2a7974b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505300753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3505300753
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3725847431
Short name T394
Test name
Test status
Simulation time 955419349 ps
CPU time 4.86 seconds
Started Jul 10 07:20:05 PM PDT 24
Finished Jul 10 07:20:11 PM PDT 24
Peak memory 200424 kb
Host smart-17e6bed5-5646-4ed1-a741-dff74ae114f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725847431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3725847431
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3900656961
Short name T234
Test name
Test status
Simulation time 170954634 ps
CPU time 1.16 seconds
Started Jul 10 07:20:06 PM PDT 24
Finished Jul 10 07:20:08 PM PDT 24
Peak memory 200172 kb
Host smart-200ced54-90c6-4092-b2f4-7a311a850bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900656961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3900656961
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.4292296802
Short name T475
Test name
Test status
Simulation time 206739687 ps
CPU time 1.41 seconds
Started Jul 10 07:20:02 PM PDT 24
Finished Jul 10 07:20:06 PM PDT 24
Peak memory 200348 kb
Host smart-81b56208-2523-4912-b345-8e323306d914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292296802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.4292296802
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3863238806
Short name T168
Test name
Test status
Simulation time 826754865 ps
CPU time 4.14 seconds
Started Jul 10 07:20:02 PM PDT 24
Finished Jul 10 07:20:08 PM PDT 24
Peak memory 200404 kb
Host smart-62899247-a284-4e9b-922d-f1b12256e80c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863238806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3863238806
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.814013339
Short name T226
Test name
Test status
Simulation time 438877243 ps
CPU time 2.63 seconds
Started Jul 10 07:20:01 PM PDT 24
Finished Jul 10 07:20:06 PM PDT 24
Peak memory 200188 kb
Host smart-79574903-5ee5-4b6e-b6de-6dd112b44911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814013339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.814013339
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.911004310
Short name T208
Test name
Test status
Simulation time 196570572 ps
CPU time 1.17 seconds
Started Jul 10 07:19:58 PM PDT 24
Finished Jul 10 07:20:01 PM PDT 24
Peak memory 200148 kb
Host smart-c34ff392-b453-48c8-a598-54571fdd195e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911004310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.911004310
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2898702517
Short name T405
Test name
Test status
Simulation time 101153807 ps
CPU time 0.87 seconds
Started Jul 10 07:20:17 PM PDT 24
Finished Jul 10 07:20:22 PM PDT 24
Peak memory 200156 kb
Host smart-738632e2-153e-4a1b-92a3-66a15e3ab10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898702517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2898702517
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1170754724
Short name T169
Test name
Test status
Simulation time 243988438 ps
CPU time 1.12 seconds
Started Jul 10 07:20:19 PM PDT 24
Finished Jul 10 07:20:23 PM PDT 24
Peak memory 216772 kb
Host smart-8df88d58-f33f-4e9a-8390-96c6b93f269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170754724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1170754724
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3835265883
Short name T301
Test name
Test status
Simulation time 164989598 ps
CPU time 0.86 seconds
Started Jul 10 07:20:15 PM PDT 24
Finished Jul 10 07:20:19 PM PDT 24
Peak memory 199952 kb
Host smart-beca66b7-97f8-4afd-a588-d1d5e6791b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835265883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3835265883
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2517123401
Short name T96
Test name
Test status
Simulation time 710746258 ps
CPU time 3.69 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:23 PM PDT 24
Peak memory 200412 kb
Host smart-62877120-056c-4ec0-a607-d3602d8a276d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517123401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2517123401
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.4255578393
Short name T357
Test name
Test status
Simulation time 155989963 ps
CPU time 1.17 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:20 PM PDT 24
Peak memory 200136 kb
Host smart-c3f7194d-4009-4866-84b3-ca5064fc85c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255578393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.4255578393
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1796043783
Short name T530
Test name
Test status
Simulation time 114208079 ps
CPU time 1.25 seconds
Started Jul 10 07:20:16 PM PDT 24
Finished Jul 10 07:20:21 PM PDT 24
Peak memory 200468 kb
Host smart-25190ad3-febd-4b1d-b781-b6b63a25d9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796043783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1796043783
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.791224320
Short name T101
Test name
Test status
Simulation time 10385576452 ps
CPU time 41.54 seconds
Started Jul 10 07:20:14 PM PDT 24
Finished Jul 10 07:20:59 PM PDT 24
Peak memory 200452 kb
Host smart-268a7548-7601-4745-9e24-de2a5836109f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791224320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.791224320
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2513937083
Short name T236
Test name
Test status
Simulation time 338241690 ps
CPU time 2.33 seconds
Started Jul 10 07:20:12 PM PDT 24
Finished Jul 10 07:20:16 PM PDT 24
Peak memory 200152 kb
Host smart-699b491b-fa35-46bc-8b53-ac622f0e7f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513937083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2513937083
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.946260054
Short name T484
Test name
Test status
Simulation time 77814837 ps
CPU time 0.9 seconds
Started Jul 10 07:20:13 PM PDT 24
Finished Jul 10 07:20:15 PM PDT 24
Peak memory 200160 kb
Host smart-868b4bcf-1bb9-4fc7-882e-aebd42a262f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946260054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.946260054
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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