Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 16 0 16 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_info_cp 8 0 8 100.00 100 1 1 0


Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
capture_cross 16 0 16 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8809 1 T3 24 T7 13 T8 17
auto[1] 11637 1 T1 4 T3 23 T4 4



Summary for Variable reset_info_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for reset_info_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 6297 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] 6809 1 T1 2 T2 1 T3 16
reset_info_cp[2] 3174 1 T1 1 T3 5 T4 1
reset_info_cp[4] 4186 1 T1 1 T3 10 T4 1
reset_info_cp[8] 125 1 T7 1 T8 2 T11 1
reset_info_cp[16] 123 1 T7 1 T22 1 T33 1
reset_info_cp[32] 102 1 T1 1 T11 1 T33 1
reset_info_cp[64] 100 1 T7 2 T9 1 T21 1
reset_info_cp[128] 150 1 T7 1 T8 1 T11 1



Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for capture_cross

Bins
reset_info_cpenable_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] auto[0] 3311 1 T3 7 T8 17 T10 5
reset_info_cp[1] auto[1] 2878 1 T1 1 T3 8 T4 1
reset_info_cp[2] auto[0] 992 1 T3 1 T10 1 T33 6
reset_info_cp[2] auto[1] 2182 1 T1 1 T3 4 T4 1
reset_info_cp[4] auto[0] 1561 1 T3 8 T10 6 T33 4
reset_info_cp[4] auto[1] 2625 1 T1 1 T3 2 T4 1
reset_info_cp[8] auto[0] 57 1 T7 1 T11 1 T21 1
reset_info_cp[8] auto[1] 68 1 T8 2 T37 2 T39 1
reset_info_cp[16] auto[0] 56 1 T7 1 T33 1 T38 2
reset_info_cp[16] auto[1] 67 1 T22 1 T39 1 T24 1
reset_info_cp[32] auto[0] 33 1 T11 1 T39 1 T100 1
reset_info_cp[32] auto[1] 69 1 T1 1 T33 1 T37 2
reset_info_cp[64] auto[0] 38 1 T7 2 T21 1 T138 1
reset_info_cp[64] auto[1] 62 1 T9 1 T39 3 T91 1
reset_info_cp[128] auto[0] 59 1 T7 1 T11 1 T46 1
reset_info_cp[128] auto[1] 91 1 T8 1 T33 1 T87 1

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