Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8809 |
1 |
|
|
T3 |
24 |
|
T7 |
13 |
|
T8 |
17 |
auto[1] |
11637 |
1 |
|
|
T1 |
4 |
|
T3 |
23 |
|
T4 |
4 |
Summary for Variable reset_info_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for reset_info_cp
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
6297 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
6809 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
16 |
reset_info_cp[2] |
3174 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T4 |
1 |
reset_info_cp[4] |
4186 |
1 |
|
|
T1 |
1 |
|
T3 |
10 |
|
T4 |
1 |
reset_info_cp[8] |
125 |
1 |
|
|
T7 |
1 |
|
T8 |
2 |
|
T11 |
1 |
reset_info_cp[16] |
123 |
1 |
|
|
T7 |
1 |
|
T22 |
1 |
|
T33 |
1 |
reset_info_cp[32] |
102 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T33 |
1 |
reset_info_cp[64] |
100 |
1 |
|
|
T7 |
2 |
|
T9 |
1 |
|
T21 |
1 |
reset_info_cp[128] |
150 |
1 |
|
|
T7 |
1 |
|
T8 |
1 |
|
T11 |
1 |
Summary for Cross capture_cross
Samples crossed: reset_info_cp enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for capture_cross
Bins
reset_info_cp | enable_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
auto[0] |
3311 |
1 |
|
|
T3 |
7 |
|
T8 |
17 |
|
T10 |
5 |
reset_info_cp[1] |
auto[1] |
2878 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T4 |
1 |
reset_info_cp[2] |
auto[0] |
992 |
1 |
|
|
T3 |
1 |
|
T10 |
1 |
|
T33 |
6 |
reset_info_cp[2] |
auto[1] |
2182 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T4 |
1 |
reset_info_cp[4] |
auto[0] |
1561 |
1 |
|
|
T3 |
8 |
|
T10 |
6 |
|
T33 |
4 |
reset_info_cp[4] |
auto[1] |
2625 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
1 |
reset_info_cp[8] |
auto[0] |
57 |
1 |
|
|
T7 |
1 |
|
T11 |
1 |
|
T21 |
1 |
reset_info_cp[8] |
auto[1] |
68 |
1 |
|
|
T8 |
2 |
|
T37 |
2 |
|
T39 |
1 |
reset_info_cp[16] |
auto[0] |
56 |
1 |
|
|
T7 |
1 |
|
T33 |
1 |
|
T38 |
2 |
reset_info_cp[16] |
auto[1] |
67 |
1 |
|
|
T22 |
1 |
|
T39 |
1 |
|
T24 |
1 |
reset_info_cp[32] |
auto[0] |
33 |
1 |
|
|
T11 |
1 |
|
T39 |
1 |
|
T100 |
1 |
reset_info_cp[32] |
auto[1] |
69 |
1 |
|
|
T1 |
1 |
|
T33 |
1 |
|
T37 |
2 |
reset_info_cp[64] |
auto[0] |
38 |
1 |
|
|
T7 |
2 |
|
T21 |
1 |
|
T138 |
1 |
reset_info_cp[64] |
auto[1] |
62 |
1 |
|
|
T9 |
1 |
|
T39 |
3 |
|
T91 |
1 |
reset_info_cp[128] |
auto[0] |
59 |
1 |
|
|
T7 |
1 |
|
T11 |
1 |
|
T46 |
1 |
reset_info_cp[128] |
auto[1] |
91 |
1 |
|
|
T8 |
1 |
|
T33 |
1 |
|
T87 |
1 |