Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T540 /workspace/coverage/default/18.rstmgr_reset.3992629106 Jul 11 06:42:47 PM PDT 24 Jul 11 06:42:54 PM PDT 24 1457046605 ps
T541 /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2066850507 Jul 11 06:43:26 PM PDT 24 Jul 11 06:43:28 PM PDT 24 244743690 ps
T542 /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.100221791 Jul 11 06:41:53 PM PDT 24 Jul 11 06:41:55 PM PDT 24 177360097 ps
T543 /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2347003050 Jul 11 06:42:29 PM PDT 24 Jul 11 06:42:31 PM PDT 24 243955175 ps
T544 /workspace/coverage/default/26.rstmgr_por_stretcher.100431413 Jul 11 06:43:10 PM PDT 24 Jul 11 06:43:13 PM PDT 24 173536546 ps
T63 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.987949690 Jul 11 05:42:38 PM PDT 24 Jul 11 05:42:45 PM PDT 24 176190143 ps
T59 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.581426770 Jul 11 05:42:18 PM PDT 24 Jul 11 05:42:24 PM PDT 24 139944538 ps
T60 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.814501971 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:20 PM PDT 24 67322806 ps
T61 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3177400505 Jul 11 05:42:37 PM PDT 24 Jul 11 05:42:43 PM PDT 24 101657676 ps
T117 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.711517781 Jul 11 05:42:38 PM PDT 24 Jul 11 05:42:45 PM PDT 24 355376628 ps
T64 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.900287809 Jul 11 05:42:41 PM PDT 24 Jul 11 05:42:49 PM PDT 24 126362152 ps
T545 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1042173131 Jul 11 05:42:22 PM PDT 24 Jul 11 05:42:29 PM PDT 24 64317686 ps
T62 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.315238222 Jul 11 05:42:32 PM PDT 24 Jul 11 05:42:37 PM PDT 24 82820759 ps
T65 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2793846733 Jul 11 05:42:18 PM PDT 24 Jul 11 05:42:28 PM PDT 24 634870512 ps
T71 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1391545211 Jul 11 05:42:42 PM PDT 24 Jul 11 05:42:49 PM PDT 24 111487303 ps
T66 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2573007426 Jul 11 05:42:26 PM PDT 24 Jul 11 05:42:35 PM PDT 24 787375779 ps
T107 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1225058151 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:21 PM PDT 24 56148615 ps
T94 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1995206986 Jul 11 05:42:38 PM PDT 24 Jul 11 05:42:45 PM PDT 24 334250592 ps
T95 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3342396194 Jul 11 05:42:06 PM PDT 24 Jul 11 05:42:11 PM PDT 24 155748528 ps
T108 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.407929328 Jul 11 05:42:38 PM PDT 24 Jul 11 05:42:43 PM PDT 24 84565344 ps
T115 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.519492324 Jul 11 05:42:23 PM PDT 24 Jul 11 05:42:31 PM PDT 24 472581948 ps
T96 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3530615269 Jul 11 05:42:18 PM PDT 24 Jul 11 05:42:23 PM PDT 24 133618629 ps
T109 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3955089820 Jul 11 05:42:21 PM PDT 24 Jul 11 05:42:29 PM PDT 24 136363723 ps
T97 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3455150854 Jul 11 05:42:18 PM PDT 24 Jul 11 05:42:27 PM PDT 24 432151561 ps
T98 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3316226405 Jul 11 05:42:38 PM PDT 24 Jul 11 05:42:44 PM PDT 24 195990394 ps
T546 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1979006704 Jul 11 05:42:15 PM PDT 24 Jul 11 05:42:18 PM PDT 24 61903961 ps
T110 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4100776370 Jul 11 05:42:39 PM PDT 24 Jul 11 05:42:45 PM PDT 24 135612475 ps
T111 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3597997383 Jul 11 05:42:42 PM PDT 24 Jul 11 05:42:50 PM PDT 24 79577886 ps
T99 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.410605212 Jul 11 05:42:13 PM PDT 24 Jul 11 05:42:17 PM PDT 24 163537249 ps
T116 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4205582912 Jul 11 05:42:22 PM PDT 24 Jul 11 05:42:31 PM PDT 24 505453517 ps
T124 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.588746671 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:23 PM PDT 24 230274415 ps
T547 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.701280530 Jul 11 05:42:12 PM PDT 24 Jul 11 05:42:16 PM PDT 24 223698618 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1492461033 Jul 11 05:42:07 PM PDT 24 Jul 11 05:42:11 PM PDT 24 77066601 ps
T126 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3780047735 Jul 11 05:42:42 PM PDT 24 Jul 11 05:42:50 PM PDT 24 481580967 ps
T549 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3582712978 Jul 11 05:42:20 PM PDT 24 Jul 11 05:42:28 PM PDT 24 459169301 ps
T550 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1920126049 Jul 11 05:42:16 PM PDT 24 Jul 11 05:42:19 PM PDT 24 217956982 ps
T123 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.160002708 Jul 11 05:42:19 PM PDT 24 Jul 11 05:42:26 PM PDT 24 492985832 ps
T112 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1100429884 Jul 11 05:42:12 PM PDT 24 Jul 11 05:42:15 PM PDT 24 109364409 ps
T113 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.840174715 Jul 11 05:42:33 PM PDT 24 Jul 11 05:42:39 PM PDT 24 59361748 ps
T551 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4030738252 Jul 11 05:42:09 PM PDT 24 Jul 11 05:42:13 PM PDT 24 177412263 ps
T552 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3566339462 Jul 11 05:42:06 PM PDT 24 Jul 11 05:42:18 PM PDT 24 1580633841 ps
T553 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2022249816 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:20 PM PDT 24 103410494 ps
T125 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1582150517 Jul 11 05:42:38 PM PDT 24 Jul 11 05:42:45 PM PDT 24 357109699 ps
T114 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4124164682 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:20 PM PDT 24 64573162 ps
T127 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3401502010 Jul 11 05:42:16 PM PDT 24 Jul 11 05:42:22 PM PDT 24 457418341 ps
T554 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3761660580 Jul 11 05:42:19 PM PDT 24 Jul 11 05:42:26 PM PDT 24 172659440 ps
T555 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2225245288 Jul 11 05:42:21 PM PDT 24 Jul 11 05:42:28 PM PDT 24 139912277 ps
T556 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1107165822 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:21 PM PDT 24 76993182 ps
T557 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.559312310 Jul 11 05:42:07 PM PDT 24 Jul 11 05:42:13 PM PDT 24 275708252 ps
T558 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.633723070 Jul 11 05:42:01 PM PDT 24 Jul 11 05:42:07 PM PDT 24 83321820 ps
T128 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1186919012 Jul 11 05:42:27 PM PDT 24 Jul 11 05:42:34 PM PDT 24 155736450 ps
T129 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1278977494 Jul 11 05:42:39 PM PDT 24 Jul 11 05:42:48 PM PDT 24 550709443 ps
T559 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2873549927 Jul 11 05:42:16 PM PDT 24 Jul 11 05:42:19 PM PDT 24 65998944 ps
T118 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1476744605 Jul 11 05:42:07 PM PDT 24 Jul 11 05:42:14 PM PDT 24 930538826 ps
T560 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3105427017 Jul 11 05:42:18 PM PDT 24 Jul 11 05:42:24 PM PDT 24 479196619 ps
T561 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.480531053 Jul 11 05:42:21 PM PDT 24 Jul 11 05:42:27 PM PDT 24 63817604 ps
T562 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3225861158 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:25 PM PDT 24 602656697 ps
T563 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3101933367 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:21 PM PDT 24 68521982 ps
T564 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3569539980 Jul 11 05:42:19 PM PDT 24 Jul 11 05:42:25 PM PDT 24 82533308 ps
T565 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.308913057 Jul 11 05:42:20 PM PDT 24 Jul 11 05:42:27 PM PDT 24 208607755 ps
T566 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1115680734 Jul 11 05:42:18 PM PDT 24 Jul 11 05:42:22 PM PDT 24 145913216 ps
T567 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1228729048 Jul 11 05:42:08 PM PDT 24 Jul 11 05:42:13 PM PDT 24 285699446 ps
T568 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.4140286388 Jul 11 05:42:20 PM PDT 24 Jul 11 05:42:30 PM PDT 24 780455214 ps
T569 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.418310962 Jul 11 05:42:07 PM PDT 24 Jul 11 05:42:20 PM PDT 24 2272096128 ps
T570 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3989016115 Jul 11 05:42:26 PM PDT 24 Jul 11 05:42:33 PM PDT 24 125981282 ps
T571 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3696332328 Jul 11 05:42:21 PM PDT 24 Jul 11 05:42:28 PM PDT 24 157576963 ps
T572 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3500176589 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:20 PM PDT 24 85498932 ps
T137 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3545386224 Jul 11 05:42:16 PM PDT 24 Jul 11 05:42:22 PM PDT 24 896082995 ps
T573 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3370663752 Jul 11 05:42:18 PM PDT 24 Jul 11 05:42:26 PM PDT 24 304324128 ps
T574 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4209080809 Jul 11 05:42:22 PM PDT 24 Jul 11 05:42:31 PM PDT 24 496776749 ps
T575 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.77209992 Jul 11 05:42:06 PM PDT 24 Jul 11 05:42:11 PM PDT 24 258068803 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1910974921 Jul 11 05:42:37 PM PDT 24 Jul 11 05:42:45 PM PDT 24 353192057 ps
T577 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1787798700 Jul 11 05:42:05 PM PDT 24 Jul 11 05:42:11 PM PDT 24 470947018 ps
T578 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3540187343 Jul 11 05:42:18 PM PDT 24 Jul 11 05:42:23 PM PDT 24 58445915 ps
T120 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.957359766 Jul 11 05:42:19 PM PDT 24 Jul 11 05:42:27 PM PDT 24 483084191 ps
T579 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1466222313 Jul 11 05:42:03 PM PDT 24 Jul 11 05:42:10 PM PDT 24 194362801 ps
T580 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2899470318 Jul 11 05:42:08 PM PDT 24 Jul 11 05:42:14 PM PDT 24 911445278 ps
T581 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.323313408 Jul 11 05:42:20 PM PDT 24 Jul 11 05:42:28 PM PDT 24 270871107 ps
T582 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3123446872 Jul 11 05:42:05 PM PDT 24 Jul 11 05:42:13 PM PDT 24 524318006 ps
T583 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1044289860 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:20 PM PDT 24 54738014 ps
T584 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2809231499 Jul 11 05:42:49 PM PDT 24 Jul 11 05:42:56 PM PDT 24 54699176 ps
T585 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2541967083 Jul 11 05:42:19 PM PDT 24 Jul 11 05:42:28 PM PDT 24 482704708 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4055725479 Jul 11 05:42:38 PM PDT 24 Jul 11 05:42:44 PM PDT 24 120779785 ps
T587 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.771821740 Jul 11 05:42:31 PM PDT 24 Jul 11 05:42:37 PM PDT 24 253356795 ps
T588 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.970555646 Jul 11 05:42:39 PM PDT 24 Jul 11 05:42:46 PM PDT 24 278915712 ps
T589 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3879045599 Jul 11 05:42:13 PM PDT 24 Jul 11 05:42:16 PM PDT 24 169233200 ps
T590 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3520914251 Jul 11 05:42:09 PM PDT 24 Jul 11 05:42:13 PM PDT 24 240827688 ps
T591 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.880585549 Jul 11 05:42:19 PM PDT 24 Jul 11 05:42:27 PM PDT 24 397069100 ps
T592 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1219953434 Jul 11 05:42:39 PM PDT 24 Jul 11 05:42:47 PM PDT 24 882076483 ps
T593 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.860199481 Jul 11 05:42:42 PM PDT 24 Jul 11 05:42:50 PM PDT 24 196149498 ps
T594 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.179809943 Jul 11 05:42:15 PM PDT 24 Jul 11 05:42:18 PM PDT 24 105492768 ps
T595 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3990698866 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:22 PM PDT 24 181576289 ps
T596 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3985160767 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:22 PM PDT 24 197443325 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.997858162 Jul 11 05:42:14 PM PDT 24 Jul 11 05:42:18 PM PDT 24 280818822 ps
T598 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1321403720 Jul 11 05:42:32 PM PDT 24 Jul 11 05:42:37 PM PDT 24 200365239 ps
T599 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4074945949 Jul 11 05:42:19 PM PDT 24 Jul 11 05:42:27 PM PDT 24 203032913 ps
T600 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2761692621 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:22 PM PDT 24 190494554 ps
T601 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1539268749 Jul 11 05:42:19 PM PDT 24 Jul 11 05:42:25 PM PDT 24 75952447 ps
T602 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3223387636 Jul 11 05:42:42 PM PDT 24 Jul 11 05:42:49 PM PDT 24 196538368 ps
T603 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.778384561 Jul 11 05:42:32 PM PDT 24 Jul 11 05:42:37 PM PDT 24 75123537 ps
T604 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4526710 Jul 11 05:42:18 PM PDT 24 Jul 11 05:42:25 PM PDT 24 291374776 ps
T605 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2488392144 Jul 11 05:42:38 PM PDT 24 Jul 11 05:42:44 PM PDT 24 184694878 ps
T606 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3131694455 Jul 11 05:42:15 PM PDT 24 Jul 11 05:42:22 PM PDT 24 480400722 ps
T607 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3470625263 Jul 11 05:42:19 PM PDT 24 Jul 11 05:42:25 PM PDT 24 92104876 ps
T608 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.415770128 Jul 11 05:42:26 PM PDT 24 Jul 11 05:42:34 PM PDT 24 477657544 ps
T609 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.23508521 Jul 11 05:42:17 PM PDT 24 Jul 11 05:42:21 PM PDT 24 259617332 ps
T119 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.166696362 Jul 11 05:42:05 PM PDT 24 Jul 11 05:42:13 PM PDT 24 935240417 ps
T610 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3847512342 Jul 11 05:42:42 PM PDT 24 Jul 11 05:42:50 PM PDT 24 127688582 ps
T611 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2999387785 Jul 11 05:42:45 PM PDT 24 Jul 11 05:42:52 PM PDT 24 65820637 ps
T612 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2584509341 Jul 11 05:42:22 PM PDT 24 Jul 11 05:42:30 PM PDT 24 179080320 ps
T121 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3247387008 Jul 11 05:42:18 PM PDT 24 Jul 11 05:42:26 PM PDT 24 416732885 ps
T613 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.994029350 Jul 11 05:42:20 PM PDT 24 Jul 11 05:42:27 PM PDT 24 121362724 ps
T614 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3069845876 Jul 11 05:42:15 PM PDT 24 Jul 11 05:42:18 PM PDT 24 107574473 ps
T615 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2440942639 Jul 11 05:42:21 PM PDT 24 Jul 11 05:42:28 PM PDT 24 118695502 ps
T616 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.25821312 Jul 11 05:42:42 PM PDT 24 Jul 11 05:42:50 PM PDT 24 170491657 ps
T617 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1432924447 Jul 11 05:42:21 PM PDT 24 Jul 11 05:42:28 PM PDT 24 74025716 ps
T122 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.690469339 Jul 11 05:42:18 PM PDT 24 Jul 11 05:42:25 PM PDT 24 807751091 ps
T618 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1485543203 Jul 11 05:42:28 PM PDT 24 Jul 11 05:42:34 PM PDT 24 135747718 ps
T619 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1249898872 Jul 11 05:42:21 PM PDT 24 Jul 11 05:42:36 PM PDT 24 2291415942 ps
T620 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2426658691 Jul 11 05:42:32 PM PDT 24 Jul 11 05:42:38 PM PDT 24 443127567 ps

Test location /workspace/coverage/default/10.rstmgr_reset.2708288711
Short name T10
Test name
Test status
Simulation time 1432173911 ps
CPU time 6.13 seconds
Started Jul 11 06:42:24 PM PDT 24
Finished Jul 11 06:42:31 PM PDT 24
Peak memory 200428 kb
Host smart-44ff6625-fb7a-49b3-810d-5287e0b3f8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708288711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2708288711
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.497455009
Short name T34
Test name
Test status
Simulation time 116232573 ps
CPU time 1.53 seconds
Started Jul 11 06:43:35 PM PDT 24
Finished Jul 11 06:43:38 PM PDT 24
Peak memory 200368 kb
Host smart-c8bdf066-570a-450a-b5f6-8bedb9a979f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497455009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.497455009
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1960702799
Short name T11
Test name
Test status
Simulation time 272281911 ps
CPU time 1.46 seconds
Started Jul 11 06:43:32 PM PDT 24
Finished Jul 11 06:43:35 PM PDT 24
Peak memory 200380 kb
Host smart-cd07bee1-ac1d-4d0b-a020-96deedf603d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960702799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1960702799
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.900287809
Short name T64
Test name
Test status
Simulation time 126362152 ps
CPU time 1.4 seconds
Started Jul 11 05:42:41 PM PDT 24
Finished Jul 11 05:42:49 PM PDT 24
Peak memory 208700 kb
Host smart-e4a893a8-8408-40ab-bb44-0615e1cc251d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900287809 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.900287809
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.841196524
Short name T73
Test name
Test status
Simulation time 18965095457 ps
CPU time 27.18 seconds
Started Jul 11 06:41:48 PM PDT 24
Finished Jul 11 06:42:17 PM PDT 24
Peak memory 218172 kb
Host smart-52ff64f6-cfb5-474d-94ea-1ee99d4d0890
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841196524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.841196524
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1532919078
Short name T24
Test name
Test status
Simulation time 2152749920 ps
CPU time 8.03 seconds
Started Jul 11 06:43:36 PM PDT 24
Finished Jul 11 06:43:46 PM PDT 24
Peak memory 217868 kb
Host smart-59fac988-8721-4e55-b124-b9e2e66c0ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532919078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1532919078
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.519492324
Short name T115
Test name
Test status
Simulation time 472581948 ps
CPU time 2.05 seconds
Started Jul 11 05:42:23 PM PDT 24
Finished Jul 11 05:42:31 PM PDT 24
Peak memory 200580 kb
Host smart-a777ac09-d5f3-4f5c-b744-cf5e3902dd1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519492324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.519492324
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.791599785
Short name T70
Test name
Test status
Simulation time 74956857 ps
CPU time 0.78 seconds
Started Jul 11 06:42:49 PM PDT 24
Finished Jul 11 06:42:51 PM PDT 24
Peak memory 199928 kb
Host smart-e5648787-d0f8-4f3c-9ce3-aec064ee9e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791599785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.791599785
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3590090448
Short name T39
Test name
Test status
Simulation time 4185939895 ps
CPU time 17.54 seconds
Started Jul 11 06:43:33 PM PDT 24
Finished Jul 11 06:43:51 PM PDT 24
Peak memory 208708 kb
Host smart-0d5127bd-a1c1-4c8c-ab39-0f1824e462dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590090448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3590090448
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3092416145
Short name T51
Test name
Test status
Simulation time 8207177800 ps
CPU time 29.81 seconds
Started Jul 11 06:42:15 PM PDT 24
Finished Jul 11 06:42:46 PM PDT 24
Peak memory 200544 kb
Host smart-a446337e-3be4-4bbb-b852-b4b96a76048e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092416145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3092416145
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2314286620
Short name T1
Test name
Test status
Simulation time 173074659 ps
CPU time 1.21 seconds
Started Jul 11 06:43:08 PM PDT 24
Finished Jul 11 06:43:11 PM PDT 24
Peak memory 200228 kb
Host smart-71d40da8-efc0-4edd-b5c0-6ba97e271bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314286620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2314286620
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1582150517
Short name T125
Test name
Test status
Simulation time 357109699 ps
CPU time 2.6 seconds
Started Jul 11 05:42:38 PM PDT 24
Finished Jul 11 05:42:45 PM PDT 24
Peak memory 208352 kb
Host smart-e77ece79-319e-4290-8499-4bda74c91c04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582150517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1582150517
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1476744605
Short name T118
Test name
Test status
Simulation time 930538826 ps
CPU time 3.4 seconds
Started Jul 11 05:42:07 PM PDT 24
Finished Jul 11 05:42:14 PM PDT 24
Peak memory 200484 kb
Host smart-f8985e83-ca7a-476f-be18-e59a94ad5654
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476744605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1476744605
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1648676035
Short name T41
Test name
Test status
Simulation time 1886669393 ps
CPU time 7.75 seconds
Started Jul 11 06:42:21 PM PDT 24
Finished Jul 11 06:42:31 PM PDT 24
Peak memory 217748 kb
Host smart-bf5ffe24-6117-489b-b614-a5eb0f3fc017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648676035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1648676035
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3555719653
Short name T91
Test name
Test status
Simulation time 2230843572 ps
CPU time 9.8 seconds
Started Jul 11 06:42:30 PM PDT 24
Finished Jul 11 06:42:42 PM PDT 24
Peak memory 208692 kb
Host smart-bad3f305-7938-4a88-a9ea-f7ec3d925393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555719653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3555719653
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2213566585
Short name T53
Test name
Test status
Simulation time 1225464768 ps
CPU time 5.86 seconds
Started Jul 11 06:43:28 PM PDT 24
Finished Jul 11 06:43:35 PM PDT 24
Peak memory 217824 kb
Host smart-22373816-7d11-4361-8468-fe27e16e7f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213566585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2213566585
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3247387008
Short name T121
Test name
Test status
Simulation time 416732885 ps
CPU time 1.85 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:26 PM PDT 24
Peak memory 200504 kb
Host smart-1f1bb705-b886-497b-9bd9-6f68ed4fa6de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247387008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3247387008
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3123446872
Short name T582
Test name
Test status
Simulation time 524318006 ps
CPU time 3.52 seconds
Started Jul 11 05:42:05 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 216692 kb
Host smart-dc7ec291-a2ea-4996-a10e-70a057392034
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123446872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3123446872
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.407929328
Short name T108
Test name
Test status
Simulation time 84565344 ps
CPU time 0.87 seconds
Started Jul 11 05:42:38 PM PDT 24
Finished Jul 11 05:42:43 PM PDT 24
Peak memory 200192 kb
Host smart-79d59998-f4f9-4fd8-81e0-36252be490e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407929328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.407929328
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3168819516
Short name T17
Test name
Test status
Simulation time 249987639 ps
CPU time 1.09 seconds
Started Jul 11 06:42:44 PM PDT 24
Finished Jul 11 06:42:46 PM PDT 24
Peak memory 199976 kb
Host smart-a1cfe76c-ab0d-47d5-a522-88d82f952a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168819516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3168819516
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.690469339
Short name T122
Test name
Test status
Simulation time 807751091 ps
CPU time 2.74 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:25 PM PDT 24
Peak memory 200532 kb
Host smart-507865ac-0f9c-45ee-bf5d-fcdfad7a5753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690469339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
690469339
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3696332328
Short name T571
Test name
Test status
Simulation time 157576963 ps
CPU time 1.94 seconds
Started Jul 11 05:42:21 PM PDT 24
Finished Jul 11 05:42:28 PM PDT 24
Peak memory 200360 kb
Host smart-875f415c-b621-4b6c-810e-119f63b14f7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696332328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
696332328
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3566339462
Short name T552
Test name
Test status
Simulation time 1580633841 ps
CPU time 8.44 seconds
Started Jul 11 05:42:06 PM PDT 24
Finished Jul 11 05:42:18 PM PDT 24
Peak memory 200500 kb
Host smart-de0c691a-9513-4de2-8245-af6b1341cd06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566339462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
566339462
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3989016115
Short name T570
Test name
Test status
Simulation time 125981282 ps
CPU time 0.97 seconds
Started Jul 11 05:42:26 PM PDT 24
Finished Jul 11 05:42:33 PM PDT 24
Peak memory 200276 kb
Host smart-e9131bba-f632-47be-aa50-4409769cbb97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989016115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
989016115
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3761660580
Short name T554
Test name
Test status
Simulation time 172659440 ps
CPU time 1.56 seconds
Started Jul 11 05:42:19 PM PDT 24
Finished Jul 11 05:42:26 PM PDT 24
Peak memory 208760 kb
Host smart-41253589-f9c1-43ca-8d0b-64b96d0b5a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761660580 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3761660580
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3470625263
Short name T607
Test name
Test status
Simulation time 92104876 ps
CPU time 1.07 seconds
Started Jul 11 05:42:19 PM PDT 24
Finished Jul 11 05:42:25 PM PDT 24
Peak memory 200364 kb
Host smart-1c8f3554-adf8-4955-9534-de36c62f21f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470625263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3470625263
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1910974921
Short name T576
Test name
Test status
Simulation time 353192057 ps
CPU time 2.29 seconds
Started Jul 11 05:42:37 PM PDT 24
Finished Jul 11 05:42:45 PM PDT 24
Peak memory 200348 kb
Host smart-348b9178-f770-44f5-880a-37a5e9008143
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910974921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
910974921
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3131694455
Short name T606
Test name
Test status
Simulation time 480400722 ps
CPU time 5.52 seconds
Started Jul 11 05:42:15 PM PDT 24
Finished Jul 11 05:42:22 PM PDT 24
Peak memory 200472 kb
Host smart-c9ff0de1-f5a3-4ced-964f-c5814d24233e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131694455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
131694455
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3069845876
Short name T614
Test name
Test status
Simulation time 107574473 ps
CPU time 0.82 seconds
Started Jul 11 05:42:15 PM PDT 24
Finished Jul 11 05:42:18 PM PDT 24
Peak memory 200252 kb
Host smart-50d50509-0a83-435a-9418-04aa45f1e695
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069845876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
069845876
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3342396194
Short name T95
Test name
Test status
Simulation time 155748528 ps
CPU time 1.28 seconds
Started Jul 11 05:42:06 PM PDT 24
Finished Jul 11 05:42:11 PM PDT 24
Peak memory 200404 kb
Host smart-06c514f1-28f2-41f3-9352-21c5f081b652
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342396194 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3342396194
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.633723070
Short name T558
Test name
Test status
Simulation time 83321820 ps
CPU time 0.88 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:07 PM PDT 24
Peak memory 200248 kb
Host smart-9f873182-e506-4a41-8461-1648617051c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633723070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.633723070
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.308913057
Short name T565
Test name
Test status
Simulation time 208607755 ps
CPU time 1.42 seconds
Started Jul 11 05:42:20 PM PDT 24
Finished Jul 11 05:42:27 PM PDT 24
Peak memory 200464 kb
Host smart-6c25a12c-dfef-4ad7-9cbf-96d8cac01d0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308913057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.308913057
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4205582912
Short name T116
Test name
Test status
Simulation time 505453517 ps
CPU time 1.89 seconds
Started Jul 11 05:42:22 PM PDT 24
Finished Jul 11 05:42:31 PM PDT 24
Peak memory 200476 kb
Host smart-0f20f61d-f53d-4590-85b1-7e26b6c7a8d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205582912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.4205582912
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3530615269
Short name T96
Test name
Test status
Simulation time 133618629 ps
CPU time 1.52 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:23 PM PDT 24
Peak memory 208676 kb
Host smart-81889eef-ec84-461c-850f-2b6619acee83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530615269 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3530615269
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3569539980
Short name T564
Test name
Test status
Simulation time 82533308 ps
CPU time 0.85 seconds
Started Jul 11 05:42:19 PM PDT 24
Finished Jul 11 05:42:25 PM PDT 24
Peak memory 200304 kb
Host smart-7e72c017-20a7-4e1a-bd6e-74905b9ba208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569539980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3569539980
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.581426770
Short name T59
Test name
Test status
Simulation time 139944538 ps
CPU time 1.16 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:24 PM PDT 24
Peak memory 200264 kb
Host smart-c01053b2-1d97-4f3f-bd2a-d81a4784a53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581426770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.581426770
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.987949690
Short name T63
Test name
Test status
Simulation time 176190143 ps
CPU time 2.48 seconds
Started Jul 11 05:42:38 PM PDT 24
Finished Jul 11 05:42:45 PM PDT 24
Peak memory 208612 kb
Host smart-0c5e2bbb-e5df-43a4-8240-a13e630bee80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987949690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.987949690
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.160002708
Short name T123
Test name
Test status
Simulation time 492985832 ps
CPU time 1.99 seconds
Started Jul 11 05:42:19 PM PDT 24
Finished Jul 11 05:42:26 PM PDT 24
Peak memory 200564 kb
Host smart-b99ecfad-8171-4f67-9889-899e568f9af9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160002708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.160002708
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2584509341
Short name T612
Test name
Test status
Simulation time 179080320 ps
CPU time 1.68 seconds
Started Jul 11 05:42:22 PM PDT 24
Finished Jul 11 05:42:30 PM PDT 24
Peak memory 208784 kb
Host smart-5e839c87-25ad-4021-91f4-f720c2cf9982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584509341 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2584509341
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.778384561
Short name T603
Test name
Test status
Simulation time 75123537 ps
CPU time 0.89 seconds
Started Jul 11 05:42:32 PM PDT 24
Finished Jul 11 05:42:37 PM PDT 24
Peak memory 200236 kb
Host smart-6a683105-d6de-46b8-9028-09b358343381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778384561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.778384561
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.970555646
Short name T588
Test name
Test status
Simulation time 278915712 ps
CPU time 1.63 seconds
Started Jul 11 05:42:39 PM PDT 24
Finished Jul 11 05:42:46 PM PDT 24
Peak memory 200420 kb
Host smart-b26177a4-28e4-4a58-9a9e-3ed519c44216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970555646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.970555646
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3370663752
Short name T573
Test name
Test status
Simulation time 304324128 ps
CPU time 2.09 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:26 PM PDT 24
Peak memory 208628 kb
Host smart-5c047bb0-4892-4bd4-8d3c-5459f5778434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370663752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3370663752
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2899470318
Short name T580
Test name
Test status
Simulation time 911445278 ps
CPU time 3.03 seconds
Started Jul 11 05:42:08 PM PDT 24
Finished Jul 11 05:42:14 PM PDT 24
Peak memory 200472 kb
Host smart-e8bd34ac-4640-4a4f-905e-eb572373ebe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899470318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2899470318
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4030738252
Short name T551
Test name
Test status
Simulation time 177412263 ps
CPU time 1.17 seconds
Started Jul 11 05:42:09 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 208552 kb
Host smart-3d3ee52f-f381-48c4-9614-9aa37f07bfa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030738252 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.4030738252
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1042173131
Short name T545
Test name
Test status
Simulation time 64317686 ps
CPU time 0.78 seconds
Started Jul 11 05:42:22 PM PDT 24
Finished Jul 11 05:42:29 PM PDT 24
Peak memory 200316 kb
Host smart-9533c8d2-6609-4840-87b4-36f524f398d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042173131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1042173131
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.771821740
Short name T587
Test name
Test status
Simulation time 253356795 ps
CPU time 1.78 seconds
Started Jul 11 05:42:31 PM PDT 24
Finished Jul 11 05:42:37 PM PDT 24
Peak memory 200496 kb
Host smart-474c76e2-a28d-4807-8eda-c50b5b3a0f47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771821740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.771821740
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.701280530
Short name T547
Test name
Test status
Simulation time 223698618 ps
CPU time 1.73 seconds
Started Jul 11 05:42:12 PM PDT 24
Finished Jul 11 05:42:16 PM PDT 24
Peak memory 208564 kb
Host smart-5163dd9f-c91b-4171-bfea-489ca8b3a0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701280530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.701280530
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1321403720
Short name T598
Test name
Test status
Simulation time 200365239 ps
CPU time 1.33 seconds
Started Jul 11 05:42:32 PM PDT 24
Finished Jul 11 05:42:37 PM PDT 24
Peak memory 200440 kb
Host smart-b7726570-aede-48ff-861f-1606a30b6fda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321403720 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1321403720
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1432924447
Short name T617
Test name
Test status
Simulation time 74025716 ps
CPU time 0.77 seconds
Started Jul 11 05:42:21 PM PDT 24
Finished Jul 11 05:42:28 PM PDT 24
Peak memory 200252 kb
Host smart-f3322e1b-c261-464d-b90f-70303cedbf5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432924447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1432924447
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3520914251
Short name T590
Test name
Test status
Simulation time 240827688 ps
CPU time 1.52 seconds
Started Jul 11 05:42:09 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 200428 kb
Host smart-57c742aa-d0cf-4843-b2f0-87449f217989
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520914251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3520914251
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1278977494
Short name T129
Test name
Test status
Simulation time 550709443 ps
CPU time 3.44 seconds
Started Jul 11 05:42:39 PM PDT 24
Finished Jul 11 05:42:48 PM PDT 24
Peak memory 212284 kb
Host smart-a7f64303-cc69-4d24-b9c6-008c6a7a9cba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278977494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1278977494
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3582712978
Short name T549
Test name
Test status
Simulation time 459169301 ps
CPU time 1.71 seconds
Started Jul 11 05:42:20 PM PDT 24
Finished Jul 11 05:42:28 PM PDT 24
Peak memory 200588 kb
Host smart-61f1355b-da2e-4537-9c81-a2e20e2ba41b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582712978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3582712978
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3223387636
Short name T602
Test name
Test status
Simulation time 196538368 ps
CPU time 1.2 seconds
Started Jul 11 05:42:42 PM PDT 24
Finished Jul 11 05:42:49 PM PDT 24
Peak memory 208636 kb
Host smart-83d6bee3-fbee-49ce-b5a3-48a1cb2167e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223387636 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3223387636
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1044289860
Short name T583
Test name
Test status
Simulation time 54738014 ps
CPU time 0.77 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:20 PM PDT 24
Peak memory 200524 kb
Host smart-55074f00-d23a-44c0-99cc-2e8ca3bdf8c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044289860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1044289860
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3597997383
Short name T111
Test name
Test status
Simulation time 79577886 ps
CPU time 0.98 seconds
Started Jul 11 05:42:42 PM PDT 24
Finished Jul 11 05:42:50 PM PDT 24
Peak memory 200364 kb
Host smart-b733d01d-aacb-48d2-ba09-383ffe7927bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597997383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3597997383
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4526710
Short name T604
Test name
Test status
Simulation time 291374776 ps
CPU time 2.19 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:25 PM PDT 24
Peak memory 208512 kb
Host smart-f6b20408-c80f-4cb5-a220-d24497991f0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4526710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4526710
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1219953434
Short name T592
Test name
Test status
Simulation time 882076483 ps
CPU time 3.08 seconds
Started Jul 11 05:42:39 PM PDT 24
Finished Jul 11 05:42:47 PM PDT 24
Peak memory 200444 kb
Host smart-e158ebf2-c717-4ec8-ac9b-8655b7e28752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219953434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1219953434
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.860199481
Short name T593
Test name
Test status
Simulation time 196149498 ps
CPU time 1.2 seconds
Started Jul 11 05:42:42 PM PDT 24
Finished Jul 11 05:42:50 PM PDT 24
Peak memory 208296 kb
Host smart-04439817-05dd-47d3-a045-c605b95d7c2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860199481 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.860199481
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.814501971
Short name T60
Test name
Test status
Simulation time 67322806 ps
CPU time 0.77 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:20 PM PDT 24
Peak memory 200492 kb
Host smart-7a36c3c7-2b1e-4c0f-b41c-6f32b1a221cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814501971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.814501971
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1228729048
Short name T567
Test name
Test status
Simulation time 285699446 ps
CPU time 1.68 seconds
Started Jul 11 05:42:08 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 200416 kb
Host smart-07176ef5-5e04-4644-a393-d3045ba7b9a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228729048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1228729048
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3455150854
Short name T97
Test name
Test status
Simulation time 432151561 ps
CPU time 2.87 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:27 PM PDT 24
Peak memory 208812 kb
Host smart-2636b8e4-4a60-419a-8dfc-85f95af9fe09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455150854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3455150854
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3545386224
Short name T137
Test name
Test status
Simulation time 896082995 ps
CPU time 3.13 seconds
Started Jul 11 05:42:16 PM PDT 24
Finished Jul 11 05:42:22 PM PDT 24
Peak memory 200512 kb
Host smart-9a884edb-3acf-4e22-b933-680d97ea7dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545386224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3545386224
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4124164682
Short name T114
Test name
Test status
Simulation time 64573162 ps
CPU time 0.78 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:20 PM PDT 24
Peak memory 200524 kb
Host smart-9eb3afbb-58e9-47d2-ba2c-a2d70e6e80b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124164682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.4124164682
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3955089820
Short name T109
Test name
Test status
Simulation time 136363723 ps
CPU time 1.09 seconds
Started Jul 11 05:42:21 PM PDT 24
Finished Jul 11 05:42:29 PM PDT 24
Peak memory 200380 kb
Host smart-37ed25d3-44b4-4328-b7fb-0124938b126f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955089820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3955089820
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3401502010
Short name T127
Test name
Test status
Simulation time 457418341 ps
CPU time 3.65 seconds
Started Jul 11 05:42:16 PM PDT 24
Finished Jul 11 05:42:22 PM PDT 24
Peak memory 208580 kb
Host smart-a3f74d7d-b4a5-4e26-9861-793cf465106a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401502010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3401502010
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2426658691
Short name T620
Test name
Test status
Simulation time 443127567 ps
CPU time 1.87 seconds
Started Jul 11 05:42:32 PM PDT 24
Finished Jul 11 05:42:38 PM PDT 24
Peak memory 200544 kb
Host smart-9a95d7db-ce04-4c90-97b1-32a801f4b906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426658691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2426658691
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2488392144
Short name T605
Test name
Test status
Simulation time 184694878 ps
CPU time 1.16 seconds
Started Jul 11 05:42:38 PM PDT 24
Finished Jul 11 05:42:44 PM PDT 24
Peak memory 200428 kb
Host smart-875a869c-1509-41c6-9d9a-4e99404ed8f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488392144 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2488392144
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.840174715
Short name T113
Test name
Test status
Simulation time 59361748 ps
CPU time 0.83 seconds
Started Jul 11 05:42:33 PM PDT 24
Finished Jul 11 05:42:39 PM PDT 24
Peak memory 200284 kb
Host smart-6b89d44b-0ec0-4b90-aabd-243ed4b7f750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840174715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.840174715
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1100429884
Short name T112
Test name
Test status
Simulation time 109364409 ps
CPU time 1.27 seconds
Started Jul 11 05:42:12 PM PDT 24
Finished Jul 11 05:42:15 PM PDT 24
Peak memory 200500 kb
Host smart-8836c542-d161-4cb3-96cb-6caa66ab4415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100429884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1100429884
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.410605212
Short name T99
Test name
Test status
Simulation time 163537249 ps
CPU time 2.25 seconds
Started Jul 11 05:42:13 PM PDT 24
Finished Jul 11 05:42:17 PM PDT 24
Peak memory 208628 kb
Host smart-25896b9c-2934-423d-849f-7b38497d9c93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410605212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.410605212
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.415770128
Short name T608
Test name
Test status
Simulation time 477657544 ps
CPU time 1.91 seconds
Started Jul 11 05:42:26 PM PDT 24
Finished Jul 11 05:42:34 PM PDT 24
Peak memory 200524 kb
Host smart-7b26026e-2df6-4506-b3f9-a0cccaf9ab05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415770128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.415770128
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1485543203
Short name T618
Test name
Test status
Simulation time 135747718 ps
CPU time 1.13 seconds
Started Jul 11 05:42:28 PM PDT 24
Finished Jul 11 05:42:34 PM PDT 24
Peak memory 208672 kb
Host smart-7334af63-3c87-4333-b869-e3ad99e00e52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485543203 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1485543203
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2809231499
Short name T584
Test name
Test status
Simulation time 54699176 ps
CPU time 0.77 seconds
Started Jul 11 05:42:49 PM PDT 24
Finished Jul 11 05:42:56 PM PDT 24
Peak memory 200252 kb
Host smart-2c23e5bb-409b-41a2-ac2b-989a8b2941dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809231499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2809231499
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3847512342
Short name T610
Test name
Test status
Simulation time 127688582 ps
CPU time 1.13 seconds
Started Jul 11 05:42:42 PM PDT 24
Finished Jul 11 05:42:50 PM PDT 24
Peak memory 200372 kb
Host smart-b33a86e9-6814-45da-811b-b60fd5c5f338
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847512342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3847512342
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3225861158
Short name T562
Test name
Test status
Simulation time 602656697 ps
CPU time 3.62 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:25 PM PDT 24
Peak memory 212264 kb
Host smart-5474949f-3924-4873-a5a6-572f09530b52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225861158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3225861158
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2573007426
Short name T66
Test name
Test status
Simulation time 787375779 ps
CPU time 3.02 seconds
Started Jul 11 05:42:26 PM PDT 24
Finished Jul 11 05:42:35 PM PDT 24
Peak memory 200488 kb
Host smart-297ab975-11fc-4b30-81ad-c244f94eb0ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573007426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2573007426
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1186919012
Short name T128
Test name
Test status
Simulation time 155736450 ps
CPU time 1.37 seconds
Started Jul 11 05:42:27 PM PDT 24
Finished Jul 11 05:42:34 PM PDT 24
Peak memory 208608 kb
Host smart-c417d136-efbb-464e-ab4c-c51f08150416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186919012 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1186919012
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2999387785
Short name T611
Test name
Test status
Simulation time 65820637 ps
CPU time 0.81 seconds
Started Jul 11 05:42:45 PM PDT 24
Finished Jul 11 05:42:52 PM PDT 24
Peak memory 200284 kb
Host smart-c34614af-542e-42ea-932b-baad81a609a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999387785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2999387785
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4100776370
Short name T110
Test name
Test status
Simulation time 135612475 ps
CPU time 1.02 seconds
Started Jul 11 05:42:39 PM PDT 24
Finished Jul 11 05:42:45 PM PDT 24
Peak memory 200352 kb
Host smart-ea5f2ee0-abc7-4d9b-a2e0-b013d56463c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100776370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.4100776370
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.23508521
Short name T609
Test name
Test status
Simulation time 259617332 ps
CPU time 2.02 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:21 PM PDT 24
Peak memory 208516 kb
Host smart-82d37360-eacf-417f-9a7f-683e1253d3b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23508521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.23508521
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4074945949
Short name T599
Test name
Test status
Simulation time 203032913 ps
CPU time 1.65 seconds
Started Jul 11 05:42:19 PM PDT 24
Finished Jul 11 05:42:27 PM PDT 24
Peak memory 200464 kb
Host smart-85e803c7-7164-452b-a326-f8ccfdd14410
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074945949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.4
074945949
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.4140286388
Short name T568
Test name
Test status
Simulation time 780455214 ps
CPU time 4.33 seconds
Started Jul 11 05:42:20 PM PDT 24
Finished Jul 11 05:42:30 PM PDT 24
Peak memory 200348 kb
Host smart-129285a0-9c39-4103-bba7-692bed66ee8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140286388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.4
140286388
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3177400505
Short name T61
Test name
Test status
Simulation time 101657676 ps
CPU time 0.82 seconds
Started Jul 11 05:42:37 PM PDT 24
Finished Jul 11 05:42:43 PM PDT 24
Peak memory 200200 kb
Host smart-f102fd2c-da4a-42db-8d37-007be34d8318
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177400505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
177400505
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2022249816
Short name T553
Test name
Test status
Simulation time 103410494 ps
CPU time 0.97 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:20 PM PDT 24
Peak memory 200436 kb
Host smart-8bf9833d-3daa-45a8-8e68-5dd78c362260
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022249816 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2022249816
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1492461033
Short name T548
Test name
Test status
Simulation time 77066601 ps
CPU time 0.82 seconds
Started Jul 11 05:42:07 PM PDT 24
Finished Jul 11 05:42:11 PM PDT 24
Peak memory 200524 kb
Host smart-e8acf86b-ec75-4d89-b19d-11f1f8d304b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492461033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1492461033
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3985160767
Short name T596
Test name
Test status
Simulation time 197443325 ps
CPU time 1.41 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:22 PM PDT 24
Peak memory 200512 kb
Host smart-c736608c-e505-40ad-a465-48f9fa99984f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985160767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3985160767
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.994029350
Short name T613
Test name
Test status
Simulation time 121362724 ps
CPU time 1.43 seconds
Started Jul 11 05:42:20 PM PDT 24
Finished Jul 11 05:42:27 PM PDT 24
Peak memory 210880 kb
Host smart-c641f959-2447-4275-9b1b-e4abe4cd8c94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994029350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.994029350
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1787798700
Short name T577
Test name
Test status
Simulation time 470947018 ps
CPU time 2.09 seconds
Started Jul 11 05:42:05 PM PDT 24
Finished Jul 11 05:42:11 PM PDT 24
Peak memory 200792 kb
Host smart-b518cbc9-8814-4568-b8b6-be4fe112a2ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787798700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1787798700
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.711517781
Short name T117
Test name
Test status
Simulation time 355376628 ps
CPU time 2.59 seconds
Started Jul 11 05:42:38 PM PDT 24
Finished Jul 11 05:42:45 PM PDT 24
Peak memory 200092 kb
Host smart-7acdfabb-5f89-41b8-8a45-03dcc9ea1fc5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711517781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.711517781
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1249898872
Short name T619
Test name
Test status
Simulation time 2291415942 ps
CPU time 9.55 seconds
Started Jul 11 05:42:21 PM PDT 24
Finished Jul 11 05:42:36 PM PDT 24
Peak memory 200400 kb
Host smart-b6140637-16d3-4c89-b5a9-fe9422ce772f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249898872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
249898872
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1115680734
Short name T566
Test name
Test status
Simulation time 145913216 ps
CPU time 0.9 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:22 PM PDT 24
Peak memory 200312 kb
Host smart-6214e30c-0daf-40cf-8438-736f37a5bad6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115680734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
115680734
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3990698866
Short name T595
Test name
Test status
Simulation time 181576289 ps
CPU time 1.54 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:22 PM PDT 24
Peak memory 208836 kb
Host smart-fdf4ce18-e12b-4d65-a906-9b1e15efddce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990698866 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3990698866
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3540187343
Short name T578
Test name
Test status
Simulation time 58445915 ps
CPU time 0.74 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:23 PM PDT 24
Peak memory 200304 kb
Host smart-b2d870dc-719a-42e4-b2d5-e48c198f58fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540187343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3540187343
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4055725479
Short name T586
Test name
Test status
Simulation time 120779785 ps
CPU time 1.03 seconds
Started Jul 11 05:42:38 PM PDT 24
Finished Jul 11 05:42:44 PM PDT 24
Peak memory 200252 kb
Host smart-befa3c0e-aaae-4981-8634-c3ef32d3a4b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055725479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4055725479
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.997858162
Short name T597
Test name
Test status
Simulation time 280818822 ps
CPU time 1.98 seconds
Started Jul 11 05:42:14 PM PDT 24
Finished Jul 11 05:42:18 PM PDT 24
Peak memory 208644 kb
Host smart-f1e65214-9f8d-4ebd-a1dc-927d77ab349c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997858162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.997858162
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4209080809
Short name T574
Test name
Test status
Simulation time 496776749 ps
CPU time 1.94 seconds
Started Jul 11 05:42:22 PM PDT 24
Finished Jul 11 05:42:31 PM PDT 24
Peak memory 200480 kb
Host smart-50a40256-91bf-4c88-bbc0-3ead5ef93b65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209080809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.4209080809
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.880585549
Short name T591
Test name
Test status
Simulation time 397069100 ps
CPU time 2.52 seconds
Started Jul 11 05:42:19 PM PDT 24
Finished Jul 11 05:42:27 PM PDT 24
Peak memory 208660 kb
Host smart-be11fd17-d104-481f-a04b-4aeb8e4fdcb9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880585549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.880585549
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.418310962
Short name T569
Test name
Test status
Simulation time 2272096128 ps
CPU time 9.66 seconds
Started Jul 11 05:42:07 PM PDT 24
Finished Jul 11 05:42:20 PM PDT 24
Peak memory 200776 kb
Host smart-ab873ac3-aed5-4980-b5d9-baf94da0b91f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418310962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.418310962
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2225245288
Short name T555
Test name
Test status
Simulation time 139912277 ps
CPU time 0.95 seconds
Started Jul 11 05:42:21 PM PDT 24
Finished Jul 11 05:42:28 PM PDT 24
Peak memory 200152 kb
Host smart-0ff1b7e8-e656-48d9-a54e-fcb9b5c53b87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225245288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
225245288
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2440942639
Short name T615
Test name
Test status
Simulation time 118695502 ps
CPU time 0.91 seconds
Started Jul 11 05:42:21 PM PDT 24
Finished Jul 11 05:42:28 PM PDT 24
Peak memory 200332 kb
Host smart-e2bc5db1-b47d-4e75-b16b-d8b34ea9c1a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440942639 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2440942639
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3101933367
Short name T563
Test name
Test status
Simulation time 68521982 ps
CPU time 0.78 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:21 PM PDT 24
Peak memory 200312 kb
Host smart-7081ca8e-f1a7-443a-98f2-ec606eef5c2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101933367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3101933367
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.77209992
Short name T575
Test name
Test status
Simulation time 258068803 ps
CPU time 1.54 seconds
Started Jul 11 05:42:06 PM PDT 24
Finished Jul 11 05:42:11 PM PDT 24
Peak memory 200456 kb
Host smart-2c8228c5-b2a9-44f4-a35e-cab3efaf3087
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77209992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same
_csr_outstanding.77209992
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.588746671
Short name T124
Test name
Test status
Simulation time 230274415 ps
CPU time 1.85 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:23 PM PDT 24
Peak memory 208616 kb
Host smart-42ee575d-6bfd-48a0-904a-d08c12fd5f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588746671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.588746671
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2541967083
Short name T585
Test name
Test status
Simulation time 482704708 ps
CPU time 1.98 seconds
Started Jul 11 05:42:19 PM PDT 24
Finished Jul 11 05:42:28 PM PDT 24
Peak memory 200568 kb
Host smart-62dea4c2-63e0-4ba6-89cf-839d28305e10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541967083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2541967083
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1466222313
Short name T579
Test name
Test status
Simulation time 194362801 ps
CPU time 1.77 seconds
Started Jul 11 05:42:03 PM PDT 24
Finished Jul 11 05:42:10 PM PDT 24
Peak memory 208828 kb
Host smart-9ab93c19-c395-4905-b531-b5f0abe028c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466222313 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1466222313
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1225058151
Short name T107
Test name
Test status
Simulation time 56148615 ps
CPU time 0.76 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:21 PM PDT 24
Peak memory 200244 kb
Host smart-784642f4-8f89-4052-8ba9-d31838a2054c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225058151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1225058151
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3500176589
Short name T572
Test name
Test status
Simulation time 85498932 ps
CPU time 1.01 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:20 PM PDT 24
Peak memory 200376 kb
Host smart-0bf1f3d8-3227-4e2f-8e78-f1f3a1c9fe96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500176589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3500176589
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1920126049
Short name T550
Test name
Test status
Simulation time 217956982 ps
CPU time 1.53 seconds
Started Jul 11 05:42:16 PM PDT 24
Finished Jul 11 05:42:19 PM PDT 24
Peak memory 200420 kb
Host smart-42d0ccd4-3c07-4b39-abbf-8f59fe5efeee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920126049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1920126049
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.25821312
Short name T616
Test name
Test status
Simulation time 170491657 ps
CPU time 1.51 seconds
Started Jul 11 05:42:42 PM PDT 24
Finished Jul 11 05:42:50 PM PDT 24
Peak memory 208828 kb
Host smart-c2b718a6-813f-451e-89a7-8b6c1e5de40f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25821312 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.25821312
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.480531053
Short name T561
Test name
Test status
Simulation time 63817604 ps
CPU time 0.78 seconds
Started Jul 11 05:42:21 PM PDT 24
Finished Jul 11 05:42:27 PM PDT 24
Peak memory 200320 kb
Host smart-6d152ae7-b230-4fec-980b-9b626a306997
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480531053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.480531053
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1107165822
Short name T556
Test name
Test status
Simulation time 76993182 ps
CPU time 1.01 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:21 PM PDT 24
Peak memory 200560 kb
Host smart-1ac1aaed-5d0d-4402-83d7-a130dad0890c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107165822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1107165822
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.179809943
Short name T594
Test name
Test status
Simulation time 105492768 ps
CPU time 1.31 seconds
Started Jul 11 05:42:15 PM PDT 24
Finished Jul 11 05:42:18 PM PDT 24
Peak memory 208636 kb
Host smart-af805fcc-f243-43d5-aa6b-d85f56e7a0b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179809943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.179809943
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.957359766
Short name T120
Test name
Test status
Simulation time 483084191 ps
CPU time 1.87 seconds
Started Jul 11 05:42:19 PM PDT 24
Finished Jul 11 05:42:27 PM PDT 24
Peak memory 200532 kb
Host smart-692b5e4f-b94f-43f5-8291-b06fa3898a42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957359766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
957359766
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3316226405
Short name T98
Test name
Test status
Simulation time 195990394 ps
CPU time 1.18 seconds
Started Jul 11 05:42:38 PM PDT 24
Finished Jul 11 05:42:44 PM PDT 24
Peak memory 200352 kb
Host smart-15919fbd-0084-4306-9b68-85941cc08eea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316226405 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3316226405
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2873549927
Short name T559
Test name
Test status
Simulation time 65998944 ps
CPU time 0.83 seconds
Started Jul 11 05:42:16 PM PDT 24
Finished Jul 11 05:42:19 PM PDT 24
Peak memory 200248 kb
Host smart-d9009ef1-0e21-4ec6-b3f9-2effd22238fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873549927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2873549927
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.323313408
Short name T581
Test name
Test status
Simulation time 270871107 ps
CPU time 1.68 seconds
Started Jul 11 05:42:20 PM PDT 24
Finished Jul 11 05:42:28 PM PDT 24
Peak memory 200500 kb
Host smart-78182d12-4a4d-44eb-abe9-8541cdf7f3e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323313408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.323313408
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2793846733
Short name T65
Test name
Test status
Simulation time 634870512 ps
CPU time 3.98 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:28 PM PDT 24
Peak memory 208824 kb
Host smart-7d012673-6fe0-4a22-8336-1325e95e2e63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793846733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2793846733
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3105427017
Short name T560
Test name
Test status
Simulation time 479196619 ps
CPU time 1.84 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:24 PM PDT 24
Peak memory 200532 kb
Host smart-91aa9aee-83a5-443d-aea1-1df5b36a55fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105427017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3105427017
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2761692621
Short name T600
Test name
Test status
Simulation time 190494554 ps
CPU time 1.23 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:22 PM PDT 24
Peak memory 200644 kb
Host smart-c334bb35-3fea-4eb3-991f-96cd386c8036
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761692621 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2761692621
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1539268749
Short name T601
Test name
Test status
Simulation time 75952447 ps
CPU time 0.81 seconds
Started Jul 11 05:42:19 PM PDT 24
Finished Jul 11 05:42:25 PM PDT 24
Peak memory 200304 kb
Host smart-862e9ba3-4451-4d3f-91d6-c5ea427c7e6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539268749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1539268749
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3879045599
Short name T589
Test name
Test status
Simulation time 169233200 ps
CPU time 1.2 seconds
Started Jul 11 05:42:13 PM PDT 24
Finished Jul 11 05:42:16 PM PDT 24
Peak memory 200236 kb
Host smart-5c581391-8f92-47a3-b9b9-475d4803cdd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879045599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3879045599
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.559312310
Short name T557
Test name
Test status
Simulation time 275708252 ps
CPU time 2.34 seconds
Started Jul 11 05:42:07 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 216752 kb
Host smart-c7b6d5bb-40e6-42b0-a09e-548b78dea59b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559312310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.559312310
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3780047735
Short name T126
Test name
Test status
Simulation time 481580967 ps
CPU time 1.83 seconds
Started Jul 11 05:42:42 PM PDT 24
Finished Jul 11 05:42:50 PM PDT 24
Peak memory 200572 kb
Host smart-0b5b790e-8deb-4edd-990f-047ec181df8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780047735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3780047735
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1391545211
Short name T71
Test name
Test status
Simulation time 111487303 ps
CPU time 0.93 seconds
Started Jul 11 05:42:42 PM PDT 24
Finished Jul 11 05:42:49 PM PDT 24
Peak memory 200084 kb
Host smart-72e03668-0f0e-4193-8e64-dd23e86072c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391545211 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1391545211
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1979006704
Short name T546
Test name
Test status
Simulation time 61903961 ps
CPU time 0.85 seconds
Started Jul 11 05:42:15 PM PDT 24
Finished Jul 11 05:42:18 PM PDT 24
Peak memory 200292 kb
Host smart-97effcdc-217e-4864-afae-fcc8ee2ab2cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979006704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1979006704
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.315238222
Short name T62
Test name
Test status
Simulation time 82820759 ps
CPU time 1.04 seconds
Started Jul 11 05:42:32 PM PDT 24
Finished Jul 11 05:42:37 PM PDT 24
Peak memory 200364 kb
Host smart-460f6895-c326-429b-b90e-3addade3b3aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315238222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.315238222
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1995206986
Short name T94
Test name
Test status
Simulation time 334250592 ps
CPU time 2.24 seconds
Started Jul 11 05:42:38 PM PDT 24
Finished Jul 11 05:42:45 PM PDT 24
Peak memory 211156 kb
Host smart-6529f12b-17f0-43d4-8d87-7f3a51bacc76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995206986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1995206986
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.166696362
Short name T119
Test name
Test status
Simulation time 935240417 ps
CPU time 3.39 seconds
Started Jul 11 05:42:05 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 200584 kb
Host smart-f7d4a0dd-f8a7-4f00-b9ca-ecc679bc3820
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166696362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
166696362
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1816009015
Short name T234
Test name
Test status
Simulation time 73657310 ps
CPU time 0.85 seconds
Started Jul 11 06:41:52 PM PDT 24
Finished Jul 11 06:41:54 PM PDT 24
Peak memory 199964 kb
Host smart-782c9746-8a69-42bf-9424-1c7eea9a4054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816009015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1816009015
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1727520371
Short name T44
Test name
Test status
Simulation time 1222800051 ps
CPU time 5.59 seconds
Started Jul 11 06:41:46 PM PDT 24
Finished Jul 11 06:41:53 PM PDT 24
Peak memory 217648 kb
Host smart-30dcff2c-1561-47ac-a420-4d770610d5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727520371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1727520371
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2054554720
Short name T86
Test name
Test status
Simulation time 247370033 ps
CPU time 1.08 seconds
Started Jul 11 06:41:49 PM PDT 24
Finished Jul 11 06:41:51 PM PDT 24
Peak memory 217548 kb
Host smart-63720ec4-81d4-4e4c-8391-2767025beb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054554720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2054554720
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.906969166
Short name T301
Test name
Test status
Simulation time 161284720 ps
CPU time 0.83 seconds
Started Jul 11 06:41:49 PM PDT 24
Finished Jul 11 06:41:51 PM PDT 24
Peak memory 199892 kb
Host smart-d9012ad5-a79f-4fb7-a9ed-593e873cd5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906969166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.906969166
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.42712089
Short name T521
Test name
Test status
Simulation time 1375455886 ps
CPU time 5.47 seconds
Started Jul 11 06:41:47 PM PDT 24
Finished Jul 11 06:41:54 PM PDT 24
Peak memory 200468 kb
Host smart-5bd3d93f-d546-45db-8eaf-5717f8b0e6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42712089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.42712089
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1968944146
Short name T446
Test name
Test status
Simulation time 146575606 ps
CPU time 1.09 seconds
Started Jul 11 06:41:46 PM PDT 24
Finished Jul 11 06:41:48 PM PDT 24
Peak memory 200160 kb
Host smart-bde93198-fa19-428b-85db-20c6b941fd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968944146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1968944146
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1140198028
Short name T92
Test name
Test status
Simulation time 218730955 ps
CPU time 1.42 seconds
Started Jul 11 06:41:48 PM PDT 24
Finished Jul 11 06:41:50 PM PDT 24
Peak memory 200260 kb
Host smart-2ac845bf-682a-4558-97b8-7d74ad020fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140198028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1140198028
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3904240588
Short name T454
Test name
Test status
Simulation time 6321381389 ps
CPU time 27.55 seconds
Started Jul 11 06:41:48 PM PDT 24
Finished Jul 11 06:42:16 PM PDT 24
Peak memory 200688 kb
Host smart-d89e5a41-5019-4107-9f21-61cfc4692404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904240588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3904240588
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2382045613
Short name T363
Test name
Test status
Simulation time 278445090 ps
CPU time 1.98 seconds
Started Jul 11 06:41:47 PM PDT 24
Finished Jul 11 06:41:51 PM PDT 24
Peak memory 200160 kb
Host smart-c8fe6279-8306-4c94-a332-04e29ec9024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382045613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2382045613
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2219875041
Short name T529
Test name
Test status
Simulation time 171122819 ps
CPU time 1.16 seconds
Started Jul 11 06:41:48 PM PDT 24
Finished Jul 11 06:41:50 PM PDT 24
Peak memory 200156 kb
Host smart-1837c94a-2571-465e-95e6-1836a4904835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219875041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2219875041
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.234599571
Short name T418
Test name
Test status
Simulation time 147083170 ps
CPU time 1.02 seconds
Started Jul 11 06:41:55 PM PDT 24
Finished Jul 11 06:41:57 PM PDT 24
Peak memory 200160 kb
Host smart-918bb7ce-46bb-42d0-a679-e7c630bcd99e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234599571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.234599571
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3457079672
Short name T394
Test name
Test status
Simulation time 1215547602 ps
CPU time 6.12 seconds
Started Jul 11 06:41:54 PM PDT 24
Finished Jul 11 06:42:02 PM PDT 24
Peak memory 221092 kb
Host smart-d70f92f2-d335-45d7-8ecf-292ad8e29f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457079672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3457079672
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3415300426
Short name T285
Test name
Test status
Simulation time 244790837 ps
CPU time 1.09 seconds
Started Jul 11 06:41:54 PM PDT 24
Finished Jul 11 06:41:56 PM PDT 24
Peak memory 217440 kb
Host smart-15027c77-c1d6-4cc0-b44c-2256924ad637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415300426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3415300426
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.4004561874
Short name T364
Test name
Test status
Simulation time 222700372 ps
CPU time 0.93 seconds
Started Jul 11 06:41:53 PM PDT 24
Finished Jul 11 06:41:55 PM PDT 24
Peak memory 200040 kb
Host smart-dbc7ea84-c1a3-49ee-b5af-b623da8ed533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004561874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.4004561874
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1545514052
Short name T105
Test name
Test status
Simulation time 1600122767 ps
CPU time 6.12 seconds
Started Jul 11 06:41:51 PM PDT 24
Finished Jul 11 06:41:58 PM PDT 24
Peak memory 200340 kb
Host smart-8167a4d2-0d0c-4e8e-84f7-19776857b482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545514052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1545514052
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2811186870
Short name T68
Test name
Test status
Simulation time 16589964284 ps
CPU time 25.24 seconds
Started Jul 11 06:41:53 PM PDT 24
Finished Jul 11 06:42:19 PM PDT 24
Peak memory 218256 kb
Host smart-705186d6-448f-4ceb-ab0c-503823e56ef2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811186870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2811186870
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.100221791
Short name T542
Test name
Test status
Simulation time 177360097 ps
CPU time 1.21 seconds
Started Jul 11 06:41:53 PM PDT 24
Finished Jul 11 06:41:55 PM PDT 24
Peak memory 200180 kb
Host smart-c8d2afda-a1e0-49d7-a5e7-d149674ad398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100221791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.100221791
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.4054250641
Short name T194
Test name
Test status
Simulation time 201536403 ps
CPU time 1.34 seconds
Started Jul 11 06:41:55 PM PDT 24
Finished Jul 11 06:41:57 PM PDT 24
Peak memory 200360 kb
Host smart-6e42aa00-1251-42ff-9d50-8a29c1b8657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054250641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4054250641
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.4049176773
Short name T455
Test name
Test status
Simulation time 4013400462 ps
CPU time 18 seconds
Started Jul 11 06:41:54 PM PDT 24
Finished Jul 11 06:42:13 PM PDT 24
Peak memory 208732 kb
Host smart-f1fdfdc7-2ec4-4a6c-8065-2aedb00a90f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049176773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.4049176773
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1141749339
Short name T88
Test name
Test status
Simulation time 340745101 ps
CPU time 2.26 seconds
Started Jul 11 06:41:52 PM PDT 24
Finished Jul 11 06:41:55 PM PDT 24
Peak memory 208260 kb
Host smart-8744e055-29b5-4c82-80f0-0421841c39b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141749339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1141749339
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1824037007
Short name T265
Test name
Test status
Simulation time 225231934 ps
CPU time 1.4 seconds
Started Jul 11 06:41:53 PM PDT 24
Finished Jul 11 06:41:55 PM PDT 24
Peak memory 200340 kb
Host smart-590dd427-4235-475c-a81e-9946455da221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824037007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1824037007
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2554699969
Short name T178
Test name
Test status
Simulation time 73363529 ps
CPU time 0.77 seconds
Started Jul 11 06:42:23 PM PDT 24
Finished Jul 11 06:42:25 PM PDT 24
Peak memory 199972 kb
Host smart-08341d8e-2c7e-4c87-b42e-9e889467f045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554699969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2554699969
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1608522150
Short name T366
Test name
Test status
Simulation time 243500005 ps
CPU time 1.11 seconds
Started Jul 11 06:42:22 PM PDT 24
Finished Jul 11 06:42:25 PM PDT 24
Peak memory 217520 kb
Host smart-61d1c578-16c6-407d-bbdb-3ccc17f4ab10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608522150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1608522150
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2171895624
Short name T258
Test name
Test status
Simulation time 137449075 ps
CPU time 0.84 seconds
Started Jul 11 06:42:24 PM PDT 24
Finished Jul 11 06:42:26 PM PDT 24
Peak memory 199920 kb
Host smart-dcb0997f-ca51-4f69-a9dc-bcab0203e2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171895624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2171895624
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.317348357
Short name T208
Test name
Test status
Simulation time 182498125 ps
CPU time 1.28 seconds
Started Jul 11 06:48:49 PM PDT 24
Finished Jul 11 06:48:51 PM PDT 24
Peak memory 200232 kb
Host smart-34d0b1a3-1788-4dd5-9d9c-2707cb40b5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317348357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.317348357
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2548306317
Short name T148
Test name
Test status
Simulation time 118440140 ps
CPU time 1.2 seconds
Started Jul 11 06:42:21 PM PDT 24
Finished Jul 11 06:42:24 PM PDT 24
Peak memory 200400 kb
Host smart-b9b8fc84-870c-470f-9681-fc18175ca6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548306317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2548306317
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3813588893
Short name T331
Test name
Test status
Simulation time 7501589937 ps
CPU time 39.16 seconds
Started Jul 11 06:42:22 PM PDT 24
Finished Jul 11 06:43:03 PM PDT 24
Peak memory 208684 kb
Host smart-d8b4a546-23af-4d08-8b6c-603ab8f42218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813588893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3813588893
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.4064739692
Short name T361
Test name
Test status
Simulation time 144900748 ps
CPU time 1.97 seconds
Started Jul 11 06:42:23 PM PDT 24
Finished Jul 11 06:42:27 PM PDT 24
Peak memory 200164 kb
Host smart-38610506-38cf-45f8-bcfc-c13b1779ba7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064739692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.4064739692
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.4015547729
Short name T353
Test name
Test status
Simulation time 85112916 ps
CPU time 0.84 seconds
Started Jul 11 06:42:23 PM PDT 24
Finished Jul 11 06:42:26 PM PDT 24
Peak memory 200180 kb
Host smart-d297d091-8aff-455b-918a-cec68d82585b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015547729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.4015547729
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.4112465975
Short name T168
Test name
Test status
Simulation time 79493230 ps
CPU time 0.86 seconds
Started Jul 11 06:42:28 PM PDT 24
Finished Jul 11 06:42:30 PM PDT 24
Peak memory 199964 kb
Host smart-7c424f22-579b-4893-b53d-4fdedbbded67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112465975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.4112465975
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.700871523
Short name T57
Test name
Test status
Simulation time 1228297649 ps
CPU time 5.63 seconds
Started Jul 11 06:42:27 PM PDT 24
Finished Jul 11 06:42:34 PM PDT 24
Peak memory 216864 kb
Host smart-24d2ef4a-2559-4b8e-b4c2-fade2140d12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700871523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.700871523
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3137885262
Short name T84
Test name
Test status
Simulation time 244831182 ps
CPU time 1.07 seconds
Started Jul 11 06:42:40 PM PDT 24
Finished Jul 11 06:42:42 PM PDT 24
Peak memory 217540 kb
Host smart-a75112de-ea5d-4d9a-80b2-b6dea121e875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137885262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3137885262
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3516780933
Short name T381
Test name
Test status
Simulation time 123037246 ps
CPU time 0.86 seconds
Started Jul 11 06:42:23 PM PDT 24
Finished Jul 11 06:42:25 PM PDT 24
Peak memory 199928 kb
Host smart-5b6d0590-b92b-4b3d-9eef-b891cfd17beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516780933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3516780933
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4757554
Short name T177
Test name
Test status
Simulation time 969670632 ps
CPU time 5.26 seconds
Started Jul 11 06:42:25 PM PDT 24
Finished Jul 11 06:42:32 PM PDT 24
Peak memory 200504 kb
Host smart-daa27a9f-a978-439f-8831-aae2505ad5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4757554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4757554
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1208632987
Short name T443
Test name
Test status
Simulation time 105119415 ps
CPU time 1.02 seconds
Started Jul 11 06:42:28 PM PDT 24
Finished Jul 11 06:42:30 PM PDT 24
Peak memory 200132 kb
Host smart-f07b120d-edda-4496-a58f-45d7a154b123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208632987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1208632987
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3319831764
Short name T83
Test name
Test status
Simulation time 119867131 ps
CPU time 1.23 seconds
Started Jul 11 06:42:24 PM PDT 24
Finished Jul 11 06:42:27 PM PDT 24
Peak memory 200348 kb
Host smart-29e03fae-9ba8-4635-ad2f-823b38ca7213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319831764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3319831764
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.4275102135
Short name T205
Test name
Test status
Simulation time 4430402142 ps
CPU time 20.5 seconds
Started Jul 11 06:42:26 PM PDT 24
Finished Jul 11 06:42:47 PM PDT 24
Peak memory 209708 kb
Host smart-f9986148-926b-4341-901e-8551c5a18f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275102135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.4275102135
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1423580019
Short name T264
Test name
Test status
Simulation time 397333851 ps
CPU time 2.32 seconds
Started Jul 11 06:42:24 PM PDT 24
Finished Jul 11 06:42:28 PM PDT 24
Peak memory 200216 kb
Host smart-f4e8b399-ae83-4c3c-ad31-2af4ed86bf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423580019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1423580019
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2309575858
Short name T87
Test name
Test status
Simulation time 234497368 ps
CPU time 1.47 seconds
Started Jul 11 06:42:23 PM PDT 24
Finished Jul 11 06:42:27 PM PDT 24
Peak memory 200136 kb
Host smart-86612f28-fc0c-4dea-ad1a-82775025f295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309575858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2309575858
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1019548723
Short name T362
Test name
Test status
Simulation time 75447965 ps
CPU time 0.81 seconds
Started Jul 11 06:42:28 PM PDT 24
Finished Jul 11 06:42:30 PM PDT 24
Peak memory 199968 kb
Host smart-91ce0412-3264-4c7a-a240-04a4cdabdfec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019548723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1019548723
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2247170347
Short name T491
Test name
Test status
Simulation time 2366791020 ps
CPU time 8.44 seconds
Started Jul 11 06:42:27 PM PDT 24
Finished Jul 11 06:42:36 PM PDT 24
Peak memory 221772 kb
Host smart-a46d4ea2-551c-4b07-9812-5d654e32848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247170347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2247170347
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2347003050
Short name T543
Test name
Test status
Simulation time 243955175 ps
CPU time 1.07 seconds
Started Jul 11 06:42:29 PM PDT 24
Finished Jul 11 06:42:31 PM PDT 24
Peak memory 217536 kb
Host smart-98a989c5-fb8b-4211-b62b-bac8acb0f21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347003050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2347003050
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3579611585
Short name T404
Test name
Test status
Simulation time 87537889 ps
CPU time 0.73 seconds
Started Jul 11 06:42:29 PM PDT 24
Finished Jul 11 06:42:31 PM PDT 24
Peak memory 199984 kb
Host smart-3217abd6-d5b6-4853-8b2b-e25a2e1304a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579611585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3579611585
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3520156781
Short name T444
Test name
Test status
Simulation time 1782042125 ps
CPU time 6.95 seconds
Started Jul 11 06:42:29 PM PDT 24
Finished Jul 11 06:42:37 PM PDT 24
Peak memory 200444 kb
Host smart-1eadf48b-5762-4252-9cac-528dfb35b927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520156781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3520156781
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1267329428
Short name T374
Test name
Test status
Simulation time 177494460 ps
CPU time 1.23 seconds
Started Jul 11 06:42:40 PM PDT 24
Finished Jul 11 06:42:42 PM PDT 24
Peak memory 200172 kb
Host smart-6fbc68a8-06d2-4aab-8962-9bd0b1c745f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267329428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1267329428
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1021066577
Short name T260
Test name
Test status
Simulation time 202483279 ps
CPU time 1.47 seconds
Started Jul 11 06:42:27 PM PDT 24
Finished Jul 11 06:42:30 PM PDT 24
Peak memory 200444 kb
Host smart-f2855dee-4613-4a83-a1d0-7cce4c2cdae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021066577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1021066577
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2696373596
Short name T352
Test name
Test status
Simulation time 232116596 ps
CPU time 1.19 seconds
Started Jul 11 06:42:28 PM PDT 24
Finished Jul 11 06:42:30 PM PDT 24
Peak memory 200048 kb
Host smart-816c313a-41aa-4fc6-aa8f-62276b25808f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696373596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2696373596
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2955106219
Short name T419
Test name
Test status
Simulation time 135498357 ps
CPU time 1.66 seconds
Started Jul 11 06:42:29 PM PDT 24
Finished Jul 11 06:42:32 PM PDT 24
Peak memory 208408 kb
Host smart-a0713364-07e1-4075-9a66-71e6b6a382df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955106219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2955106219
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.4148457603
Short name T386
Test name
Test status
Simulation time 236231329 ps
CPU time 1.35 seconds
Started Jul 11 06:42:27 PM PDT 24
Finished Jul 11 06:42:29 PM PDT 24
Peak memory 200180 kb
Host smart-9a1dd08d-5440-4d34-ad96-b459bdc182f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148457603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.4148457603
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1672549406
Short name T195
Test name
Test status
Simulation time 61207913 ps
CPU time 0.75 seconds
Started Jul 11 06:42:31 PM PDT 24
Finished Jul 11 06:42:33 PM PDT 24
Peak memory 199956 kb
Host smart-2c6b45a4-1299-485c-93af-bbda80d2eada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672549406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1672549406
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1872708574
Short name T37
Test name
Test status
Simulation time 2357840496 ps
CPU time 8.28 seconds
Started Jul 11 06:42:31 PM PDT 24
Finished Jul 11 06:42:41 PM PDT 24
Peak memory 217396 kb
Host smart-b9dbcba6-1ef5-489b-9419-e37ca51262c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872708574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1872708574
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.942175406
Short name T78
Test name
Test status
Simulation time 244526204 ps
CPU time 1.08 seconds
Started Jul 11 06:42:30 PM PDT 24
Finished Jul 11 06:42:33 PM PDT 24
Peak memory 217548 kb
Host smart-cb2006ff-e7a4-4d42-aa93-66917493ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942175406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.942175406
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3236164339
Short name T243
Test name
Test status
Simulation time 183489360 ps
CPU time 0.93 seconds
Started Jul 11 06:42:28 PM PDT 24
Finished Jul 11 06:42:30 PM PDT 24
Peak memory 200068 kb
Host smart-bd7d6455-0067-4ee0-947d-740bacdd36fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236164339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3236164339
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.613359554
Short name T162
Test name
Test status
Simulation time 838046048 ps
CPU time 4.5 seconds
Started Jul 11 06:42:27 PM PDT 24
Finished Jul 11 06:42:32 PM PDT 24
Peak memory 200384 kb
Host smart-96006962-656d-4779-b38e-2764657b9aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613359554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.613359554
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1219738220
Short name T9
Test name
Test status
Simulation time 155190753 ps
CPU time 1.08 seconds
Started Jul 11 06:42:32 PM PDT 24
Finished Jul 11 06:42:35 PM PDT 24
Peak memory 200072 kb
Host smart-ab06b0a5-2584-4aaa-b746-19bb3dc0e946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219738220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1219738220
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.4096575299
Short name T134
Test name
Test status
Simulation time 255167730 ps
CPU time 1.65 seconds
Started Jul 11 06:42:29 PM PDT 24
Finished Jul 11 06:42:32 PM PDT 24
Peak memory 200360 kb
Host smart-4d253c83-b869-48ee-9aa1-15af2c906a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096575299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.4096575299
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2889887978
Short name T481
Test name
Test status
Simulation time 145499904 ps
CPU time 1.96 seconds
Started Jul 11 06:42:32 PM PDT 24
Finished Jul 11 06:42:35 PM PDT 24
Peak memory 200152 kb
Host smart-8e97ffbc-8960-47a7-93fe-653c17ef1c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889887978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2889887978
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1321608228
Short name T166
Test name
Test status
Simulation time 262451114 ps
CPU time 1.56 seconds
Started Jul 11 06:42:32 PM PDT 24
Finished Jul 11 06:42:35 PM PDT 24
Peak memory 200168 kb
Host smart-3a781984-bc5a-44b5-83f2-a3f39655f410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321608228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1321608228
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.679334217
Short name T503
Test name
Test status
Simulation time 66327542 ps
CPU time 0.8 seconds
Started Jul 11 06:42:35 PM PDT 24
Finished Jul 11 06:42:37 PM PDT 24
Peak memory 200016 kb
Host smart-bb1263b1-68e7-4763-b2c6-441f5ebc7fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679334217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.679334217
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.886898987
Short name T40
Test name
Test status
Simulation time 1894414979 ps
CPU time 7.25 seconds
Started Jul 11 06:42:30 PM PDT 24
Finished Jul 11 06:42:39 PM PDT 24
Peak memory 217824 kb
Host smart-5385e4f0-b9b5-4b04-a7f6-91184b4478a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886898987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.886898987
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2048118278
Short name T281
Test name
Test status
Simulation time 252196700 ps
CPU time 1.09 seconds
Started Jul 11 06:42:29 PM PDT 24
Finished Jul 11 06:42:31 PM PDT 24
Peak memory 217548 kb
Host smart-fad394f2-5c07-4566-8d9a-4fb028304c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048118278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2048118278
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1578873130
Short name T502
Test name
Test status
Simulation time 227365362 ps
CPU time 0.95 seconds
Started Jul 11 06:42:30 PM PDT 24
Finished Jul 11 06:42:33 PM PDT 24
Peak memory 199972 kb
Host smart-7206510d-1d35-43ba-922c-90bbb57a5e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578873130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1578873130
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.82372314
Short name T473
Test name
Test status
Simulation time 1425129700 ps
CPU time 5.41 seconds
Started Jul 11 06:42:31 PM PDT 24
Finished Jul 11 06:42:38 PM PDT 24
Peak memory 200436 kb
Host smart-f1594af6-2086-428e-9944-e175a42166aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82372314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.82372314
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1274549156
Short name T185
Test name
Test status
Simulation time 148081192 ps
CPU time 1.15 seconds
Started Jul 11 06:42:32 PM PDT 24
Finished Jul 11 06:42:34 PM PDT 24
Peak memory 200192 kb
Host smart-c3f27bf6-be49-4dbe-8485-6598ead38b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274549156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1274549156
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4240651381
Short name T351
Test name
Test status
Simulation time 203481330 ps
CPU time 1.43 seconds
Started Jul 11 06:42:30 PM PDT 24
Finished Jul 11 06:42:33 PM PDT 24
Peak memory 200356 kb
Host smart-56ec38d7-2104-4723-9fb3-3246dc60fc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240651381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4240651381
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2615501278
Short name T317
Test name
Test status
Simulation time 8229021961 ps
CPU time 38.74 seconds
Started Jul 11 06:42:36 PM PDT 24
Finished Jul 11 06:43:15 PM PDT 24
Peak memory 208748 kb
Host smart-85cd3df1-34b8-4bb4-9247-84d36bc6d823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615501278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2615501278
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.4210129243
Short name T492
Test name
Test status
Simulation time 131034384 ps
CPU time 1.77 seconds
Started Jul 11 06:42:32 PM PDT 24
Finished Jul 11 06:42:35 PM PDT 24
Peak memory 200132 kb
Host smart-5a1e81ce-89bd-497f-a2aa-9d24d57b025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210129243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.4210129243
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1621035729
Short name T153
Test name
Test status
Simulation time 73287327 ps
CPU time 0.87 seconds
Started Jul 11 06:42:32 PM PDT 24
Finished Jul 11 06:42:34 PM PDT 24
Peak memory 200144 kb
Host smart-10a2777c-ffd2-4596-b82d-656c812c4028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621035729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1621035729
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2488603969
Short name T240
Test name
Test status
Simulation time 69276169 ps
CPU time 0.76 seconds
Started Jul 11 06:42:41 PM PDT 24
Finished Jul 11 06:42:43 PM PDT 24
Peak memory 200140 kb
Host smart-2ea16299-4c86-427b-91cf-74ef3a4d276c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488603969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2488603969
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1915120907
Short name T393
Test name
Test status
Simulation time 2376581840 ps
CPU time 8.56 seconds
Started Jul 11 06:42:39 PM PDT 24
Finished Jul 11 06:42:48 PM PDT 24
Peak memory 221780 kb
Host smart-2567415a-8293-4e62-8045-f6ba73b788dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915120907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1915120907
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2940001582
Short name T248
Test name
Test status
Simulation time 243651904 ps
CPU time 1.2 seconds
Started Jul 11 06:42:40 PM PDT 24
Finished Jul 11 06:42:42 PM PDT 24
Peak memory 217516 kb
Host smart-e8d173d3-8897-4e68-8209-a17fd4669635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940001582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2940001582
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.954961209
Short name T209
Test name
Test status
Simulation time 128654437 ps
CPU time 0.8 seconds
Started Jul 11 06:42:36 PM PDT 24
Finished Jul 11 06:42:38 PM PDT 24
Peak memory 199880 kb
Host smart-f3b20b9a-b765-4353-95af-ff3289bc87fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954961209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.954961209
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1526255007
Short name T514
Test name
Test status
Simulation time 876122251 ps
CPU time 4.49 seconds
Started Jul 11 06:42:38 PM PDT 24
Finished Jul 11 06:42:43 PM PDT 24
Peak memory 200404 kb
Host smart-d5b7df3d-4f52-40ff-b8d2-6c532e205704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526255007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1526255007
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3066808202
Short name T486
Test name
Test status
Simulation time 93826372 ps
CPU time 1.02 seconds
Started Jul 11 06:42:42 PM PDT 24
Finished Jul 11 06:42:44 PM PDT 24
Peak memory 200184 kb
Host smart-2d135b69-fbf8-4fca-9bae-98b5502030ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066808202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3066808202
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.867569740
Short name T145
Test name
Test status
Simulation time 117375037 ps
CPU time 1.19 seconds
Started Jul 11 06:42:35 PM PDT 24
Finished Jul 11 06:42:37 PM PDT 24
Peak memory 200360 kb
Host smart-447a74f7-d4a4-4774-8b8e-d47f7693aeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867569740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.867569740
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2148531364
Short name T214
Test name
Test status
Simulation time 2564797859 ps
CPU time 13.35 seconds
Started Jul 11 06:42:42 PM PDT 24
Finished Jul 11 06:42:57 PM PDT 24
Peak memory 208700 kb
Host smart-261bf3d7-51f6-48d0-9bd8-19b907fb3e5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148531364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2148531364
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2703629589
Short name T212
Test name
Test status
Simulation time 400332231 ps
CPU time 2.25 seconds
Started Jul 11 06:42:43 PM PDT 24
Finished Jul 11 06:42:46 PM PDT 24
Peak memory 200184 kb
Host smart-88cabfd1-1144-48d0-9c9b-2dd9f3bf1c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703629589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2703629589
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3754747926
Short name T358
Test name
Test status
Simulation time 138818626 ps
CPU time 1.12 seconds
Started Jul 11 06:42:35 PM PDT 24
Finished Jul 11 06:42:37 PM PDT 24
Peak memory 200176 kb
Host smart-50f939cf-462b-4ebb-807d-66ba5a6f5428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754747926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3754747926
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.740072366
Short name T290
Test name
Test status
Simulation time 80780074 ps
CPU time 0.8 seconds
Started Jul 11 06:42:44 PM PDT 24
Finished Jul 11 06:42:46 PM PDT 24
Peak memory 199976 kb
Host smart-d2dfb029-c080-46ac-80c6-c1bcdb7c742d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740072366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.740072366
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.733009418
Short name T25
Test name
Test status
Simulation time 1226161357 ps
CPU time 5.82 seconds
Started Jul 11 06:42:41 PM PDT 24
Finished Jul 11 06:42:48 PM PDT 24
Peak memory 221808 kb
Host smart-39aeb5b8-8b1d-416f-abaf-83f05bb0be90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733009418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.733009418
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1063077793
Short name T530
Test name
Test status
Simulation time 243827897 ps
CPU time 1.28 seconds
Started Jul 11 06:42:48 PM PDT 24
Finished Jul 11 06:42:50 PM PDT 24
Peak memory 217552 kb
Host smart-5b460a9c-2ae3-4d77-ac5a-d253eb434365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063077793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1063077793
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3247335910
Short name T430
Test name
Test status
Simulation time 144568165 ps
CPU time 0.87 seconds
Started Jul 11 06:42:42 PM PDT 24
Finished Jul 11 06:42:44 PM PDT 24
Peak memory 200068 kb
Host smart-d80a0ea5-8fc4-4bd6-bd96-4f89842ccbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247335910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3247335910
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3823704791
Short name T397
Test name
Test status
Simulation time 743907610 ps
CPU time 4.03 seconds
Started Jul 11 06:42:43 PM PDT 24
Finished Jul 11 06:42:48 PM PDT 24
Peak memory 200604 kb
Host smart-e6bec08d-230f-43cd-926c-fff3428b1197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823704791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3823704791
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.469064655
Short name T4
Test name
Test status
Simulation time 97865546 ps
CPU time 0.98 seconds
Started Jul 11 06:42:42 PM PDT 24
Finished Jul 11 06:42:44 PM PDT 24
Peak memory 200260 kb
Host smart-f4ba9593-c50d-4f2e-b688-e57b9bf25ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469064655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.469064655
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3380025780
Short name T169
Test name
Test status
Simulation time 251696386 ps
CPU time 1.53 seconds
Started Jul 11 06:42:41 PM PDT 24
Finished Jul 11 06:42:43 PM PDT 24
Peak memory 200304 kb
Host smart-35f94e17-74e1-4ab9-aed5-0f5653029185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380025780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3380025780
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3466461529
Short name T141
Test name
Test status
Simulation time 152581016 ps
CPU time 1.07 seconds
Started Jul 11 06:42:45 PM PDT 24
Finished Jul 11 06:42:48 PM PDT 24
Peak memory 200156 kb
Host smart-265b0ddd-6952-4436-b03a-4d31b36e4854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466461529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3466461529
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3271486458
Short name T498
Test name
Test status
Simulation time 359291333 ps
CPU time 2.32 seconds
Started Jul 11 06:42:41 PM PDT 24
Finished Jul 11 06:42:45 PM PDT 24
Peak memory 200120 kb
Host smart-94d64677-3508-4539-a03a-b8f2e689fc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271486458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3271486458
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.512605278
Short name T288
Test name
Test status
Simulation time 82956227 ps
CPU time 0.82 seconds
Started Jul 11 06:42:42 PM PDT 24
Finished Jul 11 06:42:44 PM PDT 24
Peak memory 200132 kb
Host smart-e933f687-40de-400f-aaf6-de0be8f16aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512605278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.512605278
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1040558908
Short name T438
Test name
Test status
Simulation time 69997100 ps
CPU time 0.76 seconds
Started Jul 11 06:42:46 PM PDT 24
Finished Jul 11 06:42:48 PM PDT 24
Peak memory 199948 kb
Host smart-f70f57a8-d156-4bf3-9cc5-606590a65b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040558908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1040558908
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1066734106
Short name T55
Test name
Test status
Simulation time 2360008832 ps
CPU time 8.19 seconds
Started Jul 11 06:42:46 PM PDT 24
Finished Jul 11 06:42:55 PM PDT 24
Peak memory 217728 kb
Host smart-16286880-deac-493b-a329-e0c42376467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066734106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1066734106
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.418665024
Short name T256
Test name
Test status
Simulation time 247369715 ps
CPU time 1.03 seconds
Started Jul 11 06:42:45 PM PDT 24
Finished Jul 11 06:42:47 PM PDT 24
Peak memory 217556 kb
Host smart-e57deac1-2930-4c61-a577-a16f80874b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418665024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.418665024
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_reset.119002719
Short name T380
Test name
Test status
Simulation time 1420838318 ps
CPU time 5.86 seconds
Started Jul 11 06:42:45 PM PDT 24
Finished Jul 11 06:42:53 PM PDT 24
Peak memory 200444 kb
Host smart-7359db4c-53b2-4490-a10b-39fc2f7e68a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119002719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.119002719
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3285891739
Short name T6
Test name
Test status
Simulation time 144195474 ps
CPU time 1.13 seconds
Started Jul 11 06:42:45 PM PDT 24
Finished Jul 11 06:42:47 PM PDT 24
Peak memory 200160 kb
Host smart-0ff5243d-cfb5-4f26-88a5-f5a114e8d36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285891739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3285891739
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3867820468
Short name T436
Test name
Test status
Simulation time 123576052 ps
CPU time 1.25 seconds
Started Jul 11 06:42:46 PM PDT 24
Finished Jul 11 06:42:48 PM PDT 24
Peak memory 200376 kb
Host smart-5ad63e2e-303f-4c29-9225-87c4132c77c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867820468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3867820468
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3204511199
Short name T493
Test name
Test status
Simulation time 3151888726 ps
CPU time 12.97 seconds
Started Jul 11 06:42:44 PM PDT 24
Finished Jul 11 06:42:58 PM PDT 24
Peak memory 200448 kb
Host smart-c998d1e2-7f1a-4bd4-8925-af5d4589ad16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204511199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3204511199
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2967355551
Short name T199
Test name
Test status
Simulation time 344374005 ps
CPU time 2.26 seconds
Started Jul 11 06:42:48 PM PDT 24
Finished Jul 11 06:42:51 PM PDT 24
Peak memory 200164 kb
Host smart-fe9e3b3c-5e10-4284-9dc3-8b1546fe5918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967355551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2967355551
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3982148450
Short name T328
Test name
Test status
Simulation time 143405906 ps
CPU time 1.15 seconds
Started Jul 11 06:43:05 PM PDT 24
Finished Jul 11 06:43:08 PM PDT 24
Peak memory 200200 kb
Host smart-7eb141d1-8d42-4f9a-adb5-faf0f5954af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982148450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3982148450
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.478568858
Short name T22
Test name
Test status
Simulation time 1233380209 ps
CPU time 5.52 seconds
Started Jul 11 06:42:51 PM PDT 24
Finished Jul 11 06:42:58 PM PDT 24
Peak memory 217976 kb
Host smart-20fd54c4-28ec-4e96-851f-29d556781124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478568858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.478568858
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2916295530
Short name T280
Test name
Test status
Simulation time 243363603 ps
CPU time 1.18 seconds
Started Jul 11 06:42:51 PM PDT 24
Finished Jul 11 06:42:53 PM PDT 24
Peak memory 217540 kb
Host smart-8d443cda-1525-4558-bb8f-fdc4b4cf37da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916295530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2916295530
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1070088793
Short name T74
Test name
Test status
Simulation time 102664825 ps
CPU time 0.79 seconds
Started Jul 11 06:42:46 PM PDT 24
Finished Jul 11 06:42:48 PM PDT 24
Peak memory 199992 kb
Host smart-dcab0774-c6a6-4fb4-9753-fa2a9e6f02ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070088793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1070088793
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3992629106
Short name T540
Test name
Test status
Simulation time 1457046605 ps
CPU time 5.96 seconds
Started Jul 11 06:42:47 PM PDT 24
Finished Jul 11 06:42:54 PM PDT 24
Peak memory 200380 kb
Host smart-e555427e-34ea-4f98-8709-763a6d65fc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992629106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3992629106
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1348387755
Short name T296
Test name
Test status
Simulation time 109441317 ps
CPU time 1.03 seconds
Started Jul 11 06:42:50 PM PDT 24
Finished Jul 11 06:42:52 PM PDT 24
Peak memory 200180 kb
Host smart-8405bf7d-9971-4b21-b96b-d150899dd212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348387755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1348387755
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1293816041
Short name T221
Test name
Test status
Simulation time 192996414 ps
CPU time 1.33 seconds
Started Jul 11 06:42:47 PM PDT 24
Finished Jul 11 06:42:50 PM PDT 24
Peak memory 200360 kb
Host smart-f698a6ed-cbb3-4ac9-bac1-e0d70b30892d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293816041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1293816041
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2804673935
Short name T329
Test name
Test status
Simulation time 4639693543 ps
CPU time 21.32 seconds
Started Jul 11 06:42:50 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 208624 kb
Host smart-760c6a26-ac4d-475d-a917-add4c0a8cb99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804673935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2804673935
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.715388356
Short name T154
Test name
Test status
Simulation time 330954848 ps
CPU time 2.37 seconds
Started Jul 11 06:42:52 PM PDT 24
Finished Jul 11 06:42:55 PM PDT 24
Peak memory 208448 kb
Host smart-4ebf1545-44be-4867-b913-c935a3a00651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715388356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.715388356
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.4159779175
Short name T482
Test name
Test status
Simulation time 176106996 ps
CPU time 1.18 seconds
Started Jul 11 06:42:45 PM PDT 24
Finished Jul 11 06:42:48 PM PDT 24
Peak memory 200196 kb
Host smart-3d8e7f22-80a1-4c39-aab2-7fe4817206dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159779175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.4159779175
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3791154725
Short name T501
Test name
Test status
Simulation time 73108975 ps
CPU time 0.79 seconds
Started Jul 11 06:47:55 PM PDT 24
Finished Jul 11 06:47:57 PM PDT 24
Peak memory 200020 kb
Host smart-ccb47d5a-df72-4781-b937-398b50bdca00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791154725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3791154725
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1026110744
Short name T522
Test name
Test status
Simulation time 2375173437 ps
CPU time 9.98 seconds
Started Jul 11 06:42:49 PM PDT 24
Finished Jul 11 06:43:00 PM PDT 24
Peak memory 221772 kb
Host smart-af145e1f-95cb-48fe-b6dd-996a25c52d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026110744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1026110744
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3685989305
Short name T299
Test name
Test status
Simulation time 244080999 ps
CPU time 1.11 seconds
Started Jul 11 06:42:49 PM PDT 24
Finished Jul 11 06:42:52 PM PDT 24
Peak memory 217556 kb
Host smart-09398f1a-66fc-4c4d-a2c7-0d9bc66a8f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685989305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3685989305
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.175022373
Short name T420
Test name
Test status
Simulation time 176278760 ps
CPU time 0.86 seconds
Started Jul 11 06:42:49 PM PDT 24
Finished Jul 11 06:42:51 PM PDT 24
Peak memory 199980 kb
Host smart-801ce4d6-1b61-4403-bea9-55bd7ea47122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175022373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.175022373
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2749839553
Short name T269
Test name
Test status
Simulation time 1016085108 ps
CPU time 4.79 seconds
Started Jul 11 06:42:51 PM PDT 24
Finished Jul 11 06:42:57 PM PDT 24
Peak memory 200340 kb
Host smart-beac987f-5fdf-4b69-8a7d-8863bd77f167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749839553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2749839553
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3927108543
Short name T319
Test name
Test status
Simulation time 154958171 ps
CPU time 1.17 seconds
Started Jul 11 06:42:49 PM PDT 24
Finished Jul 11 06:42:52 PM PDT 24
Peak memory 200172 kb
Host smart-81e6895e-f687-4dbb-98db-18813d38fa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927108543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3927108543
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.667665211
Short name T159
Test name
Test status
Simulation time 234119436 ps
CPU time 1.63 seconds
Started Jul 11 06:42:54 PM PDT 24
Finished Jul 11 06:42:57 PM PDT 24
Peak memory 200348 kb
Host smart-3635e592-be85-4012-99e8-305c5ff99af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667665211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.667665211
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1702776908
Short name T337
Test name
Test status
Simulation time 2303042704 ps
CPU time 10.77 seconds
Started Jul 11 06:42:51 PM PDT 24
Finished Jul 11 06:43:03 PM PDT 24
Peak memory 200492 kb
Host smart-a3882c31-632f-4b59-afa0-3708c1bc5455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702776908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1702776908
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.46107534
Short name T193
Test name
Test status
Simulation time 145703245 ps
CPU time 1.8 seconds
Started Jul 11 06:42:50 PM PDT 24
Finished Jul 11 06:42:53 PM PDT 24
Peak memory 208584 kb
Host smart-fbb49cbf-e326-47bf-8914-521e87367948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46107534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.46107534
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3045824554
Short name T273
Test name
Test status
Simulation time 230398823 ps
CPU time 1.39 seconds
Started Jul 11 06:42:54 PM PDT 24
Finished Jul 11 06:42:56 PM PDT 24
Peak memory 200164 kb
Host smart-3b7dd2af-a43d-4d42-9b1b-0c9b3bc8c0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045824554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3045824554
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1006354015
Short name T300
Test name
Test status
Simulation time 70691032 ps
CPU time 0.88 seconds
Started Jul 11 06:42:02 PM PDT 24
Finished Jul 11 06:42:03 PM PDT 24
Peak memory 199964 kb
Host smart-70e49ed5-d4a6-4968-8dd5-785751bd67a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006354015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1006354015
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2851588255
Short name T8
Test name
Test status
Simulation time 1224381340 ps
CPU time 5.59 seconds
Started Jul 11 06:41:57 PM PDT 24
Finished Jul 11 06:42:03 PM PDT 24
Peak memory 216888 kb
Host smart-a6f1a650-7ed9-4588-828f-5363eedbfcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851588255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2851588255
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.643075795
Short name T483
Test name
Test status
Simulation time 244203941 ps
CPU time 1.14 seconds
Started Jul 11 06:41:54 PM PDT 24
Finished Jul 11 06:41:56 PM PDT 24
Peak memory 217444 kb
Host smart-954d7575-0db2-4d68-8a46-e424c1634eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643075795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.643075795
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1448465305
Short name T283
Test name
Test status
Simulation time 107828658 ps
CPU time 0.75 seconds
Started Jul 11 06:41:54 PM PDT 24
Finished Jul 11 06:41:56 PM PDT 24
Peak memory 199984 kb
Host smart-5b6727bf-9915-4d50-83e8-f603bba3c06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448465305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1448465305
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1920954625
Short name T450
Test name
Test status
Simulation time 859534791 ps
CPU time 4.64 seconds
Started Jul 11 06:41:52 PM PDT 24
Finished Jul 11 06:41:57 PM PDT 24
Peak memory 200412 kb
Host smart-9c7b6c15-47a2-4466-880a-f35a10d3281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920954625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1920954625
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.390771604
Short name T72
Test name
Test status
Simulation time 20658363129 ps
CPU time 35.23 seconds
Started Jul 11 06:41:56 PM PDT 24
Finished Jul 11 06:42:32 PM PDT 24
Peak memory 218548 kb
Host smart-74464cf7-5dd9-4d36-9a49-2259d1ecf8c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390771604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.390771604
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2107382175
Short name T422
Test name
Test status
Simulation time 142073170 ps
CPU time 1.12 seconds
Started Jul 11 06:41:56 PM PDT 24
Finished Jul 11 06:41:58 PM PDT 24
Peak memory 200160 kb
Host smart-c7c45bf3-a851-4ea6-abe8-cdc4ef8389b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107382175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2107382175
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.4013675806
Short name T461
Test name
Test status
Simulation time 126489734 ps
CPU time 1.25 seconds
Started Jul 11 06:41:51 PM PDT 24
Finished Jul 11 06:41:53 PM PDT 24
Peak memory 200360 kb
Host smart-04da6c61-a703-4c7d-8a4f-76e8573fd205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013675806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.4013675806
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.830417697
Short name T255
Test name
Test status
Simulation time 8457313190 ps
CPU time 29.94 seconds
Started Jul 11 06:41:56 PM PDT 24
Finished Jul 11 06:42:27 PM PDT 24
Peak memory 208684 kb
Host smart-6d6ed183-7638-47f7-a9ed-56a9cf62a56a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830417697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.830417697
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3534269136
Short name T341
Test name
Test status
Simulation time 359324406 ps
CPU time 2.36 seconds
Started Jul 11 06:41:56 PM PDT 24
Finished Jul 11 06:41:59 PM PDT 24
Peak memory 208376 kb
Host smart-6fe99b05-55ea-49f1-b779-1f2155de3eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534269136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3534269136
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1496329011
Short name T152
Test name
Test status
Simulation time 214493666 ps
CPU time 1.34 seconds
Started Jul 11 06:41:51 PM PDT 24
Finished Jul 11 06:41:53 PM PDT 24
Peak memory 200156 kb
Host smart-7fd0f692-b32e-4a98-97e7-0d5545cc3fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496329011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1496329011
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.358265035
Short name T459
Test name
Test status
Simulation time 64938008 ps
CPU time 0.76 seconds
Started Jul 11 06:42:56 PM PDT 24
Finished Jul 11 06:42:59 PM PDT 24
Peak memory 199964 kb
Host smart-bd0caa44-d4ea-4ae3-b0da-ace77aa39f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358265035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.358265035
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2121503686
Short name T414
Test name
Test status
Simulation time 1872081049 ps
CPU time 7.35 seconds
Started Jul 11 06:42:56 PM PDT 24
Finished Jul 11 06:43:05 PM PDT 24
Peak memory 217768 kb
Host smart-70b0ca9f-bc5a-4867-bfb9-e63c827f1bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121503686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2121503686
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.841148848
Short name T47
Test name
Test status
Simulation time 245235284 ps
CPU time 1.01 seconds
Started Jul 11 06:42:55 PM PDT 24
Finished Jul 11 06:42:58 PM PDT 24
Peak memory 217564 kb
Host smart-72b61861-feb7-4883-a8c0-eceeb579f61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841148848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.841148848
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1243386560
Short name T75
Test name
Test status
Simulation time 223864991 ps
CPU time 0.89 seconds
Started Jul 11 06:42:54 PM PDT 24
Finished Jul 11 06:42:56 PM PDT 24
Peak memory 199972 kb
Host smart-d5516460-ce19-4fd6-ba48-153094525e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243386560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1243386560
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2290457450
Short name T302
Test name
Test status
Simulation time 1875137651 ps
CPU time 7.32 seconds
Started Jul 11 06:49:30 PM PDT 24
Finished Jul 11 06:49:38 PM PDT 24
Peak memory 200388 kb
Host smart-69099850-c6bb-4c76-8420-4c60ad692e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290457450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2290457450
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1259592973
Short name T81
Test name
Test status
Simulation time 104998467 ps
CPU time 1.04 seconds
Started Jul 11 06:42:55 PM PDT 24
Finished Jul 11 06:42:58 PM PDT 24
Peak memory 200192 kb
Host smart-9877216f-0758-4bf3-9e45-32272e900f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259592973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1259592973
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3916405329
Short name T163
Test name
Test status
Simulation time 208065737 ps
CPU time 1.36 seconds
Started Jul 11 06:42:49 PM PDT 24
Finished Jul 11 06:42:52 PM PDT 24
Peak memory 200376 kb
Host smart-e7a37bb1-4a87-43ca-899f-d5571325d269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916405329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3916405329
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.656010641
Short name T402
Test name
Test status
Simulation time 16306778251 ps
CPU time 53.39 seconds
Started Jul 11 06:42:55 PM PDT 24
Finished Jul 11 06:43:50 PM PDT 24
Peak memory 208884 kb
Host smart-14c8d0c5-a31b-4b1c-b6e7-4bd18500cc35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656010641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.656010641
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3646989630
Short name T325
Test name
Test status
Simulation time 317818710 ps
CPU time 2.03 seconds
Started Jul 11 06:42:56 PM PDT 24
Finished Jul 11 06:42:59 PM PDT 24
Peak memory 208408 kb
Host smart-c102f62b-a022-4e16-8c90-01b6d37ac027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646989630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3646989630
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3264206607
Short name T456
Test name
Test status
Simulation time 125999984 ps
CPU time 1 seconds
Started Jul 11 06:42:50 PM PDT 24
Finished Jul 11 06:42:53 PM PDT 24
Peak memory 200192 kb
Host smart-aaeff015-c534-46d6-b9c2-30c3d0372825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264206607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3264206607
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1613212559
Short name T274
Test name
Test status
Simulation time 78234106 ps
CPU time 0.81 seconds
Started Jul 11 06:43:02 PM PDT 24
Finished Jul 11 06:43:05 PM PDT 24
Peak memory 200188 kb
Host smart-e25e874f-5e38-4a92-981f-2ea148bbd85e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613212559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1613212559
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1120547945
Short name T452
Test name
Test status
Simulation time 1222417162 ps
CPU time 5.48 seconds
Started Jul 11 06:42:55 PM PDT 24
Finished Jul 11 06:43:02 PM PDT 24
Peak memory 221764 kb
Host smart-3762c062-212b-4be0-a8be-429a439da20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120547945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1120547945
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1203835730
Short name T513
Test name
Test status
Simulation time 243580237 ps
CPU time 1.17 seconds
Started Jul 11 06:42:55 PM PDT 24
Finished Jul 11 06:42:57 PM PDT 24
Peak memory 217516 kb
Host smart-fd70b813-a311-49dd-8ffd-34903e53322c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203835730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1203835730
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.63629976
Short name T347
Test name
Test status
Simulation time 155583044 ps
CPU time 0.81 seconds
Started Jul 11 06:42:56 PM PDT 24
Finished Jul 11 06:42:58 PM PDT 24
Peak memory 199996 kb
Host smart-4ef98652-9cb1-45e0-9c4c-5509dd68e77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63629976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.63629976
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3284825090
Short name T369
Test name
Test status
Simulation time 1719879055 ps
CPU time 6.91 seconds
Started Jul 11 06:42:55 PM PDT 24
Finished Jul 11 06:43:03 PM PDT 24
Peak memory 200424 kb
Host smart-08e24ca0-187a-4605-be71-01b044b35e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284825090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3284825090
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3529343047
Short name T403
Test name
Test status
Simulation time 186201315 ps
CPU time 1.26 seconds
Started Jul 11 06:42:54 PM PDT 24
Finished Jul 11 06:42:57 PM PDT 24
Peak memory 200136 kb
Host smart-523cf179-a1cc-4ef3-b97b-46b726af3bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529343047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3529343047
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1452930360
Short name T516
Test name
Test status
Simulation time 254274632 ps
CPU time 1.58 seconds
Started Jul 11 06:42:54 PM PDT 24
Finished Jul 11 06:42:56 PM PDT 24
Peak memory 200340 kb
Host smart-897176c0-88ff-4b74-b5e7-9964fee9a6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452930360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1452930360
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1636949790
Short name T433
Test name
Test status
Simulation time 2992389050 ps
CPU time 16.7 seconds
Started Jul 11 06:42:55 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 200540 kb
Host smart-f7113da4-9c1f-4640-bf99-8eb7aaedd8fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636949790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1636949790
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.556332061
Short name T200
Test name
Test status
Simulation time 151986088 ps
CPU time 1.84 seconds
Started Jul 11 06:42:54 PM PDT 24
Finished Jul 11 06:42:56 PM PDT 24
Peak memory 200156 kb
Host smart-7a167f8a-0c19-426a-8e77-a04f8d22c484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556332061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.556332061
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.120835121
Short name T460
Test name
Test status
Simulation time 194955975 ps
CPU time 1.29 seconds
Started Jul 11 06:42:54 PM PDT 24
Finished Jul 11 06:42:57 PM PDT 24
Peak memory 200192 kb
Host smart-9d545243-6b23-4294-aec5-148eb883934a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120835121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.120835121
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1578684720
Short name T431
Test name
Test status
Simulation time 89413115 ps
CPU time 0.82 seconds
Started Jul 11 06:42:58 PM PDT 24
Finished Jul 11 06:43:00 PM PDT 24
Peak memory 199948 kb
Host smart-445cc103-b048-4b30-9d4e-7d09b3517e61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578684720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1578684720
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2970716105
Short name T472
Test name
Test status
Simulation time 1227503114 ps
CPU time 5.89 seconds
Started Jul 11 06:43:00 PM PDT 24
Finished Jul 11 06:43:07 PM PDT 24
Peak memory 221780 kb
Host smart-60fe08be-a46f-4c46-b841-797dbd6d7cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970716105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2970716105
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1695025191
Short name T210
Test name
Test status
Simulation time 243866903 ps
CPU time 1.17 seconds
Started Jul 11 06:42:58 PM PDT 24
Finished Jul 11 06:43:00 PM PDT 24
Peak memory 217532 kb
Host smart-2519d748-5998-45a5-a962-1de237eafddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695025191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1695025191
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.669523600
Short name T184
Test name
Test status
Simulation time 169666758 ps
CPU time 0.86 seconds
Started Jul 11 06:43:02 PM PDT 24
Finished Jul 11 06:43:05 PM PDT 24
Peak memory 200184 kb
Host smart-9c533527-9cf6-4cce-bbff-a529875dffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669523600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.669523600
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.457931736
Short name T103
Test name
Test status
Simulation time 1923414777 ps
CPU time 7.42 seconds
Started Jul 11 06:44:14 PM PDT 24
Finished Jul 11 06:44:23 PM PDT 24
Peak memory 200424 kb
Host smart-48d02d42-ec3f-462f-b4ed-de0d4e556802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457931736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.457931736
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3290704961
Short name T382
Test name
Test status
Simulation time 115153385 ps
CPU time 1.08 seconds
Started Jul 11 06:43:03 PM PDT 24
Finished Jul 11 06:43:06 PM PDT 24
Peak memory 200140 kb
Host smart-804257a8-ae77-454c-97bb-24e16104b8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290704961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3290704961
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1572325147
Short name T164
Test name
Test status
Simulation time 191356399 ps
CPU time 1.47 seconds
Started Jul 11 06:42:58 PM PDT 24
Finished Jul 11 06:43:01 PM PDT 24
Peak memory 200324 kb
Host smart-4d695aac-69ff-484c-8bae-73fb514b2eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572325147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1572325147
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.908712104
Short name T524
Test name
Test status
Simulation time 4159353145 ps
CPU time 18.65 seconds
Started Jul 11 06:43:01 PM PDT 24
Finished Jul 11 06:43:21 PM PDT 24
Peak memory 200424 kb
Host smart-c93e53a9-3214-4167-8a64-df7414e5eeb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908712104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.908712104
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.224876307
Short name T415
Test name
Test status
Simulation time 122207091 ps
CPU time 1.49 seconds
Started Jul 11 06:42:59 PM PDT 24
Finished Jul 11 06:43:02 PM PDT 24
Peak memory 200140 kb
Host smart-9dc9a696-653e-4aa7-800f-e24967b9220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224876307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.224876307
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2089024504
Short name T183
Test name
Test status
Simulation time 139160931 ps
CPU time 1.09 seconds
Started Jul 11 06:43:00 PM PDT 24
Finished Jul 11 06:43:02 PM PDT 24
Peak memory 200120 kb
Host smart-1bd72163-e777-46e3-a68d-3648e7fdb9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089024504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2089024504
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3337082662
Short name T23
Test name
Test status
Simulation time 77653169 ps
CPU time 0.79 seconds
Started Jul 11 06:43:06 PM PDT 24
Finished Jul 11 06:43:09 PM PDT 24
Peak memory 199964 kb
Host smart-ad811065-51cf-43ef-88d7-dd57b716385a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337082662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3337082662
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2573889844
Short name T30
Test name
Test status
Simulation time 1220489578 ps
CPU time 5.56 seconds
Started Jul 11 06:43:03 PM PDT 24
Finished Jul 11 06:43:10 PM PDT 24
Peak memory 217816 kb
Host smart-184c5e64-f3b5-41a6-92d9-af85a2c787ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573889844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2573889844
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.569140576
Short name T182
Test name
Test status
Simulation time 244033822 ps
CPU time 1.13 seconds
Started Jul 11 06:43:05 PM PDT 24
Finished Jul 11 06:43:08 PM PDT 24
Peak memory 217532 kb
Host smart-5d49912d-61b7-421a-bd65-50170afa3d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569140576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.569140576
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1289492304
Short name T462
Test name
Test status
Simulation time 161658441 ps
CPU time 0.88 seconds
Started Jul 11 06:42:57 PM PDT 24
Finished Jul 11 06:42:59 PM PDT 24
Peak memory 199984 kb
Host smart-5a6358f8-3966-4eb7-aa61-446266a19b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289492304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1289492304
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3346073074
Short name T247
Test name
Test status
Simulation time 1328499546 ps
CPU time 5.22 seconds
Started Jul 11 06:43:01 PM PDT 24
Finished Jul 11 06:43:08 PM PDT 24
Peak memory 200436 kb
Host smart-93c116e2-591b-4e7b-961e-c49a33143811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346073074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3346073074
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.933443997
Short name T174
Test name
Test status
Simulation time 100367411 ps
CPU time 1.11 seconds
Started Jul 11 06:43:06 PM PDT 24
Finished Jul 11 06:43:09 PM PDT 24
Peak memory 200092 kb
Host smart-8b44d7d6-3651-4f0b-ba8f-bbf0d35c7497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933443997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.933443997
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2985739766
Short name T257
Test name
Test status
Simulation time 262204083 ps
CPU time 1.65 seconds
Started Jul 11 06:42:59 PM PDT 24
Finished Jul 11 06:43:01 PM PDT 24
Peak memory 200320 kb
Host smart-87a64243-fa19-4f07-80c3-a4dd9cb55374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985739766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2985739766
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.943674669
Short name T334
Test name
Test status
Simulation time 1040957688 ps
CPU time 6.04 seconds
Started Jul 11 06:43:05 PM PDT 24
Finished Jul 11 06:43:14 PM PDT 24
Peak memory 216776 kb
Host smart-7d2034bf-5471-42a0-97f5-9e82fb12431e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943674669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.943674669
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1240533639
Short name T292
Test name
Test status
Simulation time 300492553 ps
CPU time 2.04 seconds
Started Jul 11 06:43:01 PM PDT 24
Finished Jul 11 06:43:05 PM PDT 24
Peak memory 208360 kb
Host smart-a435a60d-597d-4f44-859b-13fa8172a69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240533639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1240533639
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1778965866
Short name T276
Test name
Test status
Simulation time 120612335 ps
CPU time 1.05 seconds
Started Jul 11 06:43:00 PM PDT 24
Finished Jul 11 06:43:02 PM PDT 24
Peak memory 200120 kb
Host smart-21294f08-3bf1-4255-879e-68742f696bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778965866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1778965866
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3876384424
Short name T173
Test name
Test status
Simulation time 76146895 ps
CPU time 0.79 seconds
Started Jul 11 06:43:04 PM PDT 24
Finished Jul 11 06:43:08 PM PDT 24
Peak memory 199980 kb
Host smart-39fdb18f-a980-4322-ad36-44e4bdee7527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876384424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3876384424
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3715656736
Short name T449
Test name
Test status
Simulation time 1883416845 ps
CPU time 7.56 seconds
Started Jul 11 06:43:06 PM PDT 24
Finished Jul 11 06:43:16 PM PDT 24
Peak memory 216876 kb
Host smart-8a8cbf5e-9f5f-47dd-887d-ba1d6e146375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715656736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3715656736
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4076556046
Short name T464
Test name
Test status
Simulation time 245207621 ps
CPU time 1.06 seconds
Started Jul 11 06:43:05 PM PDT 24
Finished Jul 11 06:43:08 PM PDT 24
Peak memory 217452 kb
Host smart-f458954b-b07a-46bf-825e-b5759fa887bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076556046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4076556046
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1139987812
Short name T175
Test name
Test status
Simulation time 165874242 ps
CPU time 0.86 seconds
Started Jul 11 06:43:05 PM PDT 24
Finished Jul 11 06:43:08 PM PDT 24
Peak memory 199988 kb
Host smart-8696ae67-f910-4ff7-a85e-b993a77b8902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139987812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1139987812
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.4185417594
Short name T365
Test name
Test status
Simulation time 2213922565 ps
CPU time 8.37 seconds
Started Jul 11 06:43:05 PM PDT 24
Finished Jul 11 06:43:16 PM PDT 24
Peak memory 200540 kb
Host smart-8630e8a1-0587-40a1-b8c8-dfe7fb5f5ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185417594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.4185417594
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3228010326
Short name T160
Test name
Test status
Simulation time 106657001 ps
CPU time 1.01 seconds
Started Jul 11 06:43:06 PM PDT 24
Finished Jul 11 06:43:10 PM PDT 24
Peak memory 200168 kb
Host smart-5e381b3f-67ee-4447-abc4-bc429e142acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228010326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3228010326
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3850090042
Short name T496
Test name
Test status
Simulation time 112322395 ps
CPU time 1.19 seconds
Started Jul 11 06:43:05 PM PDT 24
Finished Jul 11 06:43:08 PM PDT 24
Peak memory 200348 kb
Host smart-f66a8cab-fa65-49fd-8b16-ad10a88bd59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850090042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3850090042
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1502491837
Short name T33
Test name
Test status
Simulation time 1589882077 ps
CPU time 7.94 seconds
Started Jul 11 06:43:05 PM PDT 24
Finished Jul 11 06:43:15 PM PDT 24
Peak memory 208668 kb
Host smart-37b73d78-95b0-45f3-8608-6cd6e5a08366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502491837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1502491837
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.4163272710
Short name T197
Test name
Test status
Simulation time 394369024 ps
CPU time 2.28 seconds
Started Jul 11 06:43:03 PM PDT 24
Finished Jul 11 06:43:07 PM PDT 24
Peak memory 200148 kb
Host smart-4a57e0e1-0788-433a-9003-80e4096e2352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163272710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4163272710
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.644486446
Short name T506
Test name
Test status
Simulation time 192075829 ps
CPU time 1.2 seconds
Started Jul 11 06:43:07 PM PDT 24
Finished Jul 11 06:43:10 PM PDT 24
Peak memory 200176 kb
Host smart-d8d7893d-a228-4486-b4fb-04ccc23c161f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644486446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.644486446
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.704929939
Short name T201
Test name
Test status
Simulation time 76531255 ps
CPU time 0.79 seconds
Started Jul 11 06:43:05 PM PDT 24
Finished Jul 11 06:43:08 PM PDT 24
Peak memory 200016 kb
Host smart-0585c728-0445-4db8-96ea-0a377b99085c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704929939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.704929939
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3156616597
Short name T196
Test name
Test status
Simulation time 2352345342 ps
CPU time 9.04 seconds
Started Jul 11 06:43:05 PM PDT 24
Finished Jul 11 06:43:16 PM PDT 24
Peak memory 221756 kb
Host smart-e84101d9-4b1d-4b10-ba92-cf82b7927da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156616597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3156616597
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.520587779
Short name T206
Test name
Test status
Simulation time 244070711 ps
CPU time 1.19 seconds
Started Jul 11 06:43:06 PM PDT 24
Finished Jul 11 06:43:10 PM PDT 24
Peak memory 217548 kb
Host smart-47a4a900-8854-4866-b395-0545173bee0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520587779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.520587779
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1847883720
Short name T15
Test name
Test status
Simulation time 83523544 ps
CPU time 0.73 seconds
Started Jul 11 06:43:07 PM PDT 24
Finished Jul 11 06:43:10 PM PDT 24
Peak memory 199988 kb
Host smart-a9ddeaa7-eea4-418d-803d-b48254a83bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847883720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1847883720
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.879238570
Short name T340
Test name
Test status
Simulation time 1115960483 ps
CPU time 5.05 seconds
Started Jul 11 06:43:06 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 200428 kb
Host smart-57f486ef-eb03-4431-8cbd-ae074af81937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879238570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.879238570
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3948534820
Short name T360
Test name
Test status
Simulation time 102622436 ps
CPU time 1.03 seconds
Started Jul 11 06:43:04 PM PDT 24
Finished Jul 11 06:43:06 PM PDT 24
Peak memory 200188 kb
Host smart-70385a90-ca4f-4e9e-9994-45b283c9b10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948534820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3948534820
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.4120647624
Short name T77
Test name
Test status
Simulation time 191607150 ps
CPU time 1.4 seconds
Started Jul 11 06:43:03 PM PDT 24
Finished Jul 11 06:43:06 PM PDT 24
Peak memory 200344 kb
Host smart-f9d40e76-9fa3-4488-8c00-14d45afd30d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120647624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4120647624
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.781949977
Short name T348
Test name
Test status
Simulation time 8134772158 ps
CPU time 36.36 seconds
Started Jul 11 06:43:04 PM PDT 24
Finished Jul 11 06:43:42 PM PDT 24
Peak memory 210568 kb
Host smart-27c57f84-1d90-475b-b156-562c2ae99038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781949977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.781949977
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2242506217
Short name T272
Test name
Test status
Simulation time 157620952 ps
CPU time 1.96 seconds
Started Jul 11 06:43:04 PM PDT 24
Finished Jul 11 06:43:09 PM PDT 24
Peak memory 200100 kb
Host smart-6fa0d01a-a09b-4888-8e8c-4cf04fe4f95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242506217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2242506217
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3067527106
Short name T527
Test name
Test status
Simulation time 79537064 ps
CPU time 0.83 seconds
Started Jul 11 06:43:05 PM PDT 24
Finished Jul 11 06:43:08 PM PDT 24
Peak memory 200180 kb
Host smart-505e13f6-ac85-4375-8565-a7fcf330780e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067527106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3067527106
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1780761953
Short name T315
Test name
Test status
Simulation time 74945022 ps
CPU time 0.76 seconds
Started Jul 11 06:43:10 PM PDT 24
Finished Jul 11 06:43:12 PM PDT 24
Peak memory 199924 kb
Host smart-8c1b09e2-d6a0-482a-b5be-4d76a4a3f4a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780761953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1780761953
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.317656392
Short name T42
Test name
Test status
Simulation time 1232549862 ps
CPU time 5.63 seconds
Started Jul 11 06:43:11 PM PDT 24
Finished Jul 11 06:43:18 PM PDT 24
Peak memory 221584 kb
Host smart-f2cdcde8-85bb-4fdf-bbd4-0c1e90df7e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317656392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.317656392
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3973788900
Short name T85
Test name
Test status
Simulation time 244861080 ps
CPU time 1.15 seconds
Started Jul 11 06:43:15 PM PDT 24
Finished Jul 11 06:43:18 PM PDT 24
Peak memory 217444 kb
Host smart-47d53308-3bb7-4364-a763-46e745ad471a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973788900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3973788900
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.100431413
Short name T544
Test name
Test status
Simulation time 173536546 ps
CPU time 0.9 seconds
Started Jul 11 06:43:10 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 200000 kb
Host smart-820745a4-5336-4883-ac02-afa1ac8ad682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100431413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.100431413
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.502767460
Short name T130
Test name
Test status
Simulation time 2282626097 ps
CPU time 7.81 seconds
Started Jul 11 06:43:09 PM PDT 24
Finished Jul 11 06:43:18 PM PDT 24
Peak memory 200492 kb
Host smart-d1dc0599-ac47-4dc1-acd5-e7c9c7060975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502767460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.502767460
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2094934561
Short name T139
Test name
Test status
Simulation time 181998009 ps
CPU time 1.15 seconds
Started Jul 11 06:43:07 PM PDT 24
Finished Jul 11 06:43:10 PM PDT 24
Peak memory 200160 kb
Host smart-3a0e22c9-5282-4f68-a770-969c73fc85e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094934561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2094934561
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1380325091
Short name T368
Test name
Test status
Simulation time 200455827 ps
CPU time 1.37 seconds
Started Jul 11 06:43:09 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 200364 kb
Host smart-32b93d0b-d2a5-4727-9c03-2810b03e7f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380325091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1380325091
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.922007854
Short name T435
Test name
Test status
Simulation time 3062469590 ps
CPU time 13.59 seconds
Started Jul 11 06:43:09 PM PDT 24
Finished Jul 11 06:43:24 PM PDT 24
Peak memory 208720 kb
Host smart-422727f5-e417-47d2-a5d8-ad1dc11b59a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922007854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.922007854
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1500832057
Short name T424
Test name
Test status
Simulation time 273446955 ps
CPU time 1.9 seconds
Started Jul 11 06:43:10 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 200172 kb
Host smart-5411a02f-0d14-4b48-b27c-aa2e60d6c95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500832057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1500832057
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.548245042
Short name T316
Test name
Test status
Simulation time 212987975 ps
CPU time 1.3 seconds
Started Jul 11 06:43:09 PM PDT 24
Finished Jul 11 06:43:12 PM PDT 24
Peak memory 200172 kb
Host smart-49825ae2-99e3-46f8-8d96-16d8399aea93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548245042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.548245042
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1551634907
Short name T383
Test name
Test status
Simulation time 55409711 ps
CPU time 0.73 seconds
Started Jul 11 06:43:11 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 199964 kb
Host smart-6fd04546-8566-4a8a-b998-abf8c95d6627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551634907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1551634907
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.824729730
Short name T532
Test name
Test status
Simulation time 1220039949 ps
CPU time 5.78 seconds
Started Jul 11 06:43:13 PM PDT 24
Finished Jul 11 06:43:20 PM PDT 24
Peak memory 217404 kb
Host smart-d7fcfc2f-cfeb-47a6-9f95-6dc3a76eb226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824729730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.824729730
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.612934918
Short name T297
Test name
Test status
Simulation time 244779876 ps
CPU time 1.05 seconds
Started Jul 11 06:43:10 PM PDT 24
Finished Jul 11 06:43:12 PM PDT 24
Peak memory 217532 kb
Host smart-c3e44e75-7d07-4b0d-ba44-815709c8471e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612934918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.612934918
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1304016497
Short name T286
Test name
Test status
Simulation time 215579277 ps
CPU time 0.93 seconds
Started Jul 11 06:43:15 PM PDT 24
Finished Jul 11 06:43:18 PM PDT 24
Peak memory 199896 kb
Host smart-26b0972e-beae-47e5-b70c-708b8ccfb1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304016497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1304016497
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.4244014354
Short name T308
Test name
Test status
Simulation time 685581630 ps
CPU time 3.85 seconds
Started Jul 11 06:43:12 PM PDT 24
Finished Jul 11 06:43:17 PM PDT 24
Peak memory 200428 kb
Host smart-3c4f12ee-586f-486f-8169-a32199e1374e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244014354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.4244014354
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1126009801
Short name T321
Test name
Test status
Simulation time 114200677 ps
CPU time 1.11 seconds
Started Jul 11 06:43:10 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 200440 kb
Host smart-bc8afeb9-97b0-40d1-9bcd-a7274b3673cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126009801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1126009801
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2636914613
Short name T179
Test name
Test status
Simulation time 7220467871 ps
CPU time 27.5 seconds
Started Jul 11 06:43:12 PM PDT 24
Finished Jul 11 06:43:41 PM PDT 24
Peak memory 208688 kb
Host smart-71a86bd1-da2a-4ead-9250-776527a305c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636914613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2636914613
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.857163056
Short name T268
Test name
Test status
Simulation time 311905725 ps
CPU time 2.24 seconds
Started Jul 11 06:43:11 PM PDT 24
Finished Jul 11 06:43:15 PM PDT 24
Peak memory 208368 kb
Host smart-c5ce8d62-5446-45c9-8a69-1baa53bb2543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857163056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.857163056
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3218387550
Short name T401
Test name
Test status
Simulation time 145495667 ps
CPU time 1.11 seconds
Started Jul 11 06:43:11 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 200136 kb
Host smart-5dbd031c-07bb-4267-b68c-806bde5f4b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218387550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3218387550
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2884783216
Short name T479
Test name
Test status
Simulation time 67898473 ps
CPU time 0.76 seconds
Started Jul 11 06:43:13 PM PDT 24
Finished Jul 11 06:43:16 PM PDT 24
Peak memory 199956 kb
Host smart-bc828af7-6556-4fd1-ab45-c926ee6386a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884783216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2884783216
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3776473100
Short name T342
Test name
Test status
Simulation time 2353348368 ps
CPU time 7.92 seconds
Started Jul 11 06:43:12 PM PDT 24
Finished Jul 11 06:43:22 PM PDT 24
Peak memory 217796 kb
Host smart-0324acae-5da5-4373-9966-5f3f4771430b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776473100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3776473100
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1902953099
Short name T289
Test name
Test status
Simulation time 243950527 ps
CPU time 1.05 seconds
Started Jul 11 06:43:15 PM PDT 24
Finished Jul 11 06:43:18 PM PDT 24
Peak memory 217572 kb
Host smart-8ae2e842-0641-44d7-9357-d08468cee16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902953099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1902953099
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3920107613
Short name T231
Test name
Test status
Simulation time 162774294 ps
CPU time 0.84 seconds
Started Jul 11 06:43:10 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 199992 kb
Host smart-5dffbbfc-8dae-458e-a250-2c37fd1763a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920107613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3920107613
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.72056372
Short name T499
Test name
Test status
Simulation time 838116293 ps
CPU time 4.23 seconds
Started Jul 11 06:43:11 PM PDT 24
Finished Jul 11 06:43:16 PM PDT 24
Peak memory 200448 kb
Host smart-4e1d0561-3ec4-4d34-91a3-a183216bda00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72056372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.72056372
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2336716926
Short name T157
Test name
Test status
Simulation time 174280285 ps
CPU time 1.23 seconds
Started Jul 11 06:43:14 PM PDT 24
Finished Jul 11 06:43:17 PM PDT 24
Peak memory 200184 kb
Host smart-1ec82285-ebd1-456d-8926-e3f914b7cfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336716926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2336716926
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1876222817
Short name T295
Test name
Test status
Simulation time 250112826 ps
CPU time 1.6 seconds
Started Jul 11 06:43:08 PM PDT 24
Finished Jul 11 06:43:11 PM PDT 24
Peak memory 200372 kb
Host smart-77c0908c-a354-48a4-b2dd-4c35a14a2c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876222817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1876222817
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.77666941
Short name T189
Test name
Test status
Simulation time 3763097736 ps
CPU time 17.81 seconds
Started Jul 11 06:43:12 PM PDT 24
Finished Jul 11 06:43:32 PM PDT 24
Peak memory 200564 kb
Host smart-998bfc4b-1eb3-4bb1-845f-275ca286f6bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77666941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.77666941
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2842759541
Short name T238
Test name
Test status
Simulation time 124748312 ps
CPU time 1.55 seconds
Started Jul 11 06:43:15 PM PDT 24
Finished Jul 11 06:43:18 PM PDT 24
Peak memory 200376 kb
Host smart-512f0bc5-57b4-4811-b520-ea2dbfaeb8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842759541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2842759541
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.138289947
Short name T487
Test name
Test status
Simulation time 159831561 ps
CPU time 1.1 seconds
Started Jul 11 06:43:10 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 200072 kb
Host smart-e63e95bd-6200-45bf-af4b-a4a33a27eb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138289947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.138289947
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3176575302
Short name T230
Test name
Test status
Simulation time 64160755 ps
CPU time 0.77 seconds
Started Jul 11 06:43:18 PM PDT 24
Finished Jul 11 06:43:21 PM PDT 24
Peak memory 199932 kb
Host smart-5f046551-1852-4741-9641-6517b6b3b30e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176575302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3176575302
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3211295786
Short name T470
Test name
Test status
Simulation time 1230465485 ps
CPU time 5.38 seconds
Started Jul 11 06:43:15 PM PDT 24
Finished Jul 11 06:43:22 PM PDT 24
Peak memory 217764 kb
Host smart-a876b095-1087-4bdb-b96d-18117ff3bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211295786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3211295786
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1065646080
Short name T192
Test name
Test status
Simulation time 244191066 ps
CPU time 1.01 seconds
Started Jul 11 06:43:11 PM PDT 24
Finished Jul 11 06:43:14 PM PDT 24
Peak memory 217616 kb
Host smart-d9230c66-0403-42d8-b2fe-9546d607aa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065646080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1065646080
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2207056595
Short name T279
Test name
Test status
Simulation time 176200659 ps
CPU time 0.89 seconds
Started Jul 11 06:43:14 PM PDT 24
Finished Jul 11 06:43:17 PM PDT 24
Peak memory 199972 kb
Host smart-f672f425-d8d2-4bc4-8513-c412e8893371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207056595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2207056595
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1738958574
Short name T307
Test name
Test status
Simulation time 1410167513 ps
CPU time 5.57 seconds
Started Jul 11 06:43:14 PM PDT 24
Finished Jul 11 06:43:21 PM PDT 24
Peak memory 200424 kb
Host smart-b04075de-6893-4418-9ea5-e5e7ef3be314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738958574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1738958574
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2177022266
Short name T355
Test name
Test status
Simulation time 97021915 ps
CPU time 1.02 seconds
Started Jul 11 06:43:15 PM PDT 24
Finished Jul 11 06:43:18 PM PDT 24
Peak memory 200160 kb
Host smart-888863a7-e1d3-499f-8210-9cdaef18195b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177022266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2177022266
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2531820958
Short name T150
Test name
Test status
Simulation time 126147446 ps
CPU time 1.25 seconds
Started Jul 11 06:43:14 PM PDT 24
Finished Jul 11 06:43:16 PM PDT 24
Peak memory 200264 kb
Host smart-17bbe9c5-b58e-4e85-9c6d-1842eef4a970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531820958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2531820958
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.180151576
Short name T132
Test name
Test status
Simulation time 7428638305 ps
CPU time 27.05 seconds
Started Jul 11 06:43:15 PM PDT 24
Finished Jul 11 06:43:44 PM PDT 24
Peak memory 208596 kb
Host smart-509613c8-acdc-47be-b4fd-f4d0f74db28d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180151576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.180151576
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.191110890
Short name T440
Test name
Test status
Simulation time 428369556 ps
CPU time 2.53 seconds
Started Jul 11 06:43:14 PM PDT 24
Finished Jul 11 06:43:18 PM PDT 24
Peak memory 200188 kb
Host smart-c56cdfbb-99e6-4aa4-a657-c88692cb2422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191110890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.191110890
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1230641109
Short name T251
Test name
Test status
Simulation time 136739995 ps
CPU time 1.19 seconds
Started Jul 11 06:43:12 PM PDT 24
Finished Jul 11 06:43:15 PM PDT 24
Peak memory 200176 kb
Host smart-d37c5ab4-e9c4-4709-95db-96ac11f7a664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230641109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1230641109
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.608289620
Short name T538
Test name
Test status
Simulation time 70571930 ps
CPU time 0.8 seconds
Started Jul 11 06:42:01 PM PDT 24
Finished Jul 11 06:42:02 PM PDT 24
Peak memory 199956 kb
Host smart-f3262bde-8f08-4679-8351-8412e7c6ae63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608289620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.608289620
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3294222948
Short name T354
Test name
Test status
Simulation time 2363718851 ps
CPU time 8.27 seconds
Started Jul 11 06:42:02 PM PDT 24
Finished Jul 11 06:42:11 PM PDT 24
Peak memory 217360 kb
Host smart-6e004f09-d98b-4c5c-9a5b-13b170a57f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294222948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3294222948
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3561607221
Short name T475
Test name
Test status
Simulation time 244023668 ps
CPU time 1.11 seconds
Started Jul 11 06:42:03 PM PDT 24
Finished Jul 11 06:42:05 PM PDT 24
Peak memory 217532 kb
Host smart-0c69278a-3530-4f21-aacf-e8c4700b37aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561607221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3561607221
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1029614522
Short name T519
Test name
Test status
Simulation time 113189857 ps
CPU time 0.84 seconds
Started Jul 11 06:42:04 PM PDT 24
Finished Jul 11 06:42:05 PM PDT 24
Peak memory 200000 kb
Host smart-eb83f2b4-6983-47dd-b811-47e7f2d41899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029614522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1029614522
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1763332439
Short name T309
Test name
Test status
Simulation time 1584418900 ps
CPU time 6.3 seconds
Started Jul 11 06:42:00 PM PDT 24
Finished Jul 11 06:42:07 PM PDT 24
Peak memory 200408 kb
Host smart-41f6730b-0395-491f-82e5-338377848d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763332439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1763332439
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1288420753
Short name T67
Test name
Test status
Simulation time 16668161670 ps
CPU time 26 seconds
Started Jul 11 06:42:01 PM PDT 24
Finished Jul 11 06:42:28 PM PDT 24
Peak memory 217276 kb
Host smart-d96bf9c3-6d33-429e-9bf3-7220180edc34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288420753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1288420753
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1419370601
Short name T336
Test name
Test status
Simulation time 142036809 ps
CPU time 1.12 seconds
Started Jul 11 06:42:03 PM PDT 24
Finished Jul 11 06:42:05 PM PDT 24
Peak memory 200180 kb
Host smart-b5b165f5-789f-4d96-8e70-5785f85de9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419370601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1419370601
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.903746211
Short name T270
Test name
Test status
Simulation time 231204102 ps
CPU time 1.57 seconds
Started Jul 11 06:42:01 PM PDT 24
Finished Jul 11 06:42:03 PM PDT 24
Peak memory 200396 kb
Host smart-542c7a48-bea8-4cb5-b8b6-b620ac1bacb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903746211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.903746211
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.468187663
Short name T445
Test name
Test status
Simulation time 9708781661 ps
CPU time 49.87 seconds
Started Jul 11 06:42:01 PM PDT 24
Finished Jul 11 06:42:52 PM PDT 24
Peak memory 208684 kb
Host smart-86f41887-5461-4688-b339-5f1819fd3af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468187663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.468187663
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.4069599631
Short name T373
Test name
Test status
Simulation time 155699723 ps
CPU time 1.91 seconds
Started Jul 11 06:42:02 PM PDT 24
Finished Jul 11 06:42:05 PM PDT 24
Peak memory 200156 kb
Host smart-7d177ad1-3516-4e3e-9ddc-6323805d0ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069599631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.4069599631
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1638146003
Short name T474
Test name
Test status
Simulation time 192780954 ps
CPU time 1.36 seconds
Started Jul 11 06:42:02 PM PDT 24
Finished Jul 11 06:42:04 PM PDT 24
Peak memory 200184 kb
Host smart-7c8869cb-de5f-4dfc-b9f4-4c88936826c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638146003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1638146003
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1947303377
Short name T186
Test name
Test status
Simulation time 78286422 ps
CPU time 0.89 seconds
Started Jul 11 06:43:19 PM PDT 24
Finished Jul 11 06:43:22 PM PDT 24
Peak memory 199932 kb
Host smart-0627649e-d18f-4c25-ad5e-5643b190e269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947303377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1947303377
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1105378838
Short name T448
Test name
Test status
Simulation time 1892626746 ps
CPU time 7.16 seconds
Started Jul 11 06:43:18 PM PDT 24
Finished Jul 11 06:43:27 PM PDT 24
Peak memory 217544 kb
Host smart-3a951a2a-fd6a-4361-b52a-23b2e1707694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105378838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1105378838
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.919257027
Short name T370
Test name
Test status
Simulation time 244023453 ps
CPU time 1.06 seconds
Started Jul 11 06:43:18 PM PDT 24
Finished Jul 11 06:43:21 PM PDT 24
Peak memory 217532 kb
Host smart-06a44a82-0956-49c1-9736-c941782e287f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919257027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.919257027
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2326874911
Short name T517
Test name
Test status
Simulation time 98284503 ps
CPU time 0.78 seconds
Started Jul 11 06:43:25 PM PDT 24
Finished Jul 11 06:43:28 PM PDT 24
Peak memory 199980 kb
Host smart-582ce84b-73dc-41c8-a8ab-ab6a2c65acfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326874911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2326874911
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3604032466
Short name T104
Test name
Test status
Simulation time 790575668 ps
CPU time 4.4 seconds
Started Jul 11 06:43:17 PM PDT 24
Finished Jul 11 06:43:24 PM PDT 24
Peak memory 200408 kb
Host smart-e7452cc1-d8ce-4c66-b371-39b8efb5f2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604032466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3604032466
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3407594474
Short name T136
Test name
Test status
Simulation time 156488439 ps
CPU time 1.08 seconds
Started Jul 11 06:43:17 PM PDT 24
Finished Jul 11 06:43:20 PM PDT 24
Peak memory 200164 kb
Host smart-d528ae20-c037-4ac7-8974-6a5109a43b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407594474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3407594474
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.144724923
Short name T237
Test name
Test status
Simulation time 263238518 ps
CPU time 1.54 seconds
Started Jul 11 06:43:19 PM PDT 24
Finished Jul 11 06:43:23 PM PDT 24
Peak memory 200296 kb
Host smart-25f08391-66ba-4fee-9b52-4ba2f2bf0f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144724923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.144724923
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.4201406865
Short name T457
Test name
Test status
Simulation time 3577258983 ps
CPU time 13.02 seconds
Started Jul 11 06:43:18 PM PDT 24
Finished Jul 11 06:43:33 PM PDT 24
Peak memory 208704 kb
Host smart-1f3bf6d6-ce5b-4955-ac39-1c3ce61fa743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201406865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.4201406865
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1209219149
Short name T90
Test name
Test status
Simulation time 387488796 ps
CPU time 2.61 seconds
Started Jul 11 06:43:18 PM PDT 24
Finished Jul 11 06:43:23 PM PDT 24
Peak memory 200172 kb
Host smart-b1ed5256-b45c-42ab-9680-e3d43b18c61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209219149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1209219149
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3771051038
Short name T426
Test name
Test status
Simulation time 125576852 ps
CPU time 1.04 seconds
Started Jul 11 06:43:18 PM PDT 24
Finished Jul 11 06:43:22 PM PDT 24
Peak memory 200192 kb
Host smart-243bf181-5389-48d1-acf3-fd1dfb9161ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771051038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3771051038
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1736143823
Short name T291
Test name
Test status
Simulation time 73498888 ps
CPU time 0.8 seconds
Started Jul 11 06:43:23 PM PDT 24
Finished Jul 11 06:43:25 PM PDT 24
Peak memory 199960 kb
Host smart-01af032f-d935-4410-92ed-4cc7a87e6bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736143823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1736143823
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1281528850
Short name T54
Test name
Test status
Simulation time 2352256561 ps
CPU time 9.22 seconds
Started Jul 11 06:43:23 PM PDT 24
Finished Jul 11 06:43:34 PM PDT 24
Peak memory 217968 kb
Host smart-c50af7de-ff3e-4c1f-b389-e81f94754407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281528850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1281528850
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1039147959
Short name T246
Test name
Test status
Simulation time 243865374 ps
CPU time 1.11 seconds
Started Jul 11 06:43:26 PM PDT 24
Finished Jul 11 06:43:28 PM PDT 24
Peak memory 217616 kb
Host smart-29bf614a-97e1-4e09-b109-ce265b7520ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039147959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1039147959
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2733015964
Short name T5
Test name
Test status
Simulation time 222949554 ps
CPU time 1.06 seconds
Started Jul 11 06:43:17 PM PDT 24
Finished Jul 11 06:43:20 PM PDT 24
Peak memory 199988 kb
Host smart-a6a14321-50ed-4e18-be55-d7f82e4e676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733015964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2733015964
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1535064025
Short name T537
Test name
Test status
Simulation time 2059589658 ps
CPU time 8.24 seconds
Started Jul 11 06:43:18 PM PDT 24
Finished Jul 11 06:43:29 PM PDT 24
Peak memory 200480 kb
Host smart-9d674422-80fd-494e-82da-0a3bd095b468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535064025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1535064025
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.4180820928
Short name T35
Test name
Test status
Simulation time 146781151 ps
CPU time 1.13 seconds
Started Jul 11 06:43:17 PM PDT 24
Finished Jul 11 06:43:20 PM PDT 24
Peak memory 200132 kb
Host smart-dfc25fb5-dcaa-4bc5-bc6a-20d6fbcd4978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180820928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.4180820928
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3603564336
Short name T49
Test name
Test status
Simulation time 199823711 ps
CPU time 1.5 seconds
Started Jul 11 06:43:20 PM PDT 24
Finished Jul 11 06:43:23 PM PDT 24
Peak memory 200340 kb
Host smart-e53fc89f-1bf2-4bde-9d1c-906e85df1377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603564336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3603564336
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1138712100
Short name T158
Test name
Test status
Simulation time 460704316 ps
CPU time 2.27 seconds
Started Jul 11 06:43:26 PM PDT 24
Finished Jul 11 06:43:30 PM PDT 24
Peak memory 200324 kb
Host smart-1acb416e-7540-48a5-ac46-ebd958a56954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138712100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1138712100
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3001731278
Short name T58
Test name
Test status
Simulation time 257831897 ps
CPU time 1.77 seconds
Started Jul 11 06:43:20 PM PDT 24
Finished Jul 11 06:43:23 PM PDT 24
Peak memory 200184 kb
Host smart-9290146b-b29d-4f2f-8f8e-c9433329ab40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001731278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3001731278
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1281420496
Short name T245
Test name
Test status
Simulation time 94618609 ps
CPU time 0.95 seconds
Started Jul 11 06:43:18 PM PDT 24
Finished Jul 11 06:43:21 PM PDT 24
Peak memory 200196 kb
Host smart-ddad0377-8316-4d3a-bbb7-160f3c09c001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281420496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1281420496
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1211188693
Short name T518
Test name
Test status
Simulation time 72320877 ps
CPU time 0.79 seconds
Started Jul 11 06:43:24 PM PDT 24
Finished Jul 11 06:43:26 PM PDT 24
Peak memory 199976 kb
Host smart-0907d526-9a73-4954-bf2e-2b75e167c6c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211188693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1211188693
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2684147403
Short name T467
Test name
Test status
Simulation time 2363638531 ps
CPU time 9.74 seconds
Started Jul 11 06:43:22 PM PDT 24
Finished Jul 11 06:43:33 PM PDT 24
Peak memory 217896 kb
Host smart-497aa8c5-e861-456e-b626-17641a8099ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684147403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2684147403
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2066850507
Short name T541
Test name
Test status
Simulation time 244743690 ps
CPU time 1.07 seconds
Started Jul 11 06:43:26 PM PDT 24
Finished Jul 11 06:43:28 PM PDT 24
Peak memory 217692 kb
Host smart-f587744e-fa4a-4a33-b1fb-15821483b656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066850507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2066850507
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2746943625
Short name T13
Test name
Test status
Simulation time 137999664 ps
CPU time 0.83 seconds
Started Jul 11 06:43:24 PM PDT 24
Finished Jul 11 06:43:26 PM PDT 24
Peak memory 199992 kb
Host smart-2099a248-3df0-49fe-98dc-0a1824280cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746943625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2746943625
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.673030024
Short name T525
Test name
Test status
Simulation time 1489463067 ps
CPU time 5.68 seconds
Started Jul 11 06:43:24 PM PDT 24
Finished Jul 11 06:43:31 PM PDT 24
Peak memory 200380 kb
Host smart-63af48b7-514e-45c1-946a-0aa785ba9ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673030024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.673030024
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.620150411
Short name T235
Test name
Test status
Simulation time 176612723 ps
CPU time 1.26 seconds
Started Jul 11 06:43:25 PM PDT 24
Finished Jul 11 06:43:27 PM PDT 24
Peak memory 200168 kb
Host smart-a96e28ab-72d3-4cfc-92b8-46868f5c0d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620150411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.620150411
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3689031337
Short name T458
Test name
Test status
Simulation time 247441003 ps
CPU time 1.6 seconds
Started Jul 11 06:43:25 PM PDT 24
Finished Jul 11 06:43:28 PM PDT 24
Peak memory 200316 kb
Host smart-06f39f20-8cf2-458c-b820-2e1141d658b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689031337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3689031337
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3548221996
Short name T80
Test name
Test status
Simulation time 5609454318 ps
CPU time 19.97 seconds
Started Jul 11 06:43:25 PM PDT 24
Finished Jul 11 06:43:47 PM PDT 24
Peak memory 200496 kb
Host smart-6b3d8c6b-0a2c-41d0-a22b-f3fe10224578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548221996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3548221996
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1559382600
Short name T417
Test name
Test status
Simulation time 120485722 ps
CPU time 1.44 seconds
Started Jul 11 06:43:24 PM PDT 24
Finished Jul 11 06:43:27 PM PDT 24
Peak memory 200168 kb
Host smart-f135785d-b2ae-49c8-8cd5-87a5cda68829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559382600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1559382600
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1081837332
Short name T471
Test name
Test status
Simulation time 218106227 ps
CPU time 1.36 seconds
Started Jul 11 06:43:22 PM PDT 24
Finished Jul 11 06:43:24 PM PDT 24
Peak memory 200196 kb
Host smart-38278a10-5693-40b5-a6bd-0bdb0e2c6acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081837332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1081837332
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2907539092
Short name T468
Test name
Test status
Simulation time 67576864 ps
CPU time 0.77 seconds
Started Jul 11 06:43:29 PM PDT 24
Finished Jul 11 06:43:31 PM PDT 24
Peak memory 199972 kb
Host smart-b128c916-ac74-4e35-9b25-ee663b459ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907539092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2907539092
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.9360506
Short name T28
Test name
Test status
Simulation time 2364633109 ps
CPU time 9.53 seconds
Started Jul 11 06:43:29 PM PDT 24
Finished Jul 11 06:43:40 PM PDT 24
Peak memory 217780 kb
Host smart-d04d4b9d-d544-48ce-aef0-24399807336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9360506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.9360506
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2217306183
Short name T379
Test name
Test status
Simulation time 244073456 ps
CPU time 1.13 seconds
Started Jul 11 06:43:27 PM PDT 24
Finished Jul 11 06:43:29 PM PDT 24
Peak memory 217540 kb
Host smart-7774b4c5-acfb-4139-9f06-439c28380243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217306183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2217306183
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3524471729
Short name T213
Test name
Test status
Simulation time 212913836 ps
CPU time 0.86 seconds
Started Jul 11 06:43:23 PM PDT 24
Finished Jul 11 06:43:25 PM PDT 24
Peak memory 199996 kb
Host smart-8e3eac9e-5ec1-4a04-a640-23c81120849e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524471729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3524471729
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1334840024
Short name T3
Test name
Test status
Simulation time 1386380905 ps
CPU time 5.59 seconds
Started Jul 11 06:43:29 PM PDT 24
Finished Jul 11 06:43:36 PM PDT 24
Peak memory 200312 kb
Host smart-37b0c3d7-1021-4cc6-bf55-74d2b9f9e86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334840024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1334840024
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1753927083
Short name T411
Test name
Test status
Simulation time 173870048 ps
CPU time 1.19 seconds
Started Jul 11 06:43:27 PM PDT 24
Finished Jul 11 06:43:30 PM PDT 24
Peak memory 200192 kb
Host smart-ef30fdff-5395-45e4-b83b-d62bf3877bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753927083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1753927083
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2569288685
Short name T190
Test name
Test status
Simulation time 121707580 ps
CPU time 1.2 seconds
Started Jul 11 06:43:25 PM PDT 24
Finished Jul 11 06:43:27 PM PDT 24
Peak memory 200364 kb
Host smart-858227b5-fa58-4fc9-a90d-1ba51b4bda50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569288685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2569288685
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.416393377
Short name T48
Test name
Test status
Simulation time 9240142285 ps
CPU time 36.82 seconds
Started Jul 11 06:43:31 PM PDT 24
Finished Jul 11 06:44:09 PM PDT 24
Peak memory 209984 kb
Host smart-1418f070-8304-4d43-8568-612c3f6a4210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416393377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.416393377
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3665926438
Short name T330
Test name
Test status
Simulation time 307410177 ps
CPU time 2.08 seconds
Started Jul 11 06:43:27 PM PDT 24
Finished Jul 11 06:43:31 PM PDT 24
Peak memory 208376 kb
Host smart-f598cf64-dcac-4f64-8f98-2b0e256709b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665926438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3665926438
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.527344197
Short name T198
Test name
Test status
Simulation time 116153047 ps
CPU time 1 seconds
Started Jul 11 06:43:29 PM PDT 24
Finished Jul 11 06:43:31 PM PDT 24
Peak memory 200160 kb
Host smart-d9a69485-d954-422e-871d-710ee686bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527344197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.527344197
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3330893750
Short name T466
Test name
Test status
Simulation time 71330995 ps
CPU time 0.77 seconds
Started Jul 11 06:43:27 PM PDT 24
Finished Jul 11 06:43:29 PM PDT 24
Peak memory 199928 kb
Host smart-df1c5112-76c4-4437-99cd-2890da114570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330893750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3330893750
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3103036068
Short name T314
Test name
Test status
Simulation time 244206203 ps
CPU time 1.09 seconds
Started Jul 11 06:43:28 PM PDT 24
Finished Jul 11 06:43:31 PM PDT 24
Peak memory 217692 kb
Host smart-34c2ca7e-dbeb-4593-9e7e-13483d46354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103036068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3103036068
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2015960831
Short name T313
Test name
Test status
Simulation time 98027020 ps
CPU time 0.8 seconds
Started Jul 11 06:43:29 PM PDT 24
Finished Jul 11 06:43:31 PM PDT 24
Peak memory 199992 kb
Host smart-6bcbd241-3629-4800-b065-4d8fccc98ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015960831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2015960831
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3668373689
Short name T357
Test name
Test status
Simulation time 1386256769 ps
CPU time 5.41 seconds
Started Jul 11 06:43:28 PM PDT 24
Finished Jul 11 06:43:34 PM PDT 24
Peak memory 200444 kb
Host smart-b31e2ba3-f721-4fd4-aeab-014f251911e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668373689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3668373689
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.753960250
Short name T167
Test name
Test status
Simulation time 155530058 ps
CPU time 1.17 seconds
Started Jul 11 06:43:27 PM PDT 24
Finished Jul 11 06:43:30 PM PDT 24
Peak memory 200164 kb
Host smart-fbcf1eb4-7086-49b0-9cd5-53725ed7509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753960250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.753960250
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.4004432272
Short name T187
Test name
Test status
Simulation time 254113546 ps
CPU time 1.57 seconds
Started Jul 11 06:43:30 PM PDT 24
Finished Jul 11 06:43:33 PM PDT 24
Peak memory 200372 kb
Host smart-97e74f4c-2367-4f8d-95b6-9282f3ff7d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004432272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.4004432272
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2627029462
Short name T408
Test name
Test status
Simulation time 10829160413 ps
CPU time 38.65 seconds
Started Jul 11 06:43:28 PM PDT 24
Finished Jul 11 06:44:09 PM PDT 24
Peak memory 200500 kb
Host smart-1789a343-98d2-4a19-8aaa-1c901ac726c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627029462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2627029462
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3408068728
Short name T405
Test name
Test status
Simulation time 474442927 ps
CPU time 2.64 seconds
Started Jul 11 06:43:27 PM PDT 24
Finished Jul 11 06:43:31 PM PDT 24
Peak memory 208352 kb
Host smart-fa1a2452-de5f-4cd7-82f9-63c5a02ae775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408068728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3408068728
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1868429218
Short name T356
Test name
Test status
Simulation time 244994845 ps
CPU time 1.46 seconds
Started Jul 11 06:43:28 PM PDT 24
Finished Jul 11 06:43:31 PM PDT 24
Peak memory 200176 kb
Host smart-90a39c0b-37d5-4408-af47-988edd307a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868429218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1868429218
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3590783931
Short name T227
Test name
Test status
Simulation time 72068611 ps
CPU time 0.78 seconds
Started Jul 11 06:43:36 PM PDT 24
Finished Jul 11 06:43:39 PM PDT 24
Peak memory 199948 kb
Host smart-cc68f6bc-2af4-408b-a67e-e49058f0d4ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590783931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3590783931
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.434986377
Short name T385
Test name
Test status
Simulation time 2350591495 ps
CPU time 8.92 seconds
Started Jul 11 06:43:33 PM PDT 24
Finished Jul 11 06:43:43 PM PDT 24
Peak memory 221792 kb
Host smart-58d8716e-1ed1-4d20-ab11-d24b025695e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434986377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.434986377
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4293341142
Short name T170
Test name
Test status
Simulation time 243869760 ps
CPU time 1.09 seconds
Started Jul 11 06:43:36 PM PDT 24
Finished Jul 11 06:43:38 PM PDT 24
Peak memory 217516 kb
Host smart-7a6ca19c-dcaf-4320-a92d-6886a9365e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293341142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4293341142
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3696048289
Short name T278
Test name
Test status
Simulation time 135608509 ps
CPU time 0.81 seconds
Started Jul 11 06:43:34 PM PDT 24
Finished Jul 11 06:43:35 PM PDT 24
Peak memory 199984 kb
Host smart-d8a9e3f9-7562-4d69-8996-5e071d5f77e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696048289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3696048289
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3354319709
Short name T333
Test name
Test status
Simulation time 698039728 ps
CPU time 3.6 seconds
Started Jul 11 06:43:33 PM PDT 24
Finished Jul 11 06:43:37 PM PDT 24
Peak memory 200428 kb
Host smart-0eb2841a-03c5-4774-9804-02311246e932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354319709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3354319709
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3630913630
Short name T520
Test name
Test status
Simulation time 101789546 ps
CPU time 1.07 seconds
Started Jul 11 06:43:34 PM PDT 24
Finished Jul 11 06:43:36 PM PDT 24
Peak memory 200140 kb
Host smart-4f7e8a06-1903-4c0d-a6a9-865803260afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630913630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3630913630
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.4198506381
Short name T324
Test name
Test status
Simulation time 192984863 ps
CPU time 1.46 seconds
Started Jul 11 06:43:35 PM PDT 24
Finished Jul 11 06:43:38 PM PDT 24
Peak memory 200360 kb
Host smart-367aa9ee-931e-4b9c-89b4-6e1bb68a4aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198506381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.4198506381
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.422443217
Short name T161
Test name
Test status
Simulation time 3367399145 ps
CPU time 14.61 seconds
Started Jul 11 06:43:35 PM PDT 24
Finished Jul 11 06:43:51 PM PDT 24
Peak memory 208640 kb
Host smart-021ae2df-c108-4a21-90bd-999d34cc1cd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422443217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.422443217
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1293407278
Short name T416
Test name
Test status
Simulation time 120791691 ps
CPU time 1.07 seconds
Started Jul 11 06:43:33 PM PDT 24
Finished Jul 11 06:43:35 PM PDT 24
Peak memory 200180 kb
Host smart-04f43080-fe21-48ae-a991-1321cc705f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293407278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1293407278
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2322921683
Short name T326
Test name
Test status
Simulation time 89940801 ps
CPU time 0.88 seconds
Started Jul 11 06:43:35 PM PDT 24
Finished Jul 11 06:43:37 PM PDT 24
Peak memory 199964 kb
Host smart-3118fd6d-bb68-43a4-ad61-cf745caa18f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322921683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2322921683
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.7475933
Short name T31
Test name
Test status
Simulation time 1234747372 ps
CPU time 6.12 seconds
Started Jul 11 06:43:33 PM PDT 24
Finished Jul 11 06:43:40 PM PDT 24
Peak memory 221760 kb
Host smart-3dc8e9bd-3922-4fdd-b6d6-8f0c77826254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7475933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.7475933
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.693368759
Short name T233
Test name
Test status
Simulation time 244107577 ps
CPU time 1.07 seconds
Started Jul 11 06:43:36 PM PDT 24
Finished Jul 11 06:43:39 PM PDT 24
Peak memory 217464 kb
Host smart-6435bb94-14cd-4baa-8418-1acba26582ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693368759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.693368759
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.873886474
Short name T16
Test name
Test status
Simulation time 83860875 ps
CPU time 0.73 seconds
Started Jul 11 06:43:33 PM PDT 24
Finished Jul 11 06:43:35 PM PDT 24
Peak memory 199988 kb
Host smart-1c844051-e80e-4249-9083-cce34396f43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873886474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.873886474
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3299828153
Short name T427
Test name
Test status
Simulation time 856407364 ps
CPU time 4.34 seconds
Started Jul 11 06:43:39 PM PDT 24
Finished Jul 11 06:43:45 PM PDT 24
Peak memory 200388 kb
Host smart-33d36881-5947-4e34-bfef-1ebb4e1aa154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299828153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3299828153
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.919431204
Short name T343
Test name
Test status
Simulation time 106606411 ps
CPU time 1 seconds
Started Jul 11 06:43:32 PM PDT 24
Finished Jul 11 06:43:34 PM PDT 24
Peak memory 200176 kb
Host smart-39b850ee-2b7d-47c1-acbe-e9837bac2635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919431204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.919431204
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.4232894299
Short name T463
Test name
Test status
Simulation time 260705910 ps
CPU time 1.51 seconds
Started Jul 11 06:43:37 PM PDT 24
Finished Jul 11 06:43:40 PM PDT 24
Peak memory 200368 kb
Host smart-a63e96e0-b95c-4525-834f-f53e56565db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232894299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.4232894299
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.418408816
Short name T254
Test name
Test status
Simulation time 140902244 ps
CPU time 1.8 seconds
Started Jul 11 06:43:35 PM PDT 24
Finished Jul 11 06:43:37 PM PDT 24
Peak memory 200184 kb
Host smart-5a7b929d-295b-482f-bae8-f855ff9e2c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418408816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.418408816
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3347686607
Short name T225
Test name
Test status
Simulation time 70023718 ps
CPU time 0.86 seconds
Started Jul 11 06:43:38 PM PDT 24
Finished Jul 11 06:43:40 PM PDT 24
Peak memory 199968 kb
Host smart-3c0a5eef-9484-40c4-b5e8-59abaf55035f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347686607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3347686607
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3718243529
Short name T429
Test name
Test status
Simulation time 243782588 ps
CPU time 1.06 seconds
Started Jul 11 06:43:37 PM PDT 24
Finished Jul 11 06:43:40 PM PDT 24
Peak memory 217552 kb
Host smart-4945358f-0eaa-41b0-a509-e932794e2780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718243529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3718243529
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2743935857
Short name T442
Test name
Test status
Simulation time 123735513 ps
CPU time 0.8 seconds
Started Jul 11 06:43:37 PM PDT 24
Finished Jul 11 06:43:39 PM PDT 24
Peak memory 199984 kb
Host smart-a56c982e-65e9-4abd-8bf7-6cf853b66fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743935857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2743935857
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3278077948
Short name T534
Test name
Test status
Simulation time 943170566 ps
CPU time 5.5 seconds
Started Jul 11 06:43:37 PM PDT 24
Finished Jul 11 06:43:44 PM PDT 24
Peak memory 200428 kb
Host smart-c71cb3c1-7fba-4018-ab0c-e8a6d921142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278077948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3278077948
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.660258437
Short name T172
Test name
Test status
Simulation time 110365800 ps
CPU time 1.03 seconds
Started Jul 11 06:43:35 PM PDT 24
Finished Jul 11 06:43:38 PM PDT 24
Peak memory 200168 kb
Host smart-1998091c-e544-4454-a33f-96200ce1be1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660258437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.660258437
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2008587455
Short name T147
Test name
Test status
Simulation time 124819505 ps
CPU time 1.19 seconds
Started Jul 11 06:43:39 PM PDT 24
Finished Jul 11 06:43:41 PM PDT 24
Peak memory 200320 kb
Host smart-f45a4e5b-f4ec-4900-9d85-27d3e42fa46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008587455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2008587455
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3980331047
Short name T410
Test name
Test status
Simulation time 5159287628 ps
CPU time 23.03 seconds
Started Jul 11 06:43:35 PM PDT 24
Finished Jul 11 06:43:59 PM PDT 24
Peak memory 200496 kb
Host smart-cb7567f4-198f-4c89-8901-c5527cdffe07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980331047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3980331047
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.206782991
Short name T262
Test name
Test status
Simulation time 145780047 ps
CPU time 1.81 seconds
Started Jul 11 06:43:36 PM PDT 24
Finished Jul 11 06:43:40 PM PDT 24
Peak memory 200188 kb
Host smart-6f6703e0-4c6e-4426-86db-46306ea47bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206782991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.206782991
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1656443388
Short name T7
Test name
Test status
Simulation time 232948092 ps
CPU time 1.29 seconds
Started Jul 11 06:43:37 PM PDT 24
Finished Jul 11 06:43:40 PM PDT 24
Peak memory 200164 kb
Host smart-e54d4446-dfaa-4579-a0ed-ef736a5a32e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656443388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1656443388
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3021046792
Short name T149
Test name
Test status
Simulation time 76493890 ps
CPU time 0.82 seconds
Started Jul 11 06:43:40 PM PDT 24
Finished Jul 11 06:43:41 PM PDT 24
Peak memory 199956 kb
Host smart-6c9d7647-e98a-43bb-83bc-7d6f71b25d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021046792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3021046792
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2206978277
Short name T387
Test name
Test status
Simulation time 1225337249 ps
CPU time 6 seconds
Started Jul 11 06:43:42 PM PDT 24
Finished Jul 11 06:43:49 PM PDT 24
Peak memory 221712 kb
Host smart-931f7304-1b0f-4ad1-a04b-f140f2e1bb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206978277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2206978277
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1805078950
Short name T52
Test name
Test status
Simulation time 243823059 ps
CPU time 1.09 seconds
Started Jul 11 06:43:42 PM PDT 24
Finished Jul 11 06:43:44 PM PDT 24
Peak memory 217472 kb
Host smart-41585d5c-f32a-4b0b-a79e-4721c40850a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805078950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1805078950
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1326569601
Short name T531
Test name
Test status
Simulation time 104819952 ps
CPU time 0.78 seconds
Started Jul 11 06:43:37 PM PDT 24
Finished Jul 11 06:43:40 PM PDT 24
Peak memory 199944 kb
Host smart-8648124f-4b73-4339-b047-0b6a33174754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326569601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1326569601
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3818041781
Short name T407
Test name
Test status
Simulation time 1561453911 ps
CPU time 6.42 seconds
Started Jul 11 06:43:38 PM PDT 24
Finished Jul 11 06:43:46 PM PDT 24
Peak memory 200604 kb
Host smart-8b0ef81f-67d5-4127-8b74-ef307162071f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818041781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3818041781
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.166522851
Short name T490
Test name
Test status
Simulation time 165916887 ps
CPU time 1.22 seconds
Started Jul 11 06:43:36 PM PDT 24
Finished Jul 11 06:43:39 PM PDT 24
Peak memory 200176 kb
Host smart-436b3a46-2773-4fcb-b1ea-63299d730943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166522851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.166522851
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2331323388
Short name T216
Test name
Test status
Simulation time 247856389 ps
CPU time 1.65 seconds
Started Jul 11 06:49:09 PM PDT 24
Finished Jul 11 06:49:12 PM PDT 24
Peak memory 200324 kb
Host smart-a23c9d44-8194-42d5-a68a-9f9eba703367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331323388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2331323388
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1315826172
Short name T131
Test name
Test status
Simulation time 4048892136 ps
CPU time 14.34 seconds
Started Jul 11 06:43:42 PM PDT 24
Finished Jul 11 06:43:57 PM PDT 24
Peak memory 200492 kb
Host smart-1ebe444b-9203-4697-a947-dcc6eed47af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315826172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1315826172
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1522739501
Short name T242
Test name
Test status
Simulation time 120954954 ps
CPU time 1.49 seconds
Started Jul 11 06:43:37 PM PDT 24
Finished Jul 11 06:43:40 PM PDT 24
Peak memory 200076 kb
Host smart-199722d9-d91a-4552-89d3-45bcb4451a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522739501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1522739501
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2287629227
Short name T322
Test name
Test status
Simulation time 164163621 ps
CPU time 1.15 seconds
Started Jul 11 06:43:36 PM PDT 24
Finished Jul 11 06:43:39 PM PDT 24
Peak memory 200176 kb
Host smart-be17379b-b144-41d4-92ed-4d88ed0c14e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287629227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2287629227
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.4272837396
Short name T142
Test name
Test status
Simulation time 57456529 ps
CPU time 0.73 seconds
Started Jul 11 06:43:47 PM PDT 24
Finished Jul 11 06:43:49 PM PDT 24
Peak memory 199968 kb
Host smart-42bd7243-5d2b-487e-acbb-52567efa56de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272837396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.4272837396
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2728503500
Short name T27
Test name
Test status
Simulation time 1901717623 ps
CPU time 7.34 seconds
Started Jul 11 06:43:42 PM PDT 24
Finished Jul 11 06:43:50 PM PDT 24
Peak memory 221684 kb
Host smart-d6c836c6-ea92-4ac8-9f37-be48718ad842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728503500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2728503500
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3278129223
Short name T181
Test name
Test status
Simulation time 244114083 ps
CPU time 1.11 seconds
Started Jul 11 06:43:46 PM PDT 24
Finished Jul 11 06:43:48 PM PDT 24
Peak memory 217568 kb
Host smart-7d2c7bd3-a5d2-4c73-9d55-f9030fd75dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278129223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3278129223
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3320990550
Short name T14
Test name
Test status
Simulation time 182198533 ps
CPU time 0.96 seconds
Started Jul 11 06:43:40 PM PDT 24
Finished Jul 11 06:43:42 PM PDT 24
Peak memory 199992 kb
Host smart-bc291315-00f4-4a57-9a47-b0c5b0229777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320990550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3320990550
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1202028077
Short name T526
Test name
Test status
Simulation time 1877304889 ps
CPU time 7.49 seconds
Started Jul 11 06:43:41 PM PDT 24
Finished Jul 11 06:43:49 PM PDT 24
Peak memory 200396 kb
Host smart-7b2ddec3-9a62-4bdc-a658-51fa29adc967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202028077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1202028077
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.31660801
Short name T79
Test name
Test status
Simulation time 170366651 ps
CPU time 1.3 seconds
Started Jul 11 06:43:47 PM PDT 24
Finished Jul 11 06:43:50 PM PDT 24
Peak memory 200092 kb
Host smart-48901a43-23d6-45cb-a0c0-66ce3a605fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31660801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.31660801
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.30194618
Short name T451
Test name
Test status
Simulation time 197607737 ps
CPU time 1.42 seconds
Started Jul 11 06:43:41 PM PDT 24
Finished Jul 11 06:43:43 PM PDT 24
Peak memory 200392 kb
Host smart-a4ee81e4-2523-488a-9076-f6264ad2aef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30194618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.30194618
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2339891138
Short name T106
Test name
Test status
Simulation time 5509664704 ps
CPU time 25.48 seconds
Started Jul 11 06:43:49 PM PDT 24
Finished Jul 11 06:44:17 PM PDT 24
Peak memory 208692 kb
Host smart-d15aa213-f4d5-44a4-9c82-fa12c8d26b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339891138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2339891138
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.948778087
Short name T36
Test name
Test status
Simulation time 362745853 ps
CPU time 2.31 seconds
Started Jul 11 06:43:42 PM PDT 24
Finished Jul 11 06:43:46 PM PDT 24
Peak memory 200160 kb
Host smart-bc5bcd2e-91ee-488c-ad0b-cd08d58f3ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948778087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.948778087
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2263557400
Short name T437
Test name
Test status
Simulation time 277861825 ps
CPU time 1.72 seconds
Started Jul 11 06:43:42 PM PDT 24
Finished Jul 11 06:43:45 PM PDT 24
Peak memory 200120 kb
Host smart-44bb7c79-e696-4ad3-b4ce-9d8f00a82d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263557400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2263557400
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1225280036
Short name T226
Test name
Test status
Simulation time 111285127 ps
CPU time 0.84 seconds
Started Jul 11 06:42:08 PM PDT 24
Finished Jul 11 06:42:10 PM PDT 24
Peak memory 199928 kb
Host smart-b4df2e2a-b730-4492-82e8-89f60abfe424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225280036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1225280036
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3004229227
Short name T409
Test name
Test status
Simulation time 2372338939 ps
CPU time 8.63 seconds
Started Jul 11 06:42:05 PM PDT 24
Finished Jul 11 06:42:15 PM PDT 24
Peak memory 217200 kb
Host smart-c63d3b68-95e6-4fe5-abc3-e279c8d1ec62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004229227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3004229227
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2237792599
Short name T439
Test name
Test status
Simulation time 244069276 ps
CPU time 1.08 seconds
Started Jul 11 06:42:05 PM PDT 24
Finished Jul 11 06:42:08 PM PDT 24
Peak memory 217552 kb
Host smart-7e5b9aea-ffd5-4818-ac59-48b9ad17e6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237792599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2237792599
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1740911349
Short name T371
Test name
Test status
Simulation time 113948728 ps
CPU time 0.78 seconds
Started Jul 11 06:42:06 PM PDT 24
Finished Jul 11 06:42:09 PM PDT 24
Peak memory 199988 kb
Host smart-a2d92bfa-53d9-4d92-bbf2-09d44426e65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740911349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1740911349
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2033227843
Short name T101
Test name
Test status
Simulation time 2151298525 ps
CPU time 7.3 seconds
Started Jul 11 06:42:08 PM PDT 24
Finished Jul 11 06:42:17 PM PDT 24
Peak memory 200452 kb
Host smart-31eb21cb-a21a-4b81-85f3-4b7b0cd26b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033227843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2033227843
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.159428240
Short name T69
Test name
Test status
Simulation time 16510198809 ps
CPU time 31.11 seconds
Started Jul 11 06:42:07 PM PDT 24
Finished Jul 11 06:42:39 PM PDT 24
Peak memory 217280 kb
Host smart-089dbf5a-786b-4511-bb77-60d9d2034a94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159428240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.159428240
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.4272600300
Short name T253
Test name
Test status
Simulation time 165480514 ps
CPU time 1.25 seconds
Started Jul 11 06:42:07 PM PDT 24
Finished Jul 11 06:42:09 PM PDT 24
Peak memory 200256 kb
Host smart-95b4a08a-bb14-4f02-8536-b90b76b9210c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272600300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.4272600300
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3686915766
Short name T400
Test name
Test status
Simulation time 238901855 ps
CPU time 1.62 seconds
Started Jul 11 06:42:01 PM PDT 24
Finished Jul 11 06:42:03 PM PDT 24
Peak memory 200376 kb
Host smart-ee6ddbe0-ef19-4e24-8d9a-4058a077793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686915766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3686915766
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.4211823204
Short name T228
Test name
Test status
Simulation time 8566720709 ps
CPU time 30.19 seconds
Started Jul 11 06:42:05 PM PDT 24
Finished Jul 11 06:42:37 PM PDT 24
Peak memory 210336 kb
Host smart-0045e0e4-0b73-4f0b-8ea2-ac93b0cc9544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211823204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.4211823204
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.183434854
Short name T432
Test name
Test status
Simulation time 425079184 ps
CPU time 2.38 seconds
Started Jul 11 06:42:04 PM PDT 24
Finished Jul 11 06:42:07 PM PDT 24
Peak memory 208408 kb
Host smart-f583e397-a748-4443-9b3b-54720fcdd3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183434854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.183434854
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.4083598597
Short name T421
Test name
Test status
Simulation time 102580417 ps
CPU time 0.99 seconds
Started Jul 11 06:42:07 PM PDT 24
Finished Jul 11 06:42:09 PM PDT 24
Peak memory 200172 kb
Host smart-7a05fc9a-72c9-4f00-9330-af0c7b8788ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083598597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.4083598597
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3510010112
Short name T447
Test name
Test status
Simulation time 74404623 ps
CPU time 0.82 seconds
Started Jul 11 06:43:46 PM PDT 24
Finished Jul 11 06:43:48 PM PDT 24
Peak memory 199964 kb
Host smart-108acff4-8a78-426b-aa75-d5c86fa3d4c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510010112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3510010112
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.159802224
Short name T515
Test name
Test status
Simulation time 1881179135 ps
CPU time 7.05 seconds
Started Jul 11 06:43:47 PM PDT 24
Finished Jul 11 06:43:56 PM PDT 24
Peak memory 217612 kb
Host smart-afd842d0-496e-4f91-8bc9-99547192d8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159802224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.159802224
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2956180593
Short name T539
Test name
Test status
Simulation time 243749030 ps
CPU time 1.18 seconds
Started Jul 11 06:43:45 PM PDT 24
Finished Jul 11 06:43:47 PM PDT 24
Peak memory 217548 kb
Host smart-541b12ab-4f4f-44dd-b904-9138a3b78b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956180593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2956180593
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3765774074
Short name T20
Test name
Test status
Simulation time 126659962 ps
CPU time 0.85 seconds
Started Jul 11 06:43:46 PM PDT 24
Finished Jul 11 06:43:48 PM PDT 24
Peak memory 200000 kb
Host smart-9fb4884c-fbd2-4849-9c69-97c23c8abb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765774074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3765774074
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.458039901
Short name T266
Test name
Test status
Simulation time 1685957532 ps
CPU time 5.93 seconds
Started Jul 11 06:43:45 PM PDT 24
Finished Jul 11 06:43:52 PM PDT 24
Peak memory 200456 kb
Host smart-910c3455-b111-4078-bf9d-529aeaccf5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458039901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.458039901
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.4194090709
Short name T259
Test name
Test status
Simulation time 112115767 ps
CPU time 1.05 seconds
Started Jul 11 06:43:46 PM PDT 24
Finished Jul 11 06:43:48 PM PDT 24
Peak memory 200172 kb
Host smart-e7f797f8-e4da-4d7a-84b0-0712c5e5fd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194090709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.4194090709
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3895838083
Short name T372
Test name
Test status
Simulation time 185993928 ps
CPU time 1.37 seconds
Started Jul 11 06:43:47 PM PDT 24
Finished Jul 11 06:43:50 PM PDT 24
Peak memory 200360 kb
Host smart-af80759f-edf2-4b99-b456-a3c7a71cc3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895838083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3895838083
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.4140054889
Short name T287
Test name
Test status
Simulation time 11715701981 ps
CPU time 39.72 seconds
Started Jul 11 06:43:49 PM PDT 24
Finished Jul 11 06:44:31 PM PDT 24
Peak memory 208688 kb
Host smart-4b079d0e-1b7f-42ea-b622-d99f105855ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140054889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.4140054889
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1815650892
Short name T133
Test name
Test status
Simulation time 394165727 ps
CPU time 2.32 seconds
Started Jul 11 06:43:46 PM PDT 24
Finished Jul 11 06:43:49 PM PDT 24
Peak memory 200132 kb
Host smart-cc06843b-b072-476c-a433-0e95d7f1b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815650892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1815650892
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.269326854
Short name T376
Test name
Test status
Simulation time 191732010 ps
CPU time 1.27 seconds
Started Jul 11 06:43:47 PM PDT 24
Finished Jul 11 06:43:50 PM PDT 24
Peak memory 200176 kb
Host smart-b28146bc-9fa9-4180-a119-58b445c301f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269326854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.269326854
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.534785892
Short name T2
Test name
Test status
Simulation time 70656123 ps
CPU time 0.77 seconds
Started Jul 11 06:43:49 PM PDT 24
Finished Jul 11 06:43:53 PM PDT 24
Peak memory 199960 kb
Host smart-05eaaa9e-ad01-48bc-8e51-4c0f117c1f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534785892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.534785892
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2050471093
Short name T29
Test name
Test status
Simulation time 2351596823 ps
CPU time 9.05 seconds
Started Jul 11 06:43:49 PM PDT 24
Finished Jul 11 06:44:00 PM PDT 24
Peak memory 217904 kb
Host smart-20e00967-d2c3-4132-b41f-488df5a914b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050471093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2050471093
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.978706980
Short name T217
Test name
Test status
Simulation time 244238274 ps
CPU time 1.09 seconds
Started Jul 11 06:43:48 PM PDT 24
Finished Jul 11 06:43:50 PM PDT 24
Peak memory 217536 kb
Host smart-b36d6bca-4e65-4b64-9f7e-a90c047ba143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978706980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.978706980
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.786407293
Short name T229
Test name
Test status
Simulation time 161988285 ps
CPU time 0.84 seconds
Started Jul 11 06:43:48 PM PDT 24
Finished Jul 11 06:43:50 PM PDT 24
Peak memory 200184 kb
Host smart-2ffab5cc-dcb4-4887-8825-4798652b368f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786407293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.786407293
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2972715624
Short name T82
Test name
Test status
Simulation time 859369280 ps
CPU time 4.69 seconds
Started Jul 11 06:43:46 PM PDT 24
Finished Jul 11 06:43:51 PM PDT 24
Peak memory 200452 kb
Host smart-5fcb2e54-1fab-4198-8026-ba44835f861f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972715624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2972715624
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1050898282
Short name T140
Test name
Test status
Simulation time 98240531 ps
CPU time 0.97 seconds
Started Jul 11 06:43:49 PM PDT 24
Finished Jul 11 06:43:53 PM PDT 24
Peak memory 200172 kb
Host smart-03b710b4-54e5-47e9-b993-374ac87ebc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050898282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1050898282
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2430849528
Short name T413
Test name
Test status
Simulation time 106077785 ps
CPU time 1.21 seconds
Started Jul 11 06:43:47 PM PDT 24
Finished Jul 11 06:43:49 PM PDT 24
Peak memory 200420 kb
Host smart-27aa428e-31c2-4298-bccb-a9bf12aff01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430849528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2430849528
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2878309877
Short name T100
Test name
Test status
Simulation time 5574285917 ps
CPU time 24.59 seconds
Started Jul 11 06:43:56 PM PDT 24
Finished Jul 11 06:44:23 PM PDT 24
Peak memory 208648 kb
Host smart-52626cb3-af13-4777-850f-74dbc60d0156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878309877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2878309877
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3630895931
Short name T476
Test name
Test status
Simulation time 128695759 ps
CPU time 1.67 seconds
Started Jul 11 06:43:46 PM PDT 24
Finished Jul 11 06:43:50 PM PDT 24
Peak memory 208404 kb
Host smart-48376047-8117-40d3-8533-4d717823bcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630895931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3630895931
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2748857172
Short name T180
Test name
Test status
Simulation time 78035170 ps
CPU time 0.88 seconds
Started Jul 11 06:43:48 PM PDT 24
Finished Jul 11 06:43:50 PM PDT 24
Peak memory 200376 kb
Host smart-4ffac0f3-3e03-438c-890a-57ff555b99c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748857172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2748857172
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3169439486
Short name T261
Test name
Test status
Simulation time 57903058 ps
CPU time 0.73 seconds
Started Jul 11 06:43:50 PM PDT 24
Finished Jul 11 06:43:54 PM PDT 24
Peak memory 199960 kb
Host smart-d538ad55-8ea4-456e-80b7-9fab5456dbe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169439486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3169439486
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3450443654
Short name T45
Test name
Test status
Simulation time 1230756411 ps
CPU time 5.59 seconds
Started Jul 11 06:43:53 PM PDT 24
Finished Jul 11 06:44:00 PM PDT 24
Peak memory 217756 kb
Host smart-d5e36bff-1597-4987-bbde-327ce04836b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450443654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3450443654
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2761195828
Short name T396
Test name
Test status
Simulation time 244571356 ps
CPU time 1.07 seconds
Started Jul 11 06:43:52 PM PDT 24
Finished Jul 11 06:43:55 PM PDT 24
Peak memory 217464 kb
Host smart-4309f0cc-d475-4a20-a6a9-ed4cf91abc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761195828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2761195828
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2542923725
Short name T398
Test name
Test status
Simulation time 157319843 ps
CPU time 0.85 seconds
Started Jul 11 06:43:51 PM PDT 24
Finished Jul 11 06:43:55 PM PDT 24
Peak memory 200004 kb
Host smart-615e699a-b481-4690-84c2-909c69a0efd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542923725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2542923725
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1460646190
Short name T395
Test name
Test status
Simulation time 1150788446 ps
CPU time 4.91 seconds
Started Jul 11 06:43:51 PM PDT 24
Finished Jul 11 06:43:59 PM PDT 24
Peak memory 200476 kb
Host smart-91ba2386-dbd8-464e-a40a-94dd1e530f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460646190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1460646190
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2677117755
Short name T171
Test name
Test status
Simulation time 108487592 ps
CPU time 1.04 seconds
Started Jul 11 06:43:55 PM PDT 24
Finished Jul 11 06:43:59 PM PDT 24
Peak memory 200176 kb
Host smart-1baeefa0-7d89-4b1d-b565-4567b5bcef90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677117755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2677117755
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2258456776
Short name T339
Test name
Test status
Simulation time 231112649 ps
CPU time 1.74 seconds
Started Jul 11 06:43:50 PM PDT 24
Finished Jul 11 06:43:55 PM PDT 24
Peak memory 200376 kb
Host smart-1ac75c95-9079-413f-95f6-faa8b05ae1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258456776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2258456776
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.309483499
Short name T284
Test name
Test status
Simulation time 3856053567 ps
CPU time 16.99 seconds
Started Jul 11 06:43:57 PM PDT 24
Finished Jul 11 06:44:16 PM PDT 24
Peak memory 208600 kb
Host smart-9e022ba6-d767-43f3-9683-241a3b818345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309483499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.309483499
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1327206997
Short name T267
Test name
Test status
Simulation time 454993369 ps
CPU time 2.86 seconds
Started Jul 11 06:43:49 PM PDT 24
Finished Jul 11 06:43:55 PM PDT 24
Peak memory 200128 kb
Host smart-2ca3d605-836d-4a44-aec5-dab4f251ed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327206997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1327206997
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.4084594010
Short name T507
Test name
Test status
Simulation time 249201254 ps
CPU time 1.44 seconds
Started Jul 11 06:43:51 PM PDT 24
Finished Jul 11 06:43:56 PM PDT 24
Peak memory 200384 kb
Host smart-ecb11f49-18ab-4311-8fe7-8efb7d42bb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084594010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4084594010
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3280779820
Short name T512
Test name
Test status
Simulation time 53907907 ps
CPU time 0.71 seconds
Started Jul 11 06:43:51 PM PDT 24
Finished Jul 11 06:43:54 PM PDT 24
Peak memory 199964 kb
Host smart-750ca532-8898-4fe5-9bb3-82361d106dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280779820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3280779820
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2520383327
Short name T485
Test name
Test status
Simulation time 1234924773 ps
CPU time 6.24 seconds
Started Jul 11 06:43:51 PM PDT 24
Finished Jul 11 06:44:00 PM PDT 24
Peak memory 217548 kb
Host smart-76fca224-51e0-40db-aacd-3bd6b3e6d66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520383327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2520383327
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.731198634
Short name T335
Test name
Test status
Simulation time 244405895 ps
CPU time 1.15 seconds
Started Jul 11 06:43:51 PM PDT 24
Finished Jul 11 06:43:55 PM PDT 24
Peak memory 217496 kb
Host smart-cb80c10e-85b2-4f50-a205-484e452abe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731198634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.731198634
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3752097020
Short name T508
Test name
Test status
Simulation time 72735973 ps
CPU time 0.73 seconds
Started Jul 11 06:43:50 PM PDT 24
Finished Jul 11 06:43:54 PM PDT 24
Peak memory 199972 kb
Host smart-6d01acf6-6087-4246-aa83-b2b681554bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752097020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3752097020
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2273191370
Short name T311
Test name
Test status
Simulation time 1526916089 ps
CPU time 6.17 seconds
Started Jul 11 06:43:55 PM PDT 24
Finished Jul 11 06:44:03 PM PDT 24
Peak memory 200428 kb
Host smart-00c102c8-dab9-4eda-9fee-fd93389c621e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273191370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2273191370
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.369538960
Short name T239
Test name
Test status
Simulation time 110456107 ps
CPU time 1.04 seconds
Started Jul 11 06:43:56 PM PDT 24
Finished Jul 11 06:43:59 PM PDT 24
Peak memory 200180 kb
Host smart-06945dbd-25d9-4d5b-a31e-a98ec985b054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369538960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.369538960
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2887198807
Short name T367
Test name
Test status
Simulation time 196948974 ps
CPU time 1.33 seconds
Started Jul 11 06:43:57 PM PDT 24
Finished Jul 11 06:44:00 PM PDT 24
Peak memory 200272 kb
Host smart-aca07881-328b-4e35-a554-b3714b0b82fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887198807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2887198807
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.4209350315
Short name T505
Test name
Test status
Simulation time 4360315738 ps
CPU time 18.63 seconds
Started Jul 11 06:43:54 PM PDT 24
Finished Jul 11 06:44:14 PM PDT 24
Peak memory 216884 kb
Host smart-3ba8433a-5e12-4789-8d1f-1aeb50a6f283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209350315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.4209350315
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.130060915
Short name T143
Test name
Test status
Simulation time 119865218 ps
CPU time 1.46 seconds
Started Jul 11 06:43:52 PM PDT 24
Finished Jul 11 06:43:56 PM PDT 24
Peak memory 200168 kb
Host smart-277b5823-7146-4eeb-8f57-7bde27ddc691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130060915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.130060915
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3266831267
Short name T155
Test name
Test status
Simulation time 242497481 ps
CPU time 1.55 seconds
Started Jul 11 06:43:56 PM PDT 24
Finished Jul 11 06:43:59 PM PDT 24
Peak memory 200384 kb
Host smart-58dba332-1e51-4ab3-acd2-b213fe900feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266831267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3266831267
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1660031452
Short name T469
Test name
Test status
Simulation time 66609686 ps
CPU time 0.74 seconds
Started Jul 11 06:43:55 PM PDT 24
Finished Jul 11 06:43:57 PM PDT 24
Peak memory 199968 kb
Host smart-708aa4de-c1aa-4cee-bbca-cd6b3ce132a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660031452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1660031452
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.4147667516
Short name T56
Test name
Test status
Simulation time 1219995596 ps
CPU time 6.28 seconds
Started Jul 11 06:43:52 PM PDT 24
Finished Jul 11 06:44:01 PM PDT 24
Peak memory 217776 kb
Host smart-d8043b48-1b75-4d96-975e-30f6c0011fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147667516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.4147667516
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3846240282
Short name T533
Test name
Test status
Simulation time 243775786 ps
CPU time 1.1 seconds
Started Jul 11 06:43:49 PM PDT 24
Finished Jul 11 06:43:53 PM PDT 24
Peak memory 217532 kb
Host smart-609b2e03-6b7d-4824-9324-ea47a8a59334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846240282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3846240282
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.813657296
Short name T523
Test name
Test status
Simulation time 162863209 ps
CPU time 0.86 seconds
Started Jul 11 06:43:51 PM PDT 24
Finished Jul 11 06:43:54 PM PDT 24
Peak memory 199968 kb
Host smart-331fa0ac-20a3-4606-be7f-4beddcac2391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813657296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.813657296
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2626514100
Short name T453
Test name
Test status
Simulation time 2109123293 ps
CPU time 8.57 seconds
Started Jul 11 06:43:57 PM PDT 24
Finished Jul 11 06:44:08 PM PDT 24
Peak memory 200340 kb
Host smart-df9bb45e-7524-4ed6-81e4-9eef2a7e3ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626514100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2626514100
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1587568295
Short name T204
Test name
Test status
Simulation time 141278399 ps
CPU time 1.13 seconds
Started Jul 11 06:43:52 PM PDT 24
Finished Jul 11 06:43:56 PM PDT 24
Peak memory 200180 kb
Host smart-fecf53b9-5c4d-4103-a6fe-67fb267186d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587568295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1587568295
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.4141747763
Short name T215
Test name
Test status
Simulation time 111361373 ps
CPU time 1.16 seconds
Started Jul 11 06:43:55 PM PDT 24
Finished Jul 11 06:43:58 PM PDT 24
Peak memory 200364 kb
Host smart-96c81e09-3a5f-4983-9297-6a8ed1bc1ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141747763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.4141747763
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2809761970
Short name T332
Test name
Test status
Simulation time 5342576471 ps
CPU time 23.12 seconds
Started Jul 11 06:43:53 PM PDT 24
Finished Jul 11 06:44:18 PM PDT 24
Peak memory 216672 kb
Host smart-23e6bc12-06ac-4266-af40-1d236ce86e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809761970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2809761970
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.854651644
Short name T89
Test name
Test status
Simulation time 412582222 ps
CPU time 2.39 seconds
Started Jul 11 06:43:52 PM PDT 24
Finished Jul 11 06:43:57 PM PDT 24
Peak memory 208396 kb
Host smart-b710a01c-f643-4fb0-aee7-63d5e9f025b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854651644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.854651644
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.333111579
Short name T21
Test name
Test status
Simulation time 214954884 ps
CPU time 1.37 seconds
Started Jul 11 06:43:52 PM PDT 24
Finished Jul 11 06:43:56 PM PDT 24
Peak memory 200228 kb
Host smart-1f2988b7-1931-4127-8c1c-f1025ff640e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333111579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.333111579
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4031307748
Short name T495
Test name
Test status
Simulation time 81397675 ps
CPU time 0.87 seconds
Started Jul 11 06:43:55 PM PDT 24
Finished Jul 11 06:43:57 PM PDT 24
Peak memory 199868 kb
Host smart-7a67b140-cebe-4011-88c5-e8bc0e725a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031307748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4031307748
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1527950652
Short name T441
Test name
Test status
Simulation time 1886634620 ps
CPU time 8.16 seconds
Started Jul 11 06:43:55 PM PDT 24
Finished Jul 11 06:44:06 PM PDT 24
Peak memory 221776 kb
Host smart-99ca8718-cb2e-4eb3-a918-54f3c1ec839f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527950652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1527950652
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2404501673
Short name T423
Test name
Test status
Simulation time 245025392 ps
CPU time 1.03 seconds
Started Jul 11 06:43:55 PM PDT 24
Finished Jul 11 06:43:57 PM PDT 24
Peak memory 217560 kb
Host smart-b038fba6-7482-4b43-ba29-85cabab175ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404501673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2404501673
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.914211481
Short name T203
Test name
Test status
Simulation time 202981239 ps
CPU time 1 seconds
Started Jul 11 06:43:55 PM PDT 24
Finished Jul 11 06:43:58 PM PDT 24
Peak memory 199980 kb
Host smart-7c6b29d6-0190-4422-aeeb-20ca8dcb1038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914211481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.914211481
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3220452551
Short name T390
Test name
Test status
Simulation time 1177550090 ps
CPU time 5.33 seconds
Started Jul 11 06:43:56 PM PDT 24
Finished Jul 11 06:44:03 PM PDT 24
Peak memory 200420 kb
Host smart-fbb0a4ad-d2ba-4f4e-af27-68da4b0db1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220452551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3220452551
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.870756602
Short name T252
Test name
Test status
Simulation time 99996045 ps
CPU time 1 seconds
Started Jul 11 06:43:58 PM PDT 24
Finished Jul 11 06:44:01 PM PDT 24
Peak memory 200052 kb
Host smart-f137c4e2-98d3-4438-9e05-5286e9d8b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870756602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.870756602
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3561800444
Short name T392
Test name
Test status
Simulation time 113831977 ps
CPU time 1.31 seconds
Started Jul 11 06:43:57 PM PDT 24
Finished Jul 11 06:44:00 PM PDT 24
Peak memory 200372 kb
Host smart-93dc6aa0-3efc-404b-9a56-30e1115a515f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561800444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3561800444
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1746310420
Short name T359
Test name
Test status
Simulation time 5202279121 ps
CPU time 26.98 seconds
Started Jul 11 06:43:56 PM PDT 24
Finished Jul 11 06:44:25 PM PDT 24
Peak memory 208692 kb
Host smart-9eb627f9-1f8a-4b12-a01a-5829f730dc67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746310420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1746310420
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2637782250
Short name T497
Test name
Test status
Simulation time 329732219 ps
CPU time 2.31 seconds
Started Jul 11 06:43:58 PM PDT 24
Finished Jul 11 06:44:02 PM PDT 24
Peak memory 200072 kb
Host smart-aad62ca1-4fce-4b99-9e85-d291e44ba79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637782250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2637782250
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2290468901
Short name T218
Test name
Test status
Simulation time 90781443 ps
CPU time 0.88 seconds
Started Jul 11 06:43:59 PM PDT 24
Finished Jul 11 06:44:02 PM PDT 24
Peak memory 200176 kb
Host smart-09167837-1a82-4053-b194-323ed95b808d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290468901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2290468901
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1142985960
Short name T303
Test name
Test status
Simulation time 72405866 ps
CPU time 0.79 seconds
Started Jul 11 06:43:56 PM PDT 24
Finished Jul 11 06:43:59 PM PDT 24
Peak memory 199944 kb
Host smart-7fba5603-211c-4851-b773-40f670d2d3ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142985960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1142985960
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2525735623
Short name T504
Test name
Test status
Simulation time 2173764465 ps
CPU time 8.05 seconds
Started Jul 11 06:43:57 PM PDT 24
Finished Jul 11 06:44:08 PM PDT 24
Peak memory 216976 kb
Host smart-2c9e79a1-036b-4f5e-941b-97086b2c5534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525735623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2525735623
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1107797979
Short name T494
Test name
Test status
Simulation time 244856966 ps
CPU time 1.09 seconds
Started Jul 11 06:43:58 PM PDT 24
Finished Jul 11 06:44:01 PM PDT 24
Peak memory 217524 kb
Host smart-f4b86a49-d3c8-4523-b28d-22f5b23e5a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107797979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1107797979
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2039437882
Short name T275
Test name
Test status
Simulation time 153619227 ps
CPU time 0.84 seconds
Started Jul 11 06:43:56 PM PDT 24
Finished Jul 11 06:43:58 PM PDT 24
Peak memory 199972 kb
Host smart-eef73e9c-cbac-48c0-ac0b-413873d7563f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039437882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2039437882
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2699266126
Short name T305
Test name
Test status
Simulation time 2064596534 ps
CPU time 7.83 seconds
Started Jul 11 06:43:57 PM PDT 24
Finished Jul 11 06:44:07 PM PDT 24
Peak memory 200432 kb
Host smart-8908719f-5683-4dd8-8237-40c233d7b63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699266126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2699266126
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.954700166
Short name T250
Test name
Test status
Simulation time 117277600 ps
CPU time 1.05 seconds
Started Jul 11 06:43:56 PM PDT 24
Finished Jul 11 06:43:59 PM PDT 24
Peak memory 200176 kb
Host smart-f998882a-64df-421e-be30-08b67cfb00e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954700166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.954700166
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.784138193
Short name T465
Test name
Test status
Simulation time 108032093 ps
CPU time 1.16 seconds
Started Jul 11 06:43:56 PM PDT 24
Finished Jul 11 06:43:59 PM PDT 24
Peak memory 200364 kb
Host smart-7959f612-9db3-4d8e-9fb9-6bd267b2fbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784138193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.784138193
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1052316164
Short name T375
Test name
Test status
Simulation time 6230372041 ps
CPU time 23.35 seconds
Started Jul 11 06:43:58 PM PDT 24
Finished Jul 11 06:44:24 PM PDT 24
Peak memory 200452 kb
Host smart-64a5053d-40c1-4e23-b89f-97ad6794d8c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052316164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1052316164
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1341645274
Short name T236
Test name
Test status
Simulation time 140530266 ps
CPU time 1.82 seconds
Started Jul 11 06:43:55 PM PDT 24
Finished Jul 11 06:43:59 PM PDT 24
Peak memory 200156 kb
Host smart-44ae9393-f96e-42f1-b131-960b6956adb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341645274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1341645274
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3405612731
Short name T38
Test name
Test status
Simulation time 176067078 ps
CPU time 1.31 seconds
Started Jul 11 06:43:59 PM PDT 24
Finished Jul 11 06:44:02 PM PDT 24
Peak memory 200380 kb
Host smart-9925e782-6fa2-481b-aa7b-792c55e218e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405612731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3405612731
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1295212565
Short name T50
Test name
Test status
Simulation time 61361038 ps
CPU time 0.85 seconds
Started Jul 11 06:44:00 PM PDT 24
Finished Jul 11 06:44:02 PM PDT 24
Peak memory 199948 kb
Host smart-95500fe0-b564-458c-9858-a6e726367f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295212565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1295212565
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1474647167
Short name T338
Test name
Test status
Simulation time 1895382786 ps
CPU time 7.92 seconds
Started Jul 11 06:44:03 PM PDT 24
Finished Jul 11 06:44:13 PM PDT 24
Peak memory 217472 kb
Host smart-6e548517-ba47-4200-8a04-f1aeff9604db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474647167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1474647167
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.31017062
Short name T412
Test name
Test status
Simulation time 244824026 ps
CPU time 1.15 seconds
Started Jul 11 06:44:00 PM PDT 24
Finished Jul 11 06:44:03 PM PDT 24
Peak memory 217532 kb
Host smart-fa9668a2-f8b8-442a-ab14-f5f1ef14d88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31017062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.31017062
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1148069397
Short name T18
Test name
Test status
Simulation time 139071242 ps
CPU time 0.81 seconds
Started Jul 11 06:44:00 PM PDT 24
Finished Jul 11 06:44:02 PM PDT 24
Peak memory 199944 kb
Host smart-db1bff00-db3b-4c22-ba6a-732daeb81346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148069397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1148069397
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1924592491
Short name T304
Test name
Test status
Simulation time 846165296 ps
CPU time 5.18 seconds
Started Jul 11 06:44:03 PM PDT 24
Finished Jul 11 06:44:10 PM PDT 24
Peak memory 200380 kb
Host smart-9c3be271-d695-4f2e-ae19-883008cd34d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924592491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1924592491
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3295871229
Short name T223
Test name
Test status
Simulation time 146565496 ps
CPU time 1.1 seconds
Started Jul 11 06:44:00 PM PDT 24
Finished Jul 11 06:44:02 PM PDT 24
Peak memory 200192 kb
Host smart-811de4cf-34dd-430f-9c9b-256ac92a1b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295871229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3295871229
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1099446672
Short name T391
Test name
Test status
Simulation time 106499333 ps
CPU time 1.23 seconds
Started Jul 11 06:44:03 PM PDT 24
Finished Jul 11 06:44:05 PM PDT 24
Peak memory 200296 kb
Host smart-fc396a67-168e-4f4f-8865-3d2f0bf9c298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099446672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1099446672
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2525971267
Short name T509
Test name
Test status
Simulation time 3853852822 ps
CPU time 16.99 seconds
Started Jul 11 06:43:59 PM PDT 24
Finished Jul 11 06:44:18 PM PDT 24
Peak memory 200500 kb
Host smart-0a405408-3caf-4a58-b29b-94bdd085a85f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525971267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2525971267
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2992763807
Short name T93
Test name
Test status
Simulation time 547745493 ps
CPU time 3.04 seconds
Started Jul 11 06:44:02 PM PDT 24
Finished Jul 11 06:44:06 PM PDT 24
Peak memory 200152 kb
Host smart-ad3d77a1-e103-4b0f-9f66-8cf76e20651e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992763807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2992763807
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3804845995
Short name T146
Test name
Test status
Simulation time 165207748 ps
CPU time 1.39 seconds
Started Jul 11 06:44:03 PM PDT 24
Finished Jul 11 06:44:05 PM PDT 24
Peak memory 200580 kb
Host smart-fd324917-a3ad-414e-b759-0c42782d3bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804845995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3804845995
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3133094566
Short name T222
Test name
Test status
Simulation time 85115579 ps
CPU time 0.83 seconds
Started Jul 11 06:43:59 PM PDT 24
Finished Jul 11 06:44:02 PM PDT 24
Peak memory 199956 kb
Host smart-2f837b44-d1e3-4e07-90aa-0c7eeea9c1a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133094566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3133094566
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2089939385
Short name T26
Test name
Test status
Simulation time 2360553331 ps
CPU time 8.61 seconds
Started Jul 11 06:44:02 PM PDT 24
Finished Jul 11 06:44:12 PM PDT 24
Peak memory 217852 kb
Host smart-e03803e4-182f-4910-ab38-5be26b27c192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089939385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2089939385
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1957615367
Short name T320
Test name
Test status
Simulation time 244291984 ps
CPU time 1.17 seconds
Started Jul 11 06:44:06 PM PDT 24
Finished Jul 11 06:44:09 PM PDT 24
Peak memory 217448 kb
Host smart-fda5eec4-83ea-4fa7-a557-f7331e30290f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957615367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1957615367
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2539459181
Short name T19
Test name
Test status
Simulation time 190401143 ps
CPU time 0.88 seconds
Started Jul 11 06:44:02 PM PDT 24
Finished Jul 11 06:44:04 PM PDT 24
Peak memory 199952 kb
Host smart-721cf7a2-fff6-4a35-82da-1980ff33eacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539459181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2539459181
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.249546057
Short name T406
Test name
Test status
Simulation time 754196102 ps
CPU time 4.25 seconds
Started Jul 11 06:44:03 PM PDT 24
Finished Jul 11 06:44:08 PM PDT 24
Peak memory 200404 kb
Host smart-83f241df-fff4-428e-8937-bc9bbc9ed8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249546057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.249546057
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3630882027
Short name T151
Test name
Test status
Simulation time 168991234 ps
CPU time 1.24 seconds
Started Jul 11 06:44:04 PM PDT 24
Finished Jul 11 06:44:07 PM PDT 24
Peak memory 200160 kb
Host smart-b4a7aae7-60a6-4ed7-827c-c0b35b9825c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630882027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3630882027
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3891810418
Short name T434
Test name
Test status
Simulation time 117245236 ps
CPU time 1.19 seconds
Started Jul 11 06:44:00 PM PDT 24
Finished Jul 11 06:44:02 PM PDT 24
Peak memory 200384 kb
Host smart-c69d0feb-a4a4-4e42-8306-fbad576dc77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891810418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3891810418
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2611491155
Short name T76
Test name
Test status
Simulation time 1002332258 ps
CPU time 4.99 seconds
Started Jul 11 06:44:00 PM PDT 24
Finished Jul 11 06:44:07 PM PDT 24
Peak memory 208628 kb
Host smart-bb2df930-8045-41cc-a7b8-49fe3f6d4902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611491155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2611491155
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2449747148
Short name T510
Test name
Test status
Simulation time 438119823 ps
CPU time 2.36 seconds
Started Jul 11 06:44:00 PM PDT 24
Finished Jul 11 06:44:04 PM PDT 24
Peak memory 208364 kb
Host smart-af2011e9-a435-4d58-a99b-fc23f4b592ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449747148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2449747148
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.773462399
Short name T500
Test name
Test status
Simulation time 70867740 ps
CPU time 0.88 seconds
Started Jul 11 06:44:02 PM PDT 24
Finished Jul 11 06:44:04 PM PDT 24
Peak memory 200188 kb
Host smart-62fcb15b-dee1-4ade-baa1-83c32f2738bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773462399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.773462399
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.154686569
Short name T350
Test name
Test status
Simulation time 66691206 ps
CPU time 0.82 seconds
Started Jul 11 06:44:08 PM PDT 24
Finished Jul 11 06:44:09 PM PDT 24
Peak memory 199876 kb
Host smart-3e87eb5a-fcfd-47b4-b7e4-8157f981e4b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154686569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.154686569
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.4037649250
Short name T399
Test name
Test status
Simulation time 1216073811 ps
CPU time 6.03 seconds
Started Jul 11 06:44:04 PM PDT 24
Finished Jul 11 06:44:12 PM PDT 24
Peak memory 217652 kb
Host smart-3c146bd8-e173-46e8-a12f-e47bfd5ba844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037649250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.4037649250
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3849293771
Short name T294
Test name
Test status
Simulation time 244566710 ps
CPU time 1.05 seconds
Started Jul 11 06:44:09 PM PDT 24
Finished Jul 11 06:44:11 PM PDT 24
Peak memory 217464 kb
Host smart-f307f7f2-0648-46dc-a4dc-e1f7d7e20b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849293771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3849293771
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2267195007
Short name T327
Test name
Test status
Simulation time 197407436 ps
CPU time 0.89 seconds
Started Jul 11 06:44:03 PM PDT 24
Finished Jul 11 06:44:06 PM PDT 24
Peak memory 199992 kb
Host smart-8b4153bd-175a-4cf1-a976-cff5e2adf0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267195007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2267195007
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.4213443596
Short name T224
Test name
Test status
Simulation time 933785670 ps
CPU time 4.62 seconds
Started Jul 11 06:44:04 PM PDT 24
Finished Jul 11 06:44:10 PM PDT 24
Peak memory 200412 kb
Host smart-eff9720d-bc60-4baf-be74-f8b3e0b33af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213443596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.4213443596
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3381620969
Short name T263
Test name
Test status
Simulation time 104659166 ps
CPU time 1.01 seconds
Started Jul 11 06:44:03 PM PDT 24
Finished Jul 11 06:44:06 PM PDT 24
Peak memory 200180 kb
Host smart-7a2efcd8-8aec-4a22-baaa-ed6083e8a5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381620969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3381620969
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.982516776
Short name T389
Test name
Test status
Simulation time 192939700 ps
CPU time 1.41 seconds
Started Jul 11 06:43:59 PM PDT 24
Finished Jul 11 06:44:02 PM PDT 24
Peak memory 200360 kb
Host smart-45d9c4ba-02b9-401c-91a0-2d3d7a5ddfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982516776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.982516776
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2678154535
Short name T232
Test name
Test status
Simulation time 3523722938 ps
CPU time 15.83 seconds
Started Jul 11 06:44:04 PM PDT 24
Finished Jul 11 06:44:22 PM PDT 24
Peak memory 200592 kb
Host smart-be4dbba6-7119-40b6-94aa-fc6a430ea537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678154535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2678154535
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.513431706
Short name T165
Test name
Test status
Simulation time 141652993 ps
CPU time 1.87 seconds
Started Jul 11 06:44:03 PM PDT 24
Finished Jul 11 06:44:07 PM PDT 24
Peak memory 200152 kb
Host smart-7ace432d-5776-43e7-8056-0154da24bc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513431706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.513431706
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3580674702
Short name T344
Test name
Test status
Simulation time 193358900 ps
CPU time 1.28 seconds
Started Jul 11 06:44:04 PM PDT 24
Finished Jul 11 06:44:07 PM PDT 24
Peak memory 200180 kb
Host smart-5f084434-a473-4fc3-9354-9d8eb06e0a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580674702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3580674702
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2004235619
Short name T306
Test name
Test status
Simulation time 60369966 ps
CPU time 0.77 seconds
Started Jul 11 06:42:09 PM PDT 24
Finished Jul 11 06:42:11 PM PDT 24
Peak memory 199952 kb
Host smart-5393ead4-519c-428c-b03c-588a040c1511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004235619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2004235619
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3337689355
Short name T43
Test name
Test status
Simulation time 1235284874 ps
CPU time 5.48 seconds
Started Jul 11 06:42:05 PM PDT 24
Finished Jul 11 06:42:12 PM PDT 24
Peak memory 221724 kb
Host smart-6ca2f589-0d18-44dc-acf7-f5871bb54d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337689355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3337689355
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2283023290
Short name T144
Test name
Test status
Simulation time 243910800 ps
CPU time 1.05 seconds
Started Jul 11 06:42:07 PM PDT 24
Finished Jul 11 06:42:09 PM PDT 24
Peak memory 217540 kb
Host smart-ba679bc8-c9e4-43b7-bd3a-9f92ffe40449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283023290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2283023290
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3840566901
Short name T219
Test name
Test status
Simulation time 214905457 ps
CPU time 0.94 seconds
Started Jul 11 06:42:06 PM PDT 24
Finished Jul 11 06:42:08 PM PDT 24
Peak memory 199984 kb
Host smart-e27e2d6e-f34d-4272-8f98-3556093bf60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840566901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3840566901
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1990950774
Short name T249
Test name
Test status
Simulation time 1299133756 ps
CPU time 6.26 seconds
Started Jul 11 06:42:08 PM PDT 24
Finished Jul 11 06:42:16 PM PDT 24
Peak memory 200388 kb
Host smart-23b06bd6-936c-4d94-9cb7-fb52a51c247c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990950774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1990950774
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2129755143
Short name T318
Test name
Test status
Simulation time 109365821 ps
CPU time 1 seconds
Started Jul 11 06:42:05 PM PDT 24
Finished Jul 11 06:42:08 PM PDT 24
Peak memory 200176 kb
Host smart-b2dec513-d473-41d4-ad57-b71f6a05739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129755143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2129755143
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1326403080
Short name T535
Test name
Test status
Simulation time 127439713 ps
CPU time 1.21 seconds
Started Jul 11 06:42:06 PM PDT 24
Finished Jul 11 06:42:09 PM PDT 24
Peak memory 200320 kb
Host smart-505ccc99-7116-44e6-acf5-53646b8de139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326403080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1326403080
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3805123693
Short name T488
Test name
Test status
Simulation time 7497458838 ps
CPU time 25.9 seconds
Started Jul 11 06:42:11 PM PDT 24
Finished Jul 11 06:42:38 PM PDT 24
Peak memory 208644 kb
Host smart-a6ea484c-339b-4419-9f53-00943b26397f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805123693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3805123693
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.508625297
Short name T241
Test name
Test status
Simulation time 114487420 ps
CPU time 1.64 seconds
Started Jul 11 06:42:06 PM PDT 24
Finished Jul 11 06:42:09 PM PDT 24
Peak memory 200212 kb
Host smart-0010a732-c147-41c7-b3a1-743f9f1bad8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508625297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.508625297
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.4092660959
Short name T428
Test name
Test status
Simulation time 90237401 ps
CPU time 0.85 seconds
Started Jul 11 06:42:04 PM PDT 24
Finished Jul 11 06:42:06 PM PDT 24
Peak memory 200184 kb
Host smart-def80d0e-5537-4bc3-9b45-1e3a83152bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092660959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.4092660959
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3595495016
Short name T511
Test name
Test status
Simulation time 60193247 ps
CPU time 0.75 seconds
Started Jul 11 06:42:21 PM PDT 24
Finished Jul 11 06:42:23 PM PDT 24
Peak memory 199928 kb
Host smart-2e987d10-d588-463f-bfd8-b71751c74718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595495016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3595495016
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3309918716
Short name T32
Test name
Test status
Simulation time 2375082822 ps
CPU time 8.2 seconds
Started Jul 11 06:42:08 PM PDT 24
Finished Jul 11 06:42:17 PM PDT 24
Peak memory 217912 kb
Host smart-4c4a030a-76f8-490c-80f5-871a4e5c3f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309918716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3309918716
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.555816536
Short name T477
Test name
Test status
Simulation time 245373992 ps
CPU time 1.12 seconds
Started Jul 11 06:42:12 PM PDT 24
Finished Jul 11 06:42:14 PM PDT 24
Peak memory 217748 kb
Host smart-80242a35-096b-4a44-b056-a4aace9b9d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555816536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.555816536
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2690461408
Short name T323
Test name
Test status
Simulation time 163441075 ps
CPU time 0.86 seconds
Started Jul 11 06:42:09 PM PDT 24
Finished Jul 11 06:42:12 PM PDT 24
Peak memory 199988 kb
Host smart-496c83d7-2ea8-4f56-9a37-3386119156d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690461408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2690461408
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1622611521
Short name T277
Test name
Test status
Simulation time 710328233 ps
CPU time 3.95 seconds
Started Jul 11 06:42:09 PM PDT 24
Finished Jul 11 06:42:14 PM PDT 24
Peak memory 200424 kb
Host smart-9842d231-03df-4ee9-a272-11d6e371b909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622611521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1622611521
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1968454800
Short name T384
Test name
Test status
Simulation time 156080919 ps
CPU time 1.19 seconds
Started Jul 11 06:42:10 PM PDT 24
Finished Jul 11 06:42:12 PM PDT 24
Peak memory 200184 kb
Host smart-fca7f7ef-c717-465a-af0d-b7ae4168287d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968454800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1968454800
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.13275956
Short name T310
Test name
Test status
Simulation time 191707147 ps
CPU time 1.39 seconds
Started Jul 11 06:42:09 PM PDT 24
Finished Jul 11 06:42:12 PM PDT 24
Peak memory 200404 kb
Host smart-493d5d9e-4451-4f0d-81b2-1af909d04e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13275956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.13275956
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3660216235
Short name T135
Test name
Test status
Simulation time 307400809 ps
CPU time 2.04 seconds
Started Jul 11 06:42:09 PM PDT 24
Finished Jul 11 06:42:12 PM PDT 24
Peak memory 200176 kb
Host smart-85b5b913-f861-4cd4-b60d-b9c563cddb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660216235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3660216235
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1644438134
Short name T138
Test name
Test status
Simulation time 116079786 ps
CPU time 0.97 seconds
Started Jul 11 06:42:10 PM PDT 24
Finished Jul 11 06:42:12 PM PDT 24
Peak memory 200176 kb
Host smart-e27cd93e-855f-47f9-8fb0-77eba52ffba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644438134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1644438134
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.4068076451
Short name T312
Test name
Test status
Simulation time 65865507 ps
CPU time 0.83 seconds
Started Jul 11 06:42:15 PM PDT 24
Finished Jul 11 06:42:16 PM PDT 24
Peak memory 199964 kb
Host smart-fef8b81f-ba09-4af9-a356-00d05e635299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068076451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.4068076451
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1937941632
Short name T378
Test name
Test status
Simulation time 2352209415 ps
CPU time 8.76 seconds
Started Jul 11 06:42:14 PM PDT 24
Finished Jul 11 06:42:24 PM PDT 24
Peak memory 221824 kb
Host smart-760ca238-0d61-4070-b593-03e9cdf21bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937941632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1937941632
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1838293431
Short name T271
Test name
Test status
Simulation time 243939659 ps
CPU time 1.16 seconds
Started Jul 11 06:42:16 PM PDT 24
Finished Jul 11 06:42:18 PM PDT 24
Peak memory 217512 kb
Host smart-7ad00588-d507-4f65-96b2-c600ad618e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838293431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1838293431
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.216972039
Short name T12
Test name
Test status
Simulation time 226574015 ps
CPU time 1.03 seconds
Started Jul 11 06:42:20 PM PDT 24
Finished Jul 11 06:42:22 PM PDT 24
Peak memory 199944 kb
Host smart-0f0cfc35-3b08-4cb4-aeac-ddbfab262fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216972039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.216972039
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.742370555
Short name T528
Test name
Test status
Simulation time 1247341975 ps
CPU time 5.17 seconds
Started Jul 11 06:42:21 PM PDT 24
Finished Jul 11 06:42:27 PM PDT 24
Peak memory 200408 kb
Host smart-a8ab20e6-3b31-470d-8f4e-2ad96ba13e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742370555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.742370555
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2405339546
Short name T202
Test name
Test status
Simulation time 107648016 ps
CPU time 1 seconds
Started Jul 11 06:42:16 PM PDT 24
Finished Jul 11 06:42:18 PM PDT 24
Peak memory 200108 kb
Host smart-3b8f749c-938b-4999-b464-7b7f2c775234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405339546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2405339546
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1991127379
Short name T211
Test name
Test status
Simulation time 249741280 ps
CPU time 1.52 seconds
Started Jul 11 06:42:12 PM PDT 24
Finished Jul 11 06:42:14 PM PDT 24
Peak memory 200316 kb
Host smart-f3c061b9-1601-4470-aad4-d55a54b301f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991127379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1991127379
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1279736518
Short name T207
Test name
Test status
Simulation time 1723496821 ps
CPU time 6.41 seconds
Started Jul 11 06:42:14 PM PDT 24
Finished Jul 11 06:42:22 PM PDT 24
Peak memory 200428 kb
Host smart-181b79e2-b30c-4562-b504-5d43cc0ffd64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279736518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1279736518
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3794945248
Short name T377
Test name
Test status
Simulation time 131868573 ps
CPU time 1.83 seconds
Started Jul 11 06:42:13 PM PDT 24
Finished Jul 11 06:42:16 PM PDT 24
Peak memory 208572 kb
Host smart-2c03bad7-b2fb-4bc3-81ef-019ec138728e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794945248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3794945248
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.123132828
Short name T282
Test name
Test status
Simulation time 154579387 ps
CPU time 1.13 seconds
Started Jul 11 06:42:14 PM PDT 24
Finished Jul 11 06:42:16 PM PDT 24
Peak memory 200176 kb
Host smart-34661aac-5b5d-4fa9-9e52-c5c308dea6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123132828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.123132828
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2765641844
Short name T156
Test name
Test status
Simulation time 71364215 ps
CPU time 0.77 seconds
Started Jul 11 06:42:18 PM PDT 24
Finished Jul 11 06:42:20 PM PDT 24
Peak memory 199964 kb
Host smart-fa229803-be5a-4038-94e1-4d0ffecd3a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765641844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2765641844
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1300137607
Short name T484
Test name
Test status
Simulation time 2374000856 ps
CPU time 9.8 seconds
Started Jul 11 06:42:19 PM PDT 24
Finished Jul 11 06:42:30 PM PDT 24
Peak memory 218008 kb
Host smart-c0d6f272-dd28-451b-b907-9eeca6cceb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300137607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1300137607
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2825728922
Short name T293
Test name
Test status
Simulation time 246120437 ps
CPU time 1.01 seconds
Started Jul 11 06:42:21 PM PDT 24
Finished Jul 11 06:42:24 PM PDT 24
Peak memory 218308 kb
Host smart-396f38c8-e8ff-47b5-93c5-f17fc675639d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825728922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2825728922
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3270765787
Short name T191
Test name
Test status
Simulation time 113821029 ps
CPU time 0.81 seconds
Started Jul 11 06:42:18 PM PDT 24
Finished Jul 11 06:42:20 PM PDT 24
Peak memory 199972 kb
Host smart-1587832f-76b8-4aba-a9e2-cd6799f3c5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270765787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3270765787
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1366318982
Short name T46
Test name
Test status
Simulation time 1478794867 ps
CPU time 6.26 seconds
Started Jul 11 06:42:17 PM PDT 24
Finished Jul 11 06:42:24 PM PDT 24
Peak memory 200388 kb
Host smart-07289fb9-b614-4500-ad5b-5aa3b16a54f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366318982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1366318982
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.370404729
Short name T388
Test name
Test status
Simulation time 183208878 ps
CPU time 1.27 seconds
Started Jul 11 06:42:19 PM PDT 24
Finished Jul 11 06:42:21 PM PDT 24
Peak memory 200092 kb
Host smart-1df2d936-5a0e-4cfc-b031-d33ddea86754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370404729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.370404729
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2517085215
Short name T346
Test name
Test status
Simulation time 203906591 ps
CPU time 1.4 seconds
Started Jul 11 06:42:21 PM PDT 24
Finished Jul 11 06:42:24 PM PDT 24
Peak memory 200320 kb
Host smart-21d70dcc-5abf-4340-910c-46fd869c1779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517085215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2517085215
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.477013053
Short name T489
Test name
Test status
Simulation time 7180206251 ps
CPU time 29.88 seconds
Started Jul 11 06:42:18 PM PDT 24
Finished Jul 11 06:42:49 PM PDT 24
Peak memory 200484 kb
Host smart-1c4d1253-50fd-492e-8528-7350a13aec67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477013053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.477013053
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3088844207
Short name T345
Test name
Test status
Simulation time 111037115 ps
CPU time 1.47 seconds
Started Jul 11 06:42:19 PM PDT 24
Finished Jul 11 06:42:21 PM PDT 24
Peak memory 200132 kb
Host smart-a7064b33-aeab-4280-b8d7-158a5d1db665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088844207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3088844207
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.460096772
Short name T188
Test name
Test status
Simulation time 178958801 ps
CPU time 1.36 seconds
Started Jul 11 06:42:20 PM PDT 24
Finished Jul 11 06:42:23 PM PDT 24
Peak memory 200440 kb
Host smart-f610caf4-4925-4cd5-9059-dde5af799fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460096772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.460096772
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1991300886
Short name T478
Test name
Test status
Simulation time 72941424 ps
CPU time 0.81 seconds
Started Jul 11 06:42:19 PM PDT 24
Finished Jul 11 06:42:20 PM PDT 24
Peak memory 199936 kb
Host smart-06137ba6-2c3c-4e14-95af-aafd03d4eb53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991300886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1991300886
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3428021882
Short name T349
Test name
Test status
Simulation time 1874331580 ps
CPU time 7.94 seconds
Started Jul 11 06:42:17 PM PDT 24
Finished Jul 11 06:42:26 PM PDT 24
Peak memory 221720 kb
Host smart-06a04681-c689-4c0e-aa4a-4b3734b35448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428021882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3428021882
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2632029521
Short name T480
Test name
Test status
Simulation time 244872368 ps
CPU time 1.08 seconds
Started Jul 11 06:42:20 PM PDT 24
Finished Jul 11 06:42:22 PM PDT 24
Peak memory 217544 kb
Host smart-017aeaad-4bf1-453c-9c5d-944cae8b4027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632029521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2632029521
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2606323490
Short name T220
Test name
Test status
Simulation time 204490620 ps
CPU time 0.89 seconds
Started Jul 11 06:42:21 PM PDT 24
Finished Jul 11 06:42:23 PM PDT 24
Peak memory 199948 kb
Host smart-6d39d933-b13e-478d-8031-bc34ab8db57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606323490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2606323490
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3274740572
Short name T102
Test name
Test status
Simulation time 1054118759 ps
CPU time 5.37 seconds
Started Jul 11 06:42:17 PM PDT 24
Finished Jul 11 06:42:23 PM PDT 24
Peak memory 200420 kb
Host smart-e7c1ac12-8a32-437d-9744-e73b51c5b8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274740572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3274740572
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2361551857
Short name T298
Test name
Test status
Simulation time 146406446 ps
CPU time 1.11 seconds
Started Jul 11 06:42:19 PM PDT 24
Finished Jul 11 06:42:21 PM PDT 24
Peak memory 200188 kb
Host smart-507b7f42-c4ec-4887-861d-72861db48e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361551857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2361551857
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1918455172
Short name T536
Test name
Test status
Simulation time 190318801 ps
CPU time 1.38 seconds
Started Jul 11 06:42:22 PM PDT 24
Finished Jul 11 06:42:25 PM PDT 24
Peak memory 200292 kb
Host smart-507450b6-a253-45f6-ac32-3e0ac18f24ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918455172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1918455172
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3212957107
Short name T176
Test name
Test status
Simulation time 4899062880 ps
CPU time 18.96 seconds
Started Jul 11 06:42:21 PM PDT 24
Finished Jul 11 06:42:41 PM PDT 24
Peak memory 208600 kb
Host smart-eb409806-4c81-42e6-bba4-4b7b877e329b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212957107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3212957107
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2324469000
Short name T425
Test name
Test status
Simulation time 115497306 ps
CPU time 1.42 seconds
Started Jul 11 06:42:21 PM PDT 24
Finished Jul 11 06:42:24 PM PDT 24
Peak memory 200080 kb
Host smart-697353ec-0ae6-4a3c-bc23-7e2bc4e26111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324469000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2324469000
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1197297209
Short name T244
Test name
Test status
Simulation time 63157446 ps
CPU time 0.8 seconds
Started Jul 11 06:42:17 PM PDT 24
Finished Jul 11 06:42:18 PM PDT 24
Peak memory 200160 kb
Host smart-a4fc3f27-82b5-4da2-9c5c-70d8b1977060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197297209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1197297209
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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