Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6655

1

T2

35

T4

25

T7

30

auto[1]

9849

1

T2

16

T4

34

T7

19

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5098	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	5654	1			T1	1		T2	14		T3	1
reset_info_cp[2]	2585	1			T2	10		T4	13		T7	5
reset_info_cp[4]	3309	1			T2	12		T4	10		T7	13
reset_info_cp[8]	87	1			T2	1		T50	2		T52	1
reset_info_cp[16]	97	1			T2	1		T13	1		T26	1
reset_info_cp[32]	106	1			T4	2		T52	2		T53	1
reset_info_cp[64]	92	1			T9	2		T26	2		T50	2
reset_info_cp[128]	96	1			T2	2		T50	2		T53	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2663	1			T2	8		T4	4		T7	6
reset_info_cp[1]	auto[1]	2371	1			T2	5		T4	12		T7	6
reset_info_cp[2]	auto[0]	778	1			T2	7		T4	8		T7	4
reset_info_cp[2]	auto[1]	1807	1			T2	3		T4	5		T7	1
reset_info_cp[4]	auto[0]	1088	1			T2	7		T4	3		T7	7
reset_info_cp[4]	auto[1]	2221	1			T2	5		T4	7		T7	6
reset_info_cp[8]	auto[0]	37	1			T2	1		T50	1		T60	2
reset_info_cp[8]	auto[1]	50	1			T50	1		T52	1		T60	1
reset_info_cp[16]	auto[0]	33	1			T26	1		T50	1		T60	1
reset_info_cp[16]	auto[1]	64	1			T2	1		T13	1		T53	1
reset_info_cp[32]	auto[0]	42	1			T39	3		T95	1		T132	1
reset_info_cp[32]	auto[1]	64	1			T4	2		T52	2		T53	1
reset_info_cp[64]	auto[0]	38	1			T26	1		T86	1		T87	1
reset_info_cp[64]	auto[1]	54	1			T9	2		T26	1		T50	2
reset_info_cp[128]	auto[0]	32	1			T86	1		T95	1		T83	1
reset_info_cp[128]	auto[1]	64	1			T2	2		T50	2		T53	2