Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T534 /workspace/coverage/default/28.rstmgr_smoke.666502360 Jul 12 05:48:36 PM PDT 24 Jul 12 05:48:39 PM PDT 24 251231493 ps
T535 /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1735265768 Jul 12 05:48:56 PM PDT 24 Jul 12 05:49:06 PM PDT 24 2354421565 ps
T536 /workspace/coverage/default/34.rstmgr_smoke.3117213887 Jul 12 05:48:44 PM PDT 24 Jul 12 05:48:47 PM PDT 24 110236949 ps
T537 /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2966460398 Jul 12 05:48:07 PM PDT 24 Jul 12 05:48:09 PM PDT 24 97772673 ps
T538 /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.256002817 Jul 12 05:48:31 PM PDT 24 Jul 12 05:48:33 PM PDT 24 248238110 ps
T69 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3476169530 Jul 12 05:47:36 PM PDT 24 Jul 12 05:47:41 PM PDT 24 299441018 ps
T64 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2517564967 Jul 12 05:47:34 PM PDT 24 Jul 12 05:47:40 PM PDT 24 888861256 ps
T65 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1051375269 Jul 12 05:47:39 PM PDT 24 Jul 12 05:47:43 PM PDT 24 202077638 ps
T66 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1364328214 Jul 12 05:47:27 PM PDT 24 Jul 12 05:47:29 PM PDT 24 83442509 ps
T67 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.363573341 Jul 12 05:47:38 PM PDT 24 Jul 12 05:47:43 PM PDT 24 147909148 ps
T71 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.479504870 Jul 12 05:47:34 PM PDT 24 Jul 12 05:47:39 PM PDT 24 807362099 ps
T70 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2662103202 Jul 12 05:47:13 PM PDT 24 Jul 12 05:47:16 PM PDT 24 163658178 ps
T72 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3325311495 Jul 12 05:47:27 PM PDT 24 Jul 12 05:47:32 PM PDT 24 487494885 ps
T88 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2430795949 Jul 12 05:47:19 PM PDT 24 Jul 12 05:47:21 PM PDT 24 119831987 ps
T89 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3238019003 Jul 12 05:47:38 PM PDT 24 Jul 12 05:47:43 PM PDT 24 320523373 ps
T102 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1482899703 Jul 12 05:47:33 PM PDT 24 Jul 12 05:47:36 PM PDT 24 76951023 ps
T90 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1593310878 Jul 12 05:47:28 PM PDT 24 Jul 12 05:47:31 PM PDT 24 205120560 ps
T91 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3114385981 Jul 12 05:47:29 PM PDT 24 Jul 12 05:47:32 PM PDT 24 121365518 ps
T103 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2146620159 Jul 12 05:47:43 PM PDT 24 Jul 12 05:47:45 PM PDT 24 71290895 ps
T539 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.983563436 Jul 12 05:47:21 PM PDT 24 Jul 12 05:47:23 PM PDT 24 87441971 ps
T104 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2749453881 Jul 12 05:47:32 PM PDT 24 Jul 12 05:47:35 PM PDT 24 241082178 ps
T92 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3479286692 Jul 12 05:47:37 PM PDT 24 Jul 12 05:47:43 PM PDT 24 909990086 ps
T93 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4112965141 Jul 12 05:47:25 PM PDT 24 Jul 12 05:47:29 PM PDT 24 527790184 ps
T540 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3704580361 Jul 12 05:47:33 PM PDT 24 Jul 12 05:47:37 PM PDT 24 82705340 ps
T541 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2746399237 Jul 12 05:47:22 PM PDT 24 Jul 12 05:47:28 PM PDT 24 490531310 ps
T111 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3470390934 Jul 12 05:47:35 PM PDT 24 Jul 12 05:47:39 PM PDT 24 205910956 ps
T542 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.930227905 Jul 12 05:47:18 PM PDT 24 Jul 12 05:47:28 PM PDT 24 2010460278 ps
T116 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.411593797 Jul 12 05:47:32 PM PDT 24 Jul 12 05:47:38 PM PDT 24 923749736 ps
T105 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1657978540 Jul 12 05:47:15 PM PDT 24 Jul 12 05:47:17 PM PDT 24 63398427 ps
T94 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.613328622 Jul 12 05:47:20 PM PDT 24 Jul 12 05:47:21 PM PDT 24 69998393 ps
T131 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1590094046 Jul 12 05:47:33 PM PDT 24 Jul 12 05:47:39 PM PDT 24 933362312 ps
T106 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3172559068 Jul 12 05:47:39 PM PDT 24 Jul 12 05:47:43 PM PDT 24 87786840 ps
T543 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3058825628 Jul 12 05:47:31 PM PDT 24 Jul 12 05:47:34 PM PDT 24 487417772 ps
T113 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.452441383 Jul 12 05:47:22 PM PDT 24 Jul 12 05:47:27 PM PDT 24 872214214 ps
T118 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2437525096 Jul 12 05:47:36 PM PDT 24 Jul 12 05:47:42 PM PDT 24 902381051 ps
T107 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.735805019 Jul 12 05:47:27 PM PDT 24 Jul 12 05:47:29 PM PDT 24 59905329 ps
T544 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2026035625 Jul 12 05:47:31 PM PDT 24 Jul 12 05:47:34 PM PDT 24 125033160 ps
T545 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4288606282 Jul 12 05:47:22 PM PDT 24 Jul 12 05:47:25 PM PDT 24 228290796 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3844071768 Jul 12 05:47:26 PM PDT 24 Jul 12 05:47:27 PM PDT 24 66653428 ps
T117 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3245920502 Jul 12 05:47:39 PM PDT 24 Jul 12 05:47:44 PM PDT 24 153742720 ps
T108 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1509447532 Jul 12 05:47:28 PM PDT 24 Jul 12 05:47:31 PM PDT 24 146614488 ps
T547 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2048115024 Jul 12 05:47:28 PM PDT 24 Jul 12 05:47:31 PM PDT 24 503287200 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.546970400 Jul 12 05:47:22 PM PDT 24 Jul 12 05:47:24 PM PDT 24 107285077 ps
T549 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3156651645 Jul 12 05:47:42 PM PDT 24 Jul 12 05:47:44 PM PDT 24 124396975 ps
T109 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3918002437 Jul 12 05:47:22 PM PDT 24 Jul 12 05:47:25 PM PDT 24 186993243 ps
T550 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.195436772 Jul 12 05:47:28 PM PDT 24 Jul 12 05:47:31 PM PDT 24 166817999 ps
T112 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3098744149 Jul 12 05:47:26 PM PDT 24 Jul 12 05:47:29 PM PDT 24 218035742 ps
T551 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1865007561 Jul 12 05:47:22 PM PDT 24 Jul 12 05:47:25 PM PDT 24 183697286 ps
T552 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3981539547 Jul 12 05:47:27 PM PDT 24 Jul 12 05:47:29 PM PDT 24 114362311 ps
T553 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3028891366 Jul 12 05:47:29 PM PDT 24 Jul 12 05:47:31 PM PDT 24 71154276 ps
T554 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1642272282 Jul 12 05:47:32 PM PDT 24 Jul 12 05:47:37 PM PDT 24 176816973 ps
T115 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1315275633 Jul 12 05:47:27 PM PDT 24 Jul 12 05:47:32 PM PDT 24 902495448 ps
T110 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2902330490 Jul 12 05:47:38 PM PDT 24 Jul 12 05:47:42 PM PDT 24 142246817 ps
T555 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2854247574 Jul 12 05:47:33 PM PDT 24 Jul 12 05:47:37 PM PDT 24 69448161 ps
T556 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4033547710 Jul 12 05:47:19 PM PDT 24 Jul 12 05:47:23 PM PDT 24 885288271 ps
T557 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1405705632 Jul 12 05:47:27 PM PDT 24 Jul 12 05:47:29 PM PDT 24 75999066 ps
T558 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2350420027 Jul 12 05:47:21 PM PDT 24 Jul 12 05:47:23 PM PDT 24 142453241 ps
T559 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.744585076 Jul 12 05:47:27 PM PDT 24 Jul 12 05:47:31 PM PDT 24 435902728 ps
T560 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2851106168 Jul 12 05:47:15 PM PDT 24 Jul 12 05:47:18 PM PDT 24 268240895 ps
T561 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1849734476 Jul 12 05:47:37 PM PDT 24 Jul 12 05:47:41 PM PDT 24 92370276 ps
T562 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.327798922 Jul 12 05:47:39 PM PDT 24 Jul 12 05:47:43 PM PDT 24 256030016 ps
T563 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1535006872 Jul 12 05:47:28 PM PDT 24 Jul 12 05:47:30 PM PDT 24 68951356 ps
T564 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.655548391 Jul 12 05:47:34 PM PDT 24 Jul 12 05:47:37 PM PDT 24 69188946 ps
T565 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2552610079 Jul 12 05:47:21 PM PDT 24 Jul 12 05:47:23 PM PDT 24 204403985 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3303531864 Jul 12 05:47:21 PM PDT 24 Jul 12 05:47:28 PM PDT 24 489875712 ps
T567 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.524315222 Jul 12 05:47:36 PM PDT 24 Jul 12 05:47:41 PM PDT 24 211244392 ps
T568 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1408679164 Jul 12 05:47:36 PM PDT 24 Jul 12 05:47:40 PM PDT 24 212241999 ps
T569 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3472083176 Jul 12 05:47:29 PM PDT 24 Jul 12 05:47:33 PM PDT 24 499249885 ps
T570 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2939399395 Jul 12 05:47:22 PM PDT 24 Jul 12 05:47:25 PM PDT 24 224314913 ps
T571 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2948891669 Jul 12 05:47:43 PM PDT 24 Jul 12 05:47:46 PM PDT 24 76363333 ps
T572 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.199997605 Jul 12 05:47:37 PM PDT 24 Jul 12 05:47:41 PM PDT 24 117665163 ps
T573 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3154637022 Jul 12 05:47:30 PM PDT 24 Jul 12 05:47:32 PM PDT 24 162480805 ps
T574 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2265891818 Jul 12 05:47:34 PM PDT 24 Jul 12 05:47:38 PM PDT 24 269947449 ps
T575 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2388379313 Jul 12 05:47:29 PM PDT 24 Jul 12 05:47:32 PM PDT 24 198654801 ps
T576 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2824539040 Jul 12 05:47:37 PM PDT 24 Jul 12 05:47:40 PM PDT 24 126898819 ps
T577 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4091872313 Jul 12 05:47:21 PM PDT 24 Jul 12 05:47:23 PM PDT 24 160647430 ps
T114 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3747596634 Jul 12 05:47:37 PM PDT 24 Jul 12 05:47:43 PM PDT 24 828157006 ps
T578 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.639154709 Jul 12 05:47:27 PM PDT 24 Jul 12 05:47:29 PM PDT 24 443915023 ps
T579 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.60036474 Jul 12 05:47:32 PM PDT 24 Jul 12 05:47:35 PM PDT 24 187453603 ps
T580 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2947294103 Jul 12 05:47:32 PM PDT 24 Jul 12 05:47:36 PM PDT 24 211153647 ps
T581 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.390693756 Jul 12 05:47:31 PM PDT 24 Jul 12 05:47:35 PM PDT 24 184608480 ps
T582 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3510103189 Jul 12 05:47:29 PM PDT 24 Jul 12 05:47:31 PM PDT 24 97192914 ps
T583 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.380313254 Jul 12 05:47:27 PM PDT 24 Jul 12 05:47:36 PM PDT 24 2003383636 ps
T584 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1714912903 Jul 12 05:47:33 PM PDT 24 Jul 12 05:47:37 PM PDT 24 436698335 ps
T585 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.166726880 Jul 12 05:47:16 PM PDT 24 Jul 12 05:47:19 PM PDT 24 359949541 ps
T586 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3563857248 Jul 12 05:47:33 PM PDT 24 Jul 12 05:47:38 PM PDT 24 236818613 ps
T587 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3588109724 Jul 12 05:47:20 PM PDT 24 Jul 12 05:47:22 PM PDT 24 420417760 ps
T588 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3270143021 Jul 12 05:47:23 PM PDT 24 Jul 12 05:47:25 PM PDT 24 82318720 ps
T589 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2708613066 Jul 12 05:47:32 PM PDT 24 Jul 12 05:47:36 PM PDT 24 109450692 ps
T590 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3830044563 Jul 12 05:47:33 PM PDT 24 Jul 12 05:47:37 PM PDT 24 149827502 ps
T591 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1311258564 Jul 12 05:47:22 PM PDT 24 Jul 12 05:47:26 PM PDT 24 436691045 ps
T592 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1238608203 Jul 12 05:47:26 PM PDT 24 Jul 12 05:47:28 PM PDT 24 78400278 ps
T593 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1386912081 Jul 12 05:47:39 PM PDT 24 Jul 12 05:47:43 PM PDT 24 146707077 ps
T594 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1966701889 Jul 12 05:47:26 PM PDT 24 Jul 12 05:47:28 PM PDT 24 76623029 ps
T595 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.449730025 Jul 12 05:47:33 PM PDT 24 Jul 12 05:47:37 PM PDT 24 145569994 ps
T596 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3938439460 Jul 12 05:47:39 PM PDT 24 Jul 12 05:47:43 PM PDT 24 107831747 ps
T597 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4002801478 Jul 12 05:47:32 PM PDT 24 Jul 12 05:47:35 PM PDT 24 130278284 ps
T598 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.723025696 Jul 12 05:47:39 PM PDT 24 Jul 12 05:47:45 PM PDT 24 1079246775 ps
T599 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3556586499 Jul 12 05:47:43 PM PDT 24 Jul 12 05:47:46 PM PDT 24 141289267 ps
T600 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.29983888 Jul 12 05:47:33 PM PDT 24 Jul 12 05:47:36 PM PDT 24 78688607 ps
T601 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3706577101 Jul 12 05:47:32 PM PDT 24 Jul 12 05:47:38 PM PDT 24 784834350 ps
T602 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2807488109 Jul 12 05:47:37 PM PDT 24 Jul 12 05:47:40 PM PDT 24 74074297 ps
T603 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3565644405 Jul 12 05:47:34 PM PDT 24 Jul 12 05:47:38 PM PDT 24 188992276 ps
T604 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2411872221 Jul 12 05:47:37 PM PDT 24 Jul 12 05:47:42 PM PDT 24 274122149 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4177547012 Jul 12 05:47:19 PM PDT 24 Jul 12 05:47:21 PM PDT 24 135274154 ps
T606 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3055898419 Jul 12 05:47:50 PM PDT 24 Jul 12 05:47:52 PM PDT 24 239410448 ps
T607 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.229530922 Jul 12 05:47:33 PM PDT 24 Jul 12 05:47:40 PM PDT 24 561160107 ps
T608 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3789909542 Jul 12 05:47:32 PM PDT 24 Jul 12 05:47:37 PM PDT 24 196735952 ps
T609 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3188254384 Jul 12 05:47:21 PM PDT 24 Jul 12 05:47:27 PM PDT 24 489749874 ps
T610 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1000392743 Jul 12 05:47:31 PM PDT 24 Jul 12 05:47:34 PM PDT 24 72274516 ps
T611 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1120130866 Jul 12 05:47:16 PM PDT 24 Jul 12 05:47:18 PM PDT 24 147817304 ps
T612 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2911419498 Jul 12 05:47:25 PM PDT 24 Jul 12 05:47:27 PM PDT 24 57120134 ps
T613 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.102508652 Jul 12 05:47:39 PM PDT 24 Jul 12 05:47:43 PM PDT 24 189490879 ps
T614 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3228322406 Jul 12 05:47:38 PM PDT 24 Jul 12 05:47:43 PM PDT 24 414571622 ps
T615 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1598408533 Jul 12 05:47:34 PM PDT 24 Jul 12 05:47:37 PM PDT 24 66606832 ps
T616 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1831062305 Jul 12 05:47:37 PM PDT 24 Jul 12 05:47:42 PM PDT 24 232444468 ps
T617 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2362790809 Jul 12 05:47:21 PM PDT 24 Jul 12 05:47:23 PM PDT 24 55151885 ps
T618 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2193051147 Jul 12 05:47:20 PM PDT 24 Jul 12 05:47:23 PM PDT 24 437031349 ps
T619 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1141862618 Jul 12 05:47:26 PM PDT 24 Jul 12 05:47:28 PM PDT 24 221788039 ps
T620 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4051821388 Jul 12 05:47:15 PM PDT 24 Jul 12 05:47:20 PM PDT 24 479657052 ps

Test location /workspace/coverage/default/43.rstmgr_reset.3210712456
Short name T9
Test name
Test status
Simulation time 1769297342 ps
CPU time 6.6 seconds
Started Jul 12 05:48:53 PM PDT 24
Finished Jul 12 05:49:00 PM PDT 24
Peak memory 200320 kb
Host smart-b5c5d524-7eee-46b7-8dea-616442d5230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210712456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3210712456
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3110523545
Short name T1
Test name
Test status
Simulation time 346578134 ps
CPU time 2.44 seconds
Started Jul 12 05:47:48 PM PDT 24
Finished Jul 12 05:47:51 PM PDT 24
Peak memory 200124 kb
Host smart-db0287d9-3f6c-42e9-aa16-0be804a6b0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110523545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3110523545
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.479504870
Short name T71
Test name
Test status
Simulation time 807362099 ps
CPU time 2.84 seconds
Started Jul 12 05:47:34 PM PDT 24
Finished Jul 12 05:47:39 PM PDT 24
Peak memory 200460 kb
Host smart-e04fffa1-fb61-4a4e-81d8-862300df5f58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479504870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
479504870
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.622786901
Short name T73
Test name
Test status
Simulation time 8363763350 ps
CPU time 13.98 seconds
Started Jul 12 05:47:43 PM PDT 24
Finished Jul 12 05:47:59 PM PDT 24
Peak memory 221236 kb
Host smart-13b16b4b-80ec-46cd-bd64-73c1f7432468
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622786901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.622786901
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1264384457
Short name T53
Test name
Test status
Simulation time 1895596995 ps
CPU time 7.22 seconds
Started Jul 12 05:48:47 PM PDT 24
Finished Jul 12 05:48:55 PM PDT 24
Peak memory 217724 kb
Host smart-ab5f05f6-dade-4e0d-ba06-02d5285d3e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264384457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1264384457
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3325311495
Short name T72
Test name
Test status
Simulation time 487494885 ps
CPU time 3.59 seconds
Started Jul 12 05:47:27 PM PDT 24
Finished Jul 12 05:47:32 PM PDT 24
Peak memory 212928 kb
Host smart-09fbaa27-fd14-4261-baff-8796d8b8e6c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325311495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3325311495
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1544289442
Short name T60
Test name
Test status
Simulation time 5142239412 ps
CPU time 23.73 seconds
Started Jul 12 05:48:14 PM PDT 24
Finished Jul 12 05:48:40 PM PDT 24
Peak memory 200412 kb
Host smart-2cc68d44-6d35-42e3-98b4-8733b5b663da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544289442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1544289442
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1578059891
Short name T32
Test name
Test status
Simulation time 1226373294 ps
CPU time 5.46 seconds
Started Jul 12 05:48:17 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 217276 kb
Host smart-7a4eb7ee-343e-4a6c-aa2c-f31b5d3295ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578059891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1578059891
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1498920320
Short name T61
Test name
Test status
Simulation time 151276105 ps
CPU time 1.1 seconds
Started Jul 12 05:47:38 PM PDT 24
Finished Jul 12 05:47:42 PM PDT 24
Peak memory 200096 kb
Host smart-0e732a00-64e4-4eec-b142-cf7e653f9f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498920320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1498920320
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3110363519
Short name T86
Test name
Test status
Simulation time 102232226 ps
CPU time 0.96 seconds
Started Jul 12 05:48:01 PM PDT 24
Finished Jul 12 05:48:04 PM PDT 24
Peak memory 200092 kb
Host smart-319d5fac-0572-453a-95c4-01b4b192217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110363519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3110363519
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3717389509
Short name T76
Test name
Test status
Simulation time 64157559 ps
CPU time 0.79 seconds
Started Jul 12 05:47:44 PM PDT 24
Finished Jul 12 05:47:46 PM PDT 24
Peak memory 199880 kb
Host smart-0e88ed79-4dd0-4eb9-b053-e862ef3fb3c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717389509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3717389509
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1590094046
Short name T131
Test name
Test status
Simulation time 933362312 ps
CPU time 3.18 seconds
Started Jul 12 05:47:33 PM PDT 24
Finished Jul 12 05:47:39 PM PDT 24
Peak memory 200500 kb
Host smart-87eefc12-9af5-4341-bc70-b0b11e2fbad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590094046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1590094046
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1842110123
Short name T179
Test name
Test status
Simulation time 162155190 ps
CPU time 1.08 seconds
Started Jul 12 05:48:07 PM PDT 24
Finished Jul 12 05:48:09 PM PDT 24
Peak memory 200080 kb
Host smart-53a17903-32b9-4645-9ced-f371c5988359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842110123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1842110123
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.411593797
Short name T116
Test name
Test status
Simulation time 923749736 ps
CPU time 3.3 seconds
Started Jul 12 05:47:32 PM PDT 24
Finished Jul 12 05:47:38 PM PDT 24
Peak memory 200516 kb
Host smart-3755e6b5-17c0-447d-9f6e-bc97478cd18a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411593797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.411593797
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.68452174
Short name T54
Test name
Test status
Simulation time 2372172608 ps
CPU time 8.88 seconds
Started Jul 12 05:48:06 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 217832 kb
Host smart-59b064cd-e411-4fbe-8159-40db1a4de3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68452174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.68452174
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1657978540
Short name T105
Test name
Test status
Simulation time 63398427 ps
CPU time 0.77 seconds
Started Jul 12 05:47:15 PM PDT 24
Finished Jul 12 05:47:17 PM PDT 24
Peak memory 200192 kb
Host smart-5241a5e1-0f95-4031-911a-937a96e3e5c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657978540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1657978540
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.591880071
Short name T21
Test name
Test status
Simulation time 100608187 ps
CPU time 0.85 seconds
Started Jul 12 05:48:15 PM PDT 24
Finished Jul 12 05:48:17 PM PDT 24
Peak memory 199884 kb
Host smart-ca8a0475-1632-48ce-ac4c-cfbdd0665bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591880071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.591880071
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2980423671
Short name T36
Test name
Test status
Simulation time 2172516027 ps
CPU time 8.37 seconds
Started Jul 12 05:47:44 PM PDT 24
Finished Jul 12 05:47:54 PM PDT 24
Peak memory 216936 kb
Host smart-2b5d4409-2887-4cb2-bed8-1aed98c88d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980423671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2980423671
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2662103202
Short name T70
Test name
Test status
Simulation time 163658178 ps
CPU time 1.5 seconds
Started Jul 12 05:47:13 PM PDT 24
Finished Jul 12 05:47:16 PM PDT 24
Peak memory 208712 kb
Host smart-1f14c600-f43c-450e-bf67-e0578ab6c678
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662103202 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2662103202
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1315275633
Short name T115
Test name
Test status
Simulation time 902495448 ps
CPU time 3.27 seconds
Started Jul 12 05:47:27 PM PDT 24
Finished Jul 12 05:47:32 PM PDT 24
Peak memory 200408 kb
Host smart-daf4d0ea-9bc1-4e32-b23c-680f867d5527
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315275633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1315275633
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.166726880
Short name T585
Test name
Test status
Simulation time 359949541 ps
CPU time 2.36 seconds
Started Jul 12 05:47:16 PM PDT 24
Finished Jul 12 05:47:19 PM PDT 24
Peak memory 200460 kb
Host smart-e4640212-6696-4f9a-99d2-230e9e5edd81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166726880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.166726880
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.930227905
Short name T542
Test name
Test status
Simulation time 2010460278 ps
CPU time 8.83 seconds
Started Jul 12 05:47:18 PM PDT 24
Finished Jul 12 05:47:28 PM PDT 24
Peak memory 200180 kb
Host smart-893fe4e4-8d4f-405b-a8d8-b62f93d595ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930227905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.930227905
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1120130866
Short name T611
Test name
Test status
Simulation time 147817304 ps
CPU time 1.06 seconds
Started Jul 12 05:47:16 PM PDT 24
Finished Jul 12 05:47:18 PM PDT 24
Peak memory 200260 kb
Host smart-92eee0e8-4976-41ab-96ac-ca129044fc55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120130866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
120130866
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2851106168
Short name T560
Test name
Test status
Simulation time 268240895 ps
CPU time 1.64 seconds
Started Jul 12 05:47:15 PM PDT 24
Finished Jul 12 05:47:18 PM PDT 24
Peak memory 200296 kb
Host smart-66015094-35ca-4541-b224-452aa379038d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851106168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2851106168
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4051821388
Short name T620
Test name
Test status
Simulation time 479657052 ps
CPU time 3.54 seconds
Started Jul 12 05:47:15 PM PDT 24
Finished Jul 12 05:47:20 PM PDT 24
Peak memory 208544 kb
Host smart-7134705b-dcf4-46a4-9c3d-ac46ad2e66ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051821388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.4051821388
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4033547710
Short name T556
Test name
Test status
Simulation time 885288271 ps
CPU time 3.29 seconds
Started Jul 12 05:47:19 PM PDT 24
Finished Jul 12 05:47:23 PM PDT 24
Peak memory 200612 kb
Host smart-4d9e4ecc-1f1d-437e-818b-fbb5a413042a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033547710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.4033547710
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2939399395
Short name T570
Test name
Test status
Simulation time 224314913 ps
CPU time 1.53 seconds
Started Jul 12 05:47:22 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 200424 kb
Host smart-28718e30-fdb1-4a52-826d-d3bc1d28c6a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939399395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
939399395
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2746399237
Short name T541
Test name
Test status
Simulation time 490531310 ps
CPU time 6.04 seconds
Started Jul 12 05:47:22 PM PDT 24
Finished Jul 12 05:47:28 PM PDT 24
Peak memory 200252 kb
Host smart-c58c37d5-1410-4d1b-8f14-6b3050e51134
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746399237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
746399237
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4177547012
Short name T605
Test name
Test status
Simulation time 135274154 ps
CPU time 0.96 seconds
Started Jul 12 05:47:19 PM PDT 24
Finished Jul 12 05:47:21 PM PDT 24
Peak memory 200228 kb
Host smart-fcdf2073-99d3-4a0a-af16-c3392d376101
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177547012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4
177547012
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4091872313
Short name T577
Test name
Test status
Simulation time 160647430 ps
CPU time 1.3 seconds
Started Jul 12 05:47:21 PM PDT 24
Finished Jul 12 05:47:23 PM PDT 24
Peak memory 208392 kb
Host smart-ddb3864b-2160-4685-8d62-8101c46b17df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091872313 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.4091872313
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3844071768
Short name T546
Test name
Test status
Simulation time 66653428 ps
CPU time 0.76 seconds
Started Jul 12 05:47:26 PM PDT 24
Finished Jul 12 05:47:27 PM PDT 24
Peak memory 200244 kb
Host smart-14cb56ee-a303-43a5-a9b9-f620f3047182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844071768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3844071768
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3055898419
Short name T606
Test name
Test status
Simulation time 239410448 ps
CPU time 1.57 seconds
Started Jul 12 05:47:50 PM PDT 24
Finished Jul 12 05:47:52 PM PDT 24
Peak memory 200448 kb
Host smart-c2e6d365-cd89-493d-8153-1faf0e246571
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055898419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3055898419
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2350420027
Short name T558
Test name
Test status
Simulation time 142453241 ps
CPU time 2.08 seconds
Started Jul 12 05:47:21 PM PDT 24
Finished Jul 12 05:47:23 PM PDT 24
Peak memory 208544 kb
Host smart-d3e6d778-797f-46ef-9fd7-925665feb6f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350420027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2350420027
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.452441383
Short name T113
Test name
Test status
Simulation time 872214214 ps
CPU time 3.2 seconds
Started Jul 12 05:47:22 PM PDT 24
Finished Jul 12 05:47:27 PM PDT 24
Peak memory 200460 kb
Host smart-3ebc6d4b-9e31-48d0-abc4-d7f2cccb80b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452441383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
452441383
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.60036474
Short name T579
Test name
Test status
Simulation time 187453603 ps
CPU time 1.7 seconds
Started Jul 12 05:47:32 PM PDT 24
Finished Jul 12 05:47:35 PM PDT 24
Peak memory 208716 kb
Host smart-1fac2c50-943c-4c56-a76e-87e90c6a6b99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60036474 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.60036474
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2911419498
Short name T612
Test name
Test status
Simulation time 57120134 ps
CPU time 0.74 seconds
Started Jul 12 05:47:25 PM PDT 24
Finished Jul 12 05:47:27 PM PDT 24
Peak memory 200168 kb
Host smart-8f5a4df0-637d-42f6-a339-7e10bad42f76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911419498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2911419498
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1141862618
Short name T619
Test name
Test status
Simulation time 221788039 ps
CPU time 1.64 seconds
Started Jul 12 05:47:26 PM PDT 24
Finished Jul 12 05:47:28 PM PDT 24
Peak memory 200400 kb
Host smart-da636362-29b2-4203-9773-9905971d7678
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141862618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1141862618
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3938439460
Short name T596
Test name
Test status
Simulation time 107831747 ps
CPU time 1.39 seconds
Started Jul 12 05:47:39 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 211508 kb
Host smart-214eca6d-b727-495e-ab74-11f327f8a3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938439460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3938439460
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3789909542
Short name T608
Test name
Test status
Simulation time 196735952 ps
CPU time 2.03 seconds
Started Jul 12 05:47:32 PM PDT 24
Finished Jul 12 05:47:37 PM PDT 24
Peak memory 208636 kb
Host smart-d82f147f-4bc0-4dd9-b0c1-21cc23fd9488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789909542 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3789909542
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1000392743
Short name T610
Test name
Test status
Simulation time 72274516 ps
CPU time 0.83 seconds
Started Jul 12 05:47:31 PM PDT 24
Finished Jul 12 05:47:34 PM PDT 24
Peak memory 200096 kb
Host smart-04597b51-b678-477a-beda-4496d7f36339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000392743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1000392743
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2947294103
Short name T580
Test name
Test status
Simulation time 211153647 ps
CPU time 1.58 seconds
Started Jul 12 05:47:32 PM PDT 24
Finished Jul 12 05:47:36 PM PDT 24
Peak memory 200440 kb
Host smart-cdd10ace-95de-4035-84db-36c21a39aac9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947294103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2947294103
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3563857248
Short name T586
Test name
Test status
Simulation time 236818613 ps
CPU time 2 seconds
Started Jul 12 05:47:33 PM PDT 24
Finished Jul 12 05:47:38 PM PDT 24
Peak memory 208568 kb
Host smart-7a1edae4-d2f1-4438-bda4-5ecd0bdaf0ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563857248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3563857248
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3058825628
Short name T543
Test name
Test status
Simulation time 487417772 ps
CPU time 1.88 seconds
Started Jul 12 05:47:31 PM PDT 24
Finished Jul 12 05:47:34 PM PDT 24
Peak memory 200480 kb
Host smart-2e751272-83de-464c-beeb-8165d8fa0c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058825628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3058825628
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4002801478
Short name T597
Test name
Test status
Simulation time 130278284 ps
CPU time 1.04 seconds
Started Jul 12 05:47:32 PM PDT 24
Finished Jul 12 05:47:35 PM PDT 24
Peak memory 200280 kb
Host smart-a544a08f-f526-4c6c-9e1b-849a424966b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002801478 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.4002801478
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3704580361
Short name T540
Test name
Test status
Simulation time 82705340 ps
CPU time 0.85 seconds
Started Jul 12 05:47:33 PM PDT 24
Finished Jul 12 05:47:37 PM PDT 24
Peak memory 200452 kb
Host smart-aca27b0e-4bad-4bfc-961e-98fe9863adef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704580361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3704580361
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2749453881
Short name T104
Test name
Test status
Simulation time 241082178 ps
CPU time 1.71 seconds
Started Jul 12 05:47:32 PM PDT 24
Finished Jul 12 05:47:35 PM PDT 24
Peak memory 200472 kb
Host smart-d812bc47-4698-4fea-bf0e-d7ef30105094
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749453881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2749453881
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3470390934
Short name T111
Test name
Test status
Simulation time 205910956 ps
CPU time 1.67 seconds
Started Jul 12 05:47:35 PM PDT 24
Finished Jul 12 05:47:39 PM PDT 24
Peak memory 211172 kb
Host smart-722049db-0102-4a7e-8b93-c4815930e95d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470390934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3470390934
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2517564967
Short name T64
Test name
Test status
Simulation time 888861256 ps
CPU time 3.51 seconds
Started Jul 12 05:47:34 PM PDT 24
Finished Jul 12 05:47:40 PM PDT 24
Peak memory 200424 kb
Host smart-8f7da5c0-5101-45fc-a197-3db93ad26248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517564967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2517564967
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.390693756
Short name T581
Test name
Test status
Simulation time 184608480 ps
CPU time 1.73 seconds
Started Jul 12 05:47:31 PM PDT 24
Finished Jul 12 05:47:35 PM PDT 24
Peak memory 208992 kb
Host smart-89cf263e-b097-4e6a-bbbc-d99f9341a8ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390693756 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.390693756
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1598408533
Short name T615
Test name
Test status
Simulation time 66606832 ps
CPU time 0.78 seconds
Started Jul 12 05:47:34 PM PDT 24
Finished Jul 12 05:47:37 PM PDT 24
Peak memory 200244 kb
Host smart-680cb827-f90e-4d70-acb9-4a4afa5ccf19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598408533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1598408533
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3830044563
Short name T590
Test name
Test status
Simulation time 149827502 ps
CPU time 1.11 seconds
Started Jul 12 05:47:33 PM PDT 24
Finished Jul 12 05:47:37 PM PDT 24
Peak memory 200304 kb
Host smart-6c54c0ed-f827-40aa-af37-9efda42a3f01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830044563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3830044563
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.229530922
Short name T607
Test name
Test status
Simulation time 561160107 ps
CPU time 3.62 seconds
Started Jul 12 05:47:33 PM PDT 24
Finished Jul 12 05:47:40 PM PDT 24
Peak memory 208632 kb
Host smart-b193fa31-d3a7-484e-8e2f-39552bd0b4c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229530922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.229530922
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1714912903
Short name T584
Test name
Test status
Simulation time 436698335 ps
CPU time 1.79 seconds
Started Jul 12 05:47:33 PM PDT 24
Finished Jul 12 05:47:37 PM PDT 24
Peak memory 200644 kb
Host smart-bf468a22-94a1-4986-8622-1ae26fef4944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714912903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1714912903
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2708613066
Short name T589
Test name
Test status
Simulation time 109450692 ps
CPU time 1.17 seconds
Started Jul 12 05:47:32 PM PDT 24
Finished Jul 12 05:47:36 PM PDT 24
Peak memory 208568 kb
Host smart-bd7e4261-f89d-44da-a00c-a9548662ce1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708613066 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2708613066
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.29983888
Short name T600
Test name
Test status
Simulation time 78688607 ps
CPU time 0.82 seconds
Started Jul 12 05:47:33 PM PDT 24
Finished Jul 12 05:47:36 PM PDT 24
Peak memory 200204 kb
Host smart-f5c1d923-1ed3-4ee6-a9c3-c198b45b9a36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29983888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.29983888
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.449730025
Short name T595
Test name
Test status
Simulation time 145569994 ps
CPU time 1.14 seconds
Started Jul 12 05:47:33 PM PDT 24
Finished Jul 12 05:47:37 PM PDT 24
Peak memory 200304 kb
Host smart-415f4a6f-cb2c-4124-9fe5-da8f26a7de50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449730025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.449730025
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3245920502
Short name T117
Test name
Test status
Simulation time 153742720 ps
CPU time 2.28 seconds
Started Jul 12 05:47:39 PM PDT 24
Finished Jul 12 05:47:44 PM PDT 24
Peak memory 212528 kb
Host smart-a90947d9-31a1-46f6-af38-c03c9b737dc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245920502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3245920502
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3156651645
Short name T549
Test name
Test status
Simulation time 124396975 ps
CPU time 0.96 seconds
Started Jul 12 05:47:42 PM PDT 24
Finished Jul 12 05:47:44 PM PDT 24
Peak memory 200376 kb
Host smart-a379fdb0-0550-4ca3-aca4-426bb546c72c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156651645 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3156651645
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2854247574
Short name T555
Test name
Test status
Simulation time 69448161 ps
CPU time 0.81 seconds
Started Jul 12 05:47:33 PM PDT 24
Finished Jul 12 05:47:37 PM PDT 24
Peak memory 200236 kb
Host smart-da43d73e-64a3-4e59-98ad-757c8696bbd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854247574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2854247574
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1482899703
Short name T102
Test name
Test status
Simulation time 76951023 ps
CPU time 0.95 seconds
Started Jul 12 05:47:33 PM PDT 24
Finished Jul 12 05:47:36 PM PDT 24
Peak memory 200276 kb
Host smart-9e5c7951-393e-4c2f-953b-bfe6428b4d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482899703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1482899703
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1642272282
Short name T554
Test name
Test status
Simulation time 176816973 ps
CPU time 2.51 seconds
Started Jul 12 05:47:32 PM PDT 24
Finished Jul 12 05:47:37 PM PDT 24
Peak memory 216676 kb
Host smart-01a16a75-c946-4a61-a1f2-851649247719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642272282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1642272282
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3706577101
Short name T601
Test name
Test status
Simulation time 784834350 ps
CPU time 2.85 seconds
Started Jul 12 05:47:32 PM PDT 24
Finished Jul 12 05:47:38 PM PDT 24
Peak memory 200432 kb
Host smart-43761449-fb13-49dd-8fc5-a43c739dec40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706577101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3706577101
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2824539040
Short name T576
Test name
Test status
Simulation time 126898819 ps
CPU time 1.03 seconds
Started Jul 12 05:47:37 PM PDT 24
Finished Jul 12 05:47:40 PM PDT 24
Peak memory 200348 kb
Host smart-4739d333-9ca8-4845-b43c-95faf3393acc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824539040 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2824539040
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2807488109
Short name T602
Test name
Test status
Simulation time 74074297 ps
CPU time 0.76 seconds
Started Jul 12 05:47:37 PM PDT 24
Finished Jul 12 05:47:40 PM PDT 24
Peak memory 200176 kb
Host smart-4c0f2ac5-258f-4ce1-8642-6490533e1828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807488109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2807488109
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3556586499
Short name T599
Test name
Test status
Simulation time 141289267 ps
CPU time 1.2 seconds
Started Jul 12 05:47:43 PM PDT 24
Finished Jul 12 05:47:46 PM PDT 24
Peak memory 200308 kb
Host smart-86de819a-a6c2-414d-86cd-6a6669f4b03f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556586499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3556586499
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1831062305
Short name T616
Test name
Test status
Simulation time 232444468 ps
CPU time 1.86 seconds
Started Jul 12 05:47:37 PM PDT 24
Finished Jul 12 05:47:42 PM PDT 24
Peak memory 208592 kb
Host smart-ba51084c-6b61-498b-9f75-2882c932a779
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831062305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1831062305
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3228322406
Short name T614
Test name
Test status
Simulation time 414571622 ps
CPU time 1.89 seconds
Started Jul 12 05:47:38 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 200444 kb
Host smart-ba1dc5a1-7aaf-4e0c-894e-8d7b8b037fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228322406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3228322406
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.524315222
Short name T567
Test name
Test status
Simulation time 211244392 ps
CPU time 2.01 seconds
Started Jul 12 05:47:36 PM PDT 24
Finished Jul 12 05:47:41 PM PDT 24
Peak memory 208696 kb
Host smart-193b2b97-564c-4415-ab59-0b1c09a10d7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524315222 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.524315222
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2146620159
Short name T103
Test name
Test status
Simulation time 71290895 ps
CPU time 0.87 seconds
Started Jul 12 05:47:43 PM PDT 24
Finished Jul 12 05:47:45 PM PDT 24
Peak memory 200248 kb
Host smart-84d05471-ca73-4a75-ae5f-9707c378176c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146620159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2146620159
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1849734476
Short name T561
Test name
Test status
Simulation time 92370276 ps
CPU time 1.21 seconds
Started Jul 12 05:47:37 PM PDT 24
Finished Jul 12 05:47:41 PM PDT 24
Peak memory 200404 kb
Host smart-92aae46f-0f4d-42a3-9e16-294f7315dccf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849734476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1849734476
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2411872221
Short name T604
Test name
Test status
Simulation time 274122149 ps
CPU time 2.15 seconds
Started Jul 12 05:47:37 PM PDT 24
Finished Jul 12 05:47:42 PM PDT 24
Peak memory 208620 kb
Host smart-9cbaae7f-bd63-412b-a7f4-92e8a2b4482a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411872221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2411872221
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3479286692
Short name T92
Test name
Test status
Simulation time 909990086 ps
CPU time 3.31 seconds
Started Jul 12 05:47:37 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 200584 kb
Host smart-94951ea5-5e89-413a-93bc-af14bd0e9132
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479286692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3479286692
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1408679164
Short name T568
Test name
Test status
Simulation time 212241999 ps
CPU time 1.4 seconds
Started Jul 12 05:47:36 PM PDT 24
Finished Jul 12 05:47:40 PM PDT 24
Peak memory 208460 kb
Host smart-ef660403-8da5-4080-bdb0-de99c1524b78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408679164 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1408679164
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3172559068
Short name T106
Test name
Test status
Simulation time 87786840 ps
CPU time 0.87 seconds
Started Jul 12 05:47:39 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 200236 kb
Host smart-487c3c24-6ca1-495d-9e42-d7e0f5b23530
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172559068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3172559068
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2902330490
Short name T110
Test name
Test status
Simulation time 142246817 ps
CPU time 1.11 seconds
Started Jul 12 05:47:38 PM PDT 24
Finished Jul 12 05:47:42 PM PDT 24
Peak memory 200160 kb
Host smart-74a29a67-21f7-4801-a29d-eb1718ec46d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902330490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2902330490
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3476169530
Short name T69
Test name
Test status
Simulation time 299441018 ps
CPU time 2.33 seconds
Started Jul 12 05:47:36 PM PDT 24
Finished Jul 12 05:47:41 PM PDT 24
Peak memory 208556 kb
Host smart-e1b2976e-87b4-4e9b-8394-5261e1515783
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476169530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3476169530
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3747596634
Short name T114
Test name
Test status
Simulation time 828157006 ps
CPU time 2.81 seconds
Started Jul 12 05:47:37 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 200496 kb
Host smart-0a71b46f-a0b9-4f52-9c4f-df50e7d5ab6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747596634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3747596634
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.102508652
Short name T613
Test name
Test status
Simulation time 189490879 ps
CPU time 1.2 seconds
Started Jul 12 05:47:39 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 200308 kb
Host smart-abf056ed-08d0-4530-952a-1596e931bbc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102508652 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.102508652
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2948891669
Short name T571
Test name
Test status
Simulation time 76363333 ps
CPU time 0.87 seconds
Started Jul 12 05:47:43 PM PDT 24
Finished Jul 12 05:47:46 PM PDT 24
Peak memory 200248 kb
Host smart-c35e8b2d-b76f-41bc-97f6-d44be150d7ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948891669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2948891669
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.199997605
Short name T572
Test name
Test status
Simulation time 117665163 ps
CPU time 1.14 seconds
Started Jul 12 05:47:37 PM PDT 24
Finished Jul 12 05:47:41 PM PDT 24
Peak memory 200428 kb
Host smart-c070a5bf-53bd-4664-b369-0fcd74b2c57e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199997605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.199997605
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3238019003
Short name T89
Test name
Test status
Simulation time 320523373 ps
CPU time 2.51 seconds
Started Jul 12 05:47:38 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 212088 kb
Host smart-9f873463-b21c-45d8-af67-7e70c72c0d37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238019003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3238019003
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2437525096
Short name T118
Test name
Test status
Simulation time 902381051 ps
CPU time 3.43 seconds
Started Jul 12 05:47:36 PM PDT 24
Finished Jul 12 05:47:42 PM PDT 24
Peak memory 200396 kb
Host smart-6f1d0200-0db9-4de4-b045-f5d3f92680c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437525096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2437525096
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.546970400
Short name T548
Test name
Test status
Simulation time 107285077 ps
CPU time 1.31 seconds
Started Jul 12 05:47:22 PM PDT 24
Finished Jul 12 05:47:24 PM PDT 24
Peak memory 200388 kb
Host smart-fab49fd7-6ea7-4cb3-bba2-2bab24865713
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546970400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.546970400
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3303531864
Short name T566
Test name
Test status
Simulation time 489875712 ps
CPU time 5.88 seconds
Started Jul 12 05:47:21 PM PDT 24
Finished Jul 12 05:47:28 PM PDT 24
Peak memory 200580 kb
Host smart-2798c93b-7a48-41d8-8c70-a83910a53c51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303531864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
303531864
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3270143021
Short name T588
Test name
Test status
Simulation time 82318720 ps
CPU time 0.84 seconds
Started Jul 12 05:47:23 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 200252 kb
Host smart-c71a7cdd-5a6f-47d6-a00b-a83544a1d25b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270143021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
270143021
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3981539547
Short name T552
Test name
Test status
Simulation time 114362311 ps
CPU time 0.99 seconds
Started Jul 12 05:47:27 PM PDT 24
Finished Jul 12 05:47:29 PM PDT 24
Peak memory 200304 kb
Host smart-e5a645c2-dce2-4634-a5d9-17fa9854b3fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981539547 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3981539547
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2362790809
Short name T617
Test name
Test status
Simulation time 55151885 ps
CPU time 0.77 seconds
Started Jul 12 05:47:21 PM PDT 24
Finished Jul 12 05:47:23 PM PDT 24
Peak memory 200220 kb
Host smart-a3c4652c-10fa-4097-a61d-52b50a2d6559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362790809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2362790809
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2552610079
Short name T565
Test name
Test status
Simulation time 204403985 ps
CPU time 1.39 seconds
Started Jul 12 05:47:21 PM PDT 24
Finished Jul 12 05:47:23 PM PDT 24
Peak memory 200424 kb
Host smart-591fdf47-4e8a-4257-a215-c20778ac8de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552610079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2552610079
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1865007561
Short name T551
Test name
Test status
Simulation time 183697286 ps
CPU time 2.78 seconds
Started Jul 12 05:47:22 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 208424 kb
Host smart-507c5e0c-51ad-4fbd-839e-0ac0380d0764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865007561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1865007561
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.639154709
Short name T578
Test name
Test status
Simulation time 443915023 ps
CPU time 1.78 seconds
Started Jul 12 05:47:27 PM PDT 24
Finished Jul 12 05:47:29 PM PDT 24
Peak memory 200528 kb
Host smart-8d7d1130-1c4f-48af-809b-012ea7515cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639154709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
639154709
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4288606282
Short name T545
Test name
Test status
Simulation time 228290796 ps
CPU time 1.61 seconds
Started Jul 12 05:47:22 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 200316 kb
Host smart-8b024dc5-2a36-4239-8e42-3649a72e1255
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288606282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
288606282
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3188254384
Short name T609
Test name
Test status
Simulation time 489749874 ps
CPU time 5.59 seconds
Started Jul 12 05:47:21 PM PDT 24
Finished Jul 12 05:47:27 PM PDT 24
Peak memory 200388 kb
Host smart-c51c0fb5-c3d7-4929-a36d-8f2126a3d5c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188254384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
188254384
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.983563436
Short name T539
Test name
Test status
Simulation time 87441971 ps
CPU time 0.84 seconds
Started Jul 12 05:47:21 PM PDT 24
Finished Jul 12 05:47:23 PM PDT 24
Peak memory 200220 kb
Host smart-aa375fde-5178-4715-826f-e472b204ced8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983563436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.983563436
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2430795949
Short name T88
Test name
Test status
Simulation time 119831987 ps
CPU time 1.03 seconds
Started Jul 12 05:47:19 PM PDT 24
Finished Jul 12 05:47:21 PM PDT 24
Peak memory 200692 kb
Host smart-21a4ae7d-d989-41fb-93be-eb8dee6dbe5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430795949 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2430795949
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.613328622
Short name T94
Test name
Test status
Simulation time 69998393 ps
CPU time 0.83 seconds
Started Jul 12 05:47:20 PM PDT 24
Finished Jul 12 05:47:21 PM PDT 24
Peak memory 200176 kb
Host smart-c728f66f-6c0d-4018-92d1-725ce6cf5cfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613328622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.613328622
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3918002437
Short name T109
Test name
Test status
Simulation time 186993243 ps
CPU time 1.43 seconds
Started Jul 12 05:47:22 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 200584 kb
Host smart-90c934aa-5e11-4570-985d-6b8f7bec6e91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918002437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3918002437
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1311258564
Short name T591
Test name
Test status
Simulation time 436691045 ps
CPU time 2.95 seconds
Started Jul 12 05:47:22 PM PDT 24
Finished Jul 12 05:47:26 PM PDT 24
Peak memory 216904 kb
Host smart-3ed74ac8-5fd8-4007-9811-777067348b8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311258564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1311258564
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3588109724
Short name T587
Test name
Test status
Simulation time 420417760 ps
CPU time 1.7 seconds
Started Jul 12 05:47:20 PM PDT 24
Finished Jul 12 05:47:22 PM PDT 24
Peak memory 200456 kb
Host smart-20b7bc24-5b7d-4b24-9e5a-a4412c1d8abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588109724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3588109724
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1386912081
Short name T593
Test name
Test status
Simulation time 146707077 ps
CPU time 1.92 seconds
Started Jul 12 05:47:39 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 200392 kb
Host smart-c4e75c97-70fe-4f8c-8448-c300d5c103f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386912081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
386912081
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.380313254
Short name T583
Test name
Test status
Simulation time 2003383636 ps
CPU time 8.91 seconds
Started Jul 12 05:47:27 PM PDT 24
Finished Jul 12 05:47:36 PM PDT 24
Peak memory 200360 kb
Host smart-1b8ed82b-f454-4cc1-b00f-99ef0f0495ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380313254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.380313254
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3510103189
Short name T582
Test name
Test status
Simulation time 97192914 ps
CPU time 0.86 seconds
Started Jul 12 05:47:29 PM PDT 24
Finished Jul 12 05:47:31 PM PDT 24
Peak memory 200256 kb
Host smart-1116bbc5-6c84-4e5c-8d43-43bd4b927b38
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510103189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
510103189
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.195436772
Short name T550
Test name
Test status
Simulation time 166817999 ps
CPU time 1.2 seconds
Started Jul 12 05:47:28 PM PDT 24
Finished Jul 12 05:47:31 PM PDT 24
Peak memory 200336 kb
Host smart-45faa409-986f-4975-910d-b8b796488ddb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195436772 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.195436772
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3028891366
Short name T553
Test name
Test status
Simulation time 71154276 ps
CPU time 0.79 seconds
Started Jul 12 05:47:29 PM PDT 24
Finished Jul 12 05:47:31 PM PDT 24
Peak memory 200248 kb
Host smart-b3e1eda7-c3e3-4441-931e-219a80764120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028891366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3028891366
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.327798922
Short name T562
Test name
Test status
Simulation time 256030016 ps
CPU time 1.49 seconds
Started Jul 12 05:47:39 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 200408 kb
Host smart-853fb92d-4c84-4ebf-b384-810deecd6a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327798922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.327798922
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2193051147
Short name T618
Test name
Test status
Simulation time 437031349 ps
CPU time 1.77 seconds
Started Jul 12 05:47:20 PM PDT 24
Finished Jul 12 05:47:23 PM PDT 24
Peak memory 200352 kb
Host smart-c10ec657-fd82-4e0e-9045-15a7e67cb93d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193051147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2193051147
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3565644405
Short name T603
Test name
Test status
Simulation time 188992276 ps
CPU time 1.74 seconds
Started Jul 12 05:47:34 PM PDT 24
Finished Jul 12 05:47:38 PM PDT 24
Peak memory 213556 kb
Host smart-d4901a36-3fa9-48e4-b84f-fe66ed325dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565644405 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3565644405
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.735805019
Short name T107
Test name
Test status
Simulation time 59905329 ps
CPU time 0.75 seconds
Started Jul 12 05:47:27 PM PDT 24
Finished Jul 12 05:47:29 PM PDT 24
Peak memory 200024 kb
Host smart-e2cd6a55-1c47-450b-bbb4-cbabcb559c7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735805019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.735805019
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.363573341
Short name T67
Test name
Test status
Simulation time 147909148 ps
CPU time 1.12 seconds
Started Jul 12 05:47:38 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 200304 kb
Host smart-ffe4b4c0-46b7-4281-a2e0-0fc0f44fb35f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363573341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.363573341
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.744585076
Short name T559
Test name
Test status
Simulation time 435902728 ps
CPU time 2.86 seconds
Started Jul 12 05:47:27 PM PDT 24
Finished Jul 12 05:47:31 PM PDT 24
Peak memory 208560 kb
Host smart-87097317-3a01-4450-8ee9-c7abe63153cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744585076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.744585076
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3472083176
Short name T569
Test name
Test status
Simulation time 499249885 ps
CPU time 2.05 seconds
Started Jul 12 05:47:29 PM PDT 24
Finished Jul 12 05:47:33 PM PDT 24
Peak memory 200452 kb
Host smart-c96d5750-e89e-4ee5-a077-6d1bfae52f67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472083176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3472083176
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2026035625
Short name T544
Test name
Test status
Simulation time 125033160 ps
CPU time 0.92 seconds
Started Jul 12 05:47:31 PM PDT 24
Finished Jul 12 05:47:34 PM PDT 24
Peak memory 200292 kb
Host smart-4e088eb4-d21c-4804-997b-f48b6f4636f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026035625 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2026035625
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1364328214
Short name T66
Test name
Test status
Simulation time 83442509 ps
CPU time 0.82 seconds
Started Jul 12 05:47:27 PM PDT 24
Finished Jul 12 05:47:29 PM PDT 24
Peak memory 200168 kb
Host smart-d0367a99-5cb8-4eed-a616-60f0d3fd4c02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364328214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1364328214
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1405705632
Short name T557
Test name
Test status
Simulation time 75999066 ps
CPU time 1.01 seconds
Started Jul 12 05:47:27 PM PDT 24
Finished Jul 12 05:47:29 PM PDT 24
Peak memory 200516 kb
Host smart-d56f33cc-2d70-4706-9f0b-c31a8585d7e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405705632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1405705632
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3098744149
Short name T112
Test name
Test status
Simulation time 218035742 ps
CPU time 1.72 seconds
Started Jul 12 05:47:26 PM PDT 24
Finished Jul 12 05:47:29 PM PDT 24
Peak memory 208532 kb
Host smart-3229cda5-86b0-4d10-90d6-a8c09a42f8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098744149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3098744149
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1593310878
Short name T90
Test name
Test status
Simulation time 205120560 ps
CPU time 1.3 seconds
Started Jul 12 05:47:28 PM PDT 24
Finished Jul 12 05:47:31 PM PDT 24
Peak memory 208564 kb
Host smart-6ee1cef4-504e-4c29-a936-176e3c990219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593310878 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1593310878
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1535006872
Short name T563
Test name
Test status
Simulation time 68951356 ps
CPU time 0.81 seconds
Started Jul 12 05:47:28 PM PDT 24
Finished Jul 12 05:47:30 PM PDT 24
Peak memory 200236 kb
Host smart-5db3cf92-55d9-477b-b4d4-988162c2465d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535006872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1535006872
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1509447532
Short name T108
Test name
Test status
Simulation time 146614488 ps
CPU time 1.15 seconds
Started Jul 12 05:47:28 PM PDT 24
Finished Jul 12 05:47:31 PM PDT 24
Peak memory 200292 kb
Host smart-3439bad8-8ed7-4acc-83f7-dd76d00a9344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509447532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1509447532
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3114385981
Short name T91
Test name
Test status
Simulation time 121365518 ps
CPU time 1.73 seconds
Started Jul 12 05:47:29 PM PDT 24
Finished Jul 12 05:47:32 PM PDT 24
Peak memory 208708 kb
Host smart-b645ce6c-7e7a-4172-89c5-161e401d602b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114385981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3114385981
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.723025696
Short name T598
Test name
Test status
Simulation time 1079246775 ps
CPU time 3.15 seconds
Started Jul 12 05:47:39 PM PDT 24
Finished Jul 12 05:47:45 PM PDT 24
Peak memory 200444 kb
Host smart-8f4c3bcf-9d72-4cf2-a1a9-7f8775b18c51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723025696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
723025696
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3154637022
Short name T573
Test name
Test status
Simulation time 162480805 ps
CPU time 1.41 seconds
Started Jul 12 05:47:30 PM PDT 24
Finished Jul 12 05:47:32 PM PDT 24
Peak memory 200492 kb
Host smart-7b1832ec-0371-40bc-a515-d0597b5adab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154637022 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3154637022
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1966701889
Short name T594
Test name
Test status
Simulation time 76623029 ps
CPU time 0.8 seconds
Started Jul 12 05:47:26 PM PDT 24
Finished Jul 12 05:47:28 PM PDT 24
Peak memory 200128 kb
Host smart-dd40e248-4177-4cc9-98e1-6a6e9007e039
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966701889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1966701889
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1238608203
Short name T592
Test name
Test status
Simulation time 78400278 ps
CPU time 0.92 seconds
Started Jul 12 05:47:26 PM PDT 24
Finished Jul 12 05:47:28 PM PDT 24
Peak memory 200300 kb
Host smart-7a15e6cc-009d-4d51-b0b8-52217cee452d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238608203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1238608203
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2388379313
Short name T575
Test name
Test status
Simulation time 198654801 ps
CPU time 1.73 seconds
Started Jul 12 05:47:29 PM PDT 24
Finished Jul 12 05:47:32 PM PDT 24
Peak memory 208564 kb
Host smart-440e36ca-1ed1-4bfd-aac0-e5cacafb799e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388379313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2388379313
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2048115024
Short name T547
Test name
Test status
Simulation time 503287200 ps
CPU time 2.01 seconds
Started Jul 12 05:47:28 PM PDT 24
Finished Jul 12 05:47:31 PM PDT 24
Peak memory 200504 kb
Host smart-4622fc27-7556-4d14-927e-bef486ce4a65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048115024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2048115024
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1051375269
Short name T65
Test name
Test status
Simulation time 202077638 ps
CPU time 1.26 seconds
Started Jul 12 05:47:39 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 208568 kb
Host smart-39843e13-9bfd-48bd-bca8-d7f9006e8f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051375269 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1051375269
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.655548391
Short name T564
Test name
Test status
Simulation time 69188946 ps
CPU time 0.78 seconds
Started Jul 12 05:47:34 PM PDT 24
Finished Jul 12 05:47:37 PM PDT 24
Peak memory 200172 kb
Host smart-cd0fc319-cf82-4d72-b0fa-34e6681f2fd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655548391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.655548391
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2265891818
Short name T574
Test name
Test status
Simulation time 269947449 ps
CPU time 1.79 seconds
Started Jul 12 05:47:34 PM PDT 24
Finished Jul 12 05:47:38 PM PDT 24
Peak memory 200440 kb
Host smart-cf301617-c5f8-4279-ac6f-da19d502e459
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265891818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2265891818
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4112965141
Short name T93
Test name
Test status
Simulation time 527790184 ps
CPU time 3.5 seconds
Started Jul 12 05:47:25 PM PDT 24
Finished Jul 12 05:47:29 PM PDT 24
Peak memory 208520 kb
Host smart-0948c7bc-129b-4a19-9190-76eb416e1951
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112965141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4112965141
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.4036976015
Short name T531
Test name
Test status
Simulation time 1233243190 ps
CPU time 5.81 seconds
Started Jul 12 05:47:44 PM PDT 24
Finished Jul 12 05:47:51 PM PDT 24
Peak memory 217796 kb
Host smart-3324d185-7f46-4893-9373-6a5351eb27f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036976015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.4036976015
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1963171434
Short name T328
Test name
Test status
Simulation time 243622875 ps
CPU time 1.03 seconds
Started Jul 12 05:47:44 PM PDT 24
Finished Jul 12 05:47:46 PM PDT 24
Peak memory 217460 kb
Host smart-3b173b38-eaf1-4cbe-9b7e-b576394ac1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963171434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1963171434
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.118602934
Short name T475
Test name
Test status
Simulation time 107439747 ps
CPU time 0.75 seconds
Started Jul 12 05:47:40 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 199904 kb
Host smart-00048444-b967-40ee-97d6-1489d4b26c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118602934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.118602934
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1663336136
Short name T504
Test name
Test status
Simulation time 922588918 ps
CPU time 4.42 seconds
Started Jul 12 05:47:39 PM PDT 24
Finished Jul 12 05:47:47 PM PDT 24
Peak memory 200304 kb
Host smart-28c5936f-be1b-4ac3-b5e9-8970c9c0e179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663336136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1663336136
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.893935094
Short name T77
Test name
Test status
Simulation time 8483483107 ps
CPU time 13.37 seconds
Started Jul 12 05:47:44 PM PDT 24
Finished Jul 12 05:47:59 PM PDT 24
Peak memory 217336 kb
Host smart-bd74620a-e40b-4d95-b056-f5069abb2c7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893935094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.893935094
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.4035256635
Short name T483
Test name
Test status
Simulation time 187775113 ps
CPU time 1.38 seconds
Started Jul 12 05:47:39 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 200280 kb
Host smart-9788e492-5968-4999-82cd-f85587a6cbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035256635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.4035256635
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1538721824
Short name T529
Test name
Test status
Simulation time 8099507570 ps
CPU time 28.26 seconds
Started Jul 12 05:47:43 PM PDT 24
Finished Jul 12 05:48:13 PM PDT 24
Peak memory 200416 kb
Host smart-6919c42a-dd67-4a09-9424-c2e65bb9dfc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538721824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1538721824
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1039450029
Short name T11
Test name
Test status
Simulation time 421110001 ps
CPU time 2.32 seconds
Started Jul 12 05:47:38 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 208284 kb
Host smart-721bfc59-bf2b-4c84-8d4d-dc8a125f55e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039450029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1039450029
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.331090253
Short name T451
Test name
Test status
Simulation time 150534488 ps
CPU time 1.24 seconds
Started Jul 12 05:47:39 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 200080 kb
Host smart-bbcd9c6d-dabf-400b-8fbb-73986cd65ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331090253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.331090253
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3703259527
Short name T178
Test name
Test status
Simulation time 79195804 ps
CPU time 0.8 seconds
Started Jul 12 05:47:46 PM PDT 24
Finished Jul 12 05:47:48 PM PDT 24
Peak memory 199780 kb
Host smart-d00e7b9b-d2de-4dea-b3be-e59d4127b988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703259527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3703259527
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.290569207
Short name T37
Test name
Test status
Simulation time 244154212 ps
CPU time 1.18 seconds
Started Jul 12 05:47:41 PM PDT 24
Finished Jul 12 05:47:44 PM PDT 24
Peak memory 217356 kb
Host smart-693c00a6-c3ce-44d4-a7b7-fa2fdd6ac34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290569207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.290569207
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1357518086
Short name T303
Test name
Test status
Simulation time 149313764 ps
CPU time 0.83 seconds
Started Jul 12 05:47:44 PM PDT 24
Finished Jul 12 05:47:46 PM PDT 24
Peak memory 199920 kb
Host smart-b228a613-9df0-4283-9b7b-a87580e5358e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357518086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1357518086
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3183534062
Short name T4
Test name
Test status
Simulation time 1509837014 ps
CPU time 5.87 seconds
Started Jul 12 05:47:43 PM PDT 24
Finished Jul 12 05:47:51 PM PDT 24
Peak memory 200288 kb
Host smart-533f69e7-9fdd-4223-a6ec-fa27074630a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183534062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3183534062
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.805393782
Short name T393
Test name
Test status
Simulation time 104741388 ps
CPU time 0.98 seconds
Started Jul 12 05:47:44 PM PDT 24
Finished Jul 12 05:47:46 PM PDT 24
Peak memory 200124 kb
Host smart-2a995083-da32-4c61-a80a-7d0f604f28a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805393782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.805393782
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1546557596
Short name T183
Test name
Test status
Simulation time 115443562 ps
CPU time 1.22 seconds
Started Jul 12 05:47:43 PM PDT 24
Finished Jul 12 05:47:46 PM PDT 24
Peak memory 200204 kb
Host smart-64cca033-2310-4f9c-a5c0-209ddc788c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546557596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1546557596
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3183217227
Short name T302
Test name
Test status
Simulation time 5337065024 ps
CPU time 20.15 seconds
Started Jul 12 05:47:43 PM PDT 24
Finished Jul 12 05:48:04 PM PDT 24
Peak memory 208656 kb
Host smart-f9a7f5d4-1fc1-424c-8958-2c81e5bfa0b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183217227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3183217227
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1366747491
Short name T182
Test name
Test status
Simulation time 410084940 ps
CPU time 2.16 seconds
Started Jul 12 05:47:43 PM PDT 24
Finished Jul 12 05:47:46 PM PDT 24
Peak memory 208244 kb
Host smart-021f6b34-bda6-46a4-9f88-890f344ee081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366747491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1366747491
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1554410196
Short name T25
Test name
Test status
Simulation time 91829105 ps
CPU time 0.88 seconds
Started Jul 12 05:47:43 PM PDT 24
Finished Jul 12 05:47:46 PM PDT 24
Peak memory 200076 kb
Host smart-e4e91084-57a3-4a03-92ad-f40862647aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554410196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1554410196
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1046227657
Short name T512
Test name
Test status
Simulation time 58038309 ps
CPU time 0.79 seconds
Started Jul 12 05:48:07 PM PDT 24
Finished Jul 12 05:48:10 PM PDT 24
Peak memory 199784 kb
Host smart-c9c870e6-c80e-4d3a-8a89-46690a72be53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046227657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1046227657
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2023000095
Short name T373
Test name
Test status
Simulation time 2360013623 ps
CPU time 7.89 seconds
Started Jul 12 05:48:01 PM PDT 24
Finished Jul 12 05:48:12 PM PDT 24
Peak memory 217780 kb
Host smart-a9107e02-f5d3-445f-a045-62dbde9fd18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023000095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2023000095
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.967220382
Short name T264
Test name
Test status
Simulation time 243984680 ps
CPU time 1.05 seconds
Started Jul 12 05:48:06 PM PDT 24
Finished Jul 12 05:48:08 PM PDT 24
Peak memory 217448 kb
Host smart-fb8d3ea4-7971-4a5a-af87-60948635de22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967220382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.967220382
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3031611950
Short name T428
Test name
Test status
Simulation time 203066420 ps
CPU time 0.87 seconds
Started Jul 12 05:48:01 PM PDT 24
Finished Jul 12 05:48:04 PM PDT 24
Peak memory 199904 kb
Host smart-ff1c78b0-742a-4992-b440-ab9d4cce5a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031611950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3031611950
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2065442982
Short name T100
Test name
Test status
Simulation time 1004113287 ps
CPU time 4.83 seconds
Started Jul 12 05:48:03 PM PDT 24
Finished Jul 12 05:48:10 PM PDT 24
Peak memory 200228 kb
Host smart-d4713f97-0267-49f0-ad56-660fb43763e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065442982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2065442982
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2948503374
Short name T411
Test name
Test status
Simulation time 144701959 ps
CPU time 1.15 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:02 PM PDT 24
Peak memory 200012 kb
Host smart-6aed9531-3ad6-4e2a-8ebc-30c2728adef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948503374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2948503374
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.701310865
Short name T267
Test name
Test status
Simulation time 239739190 ps
CPU time 1.45 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:03 PM PDT 24
Peak memory 200264 kb
Host smart-d3e72ae4-0b80-4f01-8d99-5fc12c876e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701310865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.701310865
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1262073858
Short name T353
Test name
Test status
Simulation time 1776297576 ps
CPU time 8.47 seconds
Started Jul 12 05:48:06 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 200320 kb
Host smart-0a9f1ccc-ab03-4d4c-aa8c-d593badcf22c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262073858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1262073858
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2113631086
Short name T532
Test name
Test status
Simulation time 313652891 ps
CPU time 2.03 seconds
Started Jul 12 05:48:02 PM PDT 24
Finished Jul 12 05:48:07 PM PDT 24
Peak memory 208288 kb
Host smart-ddf869d1-db59-426b-9468-1ea9a4fa2e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113631086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2113631086
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.759062057
Short name T496
Test name
Test status
Simulation time 81749168 ps
CPU time 0.89 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:02 PM PDT 24
Peak memory 200080 kb
Host smart-45904f8c-fe10-4d92-bcf5-5a5d3c8f92fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759062057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.759062057
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.147152569
Short name T429
Test name
Test status
Simulation time 76207124 ps
CPU time 0.81 seconds
Started Jul 12 05:48:08 PM PDT 24
Finished Jul 12 05:48:11 PM PDT 24
Peak memory 199876 kb
Host smart-b55ccf20-5811-4c95-bc46-36311c1751aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147152569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.147152569
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3778631217
Short name T345
Test name
Test status
Simulation time 1226961843 ps
CPU time 6.04 seconds
Started Jul 12 05:48:08 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 221608 kb
Host smart-ae21198c-b032-4bcd-8ad1-b91a32c946c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778631217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3778631217
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1505599434
Short name T3
Test name
Test status
Simulation time 244405006 ps
CPU time 1.13 seconds
Started Jul 12 05:48:07 PM PDT 24
Finished Jul 12 05:48:10 PM PDT 24
Peak memory 217708 kb
Host smart-0e17433b-b94a-4087-93d0-7efc83a122b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505599434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1505599434
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1991882983
Short name T364
Test name
Test status
Simulation time 93945290 ps
CPU time 0.77 seconds
Started Jul 12 05:48:11 PM PDT 24
Finished Jul 12 05:48:13 PM PDT 24
Peak memory 200004 kb
Host smart-f9086852-b376-4475-8cf1-5670d3d49fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991882983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1991882983
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.512209015
Short name T284
Test name
Test status
Simulation time 869823556 ps
CPU time 3.95 seconds
Started Jul 12 05:48:06 PM PDT 24
Finished Jul 12 05:48:12 PM PDT 24
Peak memory 200288 kb
Host smart-9b80471e-b165-44aa-9be7-c3982ff57f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512209015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.512209015
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2128941709
Short name T463
Test name
Test status
Simulation time 178118481 ps
CPU time 1.18 seconds
Started Jul 12 05:48:09 PM PDT 24
Finished Jul 12 05:48:11 PM PDT 24
Peak memory 200088 kb
Host smart-369b52de-e618-4412-bf8e-63765ca8c2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128941709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2128941709
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1425586934
Short name T13
Test name
Test status
Simulation time 126827374 ps
CPU time 1.21 seconds
Started Jul 12 05:48:08 PM PDT 24
Finished Jul 12 05:48:11 PM PDT 24
Peak memory 200236 kb
Host smart-f193cc5e-68ca-46f8-abbe-28e8c1eb2f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425586934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1425586934
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1810575086
Short name T87
Test name
Test status
Simulation time 2670632669 ps
CPU time 12.59 seconds
Started Jul 12 05:48:06 PM PDT 24
Finished Jul 12 05:48:20 PM PDT 24
Peak memory 208592 kb
Host smart-918d9d0e-6032-4da5-a8ba-ed282b9eaf8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810575086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1810575086
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.716465176
Short name T129
Test name
Test status
Simulation time 435274624 ps
CPU time 2.48 seconds
Started Jul 12 05:48:06 PM PDT 24
Finished Jul 12 05:48:10 PM PDT 24
Peak memory 200056 kb
Host smart-6acc4a2a-9e93-46de-aeee-a809b212e6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716465176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.716465176
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1261486486
Short name T163
Test name
Test status
Simulation time 83326120 ps
CPU time 0.84 seconds
Started Jul 12 05:48:05 PM PDT 24
Finished Jul 12 05:48:08 PM PDT 24
Peak memory 199884 kb
Host smart-0c66e010-a0da-463e-baf0-04d71d6946b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261486486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1261486486
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.843793782
Short name T51
Test name
Test status
Simulation time 2359467860 ps
CPU time 8.97 seconds
Started Jul 12 05:48:13 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 217784 kb
Host smart-f2b93922-b30b-4b65-8dca-535512ff69dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843793782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.843793782
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.529187547
Short name T286
Test name
Test status
Simulation time 244321334 ps
CPU time 1.03 seconds
Started Jul 12 05:48:06 PM PDT 24
Finished Jul 12 05:48:09 PM PDT 24
Peak memory 217364 kb
Host smart-6270974d-b43a-422d-973c-1b3ed8369d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529187547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.529187547
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3243020074
Short name T246
Test name
Test status
Simulation time 88497593 ps
CPU time 0.74 seconds
Started Jul 12 05:48:07 PM PDT 24
Finished Jul 12 05:48:10 PM PDT 24
Peak memory 199904 kb
Host smart-d220bdfb-d1ef-4b73-8943-62db1ed74971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243020074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3243020074
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3874607958
Short name T275
Test name
Test status
Simulation time 1330295282 ps
CPU time 5.46 seconds
Started Jul 12 05:48:09 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 200332 kb
Host smart-1c76d23f-4217-4d99-a670-c25cac60a0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874607958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3874607958
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3455634919
Short name T41
Test name
Test status
Simulation time 146986038 ps
CPU time 1.2 seconds
Started Jul 12 05:48:12 PM PDT 24
Finished Jul 12 05:48:15 PM PDT 24
Peak memory 200032 kb
Host smart-58092f9a-e76f-4c6f-bf34-f2493a93b232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455634919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3455634919
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2730325038
Short name T38
Test name
Test status
Simulation time 201189476 ps
CPU time 1.33 seconds
Started Jul 12 05:48:08 PM PDT 24
Finished Jul 12 05:48:11 PM PDT 24
Peak memory 200288 kb
Host smart-3f2a32e8-c3ea-4e65-8aef-e73953635676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730325038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2730325038
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3526597116
Short name T435
Test name
Test status
Simulation time 197656246 ps
CPU time 1.24 seconds
Started Jul 12 05:48:04 PM PDT 24
Finished Jul 12 05:48:07 PM PDT 24
Peak memory 199884 kb
Host smart-c4a33b9e-78d2-4594-89cc-e8c77234ddea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526597116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3526597116
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3018687855
Short name T257
Test name
Test status
Simulation time 384827863 ps
CPU time 2.33 seconds
Started Jul 12 05:48:09 PM PDT 24
Finished Jul 12 05:48:13 PM PDT 24
Peak memory 200060 kb
Host smart-6592355f-43c3-49f1-a3d5-c7733ef9d568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018687855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3018687855
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.801216413
Short name T358
Test name
Test status
Simulation time 198370699 ps
CPU time 1.33 seconds
Started Jul 12 05:48:08 PM PDT 24
Finished Jul 12 05:48:10 PM PDT 24
Peak memory 200104 kb
Host smart-1556d450-cd02-4e09-8b79-340fda24a47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801216413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.801216413
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1152659472
Short name T217
Test name
Test status
Simulation time 70615488 ps
CPU time 0.79 seconds
Started Jul 12 05:48:05 PM PDT 24
Finished Jul 12 05:48:08 PM PDT 24
Peak memory 199892 kb
Host smart-6fd17a2f-8d9d-4e0c-861c-a05a662f46bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152659472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1152659472
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3917131907
Short name T394
Test name
Test status
Simulation time 1880221938 ps
CPU time 7.2 seconds
Started Jul 12 05:48:08 PM PDT 24
Finished Jul 12 05:48:17 PM PDT 24
Peak memory 221668 kb
Host smart-1ebfde8b-7ed9-461d-98d9-3001eb2681ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917131907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3917131907
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.184999898
Short name T516
Test name
Test status
Simulation time 244152927 ps
CPU time 1.17 seconds
Started Jul 12 05:48:08 PM PDT 24
Finished Jul 12 05:48:11 PM PDT 24
Peak memory 217440 kb
Host smart-13129b63-ec12-4945-88a6-8dab6c7faac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184999898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.184999898
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.4281699437
Short name T211
Test name
Test status
Simulation time 181118340 ps
CPU time 0.87 seconds
Started Jul 12 05:48:07 PM PDT 24
Finished Jul 12 05:48:09 PM PDT 24
Peak memory 199920 kb
Host smart-7acb91ac-b050-4d90-90f1-15dc268f7e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281699437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.4281699437
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3039910984
Short name T198
Test name
Test status
Simulation time 687568047 ps
CPU time 3.48 seconds
Started Jul 12 05:48:07 PM PDT 24
Finished Jul 12 05:48:12 PM PDT 24
Peak memory 200352 kb
Host smart-5a171f64-c75f-46ef-aab7-73789372914d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039910984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3039910984
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.955071664
Short name T194
Test name
Test status
Simulation time 157029212 ps
CPU time 1.17 seconds
Started Jul 12 05:48:11 PM PDT 24
Finished Jul 12 05:48:13 PM PDT 24
Peak memory 200208 kb
Host smart-28318442-008c-48fd-b9bb-fc363b0315b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955071664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.955071664
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.424497307
Short name T410
Test name
Test status
Simulation time 187992009 ps
CPU time 1.37 seconds
Started Jul 12 05:48:07 PM PDT 24
Finished Jul 12 05:48:10 PM PDT 24
Peak memory 200276 kb
Host smart-a6d56e26-2cd4-42ad-99d9-eee78f94a627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424497307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.424497307
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.201864069
Short name T124
Test name
Test status
Simulation time 6886922464 ps
CPU time 25 seconds
Started Jul 12 05:48:13 PM PDT 24
Finished Jul 12 05:48:39 PM PDT 24
Peak memory 200352 kb
Host smart-d2b59f6b-14d5-4b70-8273-ddd5bc8170ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201864069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.201864069
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.951973597
Short name T196
Test name
Test status
Simulation time 289706501 ps
CPU time 2.14 seconds
Started Jul 12 05:48:07 PM PDT 24
Finished Jul 12 05:48:10 PM PDT 24
Peak memory 200032 kb
Host smart-3be1fece-0832-4d03-840f-ab2f61eafb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951973597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.951973597
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1937013279
Short name T166
Test name
Test status
Simulation time 78616381 ps
CPU time 0.83 seconds
Started Jul 12 05:48:09 PM PDT 24
Finished Jul 12 05:48:12 PM PDT 24
Peak memory 200092 kb
Host smart-e84bdab7-461b-413a-914d-7945dd9f6c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937013279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1937013279
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2837538549
Short name T380
Test name
Test status
Simulation time 57025109 ps
CPU time 0.72 seconds
Started Jul 12 05:48:12 PM PDT 24
Finished Jul 12 05:48:14 PM PDT 24
Peak memory 199896 kb
Host smart-385d3e25-9135-42bc-a15a-368bfb873d0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837538549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2837538549
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3886479955
Short name T479
Test name
Test status
Simulation time 244280921 ps
CPU time 1.08 seconds
Started Jul 12 05:48:14 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 217460 kb
Host smart-ee5bab11-6b75-4b4b-8c09-33538d2462c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886479955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3886479955
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3130222432
Short name T525
Test name
Test status
Simulation time 210113075 ps
CPU time 0.89 seconds
Started Jul 12 05:48:07 PM PDT 24
Finished Jul 12 05:48:09 PM PDT 24
Peak memory 200124 kb
Host smart-d9ebde4f-d717-459e-a1d2-82dd60e83d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130222432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3130222432
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1003352874
Short name T132
Test name
Test status
Simulation time 1394457262 ps
CPU time 5.54 seconds
Started Jul 12 05:48:08 PM PDT 24
Finished Jul 12 05:48:15 PM PDT 24
Peak memory 200288 kb
Host smart-c6a71647-1f30-4e5f-8e5c-c68ea3d97619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003352874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1003352874
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2966460398
Short name T537
Test name
Test status
Simulation time 97772673 ps
CPU time 1.02 seconds
Started Jul 12 05:48:07 PM PDT 24
Finished Jul 12 05:48:09 PM PDT 24
Peak memory 200032 kb
Host smart-b9951c0b-439e-42f0-a715-746085216e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966460398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2966460398
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3811474180
Short name T378
Test name
Test status
Simulation time 247405745 ps
CPU time 1.44 seconds
Started Jul 12 05:48:08 PM PDT 24
Finished Jul 12 05:48:11 PM PDT 24
Peak memory 200296 kb
Host smart-e1a5a37f-5a1a-4bde-94a1-4bed27f693a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811474180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3811474180
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.968394973
Short name T165
Test name
Test status
Simulation time 152485670 ps
CPU time 1.09 seconds
Started Jul 12 05:48:12 PM PDT 24
Finished Jul 12 05:48:14 PM PDT 24
Peak memory 200068 kb
Host smart-c4483587-5bae-47e0-bf0d-ff86f82437ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968394973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.968394973
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3789495595
Short name T325
Test name
Test status
Simulation time 128942332 ps
CPU time 1.5 seconds
Started Jul 12 05:48:06 PM PDT 24
Finished Jul 12 05:48:09 PM PDT 24
Peak memory 200088 kb
Host smart-724cccbd-bde3-46f4-97b2-44203808ac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789495595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3789495595
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3426717803
Short name T301
Test name
Test status
Simulation time 194355725 ps
CPU time 1.2 seconds
Started Jul 12 05:48:07 PM PDT 24
Finished Jul 12 05:48:10 PM PDT 24
Peak memory 200100 kb
Host smart-dba636b9-91a5-45c7-892c-8ba1555c8a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426717803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3426717803
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2170065586
Short name T58
Test name
Test status
Simulation time 76122686 ps
CPU time 0.75 seconds
Started Jul 12 05:48:13 PM PDT 24
Finished Jul 12 05:48:15 PM PDT 24
Peak memory 199808 kb
Host smart-9c5a82d5-c25a-455c-b128-8a18827cfb7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170065586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2170065586
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1119142109
Short name T28
Test name
Test status
Simulation time 1888506424 ps
CPU time 7.73 seconds
Started Jul 12 05:48:15 PM PDT 24
Finished Jul 12 05:48:25 PM PDT 24
Peak memory 217448 kb
Host smart-8b3e42bd-2ef4-4b19-837a-5f3ad58b0565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119142109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1119142109
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2508117932
Short name T413
Test name
Test status
Simulation time 243619171 ps
CPU time 1.2 seconds
Started Jul 12 05:48:13 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 217420 kb
Host smart-40b82699-6691-4e33-9d05-bb577435f40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508117932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2508117932
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3506679154
Short name T486
Test name
Test status
Simulation time 220900014 ps
CPU time 0.9 seconds
Started Jul 12 05:48:18 PM PDT 24
Finished Jul 12 05:48:19 PM PDT 24
Peak memory 199868 kb
Host smart-54953edc-482f-4a5f-90f0-78c099590e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506679154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3506679154
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3069672673
Short name T521
Test name
Test status
Simulation time 857119392 ps
CPU time 4.58 seconds
Started Jul 12 05:48:16 PM PDT 24
Finished Jul 12 05:48:22 PM PDT 24
Peak memory 200376 kb
Host smart-d1d274d4-49e1-436c-84e7-252465b017a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069672673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3069672673
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2683623242
Short name T312
Test name
Test status
Simulation time 150607395 ps
CPU time 1.11 seconds
Started Jul 12 05:48:13 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 200056 kb
Host smart-089414d0-e248-44ed-ae7f-7efb5c5d920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683623242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2683623242
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1284714298
Short name T347
Test name
Test status
Simulation time 248281287 ps
CPU time 1.47 seconds
Started Jul 12 05:48:15 PM PDT 24
Finished Jul 12 05:48:18 PM PDT 24
Peak memory 200196 kb
Host smart-5f8c3385-c721-4c9d-8a76-85c469416f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284714298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1284714298
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2912183741
Short name T238
Test name
Test status
Simulation time 351868828 ps
CPU time 2.22 seconds
Started Jul 12 05:48:16 PM PDT 24
Finished Jul 12 05:48:19 PM PDT 24
Peak memory 200220 kb
Host smart-196f9598-2a4c-453c-92ae-c78b320c7dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912183741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2912183741
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.4031452354
Short name T229
Test name
Test status
Simulation time 79484999 ps
CPU time 0.8 seconds
Started Jul 12 05:48:12 PM PDT 24
Finished Jul 12 05:48:14 PM PDT 24
Peak memory 200092 kb
Host smart-207d22af-e8fa-4aa5-9d9d-0ba527568a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031452354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.4031452354
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.329473104
Short name T305
Test name
Test status
Simulation time 60109063 ps
CPU time 0.8 seconds
Started Jul 12 05:48:15 PM PDT 24
Finished Jul 12 05:48:17 PM PDT 24
Peak memory 199896 kb
Host smart-4c1f482b-bf07-4932-96f0-3b952f3220ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329473104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.329473104
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1204647534
Short name T417
Test name
Test status
Simulation time 1229626024 ps
CPU time 5.54 seconds
Started Jul 12 05:48:14 PM PDT 24
Finished Jul 12 05:48:21 PM PDT 24
Peak memory 217528 kb
Host smart-bc90c824-5d5a-498b-885c-d4858926d816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204647534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1204647534
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1749249867
Short name T155
Test name
Test status
Simulation time 244071637 ps
CPU time 1.05 seconds
Started Jul 12 05:48:11 PM PDT 24
Finished Jul 12 05:48:14 PM PDT 24
Peak memory 217432 kb
Host smart-4668ed0d-296d-4935-84f9-be340c2d14a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749249867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1749249867
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1401293917
Short name T326
Test name
Test status
Simulation time 75780603 ps
CPU time 0.75 seconds
Started Jul 12 05:48:16 PM PDT 24
Finished Jul 12 05:48:18 PM PDT 24
Peak memory 199936 kb
Host smart-8e28236d-b821-4b90-b5d6-9047dde61d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401293917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1401293917
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1752244081
Short name T99
Test name
Test status
Simulation time 1577961133 ps
CPU time 6.25 seconds
Started Jul 12 05:48:12 PM PDT 24
Finished Jul 12 05:48:19 PM PDT 24
Peak memory 200340 kb
Host smart-681d7802-6b1a-4509-b382-4f22aeec7137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752244081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1752244081
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2398277452
Short name T172
Test name
Test status
Simulation time 178859195 ps
CPU time 1.22 seconds
Started Jul 12 05:48:12 PM PDT 24
Finished Jul 12 05:48:14 PM PDT 24
Peak memory 200072 kb
Host smart-ad8da53c-2409-47eb-be97-84643d4f602a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398277452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2398277452
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.646168503
Short name T127
Test name
Test status
Simulation time 229573554 ps
CPU time 1.41 seconds
Started Jul 12 05:48:18 PM PDT 24
Finished Jul 12 05:48:20 PM PDT 24
Peak memory 200284 kb
Host smart-d45cfc6c-a130-46ad-ac99-82f1b25cb83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646168503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.646168503
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2511872801
Short name T336
Test name
Test status
Simulation time 9647909153 ps
CPU time 33.79 seconds
Started Jul 12 05:48:13 PM PDT 24
Finished Jul 12 05:48:49 PM PDT 24
Peak memory 200336 kb
Host smart-242fbb8d-e1b6-4317-83d1-abe511517e8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511872801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2511872801
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.4028955403
Short name T420
Test name
Test status
Simulation time 273704798 ps
CPU time 1.86 seconds
Started Jul 12 05:48:12 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 200100 kb
Host smart-015a0478-856f-441b-907c-3ca2b20b40e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028955403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4028955403
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.99353519
Short name T283
Test name
Test status
Simulation time 111408932 ps
CPU time 0.94 seconds
Started Jul 12 05:48:10 PM PDT 24
Finished Jul 12 05:48:12 PM PDT 24
Peak memory 200124 kb
Host smart-0e0605c0-1a7c-451f-8ef5-5824a9ee44ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99353519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.99353519
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.333449177
Short name T523
Test name
Test status
Simulation time 85416139 ps
CPU time 0.88 seconds
Started Jul 12 05:48:19 PM PDT 24
Finished Jul 12 05:48:21 PM PDT 24
Peak memory 199884 kb
Host smart-4abc00a7-8335-4007-b048-bd5bd1cfe1cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333449177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.333449177
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1614991098
Short name T35
Test name
Test status
Simulation time 1222962349 ps
CPU time 5.52 seconds
Started Jul 12 05:48:14 PM PDT 24
Finished Jul 12 05:48:21 PM PDT 24
Peak memory 217520 kb
Host smart-fafefa9b-bc4a-441b-aead-224c0bfb3c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614991098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1614991098
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2807076762
Short name T244
Test name
Test status
Simulation time 244650939 ps
CPU time 1.08 seconds
Started Jul 12 05:48:16 PM PDT 24
Finished Jul 12 05:48:19 PM PDT 24
Peak memory 217464 kb
Host smart-344ec0da-ff71-4c1f-b53b-c8cbcf3cec10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807076762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2807076762
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3868702038
Short name T346
Test name
Test status
Simulation time 219080358 ps
CPU time 0.91 seconds
Started Jul 12 05:48:16 PM PDT 24
Finished Jul 12 05:48:18 PM PDT 24
Peak memory 199936 kb
Host smart-0f32dadb-c218-4ce3-bca9-c3b673655ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868702038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3868702038
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3823651338
Short name T98
Test name
Test status
Simulation time 898361793 ps
CPU time 4.83 seconds
Started Jul 12 05:48:16 PM PDT 24
Finished Jul 12 05:48:22 PM PDT 24
Peak memory 200360 kb
Host smart-07297475-0b6a-4a66-9b20-efa38fd51347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823651338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3823651338
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.925880257
Short name T143
Test name
Test status
Simulation time 181566587 ps
CPU time 1.2 seconds
Started Jul 12 05:48:13 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 200056 kb
Host smart-0b04902b-b2d8-4fb2-b6a2-579876f15f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925880257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.925880257
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2432560200
Short name T174
Test name
Test status
Simulation time 108283989 ps
CPU time 1.35 seconds
Started Jul 12 05:48:15 PM PDT 24
Finished Jul 12 05:48:18 PM PDT 24
Peak memory 200236 kb
Host smart-9867d1af-3af1-4dc1-b8bb-c70fcd251f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432560200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2432560200
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1313072397
Short name T412
Test name
Test status
Simulation time 7145122645 ps
CPU time 29.98 seconds
Started Jul 12 05:48:15 PM PDT 24
Finished Jul 12 05:48:47 PM PDT 24
Peak memory 208608 kb
Host smart-a411481a-2397-4e99-ad26-2514ad4e2d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313072397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1313072397
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2434518978
Short name T192
Test name
Test status
Simulation time 110329589 ps
CPU time 1.46 seconds
Started Jul 12 05:48:14 PM PDT 24
Finished Jul 12 05:48:17 PM PDT 24
Peak memory 200100 kb
Host smart-89e2f008-ac52-4e59-b688-91675383990f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434518978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2434518978
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2207637787
Short name T423
Test name
Test status
Simulation time 173872054 ps
CPU time 1.18 seconds
Started Jul 12 05:48:14 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 200080 kb
Host smart-4ac9b07b-7a8e-4291-8bd5-8bf1dc07a6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207637787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2207637787
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1656612869
Short name T139
Test name
Test status
Simulation time 82821074 ps
CPU time 0.82 seconds
Started Jul 12 05:48:27 PM PDT 24
Finished Jul 12 05:48:29 PM PDT 24
Peak memory 199900 kb
Host smart-a835834a-de46-4920-a4e3-197e84c970f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656612869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1656612869
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.161938556
Short name T511
Test name
Test status
Simulation time 244237183 ps
CPU time 1.06 seconds
Started Jul 12 05:48:17 PM PDT 24
Finished Jul 12 05:48:19 PM PDT 24
Peak memory 217300 kb
Host smart-ff816442-3e6c-4038-8b8a-aed80a6229ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161938556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.161938556
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_reset.4236321560
Short name T372
Test name
Test status
Simulation time 1362379918 ps
CPU time 5.35 seconds
Started Jul 12 05:48:15 PM PDT 24
Finished Jul 12 05:48:22 PM PDT 24
Peak memory 200304 kb
Host smart-b5b8e0f6-dae6-462c-831e-94a18bf3c874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236321560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.4236321560
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2583736
Short name T492
Test name
Test status
Simulation time 191204238 ps
CPU time 1.28 seconds
Started Jul 12 05:48:14 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 200340 kb
Host smart-03d09233-bb54-4fe1-8ff4-aac2d45bea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2583736
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.4250501739
Short name T470
Test name
Test status
Simulation time 110415518 ps
CPU time 1.2 seconds
Started Jul 12 05:48:16 PM PDT 24
Finished Jul 12 05:48:18 PM PDT 24
Peak memory 200296 kb
Host smart-1cbd20b6-9847-45d9-a1f8-4a99b18a2077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250501739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.4250501739
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2752247966
Short name T314
Test name
Test status
Simulation time 3185671290 ps
CPU time 11.85 seconds
Started Jul 12 05:48:14 PM PDT 24
Finished Jul 12 05:48:27 PM PDT 24
Peak memory 208908 kb
Host smart-6753e3e4-7e00-4eb5-bd82-83bee763028f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752247966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2752247966
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2005195078
Short name T361
Test name
Test status
Simulation time 142748500 ps
CPU time 1.84 seconds
Started Jul 12 05:48:15 PM PDT 24
Finished Jul 12 05:48:19 PM PDT 24
Peak memory 200096 kb
Host smart-6067fa15-da07-485a-a27f-ba52be292c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005195078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2005195078
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.306138622
Short name T389
Test name
Test status
Simulation time 68814451 ps
CPU time 0.78 seconds
Started Jul 12 05:48:19 PM PDT 24
Finished Jul 12 05:48:22 PM PDT 24
Peak memory 200088 kb
Host smart-2d47478b-6ef4-4870-be73-89e3420301fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306138622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.306138622
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.4219517684
Short name T146
Test name
Test status
Simulation time 61317854 ps
CPU time 0.71 seconds
Started Jul 12 05:48:18 PM PDT 24
Finished Jul 12 05:48:20 PM PDT 24
Peak memory 199828 kb
Host smart-0f3af51d-d0d5-4ee7-9ba5-dca1c07ee70a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219517684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4219517684
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3751501947
Short name T433
Test name
Test status
Simulation time 1891470904 ps
CPU time 7.65 seconds
Started Jul 12 05:48:20 PM PDT 24
Finished Jul 12 05:48:30 PM PDT 24
Peak memory 221772 kb
Host smart-7432725f-65e1-4de0-b9d7-709cb596402f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751501947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3751501947
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.256002817
Short name T538
Test name
Test status
Simulation time 248238110 ps
CPU time 1.13 seconds
Started Jul 12 05:48:31 PM PDT 24
Finished Jul 12 05:48:33 PM PDT 24
Peak memory 217324 kb
Host smart-ff4d7c90-415f-4a10-a922-71737f6e4bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256002817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.256002817
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1687443908
Short name T468
Test name
Test status
Simulation time 99697125 ps
CPU time 0.79 seconds
Started Jul 12 05:48:19 PM PDT 24
Finished Jul 12 05:48:21 PM PDT 24
Peak memory 199920 kb
Host smart-85d312d4-9e6d-4d5e-bf63-01b88efc8900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687443908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1687443908
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.14889792
Short name T387
Test name
Test status
Simulation time 720959840 ps
CPU time 3.82 seconds
Started Jul 12 05:48:19 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 200360 kb
Host smart-95965c92-9c75-4c7e-8fca-2bc9e21bcda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14889792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.14889792
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3201675293
Short name T63
Test name
Test status
Simulation time 96109470 ps
CPU time 0.98 seconds
Started Jul 12 05:48:22 PM PDT 24
Finished Jul 12 05:48:25 PM PDT 24
Peak memory 200096 kb
Host smart-1e278a4d-d6e1-4787-89b8-0ece18b01006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201675293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3201675293
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1808969955
Short name T344
Test name
Test status
Simulation time 129197043 ps
CPU time 1.32 seconds
Started Jul 12 05:48:31 PM PDT 24
Finished Jul 12 05:48:33 PM PDT 24
Peak memory 200140 kb
Host smart-00b40614-b568-4925-939e-c7e044ab0d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808969955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1808969955
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1731925848
Short name T232
Test name
Test status
Simulation time 139485858 ps
CPU time 1.05 seconds
Started Jul 12 05:48:22 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 200076 kb
Host smart-3e0aadbb-5a29-4021-b2b6-abbabfc46851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731925848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1731925848
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2775425616
Short name T295
Test name
Test status
Simulation time 548863242 ps
CPU time 2.81 seconds
Started Jul 12 05:48:20 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 200080 kb
Host smart-9dd8664d-4b86-4341-9a63-6c23eb1c3e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775425616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2775425616
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2362782838
Short name T277
Test name
Test status
Simulation time 121865434 ps
CPU time 0.96 seconds
Started Jul 12 05:48:20 PM PDT 24
Finished Jul 12 05:48:23 PM PDT 24
Peak memory 200068 kb
Host smart-a2f7b876-52e4-49be-bc22-6f40272a151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362782838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2362782838
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.732636837
Short name T81
Test name
Test status
Simulation time 56986682 ps
CPU time 0.77 seconds
Started Jul 12 05:47:48 PM PDT 24
Finished Jul 12 05:47:50 PM PDT 24
Peak memory 199888 kb
Host smart-306e361a-e085-4203-9a6d-04317131577e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732636837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.732636837
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.4041857357
Short name T459
Test name
Test status
Simulation time 1901136336 ps
CPU time 7.3 seconds
Started Jul 12 05:47:49 PM PDT 24
Finished Jul 12 05:47:57 PM PDT 24
Peak memory 216928 kb
Host smart-b58985c4-49c9-4709-aa05-5df465b60b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041857357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.4041857357
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1379818799
Short name T362
Test name
Test status
Simulation time 244319730 ps
CPU time 1.06 seconds
Started Jul 12 05:47:58 PM PDT 24
Finished Jul 12 05:48:01 PM PDT 24
Peak memory 217352 kb
Host smart-5183dbd8-875b-4927-b201-76ac46f00053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379818799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1379818799
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1061668025
Short name T206
Test name
Test status
Simulation time 226486713 ps
CPU time 0.91 seconds
Started Jul 12 05:47:49 PM PDT 24
Finished Jul 12 05:47:50 PM PDT 24
Peak memory 199908 kb
Host smart-22a16cbb-2c0c-468f-9cac-d219a95ec60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061668025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1061668025
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1552528646
Short name T43
Test name
Test status
Simulation time 683784773 ps
CPU time 3.77 seconds
Started Jul 12 05:47:49 PM PDT 24
Finished Jul 12 05:47:53 PM PDT 24
Peak memory 200320 kb
Host smart-98001ff4-e5b6-4400-a588-04794192bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552528646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1552528646
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1277102423
Short name T75
Test name
Test status
Simulation time 8325144684 ps
CPU time 12.73 seconds
Started Jul 12 05:47:50 PM PDT 24
Finished Jul 12 05:48:04 PM PDT 24
Peak memory 217584 kb
Host smart-ed107ff5-d978-4747-b38a-0d6ff00e6e44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277102423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1277102423
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.44527075
Short name T395
Test name
Test status
Simulation time 151994063 ps
CPU time 1.13 seconds
Started Jul 12 05:47:50 PM PDT 24
Finished Jul 12 05:47:52 PM PDT 24
Peak memory 200056 kb
Host smart-f756624f-768a-4619-8cc5-0fa86c70054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44527075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.44527075
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1280735478
Short name T484
Test name
Test status
Simulation time 254447704 ps
CPU time 1.48 seconds
Started Jul 12 05:47:50 PM PDT 24
Finished Jul 12 05:47:52 PM PDT 24
Peak memory 200292 kb
Host smart-2113d675-1503-4bb6-9c20-9fe1d1b40879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280735478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1280735478
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.437992137
Short name T385
Test name
Test status
Simulation time 7673474432 ps
CPU time 25.83 seconds
Started Jul 12 05:47:59 PM PDT 24
Finished Jul 12 05:48:26 PM PDT 24
Peak memory 208640 kb
Host smart-c58ad34f-d0b3-4150-99ee-52c20d8a7266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437992137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.437992137
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2980503661
Short name T462
Test name
Test status
Simulation time 283662618 ps
CPU time 1.89 seconds
Started Jul 12 05:47:49 PM PDT 24
Finished Jul 12 05:47:51 PM PDT 24
Peak memory 200080 kb
Host smart-ddbd3dac-d805-45f4-9313-cb4aa6a84d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980503661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2980503661
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1509935286
Short name T442
Test name
Test status
Simulation time 88497040 ps
CPU time 0.83 seconds
Started Jul 12 05:47:48 PM PDT 24
Finished Jul 12 05:47:49 PM PDT 24
Peak memory 200080 kb
Host smart-00bbb62e-1044-4834-9ffe-6b5539ed788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509935286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1509935286
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3195532413
Short name T490
Test name
Test status
Simulation time 96779441 ps
CPU time 0.81 seconds
Started Jul 12 05:48:17 PM PDT 24
Finished Jul 12 05:48:19 PM PDT 24
Peak memory 199896 kb
Host smart-ebdae18c-f49d-4000-bce2-d9e3c61f6a8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195532413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3195532413
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2080863511
Short name T34
Test name
Test status
Simulation time 1881578230 ps
CPU time 7.72 seconds
Started Jul 12 05:48:22 PM PDT 24
Finished Jul 12 05:48:31 PM PDT 24
Peak memory 217720 kb
Host smart-4927846a-764b-4b2e-943c-ed393d9bf6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080863511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2080863511
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1549751472
Short name T280
Test name
Test status
Simulation time 245029542 ps
CPU time 1.14 seconds
Started Jul 12 05:48:19 PM PDT 24
Finished Jul 12 05:48:21 PM PDT 24
Peak memory 217388 kb
Host smart-aa7c70aa-704f-437f-afec-a4a48c1be0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549751472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1549751472
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.216565366
Short name T186
Test name
Test status
Simulation time 207068412 ps
CPU time 0.91 seconds
Started Jul 12 05:48:18 PM PDT 24
Finished Jul 12 05:48:20 PM PDT 24
Peak memory 199916 kb
Host smart-582211f1-8edb-41af-82d8-38fe9ac9f9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216565366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.216565366
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2216913641
Short name T180
Test name
Test status
Simulation time 1256797997 ps
CPU time 5.49 seconds
Started Jul 12 05:48:30 PM PDT 24
Finished Jul 12 05:48:36 PM PDT 24
Peak memory 200260 kb
Host smart-8a392c10-1961-44f5-acd6-1b31a5077709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216913641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2216913641
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3981251650
Short name T176
Test name
Test status
Simulation time 151400005 ps
CPU time 1.14 seconds
Started Jul 12 05:48:27 PM PDT 24
Finished Jul 12 05:48:29 PM PDT 24
Peak memory 200104 kb
Host smart-6f16a17f-dee7-4a04-92f4-743419d0f566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981251650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3981251650
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.4270986879
Short name T455
Test name
Test status
Simulation time 114865041 ps
CPU time 1.22 seconds
Started Jul 12 05:48:20 PM PDT 24
Finished Jul 12 05:48:22 PM PDT 24
Peak memory 200240 kb
Host smart-1fc46e01-36a0-4dfc-807c-03df8d79e126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270986879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.4270986879
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.206946568
Short name T209
Test name
Test status
Simulation time 4499738582 ps
CPU time 20.45 seconds
Started Jul 12 05:48:20 PM PDT 24
Finished Jul 12 05:48:43 PM PDT 24
Peak memory 208660 kb
Host smart-dcf48686-c1fe-4229-b234-6349f8d40d00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206946568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.206946568
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.4276469772
Short name T80
Test name
Test status
Simulation time 138111208 ps
CPU time 1.75 seconds
Started Jul 12 05:48:27 PM PDT 24
Finished Jul 12 05:48:30 PM PDT 24
Peak memory 200100 kb
Host smart-a879775f-8f4e-4378-9655-5302a62aee23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276469772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.4276469772
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.4175566873
Short name T403
Test name
Test status
Simulation time 115658398 ps
CPU time 1 seconds
Started Jul 12 05:48:24 PM PDT 24
Finished Jul 12 05:48:26 PM PDT 24
Peak memory 200044 kb
Host smart-163eaae6-f22a-45c8-85f7-73adb295577d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175566873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.4175566873
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2606070124
Short name T390
Test name
Test status
Simulation time 67867991 ps
CPU time 0.76 seconds
Started Jul 12 05:48:27 PM PDT 24
Finished Jul 12 05:48:29 PM PDT 24
Peak memory 199896 kb
Host smart-4e841c03-9a42-4abb-b86c-a87f01b27a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606070124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2606070124
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2396401333
Short name T398
Test name
Test status
Simulation time 2374765506 ps
CPU time 9.58 seconds
Started Jul 12 05:48:21 PM PDT 24
Finished Jul 12 05:48:32 PM PDT 24
Peak memory 229888 kb
Host smart-a77ad103-0164-44a8-9abe-f76ccb87bb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396401333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2396401333
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2173619703
Short name T268
Test name
Test status
Simulation time 244024960 ps
CPU time 1.12 seconds
Started Jul 12 05:48:21 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 217704 kb
Host smart-7117f2dc-c371-4bfd-9643-d5da744684db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173619703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2173619703
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.4003584551
Short name T17
Test name
Test status
Simulation time 162111592 ps
CPU time 0.89 seconds
Started Jul 12 05:48:23 PM PDT 24
Finished Jul 12 05:48:26 PM PDT 24
Peak memory 199908 kb
Host smart-8cd7d00f-9ae7-49e2-85eb-942f3f76001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003584551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.4003584551
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3334226380
Short name T235
Test name
Test status
Simulation time 1421536511 ps
CPU time 5.69 seconds
Started Jul 12 05:48:20 PM PDT 24
Finished Jul 12 05:48:28 PM PDT 24
Peak memory 200364 kb
Host smart-5ab48de7-1eed-4166-8db6-dae01c31d901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334226380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3334226380
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3415849452
Short name T220
Test name
Test status
Simulation time 154773613 ps
CPU time 1.24 seconds
Started Jul 12 05:48:31 PM PDT 24
Finished Jul 12 05:48:32 PM PDT 24
Peak memory 199960 kb
Host smart-9d925d8c-90b2-44f4-a87e-6ad7cf2f97ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415849452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3415849452
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3873934376
Short name T148
Test name
Test status
Simulation time 195693038 ps
CPU time 1.3 seconds
Started Jul 12 05:48:23 PM PDT 24
Finished Jul 12 05:48:25 PM PDT 24
Peak memory 200296 kb
Host smart-aa52ef3b-bd61-4092-9611-824da5cdf3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873934376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3873934376
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.472670111
Short name T508
Test name
Test status
Simulation time 182821449 ps
CPU time 1.23 seconds
Started Jul 12 05:48:18 PM PDT 24
Finished Jul 12 05:48:21 PM PDT 24
Peak memory 199804 kb
Host smart-2927ceea-fa61-4b89-b037-71bd9bae8588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472670111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.472670111
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3853350412
Short name T62
Test name
Test status
Simulation time 307750288 ps
CPU time 1.97 seconds
Started Jul 12 05:48:20 PM PDT 24
Finished Jul 12 05:48:23 PM PDT 24
Peak memory 200064 kb
Host smart-76efd348-0234-43b9-a844-fb8842ebb233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853350412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3853350412
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.726642373
Short name T363
Test name
Test status
Simulation time 244399356 ps
CPU time 1.52 seconds
Started Jul 12 05:48:19 PM PDT 24
Finished Jul 12 05:48:21 PM PDT 24
Peak memory 200292 kb
Host smart-329e47f0-cf3e-40fe-8a82-1fe5ee8d36c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726642373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.726642373
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.449553809
Short name T181
Test name
Test status
Simulation time 74286922 ps
CPU time 0.8 seconds
Started Jul 12 05:48:19 PM PDT 24
Finished Jul 12 05:48:21 PM PDT 24
Peak memory 199880 kb
Host smart-40fd1111-8a64-4761-bc0e-2283f793dd95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449553809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.449553809
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3767250295
Short name T350
Test name
Test status
Simulation time 1222083947 ps
CPU time 5.71 seconds
Started Jul 12 05:48:23 PM PDT 24
Finished Jul 12 05:48:30 PM PDT 24
Peak memory 221672 kb
Host smart-090d11ee-9037-445f-bef0-b9b0b7def0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767250295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3767250295
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3351794736
Short name T24
Test name
Test status
Simulation time 244656907 ps
CPU time 1.07 seconds
Started Jul 12 05:48:20 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 217420 kb
Host smart-635b096a-3123-451e-9d72-f1de9624e696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351794736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3351794736
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.741863652
Short name T20
Test name
Test status
Simulation time 125195171 ps
CPU time 0.79 seconds
Started Jul 12 05:48:19 PM PDT 24
Finished Jul 12 05:48:21 PM PDT 24
Peak memory 199904 kb
Host smart-b3dd80c3-7cae-45d9-ad79-983c0523d7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741863652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.741863652
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3480730286
Short name T248
Test name
Test status
Simulation time 804610633 ps
CPU time 4.29 seconds
Started Jul 12 05:48:24 PM PDT 24
Finished Jul 12 05:48:29 PM PDT 24
Peak memory 200256 kb
Host smart-be7afb97-5d67-496e-8550-f5cf3e7300f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480730286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3480730286
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3940356383
Short name T274
Test name
Test status
Simulation time 153203026 ps
CPU time 1.09 seconds
Started Jul 12 05:48:22 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 200104 kb
Host smart-912a0f76-8ca4-4c8e-b933-967302105c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940356383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3940356383
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1278087365
Short name T14
Test name
Test status
Simulation time 232110850 ps
CPU time 1.51 seconds
Started Jul 12 05:48:19 PM PDT 24
Finished Jul 12 05:48:22 PM PDT 24
Peak memory 200272 kb
Host smart-080bc7ce-d3f2-42ff-b8f0-1f840f80f19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278087365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1278087365
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.506712288
Short name T119
Test name
Test status
Simulation time 8726977495 ps
CPU time 30.88 seconds
Started Jul 12 05:48:21 PM PDT 24
Finished Jul 12 05:48:54 PM PDT 24
Peak memory 208592 kb
Host smart-3a3ab8bb-5fae-4103-9905-694cedf09286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506712288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.506712288
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2247986258
Short name T503
Test name
Test status
Simulation time 124363378 ps
CPU time 1.63 seconds
Started Jul 12 05:48:19 PM PDT 24
Finished Jul 12 05:48:22 PM PDT 24
Peak memory 200084 kb
Host smart-959079f0-67e0-4eff-aedd-f69b342df911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247986258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2247986258
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2519020524
Short name T135
Test name
Test status
Simulation time 137076432 ps
CPU time 1.21 seconds
Started Jul 12 05:48:21 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 200348 kb
Host smart-b1ebead7-3b2c-4ca1-8ada-2ead6cbcff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519020524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2519020524
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1526837608
Short name T205
Test name
Test status
Simulation time 65707440 ps
CPU time 0.77 seconds
Started Jul 12 05:48:25 PM PDT 24
Finished Jul 12 05:48:26 PM PDT 24
Peak memory 199836 kb
Host smart-f164f5be-7c9e-4ad7-93da-ccaf126302a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526837608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1526837608
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3146723120
Short name T233
Test name
Test status
Simulation time 1893305541 ps
CPU time 7.01 seconds
Started Jul 12 05:48:27 PM PDT 24
Finished Jul 12 05:48:35 PM PDT 24
Peak memory 217744 kb
Host smart-4e3e117c-a945-4fb5-b3e2-c215d65a6c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146723120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3146723120
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1131353024
Short name T472
Test name
Test status
Simulation time 244067449 ps
CPU time 1.05 seconds
Started Jul 12 05:48:17 PM PDT 24
Finished Jul 12 05:48:19 PM PDT 24
Peak memory 217464 kb
Host smart-1ff275b7-9800-4ecc-b348-4f4b106b82b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131353024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1131353024
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1834962081
Short name T19
Test name
Test status
Simulation time 144525480 ps
CPU time 0.87 seconds
Started Jul 12 05:48:22 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 199920 kb
Host smart-16cf5030-9ded-470e-becb-f88f0ac206d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834962081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1834962081
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1155084220
Short name T422
Test name
Test status
Simulation time 970205168 ps
CPU time 4.89 seconds
Started Jul 12 05:48:19 PM PDT 24
Finished Jul 12 05:48:26 PM PDT 24
Peak memory 200396 kb
Host smart-6d657010-845a-43e2-82f0-330af2f195d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155084220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1155084220
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.366193944
Short name T481
Test name
Test status
Simulation time 98492742 ps
CPU time 1.06 seconds
Started Jul 12 05:48:21 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 200080 kb
Host smart-c21b9751-61ae-444f-8057-14ba01fd1968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366193944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.366193944
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.380304374
Short name T291
Test name
Test status
Simulation time 120281118 ps
CPU time 1.19 seconds
Started Jul 12 05:48:20 PM PDT 24
Finished Jul 12 05:48:23 PM PDT 24
Peak memory 200516 kb
Host smart-415995ee-c79d-4fa6-a4d0-786e92fbb3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380304374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.380304374
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3791457429
Short name T424
Test name
Test status
Simulation time 2009578900 ps
CPU time 6.85 seconds
Started Jul 12 05:48:31 PM PDT 24
Finished Jul 12 05:48:38 PM PDT 24
Peak memory 200264 kb
Host smart-8be99a72-5e52-4db8-a440-e6d35edf1168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791457429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3791457429
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2919604732
Short name T367
Test name
Test status
Simulation time 120273905 ps
CPU time 1.4 seconds
Started Jul 12 05:48:23 PM PDT 24
Finished Jul 12 05:48:26 PM PDT 24
Peak memory 200080 kb
Host smart-d5b3b322-5c95-45c9-8b28-80ead3bf19e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919604732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2919604732
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1250679454
Short name T184
Test name
Test status
Simulation time 114282790 ps
CPU time 1.04 seconds
Started Jul 12 05:48:26 PM PDT 24
Finished Jul 12 05:48:28 PM PDT 24
Peak memory 200092 kb
Host smart-adebcceb-12a0-464b-8cd2-01aee878cfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250679454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1250679454
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.4133100668
Short name T444
Test name
Test status
Simulation time 78938764 ps
CPU time 0.81 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:36 PM PDT 24
Peak memory 199888 kb
Host smart-38d42034-4969-411b-a794-7c179e86f5d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133100668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.4133100668
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1689305854
Short name T527
Test name
Test status
Simulation time 1886249550 ps
CPU time 8.41 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:44 PM PDT 24
Peak memory 221612 kb
Host smart-2cbddcf0-38e1-4f53-b2c5-5bdf3ab29523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689305854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1689305854
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3545151239
Short name T404
Test name
Test status
Simulation time 244402566 ps
CPU time 1.07 seconds
Started Jul 12 05:48:35 PM PDT 24
Finished Jul 12 05:48:37 PM PDT 24
Peak memory 217432 kb
Host smart-a7864dfc-2af5-4e23-918a-be3a07e4577c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545151239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3545151239
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3137458107
Short name T370
Test name
Test status
Simulation time 130996183 ps
CPU time 0.87 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:36 PM PDT 24
Peak memory 199904 kb
Host smart-2e671244-2ee3-464b-a5e1-ed5df85342b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137458107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3137458107
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1900215865
Short name T335
Test name
Test status
Simulation time 1243329683 ps
CPU time 4.86 seconds
Started Jul 12 05:48:36 PM PDT 24
Finished Jul 12 05:48:42 PM PDT 24
Peak memory 200376 kb
Host smart-a933d642-7ade-4510-a7e2-8182a3ae8ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900215865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1900215865
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3571387226
Short name T452
Test name
Test status
Simulation time 185243643 ps
CPU time 1.19 seconds
Started Jul 12 05:48:25 PM PDT 24
Finished Jul 12 05:48:28 PM PDT 24
Peak memory 200092 kb
Host smart-73ef6112-4d89-45ea-b5cb-e3fb35bf3a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571387226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3571387226
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2639458278
Short name T402
Test name
Test status
Simulation time 206207952 ps
CPU time 1.4 seconds
Started Jul 12 05:48:24 PM PDT 24
Finished Jul 12 05:48:27 PM PDT 24
Peak memory 200288 kb
Host smart-9601f246-f4e5-4158-a8ab-9328962146c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639458278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2639458278
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.4022230770
Short name T154
Test name
Test status
Simulation time 229022908 ps
CPU time 1.62 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:37 PM PDT 24
Peak memory 200224 kb
Host smart-033fe628-4f7c-47a0-bbd3-15219503a73e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022230770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4022230770
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2273274899
Short name T321
Test name
Test status
Simulation time 147523158 ps
CPU time 1.89 seconds
Started Jul 12 05:48:25 PM PDT 24
Finished Jul 12 05:48:28 PM PDT 24
Peak memory 200044 kb
Host smart-d4bc19d3-bc91-47a4-81e9-c076f532b358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273274899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2273274899
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2174291922
Short name T519
Test name
Test status
Simulation time 86577077 ps
CPU time 0.87 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:36 PM PDT 24
Peak memory 200088 kb
Host smart-151daaee-2b5b-4e3c-8139-0716f313edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174291922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2174291922
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1438446930
Short name T304
Test name
Test status
Simulation time 60191621 ps
CPU time 0.74 seconds
Started Jul 12 05:48:26 PM PDT 24
Finished Jul 12 05:48:27 PM PDT 24
Peak memory 199880 kb
Host smart-d51cacc3-0392-4993-ac3f-c05ce89114a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438446930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1438446930
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3069682387
Short name T454
Test name
Test status
Simulation time 2177141198 ps
CPU time 7.62 seconds
Started Jul 12 05:48:32 PM PDT 24
Finished Jul 12 05:48:40 PM PDT 24
Peak memory 221748 kb
Host smart-ce23144b-25cc-4fa8-a6c7-526b1eabec3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069682387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3069682387
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2085500098
Short name T407
Test name
Test status
Simulation time 244111866 ps
CPU time 1.1 seconds
Started Jul 12 05:48:26 PM PDT 24
Finished Jul 12 05:48:28 PM PDT 24
Peak memory 217424 kb
Host smart-318c6c5b-2d25-46cc-b05c-cbd8de29a62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085500098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2085500098
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.198202707
Short name T5
Test name
Test status
Simulation time 157457874 ps
CPU time 0.9 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:37 PM PDT 24
Peak memory 199904 kb
Host smart-8ba39c43-9246-4875-8cfd-bbd8c3c421a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198202707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.198202707
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.821873575
Short name T510
Test name
Test status
Simulation time 746289917 ps
CPU time 4.11 seconds
Started Jul 12 05:48:35 PM PDT 24
Finished Jul 12 05:48:41 PM PDT 24
Peak memory 200348 kb
Host smart-82f2ae6d-d72d-4d35-a0ac-1e320e0378c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821873575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.821873575
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.597256890
Short name T458
Test name
Test status
Simulation time 108193084 ps
CPU time 1.03 seconds
Started Jul 12 05:48:25 PM PDT 24
Finished Jul 12 05:48:26 PM PDT 24
Peak memory 200112 kb
Host smart-c67f4e5c-55f1-4492-8505-14ea2512309a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597256890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.597256890
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1394003433
Short name T514
Test name
Test status
Simulation time 122493167 ps
CPU time 1.19 seconds
Started Jul 12 05:48:32 PM PDT 24
Finished Jul 12 05:48:34 PM PDT 24
Peak memory 200256 kb
Host smart-84b03344-cad4-4971-94cd-e63fded8d0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394003433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1394003433
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1120599959
Short name T445
Test name
Test status
Simulation time 3828269641 ps
CPU time 18.65 seconds
Started Jul 12 05:48:37 PM PDT 24
Finished Jul 12 05:48:57 PM PDT 24
Peak memory 200452 kb
Host smart-4575250e-d2ec-45d5-a68e-3d5707ea51ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120599959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1120599959
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3702159479
Short name T287
Test name
Test status
Simulation time 153081975 ps
CPU time 1.89 seconds
Started Jul 12 05:48:27 PM PDT 24
Finished Jul 12 05:48:30 PM PDT 24
Peak memory 200068 kb
Host smart-97d0da58-5da9-4703-8b00-572752837591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702159479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3702159479
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3474895762
Short name T134
Test name
Test status
Simulation time 81868034 ps
CPU time 0.89 seconds
Started Jul 12 05:48:23 PM PDT 24
Finished Jul 12 05:48:25 PM PDT 24
Peak memory 199976 kb
Host smart-c683d770-34cb-4510-b425-c90aa52859ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474895762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3474895762
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.965473078
Short name T240
Test name
Test status
Simulation time 65066512 ps
CPU time 0.79 seconds
Started Jul 12 05:48:36 PM PDT 24
Finished Jul 12 05:48:39 PM PDT 24
Peak memory 199912 kb
Host smart-9d962a83-7da9-4a4c-8157-4ef513f820e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965473078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.965473078
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3480637919
Short name T52
Test name
Test status
Simulation time 1231083616 ps
CPU time 5.93 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:41 PM PDT 24
Peak memory 221624 kb
Host smart-87d8a586-7f63-4c65-852f-b7614dafd496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480637919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3480637919
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1230020810
Short name T449
Test name
Test status
Simulation time 245124689 ps
CPU time 1.04 seconds
Started Jul 12 05:48:31 PM PDT 24
Finished Jul 12 05:48:33 PM PDT 24
Peak memory 217448 kb
Host smart-07c37728-3995-4b8f-a4d8-7aa1500297b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230020810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1230020810
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1044810366
Short name T409
Test name
Test status
Simulation time 153906706 ps
CPU time 0.87 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:37 PM PDT 24
Peak memory 199852 kb
Host smart-9fa0ffe2-3f20-4cdf-b0ee-51f67e5c1d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044810366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1044810366
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.4101962454
Short name T7
Test name
Test status
Simulation time 1173710927 ps
CPU time 4.67 seconds
Started Jul 12 05:48:32 PM PDT 24
Finished Jul 12 05:48:37 PM PDT 24
Peak memory 200328 kb
Host smart-853b447f-7a81-4101-8fb6-352eaa386a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101962454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.4101962454
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1964930233
Short name T160
Test name
Test status
Simulation time 179943778 ps
CPU time 1.19 seconds
Started Jul 12 05:48:35 PM PDT 24
Finished Jul 12 05:48:38 PM PDT 24
Peak memory 200092 kb
Host smart-c4d867b0-76a4-4fc7-89fd-5281f3158b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964930233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1964930233
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.457516766
Short name T239
Test name
Test status
Simulation time 125898179 ps
CPU time 1.27 seconds
Started Jul 12 05:48:36 PM PDT 24
Finished Jul 12 05:48:39 PM PDT 24
Peak memory 200340 kb
Host smart-84b7f65c-1776-4a59-8649-d7ec2080e7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457516766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.457516766
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.775742267
Short name T221
Test name
Test status
Simulation time 7963337551 ps
CPU time 32.56 seconds
Started Jul 12 05:48:35 PM PDT 24
Finished Jul 12 05:49:10 PM PDT 24
Peak memory 200484 kb
Host smart-a0345d6c-072d-4b65-a6ce-6505c679f9c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775742267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.775742267
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1870042127
Short name T261
Test name
Test status
Simulation time 495609719 ps
CPU time 2.87 seconds
Started Jul 12 05:48:25 PM PDT 24
Finished Jul 12 05:48:29 PM PDT 24
Peak memory 200140 kb
Host smart-5c351f7f-aba4-4fa3-924e-ac6cebf1b66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870042127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1870042127
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3490266218
Short name T279
Test name
Test status
Simulation time 120162444 ps
CPU time 0.93 seconds
Started Jul 12 05:48:25 PM PDT 24
Finished Jul 12 05:48:27 PM PDT 24
Peak memory 200112 kb
Host smart-9cd8b9fe-8996-447b-8203-ffd7cfefbe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490266218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3490266218
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.436519014
Short name T430
Test name
Test status
Simulation time 77232011 ps
CPU time 0.87 seconds
Started Jul 12 05:48:35 PM PDT 24
Finished Jul 12 05:48:38 PM PDT 24
Peak memory 199884 kb
Host smart-62f20633-0991-4299-9be3-af8c59c55699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436519014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.436519014
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.347164704
Short name T461
Test name
Test status
Simulation time 2197165703 ps
CPU time 7.38 seconds
Started Jul 12 05:48:36 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 221436 kb
Host smart-705100d1-576b-4696-9e8f-560306a5174c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347164704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.347164704
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.153717687
Short name T147
Test name
Test status
Simulation time 243864648 ps
CPU time 1.08 seconds
Started Jul 12 05:48:32 PM PDT 24
Finished Jul 12 05:48:33 PM PDT 24
Peak memory 217420 kb
Host smart-fe0c1187-0dff-47dc-80ec-762a4e0fd596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153717687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.153717687
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1427842609
Short name T453
Test name
Test status
Simulation time 206622537 ps
CPU time 0.89 seconds
Started Jul 12 05:48:25 PM PDT 24
Finished Jul 12 05:48:26 PM PDT 24
Peak memory 199864 kb
Host smart-16f3bfaf-c5df-4f21-bc46-d70361e5fd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427842609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1427842609
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.318245008
Short name T95
Test name
Test status
Simulation time 877904120 ps
CPU time 4.27 seconds
Started Jul 12 05:48:30 PM PDT 24
Finished Jul 12 05:48:35 PM PDT 24
Peak memory 200336 kb
Host smart-3ff9a7e7-b1b2-4398-a6f1-e2a32d382945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318245008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.318245008
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.365224938
Short name T341
Test name
Test status
Simulation time 180660663 ps
CPU time 1.14 seconds
Started Jul 12 05:48:39 PM PDT 24
Finished Jul 12 05:48:41 PM PDT 24
Peak memory 200056 kb
Host smart-36583154-88b4-48c8-8815-00b88334d8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365224938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.365224938
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2087618643
Short name T509
Test name
Test status
Simulation time 116786679 ps
CPU time 1.2 seconds
Started Jul 12 05:48:33 PM PDT 24
Finished Jul 12 05:48:35 PM PDT 24
Peak memory 200340 kb
Host smart-7780a966-543c-4238-bfcd-b2ee40d47730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087618643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2087618643
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1553883183
Short name T365
Test name
Test status
Simulation time 3129756982 ps
CPU time 11.52 seconds
Started Jul 12 05:48:33 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 200332 kb
Host smart-d70db0aa-7583-4673-8a31-b8462f7d911a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553883183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1553883183
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2375293173
Short name T59
Test name
Test status
Simulation time 131747561 ps
CPU time 1.63 seconds
Started Jul 12 05:48:38 PM PDT 24
Finished Jul 12 05:48:42 PM PDT 24
Peak memory 208244 kb
Host smart-0a8c6480-ed92-4b31-8b9e-b8d1ac6c44e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375293173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2375293173
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3061854101
Short name T185
Test name
Test status
Simulation time 95280153 ps
CPU time 1.01 seconds
Started Jul 12 05:48:33 PM PDT 24
Finished Jul 12 05:48:35 PM PDT 24
Peak memory 200056 kb
Host smart-d489dc40-ce61-4894-9310-150087cbe90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061854101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3061854101
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1968898737
Short name T307
Test name
Test status
Simulation time 62658880 ps
CPU time 0.78 seconds
Started Jul 12 05:48:36 PM PDT 24
Finished Jul 12 05:48:39 PM PDT 24
Peak memory 199764 kb
Host smart-143457e3-4061-4e22-a9f1-ea05c7c1b7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968898737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1968898737
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3398457697
Short name T266
Test name
Test status
Simulation time 1225990711 ps
CPU time 5.59 seconds
Started Jul 12 05:48:37 PM PDT 24
Finished Jul 12 05:48:44 PM PDT 24
Peak memory 217328 kb
Host smart-30d71f92-7d76-4b5d-86f6-a64ff3012351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398457697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3398457697
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1756119760
Short name T319
Test name
Test status
Simulation time 245499367 ps
CPU time 1.07 seconds
Started Jul 12 05:48:36 PM PDT 24
Finished Jul 12 05:48:39 PM PDT 24
Peak memory 218284 kb
Host smart-43ad6844-ea91-44a0-b5cf-2f0d0116be51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756119760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1756119760
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.46666150
Short name T515
Test name
Test status
Simulation time 137606062 ps
CPU time 0.82 seconds
Started Jul 12 05:48:33 PM PDT 24
Finished Jul 12 05:48:34 PM PDT 24
Peak memory 199908 kb
Host smart-dc0b9fd3-3104-47ea-b266-60297ecc8710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46666150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.46666150
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1789580122
Short name T414
Test name
Test status
Simulation time 1158905903 ps
CPU time 5.49 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:40 PM PDT 24
Peak memory 200360 kb
Host smart-e7f8545c-29dc-4931-b109-9cf18bc34cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789580122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1789580122
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.743598375
Short name T356
Test name
Test status
Simulation time 102248533 ps
CPU time 1.03 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:37 PM PDT 24
Peak memory 200100 kb
Host smart-ebb3590e-49a8-492d-bbdc-3bfe984a2bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743598375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.743598375
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.666502360
Short name T534
Test name
Test status
Simulation time 251231493 ps
CPU time 1.58 seconds
Started Jul 12 05:48:36 PM PDT 24
Finished Jul 12 05:48:39 PM PDT 24
Peak memory 200332 kb
Host smart-5deff885-da73-4b38-a919-1753df4b0658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666502360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.666502360
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2000869253
Short name T485
Test name
Test status
Simulation time 2955008589 ps
CPU time 13.38 seconds
Started Jul 12 05:48:33 PM PDT 24
Finished Jul 12 05:48:47 PM PDT 24
Peak memory 208612 kb
Host smart-b06e51f4-0071-4469-9334-3e9628b678b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000869253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2000869253
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2853197359
Short name T188
Test name
Test status
Simulation time 298860955 ps
CPU time 2.14 seconds
Started Jul 12 05:48:37 PM PDT 24
Finished Jul 12 05:48:40 PM PDT 24
Peak memory 208364 kb
Host smart-561a2569-d39c-41bd-ae97-90c5cb688786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853197359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2853197359
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2369938222
Short name T250
Test name
Test status
Simulation time 160122739 ps
CPU time 1.11 seconds
Started Jul 12 05:48:40 PM PDT 24
Finished Jul 12 05:48:43 PM PDT 24
Peak memory 200112 kb
Host smart-a3c775b9-8d90-4c7b-bb44-0d98befe9ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369938222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2369938222
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.4187747368
Short name T376
Test name
Test status
Simulation time 79064627 ps
CPU time 0.83 seconds
Started Jul 12 05:48:38 PM PDT 24
Finished Jul 12 05:48:40 PM PDT 24
Peak memory 199844 kb
Host smart-fd4438bb-f34f-4955-98f0-e3e940804820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187747368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.4187747368
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2476129178
Short name T30
Test name
Test status
Simulation time 1252498889 ps
CPU time 5.51 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:41 PM PDT 24
Peak memory 217724 kb
Host smart-d9cd7368-db44-4a53-819b-6ab9adf3ae06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476129178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2476129178
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.419150688
Short name T191
Test name
Test status
Simulation time 244235791 ps
CPU time 1.08 seconds
Started Jul 12 05:48:33 PM PDT 24
Finished Jul 12 05:48:36 PM PDT 24
Peak memory 217512 kb
Host smart-3bb3807b-3733-45e7-8758-25afca87ac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419150688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.419150688
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.717243547
Short name T327
Test name
Test status
Simulation time 89790895 ps
CPU time 0.82 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:35 PM PDT 24
Peak memory 199896 kb
Host smart-17adc4c7-6aca-4211-ab39-ecaff6465e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717243547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.717243547
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2724743634
Short name T224
Test name
Test status
Simulation time 878746446 ps
CPU time 5.03 seconds
Started Jul 12 05:48:32 PM PDT 24
Finished Jul 12 05:48:38 PM PDT 24
Peak memory 200340 kb
Host smart-9d82818b-4213-4b6f-b7eb-4abf8a04a021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724743634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2724743634
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1650265751
Short name T223
Test name
Test status
Simulation time 179408983 ps
CPU time 1.17 seconds
Started Jul 12 05:48:31 PM PDT 24
Finished Jul 12 05:48:33 PM PDT 24
Peak memory 200192 kb
Host smart-ac6d297b-f7b8-4d7c-881c-31255cc17eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650265751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1650265751
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3841651993
Short name T427
Test name
Test status
Simulation time 116023624 ps
CPU time 1.16 seconds
Started Jul 12 05:48:34 PM PDT 24
Finished Jul 12 05:48:36 PM PDT 24
Peak memory 200248 kb
Host smart-42904cc9-95fb-4fcd-bc4f-f1e4a1532714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841651993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3841651993
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3344603140
Short name T97
Test name
Test status
Simulation time 9203400022 ps
CPU time 38.36 seconds
Started Jul 12 05:48:41 PM PDT 24
Finished Jul 12 05:49:21 PM PDT 24
Peak memory 200428 kb
Host smart-405500f3-0849-49b1-9053-a363a02dd099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344603140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3344603140
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3107847944
Short name T289
Test name
Test status
Simulation time 366913083 ps
CPU time 2.08 seconds
Started Jul 12 05:48:35 PM PDT 24
Finished Jul 12 05:48:39 PM PDT 24
Peak memory 208280 kb
Host smart-f2e7d3d0-386b-48b5-81f1-57f4c2535ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107847944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3107847944
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2287020927
Short name T323
Test name
Test status
Simulation time 87149080 ps
CPU time 0.84 seconds
Started Jul 12 05:48:35 PM PDT 24
Finished Jul 12 05:48:37 PM PDT 24
Peak memory 200064 kb
Host smart-eed9c8ec-f718-496a-a34c-2608f672c363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287020927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2287020927
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3567876455
Short name T207
Test name
Test status
Simulation time 69953816 ps
CPU time 0.77 seconds
Started Jul 12 05:47:47 PM PDT 24
Finished Jul 12 05:47:49 PM PDT 24
Peak memory 199844 kb
Host smart-394037f0-bf79-4685-bd41-134d6b4540ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567876455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3567876455
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3416339008
Short name T265
Test name
Test status
Simulation time 2364300976 ps
CPU time 7.93 seconds
Started Jul 12 05:47:49 PM PDT 24
Finished Jul 12 05:47:58 PM PDT 24
Peak memory 217872 kb
Host smart-dde59acb-43fe-4431-a711-71cdd5ad5f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416339008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3416339008
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2622775493
Short name T56
Test name
Test status
Simulation time 244360525 ps
CPU time 1.09 seconds
Started Jul 12 05:47:53 PM PDT 24
Finished Jul 12 05:47:54 PM PDT 24
Peak memory 217476 kb
Host smart-c30f1b9d-ae35-4b4c-814a-960bcee62c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622775493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2622775493
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1842553160
Short name T315
Test name
Test status
Simulation time 221690380 ps
CPU time 1.02 seconds
Started Jul 12 05:47:49 PM PDT 24
Finished Jul 12 05:47:51 PM PDT 24
Peak memory 199920 kb
Host smart-b472936b-58bc-4387-b8d2-e2eac0febdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842553160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1842553160
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.4000197661
Short name T322
Test name
Test status
Simulation time 1534967240 ps
CPU time 6.28 seconds
Started Jul 12 05:47:50 PM PDT 24
Finished Jul 12 05:47:57 PM PDT 24
Peak memory 200240 kb
Host smart-b8a82855-a249-4644-b352-eb3083126abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000197661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.4000197661
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.840733285
Short name T74
Test name
Test status
Simulation time 8443969310 ps
CPU time 13.12 seconds
Started Jul 12 05:47:48 PM PDT 24
Finished Jul 12 05:48:02 PM PDT 24
Peak memory 217044 kb
Host smart-d7a2610b-bae5-49cb-802e-ca9460853e56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840733285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.840733285
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1136620998
Short name T142
Test name
Test status
Simulation time 103741207 ps
CPU time 1.01 seconds
Started Jul 12 05:47:50 PM PDT 24
Finished Jul 12 05:47:52 PM PDT 24
Peak memory 200108 kb
Host smart-f3cbaacd-dc8f-4837-9ab2-a3b2bc34cae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136620998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1136620998
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2227692984
Short name T288
Test name
Test status
Simulation time 117785997 ps
CPU time 1.16 seconds
Started Jul 12 05:47:59 PM PDT 24
Finished Jul 12 05:48:02 PM PDT 24
Peak memory 200312 kb
Host smart-35b37de8-b436-46e8-a794-f4d0d68c3bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227692984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2227692984
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1990989621
Short name T170
Test name
Test status
Simulation time 134532704 ps
CPU time 0.98 seconds
Started Jul 12 05:47:50 PM PDT 24
Finished Jul 12 05:47:52 PM PDT 24
Peak memory 199900 kb
Host smart-c4b990ab-3b85-4a18-82e0-c367cfad4afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990989621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1990989621
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3584657027
Short name T141
Test name
Test status
Simulation time 211737204 ps
CPU time 1.38 seconds
Started Jul 12 05:47:47 PM PDT 24
Finished Jul 12 05:47:49 PM PDT 24
Peak memory 200120 kb
Host smart-c41aa23f-7e1b-4955-961c-a5cd728127c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584657027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3584657027
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1471980643
Short name T136
Test name
Test status
Simulation time 70107593 ps
CPU time 0.8 seconds
Started Jul 12 05:48:40 PM PDT 24
Finished Jul 12 05:48:42 PM PDT 24
Peak memory 199856 kb
Host smart-b51d9f9b-56b6-4040-9b9d-945c7228963c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471980643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1471980643
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2129106564
Short name T27
Test name
Test status
Simulation time 1226990275 ps
CPU time 5.92 seconds
Started Jul 12 05:48:41 PM PDT 24
Finished Jul 12 05:48:48 PM PDT 24
Peak memory 217468 kb
Host smart-18e3727a-d1c1-49f4-9adb-bcbc9937fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129106564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2129106564
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1839172616
Short name T418
Test name
Test status
Simulation time 244583115 ps
CPU time 1.13 seconds
Started Jul 12 05:48:42 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 217492 kb
Host smart-783a6495-72c9-4efd-962d-43d553a1a7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839172616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1839172616
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.462015181
Short name T15
Test name
Test status
Simulation time 230875047 ps
CPU time 0.91 seconds
Started Jul 12 05:48:40 PM PDT 24
Finished Jul 12 05:48:42 PM PDT 24
Peak memory 199844 kb
Host smart-7950f9f3-c45f-4907-9866-54729927a752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462015181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.462015181
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.4235065694
Short name T222
Test name
Test status
Simulation time 1374717129 ps
CPU time 5.4 seconds
Started Jul 12 05:48:36 PM PDT 24
Finished Jul 12 05:48:43 PM PDT 24
Peak memory 200196 kb
Host smart-795ae2f3-f2b8-4381-b5af-c6e6ef9eac09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235065694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4235065694
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1553510122
Short name T167
Test name
Test status
Simulation time 160664225 ps
CPU time 1.11 seconds
Started Jul 12 05:48:46 PM PDT 24
Finished Jul 12 05:48:48 PM PDT 24
Peak memory 200028 kb
Host smart-d64cdeb6-38fb-40f9-bfb8-646f4530e4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553510122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1553510122
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3938932726
Short name T173
Test name
Test status
Simulation time 123439563 ps
CPU time 1.24 seconds
Started Jul 12 05:48:40 PM PDT 24
Finished Jul 12 05:48:42 PM PDT 24
Peak memory 200248 kb
Host smart-a69cb044-e595-49e3-a84e-8e25be4598fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938932726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3938932726
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2264399310
Short name T366
Test name
Test status
Simulation time 5305540009 ps
CPU time 17.87 seconds
Started Jul 12 05:48:40 PM PDT 24
Finished Jul 12 05:49:00 PM PDT 24
Peak memory 208640 kb
Host smart-96e82bdd-3a45-46b2-b1a3-f925fcf12a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264399310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2264399310
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1348359639
Short name T334
Test name
Test status
Simulation time 130329741 ps
CPU time 1.57 seconds
Started Jul 12 05:48:41 PM PDT 24
Finished Jul 12 05:48:44 PM PDT 24
Peak memory 200100 kb
Host smart-1193e7a0-9411-4ff3-aa63-50ecd4b332f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348359639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1348359639
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1416822767
Short name T197
Test name
Test status
Simulation time 170692345 ps
CPU time 1.28 seconds
Started Jul 12 05:48:38 PM PDT 24
Finished Jul 12 05:48:41 PM PDT 24
Peak memory 200284 kb
Host smart-bf09e548-3118-4413-a68d-17cd4debdb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416822767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1416822767
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.715031239
Short name T498
Test name
Test status
Simulation time 57695333 ps
CPU time 0.76 seconds
Started Jul 12 05:48:43 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 199780 kb
Host smart-8913354b-d78a-4e20-92dd-9fbf859b14a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715031239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.715031239
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2499940812
Short name T343
Test name
Test status
Simulation time 1226780692 ps
CPU time 5.63 seconds
Started Jul 12 05:48:36 PM PDT 24
Finished Jul 12 05:48:43 PM PDT 24
Peak memory 221680 kb
Host smart-2afd7207-dc18-45f5-8b14-2565ee56a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499940812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2499940812
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2605219541
Short name T145
Test name
Test status
Simulation time 244527877 ps
CPU time 1.21 seconds
Started Jul 12 05:48:40 PM PDT 24
Finished Jul 12 05:48:43 PM PDT 24
Peak memory 217444 kb
Host smart-55ceb539-fd30-4056-ac2d-5de95da4b0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605219541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2605219541
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2021795239
Short name T254
Test name
Test status
Simulation time 180997762 ps
CPU time 0.85 seconds
Started Jul 12 05:48:42 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 199932 kb
Host smart-e028ed26-e451-4712-b9e4-2a172a2c5d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021795239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2021795239
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2811962268
Short name T151
Test name
Test status
Simulation time 1007374663 ps
CPU time 5.08 seconds
Started Jul 12 05:48:42 PM PDT 24
Finished Jul 12 05:48:50 PM PDT 24
Peak memory 200288 kb
Host smart-3b4c61a1-4273-472d-a5ef-947e3f14f9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811962268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2811962268
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.923299521
Short name T249
Test name
Test status
Simulation time 115445915 ps
CPU time 1.08 seconds
Started Jul 12 05:48:40 PM PDT 24
Finished Jul 12 05:48:42 PM PDT 24
Peak memory 200116 kb
Host smart-650bd5a6-b834-4792-9b79-38b1b9e40a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923299521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.923299521
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3620901647
Short name T219
Test name
Test status
Simulation time 251777983 ps
CPU time 1.59 seconds
Started Jul 12 05:48:37 PM PDT 24
Finished Jul 12 05:48:40 PM PDT 24
Peak memory 200248 kb
Host smart-ee454bd2-c633-49b7-a20c-fae5ff7e2d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620901647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3620901647
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2873597783
Short name T44
Test name
Test status
Simulation time 525775337 ps
CPU time 2.27 seconds
Started Jul 12 05:48:39 PM PDT 24
Finished Jul 12 05:48:43 PM PDT 24
Peak memory 200196 kb
Host smart-96a6d493-90e2-4e08-b8b9-5fe5e2e874df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873597783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2873597783
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3931337141
Short name T464
Test name
Test status
Simulation time 118313513 ps
CPU time 1.51 seconds
Started Jul 12 05:48:36 PM PDT 24
Finished Jul 12 05:48:39 PM PDT 24
Peak memory 200088 kb
Host smart-9dc67dd8-d2b9-4af4-af24-643631450323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931337141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3931337141
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.32012867
Short name T164
Test name
Test status
Simulation time 97331577 ps
CPU time 0.9 seconds
Started Jul 12 05:48:39 PM PDT 24
Finished Jul 12 05:48:42 PM PDT 24
Peak memory 200052 kb
Host smart-9dd5b7fa-33ac-4933-b8e2-c38a95429eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32012867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.32012867
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.110132049
Short name T168
Test name
Test status
Simulation time 73571000 ps
CPU time 0.8 seconds
Started Jul 12 05:48:46 PM PDT 24
Finished Jul 12 05:48:48 PM PDT 24
Peak memory 199820 kb
Host smart-b9c696c3-f1df-445b-b35b-41a6951ae0ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110132049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.110132049
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.694036080
Short name T416
Test name
Test status
Simulation time 1238328711 ps
CPU time 5.43 seconds
Started Jul 12 05:48:41 PM PDT 24
Finished Jul 12 05:48:48 PM PDT 24
Peak memory 217756 kb
Host smart-c4dde478-29ba-4a84-8436-7d5b7b97531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694036080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.694036080
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.305366376
Short name T187
Test name
Test status
Simulation time 244902236 ps
CPU time 1.05 seconds
Started Jul 12 05:48:40 PM PDT 24
Finished Jul 12 05:48:43 PM PDT 24
Peak memory 217488 kb
Host smart-b4a23dda-5b1c-4bfa-ba09-531f5ca866fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305366376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.305366376
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2565862649
Short name T243
Test name
Test status
Simulation time 80198219 ps
CPU time 0.74 seconds
Started Jul 12 05:48:39 PM PDT 24
Finished Jul 12 05:48:41 PM PDT 24
Peak memory 199924 kb
Host smart-349ea13b-06fb-442e-a99c-39b6a0391e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565862649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2565862649
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1839026206
Short name T202
Test name
Test status
Simulation time 1238582868 ps
CPU time 4.79 seconds
Started Jul 12 05:48:39 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 200260 kb
Host smart-c2f7eab5-012d-484d-a734-2a03a71c2dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839026206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1839026206
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2267837506
Short name T152
Test name
Test status
Simulation time 103071610 ps
CPU time 0.97 seconds
Started Jul 12 05:48:40 PM PDT 24
Finished Jul 12 05:48:43 PM PDT 24
Peak memory 200044 kb
Host smart-492031ab-86c6-4456-ae9f-922ece01fdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267837506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2267837506
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2888762847
Short name T396
Test name
Test status
Simulation time 199540268 ps
CPU time 1.37 seconds
Started Jul 12 05:48:38 PM PDT 24
Finished Jul 12 05:48:41 PM PDT 24
Peak memory 200264 kb
Host smart-8c194bba-50d8-4a9a-8f50-20510d2c4f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888762847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2888762847
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1245019545
Short name T236
Test name
Test status
Simulation time 424525618 ps
CPU time 1.96 seconds
Started Jul 12 05:48:42 PM PDT 24
Finished Jul 12 05:48:46 PM PDT 24
Peak memory 200180 kb
Host smart-c933e6f9-87f4-4ce2-8563-e1da1678d86e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245019545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1245019545
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4293938105
Short name T208
Test name
Test status
Simulation time 405611783 ps
CPU time 2.15 seconds
Started Jul 12 05:48:42 PM PDT 24
Finished Jul 12 05:48:46 PM PDT 24
Peak memory 208180 kb
Host smart-62856cdf-96b7-4382-b17c-a68229f1eb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293938105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4293938105
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.774762080
Short name T526
Test name
Test status
Simulation time 177369405 ps
CPU time 1.27 seconds
Started Jul 12 05:48:36 PM PDT 24
Finished Jul 12 05:48:39 PM PDT 24
Peak memory 200088 kb
Host smart-d7b11658-71f0-48da-8303-a9972a467cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774762080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.774762080
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3112338264
Short name T384
Test name
Test status
Simulation time 70030356 ps
CPU time 0.82 seconds
Started Jul 12 05:48:47 PM PDT 24
Finished Jul 12 05:48:48 PM PDT 24
Peak memory 199896 kb
Host smart-e9f0705e-4b75-412c-9a16-931b8df766f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112338264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3112338264
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.283990222
Short name T31
Test name
Test status
Simulation time 1901412912 ps
CPU time 7.3 seconds
Started Jul 12 05:48:40 PM PDT 24
Finished Jul 12 05:48:49 PM PDT 24
Peak memory 221420 kb
Host smart-d2c8817b-9eb3-4faf-902c-98a0c07be365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283990222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.283990222
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2835436102
Short name T349
Test name
Test status
Simulation time 243742209 ps
CPU time 1.11 seconds
Started Jul 12 05:48:45 PM PDT 24
Finished Jul 12 05:48:48 PM PDT 24
Peak memory 217452 kb
Host smart-b7e5d0db-6bbc-40bf-bfa5-1fec5fed583e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835436102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2835436102
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.85525556
Short name T388
Test name
Test status
Simulation time 170536660 ps
CPU time 0.86 seconds
Started Jul 12 05:48:49 PM PDT 24
Finished Jul 12 05:48:51 PM PDT 24
Peak memory 199848 kb
Host smart-5d1424a9-1b8f-4c0c-8f9d-fd5e6e24fa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85525556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.85525556
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2237143537
Short name T467
Test name
Test status
Simulation time 1289128721 ps
CPU time 5.2 seconds
Started Jul 12 05:48:42 PM PDT 24
Finished Jul 12 05:48:49 PM PDT 24
Peak memory 200344 kb
Host smart-fc68a9c6-6686-49f0-b2aa-0fbae46b6c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237143537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2237143537
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.4265344268
Short name T379
Test name
Test status
Simulation time 111329454 ps
CPU time 1.1 seconds
Started Jul 12 05:48:42 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 200316 kb
Host smart-92971997-ef60-4afa-b4fd-9067b0120f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265344268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.4265344268
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2066974412
Short name T156
Test name
Test status
Simulation time 186779409 ps
CPU time 1.35 seconds
Started Jul 12 05:48:38 PM PDT 24
Finished Jul 12 05:48:41 PM PDT 24
Peak memory 200288 kb
Host smart-5f8670d9-4d28-461f-a3cf-f8395caaebc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066974412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2066974412
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3337244372
Short name T308
Test name
Test status
Simulation time 4844977567 ps
CPU time 16.19 seconds
Started Jul 12 05:48:43 PM PDT 24
Finished Jul 12 05:49:01 PM PDT 24
Peak memory 208636 kb
Host smart-81c8c05a-3dc9-47a5-8a68-3f4a9a35c106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337244372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3337244372
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3719464557
Short name T215
Test name
Test status
Simulation time 125739994 ps
CPU time 1.69 seconds
Started Jul 12 05:48:43 PM PDT 24
Finished Jul 12 05:48:47 PM PDT 24
Peak memory 208280 kb
Host smart-029e8cde-14c3-4fd0-a575-ecefd9e98bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719464557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3719464557
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2217960747
Short name T199
Test name
Test status
Simulation time 151865642 ps
CPU time 1.24 seconds
Started Jul 12 05:48:42 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 200072 kb
Host smart-9704de07-cc25-4ff8-a9dc-541070506ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217960747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2217960747
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1890271862
Short name T317
Test name
Test status
Simulation time 87582469 ps
CPU time 0.86 seconds
Started Jul 12 05:48:42 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 199880 kb
Host smart-f6d0f4bf-1238-4b06-8689-0f2de5f891ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890271862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1890271862
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2846117492
Short name T49
Test name
Test status
Simulation time 1905745922 ps
CPU time 7.35 seconds
Started Jul 12 05:48:45 PM PDT 24
Finished Jul 12 05:48:54 PM PDT 24
Peak memory 221620 kb
Host smart-95c573a4-ebbe-4319-8310-949af5a466bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846117492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2846117492
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1108211778
Short name T489
Test name
Test status
Simulation time 244274192 ps
CPU time 1.04 seconds
Started Jul 12 05:48:44 PM PDT 24
Finished Jul 12 05:48:47 PM PDT 24
Peak memory 217460 kb
Host smart-12231138-4cc8-4045-a13e-56e5172f8d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108211778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1108211778
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.589433598
Short name T299
Test name
Test status
Simulation time 125826334 ps
CPU time 0.79 seconds
Started Jul 12 05:48:41 PM PDT 24
Finished Jul 12 05:48:43 PM PDT 24
Peak memory 199816 kb
Host smart-d17619ea-818b-4cde-96ec-5c904bb4fadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589433598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.589433598
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3368401317
Short name T276
Test name
Test status
Simulation time 1906749791 ps
CPU time 6.7 seconds
Started Jul 12 05:48:43 PM PDT 24
Finished Jul 12 05:48:52 PM PDT 24
Peak memory 200300 kb
Host smart-7411727a-424c-49fe-a697-927c28ab8c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368401317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3368401317
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.696023435
Short name T426
Test name
Test status
Simulation time 184649945 ps
CPU time 1.24 seconds
Started Jul 12 05:48:44 PM PDT 24
Finished Jul 12 05:48:47 PM PDT 24
Peak memory 200112 kb
Host smart-77ae5438-b89f-4c98-acfc-8ead36996c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696023435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.696023435
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3117213887
Short name T536
Test name
Test status
Simulation time 110236949 ps
CPU time 1.23 seconds
Started Jul 12 05:48:44 PM PDT 24
Finished Jul 12 05:48:47 PM PDT 24
Peak memory 200276 kb
Host smart-633320e1-7546-4fd1-af9c-9bf79c154695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117213887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3117213887
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1852295909
Short name T203
Test name
Test status
Simulation time 8732193742 ps
CPU time 31.38 seconds
Started Jul 12 05:48:45 PM PDT 24
Finished Jul 12 05:49:18 PM PDT 24
Peak memory 200408 kb
Host smart-37b77a95-3f84-450d-ac15-6bb7f61ee1b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852295909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1852295909
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1096129861
Short name T273
Test name
Test status
Simulation time 357357034 ps
CPU time 2.46 seconds
Started Jul 12 05:48:46 PM PDT 24
Finished Jul 12 05:48:50 PM PDT 24
Peak memory 200140 kb
Host smart-b31097d4-f271-450c-88a3-8ae3775c3db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096129861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1096129861
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3374621717
Short name T369
Test name
Test status
Simulation time 119318824 ps
CPU time 1.01 seconds
Started Jul 12 05:48:49 PM PDT 24
Finished Jul 12 05:48:51 PM PDT 24
Peak memory 200040 kb
Host smart-8a570bc0-9a3d-4a0d-92c4-b1983d626dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374621717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3374621717
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3115091546
Short name T502
Test name
Test status
Simulation time 65992530 ps
CPU time 0.81 seconds
Started Jul 12 05:48:46 PM PDT 24
Finished Jul 12 05:48:48 PM PDT 24
Peak memory 199896 kb
Host smart-b6692f4f-3fc9-4774-8e18-421843b14ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115091546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3115091546
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.413826424
Short name T500
Test name
Test status
Simulation time 245370651 ps
CPU time 1.05 seconds
Started Jul 12 05:48:43 PM PDT 24
Finished Jul 12 05:48:46 PM PDT 24
Peak memory 217356 kb
Host smart-2c846229-482a-42d4-bb82-88e37c04bc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413826424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.413826424
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2868531776
Short name T491
Test name
Test status
Simulation time 156623494 ps
CPU time 0.87 seconds
Started Jul 12 05:48:41 PM PDT 24
Finished Jul 12 05:48:43 PM PDT 24
Peak memory 199860 kb
Host smart-082bbdfb-6561-438b-887c-51e4733a1eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868531776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2868531776
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3459768692
Short name T228
Test name
Test status
Simulation time 812417781 ps
CPU time 4.51 seconds
Started Jul 12 05:48:43 PM PDT 24
Finished Jul 12 05:48:49 PM PDT 24
Peak memory 200388 kb
Host smart-800eb1c7-96b9-46ed-92e6-4cc121cb3c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459768692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3459768692
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1267545849
Short name T144
Test name
Test status
Simulation time 168149982 ps
CPU time 1.14 seconds
Started Jul 12 05:56:10 PM PDT 24
Finished Jul 12 05:56:12 PM PDT 24
Peak memory 200076 kb
Host smart-46c4897e-8cfd-481f-836e-a41b6b1dc844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267545849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1267545849
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2636929462
Short name T450
Test name
Test status
Simulation time 113279724 ps
CPU time 1.12 seconds
Started Jul 12 05:48:46 PM PDT 24
Finished Jul 12 05:48:48 PM PDT 24
Peak memory 200216 kb
Host smart-a1f632b5-a897-47ba-a368-de2c96f982d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636929462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2636929462
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2390048050
Short name T533
Test name
Test status
Simulation time 4597110308 ps
CPU time 18.63 seconds
Started Jul 12 05:48:46 PM PDT 24
Finished Jul 12 05:49:06 PM PDT 24
Peak memory 200352 kb
Host smart-6b3b02e3-fd9c-4c55-8b23-dbad0315d9f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390048050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2390048050
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1451914135
Short name T256
Test name
Test status
Simulation time 339569959 ps
CPU time 2.29 seconds
Started Jul 12 05:48:46 PM PDT 24
Finished Jul 12 05:48:50 PM PDT 24
Peak memory 200024 kb
Host smart-b125d9d4-6589-4e6f-bcb7-c4fd0a1878b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451914135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1451914135
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3478113958
Short name T259
Test name
Test status
Simulation time 166075917 ps
CPU time 1.36 seconds
Started Jul 12 05:48:50 PM PDT 24
Finished Jul 12 05:48:53 PM PDT 24
Peak memory 200224 kb
Host smart-9f584946-2de5-4c39-b52c-0af00a1dbf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478113958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3478113958
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.722776142
Short name T298
Test name
Test status
Simulation time 68694181 ps
CPU time 0.77 seconds
Started Jul 12 05:48:42 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 199872 kb
Host smart-04106235-06c0-4a4a-80a0-d672a336d246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722776142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.722776142
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3917601509
Short name T245
Test name
Test status
Simulation time 1888247669 ps
CPU time 7.45 seconds
Started Jul 12 05:48:46 PM PDT 24
Finished Jul 12 05:48:55 PM PDT 24
Peak memory 221700 kb
Host smart-3ecf9c55-fbde-4904-86fc-884af22314f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917601509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3917601509
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2748747912
Short name T474
Test name
Test status
Simulation time 243982552 ps
CPU time 1.15 seconds
Started Jul 12 05:48:43 PM PDT 24
Finished Jul 12 05:48:46 PM PDT 24
Peak memory 217444 kb
Host smart-eaa6b080-01e0-498d-82bf-1106471aa97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748747912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2748747912
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.81336666
Short name T441
Test name
Test status
Simulation time 120236425 ps
CPU time 0.92 seconds
Started Jul 12 05:48:44 PM PDT 24
Finished Jul 12 05:48:47 PM PDT 24
Peak memory 199804 kb
Host smart-6475895b-358f-4f43-8ba4-ae105e4d0d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81336666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.81336666
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3323128553
Short name T121
Test name
Test status
Simulation time 2245807268 ps
CPU time 8.5 seconds
Started Jul 12 05:48:43 PM PDT 24
Finished Jul 12 05:48:53 PM PDT 24
Peak memory 200424 kb
Host smart-d13795e9-ab83-484a-878f-6dd29f43ef93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323128553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3323128553
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4107613874
Short name T332
Test name
Test status
Simulation time 102035620 ps
CPU time 1.02 seconds
Started Jul 12 05:48:41 PM PDT 24
Finished Jul 12 05:48:44 PM PDT 24
Peak memory 200104 kb
Host smart-f064b41f-83e3-4db6-8e03-761286303046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107613874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4107613874
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3946457370
Short name T383
Test name
Test status
Simulation time 208398706 ps
CPU time 1.49 seconds
Started Jul 12 05:48:50 PM PDT 24
Finished Jul 12 05:48:53 PM PDT 24
Peak memory 200200 kb
Host smart-1a63ad89-15e9-4476-9001-b59df4a16876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946457370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3946457370
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1955534750
Short name T39
Test name
Test status
Simulation time 7981553682 ps
CPU time 26.96 seconds
Started Jul 12 05:48:44 PM PDT 24
Finished Jul 12 05:49:12 PM PDT 24
Peak memory 200332 kb
Host smart-c3290641-6336-46b9-80c8-97833b741878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955534750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1955534750
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2400641467
Short name T339
Test name
Test status
Simulation time 319325730 ps
CPU time 2.11 seconds
Started Jul 12 05:48:47 PM PDT 24
Finished Jul 12 05:48:51 PM PDT 24
Peak memory 200144 kb
Host smart-b1635b07-43c8-4c92-bb34-15f6d4c84817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400641467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2400641467
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.655694090
Short name T237
Test name
Test status
Simulation time 128912415 ps
CPU time 1.07 seconds
Started Jul 12 05:48:45 PM PDT 24
Finished Jul 12 05:48:47 PM PDT 24
Peak memory 200076 kb
Host smart-716c3e79-f76c-4590-8dda-c6c7933b42f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655694090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.655694090
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1225121828
Short name T23
Test name
Test status
Simulation time 101206843 ps
CPU time 0.87 seconds
Started Jul 12 05:49:04 PM PDT 24
Finished Jul 12 05:49:06 PM PDT 24
Peak memory 199900 kb
Host smart-f2ead4d3-3c44-46d6-9a58-4aae75cc0600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225121828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1225121828
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2759628945
Short name T488
Test name
Test status
Simulation time 1227045263 ps
CPU time 6.23 seconds
Started Jul 12 05:48:47 PM PDT 24
Finished Jul 12 05:48:54 PM PDT 24
Peak memory 217456 kb
Host smart-0dabfa0c-e175-4571-9f92-b019bdfa4e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759628945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2759628945
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2150887183
Short name T255
Test name
Test status
Simulation time 244401503 ps
CPU time 1.14 seconds
Started Jul 12 05:48:50 PM PDT 24
Finished Jul 12 05:48:52 PM PDT 24
Peak memory 217448 kb
Host smart-67a2db66-d697-4df4-a4b9-6a947dbdabde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150887183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2150887183
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.9449473
Short name T477
Test name
Test status
Simulation time 88237692 ps
CPU time 0.8 seconds
Started Jul 12 05:48:50 PM PDT 24
Finished Jul 12 05:48:53 PM PDT 24
Peak memory 199848 kb
Host smart-144b6482-0e8e-48c4-82e3-7a3968d9d206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9449473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.9449473
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3990667648
Short name T83
Test name
Test status
Simulation time 1659795779 ps
CPU time 5.85 seconds
Started Jul 12 05:48:47 PM PDT 24
Finished Jul 12 05:48:54 PM PDT 24
Peak memory 200348 kb
Host smart-1da554b0-2495-4b3e-9866-25d29b951c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990667648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3990667648
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3071216072
Short name T150
Test name
Test status
Simulation time 150830864 ps
CPU time 1.19 seconds
Started Jul 12 05:48:52 PM PDT 24
Finished Jul 12 05:48:55 PM PDT 24
Peak memory 200124 kb
Host smart-9db73526-b4f9-4ada-84a1-58fe76a30aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071216072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3071216072
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.311348871
Short name T190
Test name
Test status
Simulation time 248650599 ps
CPU time 1.59 seconds
Started Jul 12 05:48:54 PM PDT 24
Finished Jul 12 05:48:57 PM PDT 24
Peak memory 200244 kb
Host smart-6f826eaa-bd6b-4075-b65b-c22ffe7fb1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311348871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.311348871
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1756417389
Short name T419
Test name
Test status
Simulation time 2830926223 ps
CPU time 12.31 seconds
Started Jul 12 05:48:49 PM PDT 24
Finished Jul 12 05:49:02 PM PDT 24
Peak memory 208608 kb
Host smart-b56f2d0c-da7f-46c1-ac88-f24116e7b842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756417389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1756417389
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2349348266
Short name T440
Test name
Test status
Simulation time 273833391 ps
CPU time 1.94 seconds
Started Jul 12 05:48:50 PM PDT 24
Finished Jul 12 05:48:53 PM PDT 24
Peak memory 200008 kb
Host smart-a9ae8bcd-7b02-473c-9096-a492515fdad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349348266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2349348266
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1218716335
Short name T431
Test name
Test status
Simulation time 108483806 ps
CPU time 0.91 seconds
Started Jul 12 05:49:07 PM PDT 24
Finished Jul 12 05:49:11 PM PDT 24
Peak memory 200112 kb
Host smart-881db1dd-a364-4028-8882-4978ae14ed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218716335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1218716335
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1737127635
Short name T329
Test name
Test status
Simulation time 66695202 ps
CPU time 0.78 seconds
Started Jul 12 05:48:50 PM PDT 24
Finished Jul 12 05:48:53 PM PDT 24
Peak memory 199868 kb
Host smart-f82357c4-d772-4e8f-95d2-f55decbf73d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737127635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1737127635
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1344712297
Short name T469
Test name
Test status
Simulation time 2367757337 ps
CPU time 9.28 seconds
Started Jul 12 05:48:51 PM PDT 24
Finished Jul 12 05:49:02 PM PDT 24
Peak memory 221756 kb
Host smart-ce57838b-76c4-4c4d-a7d6-6d050b60f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344712297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1344712297
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2730931197
Short name T231
Test name
Test status
Simulation time 244822641 ps
CPU time 1.06 seconds
Started Jul 12 05:48:52 PM PDT 24
Finished Jul 12 05:48:55 PM PDT 24
Peak memory 217328 kb
Host smart-54ee492c-f14e-43b1-b7fc-8a5a5aee0288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730931197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2730931197
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2654980747
Short name T522
Test name
Test status
Simulation time 114154964 ps
CPU time 0.79 seconds
Started Jul 12 05:48:50 PM PDT 24
Finished Jul 12 05:48:52 PM PDT 24
Peak memory 199920 kb
Host smart-a14213c1-f67b-43ba-92e0-59fe47693b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654980747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2654980747
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3026520863
Short name T408
Test name
Test status
Simulation time 1409790004 ps
CPU time 5.36 seconds
Started Jul 12 05:48:49 PM PDT 24
Finished Jul 12 05:48:55 PM PDT 24
Peak memory 200288 kb
Host smart-e7c69255-4bad-489f-a294-89eb3aa74f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026520863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3026520863
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1587954270
Short name T460
Test name
Test status
Simulation time 106315761 ps
CPU time 1.02 seconds
Started Jul 12 05:48:52 PM PDT 24
Finished Jul 12 05:48:54 PM PDT 24
Peak memory 200048 kb
Host smart-38f32e9d-e705-4869-a9e4-6e55d648915f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587954270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1587954270
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.969728654
Short name T421
Test name
Test status
Simulation time 192737545 ps
CPU time 1.55 seconds
Started Jul 12 05:48:51 PM PDT 24
Finished Jul 12 05:48:54 PM PDT 24
Peak memory 200312 kb
Host smart-1af58237-2c77-4c39-8f68-293413b2266a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969728654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.969728654
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2769280012
Short name T473
Test name
Test status
Simulation time 975619415 ps
CPU time 4.89 seconds
Started Jul 12 05:48:51 PM PDT 24
Finished Jul 12 05:48:58 PM PDT 24
Peak memory 209616 kb
Host smart-08ca8ef5-ba4b-4dda-9c7b-54829a491a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769280012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2769280012
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3794564742
Short name T171
Test name
Test status
Simulation time 150195096 ps
CPU time 1.89 seconds
Started Jul 12 05:48:52 PM PDT 24
Finished Jul 12 05:48:55 PM PDT 24
Peak memory 200092 kb
Host smart-40add2c1-ebc3-4436-a629-f7d6c4c3dfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794564742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3794564742
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2408141106
Short name T513
Test name
Test status
Simulation time 257917533 ps
CPU time 1.42 seconds
Started Jul 12 05:48:48 PM PDT 24
Finished Jul 12 05:48:50 PM PDT 24
Peak memory 200100 kb
Host smart-93f5a6d0-73d7-4bc9-bb14-f5180ae8928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408141106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2408141106
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3615365648
Short name T226
Test name
Test status
Simulation time 73279998 ps
CPU time 0.78 seconds
Started Jul 12 05:49:17 PM PDT 24
Finished Jul 12 05:49:19 PM PDT 24
Peak memory 199824 kb
Host smart-c9daa32f-89fb-4622-96bd-155e60d3f651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615365648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3615365648
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3529869262
Short name T46
Test name
Test status
Simulation time 2352085798 ps
CPU time 8.52 seconds
Started Jul 12 05:48:49 PM PDT 24
Finished Jul 12 05:48:59 PM PDT 24
Peak memory 217908 kb
Host smart-132356ac-fa00-429f-82e6-bf865b89fd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529869262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3529869262
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.201271508
Short name T10
Test name
Test status
Simulation time 244232028 ps
CPU time 1.11 seconds
Started Jul 12 05:48:50 PM PDT 24
Finished Jul 12 05:48:53 PM PDT 24
Peak memory 217388 kb
Host smart-8a30e147-db92-4344-b12c-221225a15e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201271508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.201271508
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1706584559
Short name T214
Test name
Test status
Simulation time 176449555 ps
CPU time 0.86 seconds
Started Jul 12 05:48:56 PM PDT 24
Finished Jul 12 05:48:59 PM PDT 24
Peak memory 199888 kb
Host smart-4f6ef329-911a-450f-9ea2-fa1d4ce0d109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706584559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1706584559
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3336933633
Short name T201
Test name
Test status
Simulation time 1352426254 ps
CPU time 5.37 seconds
Started Jul 12 05:48:48 PM PDT 24
Finished Jul 12 05:48:54 PM PDT 24
Peak memory 200360 kb
Host smart-2e33bb34-1df2-407f-80b5-1290df3c7f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336933633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3336933633
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2276474411
Short name T159
Test name
Test status
Simulation time 137166140 ps
CPU time 1.07 seconds
Started Jul 12 05:48:48 PM PDT 24
Finished Jul 12 05:48:50 PM PDT 24
Peak memory 200096 kb
Host smart-09807a09-1f1a-447c-93f2-2601b6c9df93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276474411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2276474411
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3942319888
Short name T466
Test name
Test status
Simulation time 123457177 ps
CPU time 1.33 seconds
Started Jul 12 05:48:51 PM PDT 24
Finished Jul 12 05:48:54 PM PDT 24
Peak memory 200336 kb
Host smart-f540a4a2-46bc-4abc-b8ce-a28c216a1f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942319888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3942319888
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.791041101
Short name T371
Test name
Test status
Simulation time 1560256262 ps
CPU time 7.02 seconds
Started Jul 12 05:49:11 PM PDT 24
Finished Jul 12 05:49:19 PM PDT 24
Peak memory 200360 kb
Host smart-8daeedd1-0367-469e-909b-b523c696a5ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791041101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.791041101
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.315908183
Short name T126
Test name
Test status
Simulation time 441991270 ps
CPU time 2.23 seconds
Started Jul 12 05:48:47 PM PDT 24
Finished Jul 12 05:48:50 PM PDT 24
Peak memory 208324 kb
Host smart-6ed41df5-74cf-4426-8571-389209353e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315908183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.315908183
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3398240641
Short name T493
Test name
Test status
Simulation time 87987047 ps
CPU time 0.89 seconds
Started Jul 12 05:48:53 PM PDT 24
Finished Jul 12 05:48:55 PM PDT 24
Peak memory 200068 kb
Host smart-964ac3d1-2039-43e0-a962-7f040fad451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398240641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3398240641
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.4076364733
Short name T425
Test name
Test status
Simulation time 79117328 ps
CPU time 0.81 seconds
Started Jul 12 05:47:52 PM PDT 24
Finished Jul 12 05:47:54 PM PDT 24
Peak memory 199880 kb
Host smart-dd86140f-6aa2-486b-a9b3-69d151c2b644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076364733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4076364733
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.246213113
Short name T296
Test name
Test status
Simulation time 2369387429 ps
CPU time 7.87 seconds
Started Jul 12 05:47:55 PM PDT 24
Finished Jul 12 05:48:04 PM PDT 24
Peak memory 217712 kb
Host smart-4ef2eb94-fd0f-4283-92f4-887cd38a726e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246213113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.246213113
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3725519722
Short name T392
Test name
Test status
Simulation time 244569178 ps
CPU time 1.02 seconds
Started Jul 12 05:47:53 PM PDT 24
Finished Jul 12 05:47:55 PM PDT 24
Peak memory 217376 kb
Host smart-2e8ce986-7690-4c00-817b-6c32105cac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725519722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3725519722
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3629449721
Short name T465
Test name
Test status
Simulation time 153116175 ps
CPU time 0.79 seconds
Started Jul 12 05:47:55 PM PDT 24
Finished Jul 12 05:47:57 PM PDT 24
Peak memory 199920 kb
Host smart-40c8fe55-bc34-4dbd-9415-c1bff7c79d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629449721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3629449721
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2006734568
Short name T120
Test name
Test status
Simulation time 1903041942 ps
CPU time 7.83 seconds
Started Jul 12 05:47:53 PM PDT 24
Finished Jul 12 05:48:02 PM PDT 24
Peak memory 200380 kb
Host smart-80783802-828f-4f2b-9697-f5846c3f73eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006734568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2006734568
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.462059546
Short name T78
Test name
Test status
Simulation time 8274810885 ps
CPU time 15.42 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:16 PM PDT 24
Peak memory 217272 kb
Host smart-ecbd92ba-376b-48a6-9c87-da651d8a96be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462059546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.462059546
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3491602504
Short name T57
Test name
Test status
Simulation time 181621414 ps
CPU time 1.23 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:03 PM PDT 24
Peak memory 199956 kb
Host smart-4f8a7782-79b8-4bcc-8370-ca9009e9ebd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491602504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3491602504
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2654724827
Short name T324
Test name
Test status
Simulation time 200241867 ps
CPU time 1.3 seconds
Started Jul 12 05:47:56 PM PDT 24
Finished Jul 12 05:47:58 PM PDT 24
Peak memory 200196 kb
Host smart-1ec832c2-75b9-40e4-aab1-5349f21ac639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654724827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2654724827
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.755069847
Short name T381
Test name
Test status
Simulation time 338241245 ps
CPU time 1.6 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:04 PM PDT 24
Peak memory 200136 kb
Host smart-21dd00d0-11d2-482c-8731-f8edc37b1398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755069847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.755069847
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.629023011
Short name T269
Test name
Test status
Simulation time 294689870 ps
CPU time 1.99 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:05 PM PDT 24
Peak memory 208148 kb
Host smart-8aeb31af-5775-4b9c-8d44-5fac25f0ef79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629023011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.629023011
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3642945224
Short name T436
Test name
Test status
Simulation time 127456969 ps
CPU time 1.06 seconds
Started Jul 12 05:47:49 PM PDT 24
Finished Jul 12 05:47:51 PM PDT 24
Peak memory 200076 kb
Host smart-915fcbd3-3abe-446c-b7e6-ef508faee608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642945224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3642945224
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1343292268
Short name T42
Test name
Test status
Simulation time 55405692 ps
CPU time 0.72 seconds
Started Jul 12 05:48:49 PM PDT 24
Finished Jul 12 05:48:51 PM PDT 24
Peak memory 199764 kb
Host smart-8460d54e-7929-450a-9bde-9bc36e5c9303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343292268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1343292268
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.357456112
Short name T29
Test name
Test status
Simulation time 1219750855 ps
CPU time 5.32 seconds
Started Jul 12 05:48:49 PM PDT 24
Finished Jul 12 05:48:56 PM PDT 24
Peak memory 221624 kb
Host smart-6db5296c-8958-404f-93b1-8e48ea9dd5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357456112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.357456112
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1380313678
Short name T447
Test name
Test status
Simulation time 244327784 ps
CPU time 1.07 seconds
Started Jul 12 05:48:50 PM PDT 24
Finished Jul 12 05:48:53 PM PDT 24
Peak memory 217720 kb
Host smart-33f96746-c5b5-4eb8-b42b-750b8337ebf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380313678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1380313678
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3890065489
Short name T278
Test name
Test status
Simulation time 210657812 ps
CPU time 0.91 seconds
Started Jul 12 05:48:49 PM PDT 24
Finished Jul 12 05:48:51 PM PDT 24
Peak memory 199848 kb
Host smart-ef5299ca-a51b-40c7-b418-1a10d12104bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890065489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3890065489
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2174830231
Short name T161
Test name
Test status
Simulation time 1396591578 ps
CPU time 5.73 seconds
Started Jul 12 05:48:50 PM PDT 24
Finished Jul 12 05:48:57 PM PDT 24
Peak memory 200584 kb
Host smart-c3b3d307-ca3d-4bf9-83d3-1a4d9996b712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174830231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2174830231
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3273138202
Short name T300
Test name
Test status
Simulation time 109481446 ps
CPU time 1.05 seconds
Started Jul 12 05:48:49 PM PDT 24
Finished Jul 12 05:48:51 PM PDT 24
Peak memory 200092 kb
Host smart-739fd862-517c-4942-9045-96445c9cbaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273138202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3273138202
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3487112622
Short name T189
Test name
Test status
Simulation time 191535309 ps
CPU time 1.39 seconds
Started Jul 12 05:48:51 PM PDT 24
Finished Jul 12 05:48:54 PM PDT 24
Peak memory 200224 kb
Host smart-fa9ae507-6ac3-469c-b7f0-083d52b1d590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487112622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3487112622
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.463427890
Short name T359
Test name
Test status
Simulation time 3541635449 ps
CPU time 16.33 seconds
Started Jul 12 05:48:47 PM PDT 24
Finished Jul 12 05:49:05 PM PDT 24
Peak memory 200440 kb
Host smart-1354293d-a124-437a-9714-c172b6353c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463427890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.463427890
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.403968010
Short name T487
Test name
Test status
Simulation time 119031712 ps
CPU time 1.58 seconds
Started Jul 12 05:48:50 PM PDT 24
Finished Jul 12 05:48:58 PM PDT 24
Peak memory 208260 kb
Host smart-04690339-e67b-4b43-a9a8-04778e2b2f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403968010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.403968010
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2524586247
Short name T212
Test name
Test status
Simulation time 168322891 ps
CPU time 1.25 seconds
Started Jul 12 05:48:48 PM PDT 24
Finished Jul 12 05:48:50 PM PDT 24
Peak memory 200304 kb
Host smart-be0a23f5-bfad-49c7-a8e9-7b8cadc7258c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524586247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2524586247
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1739486735
Short name T216
Test name
Test status
Simulation time 72245395 ps
CPU time 0.83 seconds
Started Jul 12 05:49:01 PM PDT 24
Finished Jul 12 05:49:03 PM PDT 24
Peak memory 199844 kb
Host smart-2c367988-b004-47be-b8fd-c78a6023fd98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739486735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1739486735
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1006433325
Short name T354
Test name
Test status
Simulation time 2358164683 ps
CPU time 8.59 seconds
Started Jul 12 05:48:57 PM PDT 24
Finished Jul 12 05:49:08 PM PDT 24
Peak memory 221720 kb
Host smart-2c785758-bdff-4c46-a761-8e20d348556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006433325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1006433325
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2247636716
Short name T133
Test name
Test status
Simulation time 251333056 ps
CPU time 1.04 seconds
Started Jul 12 05:49:07 PM PDT 24
Finished Jul 12 05:49:10 PM PDT 24
Peak memory 217464 kb
Host smart-e0a46bda-3461-433e-bc09-9bd75f9569d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247636716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2247636716
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.567742306
Short name T16
Test name
Test status
Simulation time 144106051 ps
CPU time 0.88 seconds
Started Jul 12 05:48:55 PM PDT 24
Finished Jul 12 05:48:57 PM PDT 24
Peak memory 199916 kb
Host smart-085cbace-7881-4633-a2ca-181c156238f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567742306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.567742306
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3723540221
Short name T2
Test name
Test status
Simulation time 775368401 ps
CPU time 4.06 seconds
Started Jul 12 05:48:54 PM PDT 24
Finished Jul 12 05:49:00 PM PDT 24
Peak memory 200300 kb
Host smart-8a76f5df-57eb-4e46-91c8-393fb2b81ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723540221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3723540221
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.784595583
Short name T478
Test name
Test status
Simulation time 151988447 ps
CPU time 1.27 seconds
Started Jul 12 05:48:58 PM PDT 24
Finished Jul 12 05:49:01 PM PDT 24
Peak memory 200084 kb
Host smart-13791611-2fcf-4d79-9232-79fdc54b6f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784595583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.784595583
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3158739144
Short name T494
Test name
Test status
Simulation time 115872159 ps
CPU time 1.25 seconds
Started Jul 12 05:48:56 PM PDT 24
Finished Jul 12 05:48:59 PM PDT 24
Peak memory 200244 kb
Host smart-0be65f2b-ce2d-48ca-b4af-e9464a9792ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158739144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3158739144
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1192500844
Short name T195
Test name
Test status
Simulation time 1899217658 ps
CPU time 9.41 seconds
Started Jul 12 05:48:56 PM PDT 24
Finished Jul 12 05:49:07 PM PDT 24
Peak memory 200404 kb
Host smart-8d2baa55-5466-443e-8d23-e7adbb153f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192500844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1192500844
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1830277072
Short name T282
Test name
Test status
Simulation time 390492479 ps
CPU time 2.21 seconds
Started Jul 12 05:49:01 PM PDT 24
Finished Jul 12 05:49:05 PM PDT 24
Peak memory 200108 kb
Host smart-ade8941d-c44d-43a4-a2b9-2f4bfd3e2c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830277072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1830277072
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1145306384
Short name T158
Test name
Test status
Simulation time 137863509 ps
CPU time 1.13 seconds
Started Jul 12 05:48:56 PM PDT 24
Finished Jul 12 05:48:58 PM PDT 24
Peak memory 200068 kb
Host smart-ca5f7025-5433-4141-94ec-13bfe7a3004e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145306384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1145306384
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.498028810
Short name T313
Test name
Test status
Simulation time 86205841 ps
CPU time 0.84 seconds
Started Jul 12 05:48:53 PM PDT 24
Finished Jul 12 05:48:55 PM PDT 24
Peak memory 199876 kb
Host smart-8b67ae46-dfd8-4b31-9c67-4c248f61c4c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498028810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.498028810
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1735265768
Short name T535
Test name
Test status
Simulation time 2354421565 ps
CPU time 8.73 seconds
Started Jul 12 05:48:56 PM PDT 24
Finished Jul 12 05:49:06 PM PDT 24
Peak memory 217696 kb
Host smart-71e1278f-d53b-41b2-8d12-436e95a26ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735265768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1735265768
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3760412535
Short name T397
Test name
Test status
Simulation time 245193205 ps
CPU time 1.08 seconds
Started Jul 12 05:48:54 PM PDT 24
Finished Jul 12 05:48:57 PM PDT 24
Peak memory 217476 kb
Host smart-c8d0b5f4-3ff5-461c-a472-2bd14f63d31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760412535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3760412535
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2811857443
Short name T338
Test name
Test status
Simulation time 208814971 ps
CPU time 0.89 seconds
Started Jul 12 05:48:53 PM PDT 24
Finished Jul 12 05:48:55 PM PDT 24
Peak memory 199920 kb
Host smart-aedea0d5-bfb0-4fff-99a9-ddf28ecbfdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811857443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2811857443
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1638549432
Short name T457
Test name
Test status
Simulation time 1644412886 ps
CPU time 6.57 seconds
Started Jul 12 05:48:59 PM PDT 24
Finished Jul 12 05:49:07 PM PDT 24
Peak memory 200308 kb
Host smart-4fb80fb5-5667-4c84-8843-ffef69c1a57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638549432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1638549432
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3112028480
Short name T497
Test name
Test status
Simulation time 152238621 ps
CPU time 1.16 seconds
Started Jul 12 05:48:56 PM PDT 24
Finished Jul 12 05:48:59 PM PDT 24
Peak memory 200116 kb
Host smart-9896c580-8fd8-4d3b-8e5d-818c56ebc90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112028480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3112028480
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2288412550
Short name T149
Test name
Test status
Simulation time 123486043 ps
CPU time 1.23 seconds
Started Jul 12 05:49:05 PM PDT 24
Finished Jul 12 05:49:08 PM PDT 24
Peak memory 200296 kb
Host smart-8240a45f-efcc-4a29-855b-7b675dbd3d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288412550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2288412550
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.855082366
Short name T438
Test name
Test status
Simulation time 216814346 ps
CPU time 1.58 seconds
Started Jul 12 05:48:57 PM PDT 24
Finished Jul 12 05:49:00 PM PDT 24
Peak memory 200116 kb
Host smart-33d9effb-21ff-4afd-a208-b29a867b9288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855082366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.855082366
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3212796817
Short name T318
Test name
Test status
Simulation time 117744927 ps
CPU time 1.56 seconds
Started Jul 12 05:48:58 PM PDT 24
Finished Jul 12 05:49:01 PM PDT 24
Peak memory 200124 kb
Host smart-af8144fb-cc2f-44ac-86c1-b52e12e372ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212796817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3212796817
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1515361309
Short name T446
Test name
Test status
Simulation time 91328868 ps
CPU time 0.91 seconds
Started Jul 12 05:48:53 PM PDT 24
Finished Jul 12 05:48:55 PM PDT 24
Peak memory 200104 kb
Host smart-677ae39b-38ca-428e-a265-aa39c512c74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515361309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1515361309
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.795525062
Short name T230
Test name
Test status
Simulation time 61996678 ps
CPU time 0.79 seconds
Started Jul 12 05:49:03 PM PDT 24
Finished Jul 12 05:49:05 PM PDT 24
Peak memory 199896 kb
Host smart-2670a30c-0ff6-4dbe-aa36-6048dd99bb41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795525062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.795525062
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1874049475
Short name T311
Test name
Test status
Simulation time 1901671595 ps
CPU time 7.13 seconds
Started Jul 12 05:49:01 PM PDT 24
Finished Jul 12 05:49:10 PM PDT 24
Peak memory 217472 kb
Host smart-cdc33bd3-075e-48c0-af2c-eb7901104479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874049475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1874049475
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.757524605
Short name T399
Test name
Test status
Simulation time 247081816 ps
CPU time 1.04 seconds
Started Jul 12 05:49:02 PM PDT 24
Finished Jul 12 05:49:04 PM PDT 24
Peak memory 217460 kb
Host smart-a81da915-0e4a-4aee-9fc7-0c956ad5e00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757524605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.757524605
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1836534839
Short name T518
Test name
Test status
Simulation time 132488351 ps
CPU time 0.92 seconds
Started Jul 12 05:49:00 PM PDT 24
Finished Jul 12 05:49:02 PM PDT 24
Peak memory 199680 kb
Host smart-a9eb1868-ce3c-409d-84bf-19ed0a7279ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836534839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1836534839
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2804326859
Short name T294
Test name
Test status
Simulation time 150947639 ps
CPU time 1.18 seconds
Started Jul 12 05:48:55 PM PDT 24
Finished Jul 12 05:48:58 PM PDT 24
Peak memory 200100 kb
Host smart-5e58e70c-3653-41ae-a819-67b314929b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804326859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2804326859
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2504176937
Short name T68
Test name
Test status
Simulation time 230655618 ps
CPU time 1.51 seconds
Started Jul 12 05:48:57 PM PDT 24
Finished Jul 12 05:49:00 PM PDT 24
Peak memory 200252 kb
Host smart-1b33631e-586a-4471-9518-af34e4bfc9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504176937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2504176937
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1088621186
Short name T270
Test name
Test status
Simulation time 4343567727 ps
CPU time 21.56 seconds
Started Jul 12 05:48:55 PM PDT 24
Finished Jul 12 05:49:18 PM PDT 24
Peak memory 216808 kb
Host smart-a24a7667-e4ea-499f-8df1-43e2d270520f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088621186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1088621186
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.4216062274
Short name T306
Test name
Test status
Simulation time 124940627 ps
CPU time 1.69 seconds
Started Jul 12 05:48:56 PM PDT 24
Finished Jul 12 05:48:59 PM PDT 24
Peak memory 200144 kb
Host smart-8c1ef9be-2c79-4d92-ab5f-6f8b1cb9788d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216062274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4216062274
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3395827927
Short name T225
Test name
Test status
Simulation time 85818000 ps
CPU time 0.89 seconds
Started Jul 12 05:48:57 PM PDT 24
Finished Jul 12 05:48:59 PM PDT 24
Peak memory 200060 kb
Host smart-71e3a3aa-91fb-4502-afc0-41c1fcfdf540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395827927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3395827927
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2558310879
Short name T310
Test name
Test status
Simulation time 71319333 ps
CPU time 0.79 seconds
Started Jul 12 05:49:13 PM PDT 24
Finished Jul 12 05:49:15 PM PDT 24
Peak memory 199852 kb
Host smart-25c887f1-8713-422b-9f1e-818b3fc1db15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558310879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2558310879
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3590215468
Short name T406
Test name
Test status
Simulation time 1225751725 ps
CPU time 5.59 seconds
Started Jul 12 05:48:59 PM PDT 24
Finished Jul 12 05:49:06 PM PDT 24
Peak memory 217352 kb
Host smart-29b5f6fd-6a19-44cd-a79f-7e22e0366af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590215468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3590215468
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1303906528
Short name T342
Test name
Test status
Simulation time 244701019 ps
CPU time 1.11 seconds
Started Jul 12 05:48:59 PM PDT 24
Finished Jul 12 05:49:01 PM PDT 24
Peak memory 217428 kb
Host smart-1700f2d2-3116-4b90-a6de-44088976d2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303906528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1303906528
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.4058097155
Short name T200
Test name
Test status
Simulation time 168952919 ps
CPU time 0.87 seconds
Started Jul 12 05:48:55 PM PDT 24
Finished Jul 12 05:48:57 PM PDT 24
Peak memory 199920 kb
Host smart-b856e44f-855d-4303-91bb-fe3165c1cd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058097155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4058097155
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2384915272
Short name T360
Test name
Test status
Simulation time 924574211 ps
CPU time 4.33 seconds
Started Jul 12 05:48:54 PM PDT 24
Finished Jul 12 05:49:00 PM PDT 24
Peak memory 200384 kb
Host smart-0d61ce63-d91a-445d-b58c-ac540c494ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384915272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2384915272
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2142770110
Short name T352
Test name
Test status
Simulation time 155233516 ps
CPU time 1.1 seconds
Started Jul 12 05:48:54 PM PDT 24
Finished Jul 12 05:48:57 PM PDT 24
Peak memory 200316 kb
Host smart-38521b96-958c-4612-9e1e-6819f0c561ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142770110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2142770110
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2477821168
Short name T82
Test name
Test status
Simulation time 251696119 ps
CPU time 1.48 seconds
Started Jul 12 05:48:54 PM PDT 24
Finished Jul 12 05:48:57 PM PDT 24
Peak memory 200264 kb
Host smart-7c5e323e-81c0-42b3-9b36-ab0e72f4c38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477821168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2477821168
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2155910379
Short name T357
Test name
Test status
Simulation time 3667761202 ps
CPU time 15.07 seconds
Started Jul 12 05:49:01 PM PDT 24
Finished Jul 12 05:49:17 PM PDT 24
Peak memory 200368 kb
Host smart-cf3d4e8f-d21f-411e-b649-ef34cb084262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155910379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2155910379
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1259008877
Short name T448
Test name
Test status
Simulation time 135153073 ps
CPU time 1.75 seconds
Started Jul 12 05:48:57 PM PDT 24
Finished Jul 12 05:49:00 PM PDT 24
Peak memory 200048 kb
Host smart-28ef14e0-9561-4635-be86-0e073b665484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259008877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1259008877
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1005809295
Short name T375
Test name
Test status
Simulation time 131991923 ps
CPU time 1 seconds
Started Jul 12 05:49:00 PM PDT 24
Finished Jul 12 05:49:02 PM PDT 24
Peak memory 199904 kb
Host smart-6db3bfd1-d493-47b1-b9ca-f02c486ef7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005809295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1005809295
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.844526490
Short name T241
Test name
Test status
Simulation time 62863660 ps
CPU time 0.75 seconds
Started Jul 12 05:49:03 PM PDT 24
Finished Jul 12 05:49:05 PM PDT 24
Peak memory 199896 kb
Host smart-b13345f2-adf9-454d-b526-8ca9a70c05aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844526490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.844526490
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2697461862
Short name T45
Test name
Test status
Simulation time 2172471463 ps
CPU time 8.29 seconds
Started Jul 12 05:48:58 PM PDT 24
Finished Jul 12 05:49:08 PM PDT 24
Peak memory 217788 kb
Host smart-eb88ce11-6aec-4989-b1fa-1c9849bb50e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697461862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2697461862
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3317597960
Short name T204
Test name
Test status
Simulation time 243953023 ps
CPU time 1.05 seconds
Started Jul 12 05:49:00 PM PDT 24
Finished Jul 12 05:49:02 PM PDT 24
Peak memory 217400 kb
Host smart-732ea043-edf3-4228-963a-459acfbc9b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317597960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3317597960
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3240663074
Short name T368
Test name
Test status
Simulation time 74982044 ps
CPU time 0.73 seconds
Started Jul 12 05:48:57 PM PDT 24
Finished Jul 12 05:48:59 PM PDT 24
Peak memory 199900 kb
Host smart-73cd5a48-cdc5-4b5b-a20a-2ed590693541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240663074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3240663074
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.4238749742
Short name T193
Test name
Test status
Simulation time 860739872 ps
CPU time 4.28 seconds
Started Jul 12 05:48:57 PM PDT 24
Finished Jul 12 05:49:03 PM PDT 24
Peak memory 200336 kb
Host smart-4125383c-5201-4f84-bf1f-a60525a5fe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238749742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.4238749742
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1326668293
Short name T320
Test name
Test status
Simulation time 172942571 ps
CPU time 1.2 seconds
Started Jul 12 05:49:00 PM PDT 24
Finished Jul 12 05:49:03 PM PDT 24
Peak memory 200088 kb
Host smart-925a70db-fb26-4c3d-9f89-ee2da07d285e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326668293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1326668293
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2550410193
Short name T348
Test name
Test status
Simulation time 117660041 ps
CPU time 1.27 seconds
Started Jul 12 05:48:58 PM PDT 24
Finished Jul 12 05:49:01 PM PDT 24
Peak memory 200256 kb
Host smart-fffb4a16-de39-4cc3-b0b2-633bd8748019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550410193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2550410193
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2881821216
Short name T400
Test name
Test status
Simulation time 3903859922 ps
CPU time 16.1 seconds
Started Jul 12 05:49:00 PM PDT 24
Finished Jul 12 05:49:17 PM PDT 24
Peak memory 208632 kb
Host smart-fb5bf1ab-0094-4d7b-bbc7-d2af1582555e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881821216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2881821216
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.737973818
Short name T443
Test name
Test status
Simulation time 325498091 ps
CPU time 2.25 seconds
Started Jul 12 05:48:53 PM PDT 24
Finished Jul 12 05:48:56 PM PDT 24
Peak memory 200212 kb
Host smart-0372b7ca-7a4a-4ed5-aa08-53edc1efbf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737973818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.737973818
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.623570711
Short name T499
Test name
Test status
Simulation time 90982342 ps
CPU time 0.93 seconds
Started Jul 12 05:48:58 PM PDT 24
Finished Jul 12 05:49:00 PM PDT 24
Peak memory 200080 kb
Host smart-6c043dd3-9a0b-4381-b064-57221a268364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623570711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.623570711
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2553666034
Short name T227
Test name
Test status
Simulation time 53325509 ps
CPU time 0.74 seconds
Started Jul 12 05:49:05 PM PDT 24
Finished Jul 12 05:49:07 PM PDT 24
Peak memory 199848 kb
Host smart-dada705c-5bae-4268-b67e-a7ffb1caf786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553666034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2553666034
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2283693689
Short name T130
Test name
Test status
Simulation time 1906454591 ps
CPU time 7.58 seconds
Started Jul 12 05:49:07 PM PDT 24
Finished Jul 12 05:49:16 PM PDT 24
Peak memory 217696 kb
Host smart-7649f047-2f60-441c-a95f-7b3ad8300dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283693689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2283693689
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.261329209
Short name T242
Test name
Test status
Simulation time 244245701 ps
CPU time 1.15 seconds
Started Jul 12 05:49:04 PM PDT 24
Finished Jul 12 05:49:06 PM PDT 24
Peak memory 217452 kb
Host smart-c0ce0420-74f8-495c-809a-43789f21ad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261329209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.261329209
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.576447203
Short name T495
Test name
Test status
Simulation time 158318117 ps
CPU time 0.83 seconds
Started Jul 12 05:49:14 PM PDT 24
Finished Jul 12 05:49:16 PM PDT 24
Peak memory 199904 kb
Host smart-fd3f9dc1-37c8-477d-9e2f-23dc52db7c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576447203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.576447203
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1047823101
Short name T476
Test name
Test status
Simulation time 1500921834 ps
CPU time 6.13 seconds
Started Jul 12 05:49:06 PM PDT 24
Finished Jul 12 05:49:14 PM PDT 24
Peak memory 200376 kb
Host smart-e6a98911-c7ea-44eb-8ca2-c6ac541753ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047823101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1047823101
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1732538624
Short name T517
Test name
Test status
Simulation time 177070545 ps
CPU time 1.25 seconds
Started Jul 12 05:49:07 PM PDT 24
Finished Jul 12 05:49:11 PM PDT 24
Peak memory 200096 kb
Host smart-9dc72fc8-d8c5-4261-beb2-c2ea3dddc3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732538624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1732538624
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1672262464
Short name T330
Test name
Test status
Simulation time 202189340 ps
CPU time 1.4 seconds
Started Jul 12 05:49:04 PM PDT 24
Finished Jul 12 05:49:06 PM PDT 24
Peak memory 200224 kb
Host smart-501fe7af-25d7-46d7-b1c9-dbde7f9d892c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672262464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1672262464
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2430223602
Short name T153
Test name
Test status
Simulation time 177444251 ps
CPU time 1.18 seconds
Started Jul 12 05:49:01 PM PDT 24
Finished Jul 12 05:49:03 PM PDT 24
Peak memory 200072 kb
Host smart-f7350036-c139-4a76-8089-d61cda0f3f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430223602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2430223602
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.308282193
Short name T374
Test name
Test status
Simulation time 254903263 ps
CPU time 1.77 seconds
Started Jul 12 05:49:01 PM PDT 24
Finished Jul 12 05:49:04 PM PDT 24
Peak memory 200080 kb
Host smart-31316fcf-1652-471b-aa5d-66279c699589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308282193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.308282193
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2510802819
Short name T331
Test name
Test status
Simulation time 163622999 ps
CPU time 1.08 seconds
Started Jul 12 05:49:17 PM PDT 24
Finished Jul 12 05:49:20 PM PDT 24
Peak memory 200092 kb
Host smart-5d430808-0a75-4516-a091-669b9088873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510802819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2510802819
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3492489717
Short name T437
Test name
Test status
Simulation time 67912579 ps
CPU time 0.78 seconds
Started Jul 12 05:49:01 PM PDT 24
Finished Jul 12 05:49:03 PM PDT 24
Peak memory 199884 kb
Host smart-a0094ce2-8047-44ab-b732-2007de79e948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492489717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3492489717
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3056662925
Short name T272
Test name
Test status
Simulation time 1224707999 ps
CPU time 5.9 seconds
Started Jul 12 05:49:01 PM PDT 24
Finished Jul 12 05:49:08 PM PDT 24
Peak memory 217752 kb
Host smart-8d399602-1558-4164-86be-d535760ff25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056662925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3056662925
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1671949796
Short name T355
Test name
Test status
Simulation time 243956870 ps
CPU time 1.1 seconds
Started Jul 12 05:49:09 PM PDT 24
Finished Jul 12 05:49:12 PM PDT 24
Peak memory 217328 kb
Host smart-c781168d-b986-4d18-928c-2bc5778dab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671949796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1671949796
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2307987495
Short name T22
Test name
Test status
Simulation time 138743664 ps
CPU time 0.78 seconds
Started Jul 12 05:49:11 PM PDT 24
Finished Jul 12 05:49:13 PM PDT 24
Peak memory 199896 kb
Host smart-59f88e0b-4414-48fe-9919-6ccf2763ed51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307987495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2307987495
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.911193199
Short name T96
Test name
Test status
Simulation time 946505920 ps
CPU time 4.76 seconds
Started Jul 12 05:49:06 PM PDT 24
Finished Jul 12 05:49:13 PM PDT 24
Peak memory 200308 kb
Host smart-0e6ca48d-f37d-41ad-8489-43bc78ebc3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911193199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.911193199
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2878561457
Short name T386
Test name
Test status
Simulation time 165532666 ps
CPU time 1.24 seconds
Started Jul 12 05:49:18 PM PDT 24
Finished Jul 12 05:49:20 PM PDT 24
Peak memory 200072 kb
Host smart-dc503232-3bce-47a8-9dc0-781bae0c2614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878561457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2878561457
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3879535152
Short name T175
Test name
Test status
Simulation time 191289889 ps
CPU time 1.36 seconds
Started Jul 12 05:49:08 PM PDT 24
Finished Jul 12 05:49:12 PM PDT 24
Peak memory 200264 kb
Host smart-f35ab133-2831-47ee-9f06-f8543b3dbfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879535152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3879535152
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1974554484
Short name T26
Test name
Test status
Simulation time 3692180023 ps
CPU time 14.03 seconds
Started Jul 12 05:49:07 PM PDT 24
Finished Jul 12 05:49:23 PM PDT 24
Peak memory 208592 kb
Host smart-6a0a63f8-c3e7-4997-9ca8-907c3034d203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974554484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1974554484
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.282382322
Short name T415
Test name
Test status
Simulation time 387162879 ps
CPU time 2.3 seconds
Started Jul 12 05:49:06 PM PDT 24
Finished Jul 12 05:49:11 PM PDT 24
Peak memory 200092 kb
Host smart-d7c0f321-a885-42ee-b6a0-b207f9764c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282382322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.282382322
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1261149159
Short name T271
Test name
Test status
Simulation time 131826937 ps
CPU time 0.99 seconds
Started Jul 12 05:49:09 PM PDT 24
Finished Jul 12 05:49:12 PM PDT 24
Peak memory 200112 kb
Host smart-5e75823e-8f34-4bac-a1f1-a73003f8b833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261149159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1261149159
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3146439871
Short name T377
Test name
Test status
Simulation time 84164478 ps
CPU time 0.84 seconds
Started Jul 12 05:49:08 PM PDT 24
Finished Jul 12 05:49:11 PM PDT 24
Peak memory 199884 kb
Host smart-ac0c67a7-c313-412b-add8-953524c1d427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146439871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3146439871
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2007201820
Short name T333
Test name
Test status
Simulation time 1232077277 ps
CPU time 5.76 seconds
Started Jul 12 05:49:17 PM PDT 24
Finished Jul 12 05:49:25 PM PDT 24
Peak memory 217720 kb
Host smart-4570fb13-99bd-4e5e-83aa-d6afb17911d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007201820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2007201820
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3848685727
Short name T432
Test name
Test status
Simulation time 245040800 ps
CPU time 1.03 seconds
Started Jul 12 05:49:05 PM PDT 24
Finished Jul 12 05:49:08 PM PDT 24
Peak memory 217524 kb
Host smart-05b32873-b8a1-4b78-8e71-fb8470f0f5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848685727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3848685727
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1089900601
Short name T351
Test name
Test status
Simulation time 92363178 ps
CPU time 0.74 seconds
Started Jul 12 05:49:01 PM PDT 24
Finished Jul 12 05:49:03 PM PDT 24
Peak memory 199904 kb
Host smart-91e4af3d-1fbc-481a-8b59-36054c065b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089900601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1089900601
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3924733341
Short name T290
Test name
Test status
Simulation time 1078829904 ps
CPU time 5.1 seconds
Started Jul 12 05:49:16 PM PDT 24
Finished Jul 12 05:49:22 PM PDT 24
Peak memory 200348 kb
Host smart-7048b7da-81ea-49c1-bf26-efdac20fa4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924733341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3924733341
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.305905989
Short name T12
Test name
Test status
Simulation time 180248156 ps
CPU time 1.21 seconds
Started Jul 12 05:49:02 PM PDT 24
Finished Jul 12 05:49:04 PM PDT 24
Peak memory 200060 kb
Host smart-2d4a8631-031d-413c-8439-ca5b4f272d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305905989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.305905989
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.68688577
Short name T439
Test name
Test status
Simulation time 117938965 ps
CPU time 1.23 seconds
Started Jul 12 05:49:08 PM PDT 24
Finished Jul 12 05:49:11 PM PDT 24
Peak memory 200264 kb
Host smart-b04ab45f-0a15-44ae-abf7-69b36351114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68688577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.68688577
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2243623377
Short name T177
Test name
Test status
Simulation time 497209395 ps
CPU time 2.35 seconds
Started Jul 12 05:49:15 PM PDT 24
Finished Jul 12 05:49:18 PM PDT 24
Peak memory 200256 kb
Host smart-e8fa1308-6959-4276-9957-bb2171527e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243623377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2243623377
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2136674857
Short name T234
Test name
Test status
Simulation time 431457542 ps
CPU time 2.41 seconds
Started Jul 12 05:49:03 PM PDT 24
Finished Jul 12 05:49:07 PM PDT 24
Peak memory 200144 kb
Host smart-807d38d3-76f0-4852-be89-840b9147754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136674857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2136674857
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3757048930
Short name T281
Test name
Test status
Simulation time 201150304 ps
CPU time 1.18 seconds
Started Jul 12 05:48:59 PM PDT 24
Finished Jul 12 05:49:02 PM PDT 24
Peak memory 200112 kb
Host smart-071df7b6-721e-45c9-90b2-dfa78d0bc583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757048930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3757048930
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.224925514
Short name T85
Test name
Test status
Simulation time 97328750 ps
CPU time 0.81 seconds
Started Jul 12 05:49:04 PM PDT 24
Finished Jul 12 05:49:07 PM PDT 24
Peak memory 199872 kb
Host smart-f8f875ce-e2c5-4cec-b5de-b65dc164e609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224925514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.224925514
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1298156170
Short name T480
Test name
Test status
Simulation time 2369336344 ps
CPU time 8.21 seconds
Started Jul 12 05:51:38 PM PDT 24
Finished Jul 12 05:51:47 PM PDT 24
Peak memory 217868 kb
Host smart-b5b4b7e0-5adb-4f6c-aa7d-ad42b8f4493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298156170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1298156170
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2493932464
Short name T482
Test name
Test status
Simulation time 243906949 ps
CPU time 1.15 seconds
Started Jul 12 06:22:34 PM PDT 24
Finished Jul 12 06:22:37 PM PDT 24
Peak memory 217456 kb
Host smart-b8e8a11d-f853-43a7-893f-cad4fd96c1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493932464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2493932464
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3324021059
Short name T316
Test name
Test status
Simulation time 112776377 ps
CPU time 0.83 seconds
Started Jul 12 05:49:02 PM PDT 24
Finished Jul 12 05:49:04 PM PDT 24
Peak memory 199916 kb
Host smart-22aba454-c670-4d77-8281-f5e64422501e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324021059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3324021059
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2390686105
Short name T140
Test name
Test status
Simulation time 1224288512 ps
CPU time 5.2 seconds
Started Jul 12 05:49:11 PM PDT 24
Finished Jul 12 05:49:17 PM PDT 24
Peak memory 200348 kb
Host smart-6e8e14d0-c20a-483b-8b99-44f59ee77d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390686105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2390686105
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2628974885
Short name T8
Test name
Test status
Simulation time 191031762 ps
CPU time 1.25 seconds
Started Jul 12 06:31:26 PM PDT 24
Finished Jul 12 06:31:29 PM PDT 24
Peak memory 200096 kb
Host smart-e10f62a5-a182-49c7-8c87-60dcbea499a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628974885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2628974885
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2279532068
Short name T40
Test name
Test status
Simulation time 127699645 ps
CPU time 1.26 seconds
Started Jul 12 05:49:01 PM PDT 24
Finished Jul 12 05:49:04 PM PDT 24
Peak memory 200280 kb
Host smart-234c9bf6-1846-4fdc-a605-a7919739d9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279532068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2279532068
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.701492732
Short name T262
Test name
Test status
Simulation time 3068047327 ps
CPU time 11.19 seconds
Started Jul 12 05:49:12 PM PDT 24
Finished Jul 12 05:49:25 PM PDT 24
Peak memory 200412 kb
Host smart-585b34b5-9746-493e-8de3-a17913398b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701492732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.701492732
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1983721954
Short name T252
Test name
Test status
Simulation time 318206244 ps
CPU time 2.06 seconds
Started Jul 12 05:49:01 PM PDT 24
Finished Jul 12 05:49:04 PM PDT 24
Peak memory 208352 kb
Host smart-1b35a80d-b70c-4e1f-b9df-a5696f89ca0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983721954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1983721954
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.975940833
Short name T405
Test name
Test status
Simulation time 96244319 ps
CPU time 0.99 seconds
Started Jul 12 05:49:02 PM PDT 24
Finished Jul 12 05:49:04 PM PDT 24
Peak memory 200096 kb
Host smart-5a6f8db4-a76f-4eba-b84c-fb53d77fd3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975940833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.975940833
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.301398962
Short name T524
Test name
Test status
Simulation time 73355902 ps
CPU time 0.84 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:03 PM PDT 24
Peak memory 199872 kb
Host smart-dff03c9a-3b5d-48d4-b31c-78883ee2b55f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301398962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.301398962
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3652198951
Short name T33
Test name
Test status
Simulation time 2359581657 ps
CPU time 8.77 seconds
Started Jul 12 05:47:54 PM PDT 24
Finished Jul 12 05:48:04 PM PDT 24
Peak memory 221780 kb
Host smart-0a9fd157-5ca5-4492-8d25-e0b9df0bab27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652198951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3652198951
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3919978023
Short name T210
Test name
Test status
Simulation time 243523114 ps
CPU time 1.13 seconds
Started Jul 12 05:47:55 PM PDT 24
Finished Jul 12 05:47:58 PM PDT 24
Peak memory 217444 kb
Host smart-9a6f59e9-8baf-478c-beba-914205dcea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919978023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3919978023
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.90363507
Short name T218
Test name
Test status
Simulation time 101814069 ps
CPU time 0.76 seconds
Started Jul 12 05:47:54 PM PDT 24
Finished Jul 12 05:47:56 PM PDT 24
Peak memory 199900 kb
Host smart-c1d7b92e-d15e-4c60-8628-e517f4745c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90363507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.90363507
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.840729371
Short name T125
Test name
Test status
Simulation time 1656038444 ps
CPU time 6.06 seconds
Started Jul 12 05:47:55 PM PDT 24
Finished Jul 12 05:48:03 PM PDT 24
Peak memory 200332 kb
Host smart-3f7ddc37-a0d4-46a9-9463-4957588a7cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840729371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.840729371
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3645647888
Short name T251
Test name
Test status
Simulation time 147577882 ps
CPU time 1.12 seconds
Started Jul 12 05:47:57 PM PDT 24
Finished Jul 12 05:47:59 PM PDT 24
Peak memory 200096 kb
Host smart-d2823ec6-3247-4b92-8894-56f91955aadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645647888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3645647888
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3186218126
Short name T293
Test name
Test status
Simulation time 227482371 ps
CPU time 1.49 seconds
Started Jul 12 05:47:54 PM PDT 24
Finished Jul 12 05:47:56 PM PDT 24
Peak memory 200236 kb
Host smart-1612fa5a-2174-47a3-a11c-d56781fb0a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186218126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3186218126
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3411760942
Short name T50
Test name
Test status
Simulation time 3115600271 ps
CPU time 14.35 seconds
Started Jul 12 05:47:53 PM PDT 24
Finished Jul 12 05:48:08 PM PDT 24
Peak memory 200396 kb
Host smart-12d501ac-ca61-4f2b-a7ec-c6cdc1c9f2e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411760942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3411760942
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.155585092
Short name T501
Test name
Test status
Simulation time 463706036 ps
CPU time 2.46 seconds
Started Jul 12 05:47:58 PM PDT 24
Finished Jul 12 05:48:02 PM PDT 24
Peak memory 200088 kb
Host smart-e0fb65d5-be46-4bc3-802f-820700ca3656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155585092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.155585092
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3080582842
Short name T507
Test name
Test status
Simulation time 126118153 ps
CPU time 0.99 seconds
Started Jul 12 05:47:52 PM PDT 24
Finished Jul 12 05:47:54 PM PDT 24
Peak memory 200060 kb
Host smart-c898ca5b-e787-42f9-9ea2-0cf1eca25795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080582842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3080582842
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2104438804
Short name T260
Test name
Test status
Simulation time 85619771 ps
CPU time 0.81 seconds
Started Jul 12 05:47:56 PM PDT 24
Finished Jul 12 05:47:58 PM PDT 24
Peak memory 199868 kb
Host smart-3506634b-a284-4c03-9f87-d7fef3a08139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104438804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2104438804
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1008153039
Short name T456
Test name
Test status
Simulation time 1218619894 ps
CPU time 5.31 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:08 PM PDT 24
Peak memory 217504 kb
Host smart-64193df8-e075-4d44-b6be-32d9a0a41e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008153039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1008153039
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1800976340
Short name T520
Test name
Test status
Simulation time 244950652 ps
CPU time 1.12 seconds
Started Jul 12 05:47:54 PM PDT 24
Finished Jul 12 05:47:56 PM PDT 24
Peak memory 217456 kb
Host smart-0ef86039-0280-45d5-a9a8-7c1e3355e751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800976340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1800976340
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1733818161
Short name T6
Test name
Test status
Simulation time 94828092 ps
CPU time 0.79 seconds
Started Jul 12 05:47:55 PM PDT 24
Finished Jul 12 05:47:56 PM PDT 24
Peak memory 199900 kb
Host smart-093e3715-b8f0-4ec1-9634-7eb6d4b43c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733818161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1733818161
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1885567176
Short name T340
Test name
Test status
Simulation time 1551635736 ps
CPU time 5.57 seconds
Started Jul 12 05:47:53 PM PDT 24
Finished Jul 12 05:48:00 PM PDT 24
Peak memory 200260 kb
Host smart-7a735a6f-027a-427a-b95b-a5bb09861574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885567176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1885567176
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3013162769
Short name T309
Test name
Test status
Simulation time 110657248 ps
CPU time 1.09 seconds
Started Jul 12 05:47:56 PM PDT 24
Finished Jul 12 05:47:58 PM PDT 24
Peak memory 200076 kb
Host smart-d789cace-bc40-43f6-bd86-ade6b3cf8db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013162769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3013162769
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2607976917
Short name T79
Test name
Test status
Simulation time 116075197 ps
CPU time 1.25 seconds
Started Jul 12 05:47:55 PM PDT 24
Finished Jul 12 05:47:57 PM PDT 24
Peak memory 200256 kb
Host smart-825dd964-3aab-4c31-b647-784a9f14bd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607976917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2607976917
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.47561626
Short name T434
Test name
Test status
Simulation time 5919152054 ps
CPU time 26.25 seconds
Started Jul 12 05:47:54 PM PDT 24
Finished Jul 12 05:48:21 PM PDT 24
Peak memory 200380 kb
Host smart-9886f8e7-ae5f-4443-ad38-163c264c7a82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47561626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.47561626
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3222567432
Short name T530
Test name
Test status
Simulation time 384247198 ps
CPU time 2.39 seconds
Started Jul 12 05:47:58 PM PDT 24
Finished Jul 12 05:48:01 PM PDT 24
Peak memory 199988 kb
Host smart-303704d4-7b6c-46be-9dad-c4ae8fed649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222567432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3222567432
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1466814621
Short name T506
Test name
Test status
Simulation time 164826949 ps
CPU time 1.25 seconds
Started Jul 12 05:47:54 PM PDT 24
Finished Jul 12 05:47:56 PM PDT 24
Peak memory 200312 kb
Host smart-5c7a54a8-8bd5-4b44-81b1-d7b3e0366c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466814621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1466814621
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.815018483
Short name T137
Test name
Test status
Simulation time 73152443 ps
CPU time 0.82 seconds
Started Jul 12 05:48:03 PM PDT 24
Finished Jul 12 05:48:06 PM PDT 24
Peak memory 199844 kb
Host smart-aafbb3b7-c9c4-42cf-9b24-283885892838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815018483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.815018483
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1701697838
Short name T48
Test name
Test status
Simulation time 2356933554 ps
CPU time 8.1 seconds
Started Jul 12 05:48:02 PM PDT 24
Finished Jul 12 05:48:13 PM PDT 24
Peak memory 217856 kb
Host smart-71dce6b0-360e-4c78-baf0-75e14be55d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701697838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1701697838
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.4244798312
Short name T337
Test name
Test status
Simulation time 244649226 ps
CPU time 1.11 seconds
Started Jul 12 05:48:03 PM PDT 24
Finished Jul 12 05:48:06 PM PDT 24
Peak memory 217408 kb
Host smart-2580de74-8a5c-4686-b7f9-d4da059881d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244798312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.4244798312
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1482288385
Short name T391
Test name
Test status
Simulation time 187290742 ps
CPU time 0.87 seconds
Started Jul 12 05:48:03 PM PDT 24
Finished Jul 12 05:48:06 PM PDT 24
Peak memory 199868 kb
Host smart-d614451d-27eb-4055-8e3a-adbc3e1e4314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482288385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1482288385
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.819260310
Short name T101
Test name
Test status
Simulation time 675249546 ps
CPU time 3.84 seconds
Started Jul 12 05:48:03 PM PDT 24
Finished Jul 12 05:48:09 PM PDT 24
Peak memory 200468 kb
Host smart-821c4d3a-2882-4e28-9797-ea03dfc29896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819260310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.819260310
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1724911188
Short name T253
Test name
Test status
Simulation time 154285803 ps
CPU time 1.19 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:04 PM PDT 24
Peak memory 200028 kb
Host smart-80f76a74-04df-4935-ab99-c25af24e5ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724911188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1724911188
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1790829724
Short name T292
Test name
Test status
Simulation time 121359483 ps
CPU time 1.16 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:04 PM PDT 24
Peak memory 200272 kb
Host smart-32cdcf36-dcf7-4d9b-afc3-344ba4c70834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790829724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1790829724
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1404686749
Short name T263
Test name
Test status
Simulation time 4068978860 ps
CPU time 18.98 seconds
Started Jul 12 05:48:02 PM PDT 24
Finished Jul 12 05:48:24 PM PDT 24
Peak memory 208632 kb
Host smart-68e82bd1-052b-479b-b608-085cfc5f2076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404686749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1404686749
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.4042681749
Short name T162
Test name
Test status
Simulation time 427497659 ps
CPU time 2.48 seconds
Started Jul 12 05:48:01 PM PDT 24
Finished Jul 12 05:48:07 PM PDT 24
Peak memory 208268 kb
Host smart-29a659ea-3cf1-4937-8619-0d76f4f0476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042681749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.4042681749
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.952228391
Short name T258
Test name
Test status
Simulation time 157531251 ps
CPU time 1.22 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:03 PM PDT 24
Peak memory 200312 kb
Host smart-e50e3d6e-fbb4-4cfc-8c35-102c4af926da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952228391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.952228391
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.826133801
Short name T157
Test name
Test status
Simulation time 77455413 ps
CPU time 0.81 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:04 PM PDT 24
Peak memory 199864 kb
Host smart-f6a8f223-9ceb-490a-bd93-460ea0566ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826133801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.826133801
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1552517469
Short name T47
Test name
Test status
Simulation time 2353756614 ps
CPU time 7.89 seconds
Started Jul 12 05:48:01 PM PDT 24
Finished Jul 12 05:48:11 PM PDT 24
Peak memory 217800 kb
Host smart-f5ea8af6-f983-4fb6-977c-f4326bdf7931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552517469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1552517469
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.37601983
Short name T247
Test name
Test status
Simulation time 244247324 ps
CPU time 1.04 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:03 PM PDT 24
Peak memory 217408 kb
Host smart-c21b2ee9-c485-4661-bc99-1f3a54a2d3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37601983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.37601983
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.668933776
Short name T18
Test name
Test status
Simulation time 157944470 ps
CPU time 0.83 seconds
Started Jul 12 05:48:01 PM PDT 24
Finished Jul 12 05:48:05 PM PDT 24
Peak memory 199888 kb
Host smart-03c8068c-41ab-46cf-848e-b32a2b182d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668933776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.668933776
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.789882168
Short name T213
Test name
Test status
Simulation time 1448703183 ps
CPU time 5.53 seconds
Started Jul 12 05:47:58 PM PDT 24
Finished Jul 12 05:48:04 PM PDT 24
Peak memory 200392 kb
Host smart-2b7ba4a5-051e-416f-a475-8ec7d9407ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789882168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.789882168
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1697137078
Short name T169
Test name
Test status
Simulation time 109365481 ps
CPU time 1.09 seconds
Started Jul 12 05:47:59 PM PDT 24
Finished Jul 12 05:48:02 PM PDT 24
Peak memory 200092 kb
Host smart-ae98286b-ccd7-4123-9b83-90868fc31726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697137078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1697137078
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1177352547
Short name T505
Test name
Test status
Simulation time 232905776 ps
CPU time 1.55 seconds
Started Jul 12 05:48:02 PM PDT 24
Finished Jul 12 05:48:07 PM PDT 24
Peak memory 200240 kb
Host smart-388bd7eb-75d0-4c7b-a232-5a41dfe931eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177352547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1177352547
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1307049024
Short name T401
Test name
Test status
Simulation time 1249833788 ps
CPU time 5.07 seconds
Started Jul 12 05:48:03 PM PDT 24
Finished Jul 12 05:48:10 PM PDT 24
Peak memory 200328 kb
Host smart-726e78e9-0fc1-429d-b3c1-4ebcf3bd23a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307049024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1307049024
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1882201083
Short name T471
Test name
Test status
Simulation time 134915314 ps
CPU time 1.69 seconds
Started Jul 12 05:48:02 PM PDT 24
Finished Jul 12 05:48:07 PM PDT 24
Peak memory 208236 kb
Host smart-9a233686-931f-42ae-ba0f-1d30699e6c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882201083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1882201083
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1553076289
Short name T297
Test name
Test status
Simulation time 75115717 ps
CPU time 0.79 seconds
Started Jul 12 05:48:01 PM PDT 24
Finished Jul 12 05:48:05 PM PDT 24
Peak memory 199820 kb
Host smart-ef901fc9-6c14-4639-ac8b-4727544e2eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553076289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1553076289
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2394517062
Short name T55
Test name
Test status
Simulation time 1901620389 ps
CPU time 7.09 seconds
Started Jul 12 05:48:03 PM PDT 24
Finished Jul 12 05:48:13 PM PDT 24
Peak memory 221492 kb
Host smart-a652c6c9-bd3e-4704-8525-8481f73e7a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394517062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2394517062
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.811911774
Short name T138
Test name
Test status
Simulation time 255860076 ps
CPU time 1.1 seconds
Started Jul 12 05:48:00 PM PDT 24
Finished Jul 12 05:48:02 PM PDT 24
Peak memory 217444 kb
Host smart-8ab1a466-bbfb-4c3a-8e06-876268b7fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811911774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.811911774
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.79392572
Short name T285
Test name
Test status
Simulation time 94070867 ps
CPU time 0.77 seconds
Started Jul 12 05:48:01 PM PDT 24
Finished Jul 12 05:48:05 PM PDT 24
Peak memory 199848 kb
Host smart-cc333988-c965-436d-8282-f8d412353cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79392572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.79392572
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2800293085
Short name T123
Test name
Test status
Simulation time 1861637247 ps
CPU time 7.09 seconds
Started Jul 12 05:48:02 PM PDT 24
Finished Jul 12 05:48:12 PM PDT 24
Peak memory 200376 kb
Host smart-c21cfbba-fe2b-40f7-8604-5e999d060bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800293085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2800293085
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1896194226
Short name T84
Test name
Test status
Simulation time 182855685 ps
CPU time 1.25 seconds
Started Jul 12 05:47:59 PM PDT 24
Finished Jul 12 05:48:02 PM PDT 24
Peak memory 200088 kb
Host smart-1e9619e7-239f-4d08-b235-695a14f1702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896194226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1896194226
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.562152102
Short name T382
Test name
Test status
Simulation time 184785535 ps
CPU time 1.47 seconds
Started Jul 12 05:47:59 PM PDT 24
Finished Jul 12 05:48:02 PM PDT 24
Peak memory 200252 kb
Host smart-6af10fcd-cdea-4c99-82b8-ae91bd82c507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562152102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.562152102
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.292961877
Short name T122
Test name
Test status
Simulation time 2104805678 ps
CPU time 7.95 seconds
Started Jul 12 05:48:02 PM PDT 24
Finished Jul 12 05:48:12 PM PDT 24
Peak memory 208956 kb
Host smart-ac5b136e-3331-4c1f-a8fb-57e2c6e408b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292961877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.292961877
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1316393135
Short name T128
Test name
Test status
Simulation time 529079977 ps
CPU time 2.79 seconds
Started Jul 12 05:48:03 PM PDT 24
Finished Jul 12 05:48:08 PM PDT 24
Peak memory 199968 kb
Host smart-6d7df58a-b960-4385-b61f-5c6093ecce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316393135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1316393135
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.267144313
Short name T528
Test name
Test status
Simulation time 132783159 ps
CPU time 1.11 seconds
Started Jul 12 05:48:03 PM PDT 24
Finished Jul 12 05:48:07 PM PDT 24
Peak memory 200208 kb
Host smart-bdd866ac-6fa6-47eb-ad41-26a0150f8846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267144313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.267144313
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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