Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8596

1

T1

37

T3

29

T9

166

auto[1]

11467

1

T1

24

T2

4

T3

27

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6154	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6729	1			T1	28		T2	2		T3	16
reset_info_cp[2]	3186	1			T1	9		T2	1		T3	7
reset_info_cp[4]	4060	1			T1	12		T2	1		T3	9
reset_info_cp[8]	107	1			T9	3		T11	1		T25	2
reset_info_cp[16]	105	1			T52	1		T26	1		T45	1
reset_info_cp[32]	113	1			T11	4		T13	1		T93	1
reset_info_cp[64]	116	1			T3	1		T10	1		T11	1
reset_info_cp[128]	113	1			T1	1		T9	2		T11	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3256	1			T1	11		T3	7		T9	62
reset_info_cp[1]	auto[1]	2853	1			T1	16		T2	1		T3	8
reset_info_cp[2]	auto[0]	997	1			T1	6		T3	3		T9	18
reset_info_cp[2]	auto[1]	2189	1			T1	3		T2	1		T3	4
reset_info_cp[4]	auto[0]	1513	1			T1	9		T3	5		T9	32
reset_info_cp[4]	auto[1]	2547	1			T1	3		T2	1		T3	4
reset_info_cp[8]	auto[0]	35	1			T9	2		T11	1		T25	2
reset_info_cp[8]	auto[1]	72	1			T9	1		T47	1		T35	2
reset_info_cp[16]	auto[0]	33	1			T26	1		T136	2		T106	1
reset_info_cp[16]	auto[1]	72	1			T52	1		T45	1		T86	1
reset_info_cp[32]	auto[0]	45	1			T11	2		T13	1		T93	1
reset_info_cp[32]	auto[1]	68	1			T11	2		T32	2		T34	1
reset_info_cp[64]	auto[0]	49	1			T3	1		T13	1		T26	1
reset_info_cp[64]	auto[1]	67	1			T10	1		T11	1		T25	1
reset_info_cp[128]	auto[0]	45	1			T11	1		T26	1		T88	1
reset_info_cp[128]	auto[1]	68	1			T1	1		T9	2		T32	1