Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T535 /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1473972917 Jul 13 06:45:58 PM PDT 24 Jul 13 06:46:00 PM PDT 24 112249080 ps
T536 /workspace/coverage/default/4.rstmgr_reset.705884267 Jul 13 06:45:27 PM PDT 24 Jul 13 06:45:34 PM PDT 24 1516454424 ps
T537 /workspace/coverage/default/14.rstmgr_sw_rst.2921358596 Jul 13 06:45:40 PM PDT 24 Jul 13 06:45:44 PM PDT 24 288956797 ps
T538 /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1651098936 Jul 13 06:46:25 PM PDT 24 Jul 13 06:46:29 PM PDT 24 105582931 ps
T539 /workspace/coverage/default/42.rstmgr_sw_rst.3419976273 Jul 13 06:46:25 PM PDT 24 Jul 13 06:46:29 PM PDT 24 325493372 ps
T73 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2855758601 Jul 13 06:45:07 PM PDT 24 Jul 13 06:45:10 PM PDT 24 422612768 ps
T74 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2774182758 Jul 13 06:45:03 PM PDT 24 Jul 13 06:45:05 PM PDT 24 82487162 ps
T75 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2578223828 Jul 13 06:44:54 PM PDT 24 Jul 13 06:44:58 PM PDT 24 427487556 ps
T117 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2423717452 Jul 13 06:45:03 PM PDT 24 Jul 13 06:45:05 PM PDT 24 124483473 ps
T77 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2356327599 Jul 13 06:45:23 PM PDT 24 Jul 13 06:45:25 PM PDT 24 114489602 ps
T78 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.155329895 Jul 13 06:45:05 PM PDT 24 Jul 13 06:45:09 PM PDT 24 392115931 ps
T540 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1346713898 Jul 13 06:45:04 PM PDT 24 Jul 13 06:45:07 PM PDT 24 254233700 ps
T100 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1788915284 Jul 13 06:44:53 PM PDT 24 Jul 13 06:44:56 PM PDT 24 488417278 ps
T80 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2705726102 Jul 13 06:45:23 PM PDT 24 Jul 13 06:45:27 PM PDT 24 966206387 ps
T79 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1553315822 Jul 13 06:44:55 PM PDT 24 Jul 13 06:44:59 PM PDT 24 426708877 ps
T541 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1664713298 Jul 13 06:44:56 PM PDT 24 Jul 13 06:44:58 PM PDT 24 66695910 ps
T108 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3846531605 Jul 13 06:44:57 PM PDT 24 Jul 13 06:44:59 PM PDT 24 101075201 ps
T94 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.216208032 Jul 13 06:45:05 PM PDT 24 Jul 13 06:45:09 PM PDT 24 379528524 ps
T109 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1348952970 Jul 13 06:45:05 PM PDT 24 Jul 13 06:45:07 PM PDT 24 75524790 ps
T95 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2566934219 Jul 13 06:45:20 PM PDT 24 Jul 13 06:45:25 PM PDT 24 475872398 ps
T542 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2115115285 Jul 13 06:44:57 PM PDT 24 Jul 13 06:44:59 PM PDT 24 63660058 ps
T135 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3399096463 Jul 13 06:44:55 PM PDT 24 Jul 13 06:45:01 PM PDT 24 1017294197 ps
T96 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2951378555 Jul 13 06:45:21 PM PDT 24 Jul 13 06:45:26 PM PDT 24 963456956 ps
T110 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3302630925 Jul 13 06:45:16 PM PDT 24 Jul 13 06:45:19 PM PDT 24 224485206 ps
T97 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3495253755 Jul 13 06:45:12 PM PDT 24 Jul 13 06:45:14 PM PDT 24 171236590 ps
T543 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3093121426 Jul 13 06:45:08 PM PDT 24 Jul 13 06:45:11 PM PDT 24 247360277 ps
T111 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.39129528 Jul 13 06:45:23 PM PDT 24 Jul 13 06:45:26 PM PDT 24 138577185 ps
T98 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1450839731 Jul 13 06:45:05 PM PDT 24 Jul 13 06:45:11 PM PDT 24 469821300 ps
T544 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.37855871 Jul 13 06:45:02 PM PDT 24 Jul 13 06:45:04 PM PDT 24 61690661 ps
T99 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.104581218 Jul 13 06:45:16 PM PDT 24 Jul 13 06:45:18 PM PDT 24 165582915 ps
T112 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2588266359 Jul 13 06:45:17 PM PDT 24 Jul 13 06:45:19 PM PDT 24 75313064 ps
T113 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1583373887 Jul 13 06:45:11 PM PDT 24 Jul 13 06:45:12 PM PDT 24 57903048 ps
T545 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3800367627 Jul 13 06:44:54 PM PDT 24 Jul 13 06:45:00 PM PDT 24 794201804 ps
T101 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.886079983 Jul 13 06:45:15 PM PDT 24 Jul 13 06:45:18 PM PDT 24 166160093 ps
T114 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.526569813 Jul 13 06:45:16 PM PDT 24 Jul 13 06:45:18 PM PDT 24 56152896 ps
T546 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2834176597 Jul 13 06:45:16 PM PDT 24 Jul 13 06:45:18 PM PDT 24 62785951 ps
T547 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2193949286 Jul 13 06:45:09 PM PDT 24 Jul 13 06:45:13 PM PDT 24 876080376 ps
T548 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.323391058 Jul 13 06:45:14 PM PDT 24 Jul 13 06:45:17 PM PDT 24 207907796 ps
T123 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3349170057 Jul 13 06:44:57 PM PDT 24 Jul 13 06:44:59 PM PDT 24 127408037 ps
T549 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2215074040 Jul 13 06:45:00 PM PDT 24 Jul 13 06:45:02 PM PDT 24 94441401 ps
T115 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1432250113 Jul 13 06:44:56 PM PDT 24 Jul 13 06:44:59 PM PDT 24 76897733 ps
T116 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.403004149 Jul 13 06:45:07 PM PDT 24 Jul 13 06:45:09 PM PDT 24 66699542 ps
T118 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3052064421 Jul 13 06:45:15 PM PDT 24 Jul 13 06:45:19 PM PDT 24 888117421 ps
T550 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.116053521 Jul 13 06:45:16 PM PDT 24 Jul 13 06:45:18 PM PDT 24 88238499 ps
T551 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3712451438 Jul 13 06:45:02 PM PDT 24 Jul 13 06:45:04 PM PDT 24 196317811 ps
T552 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3032061542 Jul 13 06:44:56 PM PDT 24 Jul 13 06:44:58 PM PDT 24 124485400 ps
T133 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.100631543 Jul 13 06:44:55 PM PDT 24 Jul 13 06:44:59 PM PDT 24 808238466 ps
T553 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3687805278 Jul 13 06:45:03 PM PDT 24 Jul 13 06:45:05 PM PDT 24 168411818 ps
T554 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2340332879 Jul 13 06:45:06 PM PDT 24 Jul 13 06:45:09 PM PDT 24 143400587 ps
T555 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2830778983 Jul 13 06:45:19 PM PDT 24 Jul 13 06:45:22 PM PDT 24 175658489 ps
T556 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1556123085 Jul 13 06:45:02 PM PDT 24 Jul 13 06:45:05 PM PDT 24 180540960 ps
T557 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.194972247 Jul 13 06:45:04 PM PDT 24 Jul 13 06:45:07 PM PDT 24 245023054 ps
T558 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.709200206 Jul 13 06:45:18 PM PDT 24 Jul 13 06:45:20 PM PDT 24 132860887 ps
T559 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.745747837 Jul 13 06:45:03 PM PDT 24 Jul 13 06:45:07 PM PDT 24 384993971 ps
T560 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1294020325 Jul 13 06:44:55 PM PDT 24 Jul 13 06:44:57 PM PDT 24 71448634 ps
T561 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3620441715 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:53 PM PDT 24 173330419 ps
T122 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.242021391 Jul 13 06:45:03 PM PDT 24 Jul 13 06:45:07 PM PDT 24 918868677 ps
T119 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.848812663 Jul 13 06:44:55 PM PDT 24 Jul 13 06:45:00 PM PDT 24 922838939 ps
T562 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1304358795 Jul 13 06:45:23 PM PDT 24 Jul 13 06:45:26 PM PDT 24 137609319 ps
T121 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3891145828 Jul 13 06:45:06 PM PDT 24 Jul 13 06:45:09 PM PDT 24 431997191 ps
T563 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.694013126 Jul 13 06:44:53 PM PDT 24 Jul 13 06:44:55 PM PDT 24 164783212 ps
T564 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2878912893 Jul 13 06:48:53 PM PDT 24 Jul 13 06:48:56 PM PDT 24 1147791773 ps
T565 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.881778854 Jul 13 06:45:21 PM PDT 24 Jul 13 06:45:24 PM PDT 24 263033433 ps
T566 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4060709495 Jul 13 06:45:00 PM PDT 24 Jul 13 06:45:04 PM PDT 24 274742580 ps
T567 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.809372857 Jul 13 06:45:08 PM PDT 24 Jul 13 06:45:09 PM PDT 24 63738690 ps
T568 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3707934954 Jul 13 06:45:17 PM PDT 24 Jul 13 06:45:22 PM PDT 24 409860565 ps
T569 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2234109610 Jul 13 06:44:56 PM PDT 24 Jul 13 06:45:05 PM PDT 24 1556418952 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.582524597 Jul 13 06:45:04 PM PDT 24 Jul 13 06:45:06 PM PDT 24 171541795 ps
T571 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1448187826 Jul 13 06:45:17 PM PDT 24 Jul 13 06:45:20 PM PDT 24 133159268 ps
T572 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2386313498 Jul 13 06:44:52 PM PDT 24 Jul 13 06:44:54 PM PDT 24 103747116 ps
T573 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4124489174 Jul 13 06:45:03 PM PDT 24 Jul 13 06:45:05 PM PDT 24 182355812 ps
T574 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.742785137 Jul 13 06:45:02 PM PDT 24 Jul 13 06:45:04 PM PDT 24 143283052 ps
T575 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4206408425 Jul 13 06:45:17 PM PDT 24 Jul 13 06:45:19 PM PDT 24 129865305 ps
T576 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2439455825 Jul 13 06:44:54 PM PDT 24 Jul 13 06:44:57 PM PDT 24 121747482 ps
T577 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.456271960 Jul 13 06:45:09 PM PDT 24 Jul 13 06:45:11 PM PDT 24 181957217 ps
T578 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3376568354 Jul 13 06:45:04 PM PDT 24 Jul 13 06:45:07 PM PDT 24 195189207 ps
T579 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.714422783 Jul 13 06:45:06 PM PDT 24 Jul 13 06:45:08 PM PDT 24 57288197 ps
T580 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2359332172 Jul 13 06:45:05 PM PDT 24 Jul 13 06:45:09 PM PDT 24 783904607 ps
T581 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3429012297 Jul 13 06:45:02 PM PDT 24 Jul 13 06:45:05 PM PDT 24 204944951 ps
T582 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3183375800 Jul 13 06:44:52 PM PDT 24 Jul 13 06:44:55 PM PDT 24 231456223 ps
T583 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3259981937 Jul 13 06:44:55 PM PDT 24 Jul 13 06:44:58 PM PDT 24 101582631 ps
T584 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1019868052 Jul 13 06:44:55 PM PDT 24 Jul 13 06:45:00 PM PDT 24 241533340 ps
T585 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.558717877 Jul 13 06:45:14 PM PDT 24 Jul 13 06:45:20 PM PDT 24 631209089 ps
T586 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.331289960 Jul 13 06:45:16 PM PDT 24 Jul 13 06:45:20 PM PDT 24 771249065 ps
T587 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.163462375 Jul 13 06:44:58 PM PDT 24 Jul 13 06:45:00 PM PDT 24 141411727 ps
T588 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.741573366 Jul 13 06:45:06 PM PDT 24 Jul 13 06:45:09 PM PDT 24 78773780 ps
T589 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4072208878 Jul 13 06:45:20 PM PDT 24 Jul 13 06:45:22 PM PDT 24 66731902 ps
T134 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.763407810 Jul 13 06:45:14 PM PDT 24 Jul 13 06:45:16 PM PDT 24 421283615 ps
T590 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1618990466 Jul 13 06:44:55 PM PDT 24 Jul 13 06:44:57 PM PDT 24 129865596 ps
T591 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2355143251 Jul 13 06:45:05 PM PDT 24 Jul 13 06:45:08 PM PDT 24 195490785 ps
T592 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3474624459 Jul 13 06:45:09 PM PDT 24 Jul 13 06:45:11 PM PDT 24 67321779 ps
T593 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.677001506 Jul 13 06:44:57 PM PDT 24 Jul 13 06:44:59 PM PDT 24 161607936 ps
T594 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4098860739 Jul 13 06:45:20 PM PDT 24 Jul 13 06:45:25 PM PDT 24 907083866 ps
T595 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4118641690 Jul 13 06:45:04 PM PDT 24 Jul 13 06:45:07 PM PDT 24 134982326 ps
T596 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2556478244 Jul 13 06:44:55 PM PDT 24 Jul 13 06:44:57 PM PDT 24 90231110 ps
T597 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.345527128 Jul 13 06:45:13 PM PDT 24 Jul 13 06:45:15 PM PDT 24 247404126 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.38353618 Jul 13 06:45:01 PM PDT 24 Jul 13 06:45:04 PM PDT 24 503818516 ps
T599 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3787398650 Jul 13 06:45:21 PM PDT 24 Jul 13 06:45:27 PM PDT 24 704419743 ps
T600 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3921909184 Jul 13 06:45:09 PM PDT 24 Jul 13 06:45:15 PM PDT 24 812652962 ps
T601 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2276779582 Jul 13 06:45:16 PM PDT 24 Jul 13 06:45:22 PM PDT 24 640576609 ps
T602 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4029678251 Jul 13 06:45:02 PM PDT 24 Jul 13 06:45:03 PM PDT 24 76698382 ps
T603 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3514216840 Jul 13 06:45:15 PM PDT 24 Jul 13 06:45:17 PM PDT 24 68650940 ps
T604 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.761770264 Jul 13 06:44:58 PM PDT 24 Jul 13 06:45:00 PM PDT 24 85284003 ps
T605 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2379277298 Jul 13 06:44:58 PM PDT 24 Jul 13 06:45:01 PM PDT 24 156909333 ps
T606 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3074615994 Jul 13 06:45:06 PM PDT 24 Jul 13 06:45:09 PM PDT 24 92605147 ps
T607 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1547662670 Jul 13 06:45:01 PM PDT 24 Jul 13 06:45:03 PM PDT 24 68239313 ps
T608 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.599303901 Jul 13 06:45:21 PM PDT 24 Jul 13 06:45:24 PM PDT 24 111989132 ps
T609 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3609941994 Jul 13 06:45:03 PM PDT 24 Jul 13 06:45:05 PM PDT 24 144565376 ps
T610 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3788299860 Jul 13 06:44:58 PM PDT 24 Jul 13 06:45:02 PM PDT 24 386236693 ps
T611 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.474045301 Jul 13 06:45:01 PM PDT 24 Jul 13 06:45:03 PM PDT 24 88163679 ps
T612 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1868062438 Jul 13 06:45:00 PM PDT 24 Jul 13 06:45:02 PM PDT 24 212825480 ps
T120 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.232675942 Jul 13 06:45:14 PM PDT 24 Jul 13 06:45:18 PM PDT 24 864864742 ps
T613 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.64138657 Jul 13 06:45:12 PM PDT 24 Jul 13 06:45:14 PM PDT 24 114066470 ps
T614 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4274961432 Jul 13 06:45:03 PM PDT 24 Jul 13 06:45:04 PM PDT 24 68076292 ps
T615 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4205149416 Jul 13 06:45:04 PM PDT 24 Jul 13 06:45:07 PM PDT 24 473825818 ps
T616 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3110851770 Jul 13 06:45:06 PM PDT 24 Jul 13 06:45:09 PM PDT 24 236247864 ps
T617 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1864615158 Jul 13 06:44:56 PM PDT 24 Jul 13 06:44:59 PM PDT 24 538660908 ps
T618 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2379802422 Jul 13 06:44:58 PM PDT 24 Jul 13 06:45:01 PM PDT 24 229243039 ps
T619 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1013776141 Jul 13 06:45:08 PM PDT 24 Jul 13 06:45:10 PM PDT 24 142022896 ps
T620 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4196117874 Jul 13 06:45:08 PM PDT 24 Jul 13 06:45:10 PM PDT 24 75956211 ps

Test location /workspace/coverage/default/49.rstmgr_stress_all.2028888870
Short name T9
Test name
Test status
Simulation time 7978799400 ps
CPU time 31.94 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:47:13 PM PDT 24
Peak memory 208624 kb
Host smart-103dc65a-25b0-4537-8ec3-831590d5e70b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028888870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2028888870
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1604149365
Short name T72
Test name
Test status
Simulation time 140660476 ps
CPU time 1.85 seconds
Started Jul 13 06:45:26 PM PDT 24
Finished Jul 13 06:45:29 PM PDT 24
Peak memory 208312 kb
Host smart-3e7f9cf3-6dd7-474d-aac1-ac7bf5a4cc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604149365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1604149365
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1553315822
Short name T79
Test name
Test status
Simulation time 426708877 ps
CPU time 3.48 seconds
Started Jul 13 06:44:55 PM PDT 24
Finished Jul 13 06:44:59 PM PDT 24
Peak memory 208572 kb
Host smart-bed509a4-b5a7-46b6-8e4c-d3815fac83f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553315822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1553315822
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2525535981
Short name T11
Test name
Test status
Simulation time 7421301510 ps
CPU time 33.66 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:46:21 PM PDT 24
Peak memory 208644 kb
Host smart-c661c3f5-c7f9-4fe6-adac-8eb617c76181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525535981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2525535981
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1055824046
Short name T81
Test name
Test status
Simulation time 16514867657 ps
CPU time 26.97 seconds
Started Jul 13 06:45:17 PM PDT 24
Finished Jul 13 06:45:46 PM PDT 24
Peak memory 216360 kb
Host smart-b8fbedba-fc39-4698-9b85-6e053f7e7031
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055824046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1055824046
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.635298798
Short name T36
Test name
Test status
Simulation time 2166139197 ps
CPU time 8.46 seconds
Started Jul 13 06:46:12 PM PDT 24
Finished Jul 13 06:46:21 PM PDT 24
Peak memory 221756 kb
Host smart-b47533f6-4830-4b56-8895-3c3b3fbd0008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635298798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.635298798
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1788915284
Short name T100
Test name
Test status
Simulation time 488417278 ps
CPU time 2.02 seconds
Started Jul 13 06:44:53 PM PDT 24
Finished Jul 13 06:44:56 PM PDT 24
Peak memory 200440 kb
Host smart-c82ea637-9ed5-4417-9cbc-634956686d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788915284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1788915284
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2019392236
Short name T105
Test name
Test status
Simulation time 12368837993 ps
CPU time 41.85 seconds
Started Jul 13 06:45:30 PM PDT 24
Finished Jul 13 06:46:13 PM PDT 24
Peak memory 208668 kb
Host smart-9338c86a-18f2-48e9-aad4-919b842b27a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019392236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2019392236
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3977895971
Short name T6
Test name
Test status
Simulation time 72108324 ps
CPU time 0.76 seconds
Started Jul 13 06:45:54 PM PDT 24
Finished Jul 13 06:46:00 PM PDT 24
Peak memory 199888 kb
Host smart-0122eb4d-88fd-4c4b-a920-497f602fd999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977895971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3977895971
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3835141476
Short name T55
Test name
Test status
Simulation time 153408593 ps
CPU time 1.22 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:42 PM PDT 24
Peak memory 200324 kb
Host smart-81a9473b-11e3-4bfa-a001-6828a4b6c49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835141476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3835141476
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.100631543
Short name T133
Test name
Test status
Simulation time 808238466 ps
CPU time 2.96 seconds
Started Jul 13 06:44:55 PM PDT 24
Finished Jul 13 06:44:59 PM PDT 24
Peak memory 200452 kb
Host smart-7128bd36-c9d9-4cc0-9d4d-fa7e4a448f04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100631543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
100631543
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2238291417
Short name T136
Test name
Test status
Simulation time 163446173 ps
CPU time 1.27 seconds
Started Jul 13 06:45:48 PM PDT 24
Finished Jul 13 06:45:51 PM PDT 24
Peak memory 200304 kb
Host smart-4debbcc6-181e-43ec-a59f-29617fc0dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238291417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2238291417
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3465048761
Short name T32
Test name
Test status
Simulation time 2334973286 ps
CPU time 8.85 seconds
Started Jul 13 06:46:38 PM PDT 24
Finished Jul 13 06:46:48 PM PDT 24
Peak memory 217288 kb
Host smart-37b7aaa8-7284-48fb-a1fa-32fe563de8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465048761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3465048761
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3620441715
Short name T561
Test name
Test status
Simulation time 173330419 ps
CPU time 2.62 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:53 PM PDT 24
Peak memory 208576 kb
Host smart-c06d3b71-5b36-4579-be26-0541de2351e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620441715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3620441715
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3052064421
Short name T118
Test name
Test status
Simulation time 888117421 ps
CPU time 3.26 seconds
Started Jul 13 06:45:15 PM PDT 24
Finished Jul 13 06:45:19 PM PDT 24
Peak memory 200528 kb
Host smart-e9ab6d17-be0f-4fd7-9011-91fddde9a6fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052064421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3052064421
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.232675942
Short name T120
Test name
Test status
Simulation time 864864742 ps
CPU time 3.28 seconds
Started Jul 13 06:45:14 PM PDT 24
Finished Jul 13 06:45:18 PM PDT 24
Peak memory 200448 kb
Host smart-f97f367a-0708-4d0f-88ec-f0a9cf96698c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232675942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.232675942
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1432250113
Short name T115
Test name
Test status
Simulation time 76897733 ps
CPU time 0.94 seconds
Started Jul 13 06:44:56 PM PDT 24
Finished Jul 13 06:44:59 PM PDT 24
Peak memory 200304 kb
Host smart-2708b5a5-1154-4d10-b6c3-376359818fa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432250113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1432250113
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2540627475
Short name T18
Test name
Test status
Simulation time 108785451 ps
CPU time 0.86 seconds
Started Jul 13 06:45:49 PM PDT 24
Finished Jul 13 06:45:51 PM PDT 24
Peak memory 199900 kb
Host smart-86d80465-c32d-4a7f-8186-936f64b402d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540627475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2540627475
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.196426165
Short name T334
Test name
Test status
Simulation time 1221342130 ps
CPU time 6.01 seconds
Started Jul 13 06:45:34 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 217772 kb
Host smart-a00d6ef0-4197-458d-a6b8-f0cfd3a0dd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196426165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.196426165
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3183375800
Short name T582
Test name
Test status
Simulation time 231456223 ps
CPU time 1.72 seconds
Started Jul 13 06:44:52 PM PDT 24
Finished Jul 13 06:44:55 PM PDT 24
Peak memory 200264 kb
Host smart-5bedefe0-1941-4c6f-9377-064724ab5190
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183375800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
183375800
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3399096463
Short name T135
Test name
Test status
Simulation time 1017294197 ps
CPU time 4.91 seconds
Started Jul 13 06:44:55 PM PDT 24
Finished Jul 13 06:45:01 PM PDT 24
Peak memory 200336 kb
Host smart-3a5b848f-dce1-4263-8364-c67dbc81417d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399096463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
399096463
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2386313498
Short name T572
Test name
Test status
Simulation time 103747116 ps
CPU time 0.85 seconds
Started Jul 13 06:44:52 PM PDT 24
Finished Jul 13 06:44:54 PM PDT 24
Peak memory 200176 kb
Host smart-9a242c29-ce45-4c19-90cb-ba6a78783c14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386313498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
386313498
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2439455825
Short name T576
Test name
Test status
Simulation time 121747482 ps
CPU time 1.27 seconds
Started Jul 13 06:44:54 PM PDT 24
Finished Jul 13 06:44:57 PM PDT 24
Peak memory 208572 kb
Host smart-42422acb-f1ef-4079-b509-f7d3db093d46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439455825 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2439455825
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4274961432
Short name T614
Test name
Test status
Simulation time 68076292 ps
CPU time 0.87 seconds
Started Jul 13 06:45:03 PM PDT 24
Finished Jul 13 06:45:04 PM PDT 24
Peak memory 200232 kb
Host smart-257f67a9-8af9-4124-a2ed-cfa1c34027fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274961432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.4274961432
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.694013126
Short name T563
Test name
Test status
Simulation time 164783212 ps
CPU time 1.18 seconds
Started Jul 13 06:44:53 PM PDT 24
Finished Jul 13 06:44:55 PM PDT 24
Peak memory 200240 kb
Host smart-e041e7f3-981d-463a-bfc2-a88eb4d6ab29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694013126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.694013126
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.38353618
Short name T598
Test name
Test status
Simulation time 503818516 ps
CPU time 2.19 seconds
Started Jul 13 06:45:01 PM PDT 24
Finished Jul 13 06:45:04 PM PDT 24
Peak memory 200516 kb
Host smart-9a261a09-8eec-41c2-aaa2-87e47b36f988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38353618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.38353618
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1346713898
Short name T540
Test name
Test status
Simulation time 254233700 ps
CPU time 1.62 seconds
Started Jul 13 06:45:04 PM PDT 24
Finished Jul 13 06:45:07 PM PDT 24
Peak memory 200432 kb
Host smart-24aa8bd9-1624-4c2a-8c6a-8e7268dfcbb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346713898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
346713898
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3800367627
Short name T545
Test name
Test status
Simulation time 794201804 ps
CPU time 4.45 seconds
Started Jul 13 06:44:54 PM PDT 24
Finished Jul 13 06:45:00 PM PDT 24
Peak memory 200412 kb
Host smart-20f661c4-6e20-420b-a1c4-4b9e46a12914
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800367627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
800367627
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2423717452
Short name T117
Test name
Test status
Simulation time 124483473 ps
CPU time 0.95 seconds
Started Jul 13 06:45:03 PM PDT 24
Finished Jul 13 06:45:05 PM PDT 24
Peak memory 200184 kb
Host smart-44c0dbd9-b636-4945-b98b-687d2a525006
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423717452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
423717452
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3712451438
Short name T551
Test name
Test status
Simulation time 196317811 ps
CPU time 1.35 seconds
Started Jul 13 06:45:02 PM PDT 24
Finished Jul 13 06:45:04 PM PDT 24
Peak memory 200324 kb
Host smart-8bdd09f8-c1b3-4e98-8ffb-ef3adf50a4b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712451438 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3712451438
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2115115285
Short name T542
Test name
Test status
Simulation time 63660058 ps
CPU time 0.79 seconds
Started Jul 13 06:44:57 PM PDT 24
Finished Jul 13 06:44:59 PM PDT 24
Peak memory 200144 kb
Host smart-6d5be676-2b07-40c0-bf05-d70626877bc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115115285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2115115285
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.456271960
Short name T577
Test name
Test status
Simulation time 181957217 ps
CPU time 1.35 seconds
Started Jul 13 06:45:09 PM PDT 24
Finished Jul 13 06:45:11 PM PDT 24
Peak memory 208512 kb
Host smart-33250da8-6f59-4782-b46a-b2b2935dafdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456271960 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.456271960
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4196117874
Short name T620
Test name
Test status
Simulation time 75956211 ps
CPU time 0.9 seconds
Started Jul 13 06:45:08 PM PDT 24
Finished Jul 13 06:45:10 PM PDT 24
Peak memory 200120 kb
Host smart-fff7f0fc-fc79-4076-90a1-54a2bdb37238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196117874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4196117874
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2340332879
Short name T554
Test name
Test status
Simulation time 143400587 ps
CPU time 1.13 seconds
Started Jul 13 06:45:06 PM PDT 24
Finished Jul 13 06:45:09 PM PDT 24
Peak memory 200296 kb
Host smart-ee4471ea-a462-4a71-94b5-821be2955b30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340332879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2340332879
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.558717877
Short name T585
Test name
Test status
Simulation time 631209089 ps
CPU time 4.23 seconds
Started Jul 13 06:45:14 PM PDT 24
Finished Jul 13 06:45:20 PM PDT 24
Peak memory 208780 kb
Host smart-8120d2ad-e990-4d86-ad52-c4c57050802f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558717877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.558717877
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2855758601
Short name T73
Test name
Test status
Simulation time 422612768 ps
CPU time 1.97 seconds
Started Jul 13 06:45:07 PM PDT 24
Finished Jul 13 06:45:10 PM PDT 24
Peak memory 200492 kb
Host smart-5783b0b6-d168-4d56-8870-fcdd113a735e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855758601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2855758601
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.323391058
Short name T548
Test name
Test status
Simulation time 207907796 ps
CPU time 1.39 seconds
Started Jul 13 06:45:14 PM PDT 24
Finished Jul 13 06:45:17 PM PDT 24
Peak memory 208628 kb
Host smart-64a80d8c-7259-49e2-bdb3-8aeb7a8088ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323391058 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.323391058
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.403004149
Short name T116
Test name
Test status
Simulation time 66699542 ps
CPU time 0.79 seconds
Started Jul 13 06:45:07 PM PDT 24
Finished Jul 13 06:45:09 PM PDT 24
Peak memory 200244 kb
Host smart-4236b1c0-4b13-4135-8dde-bd7c011b4e9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403004149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.403004149
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.194972247
Short name T557
Test name
Test status
Simulation time 245023054 ps
CPU time 1.59 seconds
Started Jul 13 06:45:04 PM PDT 24
Finished Jul 13 06:45:07 PM PDT 24
Peak memory 200476 kb
Host smart-9c99cdab-a7e8-487e-a949-5d5918cd0380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194972247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.194972247
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.216208032
Short name T94
Test name
Test status
Simulation time 379528524 ps
CPU time 3.01 seconds
Started Jul 13 06:45:05 PM PDT 24
Finished Jul 13 06:45:09 PM PDT 24
Peak memory 208564 kb
Host smart-b3963fa5-f3fd-4bd0-86ef-5ebbc42852bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216208032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.216208032
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.763407810
Short name T134
Test name
Test status
Simulation time 421283615 ps
CPU time 1.91 seconds
Started Jul 13 06:45:14 PM PDT 24
Finished Jul 13 06:45:16 PM PDT 24
Peak memory 200492 kb
Host smart-641244b8-df45-4874-af21-8408a58ad2c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763407810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.763407810
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.64138657
Short name T613
Test name
Test status
Simulation time 114066470 ps
CPU time 1.03 seconds
Started Jul 13 06:45:12 PM PDT 24
Finished Jul 13 06:45:14 PM PDT 24
Peak memory 200292 kb
Host smart-abe1b436-95ba-4188-9828-a3aed9e363a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64138657 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.64138657
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.809372857
Short name T567
Test name
Test status
Simulation time 63738690 ps
CPU time 0.9 seconds
Started Jul 13 06:45:08 PM PDT 24
Finished Jul 13 06:45:09 PM PDT 24
Peak memory 200264 kb
Host smart-315b3c8b-caa3-4c7b-aa6c-6e22d4714d7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809372857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.809372857
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3074615994
Short name T606
Test name
Test status
Simulation time 92605147 ps
CPU time 1.24 seconds
Started Jul 13 06:45:06 PM PDT 24
Finished Jul 13 06:45:09 PM PDT 24
Peak memory 200488 kb
Host smart-3ff9772e-e902-4589-9bda-42e04b0c247d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074615994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3074615994
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.345527128
Short name T597
Test name
Test status
Simulation time 247404126 ps
CPU time 1.85 seconds
Started Jul 13 06:45:13 PM PDT 24
Finished Jul 13 06:45:15 PM PDT 24
Peak memory 208560 kb
Host smart-ed32ff2c-b9ca-4043-ac54-66eab859e717
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345527128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.345527128
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1013776141
Short name T619
Test name
Test status
Simulation time 142022896 ps
CPU time 1.23 seconds
Started Jul 13 06:45:08 PM PDT 24
Finished Jul 13 06:45:10 PM PDT 24
Peak memory 208560 kb
Host smart-83b7e230-949d-4f9c-afde-968369cc131e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013776141 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1013776141
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.714422783
Short name T579
Test name
Test status
Simulation time 57288197 ps
CPU time 0.77 seconds
Started Jul 13 06:45:06 PM PDT 24
Finished Jul 13 06:45:08 PM PDT 24
Peak memory 200272 kb
Host smart-e453c523-1970-423e-9ecf-17262ff8a1b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714422783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.714422783
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.741573366
Short name T588
Test name
Test status
Simulation time 78773780 ps
CPU time 1.01 seconds
Started Jul 13 06:45:06 PM PDT 24
Finished Jul 13 06:45:09 PM PDT 24
Peak memory 200300 kb
Host smart-2fc6e6e4-5add-415f-a322-67e043a12914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741573366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.741573366
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.155329895
Short name T78
Test name
Test status
Simulation time 392115931 ps
CPU time 2.69 seconds
Started Jul 13 06:45:05 PM PDT 24
Finished Jul 13 06:45:09 PM PDT 24
Peak memory 208592 kb
Host smart-08c46e09-0783-4961-8ce8-e3010a6298ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155329895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.155329895
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2878912893
Short name T564
Test name
Test status
Simulation time 1147791773 ps
CPU time 3.35 seconds
Started Jul 13 06:48:53 PM PDT 24
Finished Jul 13 06:48:56 PM PDT 24
Peak memory 200720 kb
Host smart-05b50172-f25b-4ae7-82e3-7eb725ded174
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878912893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2878912893
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.886079983
Short name T101
Test name
Test status
Simulation time 166160093 ps
CPU time 1.52 seconds
Started Jul 13 06:45:15 PM PDT 24
Finished Jul 13 06:45:18 PM PDT 24
Peak memory 208696 kb
Host smart-0c212387-e3a8-416e-9a20-5ffc9c0aca10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886079983 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.886079983
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1583373887
Short name T113
Test name
Test status
Simulation time 57903048 ps
CPU time 0.95 seconds
Started Jul 13 06:45:11 PM PDT 24
Finished Jul 13 06:45:12 PM PDT 24
Peak memory 200448 kb
Host smart-4265d182-de38-4a14-923b-35e079497011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583373887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1583373887
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.881778854
Short name T565
Test name
Test status
Simulation time 263033433 ps
CPU time 1.73 seconds
Started Jul 13 06:45:21 PM PDT 24
Finished Jul 13 06:45:24 PM PDT 24
Peak memory 200416 kb
Host smart-42ce1798-8243-4650-8b11-57d6c9687f0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881778854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.881778854
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1450839731
Short name T98
Test name
Test status
Simulation time 469821300 ps
CPU time 3.59 seconds
Started Jul 13 06:45:05 PM PDT 24
Finished Jul 13 06:45:11 PM PDT 24
Peak memory 200368 kb
Host smart-dc4c8e6c-17d8-4276-a768-6ff15fd51520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450839731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1450839731
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2359332172
Short name T580
Test name
Test status
Simulation time 783904607 ps
CPU time 2.82 seconds
Started Jul 13 06:45:05 PM PDT 24
Finished Jul 13 06:45:09 PM PDT 24
Peak memory 200588 kb
Host smart-8d735849-6e20-4aa7-ab27-6d1fce09f6a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359332172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2359332172
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.104581218
Short name T99
Test name
Test status
Simulation time 165582915 ps
CPU time 1.46 seconds
Started Jul 13 06:45:16 PM PDT 24
Finished Jul 13 06:45:18 PM PDT 24
Peak memory 208704 kb
Host smart-daf68a75-abc0-48a2-8c2c-29d406796d84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104581218 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.104581218
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3514216840
Short name T603
Test name
Test status
Simulation time 68650940 ps
CPU time 0.75 seconds
Started Jul 13 06:45:15 PM PDT 24
Finished Jul 13 06:45:17 PM PDT 24
Peak memory 200168 kb
Host smart-295c287a-e43f-4c61-a3d6-e93800f3cddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514216840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3514216840
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.39129528
Short name T111
Test name
Test status
Simulation time 138577185 ps
CPU time 1.14 seconds
Started Jul 13 06:45:23 PM PDT 24
Finished Jul 13 06:45:26 PM PDT 24
Peak memory 200296 kb
Host smart-a39b7fff-7370-4236-89d8-cac41f9b602d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39129528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sam
e_csr_outstanding.39129528
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3707934954
Short name T568
Test name
Test status
Simulation time 409860565 ps
CPU time 3.2 seconds
Started Jul 13 06:45:17 PM PDT 24
Finished Jul 13 06:45:22 PM PDT 24
Peak memory 216584 kb
Host smart-fe62da28-2b8d-4f24-aaad-537328658d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707934954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3707934954
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1448187826
Short name T571
Test name
Test status
Simulation time 133159268 ps
CPU time 1.15 seconds
Started Jul 13 06:45:17 PM PDT 24
Finished Jul 13 06:45:20 PM PDT 24
Peak memory 208828 kb
Host smart-91bb8590-b188-4549-8d65-7d25e8e2c284
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448187826 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1448187826
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.526569813
Short name T114
Test name
Test status
Simulation time 56152896 ps
CPU time 0.73 seconds
Started Jul 13 06:45:16 PM PDT 24
Finished Jul 13 06:45:18 PM PDT 24
Peak memory 200248 kb
Host smart-25b73dc3-d902-484a-827f-6a8a81ad645b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526569813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.526569813
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2588266359
Short name T112
Test name
Test status
Simulation time 75313064 ps
CPU time 1.01 seconds
Started Jul 13 06:45:17 PM PDT 24
Finished Jul 13 06:45:19 PM PDT 24
Peak memory 200296 kb
Host smart-57a59cad-2fb4-4e8d-a7fc-7d952e6a5717
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588266359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2588266359
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3787398650
Short name T599
Test name
Test status
Simulation time 704419743 ps
CPU time 4.34 seconds
Started Jul 13 06:45:21 PM PDT 24
Finished Jul 13 06:45:27 PM PDT 24
Peak memory 208604 kb
Host smart-d094507c-a4a8-4595-afc8-1d1a5bd6b78f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787398650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3787398650
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4098860739
Short name T594
Test name
Test status
Simulation time 907083866 ps
CPU time 3.25 seconds
Started Jul 13 06:45:20 PM PDT 24
Finished Jul 13 06:45:25 PM PDT 24
Peak memory 200384 kb
Host smart-82689326-1c17-435d-80bf-9942b5bd9894
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098860739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.4098860739
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2830778983
Short name T555
Test name
Test status
Simulation time 175658489 ps
CPU time 1.68 seconds
Started Jul 13 06:45:19 PM PDT 24
Finished Jul 13 06:45:22 PM PDT 24
Peak memory 208712 kb
Host smart-a7d21ec7-89f3-4569-bdfb-d8d106306fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830778983 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2830778983
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.116053521
Short name T550
Test name
Test status
Simulation time 88238499 ps
CPU time 0.9 seconds
Started Jul 13 06:45:16 PM PDT 24
Finished Jul 13 06:45:18 PM PDT 24
Peak memory 200120 kb
Host smart-c2691655-70b4-4e27-918b-a1433a3f912b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116053521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.116053521
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.709200206
Short name T558
Test name
Test status
Simulation time 132860887 ps
CPU time 1.03 seconds
Started Jul 13 06:45:18 PM PDT 24
Finished Jul 13 06:45:20 PM PDT 24
Peak memory 200300 kb
Host smart-683997d5-21c3-4fb0-a640-839cd648b6a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709200206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.709200206
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2566934219
Short name T95
Test name
Test status
Simulation time 475872398 ps
CPU time 3.01 seconds
Started Jul 13 06:45:20 PM PDT 24
Finished Jul 13 06:45:25 PM PDT 24
Peak memory 208556 kb
Host smart-a6f80bdb-e887-4a60-8d02-2be1382ab61a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566934219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2566934219
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2705726102
Short name T80
Test name
Test status
Simulation time 966206387 ps
CPU time 2.98 seconds
Started Jul 13 06:45:23 PM PDT 24
Finished Jul 13 06:45:27 PM PDT 24
Peak memory 200372 kb
Host smart-c5cfe393-a32e-4705-ac25-1e81110afb87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705726102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2705726102
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2356327599
Short name T77
Test name
Test status
Simulation time 114489602 ps
CPU time 0.92 seconds
Started Jul 13 06:45:23 PM PDT 24
Finished Jul 13 06:45:25 PM PDT 24
Peak memory 200304 kb
Host smart-edc6ac99-7874-4f4d-a0fa-8ffcb4b5dd95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356327599 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2356327599
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4072208878
Short name T589
Test name
Test status
Simulation time 66731902 ps
CPU time 0.82 seconds
Started Jul 13 06:45:20 PM PDT 24
Finished Jul 13 06:45:22 PM PDT 24
Peak memory 200244 kb
Host smart-524537db-e62f-4086-91bb-4d565b55591c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072208878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4072208878
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3302630925
Short name T110
Test name
Test status
Simulation time 224485206 ps
CPU time 1.46 seconds
Started Jul 13 06:45:16 PM PDT 24
Finished Jul 13 06:45:19 PM PDT 24
Peak memory 208696 kb
Host smart-4d3c2653-7365-47db-83cc-008828c2d7d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302630925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3302630925
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2276779582
Short name T601
Test name
Test status
Simulation time 640576609 ps
CPU time 4.48 seconds
Started Jul 13 06:45:16 PM PDT 24
Finished Jul 13 06:45:22 PM PDT 24
Peak memory 208516 kb
Host smart-eff7f079-dcd1-45e5-b205-c50eb15589d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276779582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2276779582
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2951378555
Short name T96
Test name
Test status
Simulation time 963456956 ps
CPU time 3.15 seconds
Started Jul 13 06:45:21 PM PDT 24
Finished Jul 13 06:45:26 PM PDT 24
Peak memory 200348 kb
Host smart-044032fb-a8b9-4db1-8811-64e302459dae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951378555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2951378555
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.599303901
Short name T608
Test name
Test status
Simulation time 111989132 ps
CPU time 0.95 seconds
Started Jul 13 06:45:21 PM PDT 24
Finished Jul 13 06:45:24 PM PDT 24
Peak memory 200360 kb
Host smart-f608aec2-208f-4e62-ade9-50ee452e7e3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599303901 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.599303901
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2834176597
Short name T546
Test name
Test status
Simulation time 62785951 ps
CPU time 0.79 seconds
Started Jul 13 06:45:16 PM PDT 24
Finished Jul 13 06:45:18 PM PDT 24
Peak memory 200240 kb
Host smart-58e0bc3c-68eb-437d-b53f-a9e17bd6e102
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834176597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2834176597
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4206408425
Short name T575
Test name
Test status
Simulation time 129865305 ps
CPU time 1.29 seconds
Started Jul 13 06:45:17 PM PDT 24
Finished Jul 13 06:45:19 PM PDT 24
Peak memory 200344 kb
Host smart-e2003bf5-340a-4a5c-9afe-7fc231ac9deb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206408425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.4206408425
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1304358795
Short name T562
Test name
Test status
Simulation time 137609319 ps
CPU time 2.03 seconds
Started Jul 13 06:45:23 PM PDT 24
Finished Jul 13 06:45:26 PM PDT 24
Peak memory 208456 kb
Host smart-cc067619-e501-462c-a42f-3a15a99f1e98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304358795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1304358795
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.331289960
Short name T586
Test name
Test status
Simulation time 771249065 ps
CPU time 2.85 seconds
Started Jul 13 06:45:16 PM PDT 24
Finished Jul 13 06:45:20 PM PDT 24
Peak memory 200372 kb
Host smart-9ed52f88-4708-4766-890b-7cacfb8b5cfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331289960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.331289960
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3429012297
Short name T581
Test name
Test status
Simulation time 204944951 ps
CPU time 1.62 seconds
Started Jul 13 06:45:02 PM PDT 24
Finished Jul 13 06:45:05 PM PDT 24
Peak memory 200324 kb
Host smart-7fb7e1eb-5249-4c50-81ac-4668c5232c18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429012297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
429012297
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2234109610
Short name T569
Test name
Test status
Simulation time 1556418952 ps
CPU time 8.69 seconds
Started Jul 13 06:44:56 PM PDT 24
Finished Jul 13 06:45:05 PM PDT 24
Peak memory 200444 kb
Host smart-71987e3c-8c4b-4c79-b06f-37b735ccf72a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234109610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
234109610
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2215074040
Short name T549
Test name
Test status
Simulation time 94441401 ps
CPU time 0.85 seconds
Started Jul 13 06:45:00 PM PDT 24
Finished Jul 13 06:45:02 PM PDT 24
Peak memory 200244 kb
Host smart-91ee3523-2226-4ddd-b832-d0019ada3951
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215074040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
215074040
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1618990466
Short name T590
Test name
Test status
Simulation time 129865596 ps
CPU time 1.36 seconds
Started Jul 13 06:44:55 PM PDT 24
Finished Jul 13 06:44:57 PM PDT 24
Peak memory 208588 kb
Host smart-76204196-e9bb-40eb-a7a1-b2b4299068f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618990466 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1618990466
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.37855871
Short name T544
Test name
Test status
Simulation time 61690661 ps
CPU time 0.79 seconds
Started Jul 13 06:45:02 PM PDT 24
Finished Jul 13 06:45:04 PM PDT 24
Peak memory 200248 kb
Host smart-adf4be78-f045-4fca-8f07-0ad08ae0b420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37855871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.37855871
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.677001506
Short name T593
Test name
Test status
Simulation time 161607936 ps
CPU time 1.27 seconds
Started Jul 13 06:44:57 PM PDT 24
Finished Jul 13 06:44:59 PM PDT 24
Peak memory 200292 kb
Host smart-ada6a75c-cf47-4d8e-9060-1c45dace70f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677001506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.677001506
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3788299860
Short name T610
Test name
Test status
Simulation time 386236693 ps
CPU time 2.98 seconds
Started Jul 13 06:44:58 PM PDT 24
Finished Jul 13 06:45:02 PM PDT 24
Peak memory 208652 kb
Host smart-3ef1118c-d5f7-4f74-b411-20eb3ccc1cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788299860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3788299860
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3891145828
Short name T121
Test name
Test status
Simulation time 431997191 ps
CPU time 1.93 seconds
Started Jul 13 06:45:06 PM PDT 24
Finished Jul 13 06:45:09 PM PDT 24
Peak memory 200464 kb
Host smart-47368f86-b69d-4927-a380-789dbed1d9dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891145828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3891145828
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2379277298
Short name T605
Test name
Test status
Simulation time 156909333 ps
CPU time 1.99 seconds
Started Jul 13 06:44:58 PM PDT 24
Finished Jul 13 06:45:01 PM PDT 24
Peak memory 200388 kb
Host smart-2a6d7ea3-cf57-4bc0-b839-8977a1a51257
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379277298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
379277298
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4060709495
Short name T566
Test name
Test status
Simulation time 274742580 ps
CPU time 3.42 seconds
Started Jul 13 06:45:00 PM PDT 24
Finished Jul 13 06:45:04 PM PDT 24
Peak memory 200348 kb
Host smart-b664ae40-08b2-4e70-9650-fe555476ff64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060709495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.4
060709495
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3032061542
Short name T552
Test name
Test status
Simulation time 124485400 ps
CPU time 0.89 seconds
Started Jul 13 06:44:56 PM PDT 24
Finished Jul 13 06:44:58 PM PDT 24
Peak memory 200244 kb
Host smart-1e77f4b4-a5e6-4428-9c8c-26cfbcecd35b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032061542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
032061542
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.582524597
Short name T570
Test name
Test status
Simulation time 171541795 ps
CPU time 1.19 seconds
Started Jul 13 06:45:04 PM PDT 24
Finished Jul 13 06:45:06 PM PDT 24
Peak memory 209660 kb
Host smart-024c498b-091f-40e5-b454-2ff7805d23ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582524597 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.582524597
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1294020325
Short name T560
Test name
Test status
Simulation time 71448634 ps
CPU time 0.84 seconds
Started Jul 13 06:44:55 PM PDT 24
Finished Jul 13 06:44:57 PM PDT 24
Peak memory 200236 kb
Host smart-1201fc1f-734f-485b-9780-85cd1dbf0339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294020325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1294020325
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.742785137
Short name T574
Test name
Test status
Simulation time 143283052 ps
CPU time 1.15 seconds
Started Jul 13 06:45:02 PM PDT 24
Finished Jul 13 06:45:04 PM PDT 24
Peak memory 200308 kb
Host smart-987b487e-a396-44a0-b1f8-9cd0687e3b8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742785137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.742785137
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3259981937
Short name T583
Test name
Test status
Simulation time 101582631 ps
CPU time 1.32 seconds
Started Jul 13 06:44:55 PM PDT 24
Finished Jul 13 06:44:58 PM PDT 24
Peak memory 208476 kb
Host smart-db492486-6af7-41eb-aede-65ae16acbcaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259981937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3259981937
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4205149416
Short name T615
Test name
Test status
Simulation time 473825818 ps
CPU time 1.9 seconds
Started Jul 13 06:45:04 PM PDT 24
Finished Jul 13 06:45:07 PM PDT 24
Peak memory 200440 kb
Host smart-220ca1c5-a9be-4876-ac97-f5762ac2d39d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205149416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.4205149416
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3093121426
Short name T543
Test name
Test status
Simulation time 247360277 ps
CPU time 1.73 seconds
Started Jul 13 06:45:08 PM PDT 24
Finished Jul 13 06:45:11 PM PDT 24
Peak memory 200396 kb
Host smart-6cfd0673-93aa-4769-b853-d2dc2e527018
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093121426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
093121426
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3921909184
Short name T600
Test name
Test status
Simulation time 812652962 ps
CPU time 4.87 seconds
Started Jul 13 06:45:09 PM PDT 24
Finished Jul 13 06:45:15 PM PDT 24
Peak memory 200384 kb
Host smart-d60f9874-5837-4764-883e-3bcb85a7367c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921909184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
921909184
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3609941994
Short name T609
Test name
Test status
Simulation time 144565376 ps
CPU time 0.93 seconds
Started Jul 13 06:45:03 PM PDT 24
Finished Jul 13 06:45:05 PM PDT 24
Peak memory 200256 kb
Host smart-39edb122-68d4-47cd-af31-622295e65104
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609941994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
609941994
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3687805278
Short name T553
Test name
Test status
Simulation time 168411818 ps
CPU time 1.15 seconds
Started Jul 13 06:45:03 PM PDT 24
Finished Jul 13 06:45:05 PM PDT 24
Peak memory 208572 kb
Host smart-b63a6f92-22e7-4c6d-8030-7c1b4fc29687
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687805278 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3687805278
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1547662670
Short name T607
Test name
Test status
Simulation time 68239313 ps
CPU time 0.82 seconds
Started Jul 13 06:45:01 PM PDT 24
Finished Jul 13 06:45:03 PM PDT 24
Peak memory 200252 kb
Host smart-bea2dd11-2db5-4c6e-965c-1cbcadbe3f8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547662670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1547662670
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2774182758
Short name T74
Test name
Test status
Simulation time 82487162 ps
CPU time 1.05 seconds
Started Jul 13 06:45:03 PM PDT 24
Finished Jul 13 06:45:05 PM PDT 24
Peak memory 200304 kb
Host smart-b2501608-6e00-441b-9006-49ebf3a4c2ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774182758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2774182758
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4118641690
Short name T595
Test name
Test status
Simulation time 134982326 ps
CPU time 1.9 seconds
Started Jul 13 06:45:04 PM PDT 24
Finished Jul 13 06:45:07 PM PDT 24
Peak memory 216780 kb
Host smart-348ccb68-b7b6-471f-90bb-dd451bd71692
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118641690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.4118641690
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2193949286
Short name T547
Test name
Test status
Simulation time 876080376 ps
CPU time 3.27 seconds
Started Jul 13 06:45:09 PM PDT 24
Finished Jul 13 06:45:13 PM PDT 24
Peak memory 200516 kb
Host smart-5edd4940-d2e0-472b-9b89-1b3ae5a3df71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193949286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2193949286
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.163462375
Short name T587
Test name
Test status
Simulation time 141411727 ps
CPU time 1.11 seconds
Started Jul 13 06:44:58 PM PDT 24
Finished Jul 13 06:45:00 PM PDT 24
Peak memory 200576 kb
Host smart-774c8329-a92b-4b2a-9bd5-5f74f75a17d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163462375 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.163462375
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3474624459
Short name T592
Test name
Test status
Simulation time 67321779 ps
CPU time 0.84 seconds
Started Jul 13 06:45:09 PM PDT 24
Finished Jul 13 06:45:11 PM PDT 24
Peak memory 200236 kb
Host smart-bb39fcac-74e1-410f-ae8e-0de0d19f9f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474624459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3474624459
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2355143251
Short name T591
Test name
Test status
Simulation time 195490785 ps
CPU time 1.63 seconds
Started Jul 13 06:45:05 PM PDT 24
Finished Jul 13 06:45:08 PM PDT 24
Peak memory 200448 kb
Host smart-a1efcefb-3246-4b58-86a1-238933cc200c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355143251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2355143251
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2379802422
Short name T618
Test name
Test status
Simulation time 229243039 ps
CPU time 1.89 seconds
Started Jul 13 06:44:58 PM PDT 24
Finished Jul 13 06:45:01 PM PDT 24
Peak memory 208456 kb
Host smart-ec85575f-8a26-41fc-9d7c-8bd10220df33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379802422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2379802422
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2578223828
Short name T75
Test name
Test status
Simulation time 427487556 ps
CPU time 2.16 seconds
Started Jul 13 06:44:54 PM PDT 24
Finished Jul 13 06:44:58 PM PDT 24
Peak memory 200484 kb
Host smart-5e2ef1f6-0751-49ce-abf7-6b14da26bba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578223828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2578223828
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3349170057
Short name T123
Test name
Test status
Simulation time 127408037 ps
CPU time 1.45 seconds
Started Jul 13 06:44:57 PM PDT 24
Finished Jul 13 06:44:59 PM PDT 24
Peak memory 208748 kb
Host smart-fc6feb3e-6dc1-44a0-95d7-f00d82b8e64b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349170057 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3349170057
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1664713298
Short name T541
Test name
Test status
Simulation time 66695910 ps
CPU time 0.76 seconds
Started Jul 13 06:44:56 PM PDT 24
Finished Jul 13 06:44:58 PM PDT 24
Peak memory 200168 kb
Host smart-fcb9f91b-5f19-4a30-a23f-b991e143b2ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664713298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1664713298
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3846531605
Short name T108
Test name
Test status
Simulation time 101075201 ps
CPU time 1.24 seconds
Started Jul 13 06:44:57 PM PDT 24
Finished Jul 13 06:44:59 PM PDT 24
Peak memory 200344 kb
Host smart-d31231d7-0e9d-45cb-8bb9-b08ac3c570b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846531605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3846531605
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1019868052
Short name T584
Test name
Test status
Simulation time 241533340 ps
CPU time 3.77 seconds
Started Jul 13 06:44:55 PM PDT 24
Finished Jul 13 06:45:00 PM PDT 24
Peak memory 208588 kb
Host smart-05cf5c4a-950b-4b4c-b2e3-4ec3cb46355b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019868052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1019868052
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.242021391
Short name T122
Test name
Test status
Simulation time 918868677 ps
CPU time 3.22 seconds
Started Jul 13 06:45:03 PM PDT 24
Finished Jul 13 06:45:07 PM PDT 24
Peak memory 200552 kb
Host smart-ab987dd4-2069-4af8-bb43-7f10002115aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242021391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
242021391
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3376568354
Short name T578
Test name
Test status
Simulation time 195189207 ps
CPU time 1.23 seconds
Started Jul 13 06:45:04 PM PDT 24
Finished Jul 13 06:45:07 PM PDT 24
Peak memory 208592 kb
Host smart-8587e1fe-c983-4ae5-af19-8c49917a68cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376568354 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3376568354
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4029678251
Short name T602
Test name
Test status
Simulation time 76698382 ps
CPU time 0.86 seconds
Started Jul 13 06:45:02 PM PDT 24
Finished Jul 13 06:45:03 PM PDT 24
Peak memory 200176 kb
Host smart-5d535595-3f1a-4509-b613-cff87def8c58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029678251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.4029678251
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2556478244
Short name T596
Test name
Test status
Simulation time 90231110 ps
CPU time 1 seconds
Started Jul 13 06:44:55 PM PDT 24
Finished Jul 13 06:44:57 PM PDT 24
Peak memory 200248 kb
Host smart-4ab95cc6-dd20-4a6c-9b4a-4077e10c9947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556478244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2556478244
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.745747837
Short name T559
Test name
Test status
Simulation time 384993971 ps
CPU time 2.72 seconds
Started Jul 13 06:45:03 PM PDT 24
Finished Jul 13 06:45:07 PM PDT 24
Peak memory 208860 kb
Host smart-7e27e648-9d43-4ebe-bee5-d34062a42af6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745747837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.745747837
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.848812663
Short name T119
Test name
Test status
Simulation time 922838939 ps
CPU time 3.24 seconds
Started Jul 13 06:44:55 PM PDT 24
Finished Jul 13 06:45:00 PM PDT 24
Peak memory 200472 kb
Host smart-59669719-1219-479e-9c20-ead6a1ae576e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848812663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
848812663
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4124489174
Short name T573
Test name
Test status
Simulation time 182355812 ps
CPU time 1.27 seconds
Started Jul 13 06:45:03 PM PDT 24
Finished Jul 13 06:45:05 PM PDT 24
Peak memory 200372 kb
Host smart-495e10be-8585-48d2-9437-14587b7f347c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124489174 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.4124489174
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.474045301
Short name T611
Test name
Test status
Simulation time 88163679 ps
CPU time 1.02 seconds
Started Jul 13 06:45:01 PM PDT 24
Finished Jul 13 06:45:03 PM PDT 24
Peak memory 200264 kb
Host smart-dd12920d-8cc8-4152-8e2c-9869117769c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474045301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.474045301
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1348952970
Short name T109
Test name
Test status
Simulation time 75524790 ps
CPU time 0.97 seconds
Started Jul 13 06:45:05 PM PDT 24
Finished Jul 13 06:45:07 PM PDT 24
Peak memory 200296 kb
Host smart-de3ff973-7a0d-4843-93a9-4f4f772f6a7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348952970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1348952970
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1868062438
Short name T612
Test name
Test status
Simulation time 212825480 ps
CPU time 1.8 seconds
Started Jul 13 06:45:00 PM PDT 24
Finished Jul 13 06:45:02 PM PDT 24
Peak memory 208652 kb
Host smart-51af5163-601d-4448-86fd-b66df3b8c1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868062438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1868062438
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1864615158
Short name T617
Test name
Test status
Simulation time 538660908 ps
CPU time 2 seconds
Started Jul 13 06:44:56 PM PDT 24
Finished Jul 13 06:44:59 PM PDT 24
Peak memory 200460 kb
Host smart-1d81a1fd-318e-4dbf-bc68-af00afe2db01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864615158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1864615158
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3495253755
Short name T97
Test name
Test status
Simulation time 171236590 ps
CPU time 1.31 seconds
Started Jul 13 06:45:12 PM PDT 24
Finished Jul 13 06:45:14 PM PDT 24
Peak memory 208584 kb
Host smart-3d7862ce-cb79-4bc3-b1c0-ad851d250a5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495253755 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3495253755
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.761770264
Short name T604
Test name
Test status
Simulation time 85284003 ps
CPU time 0.87 seconds
Started Jul 13 06:44:58 PM PDT 24
Finished Jul 13 06:45:00 PM PDT 24
Peak memory 200252 kb
Host smart-3508a08b-86af-442a-902e-f3bcd50977a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761770264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.761770264
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3110851770
Short name T616
Test name
Test status
Simulation time 236247864 ps
CPU time 1.69 seconds
Started Jul 13 06:45:06 PM PDT 24
Finished Jul 13 06:45:09 PM PDT 24
Peak memory 200456 kb
Host smart-ce173324-d168-44c3-b3c6-349e777d13ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110851770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3110851770
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1556123085
Short name T556
Test name
Test status
Simulation time 180540960 ps
CPU time 2.58 seconds
Started Jul 13 06:45:02 PM PDT 24
Finished Jul 13 06:45:05 PM PDT 24
Peak memory 208456 kb
Host smart-d1d1e56a-7ac7-4ea1-b59d-9c818bffd7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556123085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1556123085
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1761762508
Short name T89
Test name
Test status
Simulation time 80033902 ps
CPU time 0.82 seconds
Started Jul 13 06:45:18 PM PDT 24
Finished Jul 13 06:45:20 PM PDT 24
Peak memory 199892 kb
Host smart-8bbc3ee8-2a93-4330-bcb0-bef7f4355046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761762508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1761762508
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1778182227
Short name T132
Test name
Test status
Simulation time 2174305915 ps
CPU time 9.92 seconds
Started Jul 13 06:45:19 PM PDT 24
Finished Jul 13 06:45:30 PM PDT 24
Peak memory 221744 kb
Host smart-49dec044-3541-47d1-bf47-33e98318d6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778182227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1778182227
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.918558174
Short name T442
Test name
Test status
Simulation time 244580255 ps
CPU time 1.09 seconds
Started Jul 13 06:45:20 PM PDT 24
Finished Jul 13 06:45:22 PM PDT 24
Peak memory 217456 kb
Host smart-57c6f66d-2260-4de0-a1d6-675692553590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918558174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.918558174
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.4263342549
Short name T448
Test name
Test status
Simulation time 194532402 ps
CPU time 0.92 seconds
Started Jul 13 06:45:18 PM PDT 24
Finished Jul 13 06:45:20 PM PDT 24
Peak memory 199868 kb
Host smart-64829ef2-5d53-45bc-9fdb-a386753b7155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263342549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4263342549
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.920183784
Short name T93
Test name
Test status
Simulation time 707500301 ps
CPU time 4.08 seconds
Started Jul 13 06:45:19 PM PDT 24
Finished Jul 13 06:45:25 PM PDT 24
Peak memory 200248 kb
Host smart-8e418b97-383e-44ef-9f85-5431840302ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920183784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.920183784
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2104482807
Short name T85
Test name
Test status
Simulation time 8306563171 ps
CPU time 13.42 seconds
Started Jul 13 06:45:21 PM PDT 24
Finished Jul 13 06:45:36 PM PDT 24
Peak memory 217152 kb
Host smart-333e9c87-6db1-4f10-8c77-426e26c7dd5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104482807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2104482807
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3602400146
Short name T532
Test name
Test status
Simulation time 182661558 ps
CPU time 1.25 seconds
Started Jul 13 06:45:17 PM PDT 24
Finished Jul 13 06:45:20 PM PDT 24
Peak memory 200096 kb
Host smart-ca0f7d9a-3a77-4e15-b329-dcbef43ccdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602400146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3602400146
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.250489129
Short name T226
Test name
Test status
Simulation time 118939913 ps
CPU time 1.3 seconds
Started Jul 13 06:45:20 PM PDT 24
Finished Jul 13 06:45:23 PM PDT 24
Peak memory 200232 kb
Host smart-7efb58ba-9f52-4a76-b800-e4f0871cbbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250489129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.250489129
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2368730707
Short name T342
Test name
Test status
Simulation time 4704229623 ps
CPU time 16.42 seconds
Started Jul 13 06:45:20 PM PDT 24
Finished Jul 13 06:45:38 PM PDT 24
Peak memory 200424 kb
Host smart-273fa88a-dbf8-41b9-8966-15aecab51b9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368730707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2368730707
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.655840353
Short name T217
Test name
Test status
Simulation time 130564237 ps
CPU time 1.6 seconds
Started Jul 13 06:45:19 PM PDT 24
Finished Jul 13 06:45:22 PM PDT 24
Peak memory 200128 kb
Host smart-38e50bcf-e4ab-4288-bade-d7557613b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655840353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.655840353
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.478592273
Short name T513
Test name
Test status
Simulation time 69068371 ps
CPU time 0.79 seconds
Started Jul 13 06:45:22 PM PDT 24
Finished Jul 13 06:45:24 PM PDT 24
Peak memory 200096 kb
Host smart-193c137d-f5db-4da2-b106-e12b8b867261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478592273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.478592273
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.534551493
Short name T484
Test name
Test status
Simulation time 80582938 ps
CPU time 0.84 seconds
Started Jul 13 06:45:21 PM PDT 24
Finished Jul 13 06:45:23 PM PDT 24
Peak memory 199884 kb
Host smart-d586bd24-0f01-447f-be4b-21b5bc5ce00a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534551493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.534551493
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.4289956868
Short name T387
Test name
Test status
Simulation time 1223913435 ps
CPU time 6.44 seconds
Started Jul 13 06:45:17 PM PDT 24
Finished Jul 13 06:45:25 PM PDT 24
Peak memory 216676 kb
Host smart-c1a073f4-f7e2-46a6-82c4-0bd911a6ade5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289956868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.4289956868
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.4018346655
Short name T231
Test name
Test status
Simulation time 244655394 ps
CPU time 1.08 seconds
Started Jul 13 06:45:20 PM PDT 24
Finished Jul 13 06:45:22 PM PDT 24
Peak memory 217380 kb
Host smart-042fe065-6744-4adc-8c99-bd09dcd677bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018346655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.4018346655
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.4072000448
Short name T196
Test name
Test status
Simulation time 193699157 ps
CPU time 0.9 seconds
Started Jul 13 06:45:20 PM PDT 24
Finished Jul 13 06:45:22 PM PDT 24
Peak memory 199880 kb
Host smart-5da8ee42-23a1-406a-9061-7f6406ee0456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072000448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.4072000448
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2890318040
Short name T193
Test name
Test status
Simulation time 1036461211 ps
CPU time 5.88 seconds
Started Jul 13 06:45:18 PM PDT 24
Finished Jul 13 06:45:25 PM PDT 24
Peak memory 200656 kb
Host smart-a5c9d55d-521c-4df9-b5f4-95266bb41f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890318040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2890318040
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3201693014
Short name T82
Test name
Test status
Simulation time 8383588515 ps
CPU time 13.04 seconds
Started Jul 13 06:45:18 PM PDT 24
Finished Jul 13 06:45:32 PM PDT 24
Peak memory 217116 kb
Host smart-a73deda2-2c39-4817-9939-24f2ac86d662
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201693014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3201693014
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1488525510
Short name T363
Test name
Test status
Simulation time 99945614 ps
CPU time 1.05 seconds
Started Jul 13 06:45:21 PM PDT 24
Finished Jul 13 06:45:23 PM PDT 24
Peak memory 200132 kb
Host smart-b86f967f-abd8-4c30-bff2-aacd7e4adc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488525510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1488525510
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.446493943
Short name T452
Test name
Test status
Simulation time 116038951 ps
CPU time 1.31 seconds
Started Jul 13 06:45:19 PM PDT 24
Finished Jul 13 06:45:21 PM PDT 24
Peak memory 200312 kb
Host smart-29269d1f-e86d-4352-9fa3-377f8b9645bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446493943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.446493943
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1364088774
Short name T493
Test name
Test status
Simulation time 4662777973 ps
CPU time 20.47 seconds
Started Jul 13 06:45:16 PM PDT 24
Finished Jul 13 06:45:37 PM PDT 24
Peak memory 200440 kb
Host smart-a16ac779-b8e9-4019-91a4-c8ec191b7888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364088774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1364088774
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.337733415
Short name T131
Test name
Test status
Simulation time 333530755 ps
CPU time 2.09 seconds
Started Jul 13 06:45:21 PM PDT 24
Finished Jul 13 06:45:25 PM PDT 24
Peak memory 200020 kb
Host smart-beae1339-3c60-41e2-87c3-b5972dec41d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337733415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.337733415
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2213012688
Short name T534
Test name
Test status
Simulation time 255491770 ps
CPU time 1.42 seconds
Started Jul 13 06:45:19 PM PDT 24
Finished Jul 13 06:45:22 PM PDT 24
Peak memory 200024 kb
Host smart-0e5bbbe4-350f-49e1-ae40-cdb5d9b1b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213012688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2213012688
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3505596050
Short name T366
Test name
Test status
Simulation time 68453768 ps
CPU time 0.81 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:37 PM PDT 24
Peak memory 199892 kb
Host smart-8960ca30-35a0-41f9-9a7e-245363e3b801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505596050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3505596050
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3535505923
Short name T61
Test name
Test status
Simulation time 1879957790 ps
CPU time 7.16 seconds
Started Jul 13 06:45:40 PM PDT 24
Finished Jul 13 06:45:49 PM PDT 24
Peak memory 217444 kb
Host smart-0d61e987-d607-41ec-8a91-cd86d7dc0293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535505923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3535505923
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3240477359
Short name T277
Test name
Test status
Simulation time 243944522 ps
CPU time 1.16 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:38 PM PDT 24
Peak memory 217488 kb
Host smart-d1265e6f-2971-496c-bd96-6f27faab19ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240477359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3240477359
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1454929734
Short name T220
Test name
Test status
Simulation time 93987831 ps
CPU time 0.76 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:40 PM PDT 24
Peak memory 199920 kb
Host smart-1c8c2ec6-012f-40ef-bf8d-049e3ba91448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454929734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1454929734
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1243072140
Short name T170
Test name
Test status
Simulation time 1085505148 ps
CPU time 5.31 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:45 PM PDT 24
Peak memory 200280 kb
Host smart-c2cb8d65-dbaf-4b77-b699-6eca5f5833c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243072140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1243072140
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1706369054
Short name T429
Test name
Test status
Simulation time 143439843 ps
CPU time 1.15 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:42 PM PDT 24
Peak memory 199412 kb
Host smart-43a21c02-b487-4de9-82eb-1aa97fd13227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706369054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1706369054
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2956668995
Short name T408
Test name
Test status
Simulation time 113362077 ps
CPU time 1.19 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:45:39 PM PDT 24
Peak memory 200284 kb
Host smart-faee81db-9b88-471a-88d1-831658f1e6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956668995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2956668995
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3874167006
Short name T481
Test name
Test status
Simulation time 1520629553 ps
CPU time 6.36 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:45:44 PM PDT 24
Peak memory 200424 kb
Host smart-6f7d2784-b761-4ad4-94ee-b3192ebefa0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874167006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3874167006
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3489438647
Short name T284
Test name
Test status
Simulation time 118192474 ps
CPU time 1.5 seconds
Started Jul 13 06:45:39 PM PDT 24
Finished Jul 13 06:45:43 PM PDT 24
Peak memory 200044 kb
Host smart-ef2c7a06-c840-4712-bab8-d2e6c23efd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489438647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3489438647
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1426670641
Short name T369
Test name
Test status
Simulation time 94325761 ps
CPU time 0.95 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:42 PM PDT 24
Peak memory 200092 kb
Host smart-e622e832-1aeb-4ebd-af80-9c8dd42aa035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426670641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1426670641
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.291695260
Short name T189
Test name
Test status
Simulation time 68993765 ps
CPU time 0.83 seconds
Started Jul 13 06:45:41 PM PDT 24
Finished Jul 13 06:45:43 PM PDT 24
Peak memory 199896 kb
Host smart-7db30f23-0b85-4eae-b657-d654cec9629b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291695260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.291695260
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2314304112
Short name T519
Test name
Test status
Simulation time 2349380386 ps
CPU time 8.84 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:49 PM PDT 24
Peak memory 217792 kb
Host smart-59214c13-89d3-40a1-8c9b-2da99c62c5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314304112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2314304112
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3117352483
Short name T265
Test name
Test status
Simulation time 244619603 ps
CPU time 1.11 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:45:40 PM PDT 24
Peak memory 217496 kb
Host smart-9cececc8-dd9a-4019-b207-c57e84523593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117352483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3117352483
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.645005161
Short name T315
Test name
Test status
Simulation time 89996077 ps
CPU time 0.79 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:42 PM PDT 24
Peak memory 199952 kb
Host smart-61a8221e-73bf-46bf-a7ec-6251867c0312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645005161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.645005161
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3830202017
Short name T441
Test name
Test status
Simulation time 1486410036 ps
CPU time 6.73 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:48 PM PDT 24
Peak memory 199736 kb
Host smart-5bbd50e9-f8e9-458c-9a86-d447af635a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830202017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3830202017
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1271611456
Short name T30
Test name
Test status
Simulation time 189368935 ps
CPU time 1.46 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 200316 kb
Host smart-4e505674-bbc2-4a4c-b672-798fbe00a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271611456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1271611456
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3024582688
Short name T198
Test name
Test status
Simulation time 6569205024 ps
CPU time 23.8 seconds
Started Jul 13 06:45:43 PM PDT 24
Finished Jul 13 06:46:08 PM PDT 24
Peak memory 208632 kb
Host smart-56c8953d-8a23-4630-8f52-706e52d1670a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024582688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3024582688
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3444807691
Short name T229
Test name
Test status
Simulation time 280900682 ps
CPU time 1.9 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:38 PM PDT 24
Peak memory 200092 kb
Host smart-c42afec5-aaef-4344-a414-9e8d83201aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444807691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3444807691
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3035320742
Short name T155
Test name
Test status
Simulation time 187416991 ps
CPU time 1.26 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:45:40 PM PDT 24
Peak memory 200088 kb
Host smart-7c2454fc-ce1f-4135-8f46-1bef0f73b439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035320742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3035320742
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3461273724
Short name T141
Test name
Test status
Simulation time 83202128 ps
CPU time 0.88 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:37 PM PDT 24
Peak memory 199892 kb
Host smart-07f9c9f8-e33a-400f-85a2-3d9f91fe4aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461273724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3461273724
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1846157955
Short name T310
Test name
Test status
Simulation time 1232671550 ps
CPU time 5.26 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 221640 kb
Host smart-2b8136df-456a-48d3-9091-51de3f3d9b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846157955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1846157955
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.4254938461
Short name T503
Test name
Test status
Simulation time 243413386 ps
CPU time 1.11 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:45:39 PM PDT 24
Peak memory 217468 kb
Host smart-037b908c-1675-4aa1-95de-f47523ffe2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254938461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.4254938461
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3134050744
Short name T473
Test name
Test status
Simulation time 158784580 ps
CPU time 0.82 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 200132 kb
Host smart-34f2869f-e9bf-441e-8504-bb097b731bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134050744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3134050744
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3920096888
Short name T502
Test name
Test status
Simulation time 770446111 ps
CPU time 4.04 seconds
Started Jul 13 06:45:34 PM PDT 24
Finished Jul 13 06:45:39 PM PDT 24
Peak memory 200364 kb
Host smart-73fc6fbf-eb63-4a82-8ce4-cfeeeb7d3148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920096888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3920096888
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2702805014
Short name T376
Test name
Test status
Simulation time 150742329 ps
CPU time 1.16 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:42 PM PDT 24
Peak memory 200140 kb
Host smart-4edc0f48-b9fe-46b7-98f4-a3322ed161d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702805014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2702805014
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1340423828
Short name T259
Test name
Test status
Simulation time 124861677 ps
CPU time 1.24 seconds
Started Jul 13 06:45:40 PM PDT 24
Finished Jul 13 06:45:43 PM PDT 24
Peak memory 200256 kb
Host smart-3704bbe9-f5ae-4663-88e7-4904ee3b21ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340423828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1340423828
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.464483017
Short name T511
Test name
Test status
Simulation time 1253255148 ps
CPU time 6.31 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:47 PM PDT 24
Peak memory 200252 kb
Host smart-c84406ec-3ca0-4b61-9a1a-7d3128f8a710
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464483017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.464483017
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1999144206
Short name T472
Test name
Test status
Simulation time 296155545 ps
CPU time 1.94 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:39 PM PDT 24
Peak memory 208252 kb
Host smart-d2683848-bca0-483d-89da-ab3d6facbd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999144206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1999144206
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1435340898
Short name T165
Test name
Test status
Simulation time 65118424 ps
CPU time 0.81 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 200004 kb
Host smart-c474c63a-2bf6-4db2-8b12-2033a050171b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435340898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1435340898
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.4157764908
Short name T375
Test name
Test status
Simulation time 68730419 ps
CPU time 0.79 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:37 PM PDT 24
Peak memory 199888 kb
Host smart-307142f4-caa8-47ef-a921-94a4aeb695d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157764908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.4157764908
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1560701892
Short name T425
Test name
Test status
Simulation time 244207330 ps
CPU time 1.2 seconds
Started Jul 13 06:45:41 PM PDT 24
Finished Jul 13 06:45:44 PM PDT 24
Peak memory 217384 kb
Host smart-4ff4fa7a-ff97-4789-a038-c0d7ec326be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560701892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1560701892
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2356236887
Short name T434
Test name
Test status
Simulation time 189329556 ps
CPU time 0.93 seconds
Started Jul 13 06:45:44 PM PDT 24
Finished Jul 13 06:45:45 PM PDT 24
Peak memory 199912 kb
Host smart-fa0eadb2-2189-47a1-baa1-129f8143ad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356236887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2356236887
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3086096831
Short name T322
Test name
Test status
Simulation time 1257874111 ps
CPU time 5.71 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:47 PM PDT 24
Peak memory 200348 kb
Host smart-1ca39700-46c2-4b3d-8add-b030dff5a880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086096831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3086096831
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1732383450
Short name T208
Test name
Test status
Simulation time 100832548 ps
CPU time 0.98 seconds
Started Jul 13 06:45:42 PM PDT 24
Finished Jul 13 06:45:44 PM PDT 24
Peak memory 200092 kb
Host smart-c13f39b4-5569-47af-8f90-9a755968684c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732383450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1732383450
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.188747876
Short name T91
Test name
Test status
Simulation time 112403841 ps
CPU time 1.21 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:42 PM PDT 24
Peak memory 200156 kb
Host smart-0124a9fb-e746-486b-be6a-7294ad0c6fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188747876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.188747876
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3376101414
Short name T267
Test name
Test status
Simulation time 4696367058 ps
CPU time 17.32 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:45:56 PM PDT 24
Peak memory 200424 kb
Host smart-fcb4f8f6-7755-4289-9f6f-04e21e44b67d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376101414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3376101414
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.969130907
Short name T168
Test name
Test status
Simulation time 344325207 ps
CPU time 2.38 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 200132 kb
Host smart-a8217a16-85d5-4764-944c-42e62e2a7612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969130907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.969130907
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1680346106
Short name T253
Test name
Test status
Simulation time 67444929 ps
CPU time 0.77 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:42 PM PDT 24
Peak memory 200092 kb
Host smart-223d7140-ba3a-4c68-b6aa-9d07846620d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680346106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1680346106
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3174211356
Short name T348
Test name
Test status
Simulation time 67079901 ps
CPU time 0.79 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:38 PM PDT 24
Peak memory 199892 kb
Host smart-91c12f20-ea96-4686-9978-f7099f7ae182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174211356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3174211356
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2428665193
Short name T63
Test name
Test status
Simulation time 2363267132 ps
CPU time 8.93 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:49 PM PDT 24
Peak memory 217724 kb
Host smart-41dc1796-44ec-4526-8fbb-69b34102ad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428665193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2428665193
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2600306378
Short name T264
Test name
Test status
Simulation time 244949303 ps
CPU time 1.08 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:45:40 PM PDT 24
Peak memory 217460 kb
Host smart-ad6a8401-de27-49da-bc1e-ee57c388fae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600306378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2600306378
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.371201159
Short name T295
Test name
Test status
Simulation time 87610739 ps
CPU time 0.83 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:45:39 PM PDT 24
Peak memory 199916 kb
Host smart-c4fcfdd8-6bc7-4c6f-a821-808a45ea500d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371201159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.371201159
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3119406557
Short name T281
Test name
Test status
Simulation time 1732452918 ps
CPU time 6.61 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:44 PM PDT 24
Peak memory 200412 kb
Host smart-cf5bb895-4865-4918-94af-d3ebe1beff18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119406557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3119406557
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1948378813
Short name T404
Test name
Test status
Simulation time 149950332 ps
CPU time 1.17 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:45:39 PM PDT 24
Peak memory 200116 kb
Host smart-ee954023-dd28-4f80-95c8-db344b385bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948378813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1948378813
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3729819145
Short name T76
Test name
Test status
Simulation time 192613098 ps
CPU time 1.36 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:38 PM PDT 24
Peak memory 200252 kb
Host smart-6f81e31a-f4cf-41e9-afe7-5329c006940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729819145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3729819145
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2395253161
Short name T282
Test name
Test status
Simulation time 10984787783 ps
CPU time 39.61 seconds
Started Jul 13 06:45:40 PM PDT 24
Finished Jul 13 06:46:22 PM PDT 24
Peak memory 200428 kb
Host smart-26d28363-a605-472d-9b33-bcc060edf3ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395253161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2395253161
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2921358596
Short name T537
Test name
Test status
Simulation time 288956797 ps
CPU time 2.15 seconds
Started Jul 13 06:45:40 PM PDT 24
Finished Jul 13 06:45:44 PM PDT 24
Peak memory 200088 kb
Host smart-798e84d4-4e11-464b-af0c-6820f30e2717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921358596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2921358596
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.4265758092
Short name T396
Test name
Test status
Simulation time 280110829 ps
CPU time 1.68 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 200332 kb
Host smart-1571f437-8c9e-443e-9a05-eb7de147c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265758092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.4265758092
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3661528385
Short name T435
Test name
Test status
Simulation time 212485297 ps
CPU time 1.09 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 199744 kb
Host smart-95d2cf91-67ee-401f-862f-cdb1a66f2ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661528385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3661528385
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3298579382
Short name T39
Test name
Test status
Simulation time 1897009268 ps
CPU time 7.21 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:46 PM PDT 24
Peak memory 221636 kb
Host smart-c3bac6bc-ad19-4e9b-834d-5ab16ff45e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298579382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3298579382
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2964927707
Short name T31
Test name
Test status
Simulation time 243830751 ps
CPU time 1.13 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 217392 kb
Host smart-ffa94b53-47b2-4ece-bcc3-9c7af4202ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964927707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2964927707
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3289994032
Short name T180
Test name
Test status
Simulation time 87647086 ps
CPU time 0.79 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:40 PM PDT 24
Peak memory 199920 kb
Host smart-fea23fad-f4d7-47a5-a7d3-b36aa1948b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289994032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3289994032
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3610517338
Short name T45
Test name
Test status
Simulation time 1053784464 ps
CPU time 5.31 seconds
Started Jul 13 06:45:39 PM PDT 24
Finished Jul 13 06:45:47 PM PDT 24
Peak memory 200384 kb
Host smart-547c76cf-a48a-4dc1-905c-0b67b44878d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610517338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3610517338
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1742024174
Short name T468
Test name
Test status
Simulation time 143820226 ps
CPU time 1.09 seconds
Started Jul 13 06:45:39 PM PDT 24
Finished Jul 13 06:45:43 PM PDT 24
Peak memory 200092 kb
Host smart-34350789-a4af-4831-b78c-dfad4ed93c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742024174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1742024174
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.808668709
Short name T365
Test name
Test status
Simulation time 256654344 ps
CPU time 1.55 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:43 PM PDT 24
Peak memory 200324 kb
Host smart-ab375ca0-4262-418a-9313-11219a08e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808668709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.808668709
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.997031443
Short name T286
Test name
Test status
Simulation time 7116164116 ps
CPU time 31.63 seconds
Started Jul 13 06:45:43 PM PDT 24
Finished Jul 13 06:46:16 PM PDT 24
Peak memory 208652 kb
Host smart-1abc2966-e55a-4dab-8442-09ed1ac23ce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997031443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.997031443
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.276700019
Short name T250
Test name
Test status
Simulation time 393653584 ps
CPU time 2.68 seconds
Started Jul 13 06:45:39 PM PDT 24
Finished Jul 13 06:45:45 PM PDT 24
Peak memory 200044 kb
Host smart-b0f6b938-dc9c-4051-bed9-cca3d0bf2008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276700019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.276700019
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3534879136
Short name T178
Test name
Test status
Simulation time 133732524 ps
CPU time 1.19 seconds
Started Jul 13 06:45:38 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 200120 kb
Host smart-495f2dfb-a788-47a2-aaab-9016624cbabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534879136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3534879136
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1691528571
Short name T48
Test name
Test status
Simulation time 96280216 ps
CPU time 0.86 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:50 PM PDT 24
Peak memory 199892 kb
Host smart-9f19beec-9abf-413b-8629-1f8ddeca3549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691528571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1691528571
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2620005654
Short name T388
Test name
Test status
Simulation time 1226579576 ps
CPU time 5.55 seconds
Started Jul 13 06:45:49 PM PDT 24
Finished Jul 13 06:45:56 PM PDT 24
Peak memory 221696 kb
Host smart-3cab51d0-06b5-47ad-8a45-e25cd5ce73b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620005654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2620005654
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3090163800
Short name T405
Test name
Test status
Simulation time 244444606 ps
CPU time 1.08 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:50 PM PDT 24
Peak memory 217404 kb
Host smart-70051746-b181-4a6e-881f-84a12c87b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090163800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3090163800
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.4229065830
Short name T437
Test name
Test status
Simulation time 85234364 ps
CPU time 0.79 seconds
Started Jul 13 06:45:43 PM PDT 24
Finished Jul 13 06:45:45 PM PDT 24
Peak memory 199904 kb
Host smart-b3d5dd46-37e3-4e90-b22f-971dcd40f9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229065830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.4229065830
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2106956445
Short name T160
Test name
Test status
Simulation time 662780696 ps
CPU time 3.86 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:44 PM PDT 24
Peak memory 200200 kb
Host smart-b31df60f-6eb4-4e66-a74f-dea9aaac77d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106956445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2106956445
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3840057113
Short name T43
Test name
Test status
Simulation time 152982511 ps
CPU time 1.12 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 199948 kb
Host smart-ac6a261b-8275-4cc2-bd8f-ed96e46f3235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840057113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3840057113
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2287382183
Short name T236
Test name
Test status
Simulation time 249033457 ps
CPU time 1.5 seconds
Started Jul 13 06:45:39 PM PDT 24
Finished Jul 13 06:45:43 PM PDT 24
Peak memory 200284 kb
Host smart-dfd090c3-4652-4a7f-99e5-2fb8624a0d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287382183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2287382183
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.451390442
Short name T447
Test name
Test status
Simulation time 4369823764 ps
CPU time 16.23 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:46:04 PM PDT 24
Peak memory 208680 kb
Host smart-2bf835e1-0445-4d12-8f6c-4995c93a0be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451390442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.451390442
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2908546292
Short name T157
Test name
Test status
Simulation time 150581399 ps
CPU time 1.89 seconds
Started Jul 13 06:45:40 PM PDT 24
Finished Jul 13 06:45:44 PM PDT 24
Peak memory 200040 kb
Host smart-f4b9ff7b-4e47-4ff0-8e65-a2e4f5e4efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908546292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2908546292
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2297066064
Short name T252
Test name
Test status
Simulation time 108033204 ps
CPU time 0.95 seconds
Started Jul 13 06:45:39 PM PDT 24
Finished Jul 13 06:45:42 PM PDT 24
Peak memory 200100 kb
Host smart-bafcb860-d9c3-4ddd-a53e-6c34dbd9effe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297066064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2297066064
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3047035747
Short name T372
Test name
Test status
Simulation time 88568099 ps
CPU time 0.84 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:49 PM PDT 24
Peak memory 199892 kb
Host smart-722d748a-b7a9-4f7b-8f87-6925d32371ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047035747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3047035747
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.4202688238
Short name T431
Test name
Test status
Simulation time 2377267110 ps
CPU time 8.52 seconds
Started Jul 13 06:45:53 PM PDT 24
Finished Jul 13 06:46:03 PM PDT 24
Peak memory 217772 kb
Host smart-210de704-fdb2-4d84-98bc-bd9dcc9df6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202688238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.4202688238
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1294352616
Short name T516
Test name
Test status
Simulation time 245069780 ps
CPU time 1.14 seconds
Started Jul 13 06:45:49 PM PDT 24
Finished Jul 13 06:45:52 PM PDT 24
Peak memory 217400 kb
Host smart-90d75072-00d3-4f61-8afc-394937596323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294352616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1294352616
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2550117378
Short name T211
Test name
Test status
Simulation time 88860848 ps
CPU time 0.79 seconds
Started Jul 13 06:45:51 PM PDT 24
Finished Jul 13 06:45:53 PM PDT 24
Peak memory 199900 kb
Host smart-d7a04f24-7bff-4072-98c0-2211284fc159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550117378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2550117378
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2867203475
Short name T102
Test name
Test status
Simulation time 923540073 ps
CPU time 4.91 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:45:53 PM PDT 24
Peak memory 200420 kb
Host smart-49033459-4ff3-4b33-8c33-1a5b2b2e7a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867203475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2867203475
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3324271786
Short name T92
Test name
Test status
Simulation time 100116033 ps
CPU time 1.08 seconds
Started Jul 13 06:45:44 PM PDT 24
Finished Jul 13 06:45:46 PM PDT 24
Peak memory 200048 kb
Host smart-868e231d-ee32-4815-984d-954a6bd00688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324271786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3324271786
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2198905714
Short name T487
Test name
Test status
Simulation time 253734950 ps
CPU time 1.57 seconds
Started Jul 13 06:45:45 PM PDT 24
Finished Jul 13 06:45:48 PM PDT 24
Peak memory 200340 kb
Host smart-fdffa956-d3ca-49d6-9533-f87d24b9edc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198905714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2198905714
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1949597436
Short name T163
Test name
Test status
Simulation time 7838095442 ps
CPU time 31.38 seconds
Started Jul 13 06:45:53 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 210676 kb
Host smart-87b66d57-e0fc-4cab-b72b-a00f42a40da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949597436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1949597436
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.334150347
Short name T498
Test name
Test status
Simulation time 539960034 ps
CPU time 2.84 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:52 PM PDT 24
Peak memory 200104 kb
Host smart-e1752bc3-19d3-4017-b2ee-5f5a8a631e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334150347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.334150347
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.358264054
Short name T173
Test name
Test status
Simulation time 114110580 ps
CPU time 1.05 seconds
Started Jul 13 06:45:54 PM PDT 24
Finished Jul 13 06:45:55 PM PDT 24
Peak memory 200068 kb
Host smart-3c87b6e3-1f94-4073-a5f1-64e951697527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358264054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.358264054
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3921294824
Short name T374
Test name
Test status
Simulation time 80450034 ps
CPU time 0.8 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:49 PM PDT 24
Peak memory 199856 kb
Host smart-9cc20917-572d-4902-8b5b-eccae12bd770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921294824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3921294824
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1789782944
Short name T470
Test name
Test status
Simulation time 1220751979 ps
CPU time 5.81 seconds
Started Jul 13 06:45:49 PM PDT 24
Finished Jul 13 06:45:57 PM PDT 24
Peak memory 217712 kb
Host smart-b004142b-cad7-4ddd-b4c8-c7ee5d55c14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789782944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1789782944
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3970587773
Short name T167
Test name
Test status
Simulation time 243495905 ps
CPU time 1.25 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:51 PM PDT 24
Peak memory 217468 kb
Host smart-24b5be04-c710-4450-8127-503b41c7eda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970587773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3970587773
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_reset.922094346
Short name T124
Test name
Test status
Simulation time 1723461966 ps
CPU time 7.37 seconds
Started Jul 13 06:45:45 PM PDT 24
Finished Jul 13 06:45:54 PM PDT 24
Peak memory 200392 kb
Host smart-03ebbd23-db9b-4f9a-8eda-b17f0bb6f2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922094346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.922094346
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2948272024
Short name T2
Test name
Test status
Simulation time 180996708 ps
CPU time 1.2 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:45:48 PM PDT 24
Peak memory 200116 kb
Host smart-e47f1294-f80d-412a-bdbb-614c6eb1d4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948272024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2948272024
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1286112939
Short name T358
Test name
Test status
Simulation time 261165890 ps
CPU time 1.52 seconds
Started Jul 13 06:45:45 PM PDT 24
Finished Jul 13 06:45:48 PM PDT 24
Peak memory 200236 kb
Host smart-abd5e1a0-f7bb-4cd6-afae-114bbe61b197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286112939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1286112939
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3460908463
Short name T508
Test name
Test status
Simulation time 5689164908 ps
CPU time 26.52 seconds
Started Jul 13 06:45:48 PM PDT 24
Finished Jul 13 06:46:16 PM PDT 24
Peak memory 200440 kb
Host smart-d7ec239b-fe15-4944-b0fe-908400dba3e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460908463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3460908463
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.442729712
Short name T4
Test name
Test status
Simulation time 381168275 ps
CPU time 2.11 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:45:49 PM PDT 24
Peak memory 200120 kb
Host smart-ee4dd2e8-d43c-4a32-ad19-dd23844383c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442729712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.442729712
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.30614875
Short name T270
Test name
Test status
Simulation time 95022428 ps
CPU time 0.94 seconds
Started Jul 13 06:45:52 PM PDT 24
Finished Jul 13 06:45:53 PM PDT 24
Peak memory 200100 kb
Host smart-032192dd-a19b-48cf-8ec6-c8a089a91fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30614875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.30614875
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.854627315
Short name T355
Test name
Test status
Simulation time 62074179 ps
CPU time 0.8 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:50 PM PDT 24
Peak memory 199912 kb
Host smart-9abc26ec-013c-460a-a46e-0d491ca0a054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854627315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.854627315
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.652658196
Short name T399
Test name
Test status
Simulation time 1895785997 ps
CPU time 6.88 seconds
Started Jul 13 06:45:51 PM PDT 24
Finished Jul 13 06:45:59 PM PDT 24
Peak memory 217488 kb
Host smart-59cbaa90-3fa7-4055-838e-92559211bc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652658196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.652658196
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2453025506
Short name T260
Test name
Test status
Simulation time 244328444 ps
CPU time 1.11 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:45:49 PM PDT 24
Peak memory 217748 kb
Host smart-67079ea6-176d-4fb0-8dc4-6ce829d05b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453025506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2453025506
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2574178121
Short name T364
Test name
Test status
Simulation time 107401467 ps
CPU time 0.83 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:50 PM PDT 24
Peak memory 199900 kb
Host smart-00201fa3-69e1-4538-8dbd-b043aaeb63ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574178121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2574178121
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.558017262
Short name T223
Test name
Test status
Simulation time 922919907 ps
CPU time 4.82 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:45:52 PM PDT 24
Peak memory 200372 kb
Host smart-29ddac21-dfb0-498a-9e70-29c0b3117e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558017262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.558017262
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1996594076
Short name T444
Test name
Test status
Simulation time 172620467 ps
CPU time 1.19 seconds
Started Jul 13 06:45:44 PM PDT 24
Finished Jul 13 06:45:46 PM PDT 24
Peak memory 200112 kb
Host smart-bb0f4609-8fa0-4a16-afd9-a11b85e34a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996594076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1996594076
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2645551163
Short name T367
Test name
Test status
Simulation time 196617205 ps
CPU time 1.64 seconds
Started Jul 13 06:45:48 PM PDT 24
Finished Jul 13 06:45:52 PM PDT 24
Peak memory 200276 kb
Host smart-e499e353-0085-4f9e-9ddc-eb77f05654ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645551163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2645551163
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2348708882
Short name T340
Test name
Test status
Simulation time 135529187 ps
CPU time 1.65 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:45:48 PM PDT 24
Peak memory 208332 kb
Host smart-fc007684-6d54-4886-ab82-baf4c7d7470f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348708882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2348708882
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1546210496
Short name T263
Test name
Test status
Simulation time 103278822 ps
CPU time 0.92 seconds
Started Jul 13 06:45:52 PM PDT 24
Finished Jul 13 06:45:54 PM PDT 24
Peak memory 200124 kb
Host smart-bd01d126-dc9f-4c55-af69-c87860f0a819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546210496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1546210496
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.651343160
Short name T266
Test name
Test status
Simulation time 82324120 ps
CPU time 0.8 seconds
Started Jul 13 06:45:18 PM PDT 24
Finished Jul 13 06:45:20 PM PDT 24
Peak memory 199876 kb
Host smart-2eb27f7c-6777-4c3a-9286-1cc0f01b0240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651343160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.651343160
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.903656740
Short name T37
Test name
Test status
Simulation time 1237999188 ps
CPU time 5.7 seconds
Started Jul 13 06:45:17 PM PDT 24
Finished Jul 13 06:45:24 PM PDT 24
Peak memory 217664 kb
Host smart-c91feaea-a254-4d9e-89ed-9a28f823af9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903656740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.903656740
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1371007316
Short name T213
Test name
Test status
Simulation time 244666889 ps
CPU time 1.07 seconds
Started Jul 13 06:45:23 PM PDT 24
Finished Jul 13 06:45:26 PM PDT 24
Peak memory 217468 kb
Host smart-4c6cf248-8b6f-4afe-8ee7-0dbd884adaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371007316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1371007316
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3052624961
Short name T302
Test name
Test status
Simulation time 154702912 ps
CPU time 0.92 seconds
Started Jul 13 06:45:21 PM PDT 24
Finished Jul 13 06:45:23 PM PDT 24
Peak memory 199908 kb
Host smart-d5b9b246-aeea-45ca-83a8-c8adc51315dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052624961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3052624961
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1477728952
Short name T521
Test name
Test status
Simulation time 1424996222 ps
CPU time 6.07 seconds
Started Jul 13 06:45:17 PM PDT 24
Finished Jul 13 06:45:25 PM PDT 24
Peak memory 200376 kb
Host smart-9806a4d7-8d4f-41fe-9734-87faa6cf69ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477728952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1477728952
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1176557550
Short name T271
Test name
Test status
Simulation time 189282151 ps
CPU time 1.34 seconds
Started Jul 13 06:45:21 PM PDT 24
Finished Jul 13 06:45:23 PM PDT 24
Peak memory 200144 kb
Host smart-ccbc6f64-097f-4ebe-bf99-828923ca8300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176557550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1176557550
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1936389089
Short name T169
Test name
Test status
Simulation time 119742491 ps
CPU time 1.16 seconds
Started Jul 13 06:45:14 PM PDT 24
Finished Jul 13 06:45:16 PM PDT 24
Peak memory 200316 kb
Host smart-a234fd9d-3851-42fb-aca6-3e461954fe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936389089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1936389089
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2005694008
Short name T161
Test name
Test status
Simulation time 11173629714 ps
CPU time 40.14 seconds
Started Jul 13 06:45:21 PM PDT 24
Finished Jul 13 06:46:03 PM PDT 24
Peak memory 208652 kb
Host smart-e7b3d7f9-ed42-452c-be5a-ec2733b4bbf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005694008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2005694008
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1260660557
Short name T194
Test name
Test status
Simulation time 140829216 ps
CPU time 1.9 seconds
Started Jul 13 06:45:19 PM PDT 24
Finished Jul 13 06:45:22 PM PDT 24
Peak memory 200104 kb
Host smart-395945c7-fd06-46b9-a494-55d3d341432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260660557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1260660557
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.130203694
Short name T309
Test name
Test status
Simulation time 236024727 ps
CPU time 1.48 seconds
Started Jul 13 06:45:16 PM PDT 24
Finished Jul 13 06:45:19 PM PDT 24
Peak memory 200100 kb
Host smart-61aa60fd-6803-4a83-a1bf-6e8620d747e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130203694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.130203694
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3022238075
Short name T336
Test name
Test status
Simulation time 76533859 ps
CPU time 0.85 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:45:48 PM PDT 24
Peak memory 199888 kb
Host smart-e5a85e45-b6a0-47db-b6f0-e16d03c09292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022238075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3022238075
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3287711318
Short name T64
Test name
Test status
Simulation time 1882036205 ps
CPU time 7.35 seconds
Started Jul 13 06:45:48 PM PDT 24
Finished Jul 13 06:45:57 PM PDT 24
Peak memory 221424 kb
Host smart-4dfd55a7-14c5-447d-a084-3f3ce37f23f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287711318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3287711318
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.4024649691
Short name T533
Test name
Test status
Simulation time 244069128 ps
CPU time 1.08 seconds
Started Jul 13 06:45:49 PM PDT 24
Finished Jul 13 06:45:52 PM PDT 24
Peak memory 217460 kb
Host smart-d6b8d694-af5c-4b05-b7da-d69cf6711b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024649691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.4024649691
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3883450375
Short name T291
Test name
Test status
Simulation time 196239992 ps
CPU time 0.95 seconds
Started Jul 13 06:45:45 PM PDT 24
Finished Jul 13 06:45:47 PM PDT 24
Peak memory 199860 kb
Host smart-7ecdd247-3afb-4511-b259-baf34db2f7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883450375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3883450375
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.751357586
Short name T14
Test name
Test status
Simulation time 879779439 ps
CPU time 4.5 seconds
Started Jul 13 06:45:52 PM PDT 24
Finished Jul 13 06:45:57 PM PDT 24
Peak memory 200420 kb
Host smart-24baf3b3-da39-4b9a-ac81-52b40c43443b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751357586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.751357586
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1929229294
Short name T303
Test name
Test status
Simulation time 171567656 ps
CPU time 1.17 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:50 PM PDT 24
Peak memory 200108 kb
Host smart-b803433d-91ef-4073-9d69-596a54fa0a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929229294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1929229294
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1187353877
Short name T495
Test name
Test status
Simulation time 117527408 ps
CPU time 1.17 seconds
Started Jul 13 06:45:51 PM PDT 24
Finished Jul 13 06:45:53 PM PDT 24
Peak memory 200280 kb
Host smart-219f8247-f495-4beb-9a3a-1bda034aff7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187353877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1187353877
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1668294369
Short name T459
Test name
Test status
Simulation time 6931261051 ps
CPU time 25.24 seconds
Started Jul 13 06:45:50 PM PDT 24
Finished Jul 13 06:46:16 PM PDT 24
Peak memory 200484 kb
Host smart-c6c7b4f4-f1c9-436e-809d-ba0e8720cbe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668294369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1668294369
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.970347542
Short name T166
Test name
Test status
Simulation time 370661402 ps
CPU time 2.49 seconds
Started Jul 13 06:45:49 PM PDT 24
Finished Jul 13 06:45:53 PM PDT 24
Peak memory 200116 kb
Host smart-881fd862-6c71-4a21-8b01-308a43d9aac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970347542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.970347542
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3885677785
Short name T317
Test name
Test status
Simulation time 197064318 ps
CPU time 1.22 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:45:48 PM PDT 24
Peak memory 200084 kb
Host smart-7c568933-417b-45ef-88af-dd25f64fe4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885677785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3885677785
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2496039592
Short name T418
Test name
Test status
Simulation time 64315637 ps
CPU time 0.77 seconds
Started Jul 13 06:45:50 PM PDT 24
Finished Jul 13 06:45:52 PM PDT 24
Peak memory 199896 kb
Host smart-d4e8e468-7b42-4567-bba2-781398987d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496039592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2496039592
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2825808810
Short name T350
Test name
Test status
Simulation time 1224924508 ps
CPU time 5.71 seconds
Started Jul 13 06:45:53 PM PDT 24
Finished Jul 13 06:45:59 PM PDT 24
Peak memory 221640 kb
Host smart-2daadeec-7367-4795-b348-bd44a5287df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825808810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2825808810
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.876613024
Short name T287
Test name
Test status
Simulation time 245166820 ps
CPU time 1.05 seconds
Started Jul 13 06:45:44 PM PDT 24
Finished Jul 13 06:45:46 PM PDT 24
Peak memory 217484 kb
Host smart-2192e4d7-7fd4-429a-9bc1-38f515fc0fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876613024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.876613024
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.4190335898
Short name T496
Test name
Test status
Simulation time 124120139 ps
CPU time 0.82 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:49 PM PDT 24
Peak memory 199932 kb
Host smart-e231ded3-05f3-4d6c-b827-0fb1ef0a684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190335898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.4190335898
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.406608417
Short name T86
Test name
Test status
Simulation time 927994492 ps
CPU time 4.83 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:54 PM PDT 24
Peak memory 200352 kb
Host smart-55a28ef8-799b-49a2-8dcf-bb583713fe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406608417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.406608417
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1509863172
Short name T219
Test name
Test status
Simulation time 106280102 ps
CPU time 1.03 seconds
Started Jul 13 06:45:48 PM PDT 24
Finished Jul 13 06:45:51 PM PDT 24
Peak memory 200072 kb
Host smart-47828997-4f5c-490e-bae8-2b79fbd2c1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509863172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1509863172
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.730663153
Short name T477
Test name
Test status
Simulation time 190491089 ps
CPU time 1.33 seconds
Started Jul 13 06:45:50 PM PDT 24
Finished Jul 13 06:45:52 PM PDT 24
Peak memory 200280 kb
Host smart-5fc30ebe-0226-4db0-8b50-4f936e058726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730663153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.730663153
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.187296901
Short name T49
Test name
Test status
Simulation time 1031916876 ps
CPU time 5.14 seconds
Started Jul 13 06:45:48 PM PDT 24
Finished Jul 13 06:45:55 PM PDT 24
Peak memory 200412 kb
Host smart-e310bdc9-5760-417e-a7d7-00be3c122b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187296901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.187296901
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1694410195
Short name T328
Test name
Test status
Simulation time 147994350 ps
CPU time 1.91 seconds
Started Jul 13 06:45:45 PM PDT 24
Finished Jul 13 06:45:48 PM PDT 24
Peak memory 200120 kb
Host smart-a5b30889-43cf-453c-9889-6df01b4c2d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694410195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1694410195
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2724513207
Short name T471
Test name
Test status
Simulation time 104781955 ps
CPU time 0.98 seconds
Started Jul 13 06:45:44 PM PDT 24
Finished Jul 13 06:45:46 PM PDT 24
Peak memory 200112 kb
Host smart-d522dbfb-f25c-43c0-9df4-3f68f8bcbdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724513207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2724513207
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.711681629
Short name T356
Test name
Test status
Simulation time 1223963849 ps
CPU time 6.26 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:55 PM PDT 24
Peak memory 221648 kb
Host smart-27494375-00c1-45c9-b0dc-3135f7b07e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711681629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.711681629
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.62802369
Short name T154
Test name
Test status
Simulation time 243738839 ps
CPU time 1.19 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:45:49 PM PDT 24
Peak memory 217496 kb
Host smart-b5495aa8-0c47-41c5-8146-3e6f9729ff66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62802369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.62802369
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2723258533
Short name T319
Test name
Test status
Simulation time 232314535 ps
CPU time 1 seconds
Started Jul 13 06:45:53 PM PDT 24
Finished Jul 13 06:45:55 PM PDT 24
Peak memory 199904 kb
Host smart-60868f09-5f6b-4235-a6ba-a3f7c241a695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723258533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2723258533
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1705042817
Short name T71
Test name
Test status
Simulation time 775533388 ps
CPU time 4.04 seconds
Started Jul 13 06:45:45 PM PDT 24
Finished Jul 13 06:45:50 PM PDT 24
Peak memory 200328 kb
Host smart-0679c4d8-663b-4131-8b9c-120ff8985cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705042817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1705042817
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.711509832
Short name T324
Test name
Test status
Simulation time 105076933 ps
CPU time 1.06 seconds
Started Jul 13 06:45:48 PM PDT 24
Finished Jul 13 06:45:51 PM PDT 24
Peak memory 200124 kb
Host smart-5b4f1d6f-fa27-44f4-9515-609746599f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711509832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.711509832
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.544587713
Short name T239
Test name
Test status
Simulation time 191156931 ps
CPU time 1.35 seconds
Started Jul 13 06:45:46 PM PDT 24
Finished Jul 13 06:45:49 PM PDT 24
Peak memory 200252 kb
Host smart-0c02f4eb-61b7-4385-9427-2d200ff70215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544587713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.544587713
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2752277910
Short name T152
Test name
Test status
Simulation time 6819671433 ps
CPU time 25.35 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:46:14 PM PDT 24
Peak memory 200432 kb
Host smart-234804f6-d9d3-4e45-805f-4257855c2e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752277910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2752277910
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2413934767
Short name T130
Test name
Test status
Simulation time 457787848 ps
CPU time 2.29 seconds
Started Jul 13 06:45:47 PM PDT 24
Finished Jul 13 06:45:51 PM PDT 24
Peak memory 200152 kb
Host smart-52fa0f0c-c895-4ed1-9709-baa37221d549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413934767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2413934767
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2224865435
Short name T308
Test name
Test status
Simulation time 180235522 ps
CPU time 1.29 seconds
Started Jul 13 06:45:44 PM PDT 24
Finished Jul 13 06:45:46 PM PDT 24
Peak memory 200304 kb
Host smart-33c45566-2055-4c0c-a7b2-20645c093bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224865435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2224865435
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.925354988
Short name T33
Test name
Test status
Simulation time 69492542 ps
CPU time 0.79 seconds
Started Jul 13 06:45:56 PM PDT 24
Finished Jul 13 06:45:57 PM PDT 24
Peak memory 199896 kb
Host smart-6ca52911-e28d-49ce-9f01-a914bd1d3456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925354988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.925354988
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1457460335
Short name T501
Test name
Test status
Simulation time 2340471807 ps
CPU time 9.17 seconds
Started Jul 13 06:45:58 PM PDT 24
Finished Jul 13 06:46:08 PM PDT 24
Peak memory 217712 kb
Host smart-10e9171c-1d61-48c7-9590-237db40591c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457460335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1457460335
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3378922844
Short name T401
Test name
Test status
Simulation time 244499107 ps
CPU time 1.12 seconds
Started Jul 13 06:46:01 PM PDT 24
Finished Jul 13 06:46:02 PM PDT 24
Peak memory 217468 kb
Host smart-d7dd2c13-a574-429e-8ecc-77a5f7610173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378922844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3378922844
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1340080021
Short name T234
Test name
Test status
Simulation time 127526023 ps
CPU time 0.81 seconds
Started Jul 13 06:45:48 PM PDT 24
Finished Jul 13 06:45:51 PM PDT 24
Peak memory 199908 kb
Host smart-1f1c0210-9940-4571-b3eb-a454ec338158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340080021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1340080021
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1276305380
Short name T1
Test name
Test status
Simulation time 2141181484 ps
CPU time 7.71 seconds
Started Jul 13 06:45:53 PM PDT 24
Finished Jul 13 06:46:01 PM PDT 24
Peak memory 200376 kb
Host smart-8fa4aa36-7740-4a88-a4d6-99c66e453b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276305380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1276305380
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3452955471
Short name T465
Test name
Test status
Simulation time 155624240 ps
CPU time 1.13 seconds
Started Jul 13 06:45:58 PM PDT 24
Finished Jul 13 06:46:00 PM PDT 24
Peak memory 200092 kb
Host smart-4e468d1e-42d1-45da-943f-79c7659ac990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452955471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3452955471
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1227399860
Short name T411
Test name
Test status
Simulation time 117147335 ps
CPU time 1.24 seconds
Started Jul 13 06:45:48 PM PDT 24
Finished Jul 13 06:45:52 PM PDT 24
Peak memory 200308 kb
Host smart-2893ea7f-bf81-42b4-b332-e03d2759a4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227399860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1227399860
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.156029008
Short name T377
Test name
Test status
Simulation time 3920096890 ps
CPU time 17.9 seconds
Started Jul 13 06:45:57 PM PDT 24
Finished Jul 13 06:46:16 PM PDT 24
Peak memory 200440 kb
Host smart-8a163d1b-1e69-49d7-bff0-67e99a72bf26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156029008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.156029008
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1286042718
Short name T244
Test name
Test status
Simulation time 128528860 ps
CPU time 1.78 seconds
Started Jul 13 06:45:57 PM PDT 24
Finished Jul 13 06:46:00 PM PDT 24
Peak memory 200112 kb
Host smart-23be0cbd-0c7f-41ad-b33a-02a0646ed886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286042718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1286042718
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3416636863
Short name T480
Test name
Test status
Simulation time 266781350 ps
CPU time 1.17 seconds
Started Jul 13 06:45:57 PM PDT 24
Finished Jul 13 06:45:59 PM PDT 24
Peak memory 199888 kb
Host smart-b43ff783-4dc3-4e47-8329-0dfe5f56d9c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416636863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3416636863
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1843761205
Short name T466
Test name
Test status
Simulation time 1874712319 ps
CPU time 6.87 seconds
Started Jul 13 06:46:01 PM PDT 24
Finished Jul 13 06:46:08 PM PDT 24
Peak memory 221280 kb
Host smart-66e230a7-0581-4f34-95d7-5a88ee12022e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843761205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1843761205
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.272763531
Short name T293
Test name
Test status
Simulation time 243654851 ps
CPU time 1.13 seconds
Started Jul 13 06:45:56 PM PDT 24
Finished Jul 13 06:45:58 PM PDT 24
Peak memory 217488 kb
Host smart-3991615f-29a3-47cf-9b1e-2678805a42e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272763531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.272763531
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3485927554
Short name T204
Test name
Test status
Simulation time 152199872 ps
CPU time 0.95 seconds
Started Jul 13 06:46:00 PM PDT 24
Finished Jul 13 06:46:02 PM PDT 24
Peak memory 199888 kb
Host smart-c701937f-8583-4041-8489-e8f3c4fe1e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485927554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3485927554
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.4294248293
Short name T306
Test name
Test status
Simulation time 2058340182 ps
CPU time 7.44 seconds
Started Jul 13 06:45:58 PM PDT 24
Finished Jul 13 06:46:06 PM PDT 24
Peak memory 200348 kb
Host smart-44492210-bb86-4881-a182-bd6390843bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294248293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.4294248293
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2505959045
Short name T70
Test name
Test status
Simulation time 159037614 ps
CPU time 1.12 seconds
Started Jul 13 06:46:03 PM PDT 24
Finished Jul 13 06:46:05 PM PDT 24
Peak memory 200100 kb
Host smart-98795549-12fe-485b-b183-6783e624edcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505959045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2505959045
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1246494737
Short name T426
Test name
Test status
Simulation time 194042243 ps
CPU time 1.32 seconds
Started Jul 13 06:46:19 PM PDT 24
Finished Jul 13 06:46:21 PM PDT 24
Peak memory 200524 kb
Host smart-6c803e8f-1ea6-4c92-9db4-733d409f8aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246494737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1246494737
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2572229128
Short name T389
Test name
Test status
Simulation time 1287247715 ps
CPU time 5.31 seconds
Started Jul 13 06:45:58 PM PDT 24
Finished Jul 13 06:46:04 PM PDT 24
Peak memory 200384 kb
Host smart-651141aa-34bc-4ca7-9a47-d4cdd2c19f65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572229128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2572229128
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2340217321
Short name T381
Test name
Test status
Simulation time 443748437 ps
CPU time 2.36 seconds
Started Jul 13 06:45:55 PM PDT 24
Finished Jul 13 06:45:58 PM PDT 24
Peak memory 200100 kb
Host smart-d3ddc313-0a3b-4c1f-b52f-5d1ebe4708a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340217321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2340217321
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2928067471
Short name T321
Test name
Test status
Simulation time 128649347 ps
CPU time 1.03 seconds
Started Jul 13 06:45:56 PM PDT 24
Finished Jul 13 06:45:58 PM PDT 24
Peak memory 200052 kb
Host smart-394355d7-bf6e-49e0-b231-765a2bcbc3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928067471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2928067471
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3280397696
Short name T139
Test name
Test status
Simulation time 76580298 ps
CPU time 0.83 seconds
Started Jul 13 06:46:03 PM PDT 24
Finished Jul 13 06:46:04 PM PDT 24
Peak memory 199876 kb
Host smart-b1b85cf9-8cf0-46dc-8e2a-fc6bcb3809b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280397696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3280397696
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3946641595
Short name T59
Test name
Test status
Simulation time 1897828081 ps
CPU time 7.54 seconds
Started Jul 13 06:45:57 PM PDT 24
Finished Jul 13 06:46:05 PM PDT 24
Peak memory 221672 kb
Host smart-afbf062c-ff17-4961-ac94-41a1eea853d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946641595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3946641595
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3107201179
Short name T509
Test name
Test status
Simulation time 246659945 ps
CPU time 1.13 seconds
Started Jul 13 06:45:58 PM PDT 24
Finished Jul 13 06:46:00 PM PDT 24
Peak memory 217476 kb
Host smart-2da2ed2e-3632-4486-83e0-41bcb0a2107e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107201179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3107201179
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3362806044
Short name T222
Test name
Test status
Simulation time 226414360 ps
CPU time 0.9 seconds
Started Jul 13 06:45:55 PM PDT 24
Finished Jul 13 06:45:57 PM PDT 24
Peak memory 199856 kb
Host smart-07feba7c-0bc8-46e5-8abc-fb19fc106cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362806044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3362806044
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2253024444
Short name T323
Test name
Test status
Simulation time 600541827 ps
CPU time 3.52 seconds
Started Jul 13 06:46:00 PM PDT 24
Finished Jul 13 06:46:04 PM PDT 24
Peak memory 200376 kb
Host smart-e2bb39ec-b3e6-4b05-b86e-b8b265de7562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253024444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2253024444
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1473972917
Short name T535
Test name
Test status
Simulation time 112249080 ps
CPU time 1.05 seconds
Started Jul 13 06:45:58 PM PDT 24
Finished Jul 13 06:46:00 PM PDT 24
Peak memory 200060 kb
Host smart-c45a635c-1c2c-47f8-8b0c-fa05c1598334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473972917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1473972917
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3271551706
Short name T313
Test name
Test status
Simulation time 122608858 ps
CPU time 1.18 seconds
Started Jul 13 06:45:58 PM PDT 24
Finished Jul 13 06:46:00 PM PDT 24
Peak memory 200360 kb
Host smart-bc6f9dc0-59a0-4c9a-b7b1-a3c87ba3c42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271551706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3271551706
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3778529929
Short name T52
Test name
Test status
Simulation time 4474730874 ps
CPU time 16.27 seconds
Started Jul 13 06:45:57 PM PDT 24
Finished Jul 13 06:46:15 PM PDT 24
Peak memory 200424 kb
Host smart-e453a3ee-91f8-4018-b3ca-3754fd423a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778529929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3778529929
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2617081646
Short name T269
Test name
Test status
Simulation time 371155164 ps
CPU time 2.17 seconds
Started Jul 13 06:45:58 PM PDT 24
Finished Jul 13 06:46:01 PM PDT 24
Peak memory 200132 kb
Host smart-c6f7410f-71f7-496a-826e-c16e0d925e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617081646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2617081646
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2569497100
Short name T360
Test name
Test status
Simulation time 137857306 ps
CPU time 1.08 seconds
Started Jul 13 06:45:58 PM PDT 24
Finished Jul 13 06:46:00 PM PDT 24
Peak memory 200120 kb
Host smart-b56a09d3-c763-4c68-8f66-ecf5f73e557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569497100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2569497100
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2201550746
Short name T28
Test name
Test status
Simulation time 78899991 ps
CPU time 0.8 seconds
Started Jul 13 06:45:56 PM PDT 24
Finished Jul 13 06:45:57 PM PDT 24
Peak memory 199916 kb
Host smart-6d6112bc-1b16-4402-922c-9a47ddc376d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201550746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2201550746
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3934378123
Short name T35
Test name
Test status
Simulation time 1894215996 ps
CPU time 7.57 seconds
Started Jul 13 06:45:55 PM PDT 24
Finished Jul 13 06:46:03 PM PDT 24
Peak memory 217676 kb
Host smart-531cf37c-411b-4462-bcce-3e57dd89bb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934378123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3934378123
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2765684737
Short name T458
Test name
Test status
Simulation time 244320388 ps
CPU time 1.06 seconds
Started Jul 13 06:45:56 PM PDT 24
Finished Jul 13 06:45:58 PM PDT 24
Peak memory 217464 kb
Host smart-8f841d46-7e7a-4d09-8f34-3a314073ed43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765684737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2765684737
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3077962442
Short name T21
Test name
Test status
Simulation time 219409502 ps
CPU time 0.92 seconds
Started Jul 13 06:45:57 PM PDT 24
Finished Jul 13 06:45:59 PM PDT 24
Peak memory 199924 kb
Host smart-36e329f4-58f2-42c5-8068-479b5cf655c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077962442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3077962442
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3061159477
Short name T107
Test name
Test status
Simulation time 950794674 ps
CPU time 4.95 seconds
Started Jul 13 06:46:05 PM PDT 24
Finished Jul 13 06:46:11 PM PDT 24
Peak memory 200372 kb
Host smart-fef50ce0-7f6a-4da6-aae5-b89fb96d8d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061159477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3061159477
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.725337392
Short name T331
Test name
Test status
Simulation time 145399490 ps
CPU time 1.12 seconds
Started Jul 13 06:45:56 PM PDT 24
Finished Jul 13 06:45:58 PM PDT 24
Peak memory 200040 kb
Host smart-b798c38e-67eb-4825-bc61-964808898d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725337392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.725337392
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3357090080
Short name T199
Test name
Test status
Simulation time 242906501 ps
CPU time 1.49 seconds
Started Jul 13 06:45:56 PM PDT 24
Finished Jul 13 06:45:58 PM PDT 24
Peak memory 200312 kb
Host smart-3884c11e-fe87-4a73-ba25-bad4699bb225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357090080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3357090080
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.616805986
Short name T46
Test name
Test status
Simulation time 1929831474 ps
CPU time 7.31 seconds
Started Jul 13 06:46:01 PM PDT 24
Finished Jul 13 06:46:09 PM PDT 24
Peak memory 208288 kb
Host smart-f1766b8c-5c18-4ee7-bb9b-7c8299916a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616805986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.616805986
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2348324256
Short name T347
Test name
Test status
Simulation time 370576778 ps
CPU time 2.31 seconds
Started Jul 13 06:45:57 PM PDT 24
Finished Jul 13 06:46:00 PM PDT 24
Peak memory 200092 kb
Host smart-de5056bd-25d9-474f-9f17-232ec56794d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348324256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2348324256
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.159247513
Short name T148
Test name
Test status
Simulation time 115114842 ps
CPU time 1.03 seconds
Started Jul 13 06:45:54 PM PDT 24
Finished Jul 13 06:45:55 PM PDT 24
Peak memory 200096 kb
Host smart-759f13e7-dbab-47a7-814a-6737f480b1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159247513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.159247513
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.87734115
Short name T241
Test name
Test status
Simulation time 58986084 ps
CPU time 0.76 seconds
Started Jul 13 06:46:05 PM PDT 24
Finished Jul 13 06:46:06 PM PDT 24
Peak memory 199880 kb
Host smart-5abec7d6-aa36-4b40-a461-658529650b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87734115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.87734115
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2365639740
Short name T60
Test name
Test status
Simulation time 2167337451 ps
CPU time 8.38 seconds
Started Jul 13 06:46:06 PM PDT 24
Finished Jul 13 06:46:15 PM PDT 24
Peak memory 221756 kb
Host smart-8a6c0298-b323-4a18-8bf6-1af56543f2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365639740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2365639740
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.4238193846
Short name T504
Test name
Test status
Simulation time 254749879 ps
CPU time 1.09 seconds
Started Jul 13 06:46:10 PM PDT 24
Finished Jul 13 06:46:12 PM PDT 24
Peak memory 217464 kb
Host smart-67cbabf4-da3f-4d97-97f5-2160ee622ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238193846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.4238193846
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1109908619
Short name T526
Test name
Test status
Simulation time 131857628 ps
CPU time 0.83 seconds
Started Jul 13 06:46:00 PM PDT 24
Finished Jul 13 06:46:01 PM PDT 24
Peak memory 199900 kb
Host smart-a59fc715-7203-4644-8daa-c4d3fc252c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109908619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1109908619
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2341005943
Short name T3
Test name
Test status
Simulation time 1407160876 ps
CPU time 6.02 seconds
Started Jul 13 06:45:56 PM PDT 24
Finished Jul 13 06:46:03 PM PDT 24
Peak memory 200348 kb
Host smart-6cf50d22-8982-4abb-9271-c6ecde2a4829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341005943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2341005943
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1822483965
Short name T172
Test name
Test status
Simulation time 176119320 ps
CPU time 1.19 seconds
Started Jul 13 06:45:55 PM PDT 24
Finished Jul 13 06:45:57 PM PDT 24
Peak memory 200076 kb
Host smart-7e515bbd-8bdc-48c5-b803-f546703d2f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822483965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1822483965
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.492836016
Short name T463
Test name
Test status
Simulation time 125192353 ps
CPU time 1.26 seconds
Started Jul 13 06:45:59 PM PDT 24
Finished Jul 13 06:46:01 PM PDT 24
Peak memory 200284 kb
Host smart-cb2ef7a7-09e0-4ff2-888c-f34223df91e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492836016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.492836016
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.4161672628
Short name T246
Test name
Test status
Simulation time 12860142086 ps
CPU time 50.04 seconds
Started Jul 13 06:46:08 PM PDT 24
Finished Jul 13 06:47:00 PM PDT 24
Peak memory 200728 kb
Host smart-61b1082a-fef7-458d-927b-23e4a62bb499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161672628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.4161672628
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2266778652
Short name T278
Test name
Test status
Simulation time 130451516 ps
CPU time 1.93 seconds
Started Jul 13 06:46:01 PM PDT 24
Finished Jul 13 06:46:03 PM PDT 24
Peak memory 208304 kb
Host smart-a1422e5f-8428-4fce-a47f-902a7e48fc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266778652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2266778652
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2593712539
Short name T205
Test name
Test status
Simulation time 143613185 ps
CPU time 1.12 seconds
Started Jul 13 06:46:03 PM PDT 24
Finished Jul 13 06:46:05 PM PDT 24
Peak memory 200036 kb
Host smart-a24cafde-79c6-4288-9550-2a6f5e414fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593712539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2593712539
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2874488805
Short name T215
Test name
Test status
Simulation time 54106247 ps
CPU time 0.8 seconds
Started Jul 13 06:46:12 PM PDT 24
Finished Jul 13 06:46:14 PM PDT 24
Peak memory 199900 kb
Host smart-0691b392-3b32-4b40-b6f8-99a91f5cac5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874488805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2874488805
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2571662342
Short name T66
Test name
Test status
Simulation time 1225208195 ps
CPU time 5.43 seconds
Started Jul 13 06:46:11 PM PDT 24
Finished Jul 13 06:46:17 PM PDT 24
Peak memory 217696 kb
Host smart-2b1fe1c9-50c2-4424-bfa4-b184bb78b020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571662342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2571662342
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1285579223
Short name T312
Test name
Test status
Simulation time 243913187 ps
CPU time 1.19 seconds
Started Jul 13 06:46:08 PM PDT 24
Finished Jul 13 06:46:10 PM PDT 24
Peak memory 217476 kb
Host smart-51adb573-b89d-46ce-b304-316eb1ea5857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285579223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1285579223
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3674632748
Short name T276
Test name
Test status
Simulation time 95369418 ps
CPU time 0.8 seconds
Started Jul 13 06:46:08 PM PDT 24
Finished Jul 13 06:46:10 PM PDT 24
Peak memory 199904 kb
Host smart-f680e08c-8ece-429f-a542-a6cf8eeaf186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674632748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3674632748
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.4194611389
Short name T379
Test name
Test status
Simulation time 1633043826 ps
CPU time 6.14 seconds
Started Jul 13 06:46:05 PM PDT 24
Finished Jul 13 06:46:12 PM PDT 24
Peak memory 200392 kb
Host smart-d72e0ad5-63a4-40ff-b885-24bf8538c0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194611389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.4194611389
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1895545124
Short name T292
Test name
Test status
Simulation time 177364998 ps
CPU time 1.24 seconds
Started Jul 13 06:46:03 PM PDT 24
Finished Jul 13 06:46:05 PM PDT 24
Peak memory 200048 kb
Host smart-49ff9e9d-ade2-47a9-ad10-f0ff73579ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895545124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1895545124
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2149292911
Short name T67
Test name
Test status
Simulation time 117069899 ps
CPU time 1.2 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:18 PM PDT 24
Peak memory 200252 kb
Host smart-60e3514c-2249-4a74-90d0-a166b5d63cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149292911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2149292911
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2943366681
Short name T103
Test name
Test status
Simulation time 1962205017 ps
CPU time 9.34 seconds
Started Jul 13 06:46:04 PM PDT 24
Finished Jul 13 06:46:15 PM PDT 24
Peak memory 208580 kb
Host smart-98f96fdc-ae0f-466c-87d6-9f78ed6b0785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943366681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2943366681
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1774191998
Short name T248
Test name
Test status
Simulation time 145448753 ps
CPU time 1.98 seconds
Started Jul 13 06:46:13 PM PDT 24
Finished Jul 13 06:46:16 PM PDT 24
Peak memory 208528 kb
Host smart-5af52e95-47c1-4102-b6ff-0993dfea1bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774191998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1774191998
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3201766772
Short name T320
Test name
Test status
Simulation time 243873256 ps
CPU time 1.45 seconds
Started Jul 13 06:46:13 PM PDT 24
Finished Jul 13 06:46:16 PM PDT 24
Peak memory 200284 kb
Host smart-41652e90-f51e-4885-9009-3be9dbbd4da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201766772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3201766772
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.734487752
Short name T344
Test name
Test status
Simulation time 80532346 ps
CPU time 0.85 seconds
Started Jul 13 06:46:08 PM PDT 24
Finished Jul 13 06:46:10 PM PDT 24
Peak memory 199884 kb
Host smart-94066c45-4bc5-46f5-a740-44f2845c46e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734487752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.734487752
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3909920668
Short name T56
Test name
Test status
Simulation time 1904460977 ps
CPU time 7.91 seconds
Started Jul 13 06:46:11 PM PDT 24
Finished Jul 13 06:46:20 PM PDT 24
Peak memory 216796 kb
Host smart-f80a5088-cc0c-4868-9098-ec23b64a1255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909920668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3909920668
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1867747010
Short name T531
Test name
Test status
Simulation time 243873348 ps
CPU time 1.08 seconds
Started Jul 13 06:46:05 PM PDT 24
Finished Jul 13 06:46:07 PM PDT 24
Peak memory 217468 kb
Host smart-8753ccbc-268e-4afe-824c-904f4bb3075d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867747010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1867747010
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1357339457
Short name T383
Test name
Test status
Simulation time 143326161 ps
CPU time 0.85 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:16 PM PDT 24
Peak memory 199876 kb
Host smart-83c95882-3cc5-45bd-8c59-3924dbc801e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357339457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1357339457
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3770690647
Short name T467
Test name
Test status
Simulation time 1436449921 ps
CPU time 6.32 seconds
Started Jul 13 06:46:10 PM PDT 24
Finished Jul 13 06:46:17 PM PDT 24
Peak memory 200376 kb
Host smart-14c5e3a5-bf65-4cfc-a17e-50ff99e7b95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770690647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3770690647
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4158074989
Short name T242
Test name
Test status
Simulation time 188869882 ps
CPU time 1.34 seconds
Started Jul 13 06:46:07 PM PDT 24
Finished Jul 13 06:46:10 PM PDT 24
Peak memory 200140 kb
Host smart-897d9903-31c3-4ab2-ab96-d713efa9c4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158074989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4158074989
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2218033350
Short name T469
Test name
Test status
Simulation time 199658487 ps
CPU time 1.33 seconds
Started Jul 13 06:46:08 PM PDT 24
Finished Jul 13 06:46:10 PM PDT 24
Peak memory 200284 kb
Host smart-b3ac5dda-f806-4d02-bf20-039ec2238317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218033350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2218033350
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2606017024
Short name T443
Test name
Test status
Simulation time 3545818946 ps
CPU time 14.46 seconds
Started Jul 13 06:46:10 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 208608 kb
Host smart-64f83e2e-4ed4-422b-b7c4-877a6c5fc253
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606017024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2606017024
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1660630118
Short name T192
Test name
Test status
Simulation time 297861834 ps
CPU time 2.19 seconds
Started Jul 13 06:46:07 PM PDT 24
Finished Jul 13 06:46:11 PM PDT 24
Peak memory 208352 kb
Host smart-c8806ed2-eada-4213-a74b-65c22cd7bfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660630118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1660630118
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3968085429
Short name T13
Test name
Test status
Simulation time 267279802 ps
CPU time 1.48 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 200272 kb
Host smart-eea9d2b1-fe4d-470a-a360-f3c6ebe152e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968085429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3968085429
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2323478373
Short name T146
Test name
Test status
Simulation time 67623674 ps
CPU time 0.8 seconds
Started Jul 13 06:45:28 PM PDT 24
Finished Jul 13 06:45:30 PM PDT 24
Peak memory 199904 kb
Host smart-249e69aa-f6ec-4813-84da-f8ff3132bd79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323478373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2323478373
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3042058108
Short name T51
Test name
Test status
Simulation time 1232087143 ps
CPU time 5.75 seconds
Started Jul 13 06:45:24 PM PDT 24
Finished Jul 13 06:45:31 PM PDT 24
Peak memory 217500 kb
Host smart-dd715d26-fc98-4d5b-b400-d6b5c99f9737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042058108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3042058108
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.512017285
Short name T301
Test name
Test status
Simulation time 244697186 ps
CPU time 1.1 seconds
Started Jul 13 06:45:28 PM PDT 24
Finished Jul 13 06:45:31 PM PDT 24
Peak memory 217376 kb
Host smart-97ff841b-6853-4979-bf5c-da434086ba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512017285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.512017285
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.4117872456
Short name T482
Test name
Test status
Simulation time 89274567 ps
CPU time 0.74 seconds
Started Jul 13 06:45:17 PM PDT 24
Finished Jul 13 06:45:19 PM PDT 24
Peak memory 199900 kb
Host smart-87f3d4d0-3cce-4b55-8af0-e6dc9399c4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117872456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.4117872456
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1834974200
Short name T445
Test name
Test status
Simulation time 1354050202 ps
CPU time 5.95 seconds
Started Jul 13 06:45:26 PM PDT 24
Finished Jul 13 06:45:33 PM PDT 24
Peak memory 200420 kb
Host smart-14fe00c0-4a89-45f2-9f2e-9c30fd80a191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834974200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1834974200
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3390058204
Short name T84
Test name
Test status
Simulation time 17954296194 ps
CPU time 28.05 seconds
Started Jul 13 06:45:27 PM PDT 24
Finished Jul 13 06:45:57 PM PDT 24
Peak memory 217276 kb
Host smart-331b34a7-dc2f-4988-92fe-81bb355000e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390058204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3390058204
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2428376465
Short name T232
Test name
Test status
Simulation time 106690418 ps
CPU time 1.01 seconds
Started Jul 13 06:45:28 PM PDT 24
Finished Jul 13 06:45:31 PM PDT 24
Peak memory 200076 kb
Host smart-e37874db-085e-4f83-b626-ac6d6057ae52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428376465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2428376465
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1254244778
Short name T514
Test name
Test status
Simulation time 185323405 ps
CPU time 1.37 seconds
Started Jul 13 06:45:20 PM PDT 24
Finished Jul 13 06:45:22 PM PDT 24
Peak memory 200320 kb
Host smart-5d04b0cf-b2c3-4d19-8e0e-a0930e6c969a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254244778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1254244778
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3055052599
Short name T483
Test name
Test status
Simulation time 5823583481 ps
CPU time 23.97 seconds
Started Jul 13 06:45:25 PM PDT 24
Finished Jul 13 06:45:50 PM PDT 24
Peak memory 208580 kb
Host smart-ead83ca9-42b8-4a42-ae10-b7680eec4dc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055052599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3055052599
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1906478016
Short name T307
Test name
Test status
Simulation time 457151402 ps
CPU time 2.57 seconds
Started Jul 13 06:45:32 PM PDT 24
Finished Jul 13 06:45:36 PM PDT 24
Peak memory 200116 kb
Host smart-69a5d2cc-488e-44f3-afb9-562be215e4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906478016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1906478016
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.994160739
Short name T373
Test name
Test status
Simulation time 103533952 ps
CPU time 0.96 seconds
Started Jul 13 06:45:29 PM PDT 24
Finished Jul 13 06:45:32 PM PDT 24
Peak memory 200076 kb
Host smart-623661dd-8dd4-447c-82a0-c82306bd858b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994160739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.994160739
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.734749257
Short name T280
Test name
Test status
Simulation time 88703205 ps
CPU time 0.87 seconds
Started Jul 13 06:46:13 PM PDT 24
Finished Jul 13 06:46:15 PM PDT 24
Peak memory 199892 kb
Host smart-3202bb1d-e13b-4052-a54f-3aa35008e0cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734749257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.734749257
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3227871265
Short name T62
Test name
Test status
Simulation time 1214489369 ps
CPU time 6.41 seconds
Started Jul 13 06:46:09 PM PDT 24
Finished Jul 13 06:46:16 PM PDT 24
Peak memory 221708 kb
Host smart-0c81db7e-9f0d-45ed-97d3-a9928d88ca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227871265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3227871265
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2662075906
Short name T283
Test name
Test status
Simulation time 243746275 ps
CPU time 1.13 seconds
Started Jul 13 06:46:11 PM PDT 24
Finished Jul 13 06:46:13 PM PDT 24
Peak memory 217460 kb
Host smart-8ad786b7-5afd-422f-a477-f854aa55479f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662075906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2662075906
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.4258011150
Short name T235
Test name
Test status
Simulation time 89994346 ps
CPU time 0.8 seconds
Started Jul 13 06:46:12 PM PDT 24
Finished Jul 13 06:46:14 PM PDT 24
Peak memory 199920 kb
Host smart-080a30ed-9ef9-4704-b967-f8d711206f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258011150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.4258011150
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.157094135
Short name T126
Test name
Test status
Simulation time 1641994906 ps
CPU time 5.94 seconds
Started Jul 13 06:46:07 PM PDT 24
Finished Jul 13 06:46:14 PM PDT 24
Peak memory 200348 kb
Host smart-28fc7882-1f7d-4768-9580-5b7855019e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157094135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.157094135
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.4251877722
Short name T142
Test name
Test status
Simulation time 106908176 ps
CPU time 1.01 seconds
Started Jul 13 06:46:16 PM PDT 24
Finished Jul 13 06:46:20 PM PDT 24
Peak memory 200064 kb
Host smart-18074f4b-6d3d-4194-bf2b-46d4b16547dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251877722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.4251877722
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1954620832
Short name T156
Test name
Test status
Simulation time 115656405 ps
CPU time 1.2 seconds
Started Jul 13 06:46:09 PM PDT 24
Finished Jul 13 06:46:12 PM PDT 24
Peak memory 200280 kb
Host smart-9df7e6b7-11a3-4126-9d32-450670398673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954620832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1954620832
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2756561208
Short name T438
Test name
Test status
Simulation time 4712859683 ps
CPU time 17.37 seconds
Started Jul 13 06:46:09 PM PDT 24
Finished Jul 13 06:46:27 PM PDT 24
Peak memory 210428 kb
Host smart-037c8465-f7d9-434b-b16b-5ac5de7d0552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756561208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2756561208
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1523193102
Short name T174
Test name
Test status
Simulation time 362072327 ps
CPU time 2.44 seconds
Started Jul 13 06:46:07 PM PDT 24
Finished Jul 13 06:46:10 PM PDT 24
Peak memory 200092 kb
Host smart-7cfa43e1-cc51-4976-acb6-d39796132aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523193102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1523193102
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2326194210
Short name T225
Test name
Test status
Simulation time 75399408 ps
CPU time 0.83 seconds
Started Jul 13 06:46:09 PM PDT 24
Finished Jul 13 06:46:11 PM PDT 24
Peak memory 200036 kb
Host smart-41859868-deb5-486e-be4f-e635c3531184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326194210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2326194210
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1067298826
Short name T191
Test name
Test status
Simulation time 63080694 ps
CPU time 0.72 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:17 PM PDT 24
Peak memory 199856 kb
Host smart-00c7f2b1-8966-4c8a-a264-be0ac142da07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067298826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1067298826
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1649351246
Short name T529
Test name
Test status
Simulation time 1220370009 ps
CPU time 5.35 seconds
Started Jul 13 06:46:06 PM PDT 24
Finished Jul 13 06:46:12 PM PDT 24
Peak memory 217524 kb
Host smart-a519dc68-c5de-4f48-bbb9-7f77fb51d41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649351246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1649351246
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2493005846
Short name T218
Test name
Test status
Simulation time 244997233 ps
CPU time 1.11 seconds
Started Jul 13 06:46:09 PM PDT 24
Finished Jul 13 06:46:12 PM PDT 24
Peak memory 217452 kb
Host smart-a9033f28-baef-4ed2-8579-8d6e4e7283a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493005846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2493005846
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3851225355
Short name T23
Test name
Test status
Simulation time 215500065 ps
CPU time 0.97 seconds
Started Jul 13 06:46:12 PM PDT 24
Finished Jul 13 06:46:14 PM PDT 24
Peak memory 199848 kb
Host smart-001b4db6-6c60-4906-acd6-2e07ee1b1f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851225355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3851225355
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3034352236
Short name T486
Test name
Test status
Simulation time 1958998401 ps
CPU time 7.18 seconds
Started Jul 13 06:46:04 PM PDT 24
Finished Jul 13 06:46:13 PM PDT 24
Peak memory 200360 kb
Host smart-8d94cdaa-4cc4-454e-a00c-2a52cc228fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034352236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3034352236
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2653309988
Short name T415
Test name
Test status
Simulation time 164500341 ps
CPU time 1.21 seconds
Started Jul 13 06:46:04 PM PDT 24
Finished Jul 13 06:46:06 PM PDT 24
Peak memory 200096 kb
Host smart-6a136511-b5c0-4991-88bf-7e7daf449dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653309988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2653309988
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2494501234
Short name T227
Test name
Test status
Simulation time 120571312 ps
CPU time 1.24 seconds
Started Jul 13 06:46:04 PM PDT 24
Finished Jul 13 06:46:06 PM PDT 24
Peak memory 200308 kb
Host smart-22c7f417-63ef-4259-9ffd-8c10b2637546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494501234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2494501234
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.4167305583
Short name T125
Test name
Test status
Simulation time 5813498364 ps
CPU time 19.45 seconds
Started Jul 13 06:46:08 PM PDT 24
Finished Jul 13 06:46:28 PM PDT 24
Peak memory 208628 kb
Host smart-c74df237-09cd-47fd-ad2e-674282827e66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167305583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.4167305583
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.462625043
Short name T27
Test name
Test status
Simulation time 361527365 ps
CPU time 2.38 seconds
Started Jul 13 06:46:09 PM PDT 24
Finished Jul 13 06:46:13 PM PDT 24
Peak memory 200024 kb
Host smart-c84e8b03-b961-4ff1-91f7-cb1fbdaf7efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462625043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.462625043
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.250394535
Short name T368
Test name
Test status
Simulation time 91287609 ps
CPU time 0.91 seconds
Started Jul 13 06:46:19 PM PDT 24
Finished Jul 13 06:46:21 PM PDT 24
Peak memory 200048 kb
Host smart-fa8ab80e-df65-4f65-a5d4-61e9b7383557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250394535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.250394535
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.4118968201
Short name T362
Test name
Test status
Simulation time 64454328 ps
CPU time 0.72 seconds
Started Jul 13 06:46:07 PM PDT 24
Finished Jul 13 06:46:08 PM PDT 24
Peak memory 199892 kb
Host smart-1f52a64f-066d-414e-a213-0941ac3e1cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118968201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.4118968201
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3235302599
Short name T326
Test name
Test status
Simulation time 243827454 ps
CPU time 1.06 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 217424 kb
Host smart-c815116f-cb07-4b44-a82c-d819247ba4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235302599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3235302599
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1676982829
Short name T183
Test name
Test status
Simulation time 163621297 ps
CPU time 0.83 seconds
Started Jul 13 06:46:03 PM PDT 24
Finished Jul 13 06:46:05 PM PDT 24
Peak memory 199900 kb
Host smart-3e1c3106-2311-404f-885c-c6f21a48331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676982829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1676982829
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1881570948
Short name T296
Test name
Test status
Simulation time 1268631864 ps
CPU time 5.4 seconds
Started Jul 13 06:46:07 PM PDT 24
Finished Jul 13 06:46:13 PM PDT 24
Peak memory 200352 kb
Host smart-648537ad-6d43-4e14-b229-99e7bc8144b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881570948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1881570948
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.4178951298
Short name T416
Test name
Test status
Simulation time 184076657 ps
CPU time 1.2 seconds
Started Jul 13 06:46:06 PM PDT 24
Finished Jul 13 06:46:08 PM PDT 24
Peak memory 200076 kb
Host smart-f910cecf-a146-4c16-ac78-ae07b299b0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178951298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.4178951298
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1720819016
Short name T7
Test name
Test status
Simulation time 111569797 ps
CPU time 1.16 seconds
Started Jul 13 06:46:24 PM PDT 24
Finished Jul 13 06:46:28 PM PDT 24
Peak memory 200304 kb
Host smart-592d8fdb-1f59-4ff9-83fb-793be1ad2f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720819016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1720819016
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1908285684
Short name T343
Test name
Test status
Simulation time 3507433874 ps
CPU time 12.99 seconds
Started Jul 13 06:46:13 PM PDT 24
Finished Jul 13 06:46:27 PM PDT 24
Peak memory 208584 kb
Host smart-691cb524-dcc6-4146-aa54-c0151c82621a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908285684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1908285684
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1058965833
Short name T494
Test name
Test status
Simulation time 412744769 ps
CPU time 2.25 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:20 PM PDT 24
Peak memory 200056 kb
Host smart-0c89634a-6475-4341-ae9f-9d1796873c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058965833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1058965833
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1531284967
Short name T137
Test name
Test status
Simulation time 93066182 ps
CPU time 0.94 seconds
Started Jul 13 06:46:10 PM PDT 24
Finished Jul 13 06:46:12 PM PDT 24
Peak memory 200100 kb
Host smart-5ef32000-e27f-4c90-aa7c-f0f24f9325fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531284967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1531284967
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1290585411
Short name T209
Test name
Test status
Simulation time 61658116 ps
CPU time 0.74 seconds
Started Jul 13 06:46:21 PM PDT 24
Finished Jul 13 06:46:22 PM PDT 24
Peak memory 199884 kb
Host smart-6688a23d-76fb-4397-bd3d-583b62954e7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290585411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1290585411
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.980745931
Short name T523
Test name
Test status
Simulation time 1216704571 ps
CPU time 6.28 seconds
Started Jul 13 06:46:12 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 217752 kb
Host smart-8fa766c6-e8c4-46ca-a6c1-e93fe6e47546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980745931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.980745931
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3728316901
Short name T240
Test name
Test status
Simulation time 245790301 ps
CPU time 1.11 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:17 PM PDT 24
Peak memory 217472 kb
Host smart-4df664b5-94b3-4260-bc28-b0a88cc7d4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728316901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3728316901
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2014437447
Short name T527
Test name
Test status
Simulation time 147874375 ps
CPU time 0.89 seconds
Started Jul 13 06:46:05 PM PDT 24
Finished Jul 13 06:46:07 PM PDT 24
Peak memory 199920 kb
Host smart-f2fc34e5-d09e-4a79-bee4-177179068638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014437447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2014437447
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.202254004
Short name T195
Test name
Test status
Simulation time 1340370154 ps
CPU time 5.53 seconds
Started Jul 13 06:46:13 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 200324 kb
Host smart-350d6669-fa42-4785-829e-a0c6d85cfa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202254004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.202254004
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3892341778
Short name T210
Test name
Test status
Simulation time 145159432 ps
CPU time 1.17 seconds
Started Jul 13 06:46:09 PM PDT 24
Finished Jul 13 06:46:11 PM PDT 24
Peak memory 200096 kb
Host smart-6fbf39c1-3479-4fa7-abf4-d04548dbb87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892341778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3892341778
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2677284655
Short name T187
Test name
Test status
Simulation time 128741848 ps
CPU time 1.2 seconds
Started Jul 13 06:46:24 PM PDT 24
Finished Jul 13 06:46:27 PM PDT 24
Peak memory 200252 kb
Host smart-846cfd42-623d-40e6-a504-82cbfa9ba4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677284655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2677284655
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.696706989
Short name T491
Test name
Test status
Simulation time 8322307053 ps
CPU time 37.01 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:55 PM PDT 24
Peak memory 209500 kb
Host smart-f771730e-e280-405a-a3d5-e3693be374f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696706989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.696706989
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.453879780
Short name T489
Test name
Test status
Simulation time 332786305 ps
CPU time 2.12 seconds
Started Jul 13 06:46:08 PM PDT 24
Finished Jul 13 06:46:11 PM PDT 24
Peak memory 200156 kb
Host smart-cf0c2a2a-4e0f-4ae1-9df7-0b34eda7f402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453879780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.453879780
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2108349992
Short name T397
Test name
Test status
Simulation time 119066525 ps
CPU time 1.03 seconds
Started Jul 13 06:46:12 PM PDT 24
Finished Jul 13 06:46:14 PM PDT 24
Peak memory 200036 kb
Host smart-e59ed05d-1979-4fe3-a83a-5e85d72ae9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108349992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2108349992
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1882199747
Short name T54
Test name
Test status
Simulation time 55480201 ps
CPU time 0.78 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 199916 kb
Host smart-6ed6c3bc-8109-402e-a0ad-faf22720c0fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882199747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1882199747
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2449766270
Short name T485
Test name
Test status
Simulation time 2359759077 ps
CPU time 9.19 seconds
Started Jul 13 06:46:16 PM PDT 24
Finished Jul 13 06:46:28 PM PDT 24
Peak memory 217528 kb
Host smart-b9159bdf-919f-4171-bd6e-c955968ffe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449766270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2449766270
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1991387715
Short name T272
Test name
Test status
Simulation time 244125619 ps
CPU time 1.14 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 217456 kb
Host smart-314a15ca-8a29-4b72-9781-4a86337647c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991387715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1991387715
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3694710261
Short name T460
Test name
Test status
Simulation time 225161804 ps
CPU time 0.94 seconds
Started Jul 13 06:46:22 PM PDT 24
Finished Jul 13 06:46:23 PM PDT 24
Peak memory 199912 kb
Host smart-8188907b-ff76-4cb7-98c5-bf1e22c52583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694710261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3694710261
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.50266138
Short name T393
Test name
Test status
Simulation time 1030254262 ps
CPU time 5.18 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:23 PM PDT 24
Peak memory 200376 kb
Host smart-90eab074-e89e-49df-8808-aeb906e9b94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50266138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.50266138
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1848332820
Short name T492
Test name
Test status
Simulation time 159775331 ps
CPU time 1.19 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:16 PM PDT 24
Peak memory 200096 kb
Host smart-e173ea52-a4e5-452d-8dd1-471927843f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848332820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1848332820
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.4080007643
Short name T10
Test name
Test status
Simulation time 105910238 ps
CPU time 1.18 seconds
Started Jul 13 06:46:16 PM PDT 24
Finished Jul 13 06:46:20 PM PDT 24
Peak memory 200296 kb
Host smart-19a6a306-5192-4ce1-81f3-5032fbd72af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080007643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.4080007643
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.573412243
Short name T455
Test name
Test status
Simulation time 3286018966 ps
CPU time 11.28 seconds
Started Jul 13 06:46:21 PM PDT 24
Finished Jul 13 06:46:33 PM PDT 24
Peak memory 200492 kb
Host smart-9f5837bd-7ede-4bcd-b2bb-a3082ec235fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573412243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.573412243
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.4001421527
Short name T398
Test name
Test status
Simulation time 514458819 ps
CPU time 2.88 seconds
Started Jul 13 06:46:20 PM PDT 24
Finished Jul 13 06:46:23 PM PDT 24
Peak memory 200088 kb
Host smart-747fdd6d-f5c7-4dbf-b44f-a8ab4df2494c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001421527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4001421527
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.811274154
Short name T351
Test name
Test status
Simulation time 173611746 ps
CPU time 1.19 seconds
Started Jul 13 06:46:18 PM PDT 24
Finished Jul 13 06:46:21 PM PDT 24
Peak memory 200112 kb
Host smart-89ff348c-4e53-4cbd-ad0a-62158a63906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811274154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.811274154
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2004388173
Short name T289
Test name
Test status
Simulation time 75539405 ps
CPU time 0.77 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:16 PM PDT 24
Peak memory 199892 kb
Host smart-e8792fad-8908-4628-b8d4-7a56690cf3cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004388173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2004388173
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.777288355
Short name T392
Test name
Test status
Simulation time 1239532625 ps
CPU time 5.71 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:23 PM PDT 24
Peak memory 217764 kb
Host smart-2ccbe35a-b4de-4fad-b9d7-7babf57a935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777288355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.777288355
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1319201127
Short name T430
Test name
Test status
Simulation time 243862726 ps
CPU time 1.11 seconds
Started Jul 13 06:46:19 PM PDT 24
Finished Jul 13 06:46:21 PM PDT 24
Peak memory 217468 kb
Host smart-8420e295-afb6-49db-9ba0-2e6eb2b71560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319201127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1319201127
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.368098153
Short name T24
Test name
Test status
Simulation time 120943857 ps
CPU time 0.88 seconds
Started Jul 13 06:46:24 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 199916 kb
Host smart-091014a3-4d0c-4afa-8aa4-d2e4d792db91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368098153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.368098153
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2507833357
Short name T394
Test name
Test status
Simulation time 1738340251 ps
CPU time 7 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:25 PM PDT 24
Peak memory 200352 kb
Host smart-973b1a78-a97c-42fc-ae0a-0c01e2827f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507833357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2507833357
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1971701041
Short name T510
Test name
Test status
Simulation time 139655158 ps
CPU time 1.12 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 200076 kb
Host smart-9dade98b-1afe-4cb0-a248-34e4a52fc6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971701041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1971701041
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.24125260
Short name T221
Test name
Test status
Simulation time 239608443 ps
CPU time 1.68 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 200304 kb
Host smart-073294cc-4185-4805-8479-56f027ff61e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24125260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.24125260
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2286592813
Short name T47
Test name
Test status
Simulation time 1494497965 ps
CPU time 7.35 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:25 PM PDT 24
Peak memory 200376 kb
Host smart-c81572e3-7ad7-4536-a5fc-55a3b2b2ba46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286592813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2286592813
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.4030627922
Short name T412
Test name
Test status
Simulation time 342081171 ps
CPU time 2.16 seconds
Started Jul 13 06:46:19 PM PDT 24
Finished Jul 13 06:46:23 PM PDT 24
Peak memory 208284 kb
Host smart-22d21f8f-c25d-4232-804a-6fb9c59fb064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030627922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4030627922
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.4270966150
Short name T274
Test name
Test status
Simulation time 90994209 ps
CPU time 0.99 seconds
Started Jul 13 06:46:23 PM PDT 24
Finished Jul 13 06:46:24 PM PDT 24
Peak memory 200088 kb
Host smart-3ba60490-aee2-4a78-9509-c2b117dc4f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270966150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.4270966150
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3210536457
Short name T421
Test name
Test status
Simulation time 76530043 ps
CPU time 0.86 seconds
Started Jul 13 06:46:13 PM PDT 24
Finished Jul 13 06:46:16 PM PDT 24
Peak memory 199908 kb
Host smart-5b5dacb5-906e-4793-81ef-378804d0b494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210536457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3210536457
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2596670536
Short name T42
Test name
Test status
Simulation time 1219866790 ps
CPU time 5.75 seconds
Started Jul 13 06:46:13 PM PDT 24
Finished Jul 13 06:46:20 PM PDT 24
Peak memory 217688 kb
Host smart-d5138b28-733d-4421-80ca-f81803e5c2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596670536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2596670536
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.441430870
Short name T338
Test name
Test status
Simulation time 243534240 ps
CPU time 1.07 seconds
Started Jul 13 06:46:18 PM PDT 24
Finished Jul 13 06:46:21 PM PDT 24
Peak memory 217504 kb
Host smart-09c979a9-68ad-4aae-9034-e763a2f2b084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441430870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.441430870
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1837474084
Short name T476
Test name
Test status
Simulation time 192488639 ps
CPU time 0.92 seconds
Started Jul 13 06:46:17 PM PDT 24
Finished Jul 13 06:46:20 PM PDT 24
Peak memory 199944 kb
Host smart-82b72c82-2e2d-4a34-b13d-442994b29e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837474084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1837474084
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3235691562
Short name T182
Test name
Test status
Simulation time 692943550 ps
CPU time 3.73 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:20 PM PDT 24
Peak memory 200332 kb
Host smart-0713ab26-7bc4-4b9f-b15c-69892cb8255a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235691562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3235691562
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2579005528
Short name T410
Test name
Test status
Simulation time 172357983 ps
CPU time 1.26 seconds
Started Jul 13 06:46:16 PM PDT 24
Finished Jul 13 06:46:20 PM PDT 24
Peak memory 200096 kb
Host smart-e0371e4c-4ff1-43c4-a7a3-2de6e9c7c3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579005528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2579005528
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2279415636
Short name T525
Test name
Test status
Simulation time 249913576 ps
CPU time 1.57 seconds
Started Jul 13 06:46:22 PM PDT 24
Finished Jul 13 06:46:24 PM PDT 24
Peak memory 200288 kb
Host smart-e25ad298-6634-4c8a-b8d5-3846a02c75a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279415636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2279415636
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.526518471
Short name T171
Test name
Test status
Simulation time 8697931199 ps
CPU time 31.6 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:49 PM PDT 24
Peak memory 200728 kb
Host smart-93470145-bb96-47c1-b8d9-c24c88d3313a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526518471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.526518471
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.325906889
Short name T164
Test name
Test status
Simulation time 292413767 ps
CPU time 2.2 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:18 PM PDT 24
Peak memory 200120 kb
Host smart-4e2011b4-6db3-4d49-84b9-34844549bbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325906889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.325906889
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.108933838
Short name T332
Test name
Test status
Simulation time 153409300 ps
CPU time 1.25 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 200096 kb
Host smart-cd73d88e-db79-4f57-80d6-e31d9eb54219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108933838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.108933838
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3765892247
Short name T449
Test name
Test status
Simulation time 80492198 ps
CPU time 0.84 seconds
Started Jul 13 06:46:21 PM PDT 24
Finished Jul 13 06:46:23 PM PDT 24
Peak memory 199920 kb
Host smart-f18dc07e-1b71-48f0-9516-acb663bce857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765892247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3765892247
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2277272674
Short name T454
Test name
Test status
Simulation time 2158974401 ps
CPU time 8.23 seconds
Started Jul 13 06:46:16 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 217564 kb
Host smart-0b8b740a-2fcb-4236-a69e-af01a814c08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277272674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2277272674
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2479615405
Short name T186
Test name
Test status
Simulation time 245826590 ps
CPU time 1.02 seconds
Started Jul 13 06:46:16 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 217480 kb
Host smart-45c774ff-0aa0-44e5-a0aa-b7d1b90d50fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479615405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2479615405
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1025319677
Short name T402
Test name
Test status
Simulation time 107704788 ps
CPU time 0.8 seconds
Started Jul 13 06:46:16 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 199912 kb
Host smart-c309cbbe-28ff-49df-9d7c-549656af8ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025319677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1025319677
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.4264156146
Short name T297
Test name
Test status
Simulation time 986710857 ps
CPU time 4.59 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:22 PM PDT 24
Peak memory 200352 kb
Host smart-2a885ea2-451a-4ff5-99df-906ff4f72572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264156146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.4264156146
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1180277098
Short name T304
Test name
Test status
Simulation time 97277415 ps
CPU time 1 seconds
Started Jul 13 06:46:17 PM PDT 24
Finished Jul 13 06:46:20 PM PDT 24
Peak memory 200132 kb
Host smart-fb348203-9479-42d4-9e2b-0301d2f53197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180277098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1180277098
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.990561110
Short name T515
Test name
Test status
Simulation time 251498462 ps
CPU time 1.56 seconds
Started Jul 13 06:46:18 PM PDT 24
Finished Jul 13 06:46:21 PM PDT 24
Peak memory 200332 kb
Host smart-e44f3a90-b470-4f69-877c-f9f4dc795b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990561110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.990561110
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1838036983
Short name T346
Test name
Test status
Simulation time 2723353544 ps
CPU time 11.18 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:29 PM PDT 24
Peak memory 216772 kb
Host smart-8fe4c8bc-ca0e-4cf4-830b-38afbb867850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838036983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1838036983
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1767361157
Short name T255
Test name
Test status
Simulation time 124528181 ps
CPU time 1.59 seconds
Started Jul 13 06:46:21 PM PDT 24
Finished Jul 13 06:46:22 PM PDT 24
Peak memory 200092 kb
Host smart-e5ae6dcb-47a0-4739-b5cb-2c0f81bbde46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767361157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1767361157
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1048422570
Short name T300
Test name
Test status
Simulation time 141707797 ps
CPU time 1.2 seconds
Started Jul 13 06:46:16 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 200104 kb
Host smart-1f2be26c-1291-43e4-a87a-df247bcdeecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048422570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1048422570
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1525401171
Short name T144
Test name
Test status
Simulation time 63025484 ps
CPU time 0.74 seconds
Started Jul 13 06:46:16 PM PDT 24
Finished Jul 13 06:46:19 PM PDT 24
Peak memory 199856 kb
Host smart-76ae2df5-c6b7-483e-9a9e-7ccc1287efe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525401171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1525401171
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4276602412
Short name T38
Test name
Test status
Simulation time 1894427466 ps
CPU time 7.16 seconds
Started Jul 13 06:46:22 PM PDT 24
Finished Jul 13 06:46:30 PM PDT 24
Peak memory 221700 kb
Host smart-f8999215-87c4-4b3d-a8f7-074e3cddaff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276602412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4276602412
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1639152483
Short name T254
Test name
Test status
Simulation time 244323899 ps
CPU time 1.09 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:33 PM PDT 24
Peak memory 217484 kb
Host smart-92474dcd-8458-4ae7-bb9c-df222b799ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639152483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1639152483
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2002500256
Short name T19
Test name
Test status
Simulation time 215954335 ps
CPU time 0.89 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:17 PM PDT 24
Peak memory 199908 kb
Host smart-373209f1-081d-4420-b7c3-569e90055ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002500256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2002500256
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1732936865
Short name T479
Test name
Test status
Simulation time 1640916147 ps
CPU time 6.22 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:24 PM PDT 24
Peak memory 200436 kb
Host smart-130eac6a-f4d5-4c8a-93d2-1f5bbd95076e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732936865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1732936865
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3813339362
Short name T12
Test name
Test status
Simulation time 100234974 ps
CPU time 1.01 seconds
Started Jul 13 06:46:21 PM PDT 24
Finished Jul 13 06:46:23 PM PDT 24
Peak memory 200108 kb
Host smart-f2130c53-1e07-4292-8037-3c6051fbc415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813339362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3813339362
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2025802853
Short name T262
Test name
Test status
Simulation time 121123465 ps
CPU time 1.17 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:17 PM PDT 24
Peak memory 200328 kb
Host smart-03c2a69b-e46b-4e72-8374-6178bfc7567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025802853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2025802853
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3949125885
Short name T230
Test name
Test status
Simulation time 1887373362 ps
CPU time 9.02 seconds
Started Jul 13 06:46:15 PM PDT 24
Finished Jul 13 06:46:27 PM PDT 24
Peak memory 208544 kb
Host smart-5d359a8a-a4cc-40c3-8cd5-c1c4a0245438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949125885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3949125885
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3387660105
Short name T325
Test name
Test status
Simulation time 401542220 ps
CPU time 2.49 seconds
Started Jul 13 06:46:22 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 208284 kb
Host smart-e4c36672-ce89-4019-a238-21e11e0d8852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387660105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3387660105
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.868549402
Short name T345
Test name
Test status
Simulation time 177277992 ps
CPU time 1.16 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:17 PM PDT 24
Peak memory 200028 kb
Host smart-1bcb856f-8a52-4df1-8f47-c463a277df35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868549402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.868549402
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.4228799610
Short name T140
Test name
Test status
Simulation time 66124368 ps
CPU time 0.78 seconds
Started Jul 13 06:46:23 PM PDT 24
Finished Jul 13 06:46:24 PM PDT 24
Peak memory 199892 kb
Host smart-c3b3d0ce-5e49-4ebd-b8b2-0942ce736205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228799610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.4228799610
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4155289701
Short name T34
Test name
Test status
Simulation time 2158180216 ps
CPU time 7.54 seconds
Started Jul 13 06:46:16 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 217476 kb
Host smart-c5669f98-9c32-469a-a215-d9f0ae103034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155289701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4155289701
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.743926716
Short name T440
Test name
Test status
Simulation time 244077700 ps
CPU time 1.15 seconds
Started Jul 13 06:46:21 PM PDT 24
Finished Jul 13 06:46:23 PM PDT 24
Peak memory 217464 kb
Host smart-04473aaa-8604-4c50-8942-74ef80a727fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743926716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.743926716
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.4097083360
Short name T439
Test name
Test status
Simulation time 203902772 ps
CPU time 1 seconds
Started Jul 13 06:46:16 PM PDT 24
Finished Jul 13 06:46:20 PM PDT 24
Peak memory 199920 kb
Host smart-7ccdd6b7-978c-4bda-bb68-f48cec50953f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097083360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.4097083360
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3843893893
Short name T451
Test name
Test status
Simulation time 978077414 ps
CPU time 4.79 seconds
Started Jul 13 06:46:14 PM PDT 24
Finished Jul 13 06:46:21 PM PDT 24
Peak memory 200364 kb
Host smart-af0124eb-6308-4db9-8b39-916916570c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843893893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3843893893
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.503792533
Short name T190
Test name
Test status
Simulation time 187072349 ps
CPU time 1.14 seconds
Started Jul 13 06:46:19 PM PDT 24
Finished Jul 13 06:46:22 PM PDT 24
Peak memory 200324 kb
Host smart-ca4b3de1-dd27-4675-a30c-3204dfc13536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503792533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.503792533
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2811930736
Short name T417
Test name
Test status
Simulation time 125744646 ps
CPU time 1.18 seconds
Started Jul 13 06:46:21 PM PDT 24
Finished Jul 13 06:46:23 PM PDT 24
Peak memory 200288 kb
Host smart-ba86439b-f1f9-4aee-8573-f36e229d244e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811930736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2811930736
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2886405418
Short name T69
Test name
Test status
Simulation time 6659760638 ps
CPU time 27.59 seconds
Started Jul 13 06:46:17 PM PDT 24
Finished Jul 13 06:46:47 PM PDT 24
Peak memory 208708 kb
Host smart-d5b649e9-fa11-4395-a129-8633ee8c6a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886405418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2886405418
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3344607482
Short name T175
Test name
Test status
Simulation time 124368337 ps
CPU time 1.46 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 200328 kb
Host smart-e9d493fd-a79c-427f-95e6-75f3b35e2783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344607482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3344607482
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.857216248
Short name T456
Test name
Test status
Simulation time 67410639 ps
CPU time 0.81 seconds
Started Jul 13 06:46:18 PM PDT 24
Finished Jul 13 06:46:20 PM PDT 24
Peak memory 200076 kb
Host smart-480a5b2f-b67c-49fb-92e6-4c4bc2761192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857216248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.857216248
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3142893432
Short name T256
Test name
Test status
Simulation time 86444411 ps
CPU time 0.82 seconds
Started Jul 13 06:45:31 PM PDT 24
Finished Jul 13 06:45:34 PM PDT 24
Peak memory 199900 kb
Host smart-c04742cb-1d56-4565-bb3c-362e15cdcb34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142893432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3142893432
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1396312068
Short name T50
Test name
Test status
Simulation time 1230960751 ps
CPU time 5.98 seconds
Started Jul 13 06:45:33 PM PDT 24
Finished Jul 13 06:45:40 PM PDT 24
Peak memory 216896 kb
Host smart-15cd089c-0bed-4026-aa1a-da3cd6cf2e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396312068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1396312068
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3522259431
Short name T138
Test name
Test status
Simulation time 245410397 ps
CPU time 1.05 seconds
Started Jul 13 06:45:27 PM PDT 24
Finished Jul 13 06:45:30 PM PDT 24
Peak memory 217496 kb
Host smart-b87cc44d-708f-4bdd-ad05-614b4325f8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522259431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3522259431
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3798593613
Short name T22
Test name
Test status
Simulation time 131899807 ps
CPU time 0.8 seconds
Started Jul 13 06:45:27 PM PDT 24
Finished Jul 13 06:45:29 PM PDT 24
Peak memory 199912 kb
Host smart-098a1ced-8a43-4138-afb4-dec59e8e1c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798593613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3798593613
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.705884267
Short name T536
Test name
Test status
Simulation time 1516454424 ps
CPU time 5.84 seconds
Started Jul 13 06:45:27 PM PDT 24
Finished Jul 13 06:45:34 PM PDT 24
Peak memory 200332 kb
Host smart-25994424-700c-4abf-8dc3-2003b6e3af0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705884267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.705884267
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3271719152
Short name T83
Test name
Test status
Simulation time 8330507654 ps
CPU time 13.34 seconds
Started Jul 13 06:45:26 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 217148 kb
Host smart-1c23a1f0-85e0-4e80-9735-e2fa6be06ec5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271719152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3271719152
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3442771653
Short name T247
Test name
Test status
Simulation time 142778032 ps
CPU time 1.14 seconds
Started Jul 13 06:45:27 PM PDT 24
Finished Jul 13 06:45:30 PM PDT 24
Peak memory 200116 kb
Host smart-24ce20a5-e7db-412e-893c-a71c7d9289c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442771653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3442771653
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3189535650
Short name T29
Test name
Test status
Simulation time 200540038 ps
CPU time 1.4 seconds
Started Jul 13 06:45:23 PM PDT 24
Finished Jul 13 06:45:25 PM PDT 24
Peak memory 200284 kb
Host smart-39411e87-f4c0-430d-81ba-711f5ca18894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189535650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3189535650
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2190236167
Short name T294
Test name
Test status
Simulation time 2749628446 ps
CPU time 11.74 seconds
Started Jul 13 06:45:29 PM PDT 24
Finished Jul 13 06:45:43 PM PDT 24
Peak memory 210184 kb
Host smart-164ad5d5-656c-43c6-9f69-b98f1e146659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190236167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2190236167
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2011170110
Short name T87
Test name
Test status
Simulation time 358365136 ps
CPU time 2.36 seconds
Started Jul 13 06:45:27 PM PDT 24
Finished Jul 13 06:45:30 PM PDT 24
Peak memory 200124 kb
Host smart-778c0791-96c8-4b73-8764-0e6fda2854ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011170110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2011170110
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2892001569
Short name T26
Test name
Test status
Simulation time 195942917 ps
CPU time 1.23 seconds
Started Jul 13 06:45:31 PM PDT 24
Finished Jul 13 06:45:34 PM PDT 24
Peak memory 200088 kb
Host smart-b26e7a05-aab4-4eb9-a959-0450ab5e4d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892001569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2892001569
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1213490786
Short name T475
Test name
Test status
Simulation time 63245037 ps
CPU time 0.73 seconds
Started Jul 13 06:46:29 PM PDT 24
Finished Jul 13 06:46:33 PM PDT 24
Peak memory 199776 kb
Host smart-1c044714-f22c-4d51-85ee-a5ed82f271e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213490786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1213490786
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.356121185
Short name T390
Test name
Test status
Simulation time 1235239581 ps
CPU time 5.55 seconds
Started Jul 13 06:46:24 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 216856 kb
Host smart-3950ce13-66ff-430e-901d-e98aaa1d7221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356121185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.356121185
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.194803190
Short name T228
Test name
Test status
Simulation time 244363639 ps
CPU time 1.06 seconds
Started Jul 13 06:46:24 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 217360 kb
Host smart-e9a79b52-0103-45e9-9179-cf59d4e1567c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194803190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.194803190
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3340075121
Short name T202
Test name
Test status
Simulation time 162233350 ps
CPU time 0.84 seconds
Started Jul 13 06:46:30 PM PDT 24
Finished Jul 13 06:46:33 PM PDT 24
Peak memory 199700 kb
Host smart-a84e13f3-8970-4cea-918c-c72519f215f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340075121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3340075121
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3919294772
Short name T159
Test name
Test status
Simulation time 1566244355 ps
CPU time 6.87 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:38 PM PDT 24
Peak memory 200448 kb
Host smart-b4a389b2-7ef5-45d6-8cad-e1d4451103f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919294772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3919294772
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1651098936
Short name T538
Test name
Test status
Simulation time 105582931 ps
CPU time 1.02 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:29 PM PDT 24
Peak memory 200116 kb
Host smart-30ce15be-a005-4c0b-a96f-c4a003bf366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651098936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1651098936
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.969859888
Short name T279
Test name
Test status
Simulation time 194566959 ps
CPU time 1.46 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:29 PM PDT 24
Peak memory 200308 kb
Host smart-5049cf9b-dbbd-4e20-a5e0-d5078a0e3b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969859888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.969859888
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.856801172
Short name T162
Test name
Test status
Simulation time 2750345599 ps
CPU time 12.65 seconds
Started Jul 13 06:46:24 PM PDT 24
Finished Jul 13 06:46:39 PM PDT 24
Peak memory 200440 kb
Host smart-c942da8e-c120-4763-ac8d-f8756dcfc00a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856801172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.856801172
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.995474017
Short name T143
Test name
Test status
Simulation time 144070579 ps
CPU time 1.92 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 200120 kb
Host smart-2ffbc054-8634-447d-92fe-7a3791c7881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995474017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.995474017
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.4059608632
Short name T257
Test name
Test status
Simulation time 85649762 ps
CPU time 0.89 seconds
Started Jul 13 06:46:24 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 200100 kb
Host smart-c6e2fb33-2746-4bb5-bd9d-2528d43d14bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059608632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.4059608632
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.638072699
Short name T490
Test name
Test status
Simulation time 57318817 ps
CPU time 0.74 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 199936 kb
Host smart-0cf85c22-ddff-4119-b43e-99a69740a9ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638072699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.638072699
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1985275253
Short name T446
Test name
Test status
Simulation time 1894958480 ps
CPU time 7.46 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:39 PM PDT 24
Peak memory 217716 kb
Host smart-b5d6d050-d635-4235-8cd7-42521bb7c384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985275253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1985275253
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2111275195
Short name T224
Test name
Test status
Simulation time 244910647 ps
CPU time 1.09 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 217392 kb
Host smart-c1fe4003-c589-455c-8f09-573fcb423bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111275195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2111275195
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3017348474
Short name T329
Test name
Test status
Simulation time 75071792 ps
CPU time 0.71 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 199920 kb
Host smart-4b43d3d0-84ab-4dfe-9bb0-8251e5e1a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017348474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3017348474
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.4086854600
Short name T299
Test name
Test status
Simulation time 1134954578 ps
CPU time 4.81 seconds
Started Jul 13 06:46:24 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 200348 kb
Host smart-d9dafaf3-b45d-44c1-81d9-9ebc655fb1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086854600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.4086854600
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2723190711
Short name T305
Test name
Test status
Simulation time 161947279 ps
CPU time 1.15 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:29 PM PDT 24
Peak memory 200116 kb
Host smart-ee113852-ce32-4b50-8eac-1e51a2e4a874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723190711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2723190711
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1132847847
Short name T488
Test name
Test status
Simulation time 225243550 ps
CPU time 1.43 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:29 PM PDT 24
Peak memory 200312 kb
Host smart-f4903f5b-108d-4ece-b3b7-73383d3deab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132847847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1132847847
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3089211570
Short name T285
Test name
Test status
Simulation time 8109722645 ps
CPU time 28.83 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:58 PM PDT 24
Peak memory 200436 kb
Host smart-b930f02b-d23a-4fa8-8d52-8dfef0f607a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089211570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3089211570
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.356326788
Short name T497
Test name
Test status
Simulation time 133703983 ps
CPU time 1.6 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 208380 kb
Host smart-8000c239-cead-46c4-a451-a8db6d79a5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356326788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.356326788
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2348996562
Short name T352
Test name
Test status
Simulation time 115906579 ps
CPU time 1.04 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:28 PM PDT 24
Peak memory 200132 kb
Host smart-d561ac9d-0e5d-4eaa-bf21-1f02f8dbafa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348996562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2348996562
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1813221932
Short name T185
Test name
Test status
Simulation time 60576078 ps
CPU time 0.72 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 199900 kb
Host smart-02139774-239a-424d-9ad7-67113b770c42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813221932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1813221932
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2309187947
Short name T65
Test name
Test status
Simulation time 1899413290 ps
CPU time 7.06 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:37 PM PDT 24
Peak memory 217504 kb
Host smart-fe46c58d-805a-42ab-9ccc-d24f9a86b1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309187947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2309187947
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2203630873
Short name T353
Test name
Test status
Simulation time 244615999 ps
CPU time 1.21 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 217436 kb
Host smart-1971bea1-68c9-4373-a9d6-cb2235b48ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203630873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2203630873
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3014479986
Short name T478
Test name
Test status
Simulation time 88202368 ps
CPU time 0.72 seconds
Started Jul 13 06:46:23 PM PDT 24
Finished Jul 13 06:46:24 PM PDT 24
Peak memory 199908 kb
Host smart-fca782e0-1ee1-481e-9023-8c0ddf40741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014479986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3014479986
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1057189364
Short name T378
Test name
Test status
Simulation time 1206873102 ps
CPU time 4.94 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:35 PM PDT 24
Peak memory 200380 kb
Host smart-820262bc-9cf8-4406-aa3a-085a52922e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057189364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1057189364
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2769057161
Short name T453
Test name
Test status
Simulation time 155989706 ps
CPU time 1.1 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:29 PM PDT 24
Peak memory 200048 kb
Host smart-4269af48-6be7-4ed0-977c-fcba69b68d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769057161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2769057161
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1114109892
Short name T361
Test name
Test status
Simulation time 199855943 ps
CPU time 1.39 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:29 PM PDT 24
Peak memory 200296 kb
Host smart-b694da0e-1c3d-4c56-b83a-d7a1c29ab35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114109892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1114109892
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2070449800
Short name T512
Test name
Test status
Simulation time 6173863922 ps
CPU time 20.88 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:48 PM PDT 24
Peak memory 210336 kb
Host smart-65852ae1-e99a-4844-bab1-e4cfe52becef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070449800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2070449800
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3419976273
Short name T539
Test name
Test status
Simulation time 325493372 ps
CPU time 2.03 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:29 PM PDT 24
Peak memory 200100 kb
Host smart-c1f6bf6e-6edb-4c09-8621-62427136a207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419976273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3419976273
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1765481540
Short name T462
Test name
Test status
Simulation time 97488752 ps
CPU time 0.87 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 200128 kb
Host smart-7c03b7c2-9676-42f2-8126-0500964c4a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765481540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1765481540
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2528062331
Short name T5
Test name
Test status
Simulation time 68865599 ps
CPU time 0.74 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 199900 kb
Host smart-68326b08-e474-4dc1-996a-3e0be4595d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528062331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2528062331
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3539586220
Short name T432
Test name
Test status
Simulation time 1224291414 ps
CPU time 5.74 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:34 PM PDT 24
Peak memory 221716 kb
Host smart-61042743-9e73-405f-8274-ed81efb6ff72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539586220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3539586220
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1233535810
Short name T214
Test name
Test status
Simulation time 243659691 ps
CPU time 1.19 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 217484 kb
Host smart-9081c970-b806-4355-bdfc-6205f7eefb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233535810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1233535810
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1467427724
Short name T15
Test name
Test status
Simulation time 142625202 ps
CPU time 0.87 seconds
Started Jul 13 06:46:24 PM PDT 24
Finished Jul 13 06:46:27 PM PDT 24
Peak memory 199908 kb
Host smart-1ab1eaf7-f74d-4615-aeac-61b36f3bdef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467427724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1467427724
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.98649859
Short name T395
Test name
Test status
Simulation time 2287248159 ps
CPU time 7.82 seconds
Started Jul 13 06:46:29 PM PDT 24
Finished Jul 13 06:46:40 PM PDT 24
Peak memory 200656 kb
Host smart-ab5ca57f-ab96-4ff1-80c7-5c1156ccf5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98649859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.98649859
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1504814646
Short name T212
Test name
Test status
Simulation time 106316068 ps
CPU time 1.01 seconds
Started Jul 13 06:46:24 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 200076 kb
Host smart-feec0f13-02bf-424f-9e96-c9a318508e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504814646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1504814646
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3525717997
Short name T149
Test name
Test status
Simulation time 123829439 ps
CPU time 1.23 seconds
Started Jul 13 06:46:30 PM PDT 24
Finished Jul 13 06:46:33 PM PDT 24
Peak memory 200212 kb
Host smart-5ace415f-123d-4cab-bb60-8d9ae4128a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525717997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3525717997
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2565109693
Short name T104
Test name
Test status
Simulation time 9784318296 ps
CPU time 36.49 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:47:07 PM PDT 24
Peak memory 208612 kb
Host smart-2330f7f0-9918-47b9-84ec-ec73bddb0dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565109693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2565109693
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1745151290
Short name T150
Test name
Test status
Simulation time 308916741 ps
CPU time 2.04 seconds
Started Jul 13 06:46:23 PM PDT 24
Finished Jul 13 06:46:25 PM PDT 24
Peak memory 208288 kb
Host smart-c581ee73-f69c-428a-97f6-fa20f4d94bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745151290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1745151290
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3599993254
Short name T201
Test name
Test status
Simulation time 120781784 ps
CPU time 1.14 seconds
Started Jul 13 06:46:30 PM PDT 24
Finished Jul 13 06:46:33 PM PDT 24
Peak memory 200316 kb
Host smart-9aea98cd-db2c-421d-aca0-88ed83c51cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599993254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3599993254
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3590221289
Short name T461
Test name
Test status
Simulation time 69077257 ps
CPU time 0.76 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 199904 kb
Host smart-1efbf20f-a106-4aac-be56-bfc885a7852d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590221289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3590221289
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2069431553
Short name T436
Test name
Test status
Simulation time 1226584261 ps
CPU time 6.06 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:36 PM PDT 24
Peak memory 217256 kb
Host smart-1a2765ce-1c18-4b93-89c6-678f4a15eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069431553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2069431553
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2001936168
Short name T243
Test name
Test status
Simulation time 244693361 ps
CPU time 1.09 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 217348 kb
Host smart-83ee0d0f-5dde-401b-aab6-ac60b3dbe1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001936168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2001936168
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3856196893
Short name T424
Test name
Test status
Simulation time 134022011 ps
CPU time 0.85 seconds
Started Jul 13 06:46:24 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 199864 kb
Host smart-fdce62fc-98fe-4f90-a49e-5de79dce5b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856196893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3856196893
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2880583368
Short name T505
Test name
Test status
Simulation time 792322229 ps
CPU time 4.07 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:34 PM PDT 24
Peak memory 200388 kb
Host smart-8d2b3069-90f6-4890-8de4-513bec532da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880583368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2880583368
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1038821004
Short name T261
Test name
Test status
Simulation time 188623680 ps
CPU time 1.28 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 200108 kb
Host smart-598667b1-d225-4db7-957d-19919a4558c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038821004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1038821004
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2435349210
Short name T391
Test name
Test status
Simulation time 235160112 ps
CPU time 1.63 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 200132 kb
Host smart-cfcbd43a-8e2e-4fa1-9dbe-77aabeac8eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435349210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2435349210
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.868039665
Short name T245
Test name
Test status
Simulation time 4945196028 ps
CPU time 23.15 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:53 PM PDT 24
Peak memory 208460 kb
Host smart-04a4ed17-23b7-480a-98fd-bf5bc89072ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868039665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.868039665
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1231729115
Short name T288
Test name
Test status
Simulation time 267066066 ps
CPU time 1.91 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 200128 kb
Host smart-79175722-868a-474e-b764-3bf18ad7e676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231729115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1231729115
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.215357131
Short name T524
Test name
Test status
Simulation time 142696028 ps
CPU time 1.16 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:29 PM PDT 24
Peak memory 200120 kb
Host smart-ae9e793c-32e9-413d-bf8c-8a1e654cafe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215357131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.215357131
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.284250243
Short name T147
Test name
Test status
Simulation time 72830998 ps
CPU time 0.83 seconds
Started Jul 13 06:46:34 PM PDT 24
Finished Jul 13 06:46:35 PM PDT 24
Peak memory 199896 kb
Host smart-2b02872c-fde7-4845-86c7-d7a20f542087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284250243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.284250243
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1607492522
Short name T58
Test name
Test status
Simulation time 2179721162 ps
CPU time 8.07 seconds
Started Jul 13 06:46:29 PM PDT 24
Finished Jul 13 06:46:40 PM PDT 24
Peak memory 217616 kb
Host smart-9a46a0e4-6225-4394-94a6-52a24b5ad57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607492522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1607492522
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2874110019
Short name T506
Test name
Test status
Simulation time 244858908 ps
CPU time 1.14 seconds
Started Jul 13 06:46:33 PM PDT 24
Finished Jul 13 06:46:35 PM PDT 24
Peak memory 217468 kb
Host smart-35cd226f-145f-40b1-ad80-b71cdf0cc231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874110019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2874110019
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.4012129905
Short name T370
Test name
Test status
Simulation time 144700010 ps
CPU time 0.87 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:30 PM PDT 24
Peak memory 199924 kb
Host smart-60e878d0-e412-46f6-be53-f3729ed2cf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012129905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.4012129905
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3841955673
Short name T251
Test name
Test status
Simulation time 1598044439 ps
CPU time 6.25 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:36 PM PDT 24
Peak memory 200244 kb
Host smart-801f9e0c-e541-4701-8bd8-f00715ab7019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841955673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3841955673
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1159850582
Short name T457
Test name
Test status
Simulation time 150956059 ps
CPU time 1.12 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 199464 kb
Host smart-d9ba2125-d50d-4cdc-b1c1-14ad4b421da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159850582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1159850582
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.639549032
Short name T400
Test name
Test status
Simulation time 189449617 ps
CPU time 1.37 seconds
Started Jul 13 06:46:30 PM PDT 24
Finished Jul 13 06:46:33 PM PDT 24
Peak memory 200520 kb
Host smart-2752d0f2-3d5e-4647-a453-d2f34693cf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639549032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.639549032
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1574163148
Short name T420
Test name
Test status
Simulation time 7851513395 ps
CPU time 32.91 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:47:03 PM PDT 24
Peak memory 200440 kb
Host smart-937503a3-321d-4b86-8498-b16405a6237c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574163148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1574163148
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2043582065
Short name T129
Test name
Test status
Simulation time 345859205 ps
CPU time 1.92 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 200120 kb
Host smart-d1c6f760-bb6e-4fa7-9d79-e4b3442d0d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043582065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2043582065
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.4231128485
Short name T216
Test name
Test status
Simulation time 125120688 ps
CPU time 0.97 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:30 PM PDT 24
Peak memory 200084 kb
Host smart-1a9fd694-ce19-47e8-a344-83b9bdc22d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231128485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.4231128485
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2064487948
Short name T298
Test name
Test status
Simulation time 61949103 ps
CPU time 0.74 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 199920 kb
Host smart-337cd197-a1a1-49ec-aa83-277c60146cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064487948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2064487948
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3851041776
Short name T528
Test name
Test status
Simulation time 1231917212 ps
CPU time 5.53 seconds
Started Jul 13 06:46:34 PM PDT 24
Finished Jul 13 06:46:40 PM PDT 24
Peak memory 217388 kb
Host smart-37c03a95-92a5-4417-b85a-ce3f3309be8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851041776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3851041776
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2022678773
Short name T258
Test name
Test status
Simulation time 244333975 ps
CPU time 1.08 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 217492 kb
Host smart-66119943-a535-471d-8d2d-26016d67fd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022678773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2022678773
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2657296836
Short name T357
Test name
Test status
Simulation time 177948301 ps
CPU time 0.87 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 199888 kb
Host smart-a5c45b39-f552-4829-bfbc-37f24e691108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657296836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2657296836
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3060565171
Short name T371
Test name
Test status
Simulation time 1727287342 ps
CPU time 7.26 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:37 PM PDT 24
Peak memory 200376 kb
Host smart-5b8f5116-19eb-4993-91f2-1a84e6df55a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060565171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3060565171
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.4087876251
Short name T339
Test name
Test status
Simulation time 139991316 ps
CPU time 1.12 seconds
Started Jul 13 06:46:33 PM PDT 24
Finished Jul 13 06:46:34 PM PDT 24
Peak memory 200092 kb
Host smart-56cc8d66-2aca-4556-992f-6f1cecccf08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087876251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.4087876251
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3770431258
Short name T464
Test name
Test status
Simulation time 251069527 ps
CPU time 1.53 seconds
Started Jul 13 06:46:34 PM PDT 24
Finished Jul 13 06:46:36 PM PDT 24
Peak memory 200320 kb
Host smart-c4b3c130-e3f3-4ee3-8926-f15c3862d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770431258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3770431258
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2531480101
Short name T335
Test name
Test status
Simulation time 12643664961 ps
CPU time 41.96 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:47:12 PM PDT 24
Peak memory 208612 kb
Host smart-2b6027e0-dcbd-4a9f-8031-c68ecba552fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531480101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2531480101
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2038937562
Short name T311
Test name
Test status
Simulation time 436528485 ps
CPU time 2.36 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 200100 kb
Host smart-c0cdc367-bfea-4de5-950a-3cbf1c4144c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038937562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2038937562
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.379862719
Short name T249
Test name
Test status
Simulation time 58609163 ps
CPU time 0.76 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 200076 kb
Host smart-804a44ef-62d5-471a-8251-1d039d7c084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379862719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.379862719
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3724863094
Short name T413
Test name
Test status
Simulation time 74610882 ps
CPU time 0.8 seconds
Started Jul 13 06:46:43 PM PDT 24
Finished Jul 13 06:46:45 PM PDT 24
Peak memory 199840 kb
Host smart-e14f2a52-f982-4c09-b019-f913ce28c875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724863094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3724863094
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.4089686486
Short name T318
Test name
Test status
Simulation time 2355302619 ps
CPU time 7.86 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:37 PM PDT 24
Peak memory 217740 kb
Host smart-a3693ee4-506d-4a1c-8db5-9396b9ef066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089686486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.4089686486
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2528637728
Short name T179
Test name
Test status
Simulation time 246042460 ps
CPU time 1.16 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 217524 kb
Host smart-b0e93b37-ce90-4075-af9c-2c0d721853ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528637728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2528637728
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3641727616
Short name T409
Test name
Test status
Simulation time 146065139 ps
CPU time 0.89 seconds
Started Jul 13 06:46:30 PM PDT 24
Finished Jul 13 06:46:33 PM PDT 24
Peak memory 199900 kb
Host smart-64cff9e0-f246-4a70-8775-7e11347f6961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641727616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3641727616
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2706790452
Short name T273
Test name
Test status
Simulation time 1099792673 ps
CPU time 4.88 seconds
Started Jul 13 06:46:25 PM PDT 24
Finished Jul 13 06:46:33 PM PDT 24
Peak memory 200376 kb
Host smart-64fd452b-60b5-4585-9fe9-1489a42849fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706790452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2706790452
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1322728318
Short name T474
Test name
Test status
Simulation time 178328126 ps
CPU time 1.22 seconds
Started Jul 13 06:46:26 PM PDT 24
Finished Jul 13 06:46:31 PM PDT 24
Peak memory 200112 kb
Host smart-4921ebae-5bdf-4d01-8cd8-820d1f029ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322728318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1322728318
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3297999788
Short name T151
Test name
Test status
Simulation time 201119325 ps
CPU time 1.35 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:33 PM PDT 24
Peak memory 200252 kb
Host smart-0ff53427-b43d-4227-823b-b84e83b23067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297999788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3297999788
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2279408737
Short name T428
Test name
Test status
Simulation time 7292630242 ps
CPU time 25.89 seconds
Started Jul 13 06:46:28 PM PDT 24
Finished Jul 13 06:46:58 PM PDT 24
Peak memory 200512 kb
Host smart-f8910b29-26fd-49de-a2ff-38ac6b7007c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279408737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2279408737
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.873658661
Short name T386
Test name
Test status
Simulation time 512862311 ps
CPU time 3.01 seconds
Started Jul 13 06:46:30 PM PDT 24
Finished Jul 13 06:46:35 PM PDT 24
Peak memory 200120 kb
Host smart-56dd6991-37e1-4482-8bcd-ff1937932cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873658661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.873658661
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1788916423
Short name T330
Test name
Test status
Simulation time 112696179 ps
CPU time 1.02 seconds
Started Jul 13 06:46:27 PM PDT 24
Finished Jul 13 06:46:32 PM PDT 24
Peak memory 200024 kb
Host smart-545bad2b-1e50-44d8-9389-3a3cf2ff37ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788916423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1788916423
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.178847284
Short name T520
Test name
Test status
Simulation time 63373594 ps
CPU time 0.76 seconds
Started Jul 13 06:46:36 PM PDT 24
Finished Jul 13 06:46:38 PM PDT 24
Peak memory 199884 kb
Host smart-fe9a1d85-a73f-4cf7-bf43-bf7f8cd8ff33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178847284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.178847284
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.263016301
Short name T8
Test name
Test status
Simulation time 245206983 ps
CPU time 1.15 seconds
Started Jul 13 06:46:41 PM PDT 24
Finished Jul 13 06:46:43 PM PDT 24
Peak memory 217424 kb
Host smart-8edc9ed3-e5cc-4a35-98c3-e2cebdadfb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263016301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.263016301
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2729665431
Short name T406
Test name
Test status
Simulation time 92826986 ps
CPU time 0.8 seconds
Started Jul 13 06:46:39 PM PDT 24
Finished Jul 13 06:46:41 PM PDT 24
Peak memory 199916 kb
Host smart-625f1058-33c7-4df8-9f5d-5207e2808abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729665431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2729665431
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1185671800
Short name T423
Test name
Test status
Simulation time 1398168239 ps
CPU time 5.44 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:46:47 PM PDT 24
Peak memory 200420 kb
Host smart-e3e3b1c2-f098-4afe-89d2-3a4cca4a6e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185671800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1185671800
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.451581019
Short name T422
Test name
Test status
Simulation time 142366815 ps
CPU time 1.14 seconds
Started Jul 13 06:46:43 PM PDT 24
Finished Jul 13 06:46:45 PM PDT 24
Peak memory 200112 kb
Host smart-88850109-1d1a-48c2-8ffc-1db5a4e86ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451581019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.451581019
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3833356914
Short name T184
Test name
Test status
Simulation time 204735185 ps
CPU time 1.48 seconds
Started Jul 13 06:46:36 PM PDT 24
Finished Jul 13 06:46:38 PM PDT 24
Peak memory 200312 kb
Host smart-e79afdd5-0d5e-4176-b8e7-8803e7ee6ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833356914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3833356914
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1627003618
Short name T128
Test name
Test status
Simulation time 12898183536 ps
CPU time 46.93 seconds
Started Jul 13 06:46:43 PM PDT 24
Finished Jul 13 06:47:31 PM PDT 24
Peak memory 208640 kb
Host smart-89706969-50e0-453a-aa3e-c6086d4910d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627003618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1627003618
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1433884660
Short name T337
Test name
Test status
Simulation time 493495705 ps
CPU time 2.96 seconds
Started Jul 13 06:46:38 PM PDT 24
Finished Jul 13 06:46:42 PM PDT 24
Peak memory 200120 kb
Host smart-7962db5f-edc5-4906-87b7-c1491b4e4f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433884660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1433884660
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.358583010
Short name T88
Test name
Test status
Simulation time 139022413 ps
CPU time 1.05 seconds
Started Jul 13 06:46:38 PM PDT 24
Finished Jul 13 06:46:40 PM PDT 24
Peak memory 200096 kb
Host smart-b0f5d483-1104-4f6d-ba30-ca09db46872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358583010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.358583010
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2313177902
Short name T237
Test name
Test status
Simulation time 74861613 ps
CPU time 0.84 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:46:42 PM PDT 24
Peak memory 199888 kb
Host smart-55b997d8-0143-4ee4-983a-225b423f8853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313177902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2313177902
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3644062918
Short name T499
Test name
Test status
Simulation time 1234334763 ps
CPU time 5.36 seconds
Started Jul 13 06:46:38 PM PDT 24
Finished Jul 13 06:46:44 PM PDT 24
Peak memory 217700 kb
Host smart-fd6a8d74-63cd-4348-9199-f011050b33f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644062918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3644062918
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2748201439
Short name T238
Test name
Test status
Simulation time 247857472 ps
CPU time 1.05 seconds
Started Jul 13 06:46:38 PM PDT 24
Finished Jul 13 06:46:39 PM PDT 24
Peak memory 217484 kb
Host smart-32ff01e2-52b4-47ff-bea3-2b0c1b58e3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748201439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2748201439
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1873341539
Short name T333
Test name
Test status
Simulation time 198858769 ps
CPU time 0.87 seconds
Started Jul 13 06:46:44 PM PDT 24
Finished Jul 13 06:46:46 PM PDT 24
Peak memory 199900 kb
Host smart-6bebf198-d288-4742-9dd2-e5108604fbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873341539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1873341539
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2014714004
Short name T349
Test name
Test status
Simulation time 819954936 ps
CPU time 3.8 seconds
Started Jul 13 06:46:37 PM PDT 24
Finished Jul 13 06:46:41 PM PDT 24
Peak memory 200360 kb
Host smart-5ea7c167-2487-43df-b7d1-ffcfd79841ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014714004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2014714004
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1875781090
Short name T206
Test name
Test status
Simulation time 141288563 ps
CPU time 1.1 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:46:42 PM PDT 24
Peak memory 200096 kb
Host smart-baa94a60-ba4b-48b2-b592-dfe44e93fe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875781090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1875781090
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2215650658
Short name T327
Test name
Test status
Simulation time 192024415 ps
CPU time 1.38 seconds
Started Jul 13 06:46:37 PM PDT 24
Finished Jul 13 06:46:39 PM PDT 24
Peak memory 200256 kb
Host smart-d33c8007-4c0f-4df0-9eaf-a095e188776d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215650658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2215650658
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.323497213
Short name T290
Test name
Test status
Simulation time 362949789 ps
CPU time 2.66 seconds
Started Jul 13 06:46:38 PM PDT 24
Finished Jul 13 06:46:41 PM PDT 24
Peak memory 200092 kb
Host smart-fe7266b5-b822-437b-b695-d59bce80ffa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323497213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.323497213
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1594432557
Short name T385
Test name
Test status
Simulation time 92484977 ps
CPU time 0.89 seconds
Started Jul 13 06:46:46 PM PDT 24
Finished Jul 13 06:46:47 PM PDT 24
Peak memory 200088 kb
Host smart-91d87330-705e-454e-a77d-766e5f37d9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594432557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1594432557
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3113147806
Short name T518
Test name
Test status
Simulation time 75036630 ps
CPU time 0.85 seconds
Started Jul 13 06:45:30 PM PDT 24
Finished Jul 13 06:45:32 PM PDT 24
Peak memory 199920 kb
Host smart-270e15a9-e8d3-4d83-8a99-95efb88cbcbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113147806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3113147806
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2961356792
Short name T57
Test name
Test status
Simulation time 1226119696 ps
CPU time 5.62 seconds
Started Jul 13 06:45:29 PM PDT 24
Finished Jul 13 06:45:37 PM PDT 24
Peak memory 221924 kb
Host smart-c8776d86-7a9d-4829-bcb2-8b9c92eb0a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961356792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2961356792
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2291643779
Short name T407
Test name
Test status
Simulation time 244167666 ps
CPU time 1.07 seconds
Started Jul 13 06:45:26 PM PDT 24
Finished Jul 13 06:45:28 PM PDT 24
Peak memory 217452 kb
Host smart-42278608-43ad-421b-ac9d-0e87ceccdcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291643779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2291643779
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.777694860
Short name T354
Test name
Test status
Simulation time 199951566 ps
CPU time 0.87 seconds
Started Jul 13 06:45:26 PM PDT 24
Finished Jul 13 06:45:28 PM PDT 24
Peak memory 199904 kb
Host smart-e5b9bb7d-45a6-47cc-83cd-52907c623797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777694860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.777694860
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1689160689
Short name T200
Test name
Test status
Simulation time 804626800 ps
CPU time 4.44 seconds
Started Jul 13 06:45:30 PM PDT 24
Finished Jul 13 06:45:36 PM PDT 24
Peak memory 200404 kb
Host smart-4d0ca208-4c07-4732-a37e-290faaf4a6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689160689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1689160689
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2041229716
Short name T382
Test name
Test status
Simulation time 167620224 ps
CPU time 1.26 seconds
Started Jul 13 06:45:28 PM PDT 24
Finished Jul 13 06:45:32 PM PDT 24
Peak memory 200116 kb
Host smart-70954d7c-f4e0-49b0-b5c7-4d48d3c70414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041229716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2041229716
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3985252830
Short name T188
Test name
Test status
Simulation time 243033302 ps
CPU time 1.47 seconds
Started Jul 13 06:45:30 PM PDT 24
Finished Jul 13 06:45:33 PM PDT 24
Peak memory 200524 kb
Host smart-93436900-2bf6-43fd-a470-a9e22e62a441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985252830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3985252830
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.242825952
Short name T44
Test name
Test status
Simulation time 2440925574 ps
CPU time 8.19 seconds
Started Jul 13 06:45:26 PM PDT 24
Finished Jul 13 06:45:36 PM PDT 24
Peak memory 208608 kb
Host smart-9911c70e-7d25-4324-ba58-2c1099a03db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242825952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.242825952
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.834589719
Short name T314
Test name
Test status
Simulation time 107071429 ps
CPU time 1.47 seconds
Started Jul 13 06:45:26 PM PDT 24
Finished Jul 13 06:45:29 PM PDT 24
Peak memory 200024 kb
Host smart-8cb4fc2f-fb4d-4764-b64d-eb12084e1acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834589719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.834589719
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.480230314
Short name T359
Test name
Test status
Simulation time 75406733 ps
CPU time 0.84 seconds
Started Jul 13 06:45:25 PM PDT 24
Finished Jul 13 06:45:27 PM PDT 24
Peak memory 200100 kb
Host smart-b71abf41-256f-407e-a8f1-2df3173dc982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480230314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.480230314
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.310750124
Short name T427
Test name
Test status
Simulation time 80943213 ps
CPU time 0.78 seconds
Started Jul 13 06:45:28 PM PDT 24
Finished Jul 13 06:45:30 PM PDT 24
Peak memory 199880 kb
Host smart-535d4473-8595-410b-a54c-3b8f4c8ba0c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310750124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.310750124
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3604414389
Short name T41
Test name
Test status
Simulation time 1229828020 ps
CPU time 5.5 seconds
Started Jul 13 06:45:27 PM PDT 24
Finished Jul 13 06:45:34 PM PDT 24
Peak memory 217804 kb
Host smart-b76642f2-ba36-4243-83bf-fe4a51003077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604414389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3604414389
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1399293432
Short name T500
Test name
Test status
Simulation time 244998765 ps
CPU time 1.04 seconds
Started Jul 13 06:45:27 PM PDT 24
Finished Jul 13 06:45:30 PM PDT 24
Peak memory 217472 kb
Host smart-6fde2218-2e49-4308-bdba-7bf908ba7436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399293432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1399293432
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1203619932
Short name T20
Test name
Test status
Simulation time 88075693 ps
CPU time 0.76 seconds
Started Jul 13 06:45:28 PM PDT 24
Finished Jul 13 06:45:31 PM PDT 24
Peak memory 199920 kb
Host smart-835beaf0-d1a1-412e-a4b5-63a8a18476da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203619932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1203619932
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2648064814
Short name T127
Test name
Test status
Simulation time 1905340497 ps
CPU time 6.61 seconds
Started Jul 13 06:45:27 PM PDT 24
Finished Jul 13 06:45:35 PM PDT 24
Peak memory 200436 kb
Host smart-d319f3dc-5037-458e-bc94-4c7ff2dcd528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648064814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2648064814
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.4053414208
Short name T316
Test name
Test status
Simulation time 113445826 ps
CPU time 1.03 seconds
Started Jul 13 06:45:28 PM PDT 24
Finished Jul 13 06:45:31 PM PDT 24
Peak memory 200028 kb
Host smart-533f8acb-227e-4690-b460-a6409e904294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053414208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.4053414208
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2550388976
Short name T403
Test name
Test status
Simulation time 246233640 ps
CPU time 1.65 seconds
Started Jul 13 06:45:32 PM PDT 24
Finished Jul 13 06:45:35 PM PDT 24
Peak memory 200324 kb
Host smart-54467ca9-1c04-48fe-93ca-a6c9ad3d4a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550388976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2550388976
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.716196267
Short name T25
Test name
Test status
Simulation time 5466525870 ps
CPU time 21.18 seconds
Started Jul 13 06:45:33 PM PDT 24
Finished Jul 13 06:45:55 PM PDT 24
Peak memory 200404 kb
Host smart-810cc90d-5f6a-4e75-998c-036908d4f691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716196267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.716196267
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.736941291
Short name T53
Test name
Test status
Simulation time 136070204 ps
CPU time 1.71 seconds
Started Jul 13 06:45:25 PM PDT 24
Finished Jul 13 06:45:28 PM PDT 24
Peak memory 200092 kb
Host smart-06aee3fd-d79b-4d7e-8fbb-83316113f656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736941291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.736941291
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.616807210
Short name T341
Test name
Test status
Simulation time 158692059 ps
CPU time 1.34 seconds
Started Jul 13 06:45:31 PM PDT 24
Finished Jul 13 06:45:34 PM PDT 24
Peak memory 200252 kb
Host smart-0988180e-4f53-4501-9234-d01fa764b7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616807210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.616807210
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.303544736
Short name T90
Test name
Test status
Simulation time 79318878 ps
CPU time 0.8 seconds
Started Jul 13 06:45:28 PM PDT 24
Finished Jul 13 06:45:31 PM PDT 24
Peak memory 199876 kb
Host smart-49d41068-720a-4af1-a2eb-d2d14cc702ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303544736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.303544736
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3407044878
Short name T40
Test name
Test status
Simulation time 1888164961 ps
CPU time 7.24 seconds
Started Jul 13 06:45:32 PM PDT 24
Finished Jul 13 06:45:40 PM PDT 24
Peak memory 221632 kb
Host smart-83a65dc3-8796-4aa2-90fc-3b64805c5ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407044878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3407044878
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2490056674
Short name T207
Test name
Test status
Simulation time 245915888 ps
CPU time 1.18 seconds
Started Jul 13 06:45:30 PM PDT 24
Finished Jul 13 06:45:33 PM PDT 24
Peak memory 217484 kb
Host smart-e3f15165-3993-467f-ba8a-7b357210c08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490056674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2490056674
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2446905758
Short name T16
Test name
Test status
Simulation time 109280188 ps
CPU time 0.8 seconds
Started Jul 13 06:45:29 PM PDT 24
Finished Jul 13 06:45:32 PM PDT 24
Peak memory 199920 kb
Host smart-4b9537ac-c428-4476-9033-50b21048389f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446905758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2446905758
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.4220405265
Short name T517
Test name
Test status
Simulation time 999541667 ps
CPU time 4.97 seconds
Started Jul 13 06:45:24 PM PDT 24
Finished Jul 13 06:45:30 PM PDT 24
Peak memory 200348 kb
Host smart-706a1c79-1c59-4110-8d01-f97cb59b9040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220405265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.4220405265
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3046080012
Short name T181
Test name
Test status
Simulation time 103165029 ps
CPU time 1.04 seconds
Started Jul 13 06:45:26 PM PDT 24
Finished Jul 13 06:45:28 PM PDT 24
Peak memory 200096 kb
Host smart-2236f89c-e8a1-412f-a768-c50e27814c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046080012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3046080012
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.22257648
Short name T233
Test name
Test status
Simulation time 115906687 ps
CPU time 1.14 seconds
Started Jul 13 06:45:30 PM PDT 24
Finished Jul 13 06:45:33 PM PDT 24
Peak memory 200320 kb
Host smart-a41ff6f5-548a-4a18-bef1-95170d5f935f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22257648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.22257648
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3516408769
Short name T176
Test name
Test status
Simulation time 131953815 ps
CPU time 1.03 seconds
Started Jul 13 06:45:30 PM PDT 24
Finished Jul 13 06:45:32 PM PDT 24
Peak memory 200132 kb
Host smart-790f42af-586e-434f-b734-679db7562c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516408769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3516408769
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1447146102
Short name T153
Test name
Test status
Simulation time 64911750 ps
CPU time 0.79 seconds
Started Jul 13 06:45:28 PM PDT 24
Finished Jul 13 06:45:31 PM PDT 24
Peak memory 199904 kb
Host smart-7304998a-39e9-4824-a775-0b975e769f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447146102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1447146102
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.719869999
Short name T419
Test name
Test status
Simulation time 1229740865 ps
CPU time 5.55 seconds
Started Jul 13 06:45:28 PM PDT 24
Finished Jul 13 06:45:36 PM PDT 24
Peak memory 220796 kb
Host smart-866ea000-7f33-45b0-bdd5-5950fb644a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719869999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.719869999
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.538292883
Short name T197
Test name
Test status
Simulation time 243988101 ps
CPU time 1.14 seconds
Started Jul 13 06:45:33 PM PDT 24
Finished Jul 13 06:45:35 PM PDT 24
Peak memory 217464 kb
Host smart-73288672-9d00-47ad-aab5-c151a2234359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538292883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.538292883
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.4132977015
Short name T380
Test name
Test status
Simulation time 166690570 ps
CPU time 0.95 seconds
Started Jul 13 06:45:32 PM PDT 24
Finished Jul 13 06:45:34 PM PDT 24
Peak memory 199912 kb
Host smart-a3110e68-de2d-4261-8342-713df5b5d2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132977015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.4132977015
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1564853519
Short name T268
Test name
Test status
Simulation time 668069508 ps
CPU time 3.48 seconds
Started Jul 13 06:45:31 PM PDT 24
Finished Jul 13 06:45:36 PM PDT 24
Peak memory 200368 kb
Host smart-0836d792-2de0-45cb-873a-7d0ed5c11167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564853519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1564853519
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4090356510
Short name T275
Test name
Test status
Simulation time 172446175 ps
CPU time 1.25 seconds
Started Jul 13 06:45:31 PM PDT 24
Finished Jul 13 06:45:34 PM PDT 24
Peak memory 200100 kb
Host smart-2cf0648e-7497-4c78-9ca9-8a7900ee084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090356510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4090356510
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1832099498
Short name T68
Test name
Test status
Simulation time 223283643 ps
CPU time 1.48 seconds
Started Jul 13 06:45:33 PM PDT 24
Finished Jul 13 06:45:35 PM PDT 24
Peak memory 200308 kb
Host smart-efcf028a-75a9-4664-907a-7190d0e5fead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832099498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1832099498
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.716646460
Short name T106
Test name
Test status
Simulation time 7522039951 ps
CPU time 28 seconds
Started Jul 13 06:45:30 PM PDT 24
Finished Jul 13 06:46:00 PM PDT 24
Peak memory 208604 kb
Host smart-70176e79-15fc-4c26-9a70-62a0e73e0bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716646460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.716646460
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2181931538
Short name T450
Test name
Test status
Simulation time 123940245 ps
CPU time 1.61 seconds
Started Jul 13 06:45:28 PM PDT 24
Finished Jul 13 06:45:32 PM PDT 24
Peak memory 200160 kb
Host smart-2081f4c1-5840-471c-af4c-acadf628831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181931538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2181931538
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1034833183
Short name T177
Test name
Test status
Simulation time 190732501 ps
CPU time 1.31 seconds
Started Jul 13 06:45:27 PM PDT 24
Finished Jul 13 06:45:30 PM PDT 24
Peak memory 200096 kb
Host smart-25de1020-6174-48db-acac-7d9a5525ddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034833183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1034833183
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3403018651
Short name T414
Test name
Test status
Simulation time 72862163 ps
CPU time 0.84 seconds
Started Jul 13 06:45:34 PM PDT 24
Finished Jul 13 06:45:36 PM PDT 24
Peak memory 199892 kb
Host smart-3694a1ec-4eb6-4047-b053-24ade560aedf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403018651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3403018651
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1293511078
Short name T507
Test name
Test status
Simulation time 1892500375 ps
CPU time 7.73 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:45 PM PDT 24
Peak memory 217736 kb
Host smart-16973864-f29b-4cd2-a775-0a1719b58f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293511078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1293511078
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.609571264
Short name T530
Test name
Test status
Simulation time 244155383 ps
CPU time 1.1 seconds
Started Jul 13 06:45:37 PM PDT 24
Finished Jul 13 06:45:40 PM PDT 24
Peak memory 217492 kb
Host smart-37941687-defa-49de-97b2-0fd9372f8810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609571264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.609571264
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.868950109
Short name T17
Test name
Test status
Simulation time 105788686 ps
CPU time 0.8 seconds
Started Jul 13 06:45:30 PM PDT 24
Finished Jul 13 06:45:33 PM PDT 24
Peak memory 199916 kb
Host smart-eafc4cb3-a72d-4091-8486-e05fe8c81412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868950109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.868950109
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3970028596
Short name T522
Test name
Test status
Simulation time 671487957 ps
CPU time 4.17 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:40 PM PDT 24
Peak memory 200360 kb
Host smart-66bd6674-72f8-4277-80d7-a5c2c0d6e71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970028596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3970028596
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.487097813
Short name T203
Test name
Test status
Simulation time 106278533 ps
CPU time 1.06 seconds
Started Jul 13 06:45:34 PM PDT 24
Finished Jul 13 06:45:36 PM PDT 24
Peak memory 200084 kb
Host smart-32a64de2-079d-4bea-b7cd-385d29e9eed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487097813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.487097813
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.421867105
Short name T145
Test name
Test status
Simulation time 188749215 ps
CPU time 1.53 seconds
Started Jul 13 06:45:30 PM PDT 24
Finished Jul 13 06:45:34 PM PDT 24
Peak memory 200304 kb
Host smart-6aa3fd63-fd17-4ec6-85af-37a911759f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421867105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.421867105
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.4218747904
Short name T384
Test name
Test status
Simulation time 10420736573 ps
CPU time 38.74 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:46:17 PM PDT 24
Peak memory 200456 kb
Host smart-e75006c5-0df4-4c44-be62-3abbf484aecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218747904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.4218747904
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3940025544
Short name T158
Test name
Test status
Simulation time 299275728 ps
CPU time 1.98 seconds
Started Jul 13 06:45:35 PM PDT 24
Finished Jul 13 06:45:39 PM PDT 24
Peak memory 208284 kb
Host smart-1159ec54-6745-4dcc-9cd0-5c1bbb2152f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940025544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3940025544
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.991683609
Short name T433
Test name
Test status
Simulation time 80699914 ps
CPU time 0.85 seconds
Started Jul 13 06:45:36 PM PDT 24
Finished Jul 13 06:45:38 PM PDT 24
Peak memory 200096 kb
Host smart-33ff4bb7-20ec-41bb-b9db-4b3bff05b06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991683609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.991683609
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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