Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7513

1

T1

14

T6

25

T7

5

auto[1]

10479

1

T1

1

T3

4

T6

76

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5639	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6208	1			T1	1		T2	1		T3	2
reset_info_cp[2]	2723	1			T3	1		T6	12		T9	8
reset_info_cp[4]	3545	1			T3	1		T6	14		T9	12
reset_info_cp[8]	81	1			T6	1		T10	4		T26	1
reset_info_cp[16]	83	1			T6	2		T10	2		T26	1
reset_info_cp[32]	114	1			T1	1		T3	1		T10	3
reset_info_cp[64]	115	1			T1	1		T6	2		T10	2
reset_info_cp[128]	104	1			T6	1		T10	5		T26	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2979	1			T6	25		T9	6		T10	78
reset_info_cp[1]	auto[1]	2609	1			T3	1		T6	1		T9	5
reset_info_cp[2]	auto[0]	810	1			T9	6		T10	44		T26	16
reset_info_cp[2]	auto[1]	1913	1			T3	1		T6	12		T9	2
reset_info_cp[4]	auto[0]	1213	1			T9	7		T10	43		T26	31
reset_info_cp[4]	auto[1]	2332	1			T3	1		T6	14		T9	5
reset_info_cp[8]	auto[0]	30	1			T10	2		T26	1		T144	1
reset_info_cp[8]	auto[1]	51	1			T6	1		T10	2		T48	2
reset_info_cp[16]	auto[0]	23	1			T10	1		T83	1		T153	1
reset_info_cp[16]	auto[1]	60	1			T6	2		T10	1		T26	1
reset_info_cp[32]	auto[0]	46	1			T1	1		T10	2		T26	1
reset_info_cp[32]	auto[1]	68	1			T3	1		T10	1		T26	2
reset_info_cp[64]	auto[0]	53	1			T1	1		T10	1		T27	1
reset_info_cp[64]	auto[1]	62	1			T6	2		T10	1		T48	1
reset_info_cp[128]	auto[0]	44	1			T27	1		T83	1		T46	1
reset_info_cp[128]	auto[1]	60	1			T6	1		T10	5		T26	1