Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T537 /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3537502421 Jul 14 07:06:30 PM PDT 24 Jul 14 07:06:34 PM PDT 24 143610326 ps
T538 /workspace/coverage/default/41.rstmgr_smoke.1829368558 Jul 14 07:07:02 PM PDT 24 Jul 14 07:07:05 PM PDT 24 116272062 ps
T539 /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.740535425 Jul 14 07:05:38 PM PDT 24 Jul 14 07:05:47 PM PDT 24 2361266469 ps
T540 /workspace/coverage/default/24.rstmgr_reset.1053703698 Jul 14 07:06:31 PM PDT 24 Jul 14 07:06:38 PM PDT 24 753421684 ps
T541 /workspace/coverage/default/1.rstmgr_smoke.4115713718 Jul 14 07:05:40 PM PDT 24 Jul 14 07:05:42 PM PDT 24 122897727 ps
T62 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1982195801 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:13 PM PDT 24 116289735 ps
T63 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4064321230 Jul 14 06:24:16 PM PDT 24 Jul 14 06:24:17 PM PDT 24 87413163 ps
T66 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.360527093 Jul 14 06:24:18 PM PDT 24 Jul 14 06:24:21 PM PDT 24 210496147 ps
T64 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2657957790 Jul 14 06:24:01 PM PDT 24 Jul 14 06:24:04 PM PDT 24 465032197 ps
T68 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.218102180 Jul 14 06:24:14 PM PDT 24 Jul 14 06:24:17 PM PDT 24 504234098 ps
T67 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1859188358 Jul 14 06:24:05 PM PDT 24 Jul 14 06:24:09 PM PDT 24 341365937 ps
T90 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2571251198 Jul 14 06:24:09 PM PDT 24 Jul 14 06:24:12 PM PDT 24 421907893 ps
T91 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3653114267 Jul 14 06:24:07 PM PDT 24 Jul 14 06:24:09 PM PDT 24 99782983 ps
T117 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4105391595 Jul 14 06:24:09 PM PDT 24 Jul 14 06:24:11 PM PDT 24 134081859 ps
T118 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3149630988 Jul 14 06:24:18 PM PDT 24 Jul 14 06:24:20 PM PDT 24 282076670 ps
T542 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1423163178 Jul 14 06:24:14 PM PDT 24 Jul 14 06:24:16 PM PDT 24 84497402 ps
T543 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1520574515 Jul 14 06:24:07 PM PDT 24 Jul 14 06:24:09 PM PDT 24 80147253 ps
T119 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.14085602 Jul 14 06:24:12 PM PDT 24 Jul 14 06:24:15 PM PDT 24 143569895 ps
T544 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1148693654 Jul 14 06:24:06 PM PDT 24 Jul 14 06:24:08 PM PDT 24 136124856 ps
T120 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.964470704 Jul 14 06:24:14 PM PDT 24 Jul 14 06:24:17 PM PDT 24 226208335 ps
T121 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.855221330 Jul 14 06:24:07 PM PDT 24 Jul 14 06:24:09 PM PDT 24 75647972 ps
T545 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.23747534 Jul 14 06:24:10 PM PDT 24 Jul 14 06:24:13 PM PDT 24 62271991 ps
T122 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4269968549 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:15 PM PDT 24 187078752 ps
T92 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3880959897 Jul 14 06:24:12 PM PDT 24 Jul 14 06:24:15 PM PDT 24 124248925 ps
T123 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1867860698 Jul 14 06:24:10 PM PDT 24 Jul 14 06:24:12 PM PDT 24 79022266 ps
T93 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.212867042 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:14 PM PDT 24 245776842 ps
T124 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.69495588 Jul 14 06:24:10 PM PDT 24 Jul 14 06:24:13 PM PDT 24 73983213 ps
T96 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1373572135 Jul 14 06:23:58 PM PDT 24 Jul 14 06:24:00 PM PDT 24 418496000 ps
T546 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3509973494 Jul 14 06:24:17 PM PDT 24 Jul 14 06:24:19 PM PDT 24 89328618 ps
T94 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1569441483 Jul 14 06:24:17 PM PDT 24 Jul 14 06:24:21 PM PDT 24 552736123 ps
T125 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3445257022 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:13 PM PDT 24 55987479 ps
T547 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4160411402 Jul 14 06:24:18 PM PDT 24 Jul 14 06:24:20 PM PDT 24 67070357 ps
T95 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3644562734 Jul 14 06:24:19 PM PDT 24 Jul 14 06:24:23 PM PDT 24 922664966 ps
T97 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1665282684 Jul 14 06:24:05 PM PDT 24 Jul 14 06:24:07 PM PDT 24 208113054 ps
T548 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3348922851 Jul 14 06:24:04 PM PDT 24 Jul 14 06:24:06 PM PDT 24 74355619 ps
T98 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2167552440 Jul 14 06:24:12 PM PDT 24 Jul 14 06:24:16 PM PDT 24 138158437 ps
T549 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1314603147 Jul 14 06:23:58 PM PDT 24 Jul 14 06:24:00 PM PDT 24 76904322 ps
T99 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3358975722 Jul 14 06:24:12 PM PDT 24 Jul 14 06:24:15 PM PDT 24 125318347 ps
T127 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1961011133 Jul 14 06:24:18 PM PDT 24 Jul 14 06:24:22 PM PDT 24 183240844 ps
T150 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3554944286 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:15 PM PDT 24 475786778 ps
T550 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.900465482 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:13 PM PDT 24 61909866 ps
T551 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2609344944 Jul 14 06:24:14 PM PDT 24 Jul 14 06:24:16 PM PDT 24 72575443 ps
T552 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.606444392 Jul 14 06:24:05 PM PDT 24 Jul 14 06:24:07 PM PDT 24 163749400 ps
T553 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1347877176 Jul 14 06:24:05 PM PDT 24 Jul 14 06:24:08 PM PDT 24 114581872 ps
T128 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2950600019 Jul 14 06:24:14 PM PDT 24 Jul 14 06:24:18 PM PDT 24 767338434 ps
T554 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.15996944 Jul 14 06:24:05 PM PDT 24 Jul 14 06:24:07 PM PDT 24 127447305 ps
T555 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1043852978 Jul 14 06:24:20 PM PDT 24 Jul 14 06:24:21 PM PDT 24 176031593 ps
T134 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1647827316 Jul 14 06:24:01 PM PDT 24 Jul 14 06:24:05 PM PDT 24 375915310 ps
T556 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2415053633 Jul 14 06:24:17 PM PDT 24 Jul 14 06:24:19 PM PDT 24 131317280 ps
T557 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.601225487 Jul 14 06:24:13 PM PDT 24 Jul 14 06:24:16 PM PDT 24 95580324 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.975688398 Jul 14 06:24:06 PM PDT 24 Jul 14 06:24:08 PM PDT 24 121399585 ps
T129 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1840624494 Jul 14 06:23:59 PM PDT 24 Jul 14 06:24:02 PM PDT 24 776706328 ps
T559 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3132510419 Jul 14 06:24:12 PM PDT 24 Jul 14 06:24:15 PM PDT 24 114287799 ps
T560 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1187456109 Jul 14 06:24:07 PM PDT 24 Jul 14 06:24:10 PM PDT 24 136983142 ps
T561 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.321311947 Jul 14 06:24:00 PM PDT 24 Jul 14 06:24:01 PM PDT 24 56454971 ps
T562 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.520256015 Jul 14 06:24:06 PM PDT 24 Jul 14 06:24:08 PM PDT 24 260693010 ps
T563 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1229062633 Jul 14 06:24:01 PM PDT 24 Jul 14 06:24:04 PM PDT 24 160247471 ps
T564 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.377428098 Jul 14 06:24:14 PM PDT 24 Jul 14 06:24:16 PM PDT 24 106664678 ps
T565 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4153168037 Jul 14 06:24:00 PM PDT 24 Jul 14 06:24:05 PM PDT 24 1175701076 ps
T566 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.902336299 Jul 14 06:24:01 PM PDT 24 Jul 14 06:24:03 PM PDT 24 246665760 ps
T131 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3391658006 Jul 14 06:24:10 PM PDT 24 Jul 14 06:24:13 PM PDT 24 464916006 ps
T567 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1748996000 Jul 14 06:24:06 PM PDT 24 Jul 14 06:24:09 PM PDT 24 292459696 ps
T568 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.399202882 Jul 14 06:24:13 PM PDT 24 Jul 14 06:24:16 PM PDT 24 77749139 ps
T569 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.406457620 Jul 14 06:24:05 PM PDT 24 Jul 14 06:24:07 PM PDT 24 110872168 ps
T570 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4216218601 Jul 14 06:24:19 PM PDT 24 Jul 14 06:24:21 PM PDT 24 189037943 ps
T571 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.782618233 Jul 14 06:24:12 PM PDT 24 Jul 14 06:24:16 PM PDT 24 276833975 ps
T132 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.541117434 Jul 14 06:24:18 PM PDT 24 Jul 14 06:24:22 PM PDT 24 916535689 ps
T572 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.487258656 Jul 14 06:24:04 PM PDT 24 Jul 14 06:24:08 PM PDT 24 942410050 ps
T573 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.924310914 Jul 14 06:24:06 PM PDT 24 Jul 14 06:24:09 PM PDT 24 146577101 ps
T574 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3782773941 Jul 14 06:24:16 PM PDT 24 Jul 14 06:24:18 PM PDT 24 181400623 ps
T575 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1785052878 Jul 14 06:24:07 PM PDT 24 Jul 14 06:24:09 PM PDT 24 187860556 ps
T130 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3376081608 Jul 14 06:24:05 PM PDT 24 Jul 14 06:24:09 PM PDT 24 877578943 ps
T576 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2912444955 Jul 14 06:24:04 PM PDT 24 Jul 14 06:24:06 PM PDT 24 82701218 ps
T133 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2874914834 Jul 14 06:24:10 PM PDT 24 Jul 14 06:24:13 PM PDT 24 496084096 ps
T577 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.927091141 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:16 PM PDT 24 243581991 ps
T578 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3949287658 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:14 PM PDT 24 140242288 ps
T151 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2490173540 Jul 14 06:24:03 PM PDT 24 Jul 14 06:24:07 PM PDT 24 882916238 ps
T579 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2366131097 Jul 14 06:24:13 PM PDT 24 Jul 14 06:24:17 PM PDT 24 399069984 ps
T580 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.321811106 Jul 14 06:24:04 PM PDT 24 Jul 14 06:24:06 PM PDT 24 150860236 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1319687306 Jul 14 06:24:10 PM PDT 24 Jul 14 06:24:13 PM PDT 24 783584728 ps
T582 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3112827624 Jul 14 06:24:16 PM PDT 24 Jul 14 06:24:18 PM PDT 24 60163867 ps
T583 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3791418562 Jul 14 06:24:00 PM PDT 24 Jul 14 06:24:02 PM PDT 24 201106778 ps
T584 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3051956450 Jul 14 06:24:00 PM PDT 24 Jul 14 06:24:02 PM PDT 24 202623962 ps
T585 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1869979458 Jul 14 06:24:17 PM PDT 24 Jul 14 06:24:19 PM PDT 24 87989742 ps
T586 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1899510786 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:14 PM PDT 24 70610202 ps
T152 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2457044008 Jul 14 06:24:05 PM PDT 24 Jul 14 06:24:09 PM PDT 24 899868004 ps
T587 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2118468454 Jul 14 06:24:07 PM PDT 24 Jul 14 06:24:10 PM PDT 24 158109298 ps
T588 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1508395581 Jul 14 06:24:09 PM PDT 24 Jul 14 06:24:12 PM PDT 24 178409983 ps
T589 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.148745446 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:16 PM PDT 24 435367288 ps
T590 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3698564032 Jul 14 06:23:59 PM PDT 24 Jul 14 06:24:01 PM PDT 24 184992722 ps
T591 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1476579889 Jul 14 06:24:00 PM PDT 24 Jul 14 06:24:02 PM PDT 24 204147772 ps
T592 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2560611238 Jul 14 06:24:18 PM PDT 24 Jul 14 06:24:20 PM PDT 24 71321605 ps
T593 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2898178803 Jul 14 06:24:02 PM PDT 24 Jul 14 06:24:04 PM PDT 24 151320200 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1343028103 Jul 14 06:24:01 PM PDT 24 Jul 14 06:24:04 PM PDT 24 185648500 ps
T595 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3549180810 Jul 14 06:24:10 PM PDT 24 Jul 14 06:24:15 PM PDT 24 885998316 ps
T596 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1452477142 Jul 14 06:24:06 PM PDT 24 Jul 14 06:24:11 PM PDT 24 275532835 ps
T597 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.4221482233 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:15 PM PDT 24 111038166 ps
T598 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2676083797 Jul 14 06:24:06 PM PDT 24 Jul 14 06:24:12 PM PDT 24 801748636 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.475291392 Jul 14 06:24:00 PM PDT 24 Jul 14 06:24:06 PM PDT 24 1174078497 ps
T600 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1949824963 Jul 14 06:24:14 PM PDT 24 Jul 14 06:24:16 PM PDT 24 77813162 ps
T601 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1164007749 Jul 14 06:24:11 PM PDT 24 Jul 14 06:24:15 PM PDT 24 175824829 ps
T602 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3308215473 Jul 14 06:23:59 PM PDT 24 Jul 14 06:24:09 PM PDT 24 2279803155 ps
T603 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2936686698 Jul 14 06:24:06 PM PDT 24 Jul 14 06:24:09 PM PDT 24 141105956 ps
T604 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2137122918 Jul 14 06:23:59 PM PDT 24 Jul 14 06:24:00 PM PDT 24 83564878 ps
T605 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2069096551 Jul 14 06:24:02 PM PDT 24 Jul 14 06:24:03 PM PDT 24 83864461 ps
T606 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3714610952 Jul 14 06:24:19 PM PDT 24 Jul 14 06:24:23 PM PDT 24 777916426 ps
T607 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1475004236 Jul 14 06:24:12 PM PDT 24 Jul 14 06:24:15 PM PDT 24 200067461 ps
T608 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2390621137 Jul 14 06:24:10 PM PDT 24 Jul 14 06:24:13 PM PDT 24 182871152 ps
T609 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3023045320 Jul 14 06:24:10 PM PDT 24 Jul 14 06:24:12 PM PDT 24 216361997 ps
T610 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2693892549 Jul 14 06:24:09 PM PDT 24 Jul 14 06:24:12 PM PDT 24 117610589 ps
T611 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2984802565 Jul 14 06:24:07 PM PDT 24 Jul 14 06:24:09 PM PDT 24 103945394 ps
T612 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2275741650 Jul 14 06:24:16 PM PDT 24 Jul 14 06:24:18 PM PDT 24 243369993 ps
T613 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2313695430 Jul 14 06:24:18 PM PDT 24 Jul 14 06:24:22 PM PDT 24 193165982 ps
T614 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3282542143 Jul 14 06:24:05 PM PDT 24 Jul 14 06:24:08 PM PDT 24 213282808 ps
T615 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3268385733 Jul 14 06:24:12 PM PDT 24 Jul 14 06:24:16 PM PDT 24 469458694 ps
T616 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1107988216 Jul 14 06:23:58 PM PDT 24 Jul 14 06:24:00 PM PDT 24 104540528 ps
T617 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.19078289 Jul 14 06:24:16 PM PDT 24 Jul 14 06:24:20 PM PDT 24 884292889 ps
T618 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2400071607 Jul 14 06:24:06 PM PDT 24 Jul 14 06:24:08 PM PDT 24 127577484 ps
T619 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4000845934 Jul 14 06:24:07 PM PDT 24 Jul 14 06:24:09 PM PDT 24 145611938 ps
T620 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1711447229 Jul 14 06:24:18 PM PDT 24 Jul 14 06:24:21 PM PDT 24 99772042 ps

Test location /workspace/coverage/default/11.rstmgr_stress_all.2839489455
Short name T10
Test name
Test status
Simulation time 8709775527 ps
CPU time 35.99 seconds
Started Jul 14 07:06:07 PM PDT 24
Finished Jul 14 07:06:45 PM PDT 24
Peak memory 210292 kb
Host smart-1b4e9c2b-787c-402e-84bb-33699512946b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839489455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2839489455
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3348284680
Short name T65
Test name
Test status
Simulation time 233236787 ps
CPU time 1.43 seconds
Started Jul 14 07:06:43 PM PDT 24
Finished Jul 14 07:06:46 PM PDT 24
Peak memory 200340 kb
Host smart-35c46c0b-4071-4f01-851e-5036b62a8960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348284680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3348284680
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1982195801
Short name T62
Test name
Test status
Simulation time 116289735 ps
CPU time 1.01 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:13 PM PDT 24
Peak memory 200412 kb
Host smart-cc2f6819-0d77-4a35-8de3-64e707b6d862
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982195801 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1982195801
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.293609279
Short name T73
Test name
Test status
Simulation time 16541087891 ps
CPU time 25.33 seconds
Started Jul 14 07:05:38 PM PDT 24
Finished Jul 14 07:06:03 PM PDT 24
Peak memory 217700 kb
Host smart-240066c7-59e0-4e39-9afa-941b50bbad51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293609279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.293609279
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1129960735
Short name T6
Test name
Test status
Simulation time 1225120145 ps
CPU time 5.4 seconds
Started Jul 14 07:05:44 PM PDT 24
Finished Jul 14 07:05:50 PM PDT 24
Peak memory 221748 kb
Host smart-4de83828-a210-44c2-8fc4-314817b1fbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129960735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1129960735
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3895067029
Short name T61
Test name
Test status
Simulation time 418071354 ps
CPU time 2.26 seconds
Started Jul 14 07:05:51 PM PDT 24
Finished Jul 14 07:05:55 PM PDT 24
Peak memory 208596 kb
Host smart-89266b80-2c6f-44a5-8e34-31ff9f22cff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895067029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3895067029
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2571251198
Short name T90
Test name
Test status
Simulation time 421907893 ps
CPU time 1.8 seconds
Started Jul 14 06:24:09 PM PDT 24
Finished Jul 14 06:24:12 PM PDT 24
Peak memory 200428 kb
Host smart-4dfdb119-9a3c-4482-9dbd-afa00870b2c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571251198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2571251198
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.636566702
Short name T5
Test name
Test status
Simulation time 83064367 ps
CPU time 0.84 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:04 PM PDT 24
Peak memory 199924 kb
Host smart-f8902b74-1afe-49aa-8e35-4b3ce73bf1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636566702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.636566702
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1859188358
Short name T67
Test name
Test status
Simulation time 341365937 ps
CPU time 2.56 seconds
Started Jul 14 06:24:05 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 208592 kb
Host smart-e7a8150a-f29d-4d81-b07b-73f127a7b93e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859188358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1859188358
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1393381682
Short name T143
Test name
Test status
Simulation time 109153078 ps
CPU time 1.01 seconds
Started Jul 14 07:05:39 PM PDT 24
Finished Jul 14 07:05:40 PM PDT 24
Peak memory 200124 kb
Host smart-b4827e70-112a-4718-8f44-2cd3ddd04c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393381682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1393381682
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2869563409
Short name T32
Test name
Test status
Simulation time 1226997090 ps
CPU time 5.58 seconds
Started Jul 14 07:07:04 PM PDT 24
Finished Jul 14 07:07:12 PM PDT 24
Peak memory 221708 kb
Host smart-f769811e-c145-41cd-8cc3-a5e46b1f0d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869563409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2869563409
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2629496364
Short name T103
Test name
Test status
Simulation time 2708762475 ps
CPU time 9.63 seconds
Started Jul 14 07:06:33 PM PDT 24
Finished Jul 14 07:06:44 PM PDT 24
Peak memory 208660 kb
Host smart-c40def78-dc6a-4735-b9f9-780f563a652b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629496364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2629496364
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3391658006
Short name T131
Test name
Test status
Simulation time 464916006 ps
CPU time 1.94 seconds
Started Jul 14 06:24:10 PM PDT 24
Finished Jul 14 06:24:13 PM PDT 24
Peak memory 200484 kb
Host smart-b7b944fa-b2fd-4d32-ba76-2b22257ab462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391658006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3391658006
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1840624494
Short name T129
Test name
Test status
Simulation time 776706328 ps
CPU time 2.87 seconds
Started Jul 14 06:23:59 PM PDT 24
Finished Jul 14 06:24:02 PM PDT 24
Peak memory 200500 kb
Host smart-894a7471-66fe-4769-8c12-f1a9c4b541d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840624494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1840624494
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1701396434
Short name T319
Test name
Test status
Simulation time 1902847663 ps
CPU time 7.01 seconds
Started Jul 14 07:06:40 PM PDT 24
Finished Jul 14 07:06:48 PM PDT 24
Peak memory 217492 kb
Host smart-b4c12b58-4847-4948-8fe1-265995d2e4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701396434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1701396434
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2867597697
Short name T7
Test name
Test status
Simulation time 95368226 ps
CPU time 0.98 seconds
Started Jul 14 07:05:41 PM PDT 24
Finished Jul 14 07:05:42 PM PDT 24
Peak memory 200132 kb
Host smart-3a51a015-4ea4-4147-819a-794823044e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867597697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2867597697
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.601225487
Short name T557
Test name
Test status
Simulation time 95580324 ps
CPU time 1.23 seconds
Started Jul 14 06:24:13 PM PDT 24
Finished Jul 14 06:24:16 PM PDT 24
Peak memory 208436 kb
Host smart-75d221b1-9e73-415d-a103-7b6599538534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601225487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.601225487
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1564519249
Short name T105
Test name
Test status
Simulation time 4308436526 ps
CPU time 19.21 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:27 PM PDT 24
Peak memory 208732 kb
Host smart-85853dd9-d006-4f1c-927e-eaafb08b8db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564519249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1564519249
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3445257022
Short name T125
Test name
Test status
Simulation time 55987479 ps
CPU time 0.77 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:13 PM PDT 24
Peak memory 200292 kb
Host smart-cddc7416-f11b-4296-b052-380fcfb4f733
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445257022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3445257022
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3515691763
Short name T17
Test name
Test status
Simulation time 123649352 ps
CPU time 0.88 seconds
Started Jul 14 07:06:08 PM PDT 24
Finished Jul 14 07:06:11 PM PDT 24
Peak memory 199808 kb
Host smart-dd56d5f5-a578-4034-b880-bd9d3122bbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515691763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3515691763
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.902336299
Short name T566
Test name
Test status
Simulation time 246665760 ps
CPU time 1.66 seconds
Started Jul 14 06:24:01 PM PDT 24
Finished Jul 14 06:24:03 PM PDT 24
Peak memory 200432 kb
Host smart-d7bf8739-0ce6-4de0-afe0-96059e02cdeb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902336299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.902336299
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.475291392
Short name T599
Test name
Test status
Simulation time 1174078497 ps
CPU time 5.4 seconds
Started Jul 14 06:24:00 PM PDT 24
Finished Jul 14 06:24:06 PM PDT 24
Peak memory 200484 kb
Host smart-142909f0-e969-4490-84e2-0c7f54343777
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475291392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.475291392
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2400071607
Short name T618
Test name
Test status
Simulation time 127577484 ps
CPU time 0.92 seconds
Started Jul 14 06:24:06 PM PDT 24
Finished Jul 14 06:24:08 PM PDT 24
Peak memory 200164 kb
Host smart-19dde122-5c11-4149-a24f-fd87279d0fed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400071607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
400071607
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3791418562
Short name T583
Test name
Test status
Simulation time 201106778 ps
CPU time 1.27 seconds
Started Jul 14 06:24:00 PM PDT 24
Finished Jul 14 06:24:02 PM PDT 24
Peak memory 208732 kb
Host smart-43c4ae84-a9c6-4888-a793-2305431c68ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791418562 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3791418562
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2137122918
Short name T604
Test name
Test status
Simulation time 83564878 ps
CPU time 0.88 seconds
Started Jul 14 06:23:59 PM PDT 24
Finished Jul 14 06:24:00 PM PDT 24
Peak memory 200172 kb
Host smart-a58f41a3-edf8-4c9c-951f-d8c6858c7a42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137122918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2137122918
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2069096551
Short name T605
Test name
Test status
Simulation time 83864461 ps
CPU time 1.11 seconds
Started Jul 14 06:24:02 PM PDT 24
Finished Jul 14 06:24:03 PM PDT 24
Peak memory 200296 kb
Host smart-4cb6190c-d21b-4a99-9f14-9b1e1a5c21a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069096551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2069096551
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1647827316
Short name T134
Test name
Test status
Simulation time 375915310 ps
CPU time 2.88 seconds
Started Jul 14 06:24:01 PM PDT 24
Finished Jul 14 06:24:05 PM PDT 24
Peak memory 208604 kb
Host smart-96c91a9a-d0fc-406c-9676-fbca6cb50e60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647827316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1647827316
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1373572135
Short name T96
Test name
Test status
Simulation time 418496000 ps
CPU time 1.87 seconds
Started Jul 14 06:23:58 PM PDT 24
Finished Jul 14 06:24:00 PM PDT 24
Peak memory 200484 kb
Host smart-5fdc1e26-0c18-42f0-8956-9feeb0acb278
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373572135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1373572135
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1476579889
Short name T591
Test name
Test status
Simulation time 204147772 ps
CPU time 1.57 seconds
Started Jul 14 06:24:00 PM PDT 24
Finished Jul 14 06:24:02 PM PDT 24
Peak memory 200360 kb
Host smart-0b612a16-fedc-46e1-9433-615071d848f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476579889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
476579889
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4153168037
Short name T565
Test name
Test status
Simulation time 1175701076 ps
CPU time 5.38 seconds
Started Jul 14 06:24:00 PM PDT 24
Finished Jul 14 06:24:05 PM PDT 24
Peak memory 200448 kb
Host smart-5fe33f32-469f-467e-9f44-dc3128e19517
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153168037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.4
153168037
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1107988216
Short name T616
Test name
Test status
Simulation time 104540528 ps
CPU time 0.88 seconds
Started Jul 14 06:23:58 PM PDT 24
Finished Jul 14 06:24:00 PM PDT 24
Peak memory 200292 kb
Host smart-b0c3118d-5eaf-48c4-aad7-89afde996d50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107988216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
107988216
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3698564032
Short name T590
Test name
Test status
Simulation time 184992722 ps
CPU time 1.23 seconds
Started Jul 14 06:23:59 PM PDT 24
Finished Jul 14 06:24:01 PM PDT 24
Peak memory 208628 kb
Host smart-00c2435b-91ad-407d-acfd-ff4516dc2fb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698564032 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3698564032
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1314603147
Short name T549
Test name
Test status
Simulation time 76904322 ps
CPU time 0.79 seconds
Started Jul 14 06:23:58 PM PDT 24
Finished Jul 14 06:24:00 PM PDT 24
Peak memory 200244 kb
Host smart-6073b71f-3dc3-471a-85d1-2094d10bafa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314603147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1314603147
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3051956450
Short name T584
Test name
Test status
Simulation time 202623962 ps
CPU time 1.51 seconds
Started Jul 14 06:24:00 PM PDT 24
Finished Jul 14 06:24:02 PM PDT 24
Peak memory 200488 kb
Host smart-855dfae9-44d6-443f-8136-ca52dc118554
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051956450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3051956450
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1343028103
Short name T594
Test name
Test status
Simulation time 185648500 ps
CPU time 2.73 seconds
Started Jul 14 06:24:01 PM PDT 24
Finished Jul 14 06:24:04 PM PDT 24
Peak memory 208560 kb
Host smart-0efcb8e6-6cae-4f50-b5f1-0f35a9410091
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343028103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1343028103
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2657957790
Short name T64
Test name
Test status
Simulation time 465032197 ps
CPU time 1.83 seconds
Started Jul 14 06:24:01 PM PDT 24
Finished Jul 14 06:24:04 PM PDT 24
Peak memory 200468 kb
Host smart-5dcace0f-b491-4340-8900-70167eaa7298
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657957790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2657957790
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4064321230
Short name T63
Test name
Test status
Simulation time 87413163 ps
CPU time 0.95 seconds
Started Jul 14 06:24:16 PM PDT 24
Finished Jul 14 06:24:17 PM PDT 24
Peak memory 200308 kb
Host smart-b3ad1d84-b12f-4081-81e6-071f2b866a51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064321230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.4064321230
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2313695430
Short name T613
Test name
Test status
Simulation time 193165982 ps
CPU time 2.79 seconds
Started Jul 14 06:24:18 PM PDT 24
Finished Jul 14 06:24:22 PM PDT 24
Peak memory 208536 kb
Host smart-0d302660-9333-4960-8838-41c45307ecae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313695430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2313695430
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3880959897
Short name T92
Test name
Test status
Simulation time 124248925 ps
CPU time 1.24 seconds
Started Jul 14 06:24:12 PM PDT 24
Finished Jul 14 06:24:15 PM PDT 24
Peak memory 208904 kb
Host smart-f39b6d32-1858-471e-80dc-ce5c65a34f6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880959897 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3880959897
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1899510786
Short name T586
Test name
Test status
Simulation time 70610202 ps
CPU time 0.81 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:14 PM PDT 24
Peak memory 200472 kb
Host smart-dde36e91-00c4-4623-8449-6e04836db984
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899510786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1899510786
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3149630988
Short name T118
Test name
Test status
Simulation time 282076670 ps
CPU time 1.62 seconds
Started Jul 14 06:24:18 PM PDT 24
Finished Jul 14 06:24:20 PM PDT 24
Peak memory 200460 kb
Host smart-c9d013e1-c897-4afb-b074-9d5f14f4bc72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149630988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3149630988
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.360527093
Short name T66
Test name
Test status
Simulation time 210496147 ps
CPU time 1.51 seconds
Started Jul 14 06:24:18 PM PDT 24
Finished Jul 14 06:24:21 PM PDT 24
Peak memory 208396 kb
Host smart-8e899559-476c-4ea2-811e-d2d7cace53ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360527093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.360527093
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.218102180
Short name T68
Test name
Test status
Simulation time 504234098 ps
CPU time 1.95 seconds
Started Jul 14 06:24:14 PM PDT 24
Finished Jul 14 06:24:17 PM PDT 24
Peak memory 200476 kb
Host smart-391dff45-ab20-4bd5-898e-70a948a52063
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218102180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.218102180
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3132510419
Short name T559
Test name
Test status
Simulation time 114287799 ps
CPU time 0.96 seconds
Started Jul 14 06:24:12 PM PDT 24
Finished Jul 14 06:24:15 PM PDT 24
Peak memory 200304 kb
Host smart-84d442d8-061e-4190-a462-934ef58dbbfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132510419 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3132510419
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.399202882
Short name T568
Test name
Test status
Simulation time 77749139 ps
CPU time 0.8 seconds
Started Jul 14 06:24:13 PM PDT 24
Finished Jul 14 06:24:16 PM PDT 24
Peak memory 200204 kb
Host smart-3fe9c51f-37cf-4371-93be-f8f2898dcd24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399202882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.399202882
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.964470704
Short name T120
Test name
Test status
Simulation time 226208335 ps
CPU time 1.59 seconds
Started Jul 14 06:24:14 PM PDT 24
Finished Jul 14 06:24:17 PM PDT 24
Peak memory 200440 kb
Host smart-c3fbe223-1e04-48fc-bb26-e61ec470fc9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964470704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.964470704
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2366131097
Short name T579
Test name
Test status
Simulation time 399069984 ps
CPU time 2.88 seconds
Started Jul 14 06:24:13 PM PDT 24
Finished Jul 14 06:24:17 PM PDT 24
Peak memory 208700 kb
Host smart-8eb7a8a7-d09d-458b-96d4-e0b5e5ed2c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366131097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2366131097
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.541117434
Short name T132
Test name
Test status
Simulation time 916535689 ps
CPU time 2.99 seconds
Started Jul 14 06:24:18 PM PDT 24
Finished Jul 14 06:24:22 PM PDT 24
Peak memory 200420 kb
Host smart-95e88901-df22-44db-bfcd-02d4dda046e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541117434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.541117434
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.377428098
Short name T564
Test name
Test status
Simulation time 106664678 ps
CPU time 1.04 seconds
Started Jul 14 06:24:14 PM PDT 24
Finished Jul 14 06:24:16 PM PDT 24
Peak memory 208588 kb
Host smart-788749fd-682b-47e4-9abb-ae469dd8508b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377428098 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.377428098
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.69495588
Short name T124
Test name
Test status
Simulation time 73983213 ps
CPU time 0.87 seconds
Started Jul 14 06:24:10 PM PDT 24
Finished Jul 14 06:24:13 PM PDT 24
Peak memory 200304 kb
Host smart-2e3580be-9101-4da8-8330-d2f32a46f4dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69495588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.69495588
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.782618233
Short name T571
Test name
Test status
Simulation time 276833975 ps
CPU time 1.72 seconds
Started Jul 14 06:24:12 PM PDT 24
Finished Jul 14 06:24:16 PM PDT 24
Peak memory 200476 kb
Host smart-d01853c7-f36f-4c9c-abf9-87a424b621d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782618233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.782618233
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2693892549
Short name T610
Test name
Test status
Simulation time 117610589 ps
CPU time 1.72 seconds
Started Jul 14 06:24:09 PM PDT 24
Finished Jul 14 06:24:12 PM PDT 24
Peak memory 208624 kb
Host smart-8d07d001-fa5b-4c84-8185-192a462f3b65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693892549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2693892549
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3554944286
Short name T150
Test name
Test status
Simulation time 475786778 ps
CPU time 2.18 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:15 PM PDT 24
Peak memory 200548 kb
Host smart-8ccd9de2-b38b-42e7-9111-768d27220672
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554944286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3554944286
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3949287658
Short name T578
Test name
Test status
Simulation time 140242288 ps
CPU time 1.11 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:14 PM PDT 24
Peak memory 200364 kb
Host smart-b00902f1-1026-4cd4-8fd9-018094868555
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949287658 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3949287658
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2609344944
Short name T551
Test name
Test status
Simulation time 72575443 ps
CPU time 0.79 seconds
Started Jul 14 06:24:14 PM PDT 24
Finished Jul 14 06:24:16 PM PDT 24
Peak memory 200244 kb
Host smart-4c661cc8-f551-43f7-8da9-c20755b7b869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609344944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2609344944
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4269968549
Short name T122
Test name
Test status
Simulation time 187078752 ps
CPU time 1.46 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:15 PM PDT 24
Peak memory 200664 kb
Host smart-67e5956f-be59-4cc5-9aa1-b705b0218e8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269968549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.4269968549
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.927091141
Short name T577
Test name
Test status
Simulation time 243581991 ps
CPU time 2.39 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:16 PM PDT 24
Peak memory 200420 kb
Host smart-2a20633a-1647-4a0a-a15a-6c7677650fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927091141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.927091141
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1164007749
Short name T601
Test name
Test status
Simulation time 175824829 ps
CPU time 1.68 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:15 PM PDT 24
Peak memory 208676 kb
Host smart-e345cc79-b18a-4f5d-a2bc-034bfb5242a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164007749 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1164007749
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1423163178
Short name T542
Test name
Test status
Simulation time 84497402 ps
CPU time 0.91 seconds
Started Jul 14 06:24:14 PM PDT 24
Finished Jul 14 06:24:16 PM PDT 24
Peak memory 200328 kb
Host smart-f20c6182-9e3e-41cd-840e-318164cc472c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423163178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1423163178
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.14085602
Short name T119
Test name
Test status
Simulation time 143569895 ps
CPU time 1.13 seconds
Started Jul 14 06:24:12 PM PDT 24
Finished Jul 14 06:24:15 PM PDT 24
Peak memory 200332 kb
Host smart-c794bf6e-0694-44e2-b26f-7fb649327c8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14085602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sam
e_csr_outstanding.14085602
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.148745446
Short name T589
Test name
Test status
Simulation time 435367288 ps
CPU time 2.71 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:16 PM PDT 24
Peak memory 211928 kb
Host smart-715f5668-67e3-4cb7-9213-192d79dd071e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148745446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.148745446
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3268385733
Short name T615
Test name
Test status
Simulation time 469458694 ps
CPU time 1.88 seconds
Started Jul 14 06:24:12 PM PDT 24
Finished Jul 14 06:24:16 PM PDT 24
Peak memory 200488 kb
Host smart-ad0d7a81-9d85-468d-bfbe-0a2d64d659bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268385733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3268385733
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3358975722
Short name T99
Test name
Test status
Simulation time 125318347 ps
CPU time 0.97 seconds
Started Jul 14 06:24:12 PM PDT 24
Finished Jul 14 06:24:15 PM PDT 24
Peak memory 200412 kb
Host smart-b1e998bf-53e3-47e8-828b-c4a8e0f4b89b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358975722 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3358975722
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3509973494
Short name T546
Test name
Test status
Simulation time 89328618 ps
CPU time 0.9 seconds
Started Jul 14 06:24:17 PM PDT 24
Finished Jul 14 06:24:19 PM PDT 24
Peak memory 200196 kb
Host smart-2897335a-b61f-4014-b5fa-806486496792
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509973494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3509973494
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.4221482233
Short name T597
Test name
Test status
Simulation time 111038166 ps
CPU time 1.27 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:15 PM PDT 24
Peak memory 200476 kb
Host smart-668c1faa-65b5-44a8-a1bc-238c8c52a188
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221482233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.4221482233
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2950600019
Short name T128
Test name
Test status
Simulation time 767338434 ps
CPU time 2.92 seconds
Started Jul 14 06:24:14 PM PDT 24
Finished Jul 14 06:24:18 PM PDT 24
Peak memory 200532 kb
Host smart-e6566dc6-1bab-438f-aaa9-60c0f3580ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950600019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2950600019
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1043852978
Short name T555
Test name
Test status
Simulation time 176031593 ps
CPU time 1.26 seconds
Started Jul 14 06:24:20 PM PDT 24
Finished Jul 14 06:24:21 PM PDT 24
Peak memory 210340 kb
Host smart-be7f7f80-d2b5-4a6e-a568-f3bf371d171f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043852978 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1043852978
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3112827624
Short name T582
Test name
Test status
Simulation time 60163867 ps
CPU time 0.76 seconds
Started Jul 14 06:24:16 PM PDT 24
Finished Jul 14 06:24:18 PM PDT 24
Peak memory 200224 kb
Host smart-5483dcbe-54f8-4f9a-a852-152c9ee76e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112827624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3112827624
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1869979458
Short name T585
Test name
Test status
Simulation time 87989742 ps
CPU time 0.97 seconds
Started Jul 14 06:24:17 PM PDT 24
Finished Jul 14 06:24:19 PM PDT 24
Peak memory 200368 kb
Host smart-4d82a557-9e44-4a5f-9733-4cb61a568538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869979458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1869979458
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2167552440
Short name T98
Test name
Test status
Simulation time 138158437 ps
CPU time 1.88 seconds
Started Jul 14 06:24:12 PM PDT 24
Finished Jul 14 06:24:16 PM PDT 24
Peak memory 216748 kb
Host smart-bc93c146-cf3a-4f90-8984-ba53b5356a75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167552440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2167552440
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.19078289
Short name T617
Test name
Test status
Simulation time 884292889 ps
CPU time 3.16 seconds
Started Jul 14 06:24:16 PM PDT 24
Finished Jul 14 06:24:20 PM PDT 24
Peak memory 200496 kb
Host smart-d70568a0-15fe-4630-8590-5487d4c4a94f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19078289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.19078289
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4216218601
Short name T570
Test name
Test status
Simulation time 189037943 ps
CPU time 1.25 seconds
Started Jul 14 06:24:19 PM PDT 24
Finished Jul 14 06:24:21 PM PDT 24
Peak memory 208796 kb
Host smart-33c67ce0-1fa7-4c3f-8fec-83da41f01cf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216218601 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.4216218601
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2560611238
Short name T592
Test name
Test status
Simulation time 71321605 ps
CPU time 0.88 seconds
Started Jul 14 06:24:18 PM PDT 24
Finished Jul 14 06:24:20 PM PDT 24
Peak memory 200164 kb
Host smart-d4575001-b24f-41b7-a28d-d9bf4e2a945b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560611238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2560611238
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2415053633
Short name T556
Test name
Test status
Simulation time 131317280 ps
CPU time 1.35 seconds
Started Jul 14 06:24:17 PM PDT 24
Finished Jul 14 06:24:19 PM PDT 24
Peak memory 200488 kb
Host smart-a15d0d2b-7d55-4ddb-b7de-c819d384b228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415053633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2415053633
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1569441483
Short name T94
Test name
Test status
Simulation time 552736123 ps
CPU time 3.57 seconds
Started Jul 14 06:24:17 PM PDT 24
Finished Jul 14 06:24:21 PM PDT 24
Peak memory 216716 kb
Host smart-936f1e63-395e-4020-92a8-02d565b16383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569441483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1569441483
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3644562734
Short name T95
Test name
Test status
Simulation time 922664966 ps
CPU time 3.36 seconds
Started Jul 14 06:24:19 PM PDT 24
Finished Jul 14 06:24:23 PM PDT 24
Peak memory 200536 kb
Host smart-1fe82390-7946-4053-9214-259fe208a4f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644562734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3644562734
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3782773941
Short name T574
Test name
Test status
Simulation time 181400623 ps
CPU time 1.83 seconds
Started Jul 14 06:24:16 PM PDT 24
Finished Jul 14 06:24:18 PM PDT 24
Peak memory 208744 kb
Host smart-c5ab4526-f534-4a9f-bb60-9f545eba83df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782773941 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3782773941
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4160411402
Short name T547
Test name
Test status
Simulation time 67070357 ps
CPU time 0.78 seconds
Started Jul 14 06:24:18 PM PDT 24
Finished Jul 14 06:24:20 PM PDT 24
Peak memory 200272 kb
Host smart-72c42ef5-fa1a-4e2b-8fd7-d04f98a7ae83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160411402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.4160411402
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1711447229
Short name T620
Test name
Test status
Simulation time 99772042 ps
CPU time 1.3 seconds
Started Jul 14 06:24:18 PM PDT 24
Finished Jul 14 06:24:21 PM PDT 24
Peak memory 200440 kb
Host smart-316b7af3-8eca-4775-a4f6-0c7f5f8f1f22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711447229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1711447229
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2275741650
Short name T612
Test name
Test status
Simulation time 243369993 ps
CPU time 1.95 seconds
Started Jul 14 06:24:16 PM PDT 24
Finished Jul 14 06:24:18 PM PDT 24
Peak memory 210932 kb
Host smart-8f6d4310-2daf-47c5-ab9d-ea7b1c22c518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275741650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2275741650
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3714610952
Short name T606
Test name
Test status
Simulation time 777916426 ps
CPU time 2.79 seconds
Started Jul 14 06:24:19 PM PDT 24
Finished Jul 14 06:24:23 PM PDT 24
Peak memory 200420 kb
Host smart-d668d6d2-7a6f-4f34-8e26-a1fbf39bd948
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714610952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3714610952
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2898178803
Short name T593
Test name
Test status
Simulation time 151320200 ps
CPU time 1.93 seconds
Started Jul 14 06:24:02 PM PDT 24
Finished Jul 14 06:24:04 PM PDT 24
Peak memory 200384 kb
Host smart-2d9f9476-8e02-4c30-bd59-14e274fdce51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898178803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
898178803
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3308215473
Short name T602
Test name
Test status
Simulation time 2279803155 ps
CPU time 9.85 seconds
Started Jul 14 06:23:59 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 200476 kb
Host smart-c798d471-88e8-41b5-b886-5b929b813b5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308215473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
308215473
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.975688398
Short name T558
Test name
Test status
Simulation time 121399585 ps
CPU time 0.91 seconds
Started Jul 14 06:24:06 PM PDT 24
Finished Jul 14 06:24:08 PM PDT 24
Peak memory 200180 kb
Host smart-468d3193-b7d2-460e-aec0-2314bab5d9d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975688398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.975688398
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1665282684
Short name T97
Test name
Test status
Simulation time 208113054 ps
CPU time 1.38 seconds
Started Jul 14 06:24:05 PM PDT 24
Finished Jul 14 06:24:07 PM PDT 24
Peak memory 208576 kb
Host smart-db4e3aef-8c04-460b-8d9b-62bb9f76fd01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665282684 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1665282684
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.321311947
Short name T561
Test name
Test status
Simulation time 56454971 ps
CPU time 0.75 seconds
Started Jul 14 06:24:00 PM PDT 24
Finished Jul 14 06:24:01 PM PDT 24
Peak memory 200276 kb
Host smart-c1019f93-3d7b-41eb-95e7-7f3724998cca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321311947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.321311947
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.15996944
Short name T554
Test name
Test status
Simulation time 127447305 ps
CPU time 1.12 seconds
Started Jul 14 06:24:05 PM PDT 24
Finished Jul 14 06:24:07 PM PDT 24
Peak memory 200352 kb
Host smart-471b9de6-1c37-4c6c-8ce2-d71c76b5f7fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15996944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same
_csr_outstanding.15996944
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1229062633
Short name T563
Test name
Test status
Simulation time 160247471 ps
CPU time 2.58 seconds
Started Jul 14 06:24:01 PM PDT 24
Finished Jul 14 06:24:04 PM PDT 24
Peak memory 208608 kb
Host smart-3b7bfe0f-2d28-4b88-9d73-315cdb84e622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229062633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1229062633
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3282542143
Short name T614
Test name
Test status
Simulation time 213282808 ps
CPU time 1.59 seconds
Started Jul 14 06:24:05 PM PDT 24
Finished Jul 14 06:24:08 PM PDT 24
Peak memory 200364 kb
Host smart-72cd3595-bd84-44dc-a43e-016bf88023a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282542143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
282542143
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1452477142
Short name T596
Test name
Test status
Simulation time 275532835 ps
CPU time 3.22 seconds
Started Jul 14 06:24:06 PM PDT 24
Finished Jul 14 06:24:11 PM PDT 24
Peak memory 200388 kb
Host smart-4ff2a84e-fdb6-404c-ac9f-8e251eefb950
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452477142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
452477142
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1148693654
Short name T544
Test name
Test status
Simulation time 136124856 ps
CPU time 1.01 seconds
Started Jul 14 06:24:06 PM PDT 24
Finished Jul 14 06:24:08 PM PDT 24
Peak memory 200216 kb
Host smart-bbcf9e16-f4bd-4cfa-94b6-b846fe6cd60f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148693654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
148693654
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2984802565
Short name T611
Test name
Test status
Simulation time 103945394 ps
CPU time 1.05 seconds
Started Jul 14 06:24:07 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 208440 kb
Host smart-4dc26ad8-164e-4b72-8690-3b9bf8616ac5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984802565 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2984802565
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1867860698
Short name T123
Test name
Test status
Simulation time 79022266 ps
CPU time 0.85 seconds
Started Jul 14 06:24:10 PM PDT 24
Finished Jul 14 06:24:12 PM PDT 24
Peak memory 200328 kb
Host smart-2f182af5-c99b-4150-8f76-ddd17cba136a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867860698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1867860698
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.924310914
Short name T573
Test name
Test status
Simulation time 146577101 ps
CPU time 1.4 seconds
Started Jul 14 06:24:06 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 200516 kb
Host smart-b6fd8f9a-e32c-47d3-a130-5b2a93b4d9a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924310914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.924310914
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2118468454
Short name T587
Test name
Test status
Simulation time 158109298 ps
CPU time 1.37 seconds
Started Jul 14 06:24:07 PM PDT 24
Finished Jul 14 06:24:10 PM PDT 24
Peak memory 200252 kb
Host smart-b2c744cc-5ec5-4030-a20b-2755a65e5e7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118468454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2118468454
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.487258656
Short name T572
Test name
Test status
Simulation time 942410050 ps
CPU time 3.87 seconds
Started Jul 14 06:24:04 PM PDT 24
Finished Jul 14 06:24:08 PM PDT 24
Peak memory 200472 kb
Host smart-4b2c055f-0bfd-4aa9-b80a-ea23059b3b60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487258656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
487258656
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.520256015
Short name T562
Test name
Test status
Simulation time 260693010 ps
CPU time 1.72 seconds
Started Jul 14 06:24:06 PM PDT 24
Finished Jul 14 06:24:08 PM PDT 24
Peak memory 200368 kb
Host smart-78d0984a-da0f-4660-bb22-6cd700ce072f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520256015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.520256015
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2676083797
Short name T598
Test name
Test status
Simulation time 801748636 ps
CPU time 4.74 seconds
Started Jul 14 06:24:06 PM PDT 24
Finished Jul 14 06:24:12 PM PDT 24
Peak memory 200468 kb
Host smart-5c2a0523-5195-4df8-a8d6-0d474b52cf70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676083797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
676083797
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4000845934
Short name T619
Test name
Test status
Simulation time 145611938 ps
CPU time 0.92 seconds
Started Jul 14 06:24:07 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 200136 kb
Host smart-adae4c8d-a3cd-4b22-b7e9-f7fadba55831
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000845934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.4
000845934
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.606444392
Short name T552
Test name
Test status
Simulation time 163749400 ps
CPU time 1.24 seconds
Started Jul 14 06:24:05 PM PDT 24
Finished Jul 14 06:24:07 PM PDT 24
Peak memory 208600 kb
Host smart-d5f997db-9eee-4576-93fc-24e8e23e45f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606444392 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.606444392
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1949824963
Short name T600
Test name
Test status
Simulation time 77813162 ps
CPU time 0.82 seconds
Started Jul 14 06:24:14 PM PDT 24
Finished Jul 14 06:24:16 PM PDT 24
Peak memory 200252 kb
Host smart-5da06295-a98f-4275-bab8-ffc0a340c13f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949824963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1949824963
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.855221330
Short name T121
Test name
Test status
Simulation time 75647972 ps
CPU time 0.96 seconds
Started Jul 14 06:24:07 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 200344 kb
Host smart-752c08f8-2f5e-4ad6-9911-3139bae8462b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855221330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.855221330
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.321811106
Short name T580
Test name
Test status
Simulation time 150860236 ps
CPU time 1.42 seconds
Started Jul 14 06:24:04 PM PDT 24
Finished Jul 14 06:24:06 PM PDT 24
Peak memory 208500 kb
Host smart-19f87431-1f01-4262-8803-597125d0529d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321811106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.321811106
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2490173540
Short name T151
Test name
Test status
Simulation time 882916238 ps
CPU time 2.98 seconds
Started Jul 14 06:24:03 PM PDT 24
Finished Jul 14 06:24:07 PM PDT 24
Peak memory 200496 kb
Host smart-e6170b5a-b4d0-4dcf-9d32-e013ec9377f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490173540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2490173540
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.406457620
Short name T569
Test name
Test status
Simulation time 110872168 ps
CPU time 0.95 seconds
Started Jul 14 06:24:05 PM PDT 24
Finished Jul 14 06:24:07 PM PDT 24
Peak memory 200420 kb
Host smart-d47f2e78-6a98-4cb1-909f-24335d18b1e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406457620 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.406457620
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1520574515
Short name T543
Test name
Test status
Simulation time 80147253 ps
CPU time 0.81 seconds
Started Jul 14 06:24:07 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 200200 kb
Host smart-e3c02985-53dd-4280-9e11-f8553b512171
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520574515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1520574515
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1347877176
Short name T553
Test name
Test status
Simulation time 114581872 ps
CPU time 1.34 seconds
Started Jul 14 06:24:05 PM PDT 24
Finished Jul 14 06:24:08 PM PDT 24
Peak memory 200492 kb
Host smart-0d9f23c5-c6ff-4aec-a3b8-6206674c8a9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347877176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1347877176
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1748996000
Short name T567
Test name
Test status
Simulation time 292459696 ps
CPU time 2.07 seconds
Started Jul 14 06:24:06 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 208600 kb
Host smart-ae5c87b7-f0e0-4c28-ae36-5ee8b2047fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748996000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1748996000
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2874914834
Short name T133
Test name
Test status
Simulation time 496084096 ps
CPU time 2.19 seconds
Started Jul 14 06:24:10 PM PDT 24
Finished Jul 14 06:24:13 PM PDT 24
Peak memory 200432 kb
Host smart-a2261c29-516b-4deb-91e4-7da28d168440
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874914834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2874914834
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1187456109
Short name T560
Test name
Test status
Simulation time 136983142 ps
CPU time 1.48 seconds
Started Jul 14 06:24:07 PM PDT 24
Finished Jul 14 06:24:10 PM PDT 24
Peak memory 208752 kb
Host smart-1df815b5-80e7-4610-bca8-14be08ba25dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187456109 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1187456109
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3348922851
Short name T548
Test name
Test status
Simulation time 74355619 ps
CPU time 0.84 seconds
Started Jul 14 06:24:04 PM PDT 24
Finished Jul 14 06:24:06 PM PDT 24
Peak memory 200208 kb
Host smart-74ad39f1-ae86-45df-bdf6-9a1e54fa1c90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348922851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3348922851
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2936686698
Short name T603
Test name
Test status
Simulation time 141105956 ps
CPU time 1.15 seconds
Started Jul 14 06:24:06 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 200232 kb
Host smart-23d66568-3523-431c-adad-08d25f3d6b5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936686698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2936686698
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3376081608
Short name T130
Test name
Test status
Simulation time 877578943 ps
CPU time 3.27 seconds
Started Jul 14 06:24:05 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 200540 kb
Host smart-3390d675-5e59-48b3-8002-cf3f57e1655e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376081608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3376081608
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3653114267
Short name T91
Test name
Test status
Simulation time 99782983 ps
CPU time 0.96 seconds
Started Jul 14 06:24:07 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 200352 kb
Host smart-ae39fb55-bee0-4847-bc39-10b95bfb829f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653114267 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3653114267
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2912444955
Short name T576
Test name
Test status
Simulation time 82701218 ps
CPU time 0.94 seconds
Started Jul 14 06:24:04 PM PDT 24
Finished Jul 14 06:24:06 PM PDT 24
Peak memory 200296 kb
Host smart-a247e106-43be-464d-83c4-03ebeac98939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912444955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2912444955
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1785052878
Short name T575
Test name
Test status
Simulation time 187860556 ps
CPU time 1.38 seconds
Started Jul 14 06:24:07 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 200368 kb
Host smart-4b5bcaa2-81b5-49cf-b2a7-0bf40587795e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785052878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1785052878
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2390621137
Short name T608
Test name
Test status
Simulation time 182871152 ps
CPU time 2.61 seconds
Started Jul 14 06:24:10 PM PDT 24
Finished Jul 14 06:24:13 PM PDT 24
Peak memory 208652 kb
Host smart-0040a761-4e6f-4e32-86e9-660167df13c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390621137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2390621137
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2457044008
Short name T152
Test name
Test status
Simulation time 899868004 ps
CPU time 2.89 seconds
Started Jul 14 06:24:05 PM PDT 24
Finished Jul 14 06:24:09 PM PDT 24
Peak memory 200512 kb
Host smart-4b7de216-489d-4316-af66-fd2d6932c254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457044008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2457044008
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1508395581
Short name T588
Test name
Test status
Simulation time 178409983 ps
CPU time 1.65 seconds
Started Jul 14 06:24:09 PM PDT 24
Finished Jul 14 06:24:12 PM PDT 24
Peak memory 208760 kb
Host smart-9a930cea-a235-47a2-b434-273acf045eb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508395581 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1508395581
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.900465482
Short name T550
Test name
Test status
Simulation time 61909866 ps
CPU time 0.79 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:13 PM PDT 24
Peak memory 200204 kb
Host smart-95e4a2c3-d51d-4fca-b072-c932304e3369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900465482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.900465482
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3023045320
Short name T609
Test name
Test status
Simulation time 216361997 ps
CPU time 1.52 seconds
Started Jul 14 06:24:10 PM PDT 24
Finished Jul 14 06:24:12 PM PDT 24
Peak memory 200536 kb
Host smart-c4f96266-0df9-4db5-b1c4-3a4790de3d0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023045320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3023045320
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1961011133
Short name T127
Test name
Test status
Simulation time 183240844 ps
CPU time 2.7 seconds
Started Jul 14 06:24:18 PM PDT 24
Finished Jul 14 06:24:22 PM PDT 24
Peak memory 208588 kb
Host smart-49071be3-79ac-4668-942e-83df06a9872f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961011133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1961011133
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3549180810
Short name T595
Test name
Test status
Simulation time 885998316 ps
CPU time 3.52 seconds
Started Jul 14 06:24:10 PM PDT 24
Finished Jul 14 06:24:15 PM PDT 24
Peak memory 200560 kb
Host smart-3a926965-9159-4ee5-8f2d-0fe62398df1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549180810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3549180810
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1475004236
Short name T607
Test name
Test status
Simulation time 200067461 ps
CPU time 1.2 seconds
Started Jul 14 06:24:12 PM PDT 24
Finished Jul 14 06:24:15 PM PDT 24
Peak memory 200504 kb
Host smart-2248c29a-8c2d-43c7-ab23-8e0fb47601a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475004236 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1475004236
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.23747534
Short name T545
Test name
Test status
Simulation time 62271991 ps
CPU time 0.78 seconds
Started Jul 14 06:24:10 PM PDT 24
Finished Jul 14 06:24:13 PM PDT 24
Peak memory 200304 kb
Host smart-d7d753b3-dc82-4e7a-85cb-6029a7fe1ef4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23747534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.23747534
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4105391595
Short name T117
Test name
Test status
Simulation time 134081859 ps
CPU time 1.08 seconds
Started Jul 14 06:24:09 PM PDT 24
Finished Jul 14 06:24:11 PM PDT 24
Peak memory 200356 kb
Host smart-543c4e3d-5451-4256-84ce-21916a7e4ab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105391595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.4105391595
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.212867042
Short name T93
Test name
Test status
Simulation time 245776842 ps
CPU time 1.68 seconds
Started Jul 14 06:24:11 PM PDT 24
Finished Jul 14 06:24:14 PM PDT 24
Peak memory 208588 kb
Host smart-24a5c105-cc39-4c8c-8b06-0a7903b33287
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212867042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.212867042
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1319687306
Short name T581
Test name
Test status
Simulation time 783584728 ps
CPU time 2.92 seconds
Started Jul 14 06:24:10 PM PDT 24
Finished Jul 14 06:24:13 PM PDT 24
Peak memory 200428 kb
Host smart-a9de8f29-dc32-43f8-82bd-6c06a4c59148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319687306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1319687306
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.697810795
Short name T155
Test name
Test status
Simulation time 86791461 ps
CPU time 0.82 seconds
Started Jul 14 07:05:40 PM PDT 24
Finished Jul 14 07:05:42 PM PDT 24
Peak memory 199976 kb
Host smart-df9ef3fd-b2d2-42a2-83db-a585b50cb3bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697810795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.697810795
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2923725541
Short name T50
Test name
Test status
Simulation time 1220749123 ps
CPU time 6.08 seconds
Started Jul 14 07:05:41 PM PDT 24
Finished Jul 14 07:05:48 PM PDT 24
Peak memory 221716 kb
Host smart-da4bca80-0db0-467f-bcfd-9d52acf1583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923725541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2923725541
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1124414226
Short name T203
Test name
Test status
Simulation time 243901885 ps
CPU time 1.14 seconds
Started Jul 14 07:05:42 PM PDT 24
Finished Jul 14 07:05:43 PM PDT 24
Peak memory 217560 kb
Host smart-4f19f82b-0ce1-4d46-8dec-723d1da4eee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124414226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1124414226
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2961562394
Short name T391
Test name
Test status
Simulation time 220570548 ps
CPU time 0.92 seconds
Started Jul 14 07:05:34 PM PDT 24
Finished Jul 14 07:05:35 PM PDT 24
Peak memory 200156 kb
Host smart-d7021ac3-5fac-4b0e-83b6-9ce95b275a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961562394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2961562394
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2391914055
Short name T532
Test name
Test status
Simulation time 1817961244 ps
CPU time 6.27 seconds
Started Jul 14 07:05:31 PM PDT 24
Finished Jul 14 07:05:38 PM PDT 24
Peak memory 200324 kb
Host smart-d9290038-6236-4278-aafa-24cad3e5501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391914055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2391914055
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4232931555
Short name T444
Test name
Test status
Simulation time 181316945 ps
CPU time 1.26 seconds
Started Jul 14 07:05:34 PM PDT 24
Finished Jul 14 07:05:36 PM PDT 24
Peak memory 200036 kb
Host smart-544846cf-e575-4f0b-a014-5c24226906f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232931555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4232931555
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1003520552
Short name T341
Test name
Test status
Simulation time 198911533 ps
CPU time 1.35 seconds
Started Jul 14 07:05:33 PM PDT 24
Finished Jul 14 07:05:36 PM PDT 24
Peak memory 200280 kb
Host smart-5502b174-b1d4-41c6-8707-3fd85b827ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003520552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1003520552
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1720906422
Short name T107
Test name
Test status
Simulation time 3738391382 ps
CPU time 13.5 seconds
Started Jul 14 07:05:38 PM PDT 24
Finished Jul 14 07:05:52 PM PDT 24
Peak memory 210124 kb
Host smart-1a07f9e5-806f-425e-a0ae-26ae5e75416f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720906422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1720906422
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1314192186
Short name T510
Test name
Test status
Simulation time 135199364 ps
CPU time 1.66 seconds
Started Jul 14 07:05:33 PM PDT 24
Finished Jul 14 07:05:36 PM PDT 24
Peak memory 200108 kb
Host smart-c3c37d5b-b74a-487b-8100-f13845032c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314192186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1314192186
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.4223657935
Short name T511
Test name
Test status
Simulation time 239611954 ps
CPU time 1.36 seconds
Started Jul 14 07:05:34 PM PDT 24
Finished Jul 14 07:05:36 PM PDT 24
Peak memory 200168 kb
Host smart-0584e5e9-00f0-4ffc-9b60-785679b044dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223657935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.4223657935
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3933757184
Short name T161
Test name
Test status
Simulation time 72192062 ps
CPU time 0.77 seconds
Started Jul 14 07:05:51 PM PDT 24
Finished Jul 14 07:05:54 PM PDT 24
Peak memory 199936 kb
Host smart-7b9c6a37-9373-421b-9852-ee69486ca1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933757184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3933757184
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.740535425
Short name T539
Test name
Test status
Simulation time 2361266469 ps
CPU time 8.46 seconds
Started Jul 14 07:05:38 PM PDT 24
Finished Jul 14 07:05:47 PM PDT 24
Peak memory 217824 kb
Host smart-11b42d4a-0b33-44ef-835d-f03f272bec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740535425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.740535425
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2860462511
Short name T226
Test name
Test status
Simulation time 245535867 ps
CPU time 1.07 seconds
Started Jul 14 07:05:42 PM PDT 24
Finished Jul 14 07:05:44 PM PDT 24
Peak memory 217532 kb
Host smart-7bdb1a9d-e78f-4fc7-83b9-07eb6aca8aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860462511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2860462511
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.39772363
Short name T300
Test name
Test status
Simulation time 207619321 ps
CPU time 0.89 seconds
Started Jul 14 07:05:38 PM PDT 24
Finished Jul 14 07:05:40 PM PDT 24
Peak memory 199908 kb
Host smart-18d1609d-5653-4669-9f86-4f29d80ed066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39772363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.39772363
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2890638754
Short name T244
Test name
Test status
Simulation time 1490332570 ps
CPU time 5.57 seconds
Started Jul 14 07:05:37 PM PDT 24
Finished Jul 14 07:05:43 PM PDT 24
Peak memory 200424 kb
Host smart-0ec68f8e-a1b3-4368-9dfa-c170535b63f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890638754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2890638754
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3018250492
Short name T70
Test name
Test status
Simulation time 18198137962 ps
CPU time 27.08 seconds
Started Jul 14 07:05:53 PM PDT 24
Finished Jul 14 07:06:22 PM PDT 24
Peak memory 217176 kb
Host smart-081d1c54-32b6-41ee-b04d-2dac403540af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018250492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3018250492
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.4115713718
Short name T541
Test name
Test status
Simulation time 122897727 ps
CPU time 1.2 seconds
Started Jul 14 07:05:40 PM PDT 24
Finished Jul 14 07:05:42 PM PDT 24
Peak memory 200552 kb
Host smart-5f584aab-633a-44a5-ae30-69b841d9cb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115713718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4115713718
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2250275544
Short name T352
Test name
Test status
Simulation time 2307295862 ps
CPU time 8.36 seconds
Started Jul 14 07:05:49 PM PDT 24
Finished Jul 14 07:05:59 PM PDT 24
Peak memory 200488 kb
Host smart-9c4d5d90-4eb1-431b-a6ac-f0dfd9c57bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250275544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2250275544
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.667130423
Short name T497
Test name
Test status
Simulation time 400913635 ps
CPU time 2.14 seconds
Started Jul 14 07:05:39 PM PDT 24
Finished Jul 14 07:05:42 PM PDT 24
Peak memory 200076 kb
Host smart-d1544a23-370e-467e-bc80-ffb50ed431a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667130423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.667130423
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3164380134
Short name T436
Test name
Test status
Simulation time 72829055 ps
CPU time 0.82 seconds
Started Jul 14 07:06:03 PM PDT 24
Finished Jul 14 07:06:05 PM PDT 24
Peak memory 199952 kb
Host smart-25dd019a-b526-4456-8c7f-15b232b7ce16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164380134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3164380134
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2592044330
Short name T489
Test name
Test status
Simulation time 1223382094 ps
CPU time 5.61 seconds
Started Jul 14 07:06:09 PM PDT 24
Finished Jul 14 07:06:16 PM PDT 24
Peak memory 221696 kb
Host smart-2dd6d4ec-e38c-4f7d-8d56-d3de93beb432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592044330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2592044330
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3282668397
Short name T289
Test name
Test status
Simulation time 243651787 ps
CPU time 1.15 seconds
Started Jul 14 07:06:05 PM PDT 24
Finished Jul 14 07:06:07 PM PDT 24
Peak memory 217524 kb
Host smart-60d16806-85db-4c2e-a6e4-e801ddab7966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282668397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3282668397
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2450601768
Short name T106
Test name
Test status
Simulation time 1756886249 ps
CPU time 6.1 seconds
Started Jul 14 07:06:04 PM PDT 24
Finished Jul 14 07:06:12 PM PDT 24
Peak memory 200412 kb
Host smart-7f0b1e48-d6ba-4b11-9475-8c30611887a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450601768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2450601768
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2847572708
Short name T141
Test name
Test status
Simulation time 137329805 ps
CPU time 1.05 seconds
Started Jul 14 07:06:06 PM PDT 24
Finished Jul 14 07:06:09 PM PDT 24
Peak memory 200144 kb
Host smart-020f58bc-31a8-4a23-9da2-a10ca02acff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847572708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2847572708
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3922349006
Short name T495
Test name
Test status
Simulation time 192411050 ps
CPU time 1.34 seconds
Started Jul 14 07:06:14 PM PDT 24
Finished Jul 14 07:06:16 PM PDT 24
Peak memory 199540 kb
Host smart-3ecd83d2-a968-4165-88bd-76d2afd62058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922349006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3922349006
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2088173371
Short name T276
Test name
Test status
Simulation time 6515997182 ps
CPU time 21.8 seconds
Started Jul 14 07:06:07 PM PDT 24
Finished Jul 14 07:06:31 PM PDT 24
Peak memory 200452 kb
Host smart-d01045fa-8d1e-42c9-a78f-f715cbd72d96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088173371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2088173371
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.4012452891
Short name T458
Test name
Test status
Simulation time 415988815 ps
CPU time 2.22 seconds
Started Jul 14 07:06:07 PM PDT 24
Finished Jul 14 07:06:11 PM PDT 24
Peak memory 200128 kb
Host smart-4ce36b11-5ab9-443c-b9ee-eae999eea7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012452891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.4012452891
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2523886495
Short name T392
Test name
Test status
Simulation time 85035288 ps
CPU time 0.88 seconds
Started Jul 14 07:06:06 PM PDT 24
Finished Jul 14 07:06:09 PM PDT 24
Peak memory 200128 kb
Host smart-b15dd783-64b1-43be-a411-1861d5dff763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523886495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2523886495
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1854802806
Short name T482
Test name
Test status
Simulation time 54902003 ps
CPU time 0.69 seconds
Started Jul 14 07:06:09 PM PDT 24
Finished Jul 14 07:06:11 PM PDT 24
Peak memory 199948 kb
Host smart-13e55fcc-86d8-4ca4-85b6-8f199028868c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854802806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1854802806
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1900590924
Short name T376
Test name
Test status
Simulation time 1232465371 ps
CPU time 5.7 seconds
Started Jul 14 07:06:05 PM PDT 24
Finished Jul 14 07:06:12 PM PDT 24
Peak memory 217572 kb
Host smart-2e2d6ba2-160e-4019-8e3e-cebd611f307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900590924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1900590924
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.688050540
Short name T2
Test name
Test status
Simulation time 244248007 ps
CPU time 1.11 seconds
Started Jul 14 07:06:08 PM PDT 24
Finished Jul 14 07:06:11 PM PDT 24
Peak memory 217528 kb
Host smart-1b427575-efb1-46ea-9a2b-09ac5b6451b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688050540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.688050540
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1468473961
Short name T363
Test name
Test status
Simulation time 169487535 ps
CPU time 0.83 seconds
Started Jul 14 07:06:05 PM PDT 24
Finished Jul 14 07:06:07 PM PDT 24
Peak memory 199980 kb
Host smart-87b547b0-e282-4e19-92d7-fc5e6bab46e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468473961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1468473961
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2092919328
Short name T27
Test name
Test status
Simulation time 1100747927 ps
CPU time 4.37 seconds
Started Jul 14 07:06:03 PM PDT 24
Finished Jul 14 07:06:08 PM PDT 24
Peak memory 200468 kb
Host smart-8a6a2c51-1196-4f27-9929-1fdc37514d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092919328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2092919328
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2273915681
Short name T504
Test name
Test status
Simulation time 176442856 ps
CPU time 1.23 seconds
Started Jul 14 07:06:06 PM PDT 24
Finished Jul 14 07:06:09 PM PDT 24
Peak memory 200068 kb
Host smart-4d15fd17-e0e0-4e88-8f13-181546aad1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273915681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2273915681
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3819283476
Short name T235
Test name
Test status
Simulation time 112196707 ps
CPU time 1.18 seconds
Started Jul 14 07:06:09 PM PDT 24
Finished Jul 14 07:06:12 PM PDT 24
Peak memory 200344 kb
Host smart-338de088-3e15-4553-a43e-b2b6343c2bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819283476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3819283476
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3088795176
Short name T59
Test name
Test status
Simulation time 141822339 ps
CPU time 1.8 seconds
Started Jul 14 07:06:08 PM PDT 24
Finished Jul 14 07:06:12 PM PDT 24
Peak memory 200004 kb
Host smart-f5631007-3170-4a97-99f0-03429ffb7c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088795176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3088795176
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3298136749
Short name T171
Test name
Test status
Simulation time 215693863 ps
CPU time 1.26 seconds
Started Jul 14 07:06:06 PM PDT 24
Finished Jul 14 07:06:09 PM PDT 24
Peak memory 200108 kb
Host smart-75301d42-ac99-4061-94e1-f46504256c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298136749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3298136749
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2226598248
Short name T383
Test name
Test status
Simulation time 75996824 ps
CPU time 0.84 seconds
Started Jul 14 07:06:07 PM PDT 24
Finished Jul 14 07:06:10 PM PDT 24
Peak memory 199880 kb
Host smart-0ba68a27-4a86-4804-ac5f-de870deea177
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226598248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2226598248
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2643131638
Short name T407
Test name
Test status
Simulation time 1923716286 ps
CPU time 6.8 seconds
Started Jul 14 07:06:14 PM PDT 24
Finished Jul 14 07:06:22 PM PDT 24
Peak memory 217764 kb
Host smart-4c96768a-ea86-4800-9a5d-3fe9f319b98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643131638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2643131638
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3291759489
Short name T530
Test name
Test status
Simulation time 244195723 ps
CPU time 1.13 seconds
Started Jul 14 07:06:07 PM PDT 24
Finished Jul 14 07:06:10 PM PDT 24
Peak memory 217472 kb
Host smart-166618b5-80d5-4164-98a8-f10e08ae73a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291759489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3291759489
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2552293290
Short name T234
Test name
Test status
Simulation time 77730018 ps
CPU time 0.71 seconds
Started Jul 14 07:06:03 PM PDT 24
Finished Jul 14 07:06:05 PM PDT 24
Peak memory 199972 kb
Host smart-4f769dd0-d39a-4abb-8d11-08f0286f6ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552293290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2552293290
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1483282536
Short name T216
Test name
Test status
Simulation time 1086787674 ps
CPU time 5.22 seconds
Started Jul 14 07:06:04 PM PDT 24
Finished Jul 14 07:06:10 PM PDT 24
Peak memory 200392 kb
Host smart-96bddc62-5f35-4ad2-bc7f-a437995e6e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483282536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1483282536
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2499546023
Short name T384
Test name
Test status
Simulation time 151816438 ps
CPU time 1.1 seconds
Started Jul 14 07:06:06 PM PDT 24
Finished Jul 14 07:06:09 PM PDT 24
Peak memory 200044 kb
Host smart-b1277295-3941-4d87-bdc6-5842298a084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499546023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2499546023
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2450641380
Short name T395
Test name
Test status
Simulation time 204483477 ps
CPU time 1.29 seconds
Started Jul 14 07:06:14 PM PDT 24
Finished Jul 14 07:06:16 PM PDT 24
Peak memory 200344 kb
Host smart-ea57d04e-4313-4d74-889c-899734cdeaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450641380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2450641380
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.309499036
Short name T459
Test name
Test status
Simulation time 231453995 ps
CPU time 1.37 seconds
Started Jul 14 07:06:08 PM PDT 24
Finished Jul 14 07:06:11 PM PDT 24
Peak memory 200068 kb
Host smart-61623aaa-b864-4712-a016-4dc5b1c738aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309499036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.309499036
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.592577670
Short name T205
Test name
Test status
Simulation time 458210485 ps
CPU time 2.45 seconds
Started Jul 14 07:06:14 PM PDT 24
Finished Jul 14 07:06:17 PM PDT 24
Peak memory 199436 kb
Host smart-c345e6ee-50c5-4c84-9db0-6dd6881a509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592577670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.592577670
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.879041169
Short name T83
Test name
Test status
Simulation time 173540883 ps
CPU time 1.24 seconds
Started Jul 14 07:06:06 PM PDT 24
Finished Jul 14 07:06:09 PM PDT 24
Peak memory 200376 kb
Host smart-dd676ecc-27e7-4994-af40-bebc1a789c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879041169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.879041169
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2585013260
Short name T179
Test name
Test status
Simulation time 69871282 ps
CPU time 0.73 seconds
Started Jul 14 07:06:13 PM PDT 24
Finished Jul 14 07:06:15 PM PDT 24
Peak memory 199968 kb
Host smart-d578ef8e-341b-46e8-8d56-43256d2dd235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585013260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2585013260
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3304077169
Short name T58
Test name
Test status
Simulation time 2350210444 ps
CPU time 8.58 seconds
Started Jul 14 07:06:13 PM PDT 24
Finished Jul 14 07:06:23 PM PDT 24
Peak memory 217892 kb
Host smart-7ae73c3b-5b4f-4ea5-a96d-7e8b636fda50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304077169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3304077169
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2314831396
Short name T187
Test name
Test status
Simulation time 244906825 ps
CPU time 0.99 seconds
Started Jul 14 07:06:15 PM PDT 24
Finished Jul 14 07:06:17 PM PDT 24
Peak memory 217376 kb
Host smart-6f7925a2-3042-4d06-a6e4-bd9b3f192d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314831396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2314831396
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.345760884
Short name T440
Test name
Test status
Simulation time 194242128 ps
CPU time 0.86 seconds
Started Jul 14 07:06:14 PM PDT 24
Finished Jul 14 07:06:16 PM PDT 24
Peak memory 199952 kb
Host smart-196b4ecd-dd56-415d-b0a8-ffb7f5179705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345760884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.345760884
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2565443491
Short name T102
Test name
Test status
Simulation time 1474219250 ps
CPU time 5.14 seconds
Started Jul 14 07:06:05 PM PDT 24
Finished Jul 14 07:06:11 PM PDT 24
Peak memory 200404 kb
Host smart-d979a036-d877-4a7a-8bf6-b1d078e595d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565443491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2565443491
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1578951623
Short name T422
Test name
Test status
Simulation time 103873452 ps
CPU time 0.97 seconds
Started Jul 14 07:06:09 PM PDT 24
Finished Jul 14 07:06:12 PM PDT 24
Peak memory 200180 kb
Host smart-d89291dc-da87-489a-ae75-4f9df1c30e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578951623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1578951623
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.835518455
Short name T325
Test name
Test status
Simulation time 116359374 ps
CPU time 1.26 seconds
Started Jul 14 07:06:08 PM PDT 24
Finished Jul 14 07:06:11 PM PDT 24
Peak memory 200332 kb
Host smart-0b977d78-d2f4-4dbf-856a-7095f22c0917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835518455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.835518455
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1062532428
Short name T86
Test name
Test status
Simulation time 8750436654 ps
CPU time 29.04 seconds
Started Jul 14 07:06:15 PM PDT 24
Finished Jul 14 07:06:45 PM PDT 24
Peak memory 200368 kb
Host smart-ad0bff33-e3af-48b9-b7eb-483c0a3ac07d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062532428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1062532428
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.4170746236
Short name T486
Test name
Test status
Simulation time 462247147 ps
CPU time 2.57 seconds
Started Jul 14 07:06:08 PM PDT 24
Finished Jul 14 07:06:12 PM PDT 24
Peak memory 200144 kb
Host smart-e00e24a3-4aac-4af0-8376-d7cb2e5a52a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170746236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.4170746236
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4021522270
Short name T162
Test name
Test status
Simulation time 111194816 ps
CPU time 1.01 seconds
Started Jul 14 07:06:07 PM PDT 24
Finished Jul 14 07:06:10 PM PDT 24
Peak memory 200088 kb
Host smart-343742b8-edb4-4e9a-88ee-d2136eeab4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021522270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4021522270
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.667519455
Short name T72
Test name
Test status
Simulation time 78580504 ps
CPU time 0.82 seconds
Started Jul 14 07:06:12 PM PDT 24
Finished Jul 14 07:06:13 PM PDT 24
Peak memory 200148 kb
Host smart-b2b8141d-2316-4653-9473-961c8ff9ddb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667519455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.667519455
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.738747260
Short name T498
Test name
Test status
Simulation time 2363047568 ps
CPU time 8.55 seconds
Started Jul 14 07:06:11 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 217780 kb
Host smart-288156a9-db39-4886-8690-babe7d5c4f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738747260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.738747260
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1110637101
Short name T239
Test name
Test status
Simulation time 244705607 ps
CPU time 1.07 seconds
Started Jul 14 07:06:11 PM PDT 24
Finished Jul 14 07:06:12 PM PDT 24
Peak memory 217528 kb
Host smart-f8542777-24f0-4572-b998-e1cf5ed9ada0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110637101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1110637101
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3418059014
Short name T356
Test name
Test status
Simulation time 86116691 ps
CPU time 0.78 seconds
Started Jul 14 07:06:11 PM PDT 24
Finished Jul 14 07:06:13 PM PDT 24
Peak memory 199928 kb
Host smart-0fe020a9-31a3-42eb-a2a2-889c52474ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418059014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3418059014
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3639249485
Short name T524
Test name
Test status
Simulation time 1420383558 ps
CPU time 5.59 seconds
Started Jul 14 07:06:13 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 200432 kb
Host smart-22cbe376-7169-4afb-844f-b58f2a18b1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639249485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3639249485
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3309469414
Short name T519
Test name
Test status
Simulation time 135833411 ps
CPU time 1.12 seconds
Started Jul 14 07:06:13 PM PDT 24
Finished Jul 14 07:06:15 PM PDT 24
Peak memory 200152 kb
Host smart-de492f53-5833-43a2-882e-c54d691a646b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309469414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3309469414
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2497437521
Short name T200
Test name
Test status
Simulation time 209660183 ps
CPU time 1.35 seconds
Started Jul 14 07:06:15 PM PDT 24
Finished Jul 14 07:06:18 PM PDT 24
Peak memory 200336 kb
Host smart-05bb044c-d0d3-4d82-8ec5-f8d32fd631cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497437521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2497437521
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2155429790
Short name T277
Test name
Test status
Simulation time 362319770 ps
CPU time 1.98 seconds
Started Jul 14 07:06:14 PM PDT 24
Finished Jul 14 07:06:17 PM PDT 24
Peak memory 200324 kb
Host smart-feb58c67-41ab-4552-b571-832b76e15e74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155429790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2155429790
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.874032126
Short name T146
Test name
Test status
Simulation time 495485168 ps
CPU time 2.67 seconds
Started Jul 14 07:06:14 PM PDT 24
Finished Jul 14 07:06:18 PM PDT 24
Peak memory 200132 kb
Host smart-38a1ecb4-c629-4b1f-b2d2-de090a873c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874032126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.874032126
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1461452948
Short name T153
Test name
Test status
Simulation time 158071547 ps
CPU time 1.25 seconds
Started Jul 14 07:06:15 PM PDT 24
Finished Jul 14 07:06:17 PM PDT 24
Peak memory 200332 kb
Host smart-a2a2793c-ffd3-4276-a002-18f383bb796a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461452948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1461452948
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.542155544
Short name T78
Test name
Test status
Simulation time 95955853 ps
CPU time 0.84 seconds
Started Jul 14 07:06:17 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 199860 kb
Host smart-5541392b-10f8-4c2b-a78c-b51ce24e198c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542155544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.542155544
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2075301844
Short name T462
Test name
Test status
Simulation time 1886421611 ps
CPU time 7.72 seconds
Started Jul 14 07:06:21 PM PDT 24
Finished Jul 14 07:06:29 PM PDT 24
Peak memory 217568 kb
Host smart-ed4807a0-7f04-4b79-bfa8-d001b153041d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075301844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2075301844
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3831166150
Short name T224
Test name
Test status
Simulation time 246232510 ps
CPU time 1 seconds
Started Jul 14 07:06:21 PM PDT 24
Finished Jul 14 07:06:22 PM PDT 24
Peak memory 217540 kb
Host smart-7995deab-1f33-4e4b-94e0-7fa7b234e0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831166150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3831166150
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1012845507
Short name T447
Test name
Test status
Simulation time 223492608 ps
CPU time 0.94 seconds
Started Jul 14 07:06:12 PM PDT 24
Finished Jul 14 07:06:14 PM PDT 24
Peak memory 199724 kb
Host smart-3758b785-c3b6-4eee-830c-6dc94c79b8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012845507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1012845507
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1761186516
Short name T369
Test name
Test status
Simulation time 2138096352 ps
CPU time 7.61 seconds
Started Jul 14 07:06:15 PM PDT 24
Finished Jul 14 07:06:24 PM PDT 24
Peak memory 200404 kb
Host smart-98a5b54d-47ed-4a5d-8573-764c7cd4bc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761186516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1761186516
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.615302272
Short name T256
Test name
Test status
Simulation time 111579814 ps
CPU time 1.01 seconds
Started Jul 14 07:06:15 PM PDT 24
Finished Jul 14 07:06:17 PM PDT 24
Peak memory 200136 kb
Host smart-0f6b1c46-da32-431a-9832-1cb569ab99a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615302272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.615302272
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.4149100206
Short name T176
Test name
Test status
Simulation time 109234356 ps
CPU time 1.19 seconds
Started Jul 14 07:06:15 PM PDT 24
Finished Jul 14 07:06:17 PM PDT 24
Peak memory 200348 kb
Host smart-820e5787-bc13-4876-ae65-c242b5ca730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149100206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4149100206
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2317880983
Short name T425
Test name
Test status
Simulation time 514787542 ps
CPU time 2.44 seconds
Started Jul 14 07:06:20 PM PDT 24
Finished Jul 14 07:06:24 PM PDT 24
Peak memory 200348 kb
Host smart-7c1612d3-9845-491b-8726-b2b8f26497ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317880983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2317880983
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2281739635
Short name T290
Test name
Test status
Simulation time 406944404 ps
CPU time 2.42 seconds
Started Jul 14 07:06:11 PM PDT 24
Finished Jul 14 07:06:14 PM PDT 24
Peak memory 200156 kb
Host smart-c3bfb792-b6f4-4186-94e7-8ac01eb3c13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281739635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2281739635
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2384818389
Short name T343
Test name
Test status
Simulation time 214160566 ps
CPU time 1.29 seconds
Started Jul 14 07:06:12 PM PDT 24
Finished Jul 14 07:06:14 PM PDT 24
Peak memory 199876 kb
Host smart-a5d64db5-ba54-4036-a39c-e517175d38bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384818389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2384818389
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2794894016
Short name T435
Test name
Test status
Simulation time 75533016 ps
CPU time 0.77 seconds
Started Jul 14 07:06:18 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 199928 kb
Host smart-e4455504-a1f1-487f-b420-580fb81b4613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794894016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2794894016
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2234636202
Short name T442
Test name
Test status
Simulation time 1883620008 ps
CPU time 7.1 seconds
Started Jul 14 07:06:20 PM PDT 24
Finished Jul 14 07:06:28 PM PDT 24
Peak memory 221616 kb
Host smart-229eb2f6-fa76-4f5a-9ae6-e7e8acb05509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234636202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2234636202
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.588608353
Short name T471
Test name
Test status
Simulation time 243981861 ps
CPU time 1.2 seconds
Started Jul 14 07:06:17 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 217720 kb
Host smart-481d5260-3395-4271-8935-e77357eeb9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588608353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.588608353
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2243581711
Short name T20
Test name
Test status
Simulation time 197566534 ps
CPU time 0.83 seconds
Started Jul 14 07:06:17 PM PDT 24
Finished Jul 14 07:06:18 PM PDT 24
Peak memory 199868 kb
Host smart-4929e839-df5c-4093-9f0f-27d099d01a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243581711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2243581711
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2443924949
Short name T302
Test name
Test status
Simulation time 847537157 ps
CPU time 4.02 seconds
Started Jul 14 07:06:20 PM PDT 24
Finished Jul 14 07:06:25 PM PDT 24
Peak memory 200304 kb
Host smart-01717954-f7cd-489b-9399-573564a25004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443924949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2443924949
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.622340320
Short name T173
Test name
Test status
Simulation time 149993937 ps
CPU time 1.09 seconds
Started Jul 14 07:06:18 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 200120 kb
Host smart-83297a9b-76c5-4b53-a274-e2a70ca195fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622340320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.622340320
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2828327531
Short name T25
Test name
Test status
Simulation time 109619981 ps
CPU time 1.14 seconds
Started Jul 14 07:06:21 PM PDT 24
Finished Jul 14 07:06:23 PM PDT 24
Peak memory 200416 kb
Host smart-957ace00-1c49-4803-a629-1474f0017bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828327531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2828327531
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2566176688
Short name T135
Test name
Test status
Simulation time 9983740994 ps
CPU time 33.47 seconds
Started Jul 14 07:06:18 PM PDT 24
Finished Jul 14 07:06:53 PM PDT 24
Peak memory 208696 kb
Host smart-a8858b68-ea0d-48ef-a453-53ba9e1c04ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566176688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2566176688
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2617220484
Short name T534
Test name
Test status
Simulation time 342833964 ps
CPU time 2.17 seconds
Started Jul 14 07:06:18 PM PDT 24
Finished Jul 14 07:06:21 PM PDT 24
Peak memory 208364 kb
Host smart-746ba65e-14cc-453e-aded-cf2ef6a14c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617220484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2617220484
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2009313192
Short name T500
Test name
Test status
Simulation time 136662620 ps
CPU time 0.96 seconds
Started Jul 14 07:06:17 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 200104 kb
Host smart-74b96fc8-7bb8-4056-aa82-4588649c4483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009313192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2009313192
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1146213032
Short name T165
Test name
Test status
Simulation time 76362907 ps
CPU time 0.8 seconds
Started Jul 14 07:06:17 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 199864 kb
Host smart-2b2627cb-7e41-4fea-aa9f-40d74ee86fa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146213032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1146213032
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1503648479
Short name T334
Test name
Test status
Simulation time 2366806360 ps
CPU time 8.27 seconds
Started Jul 14 07:06:18 PM PDT 24
Finished Jul 14 07:06:27 PM PDT 24
Peak memory 221840 kb
Host smart-a3bf358c-964a-4a09-b1e5-ef3de0fd1e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503648479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1503648479
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1335152743
Short name T266
Test name
Test status
Simulation time 243743208 ps
CPU time 1.13 seconds
Started Jul 14 07:06:17 PM PDT 24
Finished Jul 14 07:06:19 PM PDT 24
Peak memory 217536 kb
Host smart-25b6f062-19a3-4dfd-bc27-1aa20afe8c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335152743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1335152743
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3911800534
Short name T455
Test name
Test status
Simulation time 161615066 ps
CPU time 0.83 seconds
Started Jul 14 07:06:18 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 199936 kb
Host smart-9c72d19b-bd03-42d9-bb83-55adb617ee9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911800534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3911800534
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1995480430
Short name T230
Test name
Test status
Simulation time 1667583321 ps
CPU time 6.76 seconds
Started Jul 14 07:06:15 PM PDT 24
Finished Jul 14 07:06:23 PM PDT 24
Peak memory 200424 kb
Host smart-4f76c99e-9f31-44f3-9e7d-cb9ae1041520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995480430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1995480430
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3067560298
Short name T156
Test name
Test status
Simulation time 102823490 ps
CPU time 0.97 seconds
Started Jul 14 07:06:18 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 200040 kb
Host smart-c92eb5e7-d566-4980-9d77-323048afe5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067560298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3067560298
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2144879911
Short name T424
Test name
Test status
Simulation time 250952238 ps
CPU time 1.52 seconds
Started Jul 14 07:06:17 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 200328 kb
Host smart-c9dcc0a8-b842-4d94-b2db-7ae3e7f990be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144879911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2144879911
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1092206111
Short name T274
Test name
Test status
Simulation time 3455484690 ps
CPU time 11.71 seconds
Started Jul 14 07:06:22 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 200640 kb
Host smart-618475d9-b0c9-4771-b679-32346aaa369f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092206111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1092206111
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3298681963
Short name T269
Test name
Test status
Simulation time 358957722 ps
CPU time 2.13 seconds
Started Jul 14 07:06:20 PM PDT 24
Finished Jul 14 07:06:23 PM PDT 24
Peak memory 200176 kb
Host smart-693dc3b8-1e46-495d-bef8-041b66fbfc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298681963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3298681963
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.731320758
Short name T362
Test name
Test status
Simulation time 148788021 ps
CPU time 1.12 seconds
Started Jul 14 07:06:17 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 200132 kb
Host smart-e2c180ab-057e-4338-b159-8e3d9541b401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731320758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.731320758
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2043409633
Short name T487
Test name
Test status
Simulation time 71954567 ps
CPU time 0.73 seconds
Started Jul 14 07:06:29 PM PDT 24
Finished Jul 14 07:06:31 PM PDT 24
Peak memory 199940 kb
Host smart-33673e33-6c99-4902-b6c9-f52701b11f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043409633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2043409633
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3343350245
Short name T43
Test name
Test status
Simulation time 1889163553 ps
CPU time 7.06 seconds
Started Jul 14 07:06:20 PM PDT 24
Finished Jul 14 07:06:28 PM PDT 24
Peak memory 217748 kb
Host smart-eaafe0a2-86e3-4a5b-97b2-6f159e86448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343350245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3343350245
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1426376856
Short name T286
Test name
Test status
Simulation time 244152862 ps
CPU time 1.11 seconds
Started Jul 14 07:06:21 PM PDT 24
Finished Jul 14 07:06:23 PM PDT 24
Peak memory 217544 kb
Host smart-2fbb79ed-63b2-492d-8733-8e4cdcb9b5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426376856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1426376856
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.705489454
Short name T433
Test name
Test status
Simulation time 104068266 ps
CPU time 0.78 seconds
Started Jul 14 07:06:17 PM PDT 24
Finished Jul 14 07:06:19 PM PDT 24
Peak memory 199972 kb
Host smart-f7583cba-d9e2-4360-a3e8-7cdc7c51f882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705489454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.705489454
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1036052467
Short name T245
Test name
Test status
Simulation time 986867442 ps
CPU time 4.51 seconds
Started Jul 14 07:06:20 PM PDT 24
Finished Jul 14 07:06:25 PM PDT 24
Peak memory 200432 kb
Host smart-f7c51a3a-338f-4133-97b2-099a99e62ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036052467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1036052467
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1926438778
Short name T499
Test name
Test status
Simulation time 147901291 ps
CPU time 1.13 seconds
Started Jul 14 07:06:18 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 200116 kb
Host smart-a2f2c4f9-780e-4b1d-9200-f35537d8757a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926438778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1926438778
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.40694413
Short name T231
Test name
Test status
Simulation time 187789180 ps
CPU time 1.4 seconds
Started Jul 14 07:06:17 PM PDT 24
Finished Jul 14 07:06:19 PM PDT 24
Peak memory 200324 kb
Host smart-a06763f4-edce-4b85-9b36-4a38d0fe589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40694413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.40694413
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.294959166
Short name T417
Test name
Test status
Simulation time 2992806233 ps
CPU time 11.54 seconds
Started Jul 14 07:06:24 PM PDT 24
Finished Jul 14 07:06:37 PM PDT 24
Peak memory 200488 kb
Host smart-b789610c-1d75-4117-bfb5-4db6bf683884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294959166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.294959166
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1945266758
Short name T466
Test name
Test status
Simulation time 361490542 ps
CPU time 2.32 seconds
Started Jul 14 07:06:19 PM PDT 24
Finished Jul 14 07:06:23 PM PDT 24
Peak memory 200188 kb
Host smart-71073150-f499-448a-a231-7366aeb0b2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945266758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1945266758
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1796519195
Short name T52
Test name
Test status
Simulation time 158746945 ps
CPU time 1.26 seconds
Started Jul 14 07:06:18 PM PDT 24
Finished Jul 14 07:06:21 PM PDT 24
Peak memory 200232 kb
Host smart-aee9e99d-7e67-4dbd-97bb-d147e3d3d843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796519195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1796519195
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.4292361596
Short name T492
Test name
Test status
Simulation time 62829331 ps
CPU time 0.71 seconds
Started Jul 14 07:06:23 PM PDT 24
Finished Jul 14 07:06:24 PM PDT 24
Peak memory 199960 kb
Host smart-583b96d8-bd0d-48fa-a7d1-a30d0f25d93a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292361596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4292361596
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3051112570
Short name T528
Test name
Test status
Simulation time 1233952573 ps
CPU time 5.83 seconds
Started Jul 14 07:06:24 PM PDT 24
Finished Jul 14 07:06:31 PM PDT 24
Peak memory 216876 kb
Host smart-4f5453a9-084f-4d39-93a0-39fd196e4924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051112570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3051112570
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.210112696
Short name T311
Test name
Test status
Simulation time 244607604 ps
CPU time 1.05 seconds
Started Jul 14 07:06:28 PM PDT 24
Finished Jul 14 07:06:30 PM PDT 24
Peak memory 217516 kb
Host smart-f67640df-f0bd-4a22-96ef-b3acc0187a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210112696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.210112696
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1615061921
Short name T488
Test name
Test status
Simulation time 159374684 ps
CPU time 0.88 seconds
Started Jul 14 07:06:24 PM PDT 24
Finished Jul 14 07:06:26 PM PDT 24
Peak memory 199968 kb
Host smart-9f047832-3992-474e-9664-e10e9f0085c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615061921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1615061921
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3965105517
Short name T299
Test name
Test status
Simulation time 980821763 ps
CPU time 4.95 seconds
Started Jul 14 07:06:24 PM PDT 24
Finished Jul 14 07:06:30 PM PDT 24
Peak memory 200416 kb
Host smart-57e6612f-c8e0-44ec-bd06-442edc61696b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965105517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3965105517
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1200459112
Short name T201
Test name
Test status
Simulation time 143999615 ps
CPU time 1.03 seconds
Started Jul 14 07:06:22 PM PDT 24
Finished Jul 14 07:06:24 PM PDT 24
Peak memory 200124 kb
Host smart-23e6ad99-6eb3-4cd2-85a1-dbe10267bf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200459112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1200459112
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1636713297
Short name T14
Test name
Test status
Simulation time 121957974 ps
CPU time 1.26 seconds
Started Jul 14 07:06:24 PM PDT 24
Finished Jul 14 07:06:27 PM PDT 24
Peak memory 200372 kb
Host smart-53713db3-2186-4e7f-aa80-769fefd77a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636713297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1636713297
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1623270547
Short name T490
Test name
Test status
Simulation time 194954324 ps
CPU time 1.34 seconds
Started Jul 14 07:06:22 PM PDT 24
Finished Jul 14 07:06:25 PM PDT 24
Peak memory 200176 kb
Host smart-7e19d539-4504-43ab-9e74-55fdfa609d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623270547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1623270547
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3640728194
Short name T525
Test name
Test status
Simulation time 127741313 ps
CPU time 1.56 seconds
Started Jul 14 07:06:28 PM PDT 24
Finished Jul 14 07:06:31 PM PDT 24
Peak memory 200112 kb
Host smart-42e1a904-0161-462e-adad-5f44910e3f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640728194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3640728194
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3244724282
Short name T111
Test name
Test status
Simulation time 179998040 ps
CPU time 1.23 seconds
Started Jul 14 07:06:24 PM PDT 24
Finished Jul 14 07:06:27 PM PDT 24
Peak memory 200048 kb
Host smart-67c5a045-0467-4e28-9bad-8c77e6730b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244724282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3244724282
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.4026675743
Short name T54
Test name
Test status
Simulation time 68734243 ps
CPU time 0.76 seconds
Started Jul 14 07:05:45 PM PDT 24
Finished Jul 14 07:05:47 PM PDT 24
Peak memory 199912 kb
Host smart-c57adcdd-a3ce-424d-b8bb-4c93b462926d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026675743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4026675743
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1219816522
Short name T49
Test name
Test status
Simulation time 244164850 ps
CPU time 1.1 seconds
Started Jul 14 07:05:53 PM PDT 24
Finished Jul 14 07:05:55 PM PDT 24
Peak memory 217500 kb
Host smart-7facf56a-f062-4b7d-9237-05f167fe9b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219816522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1219816522
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1322465155
Short name T419
Test name
Test status
Simulation time 81782936 ps
CPU time 0.76 seconds
Started Jul 14 07:05:47 PM PDT 24
Finished Jul 14 07:05:49 PM PDT 24
Peak memory 199976 kb
Host smart-ede1ab24-01ec-4416-85c0-1b98f5294de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322465155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1322465155
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3860195122
Short name T332
Test name
Test status
Simulation time 881989786 ps
CPU time 3.99 seconds
Started Jul 14 07:05:47 PM PDT 24
Finished Jul 14 07:05:52 PM PDT 24
Peak memory 200376 kb
Host smart-057d069c-264d-4a35-b9cf-eb87c705b822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860195122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3860195122
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2847543625
Short name T74
Test name
Test status
Simulation time 16686581208 ps
CPU time 24.44 seconds
Started Jul 14 07:05:45 PM PDT 24
Finished Jul 14 07:06:10 PM PDT 24
Peak memory 217264 kb
Host smart-1c5db4cb-5b2d-4ca4-a13b-a9636bfe2b07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847543625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2847543625
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.856512938
Short name T522
Test name
Test status
Simulation time 181496922 ps
CPU time 1.17 seconds
Started Jul 14 07:05:46 PM PDT 24
Finished Jul 14 07:05:48 PM PDT 24
Peak memory 200156 kb
Host smart-3e589a75-a2d6-4e30-84c1-dcb35108cfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856512938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.856512938
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1263208497
Short name T382
Test name
Test status
Simulation time 200121116 ps
CPU time 1.29 seconds
Started Jul 14 07:05:46 PM PDT 24
Finished Jul 14 07:05:49 PM PDT 24
Peak memory 200344 kb
Host smart-112c5bec-c62a-4167-a5e7-fb9bb18afbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263208497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1263208497
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.982149286
Short name T84
Test name
Test status
Simulation time 1012289224 ps
CPU time 4.55 seconds
Started Jul 14 07:05:46 PM PDT 24
Finished Jul 14 07:05:51 PM PDT 24
Peak memory 200372 kb
Host smart-d0ce4213-5bee-412a-9b49-f2dc25187255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982149286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.982149286
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2509488382
Short name T328
Test name
Test status
Simulation time 321910760 ps
CPU time 2.01 seconds
Started Jul 14 07:05:47 PM PDT 24
Finished Jul 14 07:05:50 PM PDT 24
Peak memory 200144 kb
Host smart-640f1984-8228-45ca-b253-a2105ad98527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509488382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2509488382
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3556839123
Short name T430
Test name
Test status
Simulation time 118651791 ps
CPU time 0.96 seconds
Started Jul 14 07:05:45 PM PDT 24
Finished Jul 14 07:05:47 PM PDT 24
Peak memory 200160 kb
Host smart-48d4391b-bdf9-4c5b-9f06-f8a8713f5597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556839123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3556839123
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2737960920
Short name T505
Test name
Test status
Simulation time 63402674 ps
CPU time 0.77 seconds
Started Jul 14 07:06:26 PM PDT 24
Finished Jul 14 07:06:28 PM PDT 24
Peak memory 199880 kb
Host smart-4c49fdc0-4613-4244-afec-4d9bdb469b60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737960920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2737960920
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.4230857947
Short name T36
Test name
Test status
Simulation time 1889334550 ps
CPU time 7.82 seconds
Started Jul 14 07:06:25 PM PDT 24
Finished Jul 14 07:06:33 PM PDT 24
Peak memory 217440 kb
Host smart-3c9373e0-9788-4187-83e9-92a984a702d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230857947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.4230857947
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1592693900
Short name T306
Test name
Test status
Simulation time 244487291 ps
CPU time 1.07 seconds
Started Jul 14 07:06:23 PM PDT 24
Finished Jul 14 07:06:25 PM PDT 24
Peak memory 217552 kb
Host smart-6ef4614d-3e6f-4037-9c24-630c6fdba961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592693900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1592693900
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3531271794
Short name T12
Test name
Test status
Simulation time 230957757 ps
CPU time 0.98 seconds
Started Jul 14 07:06:29 PM PDT 24
Finished Jul 14 07:06:32 PM PDT 24
Peak memory 199988 kb
Host smart-e7f84228-4d61-4bfd-802e-c6a2abd4cc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531271794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3531271794
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.207361794
Short name T517
Test name
Test status
Simulation time 1661245533 ps
CPU time 6.76 seconds
Started Jul 14 07:06:26 PM PDT 24
Finished Jul 14 07:06:34 PM PDT 24
Peak memory 200472 kb
Host smart-d912c9a8-a8ba-440e-8005-e253db7b544e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207361794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.207361794
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2816409370
Short name T166
Test name
Test status
Simulation time 179782287 ps
CPU time 1.2 seconds
Started Jul 14 07:06:26 PM PDT 24
Finished Jul 14 07:06:28 PM PDT 24
Peak memory 200120 kb
Host smart-c91194bc-2edb-404a-a483-875d467429b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816409370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2816409370
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.4001959184
Short name T3
Test name
Test status
Simulation time 241698428 ps
CPU time 1.4 seconds
Started Jul 14 07:06:26 PM PDT 24
Finished Jul 14 07:06:28 PM PDT 24
Peak memory 200372 kb
Host smart-148437e9-d9fe-478d-a118-c8e1f5e8f631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001959184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.4001959184
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1663543664
Short name T371
Test name
Test status
Simulation time 8306064171 ps
CPU time 26.17 seconds
Started Jul 14 07:06:24 PM PDT 24
Finished Jul 14 07:06:51 PM PDT 24
Peak memory 208584 kb
Host smart-2d2d7e14-48ca-4664-becf-c41edc7a915f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663543664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1663543664
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3504198712
Short name T494
Test name
Test status
Simulation time 299742613 ps
CPU time 1.86 seconds
Started Jul 14 07:06:26 PM PDT 24
Finished Jul 14 07:06:29 PM PDT 24
Peak memory 200136 kb
Host smart-7646e6df-bc66-44be-b7a5-c521e70c129a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504198712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3504198712
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3537502421
Short name T537
Test name
Test status
Simulation time 143610326 ps
CPU time 1.06 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:34 PM PDT 24
Peak memory 200160 kb
Host smart-35f19a76-fb61-4708-8405-bb93a3d9040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537502421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3537502421
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1500126035
Short name T181
Test name
Test status
Simulation time 64071302 ps
CPU time 0.76 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:34 PM PDT 24
Peak memory 199944 kb
Host smart-e56e0332-3493-46eb-be24-99fa2dcfde11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500126035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1500126035
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.368070947
Short name T358
Test name
Test status
Simulation time 2358556876 ps
CPU time 9.23 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:41 PM PDT 24
Peak memory 217904 kb
Host smart-4ab229e4-d24b-4830-8742-5cfafa8dcca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368070947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.368070947
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1049384663
Short name T240
Test name
Test status
Simulation time 244691765 ps
CPU time 1.09 seconds
Started Jul 14 07:06:25 PM PDT 24
Finished Jul 14 07:06:27 PM PDT 24
Peak memory 217436 kb
Host smart-9f1fae0f-d6d0-4d72-bda6-cd224f101daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049384663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1049384663
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.323724304
Short name T408
Test name
Test status
Simulation time 237331942 ps
CPU time 0.98 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:34 PM PDT 24
Peak memory 199968 kb
Host smart-5a967358-676d-495c-bf4c-404661fb6d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323724304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.323724304
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1585972311
Short name T507
Test name
Test status
Simulation time 1166163850 ps
CPU time 4.62 seconds
Started Jul 14 07:06:29 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 200448 kb
Host smart-e12f37da-18ac-4185-9474-7105267c6361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585972311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1585972311
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.353093944
Short name T418
Test name
Test status
Simulation time 161690878 ps
CPU time 1.25 seconds
Started Jul 14 07:06:24 PM PDT 24
Finished Jul 14 07:06:27 PM PDT 24
Peak memory 200152 kb
Host smart-c2f22656-ac5c-4266-8071-900757794104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353093944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.353093944
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1426416721
Short name T405
Test name
Test status
Simulation time 124249548 ps
CPU time 1.16 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:33 PM PDT 24
Peak memory 200340 kb
Host smart-f5986121-a85a-4a43-810d-d9d352a69f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426416721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1426416721
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2532680277
Short name T167
Test name
Test status
Simulation time 370912285 ps
CPU time 2.23 seconds
Started Jul 14 07:06:24 PM PDT 24
Finished Jul 14 07:06:27 PM PDT 24
Peak memory 200156 kb
Host smart-fbba1dc8-7efd-4c2b-afb7-79a98c280b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532680277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2532680277
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3363453552
Short name T378
Test name
Test status
Simulation time 175984136 ps
CPU time 1.19 seconds
Started Jul 14 07:06:26 PM PDT 24
Finished Jul 14 07:06:28 PM PDT 24
Peak memory 200128 kb
Host smart-4be2b170-c0a7-4cb5-b2e4-01da97dfe68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363453552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3363453552
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.613225337
Short name T464
Test name
Test status
Simulation time 67118338 ps
CPU time 0.76 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:33 PM PDT 24
Peak memory 199976 kb
Host smart-c70d4c0a-78ce-4f77-aa27-3ce257c7c56d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613225337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.613225337
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1614182261
Short name T31
Test name
Test status
Simulation time 2171917426 ps
CPU time 7.56 seconds
Started Jul 14 07:06:22 PM PDT 24
Finished Jul 14 07:06:31 PM PDT 24
Peak memory 221720 kb
Host smart-c65a32de-73a2-4789-8187-dc2abfc7b276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614182261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1614182261
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1026734948
Short name T375
Test name
Test status
Simulation time 243691118 ps
CPU time 1.09 seconds
Started Jul 14 07:06:26 PM PDT 24
Finished Jul 14 07:06:28 PM PDT 24
Peak memory 217544 kb
Host smart-681227f6-8150-44e3-bbda-060776b302b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026734948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1026734948
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1731971843
Short name T403
Test name
Test status
Simulation time 241070592 ps
CPU time 0.98 seconds
Started Jul 14 07:06:23 PM PDT 24
Finished Jul 14 07:06:25 PM PDT 24
Peak memory 199980 kb
Host smart-06ac0e9b-5757-4e87-beb2-b8f314437995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731971843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1731971843
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.4269726281
Short name T493
Test name
Test status
Simulation time 1888296528 ps
CPU time 6.69 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:39 PM PDT 24
Peak memory 200436 kb
Host smart-7991f1aa-a88c-4f6b-9ff7-4266088c921f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269726281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.4269726281
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2116763073
Short name T30
Test name
Test status
Simulation time 101781133 ps
CPU time 1.01 seconds
Started Jul 14 07:06:27 PM PDT 24
Finished Jul 14 07:06:29 PM PDT 24
Peak memory 200088 kb
Host smart-d3b3c74f-cc3c-42ba-b804-0effbd5a98df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116763073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2116763073
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2779565184
Short name T409
Test name
Test status
Simulation time 234785192 ps
CPU time 1.44 seconds
Started Jul 14 07:06:23 PM PDT 24
Finished Jul 14 07:06:26 PM PDT 24
Peak memory 200360 kb
Host smart-93319563-4849-4481-b4d6-ab313516daa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779565184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2779565184
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.674892804
Short name T387
Test name
Test status
Simulation time 5098145843 ps
CPU time 21.71 seconds
Started Jul 14 07:06:26 PM PDT 24
Finished Jul 14 07:06:49 PM PDT 24
Peak memory 210228 kb
Host smart-8837bf9f-8bd5-42fe-a5ab-05bb36e08078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674892804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.674892804
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3554979907
Short name T252
Test name
Test status
Simulation time 121113433 ps
CPU time 1.54 seconds
Started Jul 14 07:06:28 PM PDT 24
Finished Jul 14 07:06:31 PM PDT 24
Peak memory 208324 kb
Host smart-0890764d-3db6-4dd4-9695-da50de61ba45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554979907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3554979907
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3818487440
Short name T338
Test name
Test status
Simulation time 106240293 ps
CPU time 0.87 seconds
Started Jul 14 07:06:28 PM PDT 24
Finished Jul 14 07:06:30 PM PDT 24
Peak memory 200156 kb
Host smart-52458aad-3c4f-4919-a439-889ecc4fe586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818487440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3818487440
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3852770635
Short name T339
Test name
Test status
Simulation time 77897523 ps
CPU time 0.8 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 199940 kb
Host smart-8bb49771-a632-4e23-9ffc-bbf38ef755f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852770635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3852770635
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.486750372
Short name T340
Test name
Test status
Simulation time 1207173446 ps
CPU time 5.9 seconds
Started Jul 14 07:06:33 PM PDT 24
Finished Jul 14 07:06:41 PM PDT 24
Peak memory 221668 kb
Host smart-82d4df03-86f1-497c-ab02-c0dc5ba73f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486750372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.486750372
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3701152034
Short name T8
Test name
Test status
Simulation time 245248037 ps
CPU time 1.03 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 217536 kb
Host smart-57a33b0a-a4ed-46c2-bc86-a3bcb0430b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701152034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3701152034
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2539681445
Short name T241
Test name
Test status
Simulation time 208992352 ps
CPU time 0.94 seconds
Started Jul 14 07:06:27 PM PDT 24
Finished Jul 14 07:06:29 PM PDT 24
Peak memory 199980 kb
Host smart-e61ce5fd-649e-4f1c-9356-2cd9493a35bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539681445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2539681445
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.4188308697
Short name T287
Test name
Test status
Simulation time 923711207 ps
CPU time 4.41 seconds
Started Jul 14 07:06:25 PM PDT 24
Finished Jul 14 07:06:30 PM PDT 24
Peak memory 200352 kb
Host smart-83c4e5bf-d8b5-437c-85f6-ddcb711b4f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188308697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.4188308697
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1836920775
Short name T465
Test name
Test status
Simulation time 101372637 ps
CPU time 1 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:34 PM PDT 24
Peak memory 200120 kb
Host smart-e9291e41-782f-44ff-aa67-ca1ef1cd9a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836920775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1836920775
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1390129921
Short name T253
Test name
Test status
Simulation time 248652056 ps
CPU time 1.46 seconds
Started Jul 14 07:06:26 PM PDT 24
Finished Jul 14 07:06:28 PM PDT 24
Peak memory 200308 kb
Host smart-7ef9e589-e40a-4f8e-924c-a0ebde61af04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390129921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1390129921
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1741447717
Short name T372
Test name
Test status
Simulation time 1776041336 ps
CPU time 8.1 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:42 PM PDT 24
Peak memory 200320 kb
Host smart-992823e1-afae-4148-832b-ba7508da7e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741447717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1741447717
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.4253328711
Short name T324
Test name
Test status
Simulation time 128697807 ps
CPU time 1.58 seconds
Started Jul 14 07:06:29 PM PDT 24
Finished Jul 14 07:06:33 PM PDT 24
Peak memory 208340 kb
Host smart-3d4b67bf-9cd9-4afd-8d7c-815715a75832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253328711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.4253328711
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2688574217
Short name T11
Test name
Test status
Simulation time 89374716 ps
CPU time 0.89 seconds
Started Jul 14 07:06:25 PM PDT 24
Finished Jul 14 07:06:27 PM PDT 24
Peak memory 200164 kb
Host smart-b0e14d28-7ec3-4441-8cdd-694a6409e506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688574217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2688574217
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.342319247
Short name T182
Test name
Test status
Simulation time 59982442 ps
CPU time 0.73 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 199904 kb
Host smart-5285c9a2-60dd-4ce6-a3b7-988e89bbcc17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342319247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.342319247
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.99272877
Short name T44
Test name
Test status
Simulation time 1900845779 ps
CPU time 7.14 seconds
Started Jul 14 07:06:32 PM PDT 24
Finished Jul 14 07:06:42 PM PDT 24
Peak memory 221800 kb
Host smart-6a291ecd-d413-4fca-9cb2-977aea96c5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99272877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.99272877
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2145437599
Short name T51
Test name
Test status
Simulation time 244153961 ps
CPU time 1 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 217544 kb
Host smart-5b2e584f-4212-4bdf-8ed1-80d74f0edfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145437599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2145437599
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3072521952
Short name T81
Test name
Test status
Simulation time 101581565 ps
CPU time 0.76 seconds
Started Jul 14 07:06:32 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 199928 kb
Host smart-682204b9-7ef0-41f8-8dc1-693f6012d5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072521952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3072521952
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1053703698
Short name T540
Test name
Test status
Simulation time 753421684 ps
CPU time 3.99 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:38 PM PDT 24
Peak memory 200416 kb
Host smart-33f2d7a2-7b0d-43b8-9b9e-dbfde0a15c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053703698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1053703698
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1010140470
Short name T77
Test name
Test status
Simulation time 98659270 ps
CPU time 1.01 seconds
Started Jul 14 07:06:28 PM PDT 24
Finished Jul 14 07:06:30 PM PDT 24
Peak memory 200148 kb
Host smart-122a365d-00cd-40e9-89f4-2be87d94920d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010140470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1010140470
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.898888979
Short name T394
Test name
Test status
Simulation time 195786734 ps
CPU time 1.36 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:36 PM PDT 24
Peak memory 200280 kb
Host smart-8039195f-71e0-4342-9146-367c226359df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898888979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.898888979
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.133987908
Short name T354
Test name
Test status
Simulation time 5698902830 ps
CPU time 25.29 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:59 PM PDT 24
Peak memory 200444 kb
Host smart-a0e4db97-3788-4a5f-a55f-c70073804585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133987908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.133987908
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.4082173466
Short name T346
Test name
Test status
Simulation time 118815353 ps
CPU time 1.51 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:34 PM PDT 24
Peak memory 200156 kb
Host smart-2166abdf-6021-4cfd-afad-815954e5db59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082173466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4082173466
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1454364968
Short name T357
Test name
Test status
Simulation time 161613812 ps
CPU time 1.13 seconds
Started Jul 14 07:06:29 PM PDT 24
Finished Jul 14 07:06:32 PM PDT 24
Peak memory 200120 kb
Host smart-055a7b32-1dfa-4992-9e59-560176bc3bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454364968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1454364968
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.211958468
Short name T364
Test name
Test status
Simulation time 84233600 ps
CPU time 0.87 seconds
Started Jul 14 07:06:29 PM PDT 24
Finished Jul 14 07:06:31 PM PDT 24
Peak memory 199984 kb
Host smart-800385fa-73e5-43f0-9b62-d3a5ba0c876d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211958468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.211958468
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3367676962
Short name T45
Test name
Test status
Simulation time 1223127629 ps
CPU time 5.7 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:38 PM PDT 24
Peak memory 221648 kb
Host smart-cd7bff48-cc32-4cdc-8014-3ce760bb15b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367676962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3367676962
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.780521814
Short name T267
Test name
Test status
Simulation time 244288415 ps
CPU time 1.04 seconds
Started Jul 14 07:06:27 PM PDT 24
Finished Jul 14 07:06:29 PM PDT 24
Peak memory 217524 kb
Host smart-5453ffb8-7f0c-46ac-883c-3e8b2a67d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780521814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.780521814
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1018498351
Short name T21
Test name
Test status
Simulation time 91484631 ps
CPU time 0.77 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:33 PM PDT 24
Peak memory 199964 kb
Host smart-d49f2def-8386-4507-aa2f-99afa5591667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018498351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1018498351
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.571332347
Short name T496
Test name
Test status
Simulation time 858170424 ps
CPU time 4.15 seconds
Started Jul 14 07:06:32 PM PDT 24
Finished Jul 14 07:06:39 PM PDT 24
Peak memory 200396 kb
Host smart-66a6d363-6a43-42fe-8585-e8833e54513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571332347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.571332347
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2853883310
Short name T327
Test name
Test status
Simulation time 107239124 ps
CPU time 0.99 seconds
Started Jul 14 07:06:29 PM PDT 24
Finished Jul 14 07:06:32 PM PDT 24
Peak memory 200128 kb
Host smart-d25f3bdf-b495-47ba-9fe8-7587948a48fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853883310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2853883310
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.50652490
Short name T353
Test name
Test status
Simulation time 264279823 ps
CPU time 1.63 seconds
Started Jul 14 07:06:32 PM PDT 24
Finished Jul 14 07:06:36 PM PDT 24
Peak memory 200324 kb
Host smart-67074356-b19d-4470-9f5c-e32c7012a853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50652490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.50652490
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.949251031
Short name T329
Test name
Test status
Simulation time 5809121364 ps
CPU time 25.74 seconds
Started Jul 14 07:06:29 PM PDT 24
Finished Jul 14 07:06:57 PM PDT 24
Peak memory 216844 kb
Host smart-487a9803-814b-4b81-8dd0-320fa64e6762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949251031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.949251031
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3246059537
Short name T516
Test name
Test status
Simulation time 125942818 ps
CPU time 1.61 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 208528 kb
Host smart-eb58b05b-5e2a-444c-8be5-8d67bb3c591d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246059537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3246059537
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2137695870
Short name T273
Test name
Test status
Simulation time 206664611 ps
CPU time 1.27 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 200148 kb
Host smart-4a347370-1472-4c81-b975-0b9fcf7ff1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137695870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2137695870
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1525709660
Short name T139
Test name
Test status
Simulation time 60570414 ps
CPU time 0.7 seconds
Started Jul 14 07:06:39 PM PDT 24
Finished Jul 14 07:06:41 PM PDT 24
Peak memory 199892 kb
Host smart-0d28bc1f-97b1-4179-9962-697fe5fab918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525709660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1525709660
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.877911316
Short name T420
Test name
Test status
Simulation time 1230369429 ps
CPU time 5.99 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:40 PM PDT 24
Peak memory 221696 kb
Host smart-cdca62f9-5abd-4cb0-808e-2632c70b0eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877911316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.877911316
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2109516157
Short name T278
Test name
Test status
Simulation time 244700273 ps
CPU time 1 seconds
Started Jul 14 07:06:28 PM PDT 24
Finished Jul 14 07:06:30 PM PDT 24
Peak memory 217432 kb
Host smart-ddd81a81-93e3-42a5-9b20-1565db2b8290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109516157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2109516157
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.671956720
Short name T294
Test name
Test status
Simulation time 151485476 ps
CPU time 0.83 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 199944 kb
Host smart-56b0ae73-7bab-44cd-969d-4b897bc3812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671956720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.671956720
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2061463041
Short name T379
Test name
Test status
Simulation time 1074535201 ps
CPU time 4.76 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:38 PM PDT 24
Peak memory 200428 kb
Host smart-4e9ad4e6-55ed-49fb-bfd6-45ce3b320cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061463041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2061463041
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2632551715
Short name T191
Test name
Test status
Simulation time 99705385 ps
CPU time 0.95 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:33 PM PDT 24
Peak memory 200148 kb
Host smart-d6dcd47e-da9a-4800-a47c-84d835496afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632551715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2632551715
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2449759482
Short name T416
Test name
Test status
Simulation time 203163631 ps
CPU time 1.4 seconds
Started Jul 14 07:06:31 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 200264 kb
Host smart-5565b5e6-91e2-4eac-aaf8-86da8967083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449759482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2449759482
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3882543169
Short name T536
Test name
Test status
Simulation time 4632359491 ps
CPU time 16.41 seconds
Started Jul 14 07:06:38 PM PDT 24
Finished Jul 14 07:06:55 PM PDT 24
Peak memory 208696 kb
Host smart-e0a198b9-ccbe-40c1-a5c2-e0ddf267d69d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882543169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3882543169
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2912732975
Short name T427
Test name
Test status
Simulation time 522249800 ps
CPU time 2.81 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 200176 kb
Host smart-5ee4a3d8-cdb7-4232-912d-91a7a70fa044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912732975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2912732975
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1000702527
Short name T515
Test name
Test status
Simulation time 157692186 ps
CPU time 1.08 seconds
Started Jul 14 07:06:30 PM PDT 24
Finished Jul 14 07:06:34 PM PDT 24
Peak memory 200144 kb
Host smart-5963d33d-7e54-4ab9-8d00-996b91055872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000702527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1000702527
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.810616442
Short name T172
Test name
Test status
Simulation time 68066095 ps
CPU time 0.76 seconds
Started Jul 14 07:06:40 PM PDT 24
Finished Jul 14 07:06:42 PM PDT 24
Peak memory 199960 kb
Host smart-c062771e-685f-4414-ad98-d8b2e10dd508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810616442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.810616442
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2470030398
Short name T35
Test name
Test status
Simulation time 1242948337 ps
CPU time 5.93 seconds
Started Jul 14 07:06:47 PM PDT 24
Finished Jul 14 07:06:54 PM PDT 24
Peak memory 221732 kb
Host smart-d09172c0-d46e-49f0-a404-b451f7963167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470030398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2470030398
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1600035801
Short name T53
Test name
Test status
Simulation time 244066110 ps
CPU time 1.11 seconds
Started Jul 14 07:06:43 PM PDT 24
Finished Jul 14 07:06:46 PM PDT 24
Peak memory 217544 kb
Host smart-737125f8-a455-4620-97b9-9387a223be89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600035801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1600035801
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.600294533
Short name T214
Test name
Test status
Simulation time 206947257 ps
CPU time 0.9 seconds
Started Jul 14 07:06:40 PM PDT 24
Finished Jul 14 07:06:42 PM PDT 24
Peak memory 199956 kb
Host smart-22b5e079-2248-4085-83c3-963af33d3e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600294533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.600294533
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.4123892612
Short name T512
Test name
Test status
Simulation time 1422372301 ps
CPU time 5.4 seconds
Started Jul 14 07:06:40 PM PDT 24
Finished Jul 14 07:06:47 PM PDT 24
Peak memory 200428 kb
Host smart-c42a15b4-9042-43ad-9db4-7ca335e3aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123892612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.4123892612
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1144243123
Short name T467
Test name
Test status
Simulation time 177950433 ps
CPU time 1.25 seconds
Started Jul 14 07:06:38 PM PDT 24
Finished Jul 14 07:06:41 PM PDT 24
Peak memory 200104 kb
Host smart-df0f05d0-3c31-4b1d-8c23-3eb59effd4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144243123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1144243123
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3844681706
Short name T335
Test name
Test status
Simulation time 198772486 ps
CPU time 1.31 seconds
Started Jul 14 07:06:39 PM PDT 24
Finished Jul 14 07:06:41 PM PDT 24
Peak memory 200324 kb
Host smart-0404438a-afbb-45c1-a034-44061a47bbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844681706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3844681706
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.4258101632
Short name T260
Test name
Test status
Simulation time 194650442 ps
CPU time 1.41 seconds
Started Jul 14 07:06:40 PM PDT 24
Finished Jul 14 07:06:43 PM PDT 24
Peak memory 200124 kb
Host smart-359ea709-0241-4767-8df0-e419cecb4dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258101632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.4258101632
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1326496045
Short name T348
Test name
Test status
Simulation time 139620689 ps
CPU time 1.67 seconds
Started Jul 14 07:06:39 PM PDT 24
Finished Jul 14 07:06:41 PM PDT 24
Peak memory 200116 kb
Host smart-abcf79ef-ca2f-4615-910b-f4d912e80db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326496045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1326496045
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2125220425
Short name T108
Test name
Test status
Simulation time 233704845 ps
CPU time 1.39 seconds
Started Jul 14 07:06:42 PM PDT 24
Finished Jul 14 07:06:45 PM PDT 24
Peak memory 200148 kb
Host smart-e4e0ff37-f5b3-459d-94b3-80077baba952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125220425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2125220425
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2728064848
Short name T254
Test name
Test status
Simulation time 68998501 ps
CPU time 0.79 seconds
Started Jul 14 07:06:40 PM PDT 24
Finished Jul 14 07:06:42 PM PDT 24
Peak memory 199928 kb
Host smart-ee7a0548-d364-4f9b-b2a2-0bf8fa869124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728064848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2728064848
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1035121124
Short name T233
Test name
Test status
Simulation time 243696843 ps
CPU time 1.06 seconds
Started Jul 14 07:06:42 PM PDT 24
Finished Jul 14 07:06:44 PM PDT 24
Peak memory 217500 kb
Host smart-3a902040-ba49-41e3-8418-e73c51d8ed7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035121124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1035121124
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.234427761
Short name T23
Test name
Test status
Simulation time 176107799 ps
CPU time 0.85 seconds
Started Jul 14 07:06:41 PM PDT 24
Finished Jul 14 07:06:43 PM PDT 24
Peak memory 199932 kb
Host smart-8ee3067e-e889-446f-90ee-dbc6f2bc03fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234427761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.234427761
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3624162264
Short name T380
Test name
Test status
Simulation time 860611680 ps
CPU time 4.23 seconds
Started Jul 14 07:06:38 PM PDT 24
Finished Jul 14 07:06:44 PM PDT 24
Peak memory 200372 kb
Host smart-b573a2c4-01c3-41ee-82f0-1c125d05ddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624162264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3624162264
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.131436854
Short name T434
Test name
Test status
Simulation time 176952056 ps
CPU time 1.22 seconds
Started Jul 14 07:06:39 PM PDT 24
Finished Jul 14 07:06:41 PM PDT 24
Peak memory 200148 kb
Host smart-9d3ed94a-835d-40fb-8db4-05b38230afd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131436854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.131436854
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2456019299
Short name T202
Test name
Test status
Simulation time 196578541 ps
CPU time 1.3 seconds
Started Jul 14 07:06:37 PM PDT 24
Finished Jul 14 07:06:38 PM PDT 24
Peak memory 200324 kb
Host smart-b2faf49e-9b21-4cf1-ae71-a8bd5bbec947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456019299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2456019299
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1371611317
Short name T397
Test name
Test status
Simulation time 3179024506 ps
CPU time 11.24 seconds
Started Jul 14 07:06:36 PM PDT 24
Finished Jul 14 07:06:48 PM PDT 24
Peak memory 200520 kb
Host smart-8c831f82-6334-4d94-8cd6-37f5c84b8a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371611317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1371611317
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.817894937
Short name T225
Test name
Test status
Simulation time 366408400 ps
CPU time 2.42 seconds
Started Jul 14 07:06:38 PM PDT 24
Finished Jul 14 07:06:41 PM PDT 24
Peak memory 200136 kb
Host smart-eda25b51-3cce-4f3c-b695-d31e7252ddf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817894937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.817894937
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2200758290
Short name T350
Test name
Test status
Simulation time 216291802 ps
CPU time 1.22 seconds
Started Jul 14 07:06:37 PM PDT 24
Finished Jul 14 07:06:39 PM PDT 24
Peak memory 200144 kb
Host smart-f9d6f1d1-5fba-49a4-bdb5-17e9922c1c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200758290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2200758290
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1671433549
Short name T520
Test name
Test status
Simulation time 70272550 ps
CPU time 0.75 seconds
Started Jul 14 07:06:49 PM PDT 24
Finished Jul 14 07:06:51 PM PDT 24
Peak memory 199952 kb
Host smart-579f30ae-72f4-43ca-b383-dfbd57f8f820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671433549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1671433549
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.443703963
Short name T446
Test name
Test status
Simulation time 2349300327 ps
CPU time 8.17 seconds
Started Jul 14 07:06:48 PM PDT 24
Finished Jul 14 07:06:57 PM PDT 24
Peak memory 218816 kb
Host smart-3d7c577e-7055-4e12-a173-fab21cba62ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443703963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.443703963
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1557763897
Short name T381
Test name
Test status
Simulation time 244951361 ps
CPU time 1.16 seconds
Started Jul 14 07:06:41 PM PDT 24
Finished Jul 14 07:06:43 PM PDT 24
Peak memory 217532 kb
Host smart-832d7926-d18c-4b7a-b71e-05c85558b69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557763897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1557763897
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3669598727
Short name T82
Test name
Test status
Simulation time 96329465 ps
CPU time 0.78 seconds
Started Jul 14 07:06:41 PM PDT 24
Finished Jul 14 07:06:42 PM PDT 24
Peak memory 199968 kb
Host smart-85e4f9e6-c448-4f24-a1ba-88380a94eb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669598727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3669598727
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1830022489
Short name T475
Test name
Test status
Simulation time 1559034470 ps
CPU time 6.01 seconds
Started Jul 14 07:06:47 PM PDT 24
Finished Jul 14 07:06:54 PM PDT 24
Peak memory 200396 kb
Host smart-5a353ced-bd6d-4fc5-a9ce-838fdac42004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830022489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1830022489
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2247649574
Short name T317
Test name
Test status
Simulation time 105735179 ps
CPU time 1.04 seconds
Started Jul 14 07:06:40 PM PDT 24
Finished Jul 14 07:06:43 PM PDT 24
Peak memory 200136 kb
Host smart-b1961b16-e79b-4cc9-bb8d-f88e330e9727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247649574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2247649574
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1404167912
Short name T270
Test name
Test status
Simulation time 203699203 ps
CPU time 1.42 seconds
Started Jul 14 07:06:41 PM PDT 24
Finished Jul 14 07:06:44 PM PDT 24
Peak memory 200552 kb
Host smart-1368836d-3de6-4921-9d72-979a228cfc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404167912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1404167912
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.4043488370
Short name T229
Test name
Test status
Simulation time 7311673563 ps
CPU time 25.44 seconds
Started Jul 14 07:06:41 PM PDT 24
Finished Jul 14 07:07:07 PM PDT 24
Peak memory 200428 kb
Host smart-c52167e3-0dca-46bf-84ba-daeb495f447b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043488370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.4043488370
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1011304189
Short name T184
Test name
Test status
Simulation time 376911154 ps
CPU time 2.08 seconds
Started Jul 14 07:06:38 PM PDT 24
Finished Jul 14 07:06:41 PM PDT 24
Peak memory 200164 kb
Host smart-0f68b32e-ef8b-426b-bf31-4c3d7a017c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011304189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1011304189
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3569455433
Short name T255
Test name
Test status
Simulation time 172236998 ps
CPU time 1.24 seconds
Started Jul 14 07:06:38 PM PDT 24
Finished Jul 14 07:06:40 PM PDT 24
Peak memory 200432 kb
Host smart-f3d22dd0-f044-4171-adc6-173f7de5372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569455433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3569455433
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3574762984
Short name T303
Test name
Test status
Simulation time 65454430 ps
CPU time 0.77 seconds
Started Jul 14 07:05:50 PM PDT 24
Finished Jul 14 07:05:53 PM PDT 24
Peak memory 199940 kb
Host smart-fa9808b7-04f7-4bdf-805c-aeb091b75c7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574762984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3574762984
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2250552396
Short name T39
Test name
Test status
Simulation time 2368998435 ps
CPU time 7.94 seconds
Started Jul 14 07:05:49 PM PDT 24
Finished Jul 14 07:05:58 PM PDT 24
Peak memory 221812 kb
Host smart-002e7af5-3f1d-4681-b558-77146ac386c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250552396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2250552396
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1844883419
Short name T24
Test name
Test status
Simulation time 248289316 ps
CPU time 1.12 seconds
Started Jul 14 07:06:03 PM PDT 24
Finished Jul 14 07:06:05 PM PDT 24
Peak memory 217520 kb
Host smart-23a28a3e-5fce-4122-9874-02f22e343ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844883419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1844883419
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2994316403
Short name T16
Test name
Test status
Simulation time 189239402 ps
CPU time 0.94 seconds
Started Jul 14 07:05:48 PM PDT 24
Finished Jul 14 07:05:50 PM PDT 24
Peak memory 199984 kb
Host smart-861b28d0-2698-4c39-b19b-0083d5e28674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994316403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2994316403
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3030628715
Short name T75
Test name
Test status
Simulation time 1025795611 ps
CPU time 5.22 seconds
Started Jul 14 07:05:45 PM PDT 24
Finished Jul 14 07:05:52 PM PDT 24
Peak memory 200408 kb
Host smart-126f08b6-adbf-49cd-a25f-083d7d0f5de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030628715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3030628715
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1020776590
Short name T69
Test name
Test status
Simulation time 8685847985 ps
CPU time 12.78 seconds
Started Jul 14 07:05:53 PM PDT 24
Finished Jul 14 07:06:07 PM PDT 24
Peak memory 217120 kb
Host smart-f624de3e-885d-4aa8-906c-da7bbbae8473
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020776590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1020776590
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3351664405
Short name T55
Test name
Test status
Simulation time 114456968 ps
CPU time 0.96 seconds
Started Jul 14 07:05:50 PM PDT 24
Finished Jul 14 07:05:53 PM PDT 24
Peak memory 200176 kb
Host smart-8dced152-a408-43af-b86f-19ffd15a1217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351664405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3351664405
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.12520712
Short name T365
Test name
Test status
Simulation time 226983611 ps
CPU time 1.49 seconds
Started Jul 14 07:05:46 PM PDT 24
Finished Jul 14 07:05:49 PM PDT 24
Peak memory 200328 kb
Host smart-9c7ce4f1-10c0-4938-ba0d-7c81081292cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12520712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.12520712
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.960736550
Short name T399
Test name
Test status
Simulation time 3445014187 ps
CPU time 13.46 seconds
Started Jul 14 07:06:02 PM PDT 24
Finished Jul 14 07:06:16 PM PDT 24
Peak memory 208652 kb
Host smart-259d6aee-9b9f-41b8-9ecf-84af33c9cc47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960736550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.960736550
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3984636250
Short name T478
Test name
Test status
Simulation time 325234977 ps
CPU time 1.96 seconds
Started Jul 14 07:05:50 PM PDT 24
Finished Jul 14 07:05:54 PM PDT 24
Peak memory 200148 kb
Host smart-f59f0c5f-adf8-485e-ac8a-2c24d8930fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984636250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3984636250
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2736103062
Short name T437
Test name
Test status
Simulation time 105200603 ps
CPU time 0.96 seconds
Started Jul 14 07:05:49 PM PDT 24
Finished Jul 14 07:05:52 PM PDT 24
Peak memory 200168 kb
Host smart-13951cee-7a66-448c-80ee-24a983b21966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736103062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2736103062
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1256126467
Short name T313
Test name
Test status
Simulation time 70245970 ps
CPU time 0.84 seconds
Started Jul 14 07:06:43 PM PDT 24
Finished Jul 14 07:06:46 PM PDT 24
Peak memory 199956 kb
Host smart-e94b044e-8394-4eca-89c6-b2e8ee03f6c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256126467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1256126467
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1050452752
Short name T41
Test name
Test status
Simulation time 1225822925 ps
CPU time 5.23 seconds
Started Jul 14 07:06:45 PM PDT 24
Finished Jul 14 07:06:52 PM PDT 24
Peak memory 217880 kb
Host smart-295abe3d-f486-4610-be68-a9abc7368359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050452752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1050452752
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.986295450
Short name T293
Test name
Test status
Simulation time 244953666 ps
CPU time 1.12 seconds
Started Jul 14 07:06:47 PM PDT 24
Finished Jul 14 07:06:48 PM PDT 24
Peak memory 217548 kb
Host smart-503cadb4-da0a-4dc4-80bf-de29513b9f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986295450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.986295450
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1866816826
Short name T261
Test name
Test status
Simulation time 193408980 ps
CPU time 0.86 seconds
Started Jul 14 07:06:46 PM PDT 24
Finished Jul 14 07:06:48 PM PDT 24
Peak memory 199944 kb
Host smart-dfb933eb-5cea-4b61-af29-5731fa7bdf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866816826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1866816826
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3118420745
Short name T342
Test name
Test status
Simulation time 1649922388 ps
CPU time 5.7 seconds
Started Jul 14 07:06:42 PM PDT 24
Finished Jul 14 07:06:50 PM PDT 24
Peak memory 200428 kb
Host smart-41ab3308-3971-42dc-9cbe-7997a1a3f07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118420745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3118420745
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3581242516
Short name T423
Test name
Test status
Simulation time 152073056 ps
CPU time 1.12 seconds
Started Jul 14 07:06:44 PM PDT 24
Finished Jul 14 07:06:47 PM PDT 24
Peak memory 200348 kb
Host smart-f2eb3deb-93dd-4cf4-a3d3-85ea853418d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581242516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3581242516
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1142927513
Short name T421
Test name
Test status
Simulation time 257123815 ps
CPU time 1.44 seconds
Started Jul 14 07:06:41 PM PDT 24
Finished Jul 14 07:06:44 PM PDT 24
Peak memory 200344 kb
Host smart-baac33c1-1824-4c69-b288-124466432267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142927513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1142927513
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1223732999
Short name T526
Test name
Test status
Simulation time 10167162462 ps
CPU time 34.82 seconds
Started Jul 14 07:06:43 PM PDT 24
Finished Jul 14 07:07:20 PM PDT 24
Peak memory 210508 kb
Host smart-14239593-e92e-4ca7-b197-ab58c44d0119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223732999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1223732999
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3418947614
Short name T272
Test name
Test status
Simulation time 390830485 ps
CPU time 2.18 seconds
Started Jul 14 07:06:44 PM PDT 24
Finished Jul 14 07:06:48 PM PDT 24
Peak memory 208312 kb
Host smart-ab023bb9-e406-426f-9245-3b08973e8176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418947614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3418947614
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3290213009
Short name T144
Test name
Test status
Simulation time 254233464 ps
CPU time 1.42 seconds
Started Jul 14 07:06:42 PM PDT 24
Finished Jul 14 07:06:44 PM PDT 24
Peak memory 200156 kb
Host smart-e2dbaae1-43f6-4aba-8c07-1f0ad4ac8ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290213009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3290213009
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.759309971
Short name T443
Test name
Test status
Simulation time 57651872 ps
CPU time 0.73 seconds
Started Jul 14 07:06:47 PM PDT 24
Finished Jul 14 07:06:49 PM PDT 24
Peak memory 199932 kb
Host smart-35cf9854-79af-4fc8-970e-1123b2065dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759309971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.759309971
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1817824968
Short name T323
Test name
Test status
Simulation time 1914453502 ps
CPU time 7.12 seconds
Started Jul 14 07:06:44 PM PDT 24
Finished Jul 14 07:06:53 PM PDT 24
Peak memory 229936 kb
Host smart-c0cf54fd-e7d6-4da3-af24-c60ddee1cd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817824968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1817824968
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1896610751
Short name T400
Test name
Test status
Simulation time 244779165 ps
CPU time 1.19 seconds
Started Jul 14 07:06:47 PM PDT 24
Finished Jul 14 07:06:49 PM PDT 24
Peak memory 217412 kb
Host smart-0a66fb4c-6db2-4afc-9815-6f271208ad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896610751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1896610751
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2297172278
Short name T481
Test name
Test status
Simulation time 193691475 ps
CPU time 0.89 seconds
Started Jul 14 07:06:43 PM PDT 24
Finished Jul 14 07:06:46 PM PDT 24
Peak memory 199964 kb
Host smart-5f238a08-2ed4-4fbe-a79e-d20110c82d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297172278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2297172278
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1369688223
Short name T116
Test name
Test status
Simulation time 1439257948 ps
CPU time 5.14 seconds
Started Jul 14 07:06:45 PM PDT 24
Finished Jul 14 07:06:52 PM PDT 24
Peak memory 200376 kb
Host smart-4af34dcd-e9b6-4a8a-99db-4b6cfa3c8bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369688223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1369688223
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3553095902
Short name T28
Test name
Test status
Simulation time 165159297 ps
CPU time 1.13 seconds
Started Jul 14 07:06:49 PM PDT 24
Finished Jul 14 07:06:51 PM PDT 24
Peak memory 200164 kb
Host smart-8d990c36-8274-434a-808a-e8940b2b6223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553095902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3553095902
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1272240645
Short name T238
Test name
Test status
Simulation time 108605778 ps
CPU time 1.2 seconds
Started Jul 14 07:06:47 PM PDT 24
Finished Jul 14 07:06:48 PM PDT 24
Peak memory 200404 kb
Host smart-082f5081-dc18-419c-aa9f-2fb0bc65d975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272240645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1272240645
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1856051333
Short name T398
Test name
Test status
Simulation time 6070247107 ps
CPU time 24.02 seconds
Started Jul 14 07:06:44 PM PDT 24
Finished Jul 14 07:07:10 PM PDT 24
Peak memory 200680 kb
Host smart-aceaa703-8c0f-4ecc-8099-0df450abf393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856051333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1856051333
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.15409777
Short name T404
Test name
Test status
Simulation time 158569640 ps
CPU time 1.88 seconds
Started Jul 14 07:06:42 PM PDT 24
Finished Jul 14 07:06:45 PM PDT 24
Peak memory 200176 kb
Host smart-f7feaf3d-0165-483a-9e95-c1a49c323375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15409777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.15409777
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2413845907
Short name T374
Test name
Test status
Simulation time 196740301 ps
CPU time 1.21 seconds
Started Jul 14 07:06:42 PM PDT 24
Finished Jul 14 07:06:44 PM PDT 24
Peak memory 200148 kb
Host smart-2e26b807-a3fb-4a22-9b1b-d1487d5703b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413845907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2413845907
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.377502050
Short name T333
Test name
Test status
Simulation time 70487951 ps
CPU time 0.83 seconds
Started Jul 14 07:06:47 PM PDT 24
Finished Jul 14 07:06:48 PM PDT 24
Peak memory 199736 kb
Host smart-57eceea0-650a-4047-b0b8-8b1007a5883c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377502050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.377502050
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1573715842
Short name T410
Test name
Test status
Simulation time 2149625032 ps
CPU time 7.77 seconds
Started Jul 14 07:06:44 PM PDT 24
Finished Jul 14 07:06:54 PM PDT 24
Peak memory 217812 kb
Host smart-89eff091-3037-40d5-97dd-fb93e8dab0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573715842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1573715842
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1201683546
Short name T140
Test name
Test status
Simulation time 244650019 ps
CPU time 1.03 seconds
Started Jul 14 07:06:43 PM PDT 24
Finished Jul 14 07:06:45 PM PDT 24
Peak memory 217508 kb
Host smart-f85290e6-0486-44ae-9d22-80b7490d6599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201683546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1201683546
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2851907570
Short name T281
Test name
Test status
Simulation time 189292255 ps
CPU time 0.86 seconds
Started Jul 14 07:06:42 PM PDT 24
Finished Jul 14 07:06:44 PM PDT 24
Peak memory 199932 kb
Host smart-2927d593-2603-4df5-9667-9fdf2c6cc24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851907570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2851907570
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.300845542
Short name T298
Test name
Test status
Simulation time 990031179 ps
CPU time 4.6 seconds
Started Jul 14 07:06:44 PM PDT 24
Finished Jul 14 07:06:51 PM PDT 24
Peak memory 200368 kb
Host smart-d7f85ce5-08f5-4fa7-a48e-901a069ddb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300845542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.300845542
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3001105820
Short name T242
Test name
Test status
Simulation time 163656901 ps
CPU time 1.18 seconds
Started Jul 14 07:06:43 PM PDT 24
Finished Jul 14 07:06:46 PM PDT 24
Peak memory 200164 kb
Host smart-9b62f4ad-a9bd-4142-9408-36bbf763ef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001105820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3001105820
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3374642109
Short name T248
Test name
Test status
Simulation time 12228220047 ps
CPU time 44.53 seconds
Started Jul 14 07:06:44 PM PDT 24
Finished Jul 14 07:07:30 PM PDT 24
Peak memory 208728 kb
Host smart-0950b330-f6fe-4f89-9527-27a9967d1584
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374642109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3374642109
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1023437309
Short name T331
Test name
Test status
Simulation time 141233274 ps
CPU time 1.65 seconds
Started Jul 14 07:06:43 PM PDT 24
Finished Jul 14 07:06:47 PM PDT 24
Peak memory 200112 kb
Host smart-0e3b9891-c499-4b6c-841d-1f2ff1181126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023437309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1023437309
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.146504986
Short name T457
Test name
Test status
Simulation time 157201094 ps
CPU time 1.18 seconds
Started Jul 14 07:06:43 PM PDT 24
Finished Jul 14 07:06:46 PM PDT 24
Peak memory 200132 kb
Host smart-7f80f235-3254-4847-b3a3-77ed132ca46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146504986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.146504986
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2058108010
Short name T193
Test name
Test status
Simulation time 73275332 ps
CPU time 0.77 seconds
Started Jul 14 07:06:49 PM PDT 24
Finished Jul 14 07:06:51 PM PDT 24
Peak memory 199932 kb
Host smart-e0474a2f-1bf1-459f-9ab7-66d76224a69a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058108010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2058108010
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3473161874
Short name T40
Test name
Test status
Simulation time 1886497817 ps
CPU time 7.21 seconds
Started Jul 14 07:06:52 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 221704 kb
Host smart-f78e1821-4642-41c8-98c2-206542c389e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473161874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3473161874
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.669446147
Short name T185
Test name
Test status
Simulation time 244361734 ps
CPU time 1.03 seconds
Started Jul 14 07:06:48 PM PDT 24
Finished Jul 14 07:06:50 PM PDT 24
Peak memory 217540 kb
Host smart-08eb0019-f3e1-4de0-9955-769f5e68cbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669446147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.669446147
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.4250251474
Short name T15
Test name
Test status
Simulation time 123361258 ps
CPU time 0.75 seconds
Started Jul 14 07:06:49 PM PDT 24
Finished Jul 14 07:06:51 PM PDT 24
Peak memory 199960 kb
Host smart-d34f36a9-ecc1-4b13-8074-6b4d43d0cfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250251474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.4250251474
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.829869280
Short name T104
Test name
Test status
Simulation time 2075339366 ps
CPU time 7.56 seconds
Started Jul 14 07:06:46 PM PDT 24
Finished Jul 14 07:06:55 PM PDT 24
Peak memory 200404 kb
Host smart-cabad6ab-ce13-4a97-9a32-a2800f54f0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829869280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.829869280
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2120667928
Short name T320
Test name
Test status
Simulation time 151356520 ps
CPU time 1.08 seconds
Started Jul 14 07:06:49 PM PDT 24
Finished Jul 14 07:06:51 PM PDT 24
Peak memory 200144 kb
Host smart-2db41d1e-1c64-4121-b31a-422fe0474d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120667928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2120667928
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.944624885
Short name T217
Test name
Test status
Simulation time 226037889 ps
CPU time 1.47 seconds
Started Jul 14 07:06:45 PM PDT 24
Finished Jul 14 07:06:48 PM PDT 24
Peak memory 200312 kb
Host smart-05607a31-64da-422f-ae69-a3f5a8423164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944624885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.944624885
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1992044205
Short name T386
Test name
Test status
Simulation time 13520465634 ps
CPU time 45.86 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 200516 kb
Host smart-258c1f90-8d06-43cd-8054-f04968e42bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992044205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1992044205
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1291167096
Short name T178
Test name
Test status
Simulation time 140705199 ps
CPU time 1.73 seconds
Started Jul 14 07:06:47 PM PDT 24
Finished Jul 14 07:06:50 PM PDT 24
Peak memory 200136 kb
Host smart-0ee61a7e-bd1d-47f8-8382-143bfedb8ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291167096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1291167096
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1897119040
Short name T312
Test name
Test status
Simulation time 97857050 ps
CPU time 0.93 seconds
Started Jul 14 07:06:43 PM PDT 24
Finished Jul 14 07:06:45 PM PDT 24
Peak memory 200048 kb
Host smart-f933c680-dd5e-4a92-bc1c-db85cf4e3ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897119040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1897119040
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3287393856
Short name T366
Test name
Test status
Simulation time 61411605 ps
CPU time 0.76 seconds
Started Jul 14 07:06:51 PM PDT 24
Finished Jul 14 07:06:54 PM PDT 24
Peak memory 199964 kb
Host smart-e1ac824e-3c99-4591-8eee-a31745a16eae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287393856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3287393856
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3639939455
Short name T48
Test name
Test status
Simulation time 2374045027 ps
CPU time 7.87 seconds
Started Jul 14 07:06:52 PM PDT 24
Finished Jul 14 07:07:03 PM PDT 24
Peak memory 217928 kb
Host smart-35540063-e78d-4e56-a21c-a31210cb183e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639939455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3639939455
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.715829020
Short name T198
Test name
Test status
Simulation time 244276410 ps
CPU time 1.09 seconds
Started Jul 14 07:07:00 PM PDT 24
Finished Jul 14 07:07:03 PM PDT 24
Peak memory 217496 kb
Host smart-13f848ff-42a5-474e-92be-98e611ec91f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715829020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.715829020
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.87458618
Short name T228
Test name
Test status
Simulation time 100112797 ps
CPU time 0.75 seconds
Started Jul 14 07:06:50 PM PDT 24
Finished Jul 14 07:06:52 PM PDT 24
Peak memory 199916 kb
Host smart-84c529ff-2c96-4b59-baaf-533951e6f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87458618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.87458618
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.532348110
Short name T314
Test name
Test status
Simulation time 1870581174 ps
CPU time 6.68 seconds
Started Jul 14 07:06:54 PM PDT 24
Finished Jul 14 07:07:03 PM PDT 24
Peak memory 200448 kb
Host smart-c9a35b49-4613-4921-b255-c13cad695ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532348110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.532348110
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2805469082
Short name T163
Test name
Test status
Simulation time 185150487 ps
CPU time 1.27 seconds
Started Jul 14 07:06:51 PM PDT 24
Finished Jul 14 07:06:55 PM PDT 24
Peak memory 200348 kb
Host smart-362a94c2-cf19-4237-b79a-4443e1b56b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805469082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2805469082
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2857938730
Short name T460
Test name
Test status
Simulation time 127739532 ps
CPU time 1.17 seconds
Started Jul 14 07:06:52 PM PDT 24
Finished Jul 14 07:06:55 PM PDT 24
Peak memory 200388 kb
Host smart-09f10098-34ff-4529-86dd-51395edd782f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857938730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2857938730
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.690909324
Short name T347
Test name
Test status
Simulation time 5771294697 ps
CPU time 22.29 seconds
Started Jul 14 07:06:50 PM PDT 24
Finished Jul 14 07:07:13 PM PDT 24
Peak memory 208700 kb
Host smart-976d3220-2a1d-4ac3-b181-5380296454b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690909324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.690909324
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2301794825
Short name T60
Test name
Test status
Simulation time 303608583 ps
CPU time 1.94 seconds
Started Jul 14 07:06:56 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 208432 kb
Host smart-e4a722bb-1060-40ab-93d7-985ba7644a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301794825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2301794825
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.679368443
Short name T473
Test name
Test status
Simulation time 257320141 ps
CPU time 1.71 seconds
Started Jul 14 07:06:55 PM PDT 24
Finished Jul 14 07:06:58 PM PDT 24
Peak memory 200332 kb
Host smart-4fde3945-c8fb-4559-a307-35222b2c684d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679368443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.679368443
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1327512492
Short name T523
Test name
Test status
Simulation time 69447406 ps
CPU time 0.81 seconds
Started Jul 14 07:06:53 PM PDT 24
Finished Jul 14 07:06:56 PM PDT 24
Peak memory 199920 kb
Host smart-3843d81a-c727-45cd-be92-7fe6c0ab4981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327512492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1327512492
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.286008018
Short name T38
Test name
Test status
Simulation time 1895755910 ps
CPU time 7.45 seconds
Started Jul 14 07:06:51 PM PDT 24
Finished Jul 14 07:07:00 PM PDT 24
Peak memory 221612 kb
Host smart-04aef9ed-76e3-4fa8-bf4c-1393f3a377b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286008018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.286008018
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1925892285
Short name T247
Test name
Test status
Simulation time 244160232 ps
CPU time 1.04 seconds
Started Jul 14 07:06:59 PM PDT 24
Finished Jul 14 07:07:02 PM PDT 24
Peak memory 217504 kb
Host smart-653f256e-5c8c-4c80-8ca3-f3a2a4406373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925892285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1925892285
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2865540105
Short name T309
Test name
Test status
Simulation time 116565416 ps
CPU time 0.81 seconds
Started Jul 14 07:06:51 PM PDT 24
Finished Jul 14 07:06:53 PM PDT 24
Peak memory 199868 kb
Host smart-2a9055da-9333-45d6-9afc-e54c6e893a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865540105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2865540105
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1886339146
Short name T445
Test name
Test status
Simulation time 1885035953 ps
CPU time 7.25 seconds
Started Jul 14 07:06:52 PM PDT 24
Finished Jul 14 07:07:02 PM PDT 24
Peak memory 200436 kb
Host smart-8cdfce30-66cf-4cda-9c09-3d4d14594811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886339146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1886339146
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2779548599
Short name T449
Test name
Test status
Simulation time 185828616 ps
CPU time 1.21 seconds
Started Jul 14 07:06:58 PM PDT 24
Finished Jul 14 07:07:02 PM PDT 24
Peak memory 200108 kb
Host smart-a052a963-ab81-429f-9975-e1de0a5ed651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779548599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2779548599
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.938250990
Short name T88
Test name
Test status
Simulation time 251993551 ps
CPU time 1.52 seconds
Started Jul 14 07:06:50 PM PDT 24
Finished Jul 14 07:06:53 PM PDT 24
Peak memory 200288 kb
Host smart-4c1fc505-ba6f-4878-97d1-8299d165dbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938250990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.938250990
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.809860657
Short name T259
Test name
Test status
Simulation time 2820384525 ps
CPU time 11.09 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:11 PM PDT 24
Peak memory 200512 kb
Host smart-c42e73f3-f307-40fb-a702-9e5845fb3a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809860657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.809860657
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3420471992
Short name T110
Test name
Test status
Simulation time 134149247 ps
CPU time 1.61 seconds
Started Jul 14 07:06:51 PM PDT 24
Finished Jul 14 07:06:55 PM PDT 24
Peak memory 208344 kb
Host smart-b5b98531-e57d-452a-bff1-656b9dee3217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420471992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3420471992
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3588564906
Short name T208
Test name
Test status
Simulation time 183208263 ps
CPU time 1.13 seconds
Started Jul 14 07:06:56 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 200176 kb
Host smart-49d0ed97-d8ae-4693-9a15-d38f6777c1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588564906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3588564906
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.335765654
Short name T142
Test name
Test status
Simulation time 63484936 ps
CPU time 0.86 seconds
Started Jul 14 07:06:51 PM PDT 24
Finished Jul 14 07:06:54 PM PDT 24
Peak memory 199860 kb
Host smart-f2b27c79-30ec-4d27-b322-f10da27bc4d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335765654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.335765654
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3218514735
Short name T393
Test name
Test status
Simulation time 1222255641 ps
CPU time 5.92 seconds
Started Jul 14 07:06:53 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 217620 kb
Host smart-25ed2f3f-8f2f-4893-ac92-124b71fec5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218514735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3218514735
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1400418731
Short name T282
Test name
Test status
Simulation time 244405049 ps
CPU time 1.04 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 217492 kb
Host smart-7931d51e-9f6f-4501-91d9-3782ff85642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400418731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1400418731
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1515913657
Short name T345
Test name
Test status
Simulation time 202040443 ps
CPU time 0.96 seconds
Started Jul 14 07:06:51 PM PDT 24
Finished Jul 14 07:06:53 PM PDT 24
Peak memory 199872 kb
Host smart-490fe7a8-7f7a-4bbf-a137-0ae453d2a1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515913657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1515913657
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2644510541
Short name T461
Test name
Test status
Simulation time 1420128841 ps
CPU time 5.38 seconds
Started Jul 14 07:06:52 PM PDT 24
Finished Jul 14 07:06:59 PM PDT 24
Peak memory 200432 kb
Host smart-d447b000-401c-4350-8a49-1099d14fd748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644510541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2644510541
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2641551754
Short name T284
Test name
Test status
Simulation time 102071873 ps
CPU time 1.03 seconds
Started Jul 14 07:06:51 PM PDT 24
Finished Jul 14 07:06:54 PM PDT 24
Peak memory 200068 kb
Host smart-3263b64b-d764-4e28-b01b-17cfa1338444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641551754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2641551754
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1307237792
Short name T145
Test name
Test status
Simulation time 259697738 ps
CPU time 1.49 seconds
Started Jul 14 07:06:50 PM PDT 24
Finished Jul 14 07:06:53 PM PDT 24
Peak memory 200356 kb
Host smart-781e9a7b-5fd1-4ee2-9c7e-46b725983744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307237792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1307237792
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1782350923
Short name T412
Test name
Test status
Simulation time 5062702640 ps
CPU time 17.66 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:18 PM PDT 24
Peak memory 210436 kb
Host smart-704d47b1-979f-4d73-aea8-b11e548388f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782350923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1782350923
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3812853178
Short name T318
Test name
Test status
Simulation time 428283050 ps
CPU time 2.35 seconds
Started Jul 14 07:06:51 PM PDT 24
Finished Jul 14 07:06:55 PM PDT 24
Peak memory 208372 kb
Host smart-b97cbe4d-aa8c-4f87-852e-9c40bf170635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812853178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3812853178
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1508600560
Short name T199
Test name
Test status
Simulation time 167691166 ps
CPU time 1.1 seconds
Started Jul 14 07:06:51 PM PDT 24
Finished Jul 14 07:06:53 PM PDT 24
Peak memory 200148 kb
Host smart-4266c789-be8c-416d-8ae9-66a59c54dba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508600560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1508600560
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2323775705
Short name T29
Test name
Test status
Simulation time 64486639 ps
CPU time 0.75 seconds
Started Jul 14 07:06:56 PM PDT 24
Finished Jul 14 07:06:59 PM PDT 24
Peak memory 199856 kb
Host smart-f0456d45-6800-45fb-b7e3-868a194a48eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323775705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2323775705
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2779537805
Short name T414
Test name
Test status
Simulation time 1887712311 ps
CPU time 8.06 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:08 PM PDT 24
Peak memory 217560 kb
Host smart-579b2f2a-b7af-4af8-99a7-26c362e0ebb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779537805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2779537805
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2095780215
Short name T506
Test name
Test status
Simulation time 243987834 ps
CPU time 1.08 seconds
Started Jul 14 07:06:55 PM PDT 24
Finished Jul 14 07:06:59 PM PDT 24
Peak memory 217532 kb
Host smart-3a2e1c7f-c37e-439f-92a1-dcdd0a59300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095780215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2095780215
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1865057276
Short name T491
Test name
Test status
Simulation time 207986584 ps
CPU time 0.9 seconds
Started Jul 14 07:06:52 PM PDT 24
Finished Jul 14 07:06:55 PM PDT 24
Peak memory 199936 kb
Host smart-dfce304d-4bbf-466e-9a9c-3972eb8ed690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865057276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1865057276
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2782923530
Short name T56
Test name
Test status
Simulation time 1167337068 ps
CPU time 4.72 seconds
Started Jul 14 07:06:50 PM PDT 24
Finished Jul 14 07:06:55 PM PDT 24
Peak memory 200388 kb
Host smart-81f7c23b-73b9-4fe4-9e53-20e7f90199d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782923530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2782923530
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2828979556
Short name T373
Test name
Test status
Simulation time 100605583 ps
CPU time 1.03 seconds
Started Jul 14 07:06:54 PM PDT 24
Finished Jul 14 07:06:58 PM PDT 24
Peak memory 200128 kb
Host smart-83b779dd-8e67-42a5-8360-6dd73df7e043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828979556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2828979556
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1230847355
Short name T337
Test name
Test status
Simulation time 257234424 ps
CPU time 1.45 seconds
Started Jul 14 07:06:50 PM PDT 24
Finished Jul 14 07:06:53 PM PDT 24
Peak memory 200348 kb
Host smart-4c000de0-ae98-4e36-9aa6-a1e2207fee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230847355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1230847355
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3052462010
Short name T194
Test name
Test status
Simulation time 166031406 ps
CPU time 1.2 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:05 PM PDT 24
Peak memory 200128 kb
Host smart-b0834b00-ea70-4476-970e-8deb5f81d390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052462010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3052462010
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2105928268
Short name T177
Test name
Test status
Simulation time 392357988 ps
CPU time 2.2 seconds
Started Jul 14 07:06:50 PM PDT 24
Finished Jul 14 07:06:53 PM PDT 24
Peak memory 200156 kb
Host smart-256e9281-f6a4-4926-9dd9-298f54d6bd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105928268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2105928268
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1289943356
Short name T1
Test name
Test status
Simulation time 205401758 ps
CPU time 1.43 seconds
Started Jul 14 07:06:55 PM PDT 24
Finished Jul 14 07:06:58 PM PDT 24
Peak memory 200128 kb
Host smart-a0e561ee-f630-4af8-82ff-295b41283c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289943356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1289943356
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.4224631960
Short name T79
Test name
Test status
Simulation time 94194085 ps
CPU time 0.85 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 199960 kb
Host smart-68199c25-f33c-42dc-91c0-aa225b440d8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224631960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.4224631960
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3388875205
Short name T439
Test name
Test status
Simulation time 1227948539 ps
CPU time 5.63 seconds
Started Jul 14 07:06:56 PM PDT 24
Finished Jul 14 07:07:05 PM PDT 24
Peak memory 217796 kb
Host smart-0d69e8f2-5642-4ee2-821a-12c6430f28be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388875205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3388875205
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.82495910
Short name T262
Test name
Test status
Simulation time 245527534 ps
CPU time 1.03 seconds
Started Jul 14 07:06:56 PM PDT 24
Finished Jul 14 07:07:00 PM PDT 24
Peak memory 217516 kb
Host smart-58917563-dc31-482b-913a-75ddb363cb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82495910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.82495910
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3701395414
Short name T355
Test name
Test status
Simulation time 178616510 ps
CPU time 0.87 seconds
Started Jul 14 07:06:58 PM PDT 24
Finished Jul 14 07:07:02 PM PDT 24
Peak memory 199868 kb
Host smart-ce366108-d67c-4fd7-8fd5-18f3e177cfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701395414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3701395414
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.15763552
Short name T9
Test name
Test status
Simulation time 1299085599 ps
CPU time 5.27 seconds
Started Jul 14 07:06:56 PM PDT 24
Finished Jul 14 07:07:05 PM PDT 24
Peak memory 200404 kb
Host smart-41f56a11-c042-4a5e-b513-40d48bf25105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15763552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.15763552
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1939582226
Short name T268
Test name
Test status
Simulation time 152206934 ps
CPU time 1.07 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 200164 kb
Host smart-0897d1f7-239c-4f13-8314-8a3364fc7132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939582226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1939582226
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3935329381
Short name T263
Test name
Test status
Simulation time 198282593 ps
CPU time 1.32 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:02 PM PDT 24
Peak memory 200360 kb
Host smart-ae4e47b4-825b-4a33-b5d0-abe846b37428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935329381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3935329381
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2305351171
Short name T218
Test name
Test status
Simulation time 151041833 ps
CPU time 1.12 seconds
Started Jul 14 07:07:07 PM PDT 24
Finished Jul 14 07:07:11 PM PDT 24
Peak memory 200144 kb
Host smart-edf3bd2e-c3b1-4589-aaf7-aaf42cef6875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305351171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2305351171
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3318284983
Short name T390
Test name
Test status
Simulation time 127869087 ps
CPU time 1.48 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 200184 kb
Host smart-9e64d942-4c03-4c88-a913-40f33b5bfe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318284983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3318284983
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2673543005
Short name T349
Test name
Test status
Simulation time 116106265 ps
CPU time 0.99 seconds
Started Jul 14 07:06:56 PM PDT 24
Finished Jul 14 07:07:00 PM PDT 24
Peak memory 200172 kb
Host smart-477482d8-7b5e-42a0-bd5b-82f27ee5bb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673543005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2673543005
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2722855093
Short name T164
Test name
Test status
Simulation time 66330028 ps
CPU time 0.79 seconds
Started Jul 14 07:06:56 PM PDT 24
Finished Jul 14 07:06:59 PM PDT 24
Peak memory 199888 kb
Host smart-67b6bd1d-2f23-4817-a0c3-658fce60a11e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722855093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2722855093
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3406528106
Short name T431
Test name
Test status
Simulation time 1227668863 ps
CPU time 5.42 seconds
Started Jul 14 07:06:55 PM PDT 24
Finished Jul 14 07:07:03 PM PDT 24
Peak memory 216996 kb
Host smart-edc1d1d8-4664-487d-9a22-7e549931da74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406528106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3406528106
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1388510221
Short name T275
Test name
Test status
Simulation time 243996145 ps
CPU time 1.18 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:05 PM PDT 24
Peak memory 217480 kb
Host smart-ed4f2a61-0170-4671-b8cd-22000d784a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388510221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1388510221
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3070831151
Short name T315
Test name
Test status
Simulation time 193449205 ps
CPU time 0.96 seconds
Started Jul 14 07:06:56 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 199988 kb
Host smart-a08ef866-85f5-46a8-9301-1da7df6ed4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070831151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3070831151
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.148401169
Short name T432
Test name
Test status
Simulation time 674283501 ps
CPU time 3.65 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:08 PM PDT 24
Peak memory 200428 kb
Host smart-8c33df98-3ab5-41c6-bc3b-d1997ffb2d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148401169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.148401169
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.186088867
Short name T189
Test name
Test status
Simulation time 176404478 ps
CPU time 1.15 seconds
Started Jul 14 07:06:55 PM PDT 24
Finished Jul 14 07:06:58 PM PDT 24
Peak memory 200152 kb
Host smart-4e710919-8455-4d6e-b253-d6d17c236c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186088867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.186088867
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1698795292
Short name T396
Test name
Test status
Simulation time 197332887 ps
CPU time 1.41 seconds
Started Jul 14 07:06:55 PM PDT 24
Finished Jul 14 07:06:58 PM PDT 24
Peak memory 200376 kb
Host smart-978a0516-e9fe-4ecf-b6e6-18081e6e5510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698795292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1698795292
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2776489696
Short name T426
Test name
Test status
Simulation time 6040536673 ps
CPU time 24.69 seconds
Started Jul 14 07:06:58 PM PDT 24
Finished Jul 14 07:07:26 PM PDT 24
Peak memory 200680 kb
Host smart-ea013f4f-f718-4436-98a2-0e027e78ea64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776489696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2776489696
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3016216590
Short name T359
Test name
Test status
Simulation time 440902206 ps
CPU time 2.41 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:02 PM PDT 24
Peak memory 208372 kb
Host smart-e38ee202-3e0e-4533-a185-c235de0828d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016216590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3016216590
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3999943822
Short name T322
Test name
Test status
Simulation time 150780158 ps
CPU time 1.04 seconds
Started Jul 14 07:06:55 PM PDT 24
Finished Jul 14 07:06:58 PM PDT 24
Peak memory 200168 kb
Host smart-013e118b-2f76-4afe-9cb4-a9ae1cbbcc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999943822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3999943822
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3380219155
Short name T158
Test name
Test status
Simulation time 63452944 ps
CPU time 0.77 seconds
Started Jul 14 07:05:49 PM PDT 24
Finished Jul 14 07:05:52 PM PDT 24
Peak memory 199964 kb
Host smart-1ea86ffb-5c5b-4fd5-9d47-642f958cb83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380219155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3380219155
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1717644341
Short name T351
Test name
Test status
Simulation time 2168555840 ps
CPU time 7.75 seconds
Started Jul 14 07:05:50 PM PDT 24
Finished Jul 14 07:06:00 PM PDT 24
Peak memory 217776 kb
Host smart-1a40ed61-1c8f-4b5e-92d9-2d78032c4dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717644341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1717644341
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1588727881
Short name T209
Test name
Test status
Simulation time 243869618 ps
CPU time 1.13 seconds
Started Jul 14 07:06:00 PM PDT 24
Finished Jul 14 07:06:03 PM PDT 24
Peak memory 217504 kb
Host smart-6082eb26-c588-4e5b-8429-4df992bb6e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588727881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1588727881
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3903089235
Short name T450
Test name
Test status
Simulation time 132867331 ps
CPU time 0.82 seconds
Started Jul 14 07:05:50 PM PDT 24
Finished Jul 14 07:05:53 PM PDT 24
Peak memory 199876 kb
Host smart-8727d28a-e89a-4748-969d-7097dfee3587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903089235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3903089235
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.4144547043
Short name T411
Test name
Test status
Simulation time 1670418557 ps
CPU time 5.86 seconds
Started Jul 14 07:05:56 PM PDT 24
Finished Jul 14 07:06:02 PM PDT 24
Peak memory 200436 kb
Host smart-53067dd8-6a2c-4589-b261-085a272377a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144547043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4144547043
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2170753099
Short name T71
Test name
Test status
Simulation time 9007818107 ps
CPU time 13.53 seconds
Started Jul 14 07:05:52 PM PDT 24
Finished Jul 14 07:06:07 PM PDT 24
Peak memory 217328 kb
Host smart-8b6ecc60-554c-4b6c-be04-88c12a9dab05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170753099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2170753099
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2971000060
Short name T215
Test name
Test status
Simulation time 96957533 ps
CPU time 0.96 seconds
Started Jul 14 07:05:55 PM PDT 24
Finished Jul 14 07:05:57 PM PDT 24
Peak memory 200156 kb
Host smart-6b9befac-6c13-4c5e-8b21-895cddc9a124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971000060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2971000060
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1927613545
Short name T452
Test name
Test status
Simulation time 248903357 ps
CPU time 1.51 seconds
Started Jul 14 07:05:53 PM PDT 24
Finished Jul 14 07:05:56 PM PDT 24
Peak memory 200360 kb
Host smart-c1b85098-b15c-4689-998b-d0a9c03d5556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927613545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1927613545
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.294010611
Short name T483
Test name
Test status
Simulation time 1921461268 ps
CPU time 7.43 seconds
Started Jul 14 07:05:50 PM PDT 24
Finished Jul 14 07:05:59 PM PDT 24
Peak memory 200416 kb
Host smart-59b8715c-d0e7-42cd-b928-f5f00bcef557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294010611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.294010611
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3378513768
Short name T112
Test name
Test status
Simulation time 489655898 ps
CPU time 2.45 seconds
Started Jul 14 07:05:49 PM PDT 24
Finished Jul 14 07:05:53 PM PDT 24
Peak memory 200180 kb
Host smart-ecf00d6b-759f-47a2-b779-bb132188f778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378513768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3378513768
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3547306087
Short name T415
Test name
Test status
Simulation time 249416029 ps
CPU time 1.51 seconds
Started Jul 14 07:05:49 PM PDT 24
Finished Jul 14 07:05:53 PM PDT 24
Peak memory 200312 kb
Host smart-b1e2b3fd-9eb5-4624-a926-79b66b85529c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547306087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3547306087
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1577140622
Short name T326
Test name
Test status
Simulation time 1232043992 ps
CPU time 5.42 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:09 PM PDT 24
Peak memory 217424 kb
Host smart-f66d0e17-253a-4555-af63-54adac5d1625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577140622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1577140622
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2822473879
Short name T195
Test name
Test status
Simulation time 243815792 ps
CPU time 1.05 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:05 PM PDT 24
Peak memory 217496 kb
Host smart-bb4a9219-b7c2-4214-b532-2e674f78848b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822473879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2822473879
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3311384228
Short name T308
Test name
Test status
Simulation time 164452884 ps
CPU time 0.85 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 199972 kb
Host smart-1d6c7400-282f-4442-9972-721297d6044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311384228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3311384228
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3313063290
Short name T305
Test name
Test status
Simulation time 1058371672 ps
CPU time 5.17 seconds
Started Jul 14 07:06:58 PM PDT 24
Finished Jul 14 07:07:06 PM PDT 24
Peak memory 200616 kb
Host smart-8160d1ae-f8e1-4677-b7e2-af580d01bb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313063290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3313063290
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2641388168
Short name T453
Test name
Test status
Simulation time 165858501 ps
CPU time 1.18 seconds
Started Jul 14 07:06:56 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 200120 kb
Host smart-79a2a0bd-23bb-4d9f-a573-0298fdd66cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641388168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2641388168
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1700520152
Short name T186
Test name
Test status
Simulation time 255827378 ps
CPU time 1.5 seconds
Started Jul 14 07:06:57 PM PDT 24
Finished Jul 14 07:07:02 PM PDT 24
Peak memory 200304 kb
Host smart-00a51913-69f2-4364-b708-42bae17d4466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700520152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1700520152
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2579243779
Short name T237
Test name
Test status
Simulation time 5313786451 ps
CPU time 19.12 seconds
Started Jul 14 07:06:59 PM PDT 24
Finished Jul 14 07:07:21 PM PDT 24
Peak memory 200468 kb
Host smart-e17b4fd2-2ea3-47cc-b43a-0cabef46bb38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579243779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2579243779
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.908802424
Short name T220
Test name
Test status
Simulation time 435534154 ps
CPU time 2.47 seconds
Started Jul 14 07:07:00 PM PDT 24
Finished Jul 14 07:07:04 PM PDT 24
Peak memory 200204 kb
Host smart-5ee8fe14-5938-492b-853a-46bd970863ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908802424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.908802424
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1962289902
Short name T159
Test name
Test status
Simulation time 100075439 ps
CPU time 1.07 seconds
Started Jul 14 07:06:59 PM PDT 24
Finished Jul 14 07:07:03 PM PDT 24
Peak memory 200164 kb
Host smart-0bdd19fb-a1a3-493e-b198-bc8428170eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962289902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1962289902
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3798388158
Short name T232
Test name
Test status
Simulation time 63038399 ps
CPU time 0.82 seconds
Started Jul 14 07:07:12 PM PDT 24
Finished Jul 14 07:07:15 PM PDT 24
Peak memory 199468 kb
Host smart-09a06415-2e92-4b5d-b8c3-8086ff2a8bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798388158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3798388158
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3240353387
Short name T477
Test name
Test status
Simulation time 1218831229 ps
CPU time 5.23 seconds
Started Jul 14 07:07:03 PM PDT 24
Finished Jul 14 07:07:10 PM PDT 24
Peak memory 221764 kb
Host smart-7745757a-e086-4475-93b8-298215be36f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240353387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3240353387
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3679814763
Short name T250
Test name
Test status
Simulation time 244447205 ps
CPU time 1.12 seconds
Started Jul 14 07:07:03 PM PDT 24
Finished Jul 14 07:07:06 PM PDT 24
Peak memory 217516 kb
Host smart-22611885-15e4-4f21-a112-7ce53b3ae754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679814763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3679814763
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.703307673
Short name T529
Test name
Test status
Simulation time 153916655 ps
CPU time 0.87 seconds
Started Jul 14 07:06:59 PM PDT 24
Finished Jul 14 07:07:02 PM PDT 24
Peak memory 199944 kb
Host smart-6ba26eab-4597-41da-8581-66af82a75653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703307673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.703307673
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2007200396
Short name T114
Test name
Test status
Simulation time 1101962714 ps
CPU time 5.55 seconds
Started Jul 14 07:07:04 PM PDT 24
Finished Jul 14 07:07:11 PM PDT 24
Peak memory 200440 kb
Host smart-1fc40feb-23ae-42ac-a623-f72f83d353b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007200396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2007200396
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3748075620
Short name T518
Test name
Test status
Simulation time 94616765 ps
CPU time 0.97 seconds
Started Jul 14 07:07:01 PM PDT 24
Finished Jul 14 07:07:04 PM PDT 24
Peak memory 200124 kb
Host smart-8c74f54a-074e-4767-8f35-a2880334b11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748075620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3748075620
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1829368558
Short name T538
Test name
Test status
Simulation time 116272062 ps
CPU time 1.22 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:05 PM PDT 24
Peak memory 200304 kb
Host smart-3a3fe2d7-cc97-4b4a-8fa8-c8559e600a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829368558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1829368558
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3903885222
Short name T170
Test name
Test status
Simulation time 144445174 ps
CPU time 1.21 seconds
Started Jul 14 07:07:05 PM PDT 24
Finished Jul 14 07:07:07 PM PDT 24
Peak memory 199924 kb
Host smart-642758e3-47d7-4a95-bed3-9bd25f463474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903885222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3903885222
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2643115746
Short name T85
Test name
Test status
Simulation time 107071826 ps
CPU time 1.45 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:05 PM PDT 24
Peak memory 200176 kb
Host smart-e7863713-2580-4ee6-826c-635fa448ee0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643115746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2643115746
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3911464745
Short name T80
Test name
Test status
Simulation time 148495078 ps
CPU time 1.14 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:05 PM PDT 24
Peak memory 200124 kb
Host smart-d66379f5-4343-4342-bef4-96a555869348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911464745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3911464745
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2350754277
Short name T428
Test name
Test status
Simulation time 73498704 ps
CPU time 0.81 seconds
Started Jul 14 07:07:12 PM PDT 24
Finished Jul 14 07:07:15 PM PDT 24
Peak memory 199788 kb
Host smart-79e15d02-510d-4607-8ba9-4b630ae1c6ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350754277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2350754277
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2840962876
Short name T307
Test name
Test status
Simulation time 1222657319 ps
CPU time 5.43 seconds
Started Jul 14 07:07:03 PM PDT 24
Finished Jul 14 07:07:11 PM PDT 24
Peak memory 221776 kb
Host smart-ec37f828-bb04-412d-a0a0-ca6a2c92fe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840962876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2840962876
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1691528903
Short name T219
Test name
Test status
Simulation time 244289639 ps
CPU time 1.12 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:09 PM PDT 24
Peak memory 217360 kb
Host smart-848314be-c1f7-42b3-9389-1419c505217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691528903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1691528903
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1119546857
Short name T291
Test name
Test status
Simulation time 83527549 ps
CPU time 0.73 seconds
Started Jul 14 07:07:05 PM PDT 24
Finished Jul 14 07:07:08 PM PDT 24
Peak memory 199996 kb
Host smart-b3a81b7d-e86a-4e9e-a255-a235ac772e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119546857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1119546857
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.614601004
Short name T137
Test name
Test status
Simulation time 2138723875 ps
CPU time 7.8 seconds
Started Jul 14 07:07:05 PM PDT 24
Finished Jul 14 07:07:14 PM PDT 24
Peak memory 200436 kb
Host smart-aec53b96-bdab-450c-a495-4639822fd823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614601004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.614601004
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.383693573
Short name T138
Test name
Test status
Simulation time 169583808 ps
CPU time 1.13 seconds
Started Jul 14 07:07:03 PM PDT 24
Finished Jul 14 07:07:06 PM PDT 24
Peak memory 200120 kb
Host smart-c8de3172-44e0-465f-8340-9f43147c8ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383693573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.383693573
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1551222567
Short name T113
Test name
Test status
Simulation time 233981571 ps
CPU time 1.46 seconds
Started Jul 14 07:07:04 PM PDT 24
Finished Jul 14 07:07:07 PM PDT 24
Peak memory 200320 kb
Host smart-daa6d8fa-565d-412a-ac5e-896bac05b23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551222567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1551222567
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1671319449
Short name T283
Test name
Test status
Simulation time 11505032457 ps
CPU time 37.8 seconds
Started Jul 14 07:07:12 PM PDT 24
Finished Jul 14 07:07:52 PM PDT 24
Peak memory 210436 kb
Host smart-df133197-0907-45e7-b69a-8afee8fe4942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671319449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1671319449
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1641092157
Short name T527
Test name
Test status
Simulation time 319664240 ps
CPU time 2.17 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:10 PM PDT 24
Peak memory 200176 kb
Host smart-041d6445-97dc-4b89-8717-86a88870274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641092157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1641092157
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2543836592
Short name T502
Test name
Test status
Simulation time 219867829 ps
CPU time 1.3 seconds
Started Jul 14 07:07:05 PM PDT 24
Finished Jul 14 07:07:08 PM PDT 24
Peak memory 200148 kb
Host smart-a0959407-a2f1-4e28-b9a2-ced25258ee08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543836592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2543836592
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3799694171
Short name T207
Test name
Test status
Simulation time 76068630 ps
CPU time 0.77 seconds
Started Jul 14 07:07:12 PM PDT 24
Finished Jul 14 07:07:15 PM PDT 24
Peak memory 199836 kb
Host smart-ffea1301-cd9b-4552-850e-ec3c6c0f2e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799694171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3799694171
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1552745054
Short name T402
Test name
Test status
Simulation time 245356774 ps
CPU time 1.07 seconds
Started Jul 14 07:07:12 PM PDT 24
Finished Jul 14 07:07:15 PM PDT 24
Peak memory 217468 kb
Host smart-ae36c6be-6064-4c7c-8148-778f7c2c4bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552745054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1552745054
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2389077667
Short name T19
Test name
Test status
Simulation time 153369934 ps
CPU time 0.87 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:08 PM PDT 24
Peak memory 199960 kb
Host smart-1b05b0df-78ca-4410-85fc-664d864749b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389077667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2389077667
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.644641672
Short name T336
Test name
Test status
Simulation time 1422833355 ps
CPU time 6.01 seconds
Started Jul 14 07:07:01 PM PDT 24
Finished Jul 14 07:07:09 PM PDT 24
Peak memory 200424 kb
Host smart-03ef0ffe-08ff-4bf2-a0cb-0364da9f1806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644641672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.644641672
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2970131015
Short name T13
Test name
Test status
Simulation time 149526307 ps
CPU time 1.09 seconds
Started Jul 14 07:07:03 PM PDT 24
Finished Jul 14 07:07:06 PM PDT 24
Peak memory 200164 kb
Host smart-cbd83f84-71e8-445b-98cb-498089b4136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970131015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2970131015
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1984170240
Short name T503
Test name
Test status
Simulation time 252107084 ps
CPU time 1.43 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:05 PM PDT 24
Peak memory 200360 kb
Host smart-7ca5cb7c-4e54-4d04-b5b7-abf72f309459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984170240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1984170240
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3638146618
Short name T297
Test name
Test status
Simulation time 1466883722 ps
CPU time 6.85 seconds
Started Jul 14 07:07:03 PM PDT 24
Finished Jul 14 07:07:12 PM PDT 24
Peak memory 208668 kb
Host smart-fbfa727b-e030-48bf-aaf9-a12c38f0092b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638146618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3638146618
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.654487389
Short name T360
Test name
Test status
Simulation time 139524196 ps
CPU time 1.75 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:06 PM PDT 24
Peak memory 200140 kb
Host smart-c9e45817-1fe6-424d-b1cd-572d9c862d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654487389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.654487389
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3492437489
Short name T304
Test name
Test status
Simulation time 64707344 ps
CPU time 0.77 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:05 PM PDT 24
Peak memory 200124 kb
Host smart-0f0292d8-cf44-4366-a6f7-89d1fd2e2351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492437489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3492437489
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3531438443
Short name T377
Test name
Test status
Simulation time 75413938 ps
CPU time 0.77 seconds
Started Jul 14 07:07:02 PM PDT 24
Finished Jul 14 07:07:04 PM PDT 24
Peak memory 199964 kb
Host smart-73b2be15-d073-4418-8751-6213f0d92c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531438443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3531438443
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2318098177
Short name T388
Test name
Test status
Simulation time 1879328895 ps
CPU time 7.24 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:15 PM PDT 24
Peak memory 217716 kb
Host smart-ffd38604-017f-4df4-9f09-0a050d541970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318098177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2318098177
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.758877311
Short name T533
Test name
Test status
Simulation time 243981413 ps
CPU time 1.13 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:10 PM PDT 24
Peak memory 217456 kb
Host smart-5fed6231-efeb-4558-95fc-fd8dfd1eea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758877311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.758877311
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3397322669
Short name T18
Test name
Test status
Simulation time 226413253 ps
CPU time 0.9 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:08 PM PDT 24
Peak memory 199884 kb
Host smart-35c3eaea-d07d-4120-8ad8-10c3ce28566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397322669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3397322669
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.862008995
Short name T367
Test name
Test status
Simulation time 843908385 ps
CPU time 4.08 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:12 PM PDT 24
Peak memory 200440 kb
Host smart-8a8692f8-07c0-4b25-8dc9-2c72bf00f61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862008995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.862008995
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.4085303603
Short name T301
Test name
Test status
Simulation time 102361860 ps
CPU time 0.99 seconds
Started Jul 14 07:07:05 PM PDT 24
Finished Jul 14 07:07:07 PM PDT 24
Peak memory 200184 kb
Host smart-377ecbf9-6785-4784-975c-ebad44fc14f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085303603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.4085303603
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.492199743
Short name T89
Test name
Test status
Simulation time 201705138 ps
CPU time 1.38 seconds
Started Jul 14 07:07:12 PM PDT 24
Finished Jul 14 07:07:15 PM PDT 24
Peak memory 199960 kb
Host smart-3d9e27d4-634b-4166-bc1d-0664879d08ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492199743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.492199743
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2296446925
Short name T438
Test name
Test status
Simulation time 145743622 ps
CPU time 1.67 seconds
Started Jul 14 07:07:05 PM PDT 24
Finished Jul 14 07:07:09 PM PDT 24
Peak memory 208372 kb
Host smart-a75a4170-047c-4489-84b7-536d29899e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296446925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2296446925
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.804648657
Short name T212
Test name
Test status
Simulation time 123581597 ps
CPU time 1 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:08 PM PDT 24
Peak memory 200160 kb
Host smart-7f972386-ac22-44cf-8ca9-2a28cf2bb028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804648657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.804648657
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2151136009
Short name T160
Test name
Test status
Simulation time 71693840 ps
CPU time 0.74 seconds
Started Jul 14 07:07:10 PM PDT 24
Finished Jul 14 07:07:13 PM PDT 24
Peak memory 199964 kb
Host smart-17291803-3b87-407b-acff-9a96a1e06970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151136009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2151136009
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2234901868
Short name T429
Test name
Test status
Simulation time 2366887693 ps
CPU time 7.83 seconds
Started Jul 14 07:07:11 PM PDT 24
Finished Jul 14 07:07:20 PM PDT 24
Peak memory 217924 kb
Host smart-aa57e102-d5ed-44cf-8a55-5e562b899651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234901868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2234901868
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.765166242
Short name T469
Test name
Test status
Simulation time 244665093 ps
CPU time 1.06 seconds
Started Jul 14 07:07:14 PM PDT 24
Finished Jul 14 07:07:17 PM PDT 24
Peak memory 217536 kb
Host smart-cbbf0b29-c325-4ca8-b740-1b6e128e664a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765166242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.765166242
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1180441682
Short name T211
Test name
Test status
Simulation time 76905286 ps
CPU time 0.71 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:08 PM PDT 24
Peak memory 199996 kb
Host smart-1af115c7-fed8-46aa-87e5-5ac61ca87aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180441682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1180441682
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1938698856
Short name T480
Test name
Test status
Simulation time 944880199 ps
CPU time 4.33 seconds
Started Jul 14 07:07:04 PM PDT 24
Finished Jul 14 07:07:10 PM PDT 24
Peak memory 200412 kb
Host smart-4678bff5-626a-44a0-9ac5-f88fbdfe0c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938698856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1938698856
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.995279702
Short name T401
Test name
Test status
Simulation time 183703604 ps
CPU time 1.22 seconds
Started Jul 14 07:07:09 PM PDT 24
Finished Jul 14 07:07:12 PM PDT 24
Peak memory 200128 kb
Host smart-8d53fe63-05c9-46be-aa55-8f276e1fefe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995279702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.995279702
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1675883872
Short name T454
Test name
Test status
Simulation time 250578619 ps
CPU time 1.49 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:09 PM PDT 24
Peak memory 200376 kb
Host smart-ef58c1fb-a05a-4243-b3bb-abcb944c363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675883872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1675883872
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.696466750
Short name T115
Test name
Test status
Simulation time 2204623127 ps
CPU time 8.03 seconds
Started Jul 14 07:07:07 PM PDT 24
Finished Jul 14 07:07:17 PM PDT 24
Peak memory 200544 kb
Host smart-fd899d22-4b68-4971-8f9b-768878a44f53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696466750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.696466750
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.284234346
Short name T470
Test name
Test status
Simulation time 377077033 ps
CPU time 2.19 seconds
Started Jul 14 07:07:13 PM PDT 24
Finished Jul 14 07:07:16 PM PDT 24
Peak memory 200176 kb
Host smart-f62f9179-2a1e-44f0-bb88-6486dc2e747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284234346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.284234346
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3247243187
Short name T292
Test name
Test status
Simulation time 161078520 ps
CPU time 1.25 seconds
Started Jul 14 07:07:04 PM PDT 24
Finished Jul 14 07:07:07 PM PDT 24
Peak memory 200392 kb
Host smart-664374d4-c0dd-49f3-bf74-8b39fe714fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247243187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3247243187
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.72050540
Short name T344
Test name
Test status
Simulation time 67779220 ps
CPU time 0.76 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:08 PM PDT 24
Peak memory 199960 kb
Host smart-1712f6aa-d1eb-486a-a5eb-d3c752f208c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72050540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.72050540
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3756987333
Short name T468
Test name
Test status
Simulation time 2352585524 ps
CPU time 7.89 seconds
Started Jul 14 07:07:14 PM PDT 24
Finished Jul 14 07:07:23 PM PDT 24
Peak memory 221780 kb
Host smart-76419cb6-ce2c-4a17-9650-4bdd920aba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756987333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3756987333
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1056988933
Short name T236
Test name
Test status
Simulation time 244981264 ps
CPU time 1.04 seconds
Started Jul 14 07:07:08 PM PDT 24
Finished Jul 14 07:07:11 PM PDT 24
Peak memory 217472 kb
Host smart-bdd237ae-2a0a-4deb-9e11-379838b80b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056988933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1056988933
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3547817063
Short name T76
Test name
Test status
Simulation time 199036242 ps
CPU time 0.9 seconds
Started Jul 14 07:07:10 PM PDT 24
Finished Jul 14 07:07:13 PM PDT 24
Peak memory 199960 kb
Host smart-bc31cc02-88f9-4452-9f98-11550a9899fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547817063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3547817063
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.4117415192
Short name T243
Test name
Test status
Simulation time 1651510777 ps
CPU time 6.58 seconds
Started Jul 14 07:07:07 PM PDT 24
Finished Jul 14 07:07:16 PM PDT 24
Peak memory 200408 kb
Host smart-4681a1e4-b8db-4215-b01e-c6ed86c8609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117415192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.4117415192
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3126760380
Short name T175
Test name
Test status
Simulation time 94407569 ps
CPU time 1.05 seconds
Started Jul 14 07:07:07 PM PDT 24
Finished Jul 14 07:07:10 PM PDT 24
Peak memory 200132 kb
Host smart-706860de-512d-4b7a-b428-3e0a5201dc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126760380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3126760380
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2332206607
Short name T330
Test name
Test status
Simulation time 261370182 ps
CPU time 1.5 seconds
Started Jul 14 07:07:09 PM PDT 24
Finished Jul 14 07:07:12 PM PDT 24
Peak memory 200376 kb
Host smart-826514c5-9552-4153-bc48-0034c7b327bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332206607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2332206607
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1577496296
Short name T222
Test name
Test status
Simulation time 992457708 ps
CPU time 4.75 seconds
Started Jul 14 07:07:10 PM PDT 24
Finished Jul 14 07:07:16 PM PDT 24
Peak memory 200476 kb
Host smart-b7e56b45-8aa8-4f52-ad9f-afcaf63e31e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577496296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1577496296
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.150662793
Short name T271
Test name
Test status
Simulation time 369450834 ps
CPU time 2.08 seconds
Started Jul 14 07:07:10 PM PDT 24
Finished Jul 14 07:07:14 PM PDT 24
Peak memory 200132 kb
Host smart-71d21d05-4765-48a5-930e-1c2718c9730d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150662793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.150662793
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2150367245
Short name T479
Test name
Test status
Simulation time 108362030 ps
CPU time 1.05 seconds
Started Jul 14 07:07:11 PM PDT 24
Finished Jul 14 07:07:14 PM PDT 24
Peak memory 200164 kb
Host smart-a3ade7d3-4c14-4227-9ee8-cc0c88656040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150367245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2150367245
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.295565000
Short name T221
Test name
Test status
Simulation time 69563925 ps
CPU time 0.75 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:09 PM PDT 24
Peak memory 199936 kb
Host smart-fd80220b-1aac-4afc-8b4f-0d5b84a4bac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295565000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.295565000
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2554445565
Short name T34
Test name
Test status
Simulation time 2182808048 ps
CPU time 8.61 seconds
Started Jul 14 07:07:08 PM PDT 24
Finished Jul 14 07:07:18 PM PDT 24
Peak memory 217636 kb
Host smart-dd3e7ad2-85a6-4304-88e7-fe3435fefd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554445565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2554445565
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.96432109
Short name T474
Test name
Test status
Simulation time 244113991 ps
CPU time 1.16 seconds
Started Jul 14 07:07:09 PM PDT 24
Finished Jul 14 07:07:12 PM PDT 24
Peak memory 217468 kb
Host smart-547d9fd1-5158-4dc6-ae6e-b8700e1a1cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96432109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.96432109
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3350132865
Short name T310
Test name
Test status
Simulation time 234286512 ps
CPU time 0.92 seconds
Started Jul 14 07:07:08 PM PDT 24
Finished Jul 14 07:07:11 PM PDT 24
Peak memory 199912 kb
Host smart-f27845cc-0301-47c0-b3e0-8738c0fe55ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350132865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3350132865
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3382295819
Short name T206
Test name
Test status
Simulation time 827533616 ps
CPU time 3.92 seconds
Started Jul 14 07:07:10 PM PDT 24
Finished Jul 14 07:07:16 PM PDT 24
Peak memory 200444 kb
Host smart-a9eec3e6-edc9-44e7-be5a-ba260905d64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382295819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3382295819
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1539405210
Short name T295
Test name
Test status
Simulation time 106485595 ps
CPU time 1.07 seconds
Started Jul 14 07:07:15 PM PDT 24
Finished Jul 14 07:07:18 PM PDT 24
Peak memory 200156 kb
Host smart-8b40be18-9e50-49a6-8ba2-1078bc54456b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539405210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1539405210
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1275597036
Short name T168
Test name
Test status
Simulation time 121499712 ps
CPU time 1.21 seconds
Started Jul 14 07:07:12 PM PDT 24
Finished Jul 14 07:07:15 PM PDT 24
Peak memory 200376 kb
Host smart-ed709478-ecb2-46b2-bec3-03c129d18aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275597036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1275597036
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2632562655
Short name T535
Test name
Test status
Simulation time 16195036529 ps
CPU time 59.09 seconds
Started Jul 14 07:07:11 PM PDT 24
Finished Jul 14 07:08:12 PM PDT 24
Peak memory 208700 kb
Host smart-8dc246d2-65d4-43d7-9d5a-781ec61f6df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632562655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2632562655
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1560462374
Short name T197
Test name
Test status
Simulation time 375615497 ps
CPU time 2.31 seconds
Started Jul 14 07:07:12 PM PDT 24
Finished Jul 14 07:07:16 PM PDT 24
Peak memory 200176 kb
Host smart-cf036756-a68c-418c-b6b5-19f0e9977359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560462374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1560462374
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3630351846
Short name T264
Test name
Test status
Simulation time 272248538 ps
CPU time 1.48 seconds
Started Jul 14 07:07:08 PM PDT 24
Finished Jul 14 07:07:11 PM PDT 24
Peak memory 200128 kb
Host smart-518161aa-6b46-42b8-95bd-2ca858123d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630351846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3630351846
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2681281599
Short name T174
Test name
Test status
Simulation time 74372435 ps
CPU time 0.84 seconds
Started Jul 14 07:07:09 PM PDT 24
Finished Jul 14 07:07:12 PM PDT 24
Peak memory 199948 kb
Host smart-b4f1b616-6dc8-4a19-aba9-6ffcd31f345b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681281599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2681281599
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2349696852
Short name T451
Test name
Test status
Simulation time 1217215723 ps
CPU time 5.71 seconds
Started Jul 14 07:07:11 PM PDT 24
Finished Jul 14 07:07:19 PM PDT 24
Peak memory 217528 kb
Host smart-48186922-5ef3-4ed2-b62d-4466056c6b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349696852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2349696852
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2743331196
Short name T321
Test name
Test status
Simulation time 245081066 ps
CPU time 1.05 seconds
Started Jul 14 07:07:07 PM PDT 24
Finished Jul 14 07:07:11 PM PDT 24
Peak memory 217484 kb
Host smart-aa6d4e1a-ef05-4153-bce3-626ff1985843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743331196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2743331196
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1713137051
Short name T456
Test name
Test status
Simulation time 165955913 ps
CPU time 0.9 seconds
Started Jul 14 07:07:10 PM PDT 24
Finished Jul 14 07:07:13 PM PDT 24
Peak memory 199968 kb
Host smart-e977af1c-a129-4860-a561-14e3ea7da357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713137051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1713137051
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2376270514
Short name T57
Test name
Test status
Simulation time 2046708770 ps
CPU time 7.13 seconds
Started Jul 14 07:07:09 PM PDT 24
Finished Jul 14 07:07:17 PM PDT 24
Peak memory 200424 kb
Host smart-4e8b40c3-b43f-416c-910d-75950c9f4b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376270514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2376270514
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2480383441
Short name T258
Test name
Test status
Simulation time 182325590 ps
CPU time 1.27 seconds
Started Jul 14 07:07:10 PM PDT 24
Finished Jul 14 07:07:14 PM PDT 24
Peak memory 200112 kb
Host smart-9367c6fb-4d1e-4e6d-8ec1-3d3e8223fbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480383441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2480383441
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1287354418
Short name T316
Test name
Test status
Simulation time 190609860 ps
CPU time 1.44 seconds
Started Jul 14 07:07:08 PM PDT 24
Finished Jul 14 07:07:12 PM PDT 24
Peak memory 200348 kb
Host smart-c37ac323-b15c-4679-872d-098f137addf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287354418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1287354418
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3440055759
Short name T101
Test name
Test status
Simulation time 2589630134 ps
CPU time 12.92 seconds
Started Jul 14 07:07:07 PM PDT 24
Finished Jul 14 07:07:22 PM PDT 24
Peak memory 200440 kb
Host smart-b3d86755-e07d-420e-9999-6f49426e129b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440055759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3440055759
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1829628219
Short name T406
Test name
Test status
Simulation time 390320644 ps
CPU time 2.11 seconds
Started Jul 14 07:07:06 PM PDT 24
Finished Jul 14 07:07:11 PM PDT 24
Peak memory 200176 kb
Host smart-23e5056e-7937-4f8e-b501-1c215464e179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829628219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1829628219
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.381535752
Short name T476
Test name
Test status
Simulation time 128856960 ps
CPU time 1.22 seconds
Started Jul 14 07:07:09 PM PDT 24
Finished Jul 14 07:07:12 PM PDT 24
Peak memory 200132 kb
Host smart-c0ff4863-7e2a-4a40-a672-ae89f489f3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381535752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.381535752
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1384346289
Short name T280
Test name
Test status
Simulation time 68407413 ps
CPU time 0.74 seconds
Started Jul 14 07:07:13 PM PDT 24
Finished Jul 14 07:07:15 PM PDT 24
Peak memory 199952 kb
Host smart-b2b7e113-af80-47f1-9f0a-50676907cec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384346289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1384346289
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2891510220
Short name T463
Test name
Test status
Simulation time 1224173447 ps
CPU time 5.3 seconds
Started Jul 14 07:07:16 PM PDT 24
Finished Jul 14 07:07:24 PM PDT 24
Peak memory 217684 kb
Host smart-99314048-1493-4de7-9fae-9024a87a4651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891510220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2891510220
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1491014269
Short name T169
Test name
Test status
Simulation time 244663971 ps
CPU time 1.06 seconds
Started Jul 14 07:07:17 PM PDT 24
Finished Jul 14 07:07:20 PM PDT 24
Peak memory 217504 kb
Host smart-44e5945f-f1e7-4f3d-bc60-4cc851430d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491014269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1491014269
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1572897757
Short name T285
Test name
Test status
Simulation time 207656671 ps
CPU time 1.03 seconds
Started Jul 14 07:07:14 PM PDT 24
Finished Jul 14 07:07:17 PM PDT 24
Peak memory 199972 kb
Host smart-c600e8ed-e8b7-413b-8eea-b94d093c7a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572897757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1572897757
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1098582889
Short name T227
Test name
Test status
Simulation time 766327547 ps
CPU time 4.02 seconds
Started Jul 14 07:07:14 PM PDT 24
Finished Jul 14 07:07:20 PM PDT 24
Peak memory 200456 kb
Host smart-21f86dd2-37b3-4c0a-b58a-f3aba52f6b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098582889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1098582889
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2046796878
Short name T154
Test name
Test status
Simulation time 157494085 ps
CPU time 1.13 seconds
Started Jul 14 07:07:15 PM PDT 24
Finished Jul 14 07:07:18 PM PDT 24
Peak memory 200116 kb
Host smart-3bbac1c3-4405-4b54-a139-1cd27204c3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046796878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2046796878
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3973967273
Short name T157
Test name
Test status
Simulation time 186868309 ps
CPU time 1.42 seconds
Started Jul 14 07:07:08 PM PDT 24
Finished Jul 14 07:07:12 PM PDT 24
Peak memory 200260 kb
Host smart-6a0243ce-703b-4832-9283-bfa3fb13a5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973967273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3973967273
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1556952867
Short name T188
Test name
Test status
Simulation time 207111675 ps
CPU time 1.35 seconds
Started Jul 14 07:07:19 PM PDT 24
Finished Jul 14 07:07:22 PM PDT 24
Peak memory 200348 kb
Host smart-de4132f3-6da8-4e34-b269-54e0726ca15e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556952867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1556952867
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3062368516
Short name T368
Test name
Test status
Simulation time 118828840 ps
CPU time 1.5 seconds
Started Jul 14 07:07:16 PM PDT 24
Finished Jul 14 07:07:19 PM PDT 24
Peak memory 200128 kb
Host smart-b1f70b58-b028-454b-a24c-5d1da056ff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062368516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3062368516
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1733532248
Short name T370
Test name
Test status
Simulation time 116205260 ps
CPU time 0.93 seconds
Started Jul 14 07:07:14 PM PDT 24
Finished Jul 14 07:07:17 PM PDT 24
Peak memory 200164 kb
Host smart-f45b8f4d-a19b-4891-9d41-68bc34d73d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733532248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1733532248
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2257874412
Short name T288
Test name
Test status
Simulation time 59829614 ps
CPU time 0.72 seconds
Started Jul 14 07:05:50 PM PDT 24
Finished Jul 14 07:05:53 PM PDT 24
Peak memory 199908 kb
Host smart-9b241b6b-c7bf-4b25-8666-b2ec4b4405ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257874412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2257874412
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1932548637
Short name T485
Test name
Test status
Simulation time 2352178497 ps
CPU time 8.13 seconds
Started Jul 14 07:05:51 PM PDT 24
Finished Jul 14 07:06:01 PM PDT 24
Peak memory 217908 kb
Host smart-c1133ff7-abed-47dc-9d07-5250164c7977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932548637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1932548637
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2002530599
Short name T251
Test name
Test status
Simulation time 244662019 ps
CPU time 1.02 seconds
Started Jul 14 07:05:52 PM PDT 24
Finished Jul 14 07:05:54 PM PDT 24
Peak memory 217544 kb
Host smart-47480e9e-96b1-4064-85a9-4333ad4e78df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002530599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2002530599
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2806609062
Short name T531
Test name
Test status
Simulation time 150490698 ps
CPU time 0.88 seconds
Started Jul 14 07:06:02 PM PDT 24
Finished Jul 14 07:06:04 PM PDT 24
Peak memory 199956 kb
Host smart-cc84ebe1-4c93-4593-918e-63321e87bb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806609062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2806609062
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1374061241
Short name T126
Test name
Test status
Simulation time 1692756372 ps
CPU time 7.22 seconds
Started Jul 14 07:05:51 PM PDT 24
Finished Jul 14 07:06:00 PM PDT 24
Peak memory 200436 kb
Host smart-965eee94-1ebe-43c0-8714-fb9783110aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374061241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1374061241
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3351557187
Short name T441
Test name
Test status
Simulation time 147272016 ps
CPU time 1.12 seconds
Started Jul 14 07:06:00 PM PDT 24
Finished Jul 14 07:06:03 PM PDT 24
Peak memory 200144 kb
Host smart-8fc88682-88a4-497b-97b2-4589b935d87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351557187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3351557187
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1369126463
Short name T279
Test name
Test status
Simulation time 120982679 ps
CPU time 1.16 seconds
Started Jul 14 07:05:52 PM PDT 24
Finished Jul 14 07:05:55 PM PDT 24
Peak memory 200328 kb
Host smart-bbc8dca7-4b59-4244-9a6f-e687f0013359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369126463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1369126463
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.432384394
Short name T472
Test name
Test status
Simulation time 13802055196 ps
CPU time 54.05 seconds
Started Jul 14 07:05:54 PM PDT 24
Finished Jul 14 07:06:49 PM PDT 24
Peak memory 208664 kb
Host smart-34ea4df1-1fea-4d83-9d9d-0596d40bdf8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432384394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.432384394
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.242620244
Short name T204
Test name
Test status
Simulation time 73412577 ps
CPU time 0.78 seconds
Started Jul 14 07:05:53 PM PDT 24
Finished Jul 14 07:05:55 PM PDT 24
Peak memory 200084 kb
Host smart-96dd6cb0-9a89-455a-bf52-237d56c74803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242620244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.242620244
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.439757629
Short name T180
Test name
Test status
Simulation time 78899129 ps
CPU time 0.81 seconds
Started Jul 14 07:05:58 PM PDT 24
Finished Jul 14 07:05:59 PM PDT 24
Peak memory 199976 kb
Host smart-6b020586-d784-4a86-9e2c-7d05dfd492bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439757629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.439757629
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1410088249
Short name T33
Test name
Test status
Simulation time 2161709867 ps
CPU time 7.45 seconds
Started Jul 14 07:05:59 PM PDT 24
Finished Jul 14 07:06:08 PM PDT 24
Peak memory 217692 kb
Host smart-522ead0c-bb9b-42ec-a56d-b0d57f13ff41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410088249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1410088249
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1387505788
Short name T223
Test name
Test status
Simulation time 245028542 ps
CPU time 1.06 seconds
Started Jul 14 07:05:58 PM PDT 24
Finished Jul 14 07:05:59 PM PDT 24
Peak memory 217540 kb
Host smart-7c9f53ca-5e3c-430a-ac43-367b36100277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387505788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1387505788
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2625190468
Short name T514
Test name
Test status
Simulation time 143022909 ps
CPU time 0.82 seconds
Started Jul 14 07:05:50 PM PDT 24
Finished Jul 14 07:05:53 PM PDT 24
Peak memory 199936 kb
Host smart-20e5b964-fe81-4b4d-9fbe-08316b22e1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625190468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2625190468
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.114030544
Short name T100
Test name
Test status
Simulation time 739910829 ps
CPU time 3.58 seconds
Started Jul 14 07:05:53 PM PDT 24
Finished Jul 14 07:05:58 PM PDT 24
Peak memory 200468 kb
Host smart-7b4befa6-021b-47c6-b222-9310d143c6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114030544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.114030544
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2267634121
Short name T109
Test name
Test status
Simulation time 175082881 ps
CPU time 1.2 seconds
Started Jul 14 07:05:59 PM PDT 24
Finished Jul 14 07:06:02 PM PDT 24
Peak memory 200108 kb
Host smart-f8a90a0e-0d64-4827-b00d-809fbec9047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267634121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2267634121
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.998258417
Short name T389
Test name
Test status
Simulation time 229745605 ps
CPU time 1.42 seconds
Started Jul 14 07:05:50 PM PDT 24
Finished Jul 14 07:05:53 PM PDT 24
Peak memory 200372 kb
Host smart-7e21402a-3731-419b-9192-9eae6dd4513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998258417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.998258417
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3035336096
Short name T26
Test name
Test status
Simulation time 9190896793 ps
CPU time 33.72 seconds
Started Jul 14 07:06:03 PM PDT 24
Finished Jul 14 07:06:38 PM PDT 24
Peak memory 200508 kb
Host smart-b265e740-0edd-498e-a806-20cac3a3f92d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035336096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3035336096
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3792908589
Short name T213
Test name
Test status
Simulation time 426284810 ps
CPU time 2.28 seconds
Started Jul 14 07:05:57 PM PDT 24
Finished Jul 14 07:06:00 PM PDT 24
Peak memory 208348 kb
Host smart-4581a43a-ff65-4aa9-a21c-1305649a8d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792908589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3792908589
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.140055633
Short name T46
Test name
Test status
Simulation time 180778621 ps
CPU time 1.22 seconds
Started Jul 14 07:05:59 PM PDT 24
Finished Jul 14 07:06:01 PM PDT 24
Peak memory 200388 kb
Host smart-8f590688-1c74-4adf-aafb-e5e962648fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140055633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.140055633
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3167250242
Short name T47
Test name
Test status
Simulation time 75123690 ps
CPU time 0.76 seconds
Started Jul 14 07:06:00 PM PDT 24
Finished Jul 14 07:06:02 PM PDT 24
Peak memory 200148 kb
Host smart-a68779f3-5252-4423-b12a-c5f15b01a7b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167250242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3167250242
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3767643819
Short name T42
Test name
Test status
Simulation time 1898588388 ps
CPU time 6.93 seconds
Started Jul 14 07:05:58 PM PDT 24
Finished Jul 14 07:06:06 PM PDT 24
Peak memory 217684 kb
Host smart-dd86b7dd-12b5-4841-9353-fe29784906b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767643819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3767643819
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1979675986
Short name T4
Test name
Test status
Simulation time 243196949 ps
CPU time 1.08 seconds
Started Jul 14 07:06:00 PM PDT 24
Finished Jul 14 07:06:02 PM PDT 24
Peak memory 217464 kb
Host smart-122ea539-d89e-4ec4-a66f-2aeb259ed58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979675986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1979675986
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1955139016
Short name T413
Test name
Test status
Simulation time 206613543 ps
CPU time 0.98 seconds
Started Jul 14 07:05:59 PM PDT 24
Finished Jul 14 07:06:01 PM PDT 24
Peak memory 199940 kb
Host smart-2080b8a2-79b4-4751-922b-aa5669ed9f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955139016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1955139016
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1108608229
Short name T361
Test name
Test status
Simulation time 1556964764 ps
CPU time 5.95 seconds
Started Jul 14 07:05:59 PM PDT 24
Finished Jul 14 07:06:06 PM PDT 24
Peak memory 200432 kb
Host smart-43e2b95a-6079-4bea-9640-0f5dc7f4c181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108608229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1108608229
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3677906402
Short name T148
Test name
Test status
Simulation time 151488456 ps
CPU time 1.12 seconds
Started Jul 14 07:05:58 PM PDT 24
Finished Jul 14 07:05:59 PM PDT 24
Peak memory 200180 kb
Host smart-d3eca489-55c4-42bd-94ca-37e53cce42df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677906402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3677906402
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1653098573
Short name T484
Test name
Test status
Simulation time 195081707 ps
CPU time 1.41 seconds
Started Jul 14 07:05:59 PM PDT 24
Finished Jul 14 07:06:01 PM PDT 24
Peak memory 200312 kb
Host smart-045ab1c6-4162-4cf8-973a-ea3bf71f5820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653098573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1653098573
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.846632945
Short name T136
Test name
Test status
Simulation time 8204800175 ps
CPU time 26.23 seconds
Started Jul 14 07:06:01 PM PDT 24
Finished Jul 14 07:06:28 PM PDT 24
Peak memory 208608 kb
Host smart-4dd05274-aa52-4585-8945-40fc3751d9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846632945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.846632945
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.972719711
Short name T521
Test name
Test status
Simulation time 145819692 ps
CPU time 1.96 seconds
Started Jul 14 07:06:01 PM PDT 24
Finished Jul 14 07:06:04 PM PDT 24
Peak memory 200172 kb
Host smart-eccc81b7-7dec-4be5-b846-e979be7ea11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972719711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.972719711
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3775908612
Short name T190
Test name
Test status
Simulation time 94579921 ps
CPU time 0.82 seconds
Started Jul 14 07:06:00 PM PDT 24
Finished Jul 14 07:06:02 PM PDT 24
Peak memory 200132 kb
Host smart-7d590cb6-e26d-410f-92d8-44a4fe7f2709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775908612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3775908612
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2654421746
Short name T257
Test name
Test status
Simulation time 73370622 ps
CPU time 0.93 seconds
Started Jul 14 07:06:00 PM PDT 24
Finished Jul 14 07:06:02 PM PDT 24
Peak memory 199948 kb
Host smart-41eaab3b-733a-489c-9fc5-365192d8d90e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654421746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2654421746
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.824222087
Short name T385
Test name
Test status
Simulation time 1238500096 ps
CPU time 5.49 seconds
Started Jul 14 07:05:57 PM PDT 24
Finished Jul 14 07:06:03 PM PDT 24
Peak memory 221688 kb
Host smart-1b8fce67-9e4c-4b17-8d94-54983a441c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824222087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.824222087
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3843469425
Short name T183
Test name
Test status
Simulation time 243867588 ps
CPU time 1.03 seconds
Started Jul 14 07:05:58 PM PDT 24
Finished Jul 14 07:06:00 PM PDT 24
Peak memory 217456 kb
Host smart-3427a60d-e761-4704-8b89-b846333074d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843469425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3843469425
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1602583705
Short name T210
Test name
Test status
Simulation time 172654428 ps
CPU time 0.91 seconds
Started Jul 14 07:06:00 PM PDT 24
Finished Jul 14 07:06:02 PM PDT 24
Peak memory 199932 kb
Host smart-8dcbf985-d098-4dbf-85a1-540ceb40a8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602583705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1602583705
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1040330190
Short name T501
Test name
Test status
Simulation time 1703037518 ps
CPU time 7.21 seconds
Started Jul 14 07:05:57 PM PDT 24
Finished Jul 14 07:06:05 PM PDT 24
Peak memory 200368 kb
Host smart-d0e609e7-ed48-4c6e-84ec-45d4f3ddcd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040330190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1040330190
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.100398453
Short name T509
Test name
Test status
Simulation time 180157982 ps
CPU time 1.23 seconds
Started Jul 14 07:05:59 PM PDT 24
Finished Jul 14 07:06:01 PM PDT 24
Peak memory 200156 kb
Host smart-bfb45e5d-f66f-4281-801f-97cef105a08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100398453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.100398453
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.4139728383
Short name T246
Test name
Test status
Simulation time 210162298 ps
CPU time 1.48 seconds
Started Jul 14 07:06:01 PM PDT 24
Finished Jul 14 07:06:03 PM PDT 24
Peak memory 200360 kb
Host smart-76b1266a-8e48-4f11-bef5-3f9d12705e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139728383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.4139728383
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.558679628
Short name T296
Test name
Test status
Simulation time 12879923391 ps
CPU time 44.59 seconds
Started Jul 14 07:05:59 PM PDT 24
Finished Jul 14 07:06:45 PM PDT 24
Peak memory 208612 kb
Host smart-5177c75f-a4a9-41f0-88a9-9a5e21a3350b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558679628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.558679628
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1099148976
Short name T87
Test name
Test status
Simulation time 283330861 ps
CPU time 1.97 seconds
Started Jul 14 07:05:59 PM PDT 24
Finished Jul 14 07:06:02 PM PDT 24
Peak memory 200116 kb
Host smart-5e0a030e-dfc8-458c-871a-3928e8efadde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099148976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1099148976
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3827766938
Short name T196
Test name
Test status
Simulation time 151815372 ps
CPU time 1.05 seconds
Started Jul 14 07:05:58 PM PDT 24
Finished Jul 14 07:06:00 PM PDT 24
Peak memory 200048 kb
Host smart-fe70ba62-3387-42ba-8e03-33f34cf4ba8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827766938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3827766938
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1086503704
Short name T192
Test name
Test status
Simulation time 71896566 ps
CPU time 0.77 seconds
Started Jul 14 07:06:04 PM PDT 24
Finished Jul 14 07:06:06 PM PDT 24
Peak memory 199984 kb
Host smart-d90221bf-ccc4-4df9-bf41-ec5cea28725a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086503704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1086503704
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1269726257
Short name T37
Test name
Test status
Simulation time 1879622830 ps
CPU time 7.09 seconds
Started Jul 14 07:06:05 PM PDT 24
Finished Jul 14 07:06:13 PM PDT 24
Peak memory 217388 kb
Host smart-f42f3002-de9c-4f6e-b62f-53d52fee8b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269726257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1269726257
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3290781215
Short name T249
Test name
Test status
Simulation time 243206977 ps
CPU time 1.07 seconds
Started Jul 14 07:06:07 PM PDT 24
Finished Jul 14 07:06:10 PM PDT 24
Peak memory 217500 kb
Host smart-7b0a9392-a2ae-4bbc-abc9-bb410b8ceac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290781215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3290781215
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3373008683
Short name T22
Test name
Test status
Simulation time 78438941 ps
CPU time 0.73 seconds
Started Jul 14 07:06:06 PM PDT 24
Finished Jul 14 07:06:09 PM PDT 24
Peak memory 199856 kb
Host smart-f0cd9347-a4d2-4ac8-8c59-e76c9372f7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373008683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3373008683
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3243661380
Short name T448
Test name
Test status
Simulation time 819786667 ps
CPU time 3.89 seconds
Started Jul 14 07:06:08 PM PDT 24
Finished Jul 14 07:06:14 PM PDT 24
Peak memory 200408 kb
Host smart-914180ec-3915-4f4e-b5af-4e1716992609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243661380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3243661380
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1424768796
Short name T508
Test name
Test status
Simulation time 167204253 ps
CPU time 1.16 seconds
Started Jul 14 07:06:08 PM PDT 24
Finished Jul 14 07:06:11 PM PDT 24
Peak memory 200132 kb
Host smart-9f5af700-df04-4d1e-afe3-301aa9ea96ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424768796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1424768796
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1211511540
Short name T513
Test name
Test status
Simulation time 121231037 ps
CPU time 1.21 seconds
Started Jul 14 07:06:05 PM PDT 24
Finished Jul 14 07:06:07 PM PDT 24
Peak memory 200336 kb
Host smart-f94a84bf-9749-4cfd-8092-a6aab76402a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211511540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1211511540
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.931022567
Short name T149
Test name
Test status
Simulation time 5129190961 ps
CPU time 18.11 seconds
Started Jul 14 07:06:08 PM PDT 24
Finished Jul 14 07:06:28 PM PDT 24
Peak memory 209504 kb
Host smart-1b0543ca-27fa-4eee-aea6-a11dc00c8d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931022567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.931022567
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.192607975
Short name T147
Test name
Test status
Simulation time 453286995 ps
CPU time 2.33 seconds
Started Jul 14 07:06:05 PM PDT 24
Finished Jul 14 07:06:08 PM PDT 24
Peak memory 200188 kb
Host smart-9e17e066-bdc9-404a-8e62-80e269bd1c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192607975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.192607975
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3662454160
Short name T265
Test name
Test status
Simulation time 218731486 ps
CPU time 1.3 seconds
Started Jul 14 07:06:05 PM PDT 24
Finished Jul 14 07:06:08 PM PDT 24
Peak memory 200344 kb
Host smart-ce87c66d-23c7-4567-934c-2344d0bf0572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662454160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3662454160
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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