Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7963

1

T2

74

T4

17

T5

14

auto[1]

11350

1

T2

103

T4

84

T5

87

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5894	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6570	1			T1	1		T2	66		T3	1
reset_info_cp[2]	3045	1			T2	22		T4	20		T5	18
reset_info_cp[4]	3905	1			T2	43		T4	14		T5	19
reset_info_cp[8]	103	1			T11	1		T45	2		T48	1
reset_info_cp[16]	100	1			T2	1		T12	1		T42	1
reset_info_cp[32]	113	1			T2	1		T5	1		T42	2
reset_info_cp[64]	94	1			T42	1		T33	1		T83	2
reset_info_cp[128]	109	1			T2	1		T4	1		T15	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3070	1			T2	22		T4	17		T5	14
reset_info_cp[1]	auto[1]	2880	1			T2	43		T4	9		T5	12
reset_info_cp[2]	auto[0]	943	1			T2	7		T12	3		T42	26
reset_info_cp[2]	auto[1]	2102	1			T2	15		T4	20		T5	18
reset_info_cp[4]	auto[0]	1414	1			T2	21		T12	6		T42	37
reset_info_cp[4]	auto[1]	2491	1			T2	22		T4	14		T5	19
reset_info_cp[8]	auto[0]	41	1			T45	2		T124	1		T84	1
reset_info_cp[8]	auto[1]	62	1			T11	1		T48	1		T27	1
reset_info_cp[16]	auto[0]	46	1			T42	1		T124	1		T110	2
reset_info_cp[16]	auto[1]	54	1			T2	1		T12	1		T48	1
reset_info_cp[32]	auto[0]	40	1			T45	1		T124	1		T140	1
reset_info_cp[32]	auto[1]	73	1			T2	1		T5	1		T42	2
reset_info_cp[64]	auto[0]	41	1			T42	1		T83	1		T84	1
reset_info_cp[64]	auto[1]	53	1			T33	1		T83	1		T84	1
reset_info_cp[128]	auto[0]	44	1			T2	1		T15	1		T42	1
reset_info_cp[128]	auto[1]	65	1			T4	1		T84	1		T91	1